Use new channel objects
This commit is contained in:
Alex Forencich
@@ -23,36 +23,24 @@ THE SOFTWARE.
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"""
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import cocotb
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from cocotb.triggers import RisingEdge, ReadOnly, Event
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from cocotb.drivers import BusDriver
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from cocotb.triggers import RisingEdge, Event
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from cocotb.log import SimLog
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from collections import deque
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from .constants import *
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from .axi_channels import *
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class AxiMasterWrite(BusDriver):
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_signals = [
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# Write address channel
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"awid", "awaddr", "awlen", "awsize", "awburst", "awprot", "awvalid", "awready",
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# Write data channel
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"wdata", "wstrb", "wlast", "wvalid", "wready",
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# Write response channel
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"bid", "bresp", "bvalid", "bready",
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]
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_optional_signals = [
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# Write address channel
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"awlock", "awcache", "awqos", "awregion", "awuser",
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# Write data channel
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"wuser",
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# Write response channel
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"buser",
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]
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class AxiMasterWrite(object):
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def __init__(self, entity, name, clock, reset=None):
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super().__init__(entity, name, clock)
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self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
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self.reset = reset
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self.aw_channel = AxiAWSource(entity, name, clock, reset)
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self.w_channel = AxiWSource(entity, name, clock, reset)
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self.b_channel = AxiBSink(entity, name, clock, reset)
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self.active_tokens = set()
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@@ -62,80 +50,30 @@ class AxiMasterWrite(BusDriver):
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self.write_resp_sync = Event()
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self.write_resp_set = set()
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self.id_queue = deque(range(2**len(self.bus.awid)))
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self.id_queue = deque(range(2**len(self.aw_channel.bus.awid)))
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self.id_sync = Event()
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self.int_write_addr_queue = deque()
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self.int_write_data_queue = deque()
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self.int_write_resp_command_queue = deque()
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self.int_write_resp_command_sync = Event()
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self.int_write_resp_queue_list = {}
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self.int_write_resp_sync_list = {}
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self.in_flight_operations = 0
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self.width = len(self.bus.wdata)
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self.width = len(self.w_channel.bus.wdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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self.strb_mask = 2**len(self.bus.wstrb)-1
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self.strb_mask = 2**self.byte_width-1
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self.max_burst_len = 256
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self.max_burst_size = (self.byte_width-1).bit_length()
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assert self.byte_width == len(self.bus.wstrb)
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assert self.byte_width == len(self.w_channel.bus.wstrb)
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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self.bus.awid.setimmediatevalue(0)
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self.bus.awaddr.setimmediatevalue(0)
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assert len(self.bus.awlen) == 8
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self.bus.awlen.setimmediatevalue(0)
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assert len(self.bus.awsize) == 3
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self.bus.awsize.setimmediatevalue(0)
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assert len(self.bus.awburst) == 2
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self.bus.awburst.setimmediatevalue(0)
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if hasattr(self.bus, "awlock"):
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assert len(self.bus.awlock) == 1
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self.bus.awlock.setimmediatevalue(0)
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if hasattr(self.bus, "awcache"):
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assert len(self.bus.awcache) == 4
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self.bus.awcache.setimmediatevalue(0)
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assert len(self.bus.awprot) == 3
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self.bus.awprot.setimmediatevalue(0)
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if hasattr(self.bus, "awqos"):
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assert len(self.bus.awqos) == 4
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self.bus.awqos.setimmediatevalue(0)
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if hasattr(self.bus, "awregion"):
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assert len(self.bus.awregion) == 4
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self.bus.awregion.setimmediatevalue(0)
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if hasattr(self.bus, "awuser"):
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self.bus.awuser.setimmediatevalue(0)
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assert len(self.bus.awvalid) == 1
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self.bus.awvalid.setimmediatevalue(0)
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assert len(self.bus.awready) == 1
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self.bus.wdata.setimmediatevalue(0)
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self.bus.wstrb.setimmediatevalue(0)
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assert len(self.bus.wlast) == 1
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self.bus.wlast.setimmediatevalue(0)
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if hasattr(self.bus, "wuser"):
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self.bus.wuser.setimmediatevalue(0)
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assert len(self.bus.wvalid) == 1
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self.bus.wvalid.setimmediatevalue(0)
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assert len(self.bus.wready) == 1
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assert len(self.bus.bid) == len(self.bus.awid)
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assert len(self.bus.bresp) == 2
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assert len(self.bus.bvalid) == 1
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assert len(self.bus.bready) == 1
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self.bus.bready.setimmediatevalue(0)
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assert len(self.b_channel.bus.bid) == len(self.aw_channel.bus.awid)
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cocotb.fork(self._process_write())
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cocotb.fork(self._process_write_resp())
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cocotb.fork(self._process_write_addr_if())
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cocotb.fork(self._process_write_data_if())
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cocotb.fork(self._process_write_resp_if())
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def init_write(self, address, data, burst=AxiBurstType.INCR, size=None, lock=AxiLockType.NORMAL, cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0, token=None):
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if token is not None:
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@@ -257,12 +195,32 @@ class AxiMasterWrite(BusDriver):
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burst_length = (min(burst_length*num_bytes, 0x1000-(cur_addr&0xfff))+num_bytes-1)//num_bytes # 4k align
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burst_list.append((awid, burst_length))
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self.int_write_addr_queue.append((cur_addr, awid, burst_length-1, size, burst, lock, cache, prot, qos, region, user))
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aw = self.aw_channel._transaction_obj()
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aw.awid = awid
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aw.awaddr = cur_addr
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aw.awlen = burst_length-1
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aw.awsize = size
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aw.awburst = burst
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aw.awlock = lock
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aw.awcache = cache
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aw.awprot = prot
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aw.awqos = qos
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aw.awregion = region
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aw.awuser = user
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self.aw_channel.send(aw)
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self.log.info(f"Write burst start awid {awid:#x} awaddr: {cur_addr:#010x} awlen: {burst_length-1} awsize: {size}")
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n += 1
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self.int_write_data_queue.append((val, strb, n >= burst_length, 0))
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w = self.w_channel._transaction_obj()
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w.wdata = val
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w.wstrb = strb
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w.wlast = n >= burst_length
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self.w_channel.send(w)
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cur_addr += num_bytes
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cycle_offset = (cycle_offset + num_bytes) % self.byte_width
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@@ -283,13 +241,20 @@ class AxiMasterWrite(BusDriver):
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for bid, burst_length in burst_list:
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self.int_write_resp_queue_list.setdefault(bid, deque())
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self.int_write_resp_sync_list.setdefault(bid, Event())
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if not self.int_write_resp_queue_list[bid]:
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self.int_write_resp_sync_list[bid].clear()
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await self.int_write_resp_sync_list[bid].wait()
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while True:
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if self.int_write_resp_queue_list[bid]:
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break
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burst_id, burst_resp, burst_user = self.int_write_resp_queue_list[bid].popleft()
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burst_resp = AxiResp(burst_resp)
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await self.b_channel.wait()
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b = self.b_channel.recv()
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self.int_write_resp_queue_list[int(b.bid)].append(b)
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b = self.int_write_resp_queue_list[bid].popleft()
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burst_id = int(b.bid)
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burst_resp = AxiResp(b.bresp)
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burst_user = int(b.buser)
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if burst_resp != AxiResp.OKAY:
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resp = burst_resp
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@@ -312,115 +277,15 @@ class AxiMasterWrite(BusDriver):
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self.write_resp_set.add(token)
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self.in_flight_operations -= 1
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async def _process_write_addr_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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awready_sample = self.bus.awready.value
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awvalid_sample = self.bus.awvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.awvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (awready_sample and awvalid_sample) or (not awvalid_sample):
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if self.int_write_addr_queue:
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addr, awid, length, size, burst, lock, cache, prot, qos, region, user = self.int_write_addr_queue.popleft()
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self.bus.awaddr <= addr
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self.bus.awid <= awid
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self.bus.awlen <= length
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self.bus.awsize <= size
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self.bus.awburst <= burst
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if hasattr(self.bus, "awlock"):
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self.bus.awlock <= lock
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if hasattr(self.bus, "awcache"):
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self.bus.awcache <= cache
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self.bus.awprot <= prot
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if hasattr(self.bus, "awqos"):
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self.bus.awqos <= qos
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if hasattr(self.bus, "awregion"):
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self.bus.awregion <= region
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if hasattr(self.bus, "awuser"):
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self.bus.awuser <= user
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self.bus.awvalid <= 1
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else:
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self.bus.awvalid <= 0
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async def _process_write_data_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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wready_sample = self.bus.wready.value
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wvalid_sample = self.bus.wvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.wvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (wready_sample and wvalid_sample) or (not wvalid_sample):
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if self.int_write_data_queue:
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data, strb, last, user = self.int_write_data_queue.popleft()
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self.bus.wdata <= data
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self.bus.wstrb <= strb
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self.bus.wlast <= last
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if hasattr(self.bus, "awuser"):
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self.bus.awuser <= user
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self.bus.wvalid <= 1
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else:
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self.bus.wvalid <= 0
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async def _process_write_resp_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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bready_sample = self.bus.bready.value
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bvalid_sample = self.bus.bvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.bready <= 0
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continue
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if bready_sample and bvalid_sample:
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bid = self.bus.bid.value.integer
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bresp = self.bus.bresp.value.integer
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buser = self.bus.buser.value.integer if hasattr(self.bus, "buser") else None
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self.int_write_resp_queue_list.setdefault(bid, deque())
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self.int_write_resp_queue_list[bid].append((bid, bresp, buser))
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self.int_write_resp_sync_list.setdefault(bid, Event())
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self.int_write_resp_sync_list[bid].set()
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await RisingEdge(self.clock)
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self.bus.bready <= 1
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class AxiMasterRead(BusDriver):
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_signals = [
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# Read address channel
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"arid", "araddr", "arlen", "arsize", "arburst", "arprot", "arvalid", "arready",
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# Read data channel
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"rid", "rdata", "rresp", "rlast", "rvalid", "rready",
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]
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_optional_signals = [
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# Read address channel
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"arlock", "arcache", "arqos", "arregion", "aruser",
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# Read data channel
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"ruser",
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]
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class AxiMasterRead(object):
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def __init__(self, entity, name, clock, reset=None):
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super().__init__(entity, name, clock)
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self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
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self.reset = reset
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self.ar_channel = AxiARSource(entity, name, clock, reset)
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self.r_channel = AxiRSink(entity, name, clock, reset)
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self.active_tokens = set()
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@@ -430,18 +295,16 @@ class AxiMasterRead(BusDriver):
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self.read_data_sync = Event()
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self.read_data_set = set()
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self.id_queue = deque(range(2**len(self.bus.arid)))
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self.id_queue = deque(range(2**len(self.ar_channel.bus.arid)))
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self.id_sync = Event()
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self.int_read_addr_queue = deque()
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self.int_read_resp_command_queue = deque()
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self.int_read_resp_command_sync = Event()
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self.int_read_resp_queue_list = {}
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self.int_read_resp_sync_list = {}
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self.in_flight_operations = 0
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self.width = len(self.bus.rdata)
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self.width = len(self.r_channel.bus.rdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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@@ -450,47 +313,10 @@ class AxiMasterRead(BusDriver):
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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self.bus.arid.setimmediatevalue(0)
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self.bus.araddr.setimmediatevalue(0)
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assert len(self.bus.arlen) == 8
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self.bus.arlen.setimmediatevalue(0)
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assert len(self.bus.arsize) == 3
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self.bus.arsize.setimmediatevalue(0)
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assert len(self.bus.arburst) == 2
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self.bus.arburst.setimmediatevalue(0)
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if hasattr(self.bus, "arlock"):
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assert len(self.bus.arlock) == 1
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self.bus.arlock.setimmediatevalue(0)
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if hasattr(self.bus, "arcache"):
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assert len(self.bus.arcache) == 4
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self.bus.arcache.setimmediatevalue(0)
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assert len(self.bus.arprot) == 3
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self.bus.arprot.setimmediatevalue(0)
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if hasattr(self.bus, "arqos"):
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assert len(self.bus.arqos) == 4
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self.bus.arqos.setimmediatevalue(0)
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if hasattr(self.bus, "arregion"):
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assert len(self.bus.arregion) == 4
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self.bus.arregion.setimmediatevalue(0)
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if hasattr(self.bus, "aruser"):
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self.bus.aruser.setimmediatevalue(0)
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assert len(self.bus.arvalid) == 1
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self.bus.arvalid.setimmediatevalue(0)
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assert len(self.bus.arready) == 1
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assert len(self.bus.rid) == len(self.bus.arid)
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assert len(self.bus.rresp) == 2
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assert len(self.bus.rlast) == 1
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assert len(self.bus.rvalid) == 1
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assert len(self.bus.rready) == 1
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self.bus.rready.setimmediatevalue(0)
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assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid)
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cocotb.fork(self._process_read())
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cocotb.fork(self._process_read_resp())
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cocotb.fork(self._process_read_addr_if())
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cocotb.fork(self._process_read_resp_if())
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def init_read(self, address, length, burst=AxiBurstType.INCR, size=None, lock=AxiLockType.NORMAL, cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0, token=None):
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if token is not None:
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@@ -591,7 +417,21 @@ class AxiMasterRead(BusDriver):
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burst_length = (min(burst_length*num_bytes, 0x1000-(cur_addr&0xfff))+num_bytes-1)//num_bytes # 4k align
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burst_list.append((arid, burst_length))
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self.int_read_addr_queue.append((cur_addr, arid, burst_length-1, size, burst, lock, cache, prot, qos, region, user))
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ar = self.r_channel._transaction_obj()
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ar.arid = arid
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ar.araddr = cur_addr
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ar.arlen = burst_length-1
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ar.arsize = size
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ar.arburst = burst
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ar.arlock = lock
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ar.arcache = cache
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ar.arprot = prot
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ar.arqos = qos
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ar.arregion = region
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ar.aruser = user
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self.ar_channel.send(ar)
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self.log.info(f"Read burst start arid {arid:#x} araddr: {cur_addr:#010x} arlen: {burst_length-1} arsize: {size}")
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@@ -600,7 +440,6 @@ class AxiMasterRead(BusDriver):
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self.int_read_resp_command_queue.append((address, length, size, cycles, prot, burst_list, token))
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self.int_read_resp_command_sync.set()
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async def _process_read_resp(self):
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while True:
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if not self.int_read_resp_command_queue:
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@@ -628,13 +467,22 @@ class AxiMasterRead(BusDriver):
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for rid, burst_length in burst_list:
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for k in range(burst_length):
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self.int_read_resp_queue_list.setdefault(rid, deque())
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self.int_read_resp_sync_list.setdefault(rid, Event())
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if not self.int_read_resp_queue_list[rid]:
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self.int_read_resp_sync_list[rid].clear()
|
||||
await self.int_read_resp_sync_list[rid].wait()
|
||||
while True:
|
||||
if self.int_read_resp_queue_list[rid]:
|
||||
break
|
||||
|
||||
cycle_id, cycle_data, cycle_resp, cycle_last, cycle_user = self.int_read_resp_queue_list[rid].popleft()
|
||||
cycle_resp = AxiResp(cycle_resp)
|
||||
await self.r_channel.wait()
|
||||
r = self.r_channel.recv()
|
||||
|
||||
self.int_read_resp_queue_list[int(r.rid)].append(r)
|
||||
|
||||
r = self.int_read_resp_queue_list[rid].popleft()
|
||||
|
||||
cycle_id = int(r.rid)
|
||||
cycle_data = int(r.rdata)
|
||||
cycle_resp = AxiResp(r.rresp)
|
||||
cycle_last = int(r.rlast)
|
||||
cycle_user = int(r.ruser)
|
||||
|
||||
if cycle_resp != AxiResp.OKAY:
|
||||
resp = cycle_resp
|
||||
@@ -674,71 +522,6 @@ class AxiMasterRead(BusDriver):
|
||||
self.read_data_set.add(token)
|
||||
self.in_flight_operations -= 1
|
||||
|
||||
async def _process_read_addr_if(self):
|
||||
while True:
|
||||
await ReadOnly()
|
||||
|
||||
# read handshake signals
|
||||
arready_sample = self.bus.arready.value
|
||||
arvalid_sample = self.bus.arvalid.value
|
||||
|
||||
if self.reset is not None and self.reset.value:
|
||||
await RisingEdge(self.clock)
|
||||
self.bus.arvalid <= 0
|
||||
continue
|
||||
|
||||
await RisingEdge(self.clock)
|
||||
|
||||
if (arready_sample and arvalid_sample) or (not arvalid_sample):
|
||||
if self.int_read_addr_queue:
|
||||
addr, arid, length, size, burst, lock, cache, prot, qos, region, user = self.int_read_addr_queue.popleft()
|
||||
self.bus.araddr <= addr
|
||||
self.bus.arid <= arid
|
||||
self.bus.arlen <= length
|
||||
self.bus.arsize <= size
|
||||
self.bus.arburst <= burst
|
||||
if hasattr(self.bus, "arlock"):
|
||||
self.bus.arlock <= lock
|
||||
if hasattr(self.bus, "arcache"):
|
||||
self.bus.arcache <= cache
|
||||
self.bus.arprot <= prot
|
||||
if hasattr(self.bus, "arqos"):
|
||||
self.bus.arqos <= qos
|
||||
if hasattr(self.bus, "arregion"):
|
||||
self.bus.arregion <= region
|
||||
if hasattr(self.bus, "aruser"):
|
||||
self.bus.aruser <= user
|
||||
self.bus.arvalid <= 1
|
||||
else:
|
||||
self.bus.arvalid <= 0
|
||||
|
||||
async def _process_read_resp_if(self):
|
||||
while True:
|
||||
await ReadOnly()
|
||||
|
||||
# read handshake signals
|
||||
rready_sample = self.bus.rready.value
|
||||
rvalid_sample = self.bus.rvalid.value
|
||||
|
||||
if self.reset is not None and self.reset.value:
|
||||
await RisingEdge(self.clock)
|
||||
self.bus.rready <= 0
|
||||
continue
|
||||
|
||||
if rready_sample and rvalid_sample:
|
||||
rid = self.bus.rid.value.integer
|
||||
rdata = self.bus.rdata.value.integer
|
||||
rresp = self.bus.rresp.value.integer
|
||||
rlast = self.bus.rlast.value.integer
|
||||
ruser = self.bus.ruser.value.integer if hasattr(self.bus, "ruser") else None
|
||||
self.int_read_resp_queue_list.setdefault(rid, deque())
|
||||
self.int_read_resp_queue_list[rid].append((rid, rdata, rresp, rlast, ruser))
|
||||
self.int_read_resp_sync_list.setdefault(rid, Event())
|
||||
self.int_read_resp_sync_list[rid].set()
|
||||
|
||||
await RisingEdge(self.clock)
|
||||
self.bus.rready <= 1
|
||||
|
||||
|
||||
class AxiMaster(object):
|
||||
def __init__(self, entity, name, clock, reset=None):
|
||||
@@ -786,3 +569,4 @@ class AxiMaster(object):
|
||||
async def write(self, address, data, burst=AxiBurstType.INCR, size=None, lock=AxiLockType.NORMAL, cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0):
|
||||
return await self.write_if.write(address, data, burst, size, lock, cache, prot, qos, region, user)
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user