Use new channel objects
This commit is contained in:
Alex Forencich
@@ -23,27 +23,24 @@ THE SOFTWARE.
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"""
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import cocotb
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from cocotb.triggers import RisingEdge, ReadOnly, Event
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from cocotb.drivers import BusDriver
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from cocotb.triggers import RisingEdge, Event
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from cocotb.log import SimLog
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from collections import deque
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from .constants import *
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from .axil_channels import *
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class AxiLiteMasterWrite(BusDriver):
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_signals = [
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# Write address channel
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"awaddr", "awprot", "awvalid", "awready",
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# Write data channel
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"wdata", "wstrb", "wvalid", "wready",
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# Write response channel
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"bresp", "bvalid", "bready",
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]
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class AxiLiteMasterWrite(object):
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def __init__(self, entity, name, clock, reset=None):
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super().__init__(entity, name, clock)
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self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
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self.reset = reset
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self.aw_channel = AxiLiteAWSource(entity, name, clock, reset)
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self.w_channel = AxiLiteWSource(entity, name, clock, reset)
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self.b_channel = AxiLiteBSink(entity, name, clock, reset)
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self.active_tokens = set()
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@@ -51,47 +48,20 @@ class AxiLiteMasterWrite(BusDriver):
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self.write_resp_sync = Event()
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self.write_resp_set = set()
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self.int_write_addr_queue = deque()
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self.int_write_data_queue = deque()
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self.int_write_resp_command_queue = deque()
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self.int_write_resp_command_sync = Event()
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self.int_write_resp_queue = deque()
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self.int_write_resp_sync = Event()
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self.in_flight_operations = 0
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self.width = len(self.bus.wdata)
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self.width = len(self.w_channel.bus.wdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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self.strb_mask = 2**len(self.bus.wstrb)-1
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self.strb_mask = 2**self.byte_width-1
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assert self.byte_width == len(self.bus.wstrb)
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assert self.byte_width == len(self.w_channel.bus.wstrb)
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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self.bus.awaddr.setimmediatevalue(0)
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assert len(self.bus.awprot) == 3
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self.bus.awprot.setimmediatevalue(0)
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assert len(self.bus.awvalid) == 1
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self.bus.awvalid.setimmediatevalue(0)
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assert len(self.bus.awready) == 1
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self.bus.wdata.setimmediatevalue(0)
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self.bus.wstrb.setimmediatevalue(0)
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assert len(self.bus.wvalid) == 1
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self.bus.wvalid.setimmediatevalue(0)
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assert len(self.bus.wready) == 1
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assert len(self.bus.bresp) == 2
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assert len(self.bus.bvalid) == 1
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assert len(self.bus.bready) == 1
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self.bus.bready.setimmediatevalue(0)
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cocotb.fork(self._process_write_resp())
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cocotb.fork(self._process_write_addr_if())
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cocotb.fork(self._process_write_data_if())
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cocotb.fork(self._process_write_resp_if())
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def init_write(self, address, data, prot=AxiProt.NONSECURE, token=None):
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if token is not None:
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@@ -135,8 +105,16 @@ class AxiLiteMasterWrite(BusDriver):
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val |= bytearray(data)[offset] << j*8
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offset += 1
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self.int_write_addr_queue.append((word_addr + start + k*self.byte_width, prot))
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self.int_write_data_queue.append((val, strb))
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aw = self.aw_channel._transaction_obj()
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aw.awaddr = word_addr + k*self.byte_width
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aw.awprot = prot
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w = self.w_channel._transaction_obj()
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w.wdata = val
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w.wstrb = strb
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self.aw_channel.send(aw)
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self.w_channel.send(w)
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def idle(self):
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return not self.in_flight_operations
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@@ -193,12 +171,10 @@ class AxiLiteMasterWrite(BusDriver):
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resp = AxiResp.OKAY
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for k in range(cycles):
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if not self.int_write_resp_queue:
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self.int_write_resp_sync.clear()
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await self.int_write_resp_sync.wait()
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await self.b_channel.wait()
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b = self.b_channel.recv()
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cycle_resp = self.int_write_resp_queue.popleft()
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cycle_resp = AxiResp(cycle_resp)
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cycle_resp = AxiResp(b.bresp)
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if cycle_resp != AxiResp.OKAY:
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resp = cycle_resp
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@@ -211,87 +187,15 @@ class AxiLiteMasterWrite(BusDriver):
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self.write_resp_set.add(token)
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self.in_flight_operations -= 1
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async def _process_write_addr_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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awready_sample = self.bus.awready.value
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awvalid_sample = self.bus.awvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.awvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (awready_sample and awvalid_sample) or (not awvalid_sample):
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if self.int_write_addr_queue:
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addr, prot = self.int_write_addr_queue.popleft()
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self.bus.awaddr <= addr
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self.bus.awprot <= prot
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self.bus.awvalid <= 1
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else:
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self.bus.awvalid <= 0
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async def _process_write_data_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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wready_sample = self.bus.wready.value
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wvalid_sample = self.bus.wvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.wvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (wready_sample and wvalid_sample) or (not wvalid_sample):
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if self.int_write_data_queue:
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data, strb = self.int_write_data_queue.popleft()
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self.bus.wdata <= data
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self.bus.wstrb <= strb
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self.bus.wvalid <= 1
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else:
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self.bus.wvalid <= 0
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async def _process_write_resp_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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bready_sample = self.bus.bready.value
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bvalid_sample = self.bus.bvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.bready <= 0
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continue
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if bready_sample and bvalid_sample:
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bresp = self.bus.bresp.value.integer
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self.int_write_resp_queue.append(bresp)
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self.int_write_resp_sync.set()
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await RisingEdge(self.clock)
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self.bus.bready <= 1
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class AxiLiteMasterRead(BusDriver):
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_signals = [
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# Read address channel
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"araddr", "arprot", "arvalid", "arready",
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# Read data channel
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"rdata", "rresp", "rvalid", "rready",
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]
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class AxiLiteMasterRead(object):
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def __init__(self, entity, name, clock, reset=None):
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super().__init__(entity, name, clock)
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self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
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self.reset = reset
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self.ar_channel = AxiLiteARSource(entity, name, clock, reset)
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self.r_channel = AxiLiteRSink(entity, name, clock, reset)
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self.active_tokens = set()
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@@ -299,37 +203,18 @@ class AxiLiteMasterRead(BusDriver):
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self.read_data_sync = Event()
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self.read_data_set = set()
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self.int_read_addr_queue = deque()
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self.int_read_resp_command_queue = deque()
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self.int_read_resp_command_sync = Event()
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self.int_read_resp_queue = deque()
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self.int_read_resp_sync = Event()
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self.in_flight_operations = 0
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self.width = len(self.bus.rdata)
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self.width = len(self.r_channel.bus.rdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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self.bus.araddr.setimmediatevalue(0)
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assert len(self.bus.arprot) == 3
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self.bus.arprot.setimmediatevalue(0)
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assert len(self.bus.arvalid) == 1
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self.bus.arvalid.setimmediatevalue(0)
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assert len(self.bus.arready) == 1
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assert len(self.bus.rresp) == 2
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assert len(self.bus.rvalid) == 1
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assert len(self.bus.rready) == 1
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self.bus.rready.setimmediatevalue(0)
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cocotb.fork(self._process_read_resp())
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cocotb.fork(self._process_read_addr_if())
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cocotb.fork(self._process_read_resp_if())
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def init_read(self, address, length, prot=AxiProt.NONSECURE, token=None):
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if token is not None:
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@@ -349,7 +234,11 @@ class AxiLiteMasterRead(BusDriver):
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self.log.info(f"Read start addr: {address:#010x} prot: {prot} length: {length}")
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for k in range(cycles):
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self.int_read_addr_queue.append((word_addr + k*self.byte_width, prot))
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ar = self.ar_channel._transaction_obj()
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ar.araddr = word_addr + k*self.byte_width
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ar.arprot = prot
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self.ar_channel.send(ar)
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def idle(self):
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return not self.in_flight_operations
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@@ -413,12 +302,11 @@ class AxiLiteMasterRead(BusDriver):
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resp = AxiResp.OKAY
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for k in range(cycles):
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if not self.int_read_resp_queue:
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self.int_read_resp_sync.clear()
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await self.int_read_resp_sync.wait()
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await self.r_channel.wait()
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r = self.r_channel.recv()
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cycle_data, cycle_resp = self.int_read_resp_queue.popleft()
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cycle_resp = AxiResp(cycle_resp)
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cycle_data = int(r.rdata)
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cycle_resp = AxiResp(r.rresp)
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if cycle_resp != AxiResp.OKAY:
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resp = cycle_resp
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@@ -442,52 +330,6 @@ class AxiLiteMasterRead(BusDriver):
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self.read_data_set.add(token)
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self.in_flight_operations -= 1
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async def _process_read_addr_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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arready_sample = self.bus.arready.value
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arvalid_sample = self.bus.arvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.arvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (arready_sample and arvalid_sample) or (not arvalid_sample):
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if self.int_read_addr_queue:
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addr, prot = self.int_read_addr_queue.popleft()
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self.bus.araddr <= addr
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self.bus.arprot <= prot
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self.bus.arvalid <= 1
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else:
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self.bus.arvalid <= 0
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async def _process_read_resp_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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rready_sample = self.bus.rready.value
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rvalid_sample = self.bus.rvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.rready <= 0
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continue
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if rready_sample and rvalid_sample:
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rdata = self.bus.rdata.value.integer
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rresp = self.bus.rresp.value.integer
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self.int_read_resp_queue.append((rdata, rresp))
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self.int_read_resp_sync.set()
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await RisingEdge(self.clock)
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self.bus.rready <= 1
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class AxiLiteMaster(object):
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def __init__(self, entity, name, clock, reset=None):
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