From e5076e700c195aa4e8bf66549ac2ef71b6b82c91 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 26 Nov 2020 21:15:37 -0800 Subject: [PATCH] Log model configuration information --- cocotbext/axi/axi_master.py | 25 +++++++++++++++++++- cocotbext/axi/axi_ram.py | 21 +++++++++++++++- cocotbext/axi/axil_master.py | 17 ++++++++++++- cocotbext/axi/axil_ram.py | 19 ++++++++++++++- cocotbext/axi/axis.py | 46 ++++++++++++++++++++++++++++++++++++ 5 files changed, 124 insertions(+), 4 deletions(-) diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py index ec2a846..8a0cc45 100644 --- a/cocotbext/axi/axi_master.py +++ b/cocotbext/axi/axi_master.py @@ -37,7 +37,7 @@ class AxiMasterWrite(object): def __init__(self, entity, name, clock, reset=None, max_burst_len=256): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) - self.log.info("AXI master model") + self.log.info("AXI master (write)") self.log.info("cocotbext-axi version %s", __version__) self.log.info("Copyright (c) 2020 Alex Forencich") self.log.info("https://github.com/alexforencich/cocotbext-axi") @@ -73,6 +73,15 @@ class AxiMasterWrite(object): self.max_burst_len = max(min(max_burst_len, 256), 1) self.max_burst_size = (self.byte_width-1).bit_length() + self.log.info("AXI master configuration:") + self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) + self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size) + self.log.info(" Max burst length: %d cycles (%d bytes)", + self.max_burst_len, self.max_burst_len*self.byte_width) + assert self.byte_width == len(self.w_channel.bus.wstrb) assert self.byte_width * self.byte_size == self.width @@ -327,6 +336,11 @@ class AxiMasterRead(object): def __init__(self, entity, name, clock, reset=None, max_burst_len=256): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) + self.log.info("AXI master (read)") + self.log.info("cocotbext-axi version %s", __version__) + self.log.info("Copyright (c) 2020 Alex Forencich") + self.log.info("https://github.com/alexforencich/cocotbext-axi") + self.reset = reset self.ar_channel = AxiARSource(entity, name, clock, reset) @@ -356,6 +370,15 @@ class AxiMasterRead(object): self.max_burst_len = max(min(max_burst_len, 256), 1) self.max_burst_size = (self.byte_width-1).bit_length() + self.log.info("AXI master configuration:") + self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) + self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size) + self.log.info(" Max burst length: %d cycles (%d bytes)", + self.max_burst_len, self.max_burst_len*self.byte_width) + assert self.byte_width * self.byte_size == self.width assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid) diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py index d9dfe02..91d13e1 100644 --- a/cocotbext/axi/axi_ram.py +++ b/cocotbext/axi/axi_ram.py @@ -37,7 +37,7 @@ class AxiRamWrite(object): def __init__(self, entity, name, clock, reset=None, size=1024, mem=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) - self.log.info("AXI RAM model") + self.log.info("AXI RAM model (write)") self.log.info("cocotbext-axi version %s", __version__) self.log.info("Copyright (c) 2020 Alex Forencich") self.log.info("https://github.com/alexforencich/cocotbext-axi") @@ -61,6 +61,13 @@ class AxiRamWrite(object): self.byte_width = self.width // self.byte_size self.strb_mask = 2**self.byte_width-1 + self.log.info("AXI RAM model configuration:") + self.log.info(" Memory size: %d bytes", len(self.mem)) + self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) + self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + assert self.byte_width == len(self.w_channel.bus.wstrb) assert self.byte_width * self.byte_size == self.width @@ -160,6 +167,11 @@ class AxiRamRead(object): def __init__(self, entity, name, clock, reset=None, size=1024, mem=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) + self.log.info("AXI RAM model (read)") + self.log.info("cocotbext-axi version %s", __version__) + self.log.info("Copyright (c) 2020 Alex Forencich") + self.log.info("https://github.com/alexforencich/cocotbext-axi") + if type(mem) is mmap.mmap: self.mem = mem else: @@ -177,6 +189,13 @@ class AxiRamRead(object): self.byte_size = 8 self.byte_width = self.width // self.byte_size + self.log.info("AXI RAM model configuration:") + self.log.info(" Memory size: %d bytes", len(self.mem)) + self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) + self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + assert self.byte_width * self.byte_size == self.width assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid) diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py index 10d138f..d24e155 100644 --- a/cocotbext/axi/axil_master.py +++ b/cocotbext/axi/axil_master.py @@ -37,7 +37,7 @@ class AxiLiteMasterWrite(object): def __init__(self, entity, name, clock, reset=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) - self.log.info("AXI lite master model") + self.log.info("AXI lite master (write)") self.log.info("cocotbext-axi version %s", __version__) self.log.info("Copyright (c) 2020 Alex Forencich") self.log.info("https://github.com/alexforencich/cocotbext-axi") @@ -66,6 +66,11 @@ class AxiLiteMasterWrite(object): self.byte_width = self.width // self.byte_size self.strb_mask = 2**self.byte_width-1 + self.log.info("AXI lite master configuration:") + self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + assert self.byte_width == len(self.w_channel.bus.wstrb) assert self.byte_width * self.byte_size == self.width @@ -239,6 +244,11 @@ class AxiLiteMasterRead(object): def __init__(self, entity, name, clock, reset=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) + self.log.info("AXI lite master (read)") + self.log.info("cocotbext-axi version %s", __version__) + self.log.info("Copyright (c) 2020 Alex Forencich") + self.log.info("https://github.com/alexforencich/cocotbext-axi") + self.reset = reset self.ar_channel = AxiLiteARSource(entity, name, clock, reset) @@ -261,6 +271,11 @@ class AxiLiteMasterRead(object): self.byte_size = 8 self.byte_width = self.width // self.byte_size + self.log.info("AXI lite master configuration:") + self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + assert self.byte_width * self.byte_size == self.width cocotb.fork(self._process_read()) diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py index 0455833..c740153 100644 --- a/cocotbext/axi/axil_ram.py +++ b/cocotbext/axi/axil_ram.py @@ -37,7 +37,7 @@ class AxiLiteRamWrite(object): def __init__(self, entity, name, clock, reset=None, size=1024, mem=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) - self.log.info("AXI lite RAM model") + self.log.info("AXI lite RAM model (write)") self.log.info("cocotbext-axi version %s", __version__) self.log.info("Copyright (c) 2020 Alex Forencich") self.log.info("https://github.com/alexforencich/cocotbext-axi") @@ -61,6 +61,12 @@ class AxiLiteRamWrite(object): self.byte_width = self.width // self.byte_size self.strb_mask = 2**self.byte_width-1 + self.log.info("AXI lite RAM model configuration:") + self.log.info(" Memory size: %d bytes", len(self.mem)) + self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + assert self.byte_width == len(self.w_channel.bus.wstrb) assert self.byte_width * self.byte_size == self.width @@ -119,6 +125,11 @@ class AxiLiteRamRead(object): def __init__(self, entity, name, clock, reset=None, size=1024, mem=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) + self.log.info("AXI lite RAM model (read)") + self.log.info("cocotbext-axi version %s", __version__) + self.log.info("Copyright (c) 2020 Alex Forencich") + self.log.info("https://github.com/alexforencich/cocotbext-axi") + self.reset = reset self.ar_channel = AxiLiteARSink(entity, name, clock, reset) @@ -136,6 +147,12 @@ class AxiLiteRamRead(object): self.byte_size = 8 self.byte_width = self.width // self.byte_size + self.log.info("AXI lite RAM model configuration:") + self.log.info(" Memory size: %d bytes", len(self.mem)) + self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + assert self.byte_width * self.byte_size == self.width cocotb.fork(self._process_read()) diff --git a/cocotbext/axi/axis.py b/cocotbext/axi/axis.py index c1b4fcf..e4b8396 100644 --- a/cocotbext/axi/axis.py +++ b/cocotbext/axi/axis.py @@ -261,6 +261,29 @@ class AxiStreamSource(object): self.byte_size = self.width // self.byte_width self.byte_mask = 2**self.byte_size-1 + self.log.info("AXI stream source configuration:") + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" tvalid: %s", "present" if hasattr(self.bus, "tvalid") else "not present") + self.log.info(" tready: %s", "present" if hasattr(self.bus, "tready") else "not present") + self.log.info(" tlast: %s", "present" if hasattr(self.bus, "tlast") else "not present") + if hasattr(self.bus, "tkeep"): + self.log.info(" tkeep width: %d bits", len(self.bus.tkeep)) + else: + self.log.info(" tkeep: not present") + if hasattr(self.bus, "tid"): + self.log.info(" tid width: %d bits", len(self.bus.tid)) + else: + self.log.info(" tid: not present") + if hasattr(self.bus, "tdest"): + self.log.info(" tdest width: %d bits", len(self.bus.tdest)) + else: + self.log.info(" tdest: not present") + if hasattr(self.bus, "tuser"): + self.log.info(" tuser width: %d bits", len(self.bus.tuser)) + else: + self.log.info(" tuser: not present") + cocotb.fork(self._run()) def send(self, frame): @@ -431,6 +454,29 @@ class AxiStreamSink(object): self.byte_size = self.width // self.byte_width self.byte_mask = 2**self.byte_size-1 + self.log.info("AXI stream sink configuration:") + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" tvalid: %s", "present" if hasattr(self.bus, "tvalid") else "not present") + self.log.info(" tready: %s", "present" if hasattr(self.bus, "tready") else "not present") + self.log.info(" tlast: %s", "present" if hasattr(self.bus, "tlast") else "not present") + if hasattr(self.bus, "tkeep"): + self.log.info(" tkeep width: %d bits", len(self.bus.tkeep)) + else: + self.log.info(" tkeep: not present") + if hasattr(self.bus, "tid"): + self.log.info(" tid width: %d bits", len(self.bus.tid)) + else: + self.log.info(" tid: not present") + if hasattr(self.bus, "tdest"): + self.log.info(" tdest width: %d bits", len(self.bus.tdest)) + else: + self.log.info(" tdest: not present") + if hasattr(self.bus, "tuser"): + self.log.info(" tuser width: %d bits", len(self.bus.tuser)) + else: + self.log.info(" tuser: not present") + cocotb.fork(self._run()) def recv(self, compact=True):