diff --git a/tests/axi/Makefile b/tests/axi/Makefile
index 58ae954..30227bb 100644
--- a/tests/axi/Makefile
+++ b/tests/axi/Makefile
@@ -24,7 +24,7 @@ SIM ?= icarus
 WAVES ?= 0
 
 COCOTB_HDL_TIMEUNIT = 1ns
-COCOTB_HDL_TIMEPRECISION = 1ps
+COCOTB_HDL_TIMEPRECISION = 1ns
 
 DUT      = test_axi
 TOPLEVEL = $(DUT)
diff --git a/tests/axi/test_axi.py b/tests/axi/test_axi.py
index d288bdd..e0a74ec 100644
--- a/tests/axi/test_axi.py
+++ b/tests/axi/test_axi.py
@@ -41,7 +41,7 @@ class TB(object):
     def __init__(self, dut):
         self.dut = dut
 
-        cocotb.fork(Clock(dut.clk, 10, units="ns").start())
+        cocotb.fork(Clock(dut.clk, 2, units="ns").start())
 
         self.axi_master = AxiMaster(dut, "axi", dut.clk, dut.rst)
         self.axi_ram = AxiRam(dut, "axi", dut.clk, dut.rst, size=2**16)
diff --git a/tests/axi/test_axi.v b/tests/axi/test_axi.v
index 5272698..db1b66a 100644
--- a/tests/axi/test_axi.v
+++ b/tests/axi/test_axi.v
@@ -24,7 +24,7 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 
 /*
  * AXI4 test module
diff --git a/tests/axil/Makefile b/tests/axil/Makefile
index 62a3090..e201784 100644
--- a/tests/axil/Makefile
+++ b/tests/axil/Makefile
@@ -24,7 +24,7 @@ SIM ?= icarus
 WAVES ?= 0
 
 COCOTB_HDL_TIMEUNIT = 1ns
-COCOTB_HDL_TIMEPRECISION = 1ps
+COCOTB_HDL_TIMEPRECISION = 1ns
 
 DUT      = test_axil
 TOPLEVEL = $(DUT)
diff --git a/tests/axil/test_axil.py b/tests/axil/test_axil.py
index 959e57d..4d1e87d 100644
--- a/tests/axil/test_axil.py
+++ b/tests/axil/test_axil.py
@@ -40,7 +40,7 @@ class TB(object):
     def __init__(self, dut):
         self.dut = dut
 
-        cocotb.fork(Clock(dut.clk, 10, units="ns").start())
+        cocotb.fork(Clock(dut.clk, 2, units="ns").start())
 
         self.axil_master = AxiLiteMaster(dut, "axil", dut.clk, dut.rst)
         self.axil_ram = AxiLiteRam(dut, "axil", dut.clk, dut.rst, size=2**16)
diff --git a/tests/axil/test_axil.v b/tests/axil/test_axil.v
index 72ad2c6..7dab0c1 100644
--- a/tests/axil/test_axil.v
+++ b/tests/axil/test_axil.v
@@ -24,7 +24,7 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 
 /*
  * AXI lite test module
diff --git a/tests/axis/Makefile b/tests/axis/Makefile
index a35c689..ad73a06 100644
--- a/tests/axis/Makefile
+++ b/tests/axis/Makefile
@@ -24,7 +24,7 @@ SIM ?= icarus
 WAVES ?= 0
 
 COCOTB_HDL_TIMEUNIT = 1ns
-COCOTB_HDL_TIMEPRECISION = 1ps
+COCOTB_HDL_TIMEPRECISION = 1ns
 
 DUT      = test_axis
 TOPLEVEL = $(DUT)
diff --git a/tests/axis/test_axis.py b/tests/axis/test_axis.py
index 2515cae..7b32851 100644
--- a/tests/axis/test_axis.py
+++ b/tests/axis/test_axis.py
@@ -40,7 +40,7 @@ class TB(object):
     def __init__(self, dut):
         self.dut = dut
 
-        cocotb.fork(Clock(dut.clk, 10, units="ns").start())
+        cocotb.fork(Clock(dut.clk, 2, units="ns").start())
 
         self.source = AxiStreamSource(dut, "axis", dut.clk, dut.rst)
         self.sink = AxiStreamSink(dut, "axis", dut.clk, dut.rst)
diff --git a/tests/axis/test_axis.v b/tests/axis/test_axis.v
index d50d112..345a411 100644
--- a/tests/axis/test_axis.v
+++ b/tests/axis/test_axis.v
@@ -24,7 +24,7 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 
 /*
  * AXI4-Stream test