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Change timescale to speed up verilator

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Alex Forencich
2020-11-15 13:09:53 -08:00
parent f258ce0f6a
commit f1648ccf78
9 changed files with 9 additions and 9 deletions
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tests/axil/Makefile
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@@ -24,7 +24,7 @@ SIM ?= icarus
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
COCOTB_HDL_TIMEPRECISION = 1ns
DUT = test_axil
TOPLEVEL = $(DUT)