Change timescale to speed up verilator

tests/axis/Makefile

@@ -24,7 +24,7 @@ SIM ?= icarus
 WAVES ?= 0
 
 COCOTB_HDL_TIMEUNIT = 1ns
-COCOTB_HDL_TIMEPRECISION = 1ps
+COCOTB_HDL_TIMEPRECISION = 1ns
 
 DUT      = test_axis
 TOPLEVEL = $(DUT)

tests/axis/test_axis.py

@@ -40,7 +40,7 @@ class TB(object):
     def __init__(self, dut):
         self.dut = dut
 
-        cocotb.fork(Clock(dut.clk, 10, units="ns").start())
+        cocotb.fork(Clock(dut.clk, 2, units="ns").start())
 
         self.source = AxiStreamSource(dut, "axis", dut.clk, dut.rst)
         self.sink = AxiStreamSink(dut, "axis", dut.clk, dut.rst)

tests/axis/test_axis.v

@@ -24,7 +24,7 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 
 /*
  * AXI4-Stream test