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Dump FST traces with Verilator

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Alex Forencich
2020-11-18 00:34:41 -08:00
parent ca57cdb198
commit f2995d716e
3 changed files with 3 additions and 6 deletions
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3
tests/axil/Makefile
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@@ -57,8 +57,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace
#COMPILE_ARGS += --trace-fst
COMPILE_ARGS += --trace-fst
endif
endif