30 Commits

Author SHA1 Message Date
Alex Forencich
f3a7652362 Release v0.1.20
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-25 17:55:54 -08:00
Alex Forencich
a84ce5447d Put sinks to sleep when idle
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-25 17:46:46 -08:00
Alex Forencich
1c03ec4697 Pass through full address for unaligned operations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-25 16:27:14 -08:00
Alex Forencich
824eba793d Update package versions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-24 12:47:15 -08:00
Alex Forencich
a0aad34698 Fix path issue so latest coverage works
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-20 20:57:30 -08:00
Alex Forencich
ede6270ed7 Put source to sleep when there is no data to send
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-20 15:49:16 -08:00
Alex Forencich
cd1a8b47a5 Fix init sequence
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-20 15:48:46 -08:00
Alex Forencich
be6d490adb Cache signal presence
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-20 15:48:23 -08:00
Alex Forencich
39686b849a Update github actions versions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-20 15:30:32 -08:00
Alex Forencich
706051cb89 Fix tox config and lock package versions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-20 15:29:11 -08:00
Alex Forencich
3e4f8d7e92 Python 3.6 is EOL; remove from CI tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-18 14:55:25 -08:00
Leon Woestenberg
afae9e69ff Fix AxiStreamFrame default for self.byte_lanes from 1 to all.
If I connect a AXIS source to an AXIS sink, the #byte_lanes is incorrectly 1 rather than all lanes enabled.
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "sink"), dut.clk, dut.reset)

Root cause is AxiStreamFrame assumes byte width 1 without TKEEP, but it should default to self.width // 8
because the AXIS specification mentions "when TKEEP is absent, TKEEP defaults to all bits HIGH" and "The width of the data payload is an integer number of bytes."

Fix: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axis.py#L290

self.byte_lanes = 1
self.byte_lanes = self.width // 8

Relevant AXIS Specification:
https://developer.arm.com/documentation/ihi0051/a/Default-Signaling-Requirements/Default-value-signaling/Optional-TKEEP-and-TSTRB?lang=en

Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
2023-01-18 12:55:19 -08:00
Alex Forencich
035c1ba803 Support interleaved read data in AXI master 2022-02-01 00:25:01 -08:00
Alex Forencich
873bb1a034 Explicit cast to integer before converting to enum or flag type 2022-01-07 12:52:41 -08:00
Alex Forencich
2d70e5cbe5 Fix AxiLiteSlave wrapper 2022-01-04 15:29:04 -08:00
Alex Forencich
35d9742ae8 Remove extraneous code 2022-01-04 15:28:48 -08:00
Alex Forencich
0f20e2e9bf Bump to dev version 2021-12-28 20:08:44 -08:00
Alex Forencich
7606d7d7bd Release v0.1.18 2021-12-28 17:23:06 -08:00
Alex Forencich
dd345e87c3 Call write from init_write via start_soon so command FIFO size can be limited 2021-12-27 23:29:29 -08:00
Alex Forencich
9c0592c16a Make wstrb optional 2021-12-27 19:44:30 -08:00
Alex Forencich
8aab5a7294 Support overriding allocated region and window types 2021-12-27 17:58:52 -08:00
Alex Forencich
4f26621e2b Make size optional when creating windows 2021-12-27 17:31:08 -08:00
Alex Forencich
1b6993d80d Use start_soon instead of fork 2021-12-27 17:10:37 -08:00
Alex Forencich
6d9ed8a2d2 Specify min package versions 2021-12-27 17:03:19 -08:00
Alex Forencich
d772b73eb2 Specify min tox and venv versions 2021-12-27 17:02:59 -08:00
Alex Forencich
bd88eda17b Skip missing interpreters 2021-12-27 17:02:39 -08:00
Alex Forencich
53313699a9 Test on Python 3.10 2021-12-27 17:00:44 -08:00
Alex Forencich
3f7193b77c Use start_soon instead of fork 2021-12-08 21:38:12 -08:00
Alex Forencich
2b0b12c68d Cache clock edge event objects 2021-12-03 18:40:04 -08:00
Alex Forencich
4a91212f37 Bump to dev version 2021-11-17 00:06:34 -08:00
16 changed files with 516 additions and 166 deletions

View File

@@ -9,13 +9,13 @@ jobs:
strategy:
matrix:
python-version: [3.6, 3.7, 3.8, 3.9]
python-version: ["3.7", "3.8", "3.9", "3.10"]
steps:
- uses: actions/checkout@v1
- uses: actions/checkout@v3
- name: Set up Python ${{ matrix.python-version }}
uses: actions/setup-python@v2
uses: actions/setup-python@v4
with:
python-version: ${{ matrix.python-version }}

View File

@@ -33,6 +33,8 @@ class MemoryInterface:
self._parent = parent
self._size = size
self._base = base
self.window_type = Window
self.window_pool_type = WindowPool
super().__init__(**kwargs)
@property
@@ -125,17 +127,22 @@ class MemoryInterface:
async def write_qword(self, address, data, byteorder='little', **kwargs):
await self.write_qwords(address, [data], byteorder, **kwargs)
def create_window(self, offset, size):
def create_window(self, offset, size=None, window_type=None):
if not size or size < 0:
size = self.size - offset
window_type = window_type or self.window_type or Window
self.check_range(offset, size)
return Window(self, offset, size, base=self.get_absolute_address(offset))
return window_type(self, offset, size, base=self.get_absolute_address(offset))
def create_window_pool(self, offset=None, size=None):
def create_window_pool(self, offset=None, size=None, window_pool_type=None, window_type=None):
if offset is None:
offset = 0
if size is None:
size = self.size - offset
window_pool_type = window_pool_type or self.window_pool_type or WindowPool
window_type = window_type or self.window_type
self.check_range(offset, size)
return WindowPool(self, offset, size, base=self.get_absolute_address(offset))
return window_pool_type(self, offset, size, base=self.get_absolute_address(offset), window_type=window_type)
def __len__(self):
return self._size
@@ -163,12 +170,13 @@ class Window(MemoryInterface):
class WindowPool(Window):
def __init__(self, parent, offset, size, base=None, **kwargs):
def __init__(self, parent, offset, size, base=None, window_type=None, **kwargs):
super().__init__(parent, offset, size, base=base, **kwargs)
self.window_type = window_type or Window
self.allocator = BuddyAllocator(size)
def alloc_window(self, size):
return self.create_window(self.allocator.alloc(size), size)
def alloc_window(self, size, window_type=None):
return self.create_window(self.allocator.alloc(size), size, window_type)
class Region(MemoryInterface):
@@ -229,6 +237,7 @@ class PeripheralRegion(Region):
class AddressSpace(Region):
def __init__(self, size=2**64, base=0, parent=None, **kwargs):
super().__init__(size=size, base=base, parent=parent, **kwargs)
self.pool_type = Pool
self.regions = []
def find_regions(self, address, length=1):
@@ -297,24 +306,27 @@ class AddressSpace(Region):
if length > 0:
raise Exception("Invalid address")
def create_pool(self, base=None, size=None):
def create_pool(self, base=None, size=None, pool_type=None, region_type=None):
if base is None:
base = 0
if size is None:
size = self.size - base
pool_type = pool_type or self.pool_type or Pool
self.check_range(base, size)
pool = Pool(self, base, size)
pool = pool_type(self, base, size, region_type=region_type)
self.register_region(pool, base, size)
return pool
class Pool(AddressSpace):
def __init__(self, parent, base, size, **kwargs):
def __init__(self, parent, base, size, region_type=None, **kwargs):
super().__init__(parent=parent, base=base, size=size, **kwargs)
self.region_type = region_type or MemoryRegion
self.allocator = BuddyAllocator(size)
def alloc_region(self, size):
def alloc_region(self, size, region_type=None):
region_type = region_type or self.region_type or MemoryRegion
base = self.allocator.alloc(size)
region = MemoryRegion(size)
region = region_type(size)
self.register_region(region, base)
return region

View File

@@ -34,8 +34,8 @@ AxiAWBus, AxiAWTransaction, AxiAWSource, AxiAWSink, AxiAWMonitor = define_stream
# Write data channel
AxiWBus, AxiWTransaction, AxiWSource, AxiWSink, AxiWMonitor = define_stream("AxiW",
signals=["wdata", "wstrb", "wlast", "wvalid", "wready"],
optional_signals=["wuser"],
signals=["wdata", "wlast", "wvalid", "wready"],
optional_signals=["wstrb", "wuser"],
signal_widths={"wlast": 1}
)

View File

@@ -124,7 +124,7 @@ class TagContext:
def _start(self):
if self._cr is None:
self._cr = cocotb.fork(self._process_queue())
self._cr = cocotb.start_soon(self._process_queue())
def _flush(self):
flushed_cmds = []
@@ -213,6 +213,7 @@ class AxiMasterWrite(Region, Reset):
self.b_channel.queue_occupancy_limit = 2
self.write_command_queue = Queue()
self.write_command_queue.queue_occupancy_limit = 2
self.current_write_command = None
self.id_count = 2**len(self.aw_channel.bus.awid)
@@ -241,6 +242,7 @@ class AxiMasterWrite(Region, Reset):
self.awqos_present = hasattr(self.bus.aw, "awqos")
self.awregion_present = hasattr(self.bus.aw, "awregion")
self.awuser_present = hasattr(self.bus.aw, "awuser")
self.wstrb_present = hasattr(self.bus.w, "wstrb")
self.wuser_present = hasattr(self.bus.w, "wuser")
self.buser_present = hasattr(self.bus.b, "buser")
@@ -263,6 +265,7 @@ class AxiMasterWrite(Region, Reset):
else:
self.log.info(" %s: not present", sig)
if self.wstrb_present:
assert self.byte_lanes == len(self.w_channel.bus.wstrb)
assert self.byte_lanes * self.byte_size == self.width
@@ -331,12 +334,10 @@ class AxiMasterWrite(Region, Reset):
else:
wuser = list(wuser)
self.in_flight_operations += 1
self._idle.clear()
data = bytes(data)
cmd = AxiWriteCmd(address, bytes(data), awid, burst, size, lock,
cache, prot, qos, region, user, wuser, event)
self.write_command_queue.put_nowait(cmd)
cocotb.start_soon(self._write_wrapper(address, data, awid, burst, size,
lock, cache, prot, qos, region, user, wuser, event))
return event
@@ -349,10 +350,74 @@ class AxiMasterWrite(Region, Reset):
async def write(self, address, data, awid=None, burst=AxiBurstType.INCR, size=None,
lock=AxiLockType.NORMAL, cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0, wuser=0):
event = self.init_write(address, data, awid, burst, size, lock, cache, prot, qos, region, user, wuser)
if address < 0 or address >= 2**self.address_width:
raise ValueError("Address out of range")
if isinstance(data, int):
raise ValueError("Expected bytes or bytearray for data")
if awid is None or awid < 0:
awid = None
elif awid > self.id_count:
raise ValueError("Requested ID exceeds maximum ID allowed for ID signal width")
burst = AxiBurstType(burst)
if size is None or size < 0:
size = self.max_burst_size
elif size > self.max_burst_size:
raise ValueError("Requested burst size exceeds maximum burst size allowed for bus width")
lock = AxiLockType(lock)
prot = AxiProt(prot)
if not self.awlock_present and lock != AxiLockType.NORMAL:
raise ValueError("awlock sideband signal value specified, but signal is not connected")
if not self.awcache_present and cache != 0b0011:
raise ValueError("awcache sideband signal value specified, but signal is not connected")
if not self.awprot_present and prot != AxiProt.NONSECURE:
raise ValueError("awprot sideband signal value specified, but signal is not connected")
if not self.awqos_present and qos != 0:
raise ValueError("awqos sideband signal value specified, but signal is not connected")
if not self.awregion_present and region != 0:
raise ValueError("awregion sideband signal value specified, but signal is not connected")
if not self.awuser_present and user != 0:
raise ValueError("awuser sideband signal value specified, but signal is not connected")
if not self.wuser_present and wuser != 0:
raise ValueError("wuser sideband signal value specified, but signal is not connected")
if wuser is None:
wuser = 0
elif isinstance(wuser, int):
pass
else:
wuser = list(wuser)
event = Event()
data = bytes(data)
self.in_flight_operations += 1
self._idle.clear()
cmd = AxiWriteCmd(address, data, awid, burst, size, lock,
cache, prot, qos, region, user, wuser, event)
await self.write_command_queue.put(cmd)
await event.wait()
return event.data
async def _write_wrapper(self, address, data, awid, burst, size,
lock, cache, prot, qos, region, user, wuser, event):
event.set(await self.write(address, data, awid, burst, size,
lock, cache, prot, qos, region, user, wuser))
def _handle_reset(self, state):
if state:
self.log.info("Reset asserted")
@@ -392,9 +457,9 @@ class AxiMasterWrite(Region, Reset):
else:
self.log.info("Reset de-asserted")
if self._process_write_cr is None:
self._process_write_cr = cocotb.fork(self._process_write())
self._process_write_cr = cocotb.start_soon(self._process_write())
if self._process_write_resp_cr is None:
self._process_write_resp_cr = cocotb.fork(self._process_write_resp())
self._process_write_resp_cr = cocotb.start_soon(self._process_write_resp())
async def _process_write(self):
while True:
@@ -411,7 +476,7 @@ class AxiMasterWrite(Region, Reset):
cycles = (len(cmd.data) + (cmd.address % num_bytes) + num_bytes-1) // num_bytes
cur_addr = aligned_addr
cur_addr = cmd.address
offset = 0
cycle_offset = aligned_addr-word_addr
n = 0
@@ -480,6 +545,9 @@ class AxiMasterWrite(Region, Reset):
n += 1
if not self.wstrb_present and strb != self.strb_mask:
self.log.warning("Partial operation requested with wstrb not connected, write will be zero-padded (0x%x != 0x%x)", strb, self.strb_mask)
w = self.w_channel._transaction_obj()
w.wdata = val
w.wstrb = strb
@@ -495,6 +563,9 @@ class AxiMasterWrite(Region, Reset):
await self.w_channel.send(w)
if k == 0:
cur_addr = aligned_addr + num_bytes
else:
cur_addr += num_bytes
cycle_offset = (cycle_offset + num_bytes) % self.byte_lanes
@@ -509,8 +580,7 @@ class AxiMasterWrite(Region, Reset):
bid = int(getattr(b, 'bid', 0))
if self.active_id[bid] <= 0:
raise Exception(f"Unexpected burst ID {bid}")
assert self.active_id[bid] > 0, "unexpected burst ID"
self.tag_context_manager.put_resp(bid, b)
@@ -523,7 +593,7 @@ class AxiMasterWrite(Region, Reset):
for burst_length in cmd.burst_list:
b = await context.get_resp()
burst_resp = AxiResp(getattr(b, 'bresp', AxiResp.OKAY))
burst_resp = AxiResp(int(getattr(b, 'bresp', AxiResp.OKAY)))
burst_user = int(getattr(b, 'buser', 0))
if burst_resp != AxiResp.OKAY:
@@ -532,8 +602,7 @@ class AxiMasterWrite(Region, Reset):
if burst_user is not None:
user.append(burst_user)
if self.active_id[bid] <= 0:
raise Exception(f"Unexpected burst ID {bid}")
assert self.active_id[bid] > 0, "unexpected burst ID"
self.active_id[bid] -= 1
@@ -573,6 +642,7 @@ class AxiMasterRead(Region, Reset):
self.r_channel.queue_occupancy_limit = 2
self.read_command_queue = Queue()
self.read_command_queue.queue_occupancy_limit = 2
self.current_read_command = None
self.id_count = 2**len(self.ar_channel.bus.arid)
@@ -678,11 +748,8 @@ class AxiMasterRead(Region, Reset):
if not self.aruser_present and user != 0:
raise ValueError("aruser sideband signal value specified, but signal is not connected")
self.in_flight_operations += 1
self._idle.clear()
cmd = AxiReadCmd(address, length, arid, burst, size, lock, cache, prot, qos, region, user, event)
self.read_command_queue.put_nowait(cmd)
cocotb.start_soon(self._read_wrapper(address, length, arid, burst, size,
lock, cache, prot, qos, region, user, event))
return event
@@ -695,10 +762,62 @@ class AxiMasterRead(Region, Reset):
async def read(self, address, length, arid=None, burst=AxiBurstType.INCR, size=None,
lock=AxiLockType.NORMAL, cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0):
event = self.init_read(address, length, arid, burst, size, lock, cache, prot, qos, region, user)
if address < 0 or address >= 2**self.address_width:
raise ValueError("Address out of range")
if length < 0:
raise ValueError("Read length must be positive")
if arid is None or arid < 0:
arid = None
elif arid > self.id_count:
raise ValueError("Requested ID exceeds maximum ID allowed for ID signal width")
burst = AxiBurstType(burst)
if size is None or size < 0:
size = self.max_burst_size
elif size > self.max_burst_size:
raise ValueError("Requested burst size exceeds maximum burst size allowed for bus width")
lock = AxiLockType(lock)
prot = AxiProt(prot)
if not self.arlock_present and lock != AxiLockType.NORMAL:
raise ValueError("arlock sideband signal value specified, but signal is not connected")
if not self.arcache_present and cache != 0b0011:
raise ValueError("arcache sideband signal value specified, but signal is not connected")
if not self.arprot_present and prot != AxiProt.NONSECURE:
raise ValueError("arprot sideband signal value specified, but signal is not connected")
if not self.arqos_present and qos != 0:
raise ValueError("arqos sideband signal value specified, but signal is not connected")
if not self.arregion_present and region != 0:
raise ValueError("arregion sideband signal value specified, but signal is not connected")
if not self.aruser_present and user != 0:
raise ValueError("aruser sideband signal value specified, but signal is not connected")
event = Event()
self.in_flight_operations += 1
self._idle.clear()
cmd = AxiReadCmd(address, length, arid, burst, size, lock, cache, prot, qos, region, user, event)
await self.read_command_queue.put(cmd)
await event.wait()
return event.data
async def _read_wrapper(self, address, length, arid, burst, size,
lock, cache, prot, qos, region, user, event):
event.set(await self.read(address, length, arid, burst, size,
lock, cache, prot, qos, region, user))
def _handle_reset(self, state):
if state:
self.log.info("Reset asserted")
@@ -737,9 +856,9 @@ class AxiMasterRead(Region, Reset):
else:
self.log.info("Reset de-asserted")
if self._process_read_cr is None:
self._process_read_cr = cocotb.fork(self._process_read())
self._process_read_cr = cocotb.start_soon(self._process_read())
if self._process_read_resp_cr is None:
self._process_read_resp_cr = cocotb.fork(self._process_read_resp())
self._process_read_resp_cr = cocotb.start_soon(self._process_read_resp())
async def _process_read(self):
while True:
@@ -754,7 +873,7 @@ class AxiMasterRead(Region, Reset):
burst_list = []
cur_addr = aligned_addr
cur_addr = cmd.address
n = 0
burst_length = 0
@@ -799,6 +918,9 @@ class AxiMasterRead(Region, Reset):
self.log.info("Read burst start arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d arprot: %s",
arid, cur_addr, burst_length-1, cmd.size, cmd.prot)
if k == 0:
cur_addr = aligned_addr + num_bytes
else:
cur_addr += num_bytes
resp_cmd = AxiReadRespCmd(cmd.address, cmd.length, cmd.size, cycles, cmd.prot, burst_list, cmd.event)
@@ -807,27 +929,14 @@ class AxiMasterRead(Region, Reset):
self.current_read_command = None
async def _process_read_resp(self):
burst = []
cur_rid = None
while True:
r = await self.r_channel.recv()
rid = int(getattr(r, 'rid', 0))
if cur_rid is not None and cur_rid != rid:
raise Exception(f"ID not constant within burst (expected {cur_rid}, got {rid})")
assert self.active_id[rid] > 0, "unexpected burst ID"
if self.active_id[rid] <= 0:
raise Exception(f"Unexpected burst ID {rid}")
burst.append(r)
cur_rid = rid
if int(r.rlast):
self.tag_context_manager.put_resp(rid, burst)
burst = []
cur_rid = None
self.tag_context_manager.put_resp(rid, r)
async def _process_read_resp_id(self, context, cmd):
rid = context.current_tag
@@ -848,14 +957,18 @@ class AxiMasterRead(Region, Reset):
first = True
for burst_length in cmd.burst_list:
burst = await context.get_resp()
for k in range(burst_length):
r = await context.get_resp()
if len(burst) != burst_length:
raise Exception(f"Burst length incorrect (ID {rid}, expected {burst_length}, got {len(burst)}")
assert self.active_id[rid] > 0, "unexpected burst ID"
if k == burst_length-1:
assert int(r.rlast), "missing rlast at end of burst"
else:
assert not int(r.rlast), "unexpected rlast within burst"
for r in burst:
cycle_data = int(r.rdata)
cycle_resp = AxiResp(getattr(r, "rresp", AxiResp.OKAY))
cycle_resp = AxiResp(int(getattr(r, "rresp", AxiResp.OKAY)))
cycle_user = int(getattr(r, "ruser", 0))
if cycle_resp != AxiResp.OKAY:

View File

@@ -63,6 +63,8 @@ class AxiSlaveWrite(Reset):
self.max_burst_size = (self.byte_lanes-1).bit_length()
self.wstrb_present = hasattr(self.bus.w, "wstrb")
self.log.info("AXI slave model configuration:")
self.log.info(" Address width: %d bits", self.address_width)
self.log.info(" ID width: %d bits", self.id_width)
@@ -77,6 +79,7 @@ class AxiSlaveWrite(Reset):
else:
self.log.info(" %s: not present", sig)
if self.wstrb_present:
assert self.byte_lanes == len(self.w_channel.bus.wstrb)
assert self.byte_lanes * self.byte_size == self.width
@@ -102,7 +105,7 @@ class AxiSlaveWrite(Reset):
else:
self.log.info("Reset de-asserted")
if self._process_write_cr is None:
self._process_write_cr = cocotb.fork(self._process_write())
self._process_write_cr = cocotb.start_soon(self._process_write())
async def _process_write(self):
while True:
@@ -112,8 +115,8 @@ class AxiSlaveWrite(Reset):
addr = int(aw.awaddr)
length = int(getattr(aw, 'awlen', 0))
size = int(getattr(aw, 'awsize', self.max_burst_size))
burst = AxiBurstType(getattr(aw, 'awburst', AxiBurstType.INCR))
prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE))
burst = AxiBurstType(int(getattr(aw, 'awburst', AxiBurstType.INCR)))
prot = AxiProt(int(getattr(aw, 'awprot', AxiProt.NONSECURE)))
self.log.info("Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d awprot: %s",
awid, addr, length, size, prot)
@@ -146,7 +149,10 @@ class AxiSlaveWrite(Reset):
w = await self.w_channel.recv()
data = int(w.wdata)
if self.wstrb_present:
strb = int(getattr(w, 'wstrb', self.strb_mask))
else:
strb = self.strb_mask
last = int(w.wlast)
# generate operation list
@@ -259,7 +265,7 @@ class AxiSlaveRead(Reset):
else:
self.log.info("Reset de-asserted")
if self._process_read_cr is None:
self._process_read_cr = cocotb.fork(self._process_read())
self._process_read_cr = cocotb.start_soon(self._process_read())
async def _process_read(self):
while True:
@@ -269,8 +275,8 @@ class AxiSlaveRead(Reset):
addr = int(ar.araddr)
length = int(getattr(ar, 'arlen', 0))
size = int(getattr(ar, 'arsize', self.max_burst_size))
burst = AxiBurstType(getattr(ar, 'arburst', AxiBurstType.INCR))
prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE))
burst = AxiBurstType(int(getattr(ar, 'arburst', AxiBurstType.INCR)))
prot = AxiProt(int(getattr(ar, 'arprot', AxiProt.NONSECURE)))
self.log.info("Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d arprot: %s",
arid, addr, length, size, prot)

View File

@@ -33,7 +33,8 @@ AxiLiteAWBus, AxiLiteAWTransaction, AxiLiteAWSource, AxiLiteAWSink, AxiLiteAWMon
# Write data channel
AxiLiteWBus, AxiLiteWTransaction, AxiLiteWSource, AxiLiteWSink, AxiLiteWMonitor = define_stream("AxiLiteW",
signals=["wdata", "wstrb", "wvalid", "wready"]
signals=["wdata", "wvalid", "wready"],
optional_signals=["wstrb"]
)
# Write response channel

View File

@@ -103,6 +103,7 @@ class AxiLiteMasterWrite(Region, Reset):
self.b_channel.queue_occupancy_limit = 2
self.write_command_queue = Queue()
self.write_command_queue.queue_occupancy_limit = 2
self.current_write_command = None
self.int_write_resp_command_queue = Queue()
@@ -119,6 +120,7 @@ class AxiLiteMasterWrite(Region, Reset):
self.strb_mask = 2**self.byte_lanes-1
self.awprot_present = hasattr(self.bus.aw, "awprot")
self.wstrb_present = hasattr(self.bus.w, "wstrb")
super().__init__(2**self.address_width, **kwargs)
@@ -135,6 +137,7 @@ class AxiLiteMasterWrite(Region, Reset):
else:
self.log.info(" %s: not present", sig)
if self.wstrb_present:
assert self.byte_lanes == len(self.w_channel.bus.wstrb)
assert self.byte_lanes * self.byte_size == self.width
@@ -159,10 +162,9 @@ class AxiLiteMasterWrite(Region, Reset):
if not self.awprot_present and prot != AxiProt.NONSECURE:
raise ValueError("awprot sideband signal value specified, but signal is not connected")
self.in_flight_operations += 1
self._idle.clear()
data = bytes(data)
self.write_command_queue.put_nowait(AxiLiteWriteCmd(address, bytes(data), prot, event))
cocotb.start_soon(self._write_wrapper(address, bytes(data), prot, event))
return event
@@ -174,10 +176,28 @@ class AxiLiteMasterWrite(Region, Reset):
await self._idle.wait()
async def write(self, address, data, prot=AxiProt.NONSECURE):
event = self.init_write(address, data, prot)
if address < 0 or address >= 2**self.address_width:
raise ValueError("Address out of range")
if isinstance(data, int):
raise ValueError("Expected bytes or bytearray for data")
if not self.awprot_present and prot != AxiProt.NONSECURE:
raise ValueError("awprot sideband signal value specified, but signal is not connected")
event = Event()
data = bytes(data)
self.in_flight_operations += 1
self._idle.clear()
await self.write_command_queue.put(AxiLiteWriteCmd(address, data, prot, event))
await event.wait()
return event.data
async def _write_wrapper(self, address, data, prot, event):
event.set(await self.write(address, data, prot))
def _handle_reset(self, state):
if state:
self.log.info("Reset asserted")
@@ -220,9 +240,9 @@ class AxiLiteMasterWrite(Region, Reset):
else:
self.log.info("Reset de-asserted")
if self._process_write_cr is None:
self._process_write_cr = cocotb.fork(self._process_write())
self._process_write_cr = cocotb.start_soon(self._process_write())
if self._process_write_resp_cr is None:
self._process_write_resp_cr = cocotb.fork(self._process_write_resp())
self._process_write_resp_cr = cocotb.start_soon(self._process_write_resp())
async def _process_write(self):
while True:
@@ -266,9 +286,15 @@ class AxiLiteMasterWrite(Region, Reset):
offset += 1
aw = self.aw_channel._transaction_obj()
if k == 0:
aw.awaddr = cmd.address
else:
aw.awaddr = word_addr + k*self.byte_lanes
aw.awprot = cmd.prot
if not self.wstrb_present and strb != self.strb_mask:
self.log.warning("Partial operation requested with wstrb not connected, write will be zero-padded (0x%x != 0x%x)", strb, self.strb_mask)
w = self.w_channel._transaction_obj()
w.wdata = val
w.wstrb = strb
@@ -288,7 +314,7 @@ class AxiLiteMasterWrite(Region, Reset):
for k in range(cmd.cycles):
b = await self.b_channel.recv()
cycle_resp = AxiResp(getattr(b, 'bresp', AxiResp.OKAY))
cycle_resp = AxiResp(int(getattr(b, 'bresp', AxiResp.OKAY)))
if cycle_resp != AxiResp.OKAY:
resp = cycle_resp
@@ -326,6 +352,7 @@ class AxiLiteMasterRead(Region, Reset):
self.r_channel.queue_occupancy_limit = 2
self.read_command_queue = Queue()
self.read_command_queue.queue_occupancy_limit = 2
self.current_read_command = None
self.int_read_resp_command_queue = Queue()
@@ -377,10 +404,7 @@ class AxiLiteMasterRead(Region, Reset):
if not self.arprot_present and prot != AxiProt.NONSECURE:
raise ValueError("arprot sideband signal value specified, but signal is not connected")
self.in_flight_operations += 1
self._idle.clear()
self.read_command_queue.put_nowait(AxiLiteReadCmd(address, length, prot, event))
cocotb.start_soon(self._read_wrapper(address, length, prot, event))
return event
@@ -392,10 +416,25 @@ class AxiLiteMasterRead(Region, Reset):
await self._idle.wait()
async def read(self, address, length, prot=AxiProt.NONSECURE):
event = self.init_read(address, length, prot)
if address < 0 or address >= 2**self.address_width:
raise ValueError("Address out of range")
if not self.arprot_present and prot != AxiProt.NONSECURE:
raise ValueError("arprot sideband signal value specified, but signal is not connected")
event = Event()
self.in_flight_operations += 1
self._idle.clear()
await self.read_command_queue.put(AxiLiteReadCmd(address, length, prot, event))
await event.wait()
return event.data
async def _read_wrapper(self, address, length, prot, event):
event.set(await self.read(address, length, prot))
def _handle_reset(self, state):
if state:
self.log.info("Reset asserted")
@@ -437,9 +476,9 @@ class AxiLiteMasterRead(Region, Reset):
else:
self.log.info("Reset de-asserted")
if self._process_read_cr is None:
self._process_read_cr = cocotb.fork(self._process_read())
self._process_read_cr = cocotb.start_soon(self._process_read())
if self._process_read_resp_cr is None:
self._process_read_resp_cr = cocotb.fork(self._process_read_resp())
self._process_read_resp_cr = cocotb.start_soon(self._process_read_resp())
async def _process_read(self):
while True:
@@ -458,6 +497,9 @@ class AxiLiteMasterRead(Region, Reset):
for k in range(cycles):
ar = self.ar_channel._transaction_obj()
if k == 0:
ar.araddr = cmd.address
else:
ar.araddr = word_addr + k*self.byte_lanes
ar.arprot = cmd.prot
@@ -481,7 +523,7 @@ class AxiLiteMasterRead(Region, Reset):
r = await self.r_channel.recv()
cycle_data = int(r.rdata)
cycle_resp = AxiResp(getattr(r, 'rresp', AxiResp.OKAY))
cycle_resp = AxiResp(int(getattr(r, 'rresp', AxiResp.OKAY)))
if cycle_resp != AxiResp.OKAY:
resp = cycle_resp

View File

@@ -60,8 +60,9 @@ class AxiLiteSlaveWrite(Reset):
self.byte_lanes = self.width // self.byte_size
self.strb_mask = 2**self.byte_lanes-1
self.wstrb_present = hasattr(self.bus.w, "wstrb")
self.log.info("AXI lite slave model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", self.address_width)
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
@@ -74,6 +75,7 @@ class AxiLiteSlaveWrite(Reset):
else:
self.log.info(" %s: not present", sig)
if self.wstrb_present:
assert self.byte_lanes == len(self.w_channel.bus.wstrb)
assert self.byte_lanes * self.byte_size == self.width
@@ -97,19 +99,22 @@ class AxiLiteSlaveWrite(Reset):
else:
self.log.info("Reset de-asserted")
if self._process_write_cr is None:
self._process_write_cr = cocotb.fork(self._process_write())
self._process_write_cr = cocotb.start_soon(self._process_write())
async def _process_write(self):
while True:
aw = await self.aw_channel.recv()
addr = (int(aw.awaddr) // self.byte_lanes) * self.byte_lanes
prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE))
prot = AxiProt(int(getattr(aw, 'awprot', AxiProt.NONSECURE)))
w = await self.w_channel.recv()
data = int(w.wdata)
if self.wstrb_present:
strb = int(getattr(w, 'wstrb', self.strb_mask))
else:
strb = self.strb_mask
# generate operation list
offset = 0
@@ -176,7 +181,6 @@ class AxiLiteSlaveRead(Reset):
self.byte_lanes = self.width // self.byte_size
self.log.info("AXI lite slave model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", self.address_width)
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
@@ -210,14 +214,14 @@ class AxiLiteSlaveRead(Reset):
else:
self.log.info("Reset de-asserted")
if self._process_read_cr is None:
self._process_read_cr = cocotb.fork(self._process_read())
self._process_read_cr = cocotb.start_soon(self._process_read())
async def _process_read(self):
while True:
ar = await self.ar_channel.recv()
addr = (int(ar.araddr) // self.byte_lanes) * self.byte_lanes
prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE))
prot = AxiProt(int(getattr(ar, 'arprot', AxiProt.NONSECURE)))
r = self.r_channel._transaction_obj()
r.rresp = AxiResp.OKAY
@@ -245,5 +249,5 @@ class AxiLiteSlave:
super().__init__(**kwargs)
self.write_if = AxiLiteSlaveWrite(target, bus.write, clock, reset, reset_active_level)
self.read_if = AxiLiteSlaveRead(target, bus.read, clock, reset, reset_active_level)
self.write_if = AxiLiteSlaveWrite(bus.write, clock, reset, target, reset_active_level)
self.read_if = AxiLiteSlaveRead(bus.read, clock, reset, target, reset_active_level)

View File

@@ -282,12 +282,13 @@ class AxiStreamBase(Reset):
self.idle_event = Event()
self.idle_event.set()
self.active_event = Event()
self.wake_event = Event()
self.queue_occupancy_bytes = 0
self.queue_occupancy_frames = 0
self.width = len(self.bus.tdata)
self.byte_lanes = 1
self.byte_lanes = self.width // 8
if self._valid_init is not None and hasattr(self.bus, "tvalid"):
self.bus.tvalid.setimmediatevalue(self._valid_init)
@@ -366,7 +367,7 @@ class AxiStreamBase(Reset):
else:
self.log.info("Reset de-asserted")
if self._run_cr is None:
self._run_cr = cocotb.fork(self._run())
self._run_cr = cocotb.start_soon(self._run())
async def _run(self):
raise NotImplementedError()
@@ -376,10 +377,23 @@ class AxiStreamPause:
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
self.pause = False
self._pause = False
self._pause_generator = None
self._pause_cr = None
def _pause_update(self, val):
pass
@property
def pause(self):
return self._pause
@pause.setter
def pause(self, val):
if self._pause != val:
self._pause_update(val)
self._pause = val
def set_pause_generator(self, generator=None):
if self._pause_cr is not None:
self._pause_cr.kill()
@@ -388,15 +402,17 @@ class AxiStreamPause:
self._pause_generator = generator
if self._pause_generator is not None:
self._pause_cr = cocotb.fork(self._run_pause())
self._pause_cr = cocotb.start_soon(self._run_pause())
def clear_pause_generator(self):
self.set_pause_generator(None)
async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator:
self.pause = val
await RisingEdge(self.clock)
await clock_edge_event
class AxiStreamSource(AxiStreamBase, AxiStreamPause):
@@ -423,6 +439,7 @@ class AxiStreamSource(AxiStreamBase, AxiStreamPause):
frame = AxiStreamFrame(frame)
await self.queue.put(frame)
self.idle_event.clear()
self.active_event.set()
self.queue_occupancy_bytes += len(frame)
self.queue_occupancy_frames += 1
@@ -432,6 +449,7 @@ class AxiStreamSource(AxiStreamBase, AxiStreamPause):
frame = AxiStreamFrame(frame)
self.queue.put_nowait(frame)
self.idle_event.clear()
self.active_event.set()
self.queue_occupancy_bytes += len(frame)
self.queue_occupancy_frames += 1
@@ -483,15 +501,25 @@ class AxiStreamSource(AxiStreamBase, AxiStreamPause):
frame_offset = 0
self.active = False
has_tready = hasattr(self.bus, "tready")
has_tvalid = hasattr(self.bus, "tvalid")
has_tlast = hasattr(self.bus, "tlast")
has_tkeep = hasattr(self.bus, "tkeep")
has_tid = hasattr(self.bus, "tid")
has_tdest = hasattr(self.bus, "tdest")
has_tuser = hasattr(self.bus, "tuser")
clock_edge_event = RisingEdge(self.clock)
while True:
await RisingEdge(self.clock)
await clock_edge_event
# read handshake signals
tready_sample = (not hasattr(self.bus, "tready")) or self.bus.tready.value
tvalid_sample = (not hasattr(self.bus, "tvalid")) or self.bus.tvalid.value
tready_sample = (not has_tready) or self.bus.tready.value
tvalid_sample = (not has_tvalid) or self.bus.tvalid.value
if (tready_sample and tvalid_sample) or not tvalid_sample:
if frame is None and not self.queue.empty():
if not frame and not self.queue.empty():
frame = self.queue.get_nowait()
self.dequeue_event.set()
self.queue_occupancy_bytes -= len(frame)
@@ -529,26 +557,29 @@ class AxiStreamSource(AxiStreamBase, AxiStreamPause):
break
self.bus.tdata.value = tdata_val
if hasattr(self.bus, "tvalid"):
if has_tvalid:
self.bus.tvalid.value = 1
if hasattr(self.bus, "tlast"):
if has_tlast:
self.bus.tlast.value = tlast_val
if hasattr(self.bus, "tkeep"):
if has_tkeep:
self.bus.tkeep.value = tkeep_val
if hasattr(self.bus, "tid"):
if has_tid:
self.bus.tid.value = tid_val
if hasattr(self.bus, "tdest"):
if has_tdest:
self.bus.tdest.value = tdest_val
if hasattr(self.bus, "tuser"):
if has_tuser:
self.bus.tuser.value = tuser_val
else:
if hasattr(self.bus, "tvalid"):
if has_tvalid:
self.bus.tvalid.value = 0
if hasattr(self.bus, "tlast"):
if has_tlast:
self.bus.tlast.value = 0
self.active = bool(frame)
if not frame and self.queue.empty():
self.idle_event.set()
self.active_event.clear()
await self.active_event.wait()
class AxiStreamMonitor(AxiStreamBase):
@@ -567,11 +598,20 @@ class AxiStreamMonitor(AxiStreamBase):
self.read_queue = []
if hasattr(self.bus, "tvalid"):
cocotb.start_soon(self._run_tvalid_monitor())
if hasattr(self.bus, "tready"):
cocotb.start_soon(self._run_tready_monitor())
def _dequeue(self, frame):
pass
def _recv(self, frame, compact=True):
if self.queue.empty():
self.active_event.clear()
self.queue_occupancy_bytes -= len(frame)
self.queue_occupancy_frames -= 1
self._dequeue(frame)
if compact:
frame.compact()
return frame
@@ -611,19 +651,45 @@ class AxiStreamMonitor(AxiStreamBase):
else:
await self.active_event.wait()
async def _run_tvalid_monitor(self):
event = RisingEdge(self.bus.tvalid)
while True:
await event
self.wake_event.set()
async def _run_tready_monitor(self):
event = RisingEdge(self.bus.tready)
while True:
await event
self.wake_event.set()
async def _run(self):
frame = None
self.active = False
has_tready = hasattr(self.bus, "tready")
has_tvalid = hasattr(self.bus, "tvalid")
has_tlast = hasattr(self.bus, "tlast")
has_tkeep = hasattr(self.bus, "tkeep")
has_tid = hasattr(self.bus, "tid")
has_tdest = hasattr(self.bus, "tdest")
has_tuser = hasattr(self.bus, "tuser")
clock_edge_event = RisingEdge(self.clock)
wake_event = self.wake_event.wait()
while True:
await RisingEdge(self.clock)
await clock_edge_event
# read handshake signals
tready_sample = (not hasattr(self.bus, "tready")) or self.bus.tready.value
tvalid_sample = (not hasattr(self.bus, "tvalid")) or self.bus.tvalid.value
tready_sample = (not has_tready) or self.bus.tready.value
tvalid_sample = (not has_tvalid) or self.bus.tvalid.value
if tready_sample and tvalid_sample:
if frame is None:
if not frame:
if self.byte_size == 8:
frame = AxiStreamFrame(bytearray(), [], [], [], [])
else:
@@ -633,16 +699,16 @@ class AxiStreamMonitor(AxiStreamBase):
for offset in range(self.byte_lanes):
frame.tdata.append((self.bus.tdata.value.integer >> (offset * self.byte_size)) & self.byte_mask)
if hasattr(self.bus, "tkeep"):
if has_tkeep:
frame.tkeep.append((self.bus.tkeep.value.integer >> offset) & 1)
if hasattr(self.bus, "tid"):
if has_tid:
frame.tid.append(self.bus.tid.value.integer)
if hasattr(self.bus, "tdest"):
if has_tdest:
frame.tdest.append(self.bus.tdest.value.integer)
if hasattr(self.bus, "tuser"):
if has_tuser:
frame.tuser.append(self.bus.tuser.value.integer)
if not hasattr(self.bus, "tlast") or self.bus.tlast.value:
if not has_tlast or self.bus.tlast.value:
frame.sim_time_end = get_sim_time()
self.log.info("RX frame: %s", frame)
@@ -656,6 +722,9 @@ class AxiStreamMonitor(AxiStreamBase):
else:
self.active = bool(frame)
self.wake_event.clear()
await wake_event
class AxiStreamSink(AxiStreamMonitor, AxiStreamPause):
@@ -669,11 +738,11 @@ class AxiStreamSink(AxiStreamMonitor, AxiStreamPause):
def __init__(self, bus, clock, reset=None, reset_active_level=True,
byte_size=None, byte_lanes=None, *args, **kwargs):
super().__init__(bus, clock, reset, reset_active_level, byte_size, byte_lanes, *args, **kwargs)
self.queue_occupancy_limit_bytes = -1
self.queue_occupancy_limit_frames = -1
super().__init__(bus, clock, reset, reset_active_level, byte_size, byte_lanes, *args, **kwargs)
def full(self):
if self.queue_occupancy_limit_bytes > 0 and self.queue_occupancy_bytes > self.queue_occupancy_limit_bytes:
return True
@@ -689,19 +758,39 @@ class AxiStreamSink(AxiStreamMonitor, AxiStreamPause):
if hasattr(self.bus, "tready"):
self.bus.tready.value = 0
def _pause_update(self, val):
self.wake_event.set()
def _dequeue(self, frame):
self.wake_event.set()
async def _run(self):
frame = None
self.active = False
has_tready = hasattr(self.bus, "tready")
has_tvalid = hasattr(self.bus, "tvalid")
has_tlast = hasattr(self.bus, "tlast")
has_tkeep = hasattr(self.bus, "tkeep")
has_tid = hasattr(self.bus, "tid")
has_tdest = hasattr(self.bus, "tdest")
has_tuser = hasattr(self.bus, "tuser")
clock_edge_event = RisingEdge(self.clock)
wake_event = self.wake_event.wait()
while True:
await RisingEdge(self.clock)
pause_sample = self.pause
await clock_edge_event
# read handshake signals
tready_sample = (not hasattr(self.bus, "tready")) or self.bus.tready.value
tvalid_sample = (not hasattr(self.bus, "tvalid")) or self.bus.tvalid.value
tready_sample = (not has_tready) or self.bus.tready.value
tvalid_sample = (not has_tvalid) or self.bus.tvalid.value
if tready_sample and tvalid_sample:
if frame is None:
if not frame:
if self.byte_size == 8:
frame = AxiStreamFrame(bytearray(), [], [], [], [])
else:
@@ -711,16 +800,16 @@ class AxiStreamSink(AxiStreamMonitor, AxiStreamPause):
for offset in range(self.byte_lanes):
frame.tdata.append((self.bus.tdata.value.integer >> (offset * self.byte_size)) & self.byte_mask)
if hasattr(self.bus, "tkeep"):
if has_tkeep:
frame.tkeep.append((self.bus.tkeep.value.integer >> offset) & 1)
if hasattr(self.bus, "tid"):
if has_tid:
frame.tid.append(self.bus.tid.value.integer)
if hasattr(self.bus, "tdest"):
if has_tdest:
frame.tdest.append(self.bus.tdest.value.integer)
if hasattr(self.bus, "tuser"):
if has_tuser:
frame.tuser.append(self.bus.tuser.value.integer)
if not hasattr(self.bus, "tlast") or self.bus.tlast.value:
if not has_tlast or self.bus.tlast.value:
frame.sim_time_end = get_sim_time()
self.log.info("RX frame: %s", frame)
@@ -734,5 +823,9 @@ class AxiStreamSink(AxiStreamMonitor, AxiStreamPause):
else:
self.active = bool(frame)
if hasattr(self.bus, "tready"):
self.bus.tready.value = (not self.full() and not self.pause)
if has_tready:
self.bus.tready.value = (not self.full() and not pause_sample)
if not tvalid_sample or (self.pause and pause_sample) or self.full():
self.wake_event.clear()
await wake_event

View File

@@ -33,7 +33,7 @@ class Reset:
self._reset_state = True
if reset_signal is not None:
cocotb.fork(self._run_reset(reset_signal, bool(active_level)))
cocotb.start_soon(self._run_reset(reset_signal, bool(active_level)))
self._update_reset()

View File

@@ -99,6 +99,7 @@ class StreamBase(Reset):
self.idle_event = Event()
self.idle_event.set()
self.active_event = Event()
self.wake_event = Event()
self.ready = None
self.valid = None
@@ -153,7 +154,7 @@ class StreamBase(Reset):
else:
self.log.info("Reset de-asserted")
if self._run_cr is None:
self._run_cr = cocotb.fork(self._run())
self._run_cr = cocotb.start_soon(self._run())
async def _run(self):
raise NotImplementedError()
@@ -163,10 +164,23 @@ class StreamPause:
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
self.pause = False
self._pause = False
self._pause_generator = None
self._pause_cr = None
def _pause_update(self, val):
pass
@property
def pause(self):
return self._pause
@pause.setter
def pause(self, val):
if self._pause != val:
self._pause_update(val)
self._pause = val
def set_pause_generator(self, generator=None):
if self._pause_cr is not None:
self._pause_cr.kill()
@@ -175,15 +189,17 @@ class StreamPause:
self._pause_generator = generator
if self._pause_generator is not None:
self._pause_cr = cocotb.fork(self._run_pause())
self._pause_cr = cocotb.start_soon(self._run_pause())
def clear_pause_generator(self):
self.set_pause_generator(None)
async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator:
self.pause = val
await RisingEdge(self.clock)
await clock_edge_event
class StreamSource(StreamBase, StreamPause):
@@ -204,12 +220,14 @@ class StreamSource(StreamBase, StreamPause):
await self.dequeue_event.wait()
await self.queue.put(obj)
self.idle_event.clear()
self.active_event.set()
def send_nowait(self, obj):
if self.full():
raise QueueFull()
self.queue.put_nowait(obj)
self.idle_event.clear()
self.active_event.set()
def full(self):
if self.queue_occupancy_limit > 0 and self.count() >= self.queue_occupancy_limit:
@@ -231,8 +249,10 @@ class StreamSource(StreamBase, StreamPause):
self.valid.value = 0
async def _run(self):
clock_edge_event = RisingEdge(self.clock)
while True:
await RisingEdge(self.clock)
await clock_edge_event
# read handshake signals
ready_sample = self.ready is None or self.ready.value
@@ -251,6 +271,9 @@ class StreamSource(StreamBase, StreamPause):
self.active = not self.queue.empty()
if self.queue.empty():
self.idle_event.set()
self.active_event.clear()
await self.active_event.wait()
class StreamMonitor(StreamBase):
@@ -260,9 +283,21 @@ class StreamMonitor(StreamBase):
_valid_init = None
_ready_init = None
def __init__(self, bus, clock, reset=None, reset_active_level=True, *args, **kwargs):
super().__init__(bus, clock, reset, reset_active_level, *args, **kwargs)
if self.valid is not None:
cocotb.start_soon(self._run_valid_monitor())
if self.ready is not None:
cocotb.start_soon(self._run_ready_monitor())
def _dequeue(self, item):
pass
def _recv(self, item):
if self.queue.empty():
self.active_event.clear()
self._dequeue(item)
return item
async def recv(self):
@@ -281,9 +316,27 @@ class StreamMonitor(StreamBase):
else:
await self.active_event.wait()
async def _run(self):
async def _run_valid_monitor(self):
event = RisingEdge(self.valid)
while True:
await RisingEdge(self.clock)
await event
self.wake_event.set()
async def _run_ready_monitor(self):
event = RisingEdge(self.ready)
while True:
await event
self.wake_event.set()
async def _run(self):
clock_edge_event = RisingEdge(self.clock)
wake_event = self.wake_event.wait()
while True:
await clock_edge_event
# read handshake signals
ready_sample = self.ready is None or self.ready.value
@@ -294,6 +347,9 @@ class StreamMonitor(StreamBase):
self.bus.sample(obj)
self.queue.put_nowait(obj)
self.active_event.set()
else:
self.wake_event.clear()
await wake_event
class StreamSink(StreamMonitor, StreamPause):
@@ -321,9 +377,21 @@ class StreamSink(StreamMonitor, StreamPause):
if self.ready is not None:
self.ready.value = 0
def _pause_update(self, val):
self.wake_event.set()
def _dequeue(self, item):
self.wake_event.set()
async def _run(self):
clock_edge_event = RisingEdge(self.clock)
wake_event = self.wake_event.wait()
while True:
await RisingEdge(self.clock)
pause_sample = self.pause
await clock_edge_event
# read handshake signals
ready_sample = self.ready is None or self.ready.value
@@ -336,7 +404,11 @@ class StreamSink(StreamMonitor, StreamPause):
self.active_event.set()
if self.ready is not None:
self.ready.value = (not self.full() and not self.pause)
self.ready.value = (not self.full() and not pause_sample)
if not valid_sample or (self.pause and pause_sample) or self.full():
self.wake_event.clear()
await wake_event
def define_stream(name, signals, optional_signals=None, valid_signal=None, ready_signal=None, signal_widths=None):

View File

@@ -1 +1 @@
__version__ = "0.1.16"
__version__ = "0.1.20"

View File

@@ -27,7 +27,7 @@ classifiers =
packages = find_namespace:
python_requires = >=3.6
install_requires =
cocotb
cocotb >= 1.6.0
cocotb-bus
[options.extras_require]
@@ -47,31 +47,38 @@ addopts =
# tox configuration
[tox:tox]
envlist = py36, py37, py38, py39
envlist = py37, py38, py39, py310
skip_missing_interpreters = true
minversion = 3.18.0
requires = virtualenv >= 16.1
[gh-actions]
python =
3.6: py36
3.7: py37
3.8: py38
3.9: py39
3.10: py310
[testenv]
setenv =
COVERAGE=1
usedevelop = True
deps =
pytest
pytest-xdist
cocotb-test
coverage
pytest-cov
pytest == 7.2.1
pytest-xdist == 3.1.0
cocotb == 1.7.2
cocotb-bus == 0.2.1
cocotb-test == 0.2.4
coverage == 7.0.5
pytest-cov == 4.0.0
commands =
pytest --cov=cocotbext --cov=tests --cov-branch -n auto
pytest --cov=cocotbext --cov=tests --cov-branch {posargs:-n auto --verbose}
bash -c 'find . -type f -name "\.coverage" | xargs coverage combine --append'
coverage report
whitelist_externals =
allowlist_externals =
bash
# combine if paths are different

View File

@@ -45,7 +45,7 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 2, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 2, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "axi"), dut.clk, dut.rst)
self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "axi"), dut.clk, dut.rst, size=2**16)
@@ -283,7 +283,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

View File

@@ -45,7 +45,7 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 2, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 2, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "axil"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "axil"), dut.clk, dut.rst, size=2**16)
@@ -272,7 +272,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

View File

@@ -45,7 +45,7 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 2, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 2, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "axis"), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "axis"), dut.clk, dut.rst)