353 lines
11 KiB
Python
353 lines
11 KiB
Python
"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import cocotb
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from cocotb.triggers import RisingEdge, ReadOnly, Event
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from cocotb.drivers import BusDriver
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import mmap
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import queue
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from collections import deque
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from .constants import *
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class AxiLiteRamWrite(BusDriver):
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_signals = [
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# Write address channel
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"awaddr", "awprot", "awvalid", "awready",
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# Write data channel
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"wdata", "wstrb", "wvalid", "wready",
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# Write response channel
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"bresp", "bvalid", "bready",
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]
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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super().__init__(entity, name, clock)
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.int_write_addr_queue = deque()
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self.int_write_addr_sync = Event()
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self.int_write_data_queue = deque()
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self.int_write_data_sync = Event()
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self.int_write_resp_queue = deque()
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self.int_write_resp_sync = Event()
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self.in_flight_operations = 0
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self.width = len(self.bus.wdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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self.strb_mask = 2**len(self.bus.wstrb)-1
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assert self.byte_width == len(self.bus.wstrb)
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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assert len(self.bus.awprot) == 3
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assert len(self.bus.awvalid) == 1
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assert len(self.bus.awready) == 1
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self.bus.awready.setimmediatevalue(0)
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assert len(self.bus.wvalid) == 1
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assert len(self.bus.wready) == 1
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self.bus.wready.setimmediatevalue(0)
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assert len(self.bus.bresp) == 2
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self.bus.bresp.setimmediatevalue(0)
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assert len(self.bus.bvalid) == 1
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self.bus.bvalid.setimmediatevalue(0)
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assert len(self.bus.bready) == 1
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cocotb.fork(self._process_write())
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cocotb.fork(self._process_write_addr_if())
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cocotb.fork(self._process_write_data_if())
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cocotb.fork(self._process_write_resp_if())
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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async def _process_write(self):
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while True:
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if not self.int_write_addr_queue:
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self.int_write_addr_sync.clear()
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await self.int_write_addr_sync.wait()
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addr, prot = self.int_write_addr_queue.popleft()
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addr = (addr // self.byte_width) * self.byte_width
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prot = AxiProt(prot)
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if not self.int_write_data_queue:
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self.int_write_data_sync.clear()
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await self.int_write_data_sync.wait()
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data, strb = self.int_write_data_queue.popleft()
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# todo latency
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self.mem.seek(addr % self.size)
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data = data.to_bytes(self.byte_width, 'little')
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self.log.info(f"Write data addr: {addr:#010x} prot: {prot} wstrb: {strb:#04x} data: {' '.join((f'{c:02x}' for c in data))}")
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for i in range(self.byte_width):
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if strb & (1 << i):
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self.mem.write(data[i:i+1])
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else:
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self.mem.seek(1, 1)
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self.int_write_resp_queue.append(AxiResp.OKAY)
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self.int_write_resp_sync.set()
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async def _process_write_addr_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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awready_sample = self.bus.awready.value
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awvalid_sample = self.bus.awvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.awready <= 0
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continue
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if awready_sample and awvalid_sample:
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awaddr = self.bus.awaddr.value.integer
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awprot = self.bus.awprot.value.integer
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self.int_write_addr_queue.append((awaddr, awprot))
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self.int_write_addr_sync.set()
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await RisingEdge(self.clock)
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self.bus.awready <= 1
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async def _process_write_data_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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wready_sample = self.bus.wready.value
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wvalid_sample = self.bus.wvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.wready <= 0
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continue
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if wready_sample and wvalid_sample:
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wdata = self.bus.wdata.value.integer
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wstrb = self.bus.wstrb.value.integer
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self.int_write_data_queue.append((wdata, wstrb))
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self.int_write_data_sync.set()
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await RisingEdge(self.clock)
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self.bus.wready <= 1
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async def _process_write_resp_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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bready_sample = self.bus.bready.value
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bvalid_sample = self.bus.bvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.bvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (bready_sample and bvalid_sample) or (not bvalid_sample):
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if self.int_write_resp_queue:
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bresp = self.int_write_resp_queue.popleft()
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self.bus.bresp <= bresp
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self.bus.bvalid <= 1
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else:
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self.bus.bvalid <= 0
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class AxiLiteRamRead(BusDriver):
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_signals = [
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# Read address channel
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"araddr", "arprot", "arvalid", "arready",
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# Read data channel
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"rdata", "rresp", "rvalid", "rready",
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]
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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super().__init__(entity, name, clock)
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.int_read_addr_queue = deque()
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self.int_read_addr_sync = Event()
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self.int_read_resp_command_queue = deque()
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self.int_read_resp_command_sync = Event()
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self.int_read_resp_queue = deque()
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self.int_read_resp_sync = Event()
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self.in_flight_operations = 0
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self.width = len(self.bus.rdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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assert len(self.bus.arprot) == 3
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assert len(self.bus.arvalid) == 1
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assert len(self.bus.arready) == 1
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self.bus.arready.setimmediatevalue(0)
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self.bus.rdata.setimmediatevalue(0)
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assert len(self.bus.rresp) == 2
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self.bus.rresp.setimmediatevalue(0)
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assert len(self.bus.rvalid) == 1
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self.bus.rvalid.setimmediatevalue(0)
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assert len(self.bus.rready) == 1
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cocotb.fork(self._process_read())
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cocotb.fork(self._process_read_addr_if())
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cocotb.fork(self._process_read_resp_if())
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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async def _process_read(self):
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while True:
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if not self.int_read_addr_queue:
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self.int_read_addr_sync.clear()
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await self.int_read_addr_sync.wait()
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addr, prot = self.int_read_addr_queue.popleft()
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addr = (addr // self.byte_width) * self.byte_width
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prot = AxiProt(prot)
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# todo latency
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self.mem.seek(addr % self.size)
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data = self.mem.read(self.byte_width)
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self.int_read_resp_queue.append((int.from_bytes(data, 'little'), AxiResp.OKAY))
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self.int_read_resp_sync.set()
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self.log.info(f"Read data addr: {addr:#010x} prot: {prot} data: {' '.join((f'{c:02x}' for c in data))}")
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async def _process_read_addr_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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arready_sample = self.bus.arready.value
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arvalid_sample = self.bus.arvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.arready <= 0
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continue
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if arready_sample and arvalid_sample:
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araddr = self.bus.araddr.value.integer
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arprot = self.bus.arprot.value.integer
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self.int_read_addr_queue.append((araddr, arprot))
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self.int_read_addr_sync.set()
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await RisingEdge(self.clock)
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self.bus.arready <= 1
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async def _process_read_resp_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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rready_sample = self.bus.rready.value
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rvalid_sample = self.bus.rvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.rvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (rready_sample and rvalid_sample) or (not rvalid_sample):
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if self.int_read_resp_queue:
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rdata, rresp = self.int_read_resp_queue.popleft()
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self.bus.rdata <= rdata
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self.bus.rresp <= rresp
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self.bus.rvalid <= 1
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else:
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self.bus.rvalid <= 0
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class AxiLiteRam(object):
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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self.write_if = None
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self.read_if = None
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.write_if = AxiLiteRamWrite(entity, name, clock, reset, mem=self.mem)
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self.read_if = AxiLiteRamRead(entity, name, clock, reset, mem=self.mem)
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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