Alex Forencich 69717c1698 Add AXI bus objects

2021-03-06 16:26:51 -08:00

..

Makefile

Rework sim_build output directory, fix default makefile target

2020-12-29 14:25:44 -08:00

test_axil.py

Add AXI bus objects

2021-03-06 16:26:51 -08:00

test_axil.v

Change timescale to speed up verilator

2020-11-15 13:09:53 -08:00