208 lines
6.7 KiB
Python
208 lines
6.7 KiB
Python
"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import mmap
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import cocotb
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from cocotb.log import SimLog
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from .version import __version__
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from .constants import AxiProt, AxiResp
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from .axil_channels import AxiLiteAWSink, AxiLiteWSink, AxiLiteBSource, AxiLiteARSink, AxiLiteRSource
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from .utils import hexdump, hexdump_str
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class AxiLiteRamWrite(object):
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
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self.log.info("AXI lite RAM model")
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self.log.info("cocotbext-axi version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.reset = reset
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self.aw_channel = AxiLiteAWSink(entity, name, clock, reset)
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self.w_channel = AxiLiteWSink(entity, name, clock, reset)
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self.b_channel = AxiLiteBSource(entity, name, clock, reset)
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self.in_flight_operations = 0
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self.width = len(self.w_channel.bus.wdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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self.strb_mask = 2**self.byte_width-1
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assert self.byte_width == len(self.w_channel.bus.wstrb)
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assert self.byte_width * self.byte_size == self.width
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cocotb.fork(self._process_write())
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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def hexdump(self, address, length, prefix=""):
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hexdump(self.mem, address, length, prefix=prefix)
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def hexdump_str(self, address, length, prefix=""):
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return hexdump_str(self.mem, address, length, prefix=prefix)
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async def _process_write(self):
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while True:
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await self.aw_channel.wait()
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aw = self.aw_channel.recv()
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addr = (int(aw.awaddr) // self.byte_width) * self.byte_width
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prot = AxiProt(aw.awprot)
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await self.w_channel.wait()
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w = self.w_channel.recv()
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data = int(w.wdata)
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strb = int(w.wstrb)
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# todo latency
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self.mem.seek(addr % self.size)
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data = data.to_bytes(self.byte_width, 'little')
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self.log.info("Write data awaddr: 0x%08x awprot: %s wstrb: 0x%02x data: %s",
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addr, prot, strb, ' '.join((f'{c:02x}' for c in data)))
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for i in range(self.byte_width):
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if strb & (1 << i):
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self.mem.write(data[i:i+1])
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else:
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self.mem.seek(1, 1)
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b = self.b_channel._transaction_obj()
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b.bresp = AxiResp.OKAY
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self.b_channel.send(b)
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class AxiLiteRamRead(object):
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
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self.reset = reset
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self.ar_channel = AxiLiteARSink(entity, name, clock, reset)
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self.r_channel = AxiLiteRSource(entity, name, clock, reset)
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.in_flight_operations = 0
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self.width = len(self.r_channel.bus.rdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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assert self.byte_width * self.byte_size == self.width
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cocotb.fork(self._process_read())
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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def hexdump(self, address, length, prefix=""):
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hexdump(self.mem, address, length, prefix=prefix)
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def hexdump_str(self, address, length, prefix=""):
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return hexdump_str(self.mem, address, length, prefix=prefix)
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async def _process_read(self):
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while True:
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await self.ar_channel.wait()
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ar = self.ar_channel.recv()
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addr = (int(ar.araddr) // self.byte_width) * self.byte_width
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prot = AxiProt(ar.arprot)
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# todo latency
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self.mem.seek(addr % self.size)
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data = self.mem.read(self.byte_width)
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r = self.r_channel._transaction_obj()
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r.rdata = int.from_bytes(data, 'little')
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r.rresp = AxiResp.OKAY
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self.r_channel.send(r)
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self.log.info("Read data araddr: 0x%08x arprot: %s data: %s",
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addr, prot, ' '.join((f'{c:02x}' for c in data)))
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class AxiLiteRam(object):
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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self.write_if = None
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self.read_if = None
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.write_if = AxiLiteRamWrite(entity, name, clock, reset, mem=self.mem)
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self.read_if = AxiLiteRamRead(entity, name, clock, reset, mem=self.mem)
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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def hexdump(self, address, length, prefix=""):
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hexdump(self.mem, address, length, prefix=prefix)
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def hexdump_str(self, address, length, prefix=""):
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return hexdump_str(self.mem, address, length, prefix=prefix)
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