Alex Forencich c677ab245c Reset more internal state

2021-03-22 22:02:06 -07:00

..

__init__.py

Add AXI bus objects

2021-03-06 16:26:51 -08:00

axi_channels.py

Add AXI bus objects

2021-03-06 16:26:51 -08:00

axi_master.py

Reset more internal state

2021-03-22 22:02:06 -07:00

axi_ram.py

Reset processing on assert edge only to permit operations to be queued while reset is asserted

2021-03-21 12:13:19 -07:00

axil_channels.py

Add AXI bus objects

2021-03-06 16:26:51 -08:00

axil_master.py

Return event object from init_read and init_write; remove get_write_resp and get_read_data

2021-03-22 21:21:34 -07:00

axil_ram.py

Reset processing on assert edge only to permit operations to be queued while reset is asserted

2021-03-21 12:13:19 -07:00

axis.py

Enforce max queue depth on streaming sources

2021-03-21 22:24:59 -07:00

constants.py

Clean up and lint removal

2020-11-26 19:51:24 -08:00

memory.py

Remove inherit from object

2020-12-24 14:44:42 -08:00

reset.py

Use start_soon instead of fork

2021-03-21 11:40:25 -07:00

stream.py

Enforce max queue depth on streaming sources

2021-03-21 22:24:59 -07:00

utils.py

Add row_size parameter to hexdump methods

2021-01-06 18:39:03 -08:00

version.py

Bump to dev version

2021-03-17 18:32:42 -07:00