Alex Forencich 11f9db8b06 Add test cases for init_read and init_write

2021-03-22 21:22:13 -07:00

..

Makefile

Rework sim_build output directory, fix default makefile target

2020-12-29 14:25:44 -08:00

test_axil.py

Add test cases for init_read and init_write

2021-03-22 21:22:13 -07:00

test_axil.v

Change timescale to speed up verilator

2020-11-15 13:09:53 -08:00