Alex Forencich 82853b31ff Rename byte_width to byte_lanes

2021-04-12 15:08:30 -07:00

..

Makefile

Rework sim_build output directory, fix default makefile target

2020-12-29 14:25:44 -08:00

test_axil.py

Rename byte_width to byte_lanes

2021-04-12 15:08:30 -07:00

test_axil.v

Change timescale to speed up verilator

2020-11-15 13:09:53 -08:00