Alex Forencich dcb9a6bd02 Rework reset logic to better handle X/Z ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-09-07 12:56:14 -07:00

..

__init__.py

Add APB modules

2025-09-06 17:13:54 -07:00

address_space.py

Add SparseMemoryRegion object

2023-03-23 23:44:29 -07:00

apb.py

Add APB modules

2025-09-06 17:13:54 -07:00

axi_channels.py

Make wstrb optional

2021-12-27 19:44:30 -08:00

axi_master.py

Fix logging when using from_entity

2023-05-26 16:45:46 -07:00

axi_ram.py

Update memory models to use SparseMemory

2023-03-23 23:43:53 -07:00

axi_slave.py

Fix logging when using from_entity

2023-05-26 16:45:46 -07:00

axil_channels.py

Make wstrb optional

2021-12-27 19:44:30 -08:00

axil_master.py

Use append instead of extend in AXI lite master

2025-09-06 17:04:48 -07:00

axil_ram.py

Update memory models to use SparseMemory

2023-03-23 23:43:53 -07:00

axil_slave.py

Fix logging when using from_entity

2023-05-26 16:45:46 -07:00

axis.py

Cast to int instead of using .integer

2025-09-06 22:25:25 -07:00

buddy_allocator.py

Add buddy allocator

2021-11-16 16:53:40 -08:00

constants.py

Clean up and lint removal

2020-11-26 19:51:24 -08:00

memory.py

Use slices to access memory contents to support both mmap and SparseMemory

2023-03-24 01:23:33 -07:00

reset.py

Rework reset logic to better handle X/Z

2025-09-07 12:56:14 -07:00

sparse_memory.py

Add sparse memory model

2023-03-23 19:27:57 -07:00

stream.py

Clean up sink pause handling

2023-08-13 13:20:35 -07:00

utils.py

Add row_size parameter to hexdump methods

2021-01-06 18:39:03 -08:00

version.py

Bump to dev version

2023-03-24 11:05:34 -07:00