95 lines
3.6 KiB
Verilog
95 lines
3.6 KiB
Verilog
/*
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 test module
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*/
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module test_axi #
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(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32,
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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parameter ID_WIDTH = 8,
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parameter AWUSER_WIDTH = 1,
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parameter WUSER_WIDTH = 1,
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parameter BUSER_WIDTH = 1,
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parameter ARUSER_WIDTH = 1,
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parameter RUSER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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inout wire [ID_WIDTH-1:0] axi_awid,
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inout wire [ADDR_WIDTH-1:0] axi_awaddr,
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inout wire [7:0] axi_awlen,
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inout wire [2:0] axi_awsize,
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inout wire [1:0] axi_awburst,
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inout wire axi_awlock,
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inout wire [3:0] axi_awcache,
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inout wire [2:0] axi_awprot,
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inout wire [3:0] axi_awqos,
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inout wire [3:0] axi_awregion,
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inout wire [AWUSER_WIDTH-1:0] axi_awuser,
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inout wire axi_awvalid,
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inout wire axi_awready,
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inout wire [DATA_WIDTH-1:0] axi_wdata,
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inout wire [STRB_WIDTH-1:0] axi_wstrb,
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inout wire axi_wlast,
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inout wire [WUSER_WIDTH-1:0] axi_wuser,
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inout wire axi_wvalid,
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inout wire axi_wready,
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inout wire [ID_WIDTH-1:0] axi_bid,
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inout wire [1:0] axi_bresp,
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inout wire [BUSER_WIDTH-1:0] axi_buser,
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inout wire axi_bvalid,
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inout wire axi_bready,
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inout wire [ID_WIDTH-1:0] axi_arid,
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inout wire [ADDR_WIDTH-1:0] axi_araddr,
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inout wire [7:0] axi_arlen,
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inout wire [2:0] axi_arsize,
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inout wire [1:0] axi_arburst,
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inout wire axi_arlock,
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inout wire [3:0] axi_arcache,
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inout wire [2:0] axi_arprot,
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inout wire [3:0] axi_arqos,
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inout wire [3:0] axi_arregion,
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inout wire [ARUSER_WIDTH-1:0] axi_aruser,
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inout wire axi_arvalid,
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inout wire axi_arready,
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inout wire [ID_WIDTH-1:0] axi_rid,
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inout wire [DATA_WIDTH-1:0] axi_rdata,
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inout wire [1:0] axi_rresp,
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inout wire axi_rlast,
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inout wire [RUSER_WIDTH-1:0] axi_ruser,
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inout wire axi_rvalid,
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inout wire axi_rready
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);
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endmodule
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