Rework sim_build output directory, fix default makefile target

tests/rgmii/Makefile

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
 MODULE   = $(DUT)
 VERILOG_SOURCES += $(DUT).v
 
-SIM_BUILD ?= sim_build_$(MODULE)
-
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
 
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
 	endif
 endif
 
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
 iverilog_dump.v:
 	echo 'module iverilog_dump();' > $@
 	echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
 	echo 'endmodule' >> $@
 
 clean::
-	@rm -rf sim_build_*
 	@rm -rf iverilog_dump.v
 	@rm -rf dump.fst $(TOPLEVEL).fst
-
-include $(shell cocotb-config --makefiles)/Makefile.sim
-

tests/rgmii/test_rgmii.py

@@ -157,8 +157,8 @@ def test_rgmii(request):
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
 
-    sim_build = os.path.join(tests_dir,
-        "sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
 
     cocotb_test.simulator.run(
         python_search=[tests_dir],