From 70772009129885a9c32a1c232fa442aab6874697 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 6 Sep 2025 22:54:37 -0700 Subject: [PATCH] Testbench cleanup for cocotb 2.0 Signed-off-by: Alex Forencich --- tests/eth_mac/Makefile | 30 +++++-------------- tests/eth_mac/test_eth_mac.py | 2 +- tests/gmii/Makefile | 30 +++++-------------- tests/gmii/test_gmii.py | 2 +- tests/gmii_phy/Makefile | 30 +++++-------------- tests/gmii_phy/test_gmii_phy.py | 2 +- tests/mii/Makefile | 30 +++++-------------- tests/mii/test_mii.py | 2 +- tests/mii_phy/Makefile | 30 +++++-------------- tests/mii_phy/test_mii_phy.py | 2 +- tests/ptp_clock/Makefile | 30 +++++-------------- tests/ptp_clock/test_ptp_clock.py | 16 +++++----- tests/ptp_clock_sim_time/Makefile | 30 +++++-------------- .../test_ptp_clock_sim_time.py | 4 +-- tests/rgmii/Makefile | 30 +++++-------------- tests/rgmii/test_rgmii.py | 2 +- tests/rgmii_phy/Makefile | 30 +++++-------------- tests/rgmii_phy/test_rgmii_phy.py | 2 +- tests/xgmii/Makefile | 30 +++++-------------- tests/xgmii/test_xgmii.py | 2 +- 20 files changed, 88 insertions(+), 248 deletions(-) diff --git a/tests/eth_mac/Makefile b/tests/eth_mac/Makefile index e2c028b..5f56983 100644 --- a/tests/eth_mac/Makefile +++ b/tests/eth_mac/Makefile @@ -27,8 +27,10 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_eth_mac -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v # module parameters @@ -42,32 +44,14 @@ export PARAM_AXIS_RX_USER_WIDTH := $(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/eth_mac/test_eth_mac.py b/tests/eth_mac/test_eth_mac.py index b4fe8ca..8e66fd4 100644 --- a/tests/eth_mac/test_eth_mac.py +++ b/tests/eth_mac/test_eth_mac.py @@ -168,7 +168,7 @@ def incrementing_payload(length): return bytearray(itertools.islice(itertools.cycle(range(256)), length)) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: if len(cocotb.top.tx_axis_tdata) == 8: speed = [100e6, 1e9] diff --git a/tests/gmii/Makefile b/tests/gmii/Makefile index 617d69e..fc5d8b9 100644 --- a/tests/gmii/Makefile +++ b/tests/gmii/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_gmii -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/gmii/test_gmii.py b/tests/gmii/test_gmii.py index df7abfe..0ae2012 100644 --- a/tests/gmii/test_gmii.py +++ b/tests/gmii/test_gmii.py @@ -132,7 +132,7 @@ def cycle_en(): return itertools.cycle([0, 0, 0, 1]) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: factory = TestFactory(run_test) factory.add_option("payload_lengths", [size_list]) diff --git a/tests/gmii_phy/Makefile b/tests/gmii_phy/Makefile index ffa7dbd..eef6784 100644 --- a/tests/gmii_phy/Makefile +++ b/tests/gmii_phy/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_gmii_phy -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/gmii_phy/test_gmii_phy.py b/tests/gmii_phy/test_gmii_phy.py index f622d43..9b0885e 100644 --- a/tests/gmii_phy/test_gmii_phy.py +++ b/tests/gmii_phy/test_gmii_phy.py @@ -140,7 +140,7 @@ def cycle_en(): return itertools.cycle([0, 0, 0, 1]) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: for test in [run_test_tx, run_test_rx]: diff --git a/tests/mii/Makefile b/tests/mii/Makefile index 69f0799..fec130b 100644 --- a/tests/mii/Makefile +++ b/tests/mii/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_mii -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/mii/test_mii.py b/tests/mii/test_mii.py index ddb77ae..ada3b04 100644 --- a/tests/mii/test_mii.py +++ b/tests/mii/test_mii.py @@ -130,7 +130,7 @@ def cycle_en(): return itertools.cycle([0, 0, 0, 1]) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: factory = TestFactory(run_test) factory.add_option("payload_lengths", [size_list]) diff --git a/tests/mii_phy/Makefile b/tests/mii_phy/Makefile index 1301d98..9b0c907 100644 --- a/tests/mii_phy/Makefile +++ b/tests/mii_phy/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_mii_phy -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/mii_phy/test_mii_phy.py b/tests/mii_phy/test_mii_phy.py index b363833..0a465ce 100644 --- a/tests/mii_phy/test_mii_phy.py +++ b/tests/mii_phy/test_mii_phy.py @@ -131,7 +131,7 @@ def cycle_en(): return itertools.cycle([0, 0, 0, 1]) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: for test in [run_test_tx, run_test_rx]: diff --git a/tests/ptp_clock/Makefile b/tests/ptp_clock/Makefile index d757424..869bebe 100644 --- a/tests/ptp_clock/Makefile +++ b/tests/ptp_clock/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps DUT = test_ptp_clock -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/ptp_clock/test_ptp_clock.py b/tests/ptp_clock/test_ptp_clock.py index 6bdb3e6..b66521a 100644 --- a/tests/ptp_clock/test_ptp_clock.py +++ b/tests/ptp_clock/test_ptp_clock.py @@ -68,11 +68,11 @@ class TB: await RisingEdge(self.dut.clk) def get_ts_tod_ns(self): - ts = self.dut.ts_tod.value.integer + ts = int(self.dut.ts_tod.value) return Decimal(ts >> 48).scaleb(9) + (Decimal(ts & 0xffffffffffff) / Decimal(2**16)) def get_ts_rel_ns(self): - ts = self.dut.ts_rel.value.integer + ts = int(self.dut.ts_rel.value) return Decimal(ts) / Decimal(2**16) @@ -127,9 +127,9 @@ async def run_load_timestamps(dut): await RisingEdge(dut.clk) - assert dut.ts_tod.value.integer == (12345678 << 16) + (tb.ptp_clock.period_ns << 16) + (tb.ptp_clock.period_fns >> 16) - assert dut.ts_rel.value.integer == (12345678 << 16) + (tb.ptp_clock.period_ns << 16) + (tb.ptp_clock.period_fns >> 16) - assert dut.ts_step.value.integer == 1 + assert int(dut.ts_tod.value) == (12345678 << 16) + (tb.ptp_clock.period_ns << 16) + (tb.ptp_clock.period_fns >> 16) + assert int(dut.ts_rel.value) == (12345678 << 16) + (tb.ptp_clock.period_ns << 16) + (tb.ptp_clock.period_fns >> 16) + assert int(dut.ts_step.value) == 1 start_time = Decimal(get_sim_time('fs')).scaleb(-6) start_ts_tod = tb.get_ts_tod_ns() @@ -184,10 +184,10 @@ async def run_seconds_increment(dut): for k in range(3000): await RisingEdge(dut.clk) - if dut.pps.value.integer: + if int(dut.pps.value): saw_pps = True - assert dut.ts_tod.value.integer >> 48 == 1 - assert dut.ts_tod.value.integer & 0xffffffffffff < 10*2**16 + assert int(dut.ts_tod.value) >> 48 == 1 + assert int(dut.ts_tod.value) & 0xffffffffffff < 10*2**16 assert saw_pps diff --git a/tests/ptp_clock_sim_time/Makefile b/tests/ptp_clock_sim_time/Makefile index 1b239e5..01964ce 100644 --- a/tests/ptp_clock_sim_time/Makefile +++ b/tests/ptp_clock_sim_time/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps DUT = test_ptp_clock_sim_time -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/ptp_clock_sim_time/test_ptp_clock_sim_time.py b/tests/ptp_clock_sim_time/test_ptp_clock_sim_time.py index b8f20a1..c033121 100644 --- a/tests/ptp_clock_sim_time/test_ptp_clock_sim_time.py +++ b/tests/ptp_clock_sim_time/test_ptp_clock_sim_time.py @@ -54,11 +54,11 @@ class TB: ) def get_ts_tod_ns(self): - ts = self.dut.ts_tod.value.integer + ts = int(self.dut.ts_tod.value) return Decimal(ts >> 48).scaleb(9) + (Decimal(ts & 0xffffffffffff) / Decimal(2**16)) def get_ts_rel_ns(self): - ts = self.dut.ts_rel.value.integer + ts = int(self.dut.ts_rel.value) return Decimal(ts) / Decimal(2**16) diff --git a/tests/rgmii/Makefile b/tests/rgmii/Makefile index 4327011..30eda11 100644 --- a/tests/rgmii/Makefile +++ b/tests/rgmii/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_rgmii -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/rgmii/test_rgmii.py b/tests/rgmii/test_rgmii.py index 9ece403..409a4d0 100644 --- a/tests/rgmii/test_rgmii.py +++ b/tests/rgmii/test_rgmii.py @@ -130,7 +130,7 @@ def cycle_en(): return itertools.cycle([0, 0, 0, 1]) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: factory = TestFactory(run_test) factory.add_option("payload_lengths", [size_list]) diff --git a/tests/rgmii_phy/Makefile b/tests/rgmii_phy/Makefile index 7b57c45..a3e3735 100644 --- a/tests/rgmii_phy/Makefile +++ b/tests/rgmii_phy/Makefile @@ -27,39 +27,23 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_rgmii_phy -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/rgmii_phy/test_rgmii_phy.py b/tests/rgmii_phy/test_rgmii_phy.py index 62b2d3a..ba9df82 100644 --- a/tests/rgmii_phy/test_rgmii_phy.py +++ b/tests/rgmii_phy/test_rgmii_phy.py @@ -144,7 +144,7 @@ def cycle_en(): return itertools.cycle([0, 0, 0, 1]) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: for test in [run_test_tx, run_test_rx]: diff --git a/tests/xgmii/Makefile b/tests/xgmii/Makefile index e4dd131..d90edc3 100644 --- a/tests/xgmii/Makefile +++ b/tests/xgmii/Makefile @@ -27,8 +27,10 @@ COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns DUT = test_xgmii -TOPLEVEL = $(DUT) -MODULE = $(DUT) +COCOTB_TEST_MODULES = $(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(DUT).v # module parameters @@ -38,32 +40,14 @@ export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 endif endif -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tests/xgmii/test_xgmii.py b/tests/xgmii/test_xgmii.py index 5b3eeb6..857fd25 100644 --- a/tests/xgmii/test_xgmii.py +++ b/tests/xgmii/test_xgmii.py @@ -208,7 +208,7 @@ def cycle_en(): return itertools.cycle([0, 0, 0, 1]) -if cocotb.SIM_NAME: +if getattr(cocotb, 'top', None) is not None: factory = TestFactory(run_test) factory.add_option("payload_lengths", [size_list])