Initial commit

tests/xgmii/test_xgmii.py

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+#!/usr/bin/env python
+"""
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+import itertools
+import os
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        cocotb.fork(Clock(dut.clk, 2, units="ns").start())
+
+        self.source = XgmiiSource(dut, "xgmii", dut.clk, dut.rst)
+        self.sink = XgmiiSink(dut, "xgmii", dut.clk, dut.rst)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst <= 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst <= 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True, force_offset_start=False):
+
+    tb = TB(dut)
+
+    byte_width = tb.source.width // 8
+
+    tb.source.ifg = ifg
+    tb.source.enable_dic = enable_dic
+    tb.source.force_offset_start = force_offset_start
+
+    await tb.reset()
+
+    test_frames = [payload_data(l) for l in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data)
+        tb.source.send(test_frame)
+
+    for test_data in test_frames:
+        await tb.sink.wait()
+        rx_frame = tb.sink.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True, force_offset_start=False):
+
+    tb = TB(dut)
+
+    byte_width = tb.source.width // 8
+
+    tb.source.ifg = ifg
+    tb.source.enable_dic = enable_dic
+    tb.source.force_offset_start = force_offset_start
+
+    await tb.reset()
+
+    for length in range(64, 96):
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            test_frame = XgmiiFrame.from_payload(test_data)
+            tb.source.send(test_frame)
+
+        for test_data in test_frames:
+            await tb.sink.wait()
+            rx_frame = tb.sink.recv()
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.ctrl is None
+
+            start_lane.append(rx_frame.rx_start_lane)
+
+        print(length)
+        print(start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+            if force_offset_start and byte_width > 4:
+                lane = 4
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+ifg) % byte_width
+
+            if enable_dic:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        print(start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        for k in range(10):
+            await RisingEdge(dut.clk)
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+def size_list():
+    return list(range(64, 128))+[512, 1514, 9214]+[64]*10+[65]*10+[66]*10+[67]*10
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12, 0])
+    factory.add_option("enable_dic", [True, False])
+    factory.add_option("force_offset_start", [False, True])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12, 0])
+    factory.add_option("enable_dic", [True, False])
+    factory.add_option("force_offset_start", [False, True])
+    factory.generate_tests()
+
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+@pytest.mark.parametrize("data_width", [32, 64])
+def test_xgmii(request, data_width):
+    dut = "test_xgmii"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{dut}.v"),
+    ]
+
+    parameters = {}
+
+    parameters['DATA_WIDTH'] = data_width
+    parameters['CTRL_WIDTH'] = parameters['DATA_WIDTH'] // 8
+
+    extra_env = {f'PARAM_{k}' : str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir,
+        "sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )
+