Get sim working, make some changes to the final addition
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@@ -3,6 +3,7 @@ module chacha20_block #(
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parameter COUNTER_SIZE = 64,
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parameter NONCE_SIZE = 64,
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parameter STATE_SIZE = 512,
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parameter ROUNDS = 20,
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parameter CONSTANT = 128'h657870616e642033322d62797465206b
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)(
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input logic i_clk,
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@@ -41,16 +42,19 @@ chacha20_qr u_chacha20_``name ( \
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)
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logic [31:0] state [21][16];
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logic [3:0] valid[21];
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logic [31:0] state [ROUNDS+1][16];
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logic [3:0] valid[ROUNDS+1];
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// logic [3:0] ready[21];
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// small fifo for storing the initial state.
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// better to store it in a memory than in flops
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logic [4:0] initial_state_wptr;
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logic [4:0] initial_state_rptr;
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logic [511:0] initial_states [20];
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logic [$clog2(ROUNDS)-1:0] initial_state_wptr;
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logic [$clog2(ROUNDS)-1:0] initial_state_rptr;
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logic [511:0] initial_states [ROUNDS];
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logic [511:0] state_pre_add;
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logic pre_add_valid;
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logic [511:0] write_initial_state, read_initial_state;
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@@ -65,14 +69,23 @@ always_ff @(posedge i_clk) begin
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initial_states[initial_state_wptr] <= write_initial_state;
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end
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if (valid[19][0]) begin
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pre_add_valid <= valid[ROUNDS][0];
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if (valid[ROUNDS][0]) begin
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read_initial_state <= initial_states[initial_state_rptr];
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for (int i = 0; i < 16; i++) begin
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state_pre_add[i*32 +: 32] <= state[ROUNDS][i];
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end
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end
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o_valid <= &valid[20];
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o_valid <= pre_add_valid;
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// We cannot just add state_pre_add and read_initial state
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// because the addition needs to be done wordwise, with no
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// carries between 32 bit groups.
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for (int i = 0; i < 16; i++) begin
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o_state[i*32 +: 32] <= state[20][i] + read_initial_state[i*32 +: 32];
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o_state[i*32 +: 32] <= state_pre_add[i*32 +: 32] + read_initial_state[i*32 +: 32];
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end
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end
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@@ -111,7 +124,7 @@ end
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generate
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for (genvar round = 0; round < 20; round+=2) begin : ROUND_LOOP
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for (genvar round = 0; round < ROUNDS; round+=2) begin : ROUND_LOOP
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`QR(0, round, 0, 0, 4, 8, 12);
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`QR(1, round, 1, 1, 5, 9, 13);
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`QR(2, round, 2, 2, 6, 10, 14);
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