Fix bug where top 2 bits were getting lost in the modulo

2025-10-30 22:34:52 -07:00
parent d6a062baa0
commit 2102cb41f4
4 changed files with 46 additions and 24 deletions
--- a/ChaCha20_Poly1305_64/sim/poly1305_friendly_modular_mult.py
+++ b/ChaCha20_Poly1305_64/sim/poly1305_friendly_modular_mult.py
@@ -78,7 +78,7 @@ async def test_sanity(dut):

    await tb.cycle_reset()

-    count = 16
+    count = 1024

    for _ in range(count):
        await tb.write_input(random.randint(1,2**128-1), random.randint(0, 2**130-6))
@@ -93,6 +93,4 @@ async def test_sanity(dut):
            tb.log.info(f"{sim_val:x} -> {dut_val:x}")
            fail = True

-    # assert not fail
-
-    await Timer(1, "us")
+    assert not fail