Fix bug where top 2 bits were getting lost in the modulo

2025-10-30 22:34:52 -07:00
parent d6a062baa0
commit 2102cb41f4
4 changed files with 46 additions and 24 deletions
--- a/ChaCha20_Poly1305_64/sim/poly1305_friendly_modulo.py
+++ b/ChaCha20_Poly1305_64/sim/poly1305_friendly_modulo.py
@@ -88,4 +88,23 @@ async def test_sanity(dut):
            tb.log.info(f"{sim_val:x} -> {dut_val:x}")
            fail = True

+    assert not fail
+
+@cocotb.test
+async def test_directed(dut):
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    await tb.write_input(0x14C0D69391E7116E057E7AD833B00B706AA2390C, 4)
+
+    fail = False
+
+    sim_val = await tb.expected_queue.get()
+    dut_val = await tb.output_queue.get()
+
+    if sim_val != dut_val:
+        tb.log.info(f"{sim_val:x} -> {dut_val:x}")
+        fail = True
+
    assert not fail