diff --git a/ChaCha20_Poly1305_64/poly1305_timing_test/poly1305_timing_test.peri.xml b/ChaCha20_Poly1305_64/poly1305_timing_test/poly1305_timing_test.peri.xml
new file mode 100644
index 0000000..e86e1b3
--- /dev/null
+++ b/ChaCha20_Poly1305_64/poly1305_timing_test/poly1305_timing_test.peri.xml
@@ -0,0 +1,122 @@
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diff --git a/ChaCha20_Poly1305_64/poly1305_timing_test/poly1305_timing_test.xml b/ChaCha20_Poly1305_64/poly1305_timing_test/poly1305_timing_test.xml
new file mode 100644
index 0000000..628ee0a
--- /dev/null
+++ b/ChaCha20_Poly1305_64/poly1305_timing_test/poly1305_timing_test.xml
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diff --git a/ChaCha20_Poly1305_64/sim/poly1305.yaml b/ChaCha20_Poly1305_64/sim/poly1305.yaml
index 152650d..481c07e 100644
--- a/ChaCha20_Poly1305_64/sim/poly1305.yaml
+++ b/ChaCha20_Poly1305_64/sim/poly1305.yaml
@@ -1,6 +1,6 @@
tests:
- name: "poly1305_core"
- toplevel: "poly1305_core_harness"
+ toplevel: "poly1305_core_wrapper"
modules:
- "poly1305_core"
sources: "sources.list"
diff --git a/ChaCha20_Poly1305_64/sim/poly1305_core.py b/ChaCha20_Poly1305_64/sim/poly1305_core.py
index b625502..b339085 100644
--- a/ChaCha20_Poly1305_64/sim/poly1305_core.py
+++ b/ChaCha20_Poly1305_64/sim/poly1305_core.py
@@ -20,7 +20,7 @@ class TB:
cocotb.start_soon(Clock(self.dut.i_clk, CLK_PERIOD, units="ns").start())
- self.s_data_axis = AxiStreamSource(AxiStreamBus.from_prefix(dut.s_data_axis, ""), dut.i_clk, dut.i_rst)
+ self.s_data_axis = AxiStreamSource(AxiStreamBus.from_prefix(dut, ""), dut.i_clk, dut.i_rst)
async def cycle_reset(self):
await self._cycle_reset(self.dut.i_rst, self.dut.i_clk)
diff --git a/ChaCha20_Poly1305_64/sim/poly1305_core_harness.sv b/ChaCha20_Poly1305_64/sim/poly1305_core_harness.sv
deleted file mode 100644
index df3f425..0000000
--- a/ChaCha20_Poly1305_64/sim/poly1305_core_harness.sv
+++ /dev/null
@@ -1,26 +0,0 @@
-module poly1305_core_harness();
-
-taxi_axis_if #(.DATA_W(128)) s_data_axis();
-
-logic i_clk;
-logic i_rst;
-
-logic [255:0] i_otk;
-logic i_otk_valid;
-
-logic [127:0] o_tag;
-logic o_tag_valid;
-
-poly1305_core u_dut (
- .i_clk (i_clk),
- .i_rst (i_rst),
- .i_otk (i_otk),
- .i_otk_valid (i_otk_valid),
-
- .o_tag (o_tag),
- .o_tag_valid (o_tag_valid),
-
- .s_data_axis (s_data_axis)
-);
-
-endmodule
\ No newline at end of file
diff --git a/ChaCha20_Poly1305_64/sim/poly1305_core_wrapper.sv b/ChaCha20_Poly1305_64/sim/poly1305_core_wrapper.sv
new file mode 100644
index 0000000..9554858
--- /dev/null
+++ b/ChaCha20_Poly1305_64/sim/poly1305_core_wrapper.sv
@@ -0,0 +1,40 @@
+module poly1305_core_wrapper(
+ input i_clk,
+ input i_rst,
+
+ input [255:0] i_otk,
+ input i_otk_valid,
+
+ output [127:0] o_tag,
+ output o_tag_valid,
+
+ input [127:0] tdata,
+ input [15:0] tkeep,
+ input [15:0] tstrb,
+ input tlast,
+ input tvalid,
+ output tready
+);
+
+taxi_axis_if #(.DATA_W(128)) s_data_axis();
+
+assign s_data_axis.tdata = tdata;
+assign s_data_axis.tkeep = tkeep;
+assign s_data_axis.tstrb = tstrb;
+assign s_data_axis.tlast = tlast;
+assign s_data_axis.tvalid = tvalid;
+assign tready = s_data_axis.tready;
+
+poly1305_core u_dut (
+ .i_clk (i_clk),
+ .i_rst (i_rst),
+ .i_otk (i_otk),
+ .i_otk_valid (i_otk_valid),
+
+ .o_tag (o_tag),
+ .o_tag_valid (o_tag_valid),
+
+ .s_data_axis (s_data_axis)
+);
+
+endmodule
\ No newline at end of file
diff --git a/ChaCha20_Poly1305_64/sim/sources.list b/ChaCha20_Poly1305_64/sim/sources.list
index 1797a9a..971f6b1 100644
--- a/ChaCha20_Poly1305_64/sim/sources.list
+++ b/ChaCha20_Poly1305_64/sim/sources.list
@@ -1,4 +1,4 @@
-poly1305_core_harness.sv
+poly1305_core_wrapper.sv
../src/sources.list
../../common/sim/sub/taxi/src/axis/rtl/taxi_axis_if.sv