From 2b8286d180f9764dd458d6ff4694571e96f5687c Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Wed, 2 Jul 2025 10:08:25 -0700
Subject: [PATCH] Change target clock to 400MHz

---
 .../chacha20_timing_test/chacha20_timing_test.xml          | 7 ++++---
 ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc  | 2 +-
 ChaCha20_Poly1305_64/doc/notes.md                          | 6 +++++-
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml
index 30e411e..9277d8b 100644
--- a/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml
+++ b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml
@@ -1,14 +1,15 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="chacha20_timing_test" description="" last_change="1751223371" sw_version="2025.1.110" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="chacha20_timing_test" description="" last_change="1751475390" sw_version="2025.1.110" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Titanium"/>
         <efx:device name="Ti375N1156"/>
         <efx:timing_model name="C4"/>
     </efx:device_info>
     <efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008" unified_flow="false">
-        <efx:top_module name="chacha20_block"/>
+        <efx:top_module name="chacha20_pipelined_block"/>
+        <efx:design_file name="../src/chacha20_pipelined_block.sv" version="default" library="default"/>
+        <efx:design_file name="../src/chacha20_pipelined_round.sv" version="default" library="default"/>
         <efx:design_file name="../src/chacha20_qr.sv" version="default" library="default"/>
-        <efx:design_file name="../src/chacha20_block.sv" version="default" library="default"/>
         <efx:top_vhdl_arch name=""/>
     </efx:design_info>
     <efx:constraint_info>
diff --git a/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc b/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc
index 3d478ee..392311c 100644
--- a/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc
+++ b/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc
@@ -1 +1 @@
-create_clock -period 4.0 -name clk [get_ports i_clk]
\ No newline at end of file
+create_clock -period 2.5 -name clk [get_ports i_clk]
\ No newline at end of file
diff --git a/ChaCha20_Poly1305_64/doc/notes.md b/ChaCha20_Poly1305_64/doc/notes.md
index 47e7a49..820b30a 100644
--- a/ChaCha20_Poly1305_64/doc/notes.md
+++ b/ChaCha20_Poly1305_64/doc/notes.md
@@ -101,4 +101,8 @@ Lets just leave it for now even if its overkill. The hardware would support up t
 we designed a custom board for it (or 120 if we used FMC connectors).
 
 If we only use a single quarter round multiplexed between all 4, then the same
-quarter round module can have 2 different blocks going through it at once.
\ No newline at end of file
+quarter round module can have 2 different blocks going through it at once.
+
+The new one multiplexes 4 quarter rounds between 1 QR module which reduces the
+logic usage down to only 46k le, of which the vast majority is flops (2k ff per round,
+0.5k lut)
\ No newline at end of file