From 8136a7526b277f1e2f6aaaed33fc4c2b1efaf961 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sat, 28 Jun 2025 15:48:14 -0700 Subject: [PATCH] Add basic repo --- .gitignore | 10 + .../chacha20_timing_test.peri.xml | 122 ++++++ .../chacha20_timing_test.sv | 75 ++++ .../chacha20_timing_test.xml | 107 +++++ .../chacha20_timing_test/constraints.sdc | 1 + ChaCha20_Poly1305_64/doc/chacha20.drawio | 388 ++++++++++++++++++ ChaCha20_Poly1305_64/doc/chacha20.drawio.png | Bin 0 -> 39010 bytes ChaCha20_Poly1305_64/doc/notes.md | 68 +++ .../chacha20_block.cpython-311.pyc | Bin 0 -> 1200 bytes .../chacha20_block.cpython-313.pyc | Bin 0 -> 1421 bytes ChaCha20_Poly1305_64/sim/chacha20.yaml | 6 + ChaCha20_Poly1305_64/sim/chacha20_block.py | 21 + ChaCha20_Poly1305_64/sim/results.xml | 8 + ChaCha20_Poly1305_64/sim/sources.list | 1 + ChaCha20_Poly1305_64/src/chacha20_block.sv | 128 ++++++ ChaCha20_Poly1305_64/src/chacha20_qr.sv | 96 +++++ ChaCha20_Poly1305_64/src/sources.list | 2 + constant.txt | 1 + init_env.sh | 11 + requirements.txt | 5 + test.log | 19 + 21 files changed, 1069 insertions(+) create mode 100644 .gitignore create mode 100644 ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.peri.xml create mode 100644 ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.sv create mode 100644 ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml create mode 100644 ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc create mode 100644 ChaCha20_Poly1305_64/doc/chacha20.drawio create mode 100644 ChaCha20_Poly1305_64/doc/chacha20.drawio.png create mode 100644 ChaCha20_Poly1305_64/sim/__pycache__/chacha20_block.cpython-311.pyc create mode 100644 ChaCha20_Poly1305_64/sim/__pycache__/chacha20_block.cpython-313.pyc create mode 100644 ChaCha20_Poly1305_64/sim/chacha20.yaml create mode 100644 ChaCha20_Poly1305_64/sim/chacha20_block.py create mode 100644 ChaCha20_Poly1305_64/sim/results.xml create mode 100644 ChaCha20_Poly1305_64/sim/sources.list create mode 100644 ChaCha20_Poly1305_64/src/chacha20_block.sv create mode 100644 ChaCha20_Poly1305_64/src/chacha20_qr.sv create mode 100644 ChaCha20_Poly1305_64/src/sources.list create mode 100644 constant.txt create mode 100644 init_env.sh create mode 100644 requirements.txt create mode 100644 test.log diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e1d6797 --- /dev/null +++ b/.gitignore @@ -0,0 +1,10 @@ +.venv +sim_build + +*.bkp + +outflow +work_pnr +work_pt +work_syn +.lock \ No newline at end of file diff --git a/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.peri.xml b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.peri.xml new file mode 100644 index 0000000..425dc88 --- /dev/null +++ b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.peri.xml @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.sv b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.sv new file mode 100644 index 0000000..fba76a1 --- /dev/null +++ b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.sv @@ -0,0 +1,75 @@ +// do an entire round combinationally + +`define ROTL(x, n) {x[31-n:0], x[31:32-n]} + + +module chacha20_qr #( + parameter PIPELINE_STAGES=7 +)( + input i_clk, + input i_rst, + + input i_valid, + output o_ready, + input logic [31:0] a_i, b_i, c_i, d_i, + + output o_valid, + input i_ready, + output logic [31:0] a_o, b_o, c_o, d_o +); + + + +logic [31:0] a_int [7]; +logic [31:0] b_int [7]; +logic [31:0] c_int [7]; +logic [31:0] d_int [7]; + +logic [6:0] valid_sr; + +// There is an output stage which handles isolating backpressure from the rest +// of the design from the core, so we don't need to worry about it here, we can +// have a single signal gate all of this. +assign o_ready = i_ready; + + +always_ff @(posedge i_clk) begin + if (i_rst) begin + valid_sr <= '0; + end else begin + if (i_ready) begin + // 1. Update A + a_int[0] <= a_i + b_i; + b_int[0] <= b_i; + c_int[0] <= c_i; + d_int[0] <= d_i; + + // 2. Update D + a_int[1] <= a_int[0]; + b_int[1] <= b_int[0]; + c_int[1] <= c_int[0]; + d_int[1] <= `ROTL(a_int[0] ^ d_int[0], 16); + + end + end +end + +endmodule + + +// always_comb begin +// a_int_0 = a_i + b_i; +// d_int_0 = a_int_0 ^ d_i; +// d_int_1 = `ROTL(d_int_0, 16); +// c_int_0 = c_i + d_int_1; +// b_int_0 = c_int_0 ^ b_i; +// b_int_1 = `ROTL(b_int_0, 12); +// a_o = a_int_0 + b_int_1; +// d_int_2 = d_int_1 ^ a_o; +// d_o = `ROTL(d_int_2, 8); +// c_o = c_int_0 + d_o; +// b_int_2 = b_int_1 ^ c_o; +// b_o = `ROTL(b_int_2, 7); +// end + +// endmodule diff --git a/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml new file mode 100644 index 0000000..545d6ef --- /dev/null +++ b/ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml @@ -0,0 +1,107 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc b/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc new file mode 100644 index 0000000..75108bb --- /dev/null +++ b/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc @@ -0,0 +1 @@ +create_clock -period 5.0 -name clk [get_ports i_clk] \ No newline at end of file diff --git a/ChaCha20_Poly1305_64/doc/chacha20.drawio b/ChaCha20_Poly1305_64/doc/chacha20.drawio new file mode 100644 index 0000000..89dfb45 --- /dev/null +++ b/ChaCha20_Poly1305_64/doc/chacha20.drawio @@ -0,0 +1,388 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0000000..2ccb74e --- /dev/null +++ b/ChaCha20_Poly1305_64/sim/chacha20_block.py @@ -0,0 +1,21 @@ +import cocotb + + +from cocotb.clock import Clock +from cocotb.triggers import Timer, RisingEdge, FallingEdge + +CLK_PERIOD = 4 + + +class TB: + def __init__(self, dut): + self.dut = dut + + cocotb.start_soon(Clock(self.dut.i_clk, CLK_PERIOD, units="ns").start()) + +@cocotb.test +async def test_sanity(dut): + tb = TB(dut) + + await RisingEdge(tb.dut.i_clk) + await RisingEdge(tb.dut.i_clk) diff --git a/ChaCha20_Poly1305_64/sim/results.xml b/ChaCha20_Poly1305_64/sim/results.xml new file mode 100644 index 0000000..62491df --- /dev/null +++ b/ChaCha20_Poly1305_64/sim/results.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/ChaCha20_Poly1305_64/sim/sources.list b/ChaCha20_Poly1305_64/sim/sources.list new file mode 100644 index 0000000..9517c7f --- /dev/null +++ b/ChaCha20_Poly1305_64/sim/sources.list @@ -0,0 +1 @@ +../src/sources.list \ No newline at end of file diff --git a/ChaCha20_Poly1305_64/src/chacha20_block.sv b/ChaCha20_Poly1305_64/src/chacha20_block.sv new file mode 100644 index 0000000..6fbc681 --- /dev/null +++ b/ChaCha20_Poly1305_64/src/chacha20_block.sv @@ -0,0 +1,128 @@ +module chacha20_block #( + parameter KEY_SIZE = 256, + parameter COUNTER_SIZE = 64, + parameter NONCE_SIZE = 64, + parameter STATE_SIZE = 512, + parameter CONSTANT = 128'h657870616e642033322d62797465206b +)( + input logic i_clk, + input logic i_rst, + + input logic [KEY_SIZE-1:0] i_key, + input logic [COUNTER_SIZE-1:0] i_counter, + input logic [NONCE_SIZE-1:0] i_nonce, + input logic i_valid, + output logic o_ready, + + + output logic [STATE_SIZE-1:0] o_state, + output logic o_valid, + input logic i_ready +); + +`define QR(name, i, n, a, b, c, d) \ +chacha20_qr u_chacha20_``name ( \ + .i_clk (i_clk), \ + .i_rst (i_rst), \ + \ + .i_valid (valid[i][n]), \ + .o_ready (), \ + .a_i (state[i][a]), \ + .b_i (state[i][b]), \ + .c_i (state[i][c]), \ + .d_i (state[i][d]), \ + \ + .o_valid (valid[i+1][n]), \ + .i_ready (i_ready), \ + .a_o (state[i+1][a]), \ + .b_o (state[i+1][b]), \ + .c_o (state[i+1][c]), \ + .d_o (state[i+1][d]) \ +) + + +logic [31:0] state [21][16]; +logic [3:0] valid[21]; +// logic [3:0] ready[21]; + + +// small fifo for storing the initial state. +// better to store it in a memory than in flops +logic [4:0] initial_state_wptr; +logic [4:0] initial_state_rptr; +logic [511:0] initial_states [20]; + +logic [511:0] write_initial_state, read_initial_state; + +logic [31:0] original_initial_state [16]; + +always_ff @(posedge i_clk) begin + if (i_rst) begin + initial_state_rptr <= '0; + initial_state_wptr <= '0; + end else begin + if (i_valid) begin + initial_states[initial_state_wptr] <= write_initial_state; + end + + if (valid[19][0]) begin + read_initial_state <= initial_states[initial_state_rptr]; + end + + + o_valid <= &valid[20]; + for (int i = 0; i < 16; i++) begin + o_state[i*32 +: 32] <= state[20][i] + read_initial_state[i*32 +: 32]; + end + end + +end + + +always_comb begin + for (int i = 0; i < 4; i++) begin + state[0][i] = CONSTANT[32*(3-i) +: 32]; // constant is big endian + end + + for (int i = 0; i < 8; i++) begin + state[0][i+4] = i_key[32*i +: 32]; + end + + state[0][12] = i_counter[0 +: 32]; + state[0][13] = i_counter[32 +: 32]; + + state[0][14] = i_nonce[0 +: 32]; + state[0][15] = i_nonce[32 +: 32]; + + + for (int i = 0; i < 4; i++) begin + valid[0][i] = i_valid; + end + + o_ready = i_ready; + + + for (int i = 0; i < 16; i++) begin + write_initial_state[i*32 +: 32] = state[0][i]; + + original_initial_state[i] = read_initial_state[i*32 +: 32]; + end +end + + +generate + for (genvar round = 0; round < 20; round+=2) begin : ROUND_LOOP + `QR(0, round, 0, 0, 4, 8, 12); + `QR(1, round, 1, 1, 5, 9, 13); + `QR(2, round, 2, 2, 6, 10, 14); + `QR(3, round, 3, 3, 7, 11, 15); + + `QR(4, round+1, 0, 0, 5, 10, 15); + `QR(5, round+1, 1, 1, 6, 11, 12); + `QR(6, round+1, 2, 2, 7, 8, 13); + `QR(7, round+1, 3, 3, 4, 9, 14); + end +endgenerate + + +endmodule \ No newline at end of file diff --git a/ChaCha20_Poly1305_64/src/chacha20_qr.sv b/ChaCha20_Poly1305_64/src/chacha20_qr.sv new file mode 100644 index 0000000..a4a6fc2 --- /dev/null +++ b/ChaCha20_Poly1305_64/src/chacha20_qr.sv @@ -0,0 +1,96 @@ +// do an entire round combinationally + +`define ROTL(x, n) {x[31-n:0], x[31:32-n]} + + +module chacha20_qr #( + parameter PIPELINE_STAGES=7 +)( + input logic i_clk, + input logic i_rst, + + input logic i_valid, + output logic o_ready, + input logic [31:0] a_i, b_i, c_i, d_i, + + output logic o_valid, + input logic i_ready, + output logic [31:0] a_o, b_o, c_o, d_o +); + + + +logic [31:0] a_int [7]; +logic [31:0] b_int [7]; +logic [31:0] c_int [7]; +logic [31:0] d_int [7]; + +logic [6:0] valid_sr; + +// There is an output stage which handles isolating backpressure from the rest +// of the design from the core, so we don't need to worry about it here, we can +// have a single signal gate all of this. +assign o_ready = i_ready; + + +always_ff @(posedge i_clk) begin + if (i_rst) begin + valid_sr <= '0; + end else begin + if (i_ready) begin + // 1. Update A + a_int[0] <= a_i + b_i; + b_int[0] <= b_i; + c_int[0] <= c_i; + d_int[0] <= d_i; + + // 2. Update D + a_int[1] <= a_int[0]; + b_int[1] <= b_int[0]; + c_int[1] <= c_int[0]; + d_int[1] <= `ROTL(a_int[0], 16) ^ `ROTL(d_int[0], 16); + + // 3. Update C + a_int[2] <= a_int[1]; + b_int[2] <= b_int[1]; + c_int[2] <= c_int[1] + d_int[1]; + d_int[2] <= d_int[1]; + + // 4. Update B + a_int[3] <= a_int[2]; + b_int[3] <= `ROTL(b_int[2], 12) ^ `ROTL(c_int[2], 12); + c_int[3] <= c_int[2]; + d_int[3] <= d_int[2]; + + // 5. Update A + a_int[4] <= a_int[3] + b_int[3]; + b_int[4] <= b_int[3]; + c_int[4] <= c_int[3]; + d_int[4] <= d_int[3]; + + // 6. Update D + a_int[5] <= a_int[4]; + b_int[5] <= b_int[4]; + c_int[5] <= c_int[4]; + d_int[5] <= `ROTL(a_int[4], 8) ^ `ROTL(d_int[4], 8); + + // 7. Update C + a_int[6] <= a_int[5]; + b_int[6] <= b_int[5]; + c_int[6] <= c_int[5] + d_int[5]; + d_int[6] <= d_int[5]; + + // 8. Update B + a_o <= a_int[6]; + b_o <= `ROTL(b_int[6], 7) ^ `ROTL(c_int[6], 7); + c_o <= c_int[6]; + d_o <= d_int[6]; + + // Simultaneously, update valid_sr; + valid_sr <= {valid_sr[5:0], i_valid}; + o_valid <= valid_sr[6]; + end + end +end + +endmodule diff --git a/ChaCha20_Poly1305_64/src/sources.list b/ChaCha20_Poly1305_64/src/sources.list new file mode 100644 index 0000000..9c60645 --- /dev/null +++ b/ChaCha20_Poly1305_64/src/sources.list @@ -0,0 +1,2 @@ +chacha20_qr.sv +chacha20_block.sv \ No newline at end of file diff --git a/constant.txt b/constant.txt new file mode 100644 index 0000000..b954fd7 --- /dev/null +++ b/constant.txt @@ -0,0 +1 @@ +expand 32-byte k diff --git a/init_env.sh b/init_env.sh new file mode 100644 index 0000000..b083139 --- /dev/null +++ b/init_env.sh @@ -0,0 +1,11 @@ +PYTHON=python3.13 + +module load verilator +module load efinity/2025.1 + +$PYTHON -m venv .venv/${HOSTNAME} +source .venv/${HOSTNAME}/bin/activate + +pip install -r requirements.txt + +export TOP_DIR=$(git rev-parse --show-toplevel) diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 0000000..2592f3a --- /dev/null +++ b/requirements.txt @@ -0,0 +1,5 @@ +build-fpga +fpga-sim>=0.3.1 +peakrdl +cocotb +cocotbext-axi \ No newline at end of file diff --git a/test.log b/test.log new file mode 100644 index 0000000..bda9449 --- /dev/null +++ b/test.log @@ -0,0 +1,19 @@ + -.--ns INFO gpi ..mbed/gpi_embed.cpp:108 in set_program_name_in_venv Using Python virtual environment interpreter at /home/byron/Projects/crypto/.venv/customer.sttlwax1.pop.starlinkisp.net/bin/python + -.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered + 0.00ns INFO cocotb Running on Verilator version 5.028 2024-08-21 + 0.00ns INFO cocotb Running tests with cocotb v1.9.2 from /home/byron/Projects/crypto/.venv/customer.sttlwax1.pop.starlinkisp.net/lib/python3.13/site-packages/cocotb + 0.00ns INFO cocotb Seeding Python random module with 1751043027 + 0.00ns INFO cocotb.regression pytest not found, install it to enable better AssertionError messages + 0.00ns INFO cocotb.regression Found test chacha20_block.test_sanity + 0.00ns INFO cocotb.regression running test_sanity (1/1) + 0.00ns ERROR cocotb.scheduler Failing test at simulator request before test run completion: Simulator shut down prematurely + 0.00ns ERROR cocotb.regression Test error has lead to simulator shutting us down + 0.00ns INFO cocotb.regression ************************************************************************************** + ** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) ** + ************************************************************************************** + ** chacha20_block.test_sanity FAIL 0.00 0.00 0.00 ** + ************************************************************************************** + ** TESTS=1 PASS=0 FAIL=1 SKIP=0 0.00 0.00 0.00 ** + ************************************************************************************** + +- :0: Verilog $finish