First shot at 1/4 version
This commit is contained in:
Byron Lathi
@@ -98,4 +98,7 @@ Actualyl its 88k luts... its 512ff * 4 * 20 = 40k ff
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Lets just leave it for now even if its overkill. The hardware would support up to
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40Gbps, and technically the FPGA has 16 lanes so could do 160Gbps in total, if
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we designed a custom board for it (or 120 if we used FMC connectors).
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we designed a custom board for it (or 120 if we used FMC connectors).
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If we only use a single quarter round multiplexed between all 4, then the same
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quarter round module can have 2 different blocks going through it at once.
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154
ChaCha20_Poly1305_64/doc/qr_pipelining.drawio
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154
ChaCha20_Poly1305_64/doc/qr_pipelining.drawio
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@@ -0,0 +1,154 @@
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<mxCell id="ZoMeok9N2fHc0OsoVYq9-35" value="<h1 style="margin-top: 0px;">State Blocks</h1><p>Each round shuffles the state, so we cannot simply pipeline the quarter roundds all the way through. Before each round, we must regroup all of the words int a single 512 bit state, then separate them again into the desired words to put into the quarter round. Even and odd rounds use different words, but every even round and every odd round is the same, so this can still be done in a for loop.</p><p>Odd loops would pass in [0,4,8,12], [1,5,9,13], [2,6,10,14], then [3,7,11,15]. This means that the output of the first clock cycle is the new [0,4,8,12], however the first cycle of the next even round needs [0, 5, 10, 15], meaning we need to wait until the 4th cycle of the previous round. This is done by writing them 1 at a time to the state_out register to their respective locations in the 512 bit register. Then, when all 512 bits are ready, it gets passed in one cycle to the next block, where it is then split up again.</p><p>As it only takes 4 cycles to to do a complete round, and the QR is 8 cycles deep, it will be possible to have multiple rounds in a quarter cycle simultaneously.&nbsp;</p>" style="text;html=1;whiteSpace=wrap;overflow=hidden;rounded=0;" vertex="1" parent="1">
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