First shot at 1/4 version
This commit is contained in:
Byron Lathi
137
ChaCha20_Poly1305_64/src/chacha20_pipelined_block.sv
Normal file
137
ChaCha20_Poly1305_64/src/chacha20_pipelined_block.sv
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@@ -0,0 +1,137 @@
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module chacha20_pipelined_block #(
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parameter KEY_SIZE = 256,
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parameter COUNTER_SIZE = 64,
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parameter NONCE_SIZE = 64,
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parameter STATE_SIZE = 512,
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parameter ROUNDS = 20,
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parameter CONSTANT = 128'h657870616e642033322d62797465206b
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)(
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input logic i_clk,
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input logic i_rst,
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input logic [KEY_SIZE-1:0] i_key,
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input logic [COUNTER_SIZE-1:0] i_counter,
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input logic [NONCE_SIZE-1:0] i_nonce,
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input logic i_valid,
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output logic o_ready,
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output logic [STATE_SIZE-1:0] o_state,
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output logic o_valid,
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input logic i_ready
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);
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// each round is 8 stages
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localparam PIPE_STAGES = ROUNDS * 8;
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logic [511:0] state [ROUNDS+1];
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logic valid[ROUNDS+1];
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logic ready[ROUNDS+1];
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// small fifo for storing the initial state.
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// better to store it in a memory than in flops
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logic [$clog2(PIPE_STAGES)-1:0] initial_state_wptr;
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logic [$clog2(PIPE_STAGES)-1:0] initial_state_rptr;
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logic [511:0] initial_states [PIPE_STAGES];
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logic [511:0] state_pre_add;
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logic pre_add_valid;
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logic [511:0] write_initial_state, read_initial_state;
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logic [511:0] original_initial_state;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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initial_state_rptr <= '0;
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initial_state_wptr <= '0;
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end else begin
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if (i_valid) begin
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initial_states[initial_state_wptr] <= write_initial_state;
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if (initial_state_wptr < PIPE_STAGES-1) begin
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initial_state_wptr <= initial_state_wptr + 1;
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end else begin
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initial_state_wptr <= '0;
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end
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end
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pre_add_valid <= valid[ROUNDS];
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if (valid[ROUNDS]) begin
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read_initial_state <= initial_states[initial_state_rptr];
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if (initial_state_rptr < PIPE_STAGES-1) begin
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initial_state_rptr <= initial_state_rptr + 1;
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end else begin
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initial_state_rptr <= '0;
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end
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state_pre_add <= state[ROUNDS];
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end
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o_valid <= pre_add_valid;
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// We cannot just add state_pre_add and read_initial state
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// because the addition needs to be done wordwise, with no
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// carries between 32 bit groups.
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for (int i = 0; i < 16; i++) begin
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o_state[i*32 +: 32] <= state_pre_add[i*32 +: 32] + read_initial_state[i*32 +: 32];
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end
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end
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end
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always_comb begin
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for (int i = 0; i < 4; i++) begin
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state[0][32*(3-i) +: 32] = CONSTANT[32*(3-i) +: 32]; // constant is big endian
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end
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for (int i = 0; i < 8; i++) begin
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state[0][32*(i+4) +: 32] = i_key[32*i +: 32];
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end
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state[0][12*32 +: 32] = i_counter[0 +: 32];
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state[0][13*32 +: 32] = i_counter[32 +: 32];
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state[0][14*32 +: 32] = i_nonce[0 +: 32];
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state[0][15*32 +: 32] = i_nonce[32 +: 32];
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valid[0] = i_valid;
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o_ready = ready[0];
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write_initial_state = state[0];
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original_initial_state = read_initial_state;
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end
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generate
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for (genvar round = 0; round < ROUNDS; round+=2) begin : ROUND_LOOP
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chacha20_pipelined_round #(.IS_EVEN(0)) chacha20_pipelined_round_inst_odd (
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.i_clk (i_clk),
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.i_rst (i_rst),
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.i_state (state[round]),
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.i_valid (valid[round]),
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.o_ready (ready[round]),
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.o_state (state[round+1]),
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.o_valid (valid[round+1]),
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.i_ready (ready[round+1])
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);
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chacha20_pipelined_round #(.IS_EVEN(1)) chacha20_pipelined_round_inst_even (
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.i_clk (i_clk),
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.i_rst (i_rst),
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.i_state (state[round+1]),
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.i_valid (valid[round+1]),
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.o_ready (ready[round+1]),
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.o_state (state[round+2]),
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.o_valid (valid[round+2]),
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.i_ready (ready[round+2])
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);
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end
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endgenerate
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endmodule
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219
ChaCha20_Poly1305_64/src/chacha20_pipelined_round.sv
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219
ChaCha20_Poly1305_64/src/chacha20_pipelined_round.sv
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@@ -0,0 +1,219 @@
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module chacha20_pipelined_round #(
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parameter IS_EVEN = 1,
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parameter KEY_SIZE = 256,
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parameter COUNTER_SIZE = 64,
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parameter NONCE_SIZE = 64,
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parameter STATE_SIZE = 512,
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parameter ROUNDS = 20,
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parameter CONSTANT = 128'h657870616e642033322d62797465206b
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)(
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input logic i_clk,
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input logic i_rst,
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input logic [STATE_SIZE-1:0] i_state,
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input logic i_valid,
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output logic o_ready,
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output logic [STATE_SIZE-1:0] o_state,
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output logic o_valid,
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input logic i_ready
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);
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logic [31:0] state_in [16];
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logic [31:0] state_out [16];
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logic [31:0] qr_a_i, qr_a_o;
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logic [31:0] qr_b_i, qr_b_o;
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logic [31:0] qr_c_i, qr_c_o;
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logic [31:0] qr_d_i, qr_d_o;
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logic qr_i_valid, qr_o_valid;
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logic qr_o_ready, qr_i_ready;
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// state is shared between the in fsm and the out fsm
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enum logic [1:0] {STATE_IN, STATE_SHIFT, STATE_OUT} in_fsm_state, out_fsm_state;
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logic [1:0] in_counter;
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logic [1:0] out_counter;
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`define QR_IN(a, b, c, d) \
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qr_a_i = state_in[a]; \
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qr_b_i = state_in[b]; \
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qr_c_i = state_in[c]; \
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qr_d_i = state_in[d]
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`define QR_OUT(a, b, c, d) \
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state_out[a] <= qr_a_o; \
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state_out[b] <= qr_b_o; \
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state_out[c] <= qr_c_o; \
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state_out[d] <= qr_d_o
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always_comb begin
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if (IS_EVEN) begin
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case (in_counter)
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0: begin
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`QR_IN(0, 5, 10, 15);
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end
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1: begin
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`QR_IN(1, 5, 9, 13);
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end
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2: begin
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`QR_IN(2, 6, 10, 14);
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end
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3: begin
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`QR_IN(3, 7, 11, 15);
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end
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endcase
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end else begin
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case (in_counter)
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0: begin
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`QR_IN(0, 4, 8, 12);
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end
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1: begin
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`QR_IN(1, 5, 9, 13);
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end
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2: begin
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`QR_IN(2, 6, 10, 14);
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end
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3: begin
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`QR_IN(3, 7, 11, 15);
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end
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endcase
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end
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for (int i = 0; i < 16; i++) begin
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o_state[32*i +: 32] = state_out[i];
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end
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end
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chacha20_qr u_chacha20_qr (
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.i_clk (i_clk),
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.i_rst (i_rst),
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.i_valid (qr_i_valid),
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.o_ready (qr_o_ready),
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.a_i (qr_a_i),
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.b_i (qr_b_i),
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.c_i (qr_c_i),
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.d_i (qr_d_i),
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.o_valid (qr_o_valid),
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.i_ready (qr_i_ready),
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.a_o (qr_a_o),
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.b_o (qr_b_o),
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.c_o (qr_c_o),
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.d_o (qr_d_o)
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);
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assign o_ready = in_fsm_state == STATE_IN;
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assign qr_i_valid = in_fsm_state == STATE_SHIFT;
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assign qr_i_ready = out_fsm_state == STATE_SHIFT;
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assign o_valid = out_fsm_state == STATE_OUT;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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in_fsm_state <= STATE_IN;
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out_fsm_state <= STATE_SHIFT;
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in_counter <= '0;
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out_counter <= '0;
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end else begin
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case (in_fsm_state)
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STATE_IN: begin
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if (i_valid) begin
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// Register incoming state as unpacked 32 bit words
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for (int i = 0; i < 16; i++) begin
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state_in[i] = i_state[32*i +: 32];
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end
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in_counter <= '0;
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in_fsm_state <= STATE_SHIFT;
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end
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end
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STATE_SHIFT: begin
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if (qr_o_ready) begin
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in_counter <= in_counter + 1;
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if (in_counter == 3) begin
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in_fsm_state <= STATE_IN;
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end
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end
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end
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default: begin
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in_fsm_state <= STATE_IN;
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end
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endcase
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case (out_fsm_state)
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STATE_SHIFT: begin
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if (qr_o_valid) begin
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if (IS_EVEN) begin
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case (out_counter)
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0: begin
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`QR_OUT(0, 5, 10, 15);
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end
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1: begin
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`QR_OUT(1, 6, 11, 12);
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end
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2: begin
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`QR_OUT(2, 7, 8, 13);
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end
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3: begin
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`QR_OUT(3, 4, 9, 14);
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end
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endcase
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end else begin
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case (out_counter)
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0: begin
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`QR_OUT(0, 4, 8, 12);
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end
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1: begin
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`QR_OUT(1, 5, 9, 13);
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end
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2: begin
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`QR_OUT(2, 6, 10, 14);
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end
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3: begin
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`QR_OUT(3, 7, 11, 15);
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end
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endcase
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end
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out_counter <= out_counter + 1;
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if (out_counter == 3) begin
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out_fsm_state <= STATE_OUT;
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end
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end
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end
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STATE_OUT: begin
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if (i_ready) begin
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out_fsm_state <= STATE_SHIFT;
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end
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end
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default: begin
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out_fsm_state <= STATE_SHIFT;
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end
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endcase
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end
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end
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endmodule
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@@ -1,2 +1,4 @@
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chacha20_qr.sv
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chacha20_block.sv
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chacha20_block.sv
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chacha20_pipelined_round.sv
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chacha20_pipelined_block.sv
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