Add new poly1305 stage

I highly doubt this will pass timing... need to make a test harness to synthesize

ChaCha20_Poly1305_64/doc/notes2.md

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+# Requirements
+
+* 2 Gbps operation
+* Handles both encrypt and decrypt
+
+At reasonable FPGA speed of 250MHz, 2 Gbps requires a minimum width of 8 bits.
+
+32 bits is a reasonable data width that would be common to see, and lets us
+have more breathing room while still maintaining line rate.
+
+Module inputs and outputs
+
+* clk
+* rst
+* data_in [31:0]
+* data_valid
+* data_ready
+* data_last
+* r [127:0]
+* s [127:0]
+* mac [127:0]
+* mac_valid
+
+There is no output backpressure. since the result is just a single 128 bit number,
+we don't need to have a ready signal. if you want to add backpressure, add a register
+slice on the output outside of this module.