Add poly1305 stage
This commit is contained in:
@@ -34,3 +34,33 @@ we need
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r\*r = r^2
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r\*r = r^2
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r\*r^2 = r^3 r^2\*r^2 = r^4
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r\*r^2 = r^3 r^2\*r^2 = r^4
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r^4\*r = r^5 r^2\*r^4 = r^6 r^3\*r^4 = r^7 r^4\*r^4 = r^8
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r^4\*r = r^5 r^2\*r^4 = r^6 r^3\*r^4 = r^7 r^4\*r^4 = r^8
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we can do all of these in parallel, so we 4 (n/2) multiply blocks that feed back
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on themselves, with some kind of FSM to control it. This can be done while another
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block is being hashed, but there will be a delay between when the key is ready from
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the chacha block and when the powers are ready, so there needs to be a fifo in between.
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Basically we have to wait until we see that the accumulator was written with our index.
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At reset though, the acumulator is unwritten? So we need to pretend that it was written
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Lets just write out what we want to happen:
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1. The index starts at 0. We accept new data, and send it through the pipeline
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2. We increment the index to 1.
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3. We accept new data and send it through the pipeline
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4. We increment the index to 2
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5. We need to wait until the index 0 is written before we can say we are ready
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6. If the index 1 is written then we still need to say we are ready though
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7. We can just use the 1 to indicate that is a valid write then?
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So in the shift register we just need to say whether it is a valid write or not,
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so always 1?
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But if we send in 0, then send in 1, then the current index will be 0
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and eventually the final index will always be 0. We need to store what
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the last written one is.
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We can just say the last written one was 2 I guess
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We also need an input that tells it to reset the accumulator
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59
ChaCha20_Poly1305_64/doc/poly1305_second_attempt.drawio
Normal file
59
ChaCha20_Poly1305_64/doc/poly1305_second_attempt.drawio
Normal file
@@ -0,0 +1,59 @@
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</mxGraphModel>
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</diagram>
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</mxfile>
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@@ -17,3 +17,9 @@ tests:
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- "poly1305_friendly_modular_mult"
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- "poly1305_friendly_modular_mult"
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sources: sources.list
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sources: sources.list
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waves: True
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waves: True
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- name: "poly1305_stage"
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toplevel: "poly1305_stage"
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modules:
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- "poly1305_stage"
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sources: sources.list
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waves: True
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@@ -78,7 +78,7 @@ async def test_sanity(dut):
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await tb.cycle_reset()
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await tb.cycle_reset()
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count = 1024
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count = 1
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for _ in range(count):
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for _ in range(count):
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await tb.write_input(random.randint(1,2**128-1), random.randint(0, 2**130-6))
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await tb.write_input(random.randint(1,2**128-1), random.randint(0, 2**130-6))
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110
ChaCha20_Poly1305_64/sim/poly1305_stage.py
Normal file
110
ChaCha20_Poly1305_64/sim/poly1305_stage.py
Normal file
@@ -0,0 +1,110 @@
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import logging
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import Timer, RisingEdge, FallingEdge
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from cocotb.queue import Queue
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from cocotbext.axi import AxiStreamBus, AxiStreamSource
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from modulo_theory import friendly_modular_mult
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import random
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PRIME = 2**130-5
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CLK_PERIOD = 4
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.INFO)
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self.input_queue = Queue()
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self.expected_queue = Queue()
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self.output_queue = Queue()
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cocotb.start_soon(Clock(self.dut.i_clk, CLK_PERIOD, units="ns").start())
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cocotb.start_soon(self.run_input())
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cocotb.start_soon(self.run_output())
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self.index = 0
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self.accumulators = [0, 0]
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async def cycle_reset(self):
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await self._cycle_reset(self.dut.i_rst, self.dut.i_clk)
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async def _cycle_reset(self, rst, clk):
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rst.setimmediatevalue(0)
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await RisingEdge(clk)
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await RisingEdge(clk)
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rst.value = 1
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await RisingEdge(clk)
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await RisingEdge(clk)
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rst.value = 0
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await RisingEdge(clk)
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await RisingEdge(clk)
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async def write_input(self, msg: int, r_power: int, clear_acc: int):
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await self.input_queue.put((msg, r_power, clear_acc))
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if clear_acc:
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expected_result = friendly_modular_mult((msg) % PRIME, r_power)
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else:
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expected_result = friendly_modular_mult((msg + self.accumulators[self.index]) % PRIME, r_power)
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self.accumulators[self.index] = expected_result
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await self.expected_queue.put(expected_result)
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self.index = 1 if self.index == 0 else 0
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async def run_input(self):
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while True:
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msg, r_power, clear_acc = await self.input_queue.get()
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self.dut.i_valid.value = 1
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self.dut.i_r_power.value = r_power
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self.dut.i_message.value = msg
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self.dut.i_clear_acc.value = clear_acc
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while True:
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await RisingEdge(self.dut.i_clk)
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if (self.dut.o_ready.value == 1):
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break
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self.dut.i_valid.value = 0
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self.dut.i_r_power.value = 0
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self.dut.i_message.value = 0
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self.dut.i_clear_acc.value = 0
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async def run_output(self):
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while True:
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await RisingEdge(self.dut.i_clk)
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if self.dut.o_valid.value:
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await self.output_queue.put(self.dut.o_result.value.integer)
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@cocotb.test
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async def test_sanity(dut):
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tb = TB(dut)
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await tb.cycle_reset()
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count = 1024
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for _ in range(count):
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clr = 1 if random.randint(0,10) == 0 else 0
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await tb.write_input(random.randint(1,2**128-1), random.randint(0, 2**130-6), clr)
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fail = False
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for _ in range(count):
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sim_val = await tb.expected_queue.get()
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dut_val = await tb.output_queue.get()
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if sim_val != dut_val:
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tb.log.info(f"{_} {sim_val:x} -> {dut_val:x}")
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fail = True
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assert not fail
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@@ -1,5 +1,5 @@
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module poly1305_friendly_modular_mult #(
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module poly1305_friendly_modular_mult #(
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parameter DATA_WIDTH = 131,
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parameter DATA_WIDTH = 130,
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parameter ACC_WIDTH = 130
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parameter ACC_WIDTH = 130
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) (
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) (
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input logic i_clk,
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input logic i_clk,
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@@ -54,7 +54,7 @@ always_ff @(posedge i_clk) begin
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end
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end
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always_comb begin
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always_comb begin
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data_next = data;
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data_next = data; // If neccesary, we can remove this state?
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h_next = h;
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h_next = h;
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state_counter_next = state_counter;
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state_counter_next = state_counter;
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145
ChaCha20_Poly1305_64/src/poly1305_stage.sv
Normal file
145
ChaCha20_Poly1305_64/src/poly1305_stage.sv
Normal file
@@ -0,0 +1,145 @@
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module poly1305_stage #(
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) (
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input logic i_clk,
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input logic i_rst,
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input logic i_valid,
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output logic o_ready,
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input logic i_clear_acc,
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input logic [129:0] i_r_power,
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input logic [127:0] i_message,
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output logic o_valid,
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output logic [129:0] o_result
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);
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localparam [129:0] PRIME = (1 << 130) - 5;
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logic mult_i_valid;
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logic mult_o_ready;
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logic [129:0] r_power, r_power_next;
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logic [130:0] mult_accumulator, mult_accumulator_next;
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logic mult_valid;
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logic [129:0] mult_result;
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logic [129:0] accumulators [2];
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logic [129:0] accumulators_next [2];
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logic [1:0] ops_in_flight, ops_in_flight_next;
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logic [1:0] index, index_next;
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logic [1:0] index_sr [16];
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logic [1:0] index_sr_next;
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enum logic [1:0] {SUM1, SUM2, MUL, STORE} state, state_next;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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state <= SUM1;
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r_power <= '0;
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mult_accumulator <= '0;
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ops_in_flight <= 2'h0;
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index <= 2'h2;
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index_sr <= '{default: '0};
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for (int i = 0; i < 2; i++) begin
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accumulators[i] <= '0;
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end
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end else begin
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state <= state_next;
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r_power <= r_power_next;
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mult_accumulator <= mult_accumulator_next;
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index <= index_next;
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ops_in_flight <= ops_in_flight_next;
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for (int i = 0; i < 2; i++) begin
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accumulators[i] <= accumulators_next[i];
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end
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index_sr[0] <= index;
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for (int i = 1; i < 16; i++) begin
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index_sr[i] <= index_sr[i-1];
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end
|
||||||
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end
|
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end
|
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|
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logic [1:0] ops_in_flight_state;
|
||||||
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assign ops_in_flight_state = {i_valid & o_ready, mult_valid};
|
||||||
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|
||||||
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always_comb begin
|
||||||
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state_next = state;
|
||||||
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o_ready = '0;
|
||||||
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mult_accumulator_next = mult_accumulator;
|
||||||
|
mult_i_valid = '0;
|
||||||
|
index_next = index;
|
||||||
|
|
||||||
|
if (mult_valid) begin
|
||||||
|
accumulators_next[index_sr[12][0]] = mult_result;
|
||||||
|
end
|
||||||
|
|
||||||
|
case (ops_in_flight_state)
|
||||||
|
2'b00: ops_in_flight_next = ops_in_flight;
|
||||||
|
2'b01: ops_in_flight_next = ops_in_flight - 1;
|
||||||
|
2'b10: ops_in_flight_next = ops_in_flight + 1;
|
||||||
|
2'b11: ops_in_flight_next = ops_in_flight;
|
||||||
|
endcase
|
||||||
|
|
||||||
|
o_valid = mult_valid;
|
||||||
|
o_result = mult_result;
|
||||||
|
|
||||||
|
case (state)
|
||||||
|
SUM1: begin
|
||||||
|
o_ready = ops_in_flight < 2;
|
||||||
|
|
||||||
|
if (i_valid && o_ready) begin
|
||||||
|
r_power_next = i_r_power;
|
||||||
|
if (i_clear_acc) begin
|
||||||
|
mult_accumulator_next = {3'b0, i_message};
|
||||||
|
end else begin
|
||||||
|
mult_accumulator_next = accumulators[index[0]] + {3'b0, i_message};
|
||||||
|
end
|
||||||
|
state_next = SUM2;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
SUM2: begin
|
||||||
|
mult_accumulator_next = mult_accumulator >= 131'(PRIME) ? 131'(mult_accumulator - PRIME) : mult_accumulator;
|
||||||
|
state_next = MUL;
|
||||||
|
end
|
||||||
|
|
||||||
|
MUL: begin
|
||||||
|
mult_i_valid = '1;
|
||||||
|
|
||||||
|
if (mult_o_ready) begin
|
||||||
|
index_next = index + 1;
|
||||||
|
|
||||||
|
state_next = SUM1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
default: begin
|
||||||
|
state_next = SUM1;
|
||||||
|
end
|
||||||
|
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
poly1305_friendly_modular_mult u_modular_mult (
|
||||||
|
.i_clk (i_clk),
|
||||||
|
.i_rst (i_rst),
|
||||||
|
|
||||||
|
.i_valid (mult_i_valid),
|
||||||
|
.o_ready (mult_o_ready),
|
||||||
|
.i_data (r_power),
|
||||||
|
.i_accumulator (mult_accumulator[129:0]),
|
||||||
|
|
||||||
|
.o_valid (mult_valid),
|
||||||
|
.o_result (mult_result)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -6,3 +6,4 @@ chacha20_pipelined_block.sv
|
|||||||
poly1305_core.sv
|
poly1305_core.sv
|
||||||
poly1305_friendly_modulo.sv
|
poly1305_friendly_modulo.sv
|
||||||
poly1305_friendly_modular_mult.sv
|
poly1305_friendly_modular_mult.sv
|
||||||
|
poly1305_stage.sv
|
||||||
Reference in New Issue
Block a user