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Make modular mult work

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This commit is contained in:
Byron Lathi
2025-10-28 21:59:28 -07:00
parent ad257f4220
commit d6a062baa0
3 changed files with 16 additions and 14 deletions
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4
ChaCha20_Poly1305_64/sim/modulo_theory.py
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@@ -57,10 +57,6 @@ def friendly_modular_mult(value_a: int, value_b: int) -> int:
mods = [friendly_modulo(prod, 26*i) for i, prod in enumerate(prods)] mods = [friendly_modulo(prod, 26*i) for i, prod in enumerate(prods)]
if sum(mods) >= 2*PRIME:
print("Saw greater than 2x prime!!!")
mod_sum = friendly_modulo(sum(mods), 0) mod_sum = friendly_modulo(sum(mods), 0)
return mod_sum return mod_sum

6
ChaCha20_Poly1305_64/sim/poly1305_friendly_modular_mult.py
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@@ -8,6 +8,8 @@ from cocotb.queue import Queue
from cocotbext.axi import AxiStreamBus, AxiStreamSource from cocotbext.axi import AxiStreamBus, AxiStreamSource
from modulo_theory import friendly_modular_mult
import random import random
PRIME = 2**130-5 PRIME = 2**130-5
@@ -48,7 +50,7 @@ class TB:
async def write_input(self, data: int, h: int): async def write_input(self, data: int, h: int):
await self.input_queue.put((data, h)) await self.input_queue.put((data, h))
await self.expected_queue.put((data * h) % PRIME) await self.expected_queue.put(friendly_modular_mult(h, data))
async def run_input(self): async def run_input(self):
while True: while True:
@@ -76,7 +78,7 @@ async def test_sanity(dut):
await tb.cycle_reset() await tb.cycle_reset()
count = 1 count = 16
for _ in range(count): for _ in range(count):
await tb.write_input(random.randint(1,2**128-1), random.randint(0, 2**130-6)) await tb.write_input(random.randint(1,2**128-1), random.randint(0, 2**130-6))

20
ChaCha20_Poly1305_64/src/poly1305_friendly_modular_mult.sv
View File

@@ -21,6 +21,7 @@ logic [2:0] state_counter, state_counter_next;
logic [2:0] state_counter_p [4]; logic [2:0] state_counter_p [4];
logic [ACC_WIDTH-1:0] accumulator, accumulator_next; // accumulator is outgoing logic [ACC_WIDTH-1:0] accumulator, accumulator_next; // accumulator is outgoing
logic [ACC_WIDTH:0] accumulator_intermediate;
logic [DATA_WIDTH-1:0] data, data_next; logic [DATA_WIDTH-1:0] data, data_next;
logic [ACC_WIDTH-1:0] h, h_next; // h is incoming logic [ACC_WIDTH-1:0] h, h_next; // h is incoming
@@ -61,26 +62,29 @@ always_comb begin
accumulator_next = '0; accumulator_next = '0;
mult_product_next = '0; mult_product_next = '0;
accumulator_intermediate = '0;
if (state_counter < 3'h5) begin
mult_product_next = h[state_counter*26 +: 26] * data;
state_counter_next = state_counter + 1;
end
if (state_counter >= 3'h4 && i_valid) begin if (state_counter >= 3'h4 && i_valid) begin
data_next = i_data; data_next = i_data;
h_next = i_accumulator; h_next = i_accumulator;
state_counter_next = '0; state_counter_next = '0;
end end
if (state_counter < 3'h5) begin
mult_product_next = h[state_counter*26 +: 26] * data;
state_counter_next = state_counter + 1;
end
if (state_counter_p[3] == '0) begin if (state_counter_p[3] == '0) begin
accumulator_next = modulo_result; accumulator_next = modulo_result;
end else begin end else begin
if (accumulator + modulo_result > PRIME) begin accumulator_intermediate = accumulator + modulo_result;
accumulator_next = accumulator + modulo_result - PRIME; if (accumulator_intermediate[130]) begin
// if we wrapped around, we need to add 5
accumulator_next = accumulator_intermediate[129:0] + 5;
end else begin end else begin
accumulator_next = accumulator + modulo_result; accumulator_next = accumulator_intermediate[129:0];
end end
end end