module mult_timing_test(
    input i_clk,

    input logic [132:0] data_a,
    input logic [127:0] data_b,
    
    output logic [260:0] data_z
);

logic [132:0] data_a_reg;
logic [127:0] data_b_reg;


logic [260:0] partial_result [7];

logic [260:0] data_z_temp_1[4];
logic [260:0] data_z_temp_2_0, data_z_temp_2_1;

always @(posedge i_clk) begin
    data_a_reg <= data_a;
    data_b_reg <= data_b;

    for (int i = 0; i < 7; i++) begin
        partial_result[i] <= data_a_reg[i*18 +: 18] * data_b_reg;
    end
    

    data_z_temp_1[0] <= (partial_result[0] << (19*0)) + (partial_result[1] << (19*1));
    data_z_temp_1[1] <= (partial_result[2] << (19*0)) + (partial_result[3] << (19*1));
    data_z_temp_1[2] <= (partial_result[4] << (19*0)) + (partial_result[5] << (19*1));
    data_z_temp_1[3] <= (partial_result[6] << (19*0));

    data_z_temp_2_0 <= data_z_temp_1[0] + (data_z_temp_1[1] << (19*2));
    data_z_temp_2_1 <= data_z_temp_1[2] + (data_z_temp_1[3] << (19*2));

    data_z <= data_z_temp_2_0 + data_z_temp_2_1;

    // data_z <= data_z_temp_2[0] + (data_z_temp_2[1] << (19*4));

end

endmodule