101 lines
2.5 KiB
Systemverilog
101 lines
2.5 KiB
Systemverilog
module poly1305_friendly_modular_mult #(
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parameter DATA_WIDTH = 128,
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parameter ACC_WIDTH = 130
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) (
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input logic i_clk,
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input logic i_rst,
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input logic i_valid,
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output logic o_ready,
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input logic [DATA_WIDTH-1:0] i_data,
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input logic [ACC_WIDTH-1:0] i_accumulator,
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output logic o_valid,
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output logic [ACC_WIDTH-1:0] o_result
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);
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localparam [129:0] PRIME = (1 << 130) - 5;
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logic [2:0] state_counter, state_counter_next;
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logic [2:0] state_counter_p [4];
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logic [ACC_WIDTH-1:0] accumulator, accumulator_next; // accumulator is outgoing
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logic [DATA_WIDTH-1:0] data, data_next;
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logic [ACC_WIDTH-1:0] h, h_next; // h is incoming
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logic [DATA_WIDTH+26-1:0] mult_product, mult_product_next;
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logic [ACC_WIDTH-1:0] modulo_result;
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assign o_ready = state_counter >= 3'h4;
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assign o_result = accumulator;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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state_counter <= 3'h5;
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state_counter_p <= '{default: 3'h5};
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end else begin
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state_counter <= state_counter_next;
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accumulator <= accumulator_next;
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data <= data_next;
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h <= h_next;
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mult_product <= mult_product_next;
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state_counter_p[0] <= state_counter;
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o_valid <= state_counter_p[3] == 3'h4;
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for (int i = 1; i < 4; i++) begin
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state_counter_p[i] <= state_counter_p[i-1];
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end
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end
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end
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always_comb begin
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data_next = data;
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h_next = h;
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state_counter_next = state_counter;
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accumulator_next = '0;
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mult_product_next = '0;
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if (state_counter >= 3'h4 && i_valid) begin
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data_next = i_data;
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h_next = i_accumulator;
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state_counter_next = '0;
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end
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if (state_counter < 3'h5) begin
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mult_product_next = h[state_counter*26 +: 26] * data;
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state_counter_next = state_counter + 1;
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end
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if (state_counter_p[3] == '0) begin
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accumulator_next = modulo_result;
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end else begin
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if (accumulator + modulo_result > PRIME) begin
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accumulator_next = accumulator + modulo_result - PRIME;
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end else begin
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accumulator_next = accumulator + modulo_result;
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end
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end
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end
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poly1305_friendly_modulo u_modulo (
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.i_clk (i_clk),
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.i_rst (i_rst),
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.i_valid ('1),
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.i_val ((2*ACC_WIDTH)'(mult_product)),
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.i_shift_amount (state_counter_p[0]),
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.o_valid (),
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.o_result (modulo_result)
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);
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endmodule |