334eb3ba15
The driver supports UHS-I bus speed modes: SDR25, DDR50, and SDR104. By default, the controller operates in SDR25 mode. Higher-speed modes can be enabled via the Device Tree by adding the following properties to the SDIO node: - sd-uhs-ddr50 - sd-uhs-sdr104 When these properties are present, the driver negotiates the highest supported UHS mode with the card and host. Signed-off-by: Swee Aun Khor <sakhor@efinixinc.com>
589 lines
19 KiB
C
589 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Efinix SDIO Host Controller Tuning Support
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*
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* Copyright (C) 2026 Efinix, Inc.
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* Author: Khor Swee Aun <sakhor@efinixinc.com>
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/mmc/mmc.h>
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#include "efx_sdio.h"
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/* Standard eMMC/SDIO tuning block patterns from bare metal driver */
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static const u32 tuning_block_pattern_8b_mode[] = {
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0xff00ffff, 0x0000ffff, 0xccccffff, 0xcccc33cc,
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0xcc3333cc, 0xffffcccc, 0xffffeeff, 0xffeeeeff,
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0xffddffff, 0xddddffff, 0xbbffffff, 0xbbffffff,
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0xffffffbb, 0xffffff77, 0x77ff7777, 0xffeeddbb,
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0x00ffffff, 0x00ffffff, 0xccffff00, 0xcc33cccc,
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0x3333cccc, 0xffcccccc, 0xffeeffff, 0xeeeeffff,
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0xddffffff, 0xddffffff, 0xffffffdd, 0xffffffbb,
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0xffffbbbb, 0xffff77ff, 0xff7777ff, 0xeeddbb77
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};
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static const u32 tuning_block_pattern_4b_mode[] = {
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0x00ff0fff, 0xccc3ccff, 0xffcc3cc3, 0xeffefffe,
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0xddffdfff, 0xfbfffbff, 0xff7fffbf, 0xefbdf777,
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0xf0fff0ff, 0x3cccfc0f, 0xcfcc33cc, 0xeeffefff,
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0xfdfffdff, 0xffbfffdf, 0xfff7ffbb, 0xde7b7ff7
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};
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void efx_sdio_set_timing_config(struct efx_sdio_host *host,
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u32 sample_count, u32 pll_shift)
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{
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u32 config_value;
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/* Build timing configuration: sample_count[31:16] | pll_shift[8:6] */
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config_value = (sample_count << 16) | (pll_shift << 6);
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/* Apply timing configuration with hardware trigger sequence:
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* 1. Write config with trigger bit clear (bit 0 = 0)
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* 2. Write config with trigger bit set (bit 0 = 1) to latch settings
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*/
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efx_sdio_writel(host, config_value | 0x0, EFX_SDIO_BASE_REG1);
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efx_sdio_writel(host, config_value | 0x1, EFX_SDIO_BASE_REG1);
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efx_sdio_writel(host, config_value | 0x0, EFX_SDIO_BASE_REG1);
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/* Wait for PLL settling */
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udelay(100); /* 100us is sufficient for PLL settling */
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}
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/* Execute custom tuning command for SDR12, SDR25 and DDR50 modes
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* Reminder : This function is called with host lock held
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*/
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int efx_sdio_execute_custom_tuning_command(struct efx_sdio_host *host, int bus_width)
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{
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u32 block_size, command_config, word_count;
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//const u32 *reference_pattern;
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u32 received_data;
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int i, mismatches = 0;
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unsigned long timeout;
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u32 tuning_present_state;
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unsigned long flags;
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u32 reg_addr = 0x0;
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// Reset CRC error flag at start of tuning command
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host->tuning_crc_error = false;
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/* Determine block size and reference pattern based on bus width */
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block_size = 16;
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word_count = block_size/4;
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//reference_pattern = NULL;
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/* Configure arguments for CMD53
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[31] R/W flag = 0
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[30:28] Function number = 0
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[27] Block mode = 0
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[26] OP code (fixed/increment) = 1
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[25:9] Register address = reg_addr
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[8:0] Byte count / block count = 16 (byte)
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*/
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u32 arg = 0;
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arg |= ( 1 << 26 | reg_addr << 9 | 16 );
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efx_sdio_writel(host, arg, EFX_SDIO_ARG1);
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/* Byte mode
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For byte mode, block size is set to the byte count and block count is set to 1
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Might not neeeded as this is a byte mode transfer
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*/
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efx_sdio_writel(host, (1 << 16) | block_size, EFX_SDIO_BLOCK_SIZE);
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/* Configure command based on single or multi-block transfer */
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u32 val = 0;
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u32 cmd_index = 53; // READ_SINGLE_BLOCK command
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u32 data_available = 1; // Data transfer expected
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u32 cmd_index_check_en = 1; // Enable command index check
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u32 cmd_crc_en = 1; // Enable command CRC check
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u32 resp_type = 2; // R1 response type (48-bit)
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u32 data_direction = 1; // Read from card
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u32 auto_cmd_en = 0; // No auto command
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u32 multi_block_en = 0; // Single block transfer
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u32 block_counter_en = 0; // Block counter disabled
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u32 dma_mode = 0; // DMA mode disabled
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/* Build command register value from configuration bits */
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val = (cmd_index << 24) | (data_available << 21) | (cmd_index_check_en << 20) |
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(cmd_crc_en << 19) | (resp_type << 16) | (multi_block_en << 5) |
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(data_direction << 4) | (auto_cmd_en << 2) | (block_counter_en << 1) | (dma_mode << 0);
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efx_sdio_writel(host, val, EFX_SDIO_TRANSFER_MODE);
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/* Wait for buffer ready with timeout */
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timeout = jiffies + msecs_to_jiffies(5);
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do {
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tuning_present_state = efx_sdio_readl(host, EFX_SDIO_PRESENT_STATE);
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if (tuning_present_state & EFX_SDIO_BUFFER_READ_EN) {
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break;
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}
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if (time_after(jiffies, timeout)) {
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dev_dbg(&host->pdev->dev, "Custom tuning command timeout after 5ms\n");
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return 0; /* Failure */
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}
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cpu_relax();
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} while (1);
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/* Read custom tuning data */
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for (i = 0; i < word_count; i++) {
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received_data = efx_sdio_readl(host, EFX_SDIO_BUFFER_DATA_PORT);
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/* Print received data for debugging */
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dev_dbg(&host->pdev->dev, "Received custom tuning data word %d: 0x%08x\n", i, received_data);
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}
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/* Delay 1ms */
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udelay(1000);
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if (host->tuning_crc_error) {
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dev_dbg(&host->pdev->dev,
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"Custom tuning command CRC error detected\n");
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host->tuning_crc_error = false; /* Reset CRC error flag after handling */
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return 0; /* Failure due to CRC error */
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}
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return 1; /* Success */
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}
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int efx_sdio_execute_tuning_command(struct efx_sdio_host *host, int bus_width)
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{
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u32 block_size, command_config, word_count;
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const u32 *reference_pattern;
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u32 received_data;
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int i, mismatches = 0;
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unsigned long timeout;
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u32 tuning_present_state;
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unsigned long flags;
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/* Determine block size and reference pattern based on bus width */
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if (bus_width == 8) {
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block_size = EFX_SDIO_TUNING_BLOCK_SIZE_8BIT;
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word_count = 32;
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reference_pattern = tuning_block_pattern_8b_mode;
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} else {
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block_size = EFX_SDIO_TUNING_BLOCK_SIZE_4BIT;
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word_count = 16;
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reference_pattern = tuning_block_pattern_4b_mode;
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}
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/* Configure command parameters for CMD19 */
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efx_sdio_writel(host, (1 << 16) | block_size, EFX_SDIO_BLOCK_SIZE);
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efx_sdio_writel(host, 0x0, EFX_SDIO_ARG1);
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/* Issue CMD19 tuning command with specific configuration */
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/* CMD19 (index=19), data present, CRC check, 48-bit response */
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//
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command_config = 0x133A0010;
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spin_lock_irqsave(&host->lock, flags);
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host->tuning_crc_error = false; // Reset CRC error flag at start of tuning command
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spin_unlock_irqrestore(&host->lock, flags);
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efx_sdio_writel(host, command_config, EFX_SDIO_TRANSFER_MODE);
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/* Wait for buffer ready with timeout */
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timeout = jiffies + msecs_to_jiffies(5);
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do {
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tuning_present_state = efx_sdio_readl(host, EFX_SDIO_PRESENT_STATE);
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if (tuning_present_state & EFX_SDIO_BUFFER_READ_EN) {
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break;
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}
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if (time_after(jiffies, timeout)) {
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dev_dbg(&host->pdev->dev, "Tuning command timeout after 5ms\n");
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return 0; /* Failure */
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}
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cpu_relax();
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} while (1);
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/* Read tuning data and compare against expected pattern */
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for (i = 0; i < word_count; i++) {
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received_data = efx_sdio_readl(host, EFX_SDIO_BUFFER_DATA_PORT);
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/* Compare against standard pattern */
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if (received_data != reference_pattern[i]) {
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mismatches++;
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dev_dbg(&host->pdev->dev,
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"Tuning data mismatch at word %d: got 0x%08x, expected 0x%08x\n",
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i, received_data, reference_pattern[i]);
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}
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}
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udelay(1000);
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if (host->tuning_crc_error) {
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dev_dbg(&host->pdev->dev,
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"Tuning command CRC error detected\n");
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host->tuning_crc_error = false; /* Reset CRC error flag after handling */
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return 0; /* Failure due to CRC error */
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}
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/* Allow up to 2 mismatches due to electrical noise during tuning */
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// SDIO: change to 0 mismatches for stricter tuning
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if (mismatches == 0) {
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return 1; /* Success */
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} else {
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dev_dbg(&host->pdev->dev, "Too many mismatches: %d\n", mismatches);
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return 0; /* Failure */
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}
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}
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static int efx_sdio_find_longest_consecutive_ones(u8 *row, int length)
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{
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int max_len, current_len, i;
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max_len = 0;
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current_len = 0;
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for (i = 0; i < length; i++) {
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if (row[i] == 1) {
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current_len++;
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if (current_len > max_len) {
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max_len = current_len;
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}
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} else {
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current_len = 0;
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}
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}
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return max_len;
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}
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static int efx_sdio_find_center_of_consecutive_ones(u8 *row, int length)
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{
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int max_len, current_len, max_start, current_start, center, i;
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max_len = 0;
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current_len = 0;
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max_start = 0;
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current_start = 0;
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for (i = 0; i < length; i++) {
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if (row[i] == 1) {
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if (current_len == 0) {
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current_start = i;
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}
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current_len++;
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if (current_len > max_len) {
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max_len = current_len;
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max_start = current_start;
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}
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} else {
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current_len = 0;
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}
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}
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/* Return center of longest consecutive sequence */
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center = max_start + (max_len / 2);
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return center;
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}
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int efx_sdio_find_optimal_timing(struct efx_sdio_host *host,
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u8 result_map[][EFX_SDIO_MAX_PLL_SHIFT],
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u32 max_sample_count)
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{
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int max_consecutive_length, row_length, optimal_sample_count,
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optimal_pll_shift;
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int *optimal_rows;
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int optimal_row_count, center_row, i;
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char optimal_row_str[32];
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optimal_rows = kmalloc(max_sample_count * sizeof(int), GFP_KERNEL);
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if (!optimal_rows) {
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return -ENOMEM;
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}
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/* Find rows with longest consecutive 1's */
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dev_dbg(&host->pdev->dev, "Analyzing timing results\n");
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max_consecutive_length = 0;
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for (i = 0; i < max_sample_count; i++) {
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row_length = efx_sdio_find_longest_consecutive_ones(result_map[i],
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EFX_SDIO_MAX_PLL_SHIFT);
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dev_dbg(&host->pdev->dev, "Sample[%u]: consecutive_length=%d\n",
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i, row_length);
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if (row_length > max_consecutive_length) {
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dev_dbg(&host->pdev->dev,
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"New best: Sample[%u] length=%d\n",
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i, row_length);
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max_consecutive_length = row_length;
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}
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}
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dev_dbg(&host->pdev->dev, "Best consecutive length: %d\n",
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max_consecutive_length);
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if (max_consecutive_length < EFX_SDIO_MIN_TIMING_MARGIN) {
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dev_warn(&host->pdev->dev,
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"Insufficient timing margin: %d (minimum %d)\n",
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max_consecutive_length, EFX_SDIO_MIN_TIMING_MARGIN);
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}
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/* Collect all rows with maximum consecutive length */
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optimal_row_count = 0;
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for (i = 0; i < max_sample_count; i++) {
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if (efx_sdio_find_longest_consecutive_ones(result_map[i],
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EFX_SDIO_MAX_PLL_SHIFT) ==
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max_consecutive_length) {
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optimal_rows[optimal_row_count++] = i;
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}
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}
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if (optimal_row_count == 0) {
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kfree(optimal_rows);
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return -ENODEV; /* No valid configurations found */
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}
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/* Find center row */
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center_row = optimal_row_count / 2;
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optimal_sample_count = optimal_rows[center_row];
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/* Find center column within optimal row */
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dev_dbg(&host->pdev->dev,
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"Selected sample_count=%d from %d optimal rows\n",
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optimal_sample_count, optimal_row_count);
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/* Debug: Show the row being analyzed for center calculation */
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optimal_row_str[0] = '\0';
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for (i = 0; i < EFX_SDIO_MAX_PLL_SHIFT; i++) {
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sprintf(optimal_row_str + strlen(optimal_row_str), "%d",
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result_map[optimal_sample_count][i]);
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}
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dev_dbg(&host->pdev->dev,
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"Analyzing row[%d]: [%s] for center calculation\n",
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optimal_sample_count, optimal_row_str);
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optimal_pll_shift =
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efx_sdio_find_center_of_consecutive_ones(result_map[optimal_sample_count],
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EFX_SDIO_MAX_PLL_SHIFT);
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dev_dbg(&host->pdev->dev,
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"Center PLL calculation result: pll_shift=%d\n",
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optimal_pll_shift);
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/* Store optimal configuration */
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host->optimal_sample_count = optimal_sample_count;
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host->optimal_pll_shift = optimal_pll_shift;
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host->optimal_margin = max_consecutive_length;
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dev_dbg(&host->pdev->dev,
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"Optimal timing found: sample_count=%u, pll_shift=%u, margin=%d\n",
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optimal_sample_count, optimal_pll_shift, max_consecutive_length);
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kfree(optimal_rows);
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return 0;
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}
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/* Execute tuning procedure for given opcode
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* Reminder: For custom tuning, this function is called with host lock released
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*/
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int efx_sdio_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct efx_sdio_host *host;
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u32 max_sample_count, sample_count, pll_shift;
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int bus_width, success, ret;
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unsigned long flags, timeout;
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u8 (*tuning_result_map)[EFX_SDIO_MAX_PLL_SHIFT];
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u32 tuning_loop = 10;
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host = mmc_priv(mmc);
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/* Set tuning in progress flag to suppress error logging */
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host->tuning_in_progress = true;
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dev_dbg(&host->pdev->dev, "Starting tuning: timing=%u, clock=%u Hz\n",
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mmc->ios.timing, mmc->ios.clock);
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/* Skip tuning if already tuned for current mode */
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if (host->prev_timing == mmc->ios.timing && host->tuning_done) {
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dev_dbg(&host->pdev->dev,
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"Tuning skipped: already tuned for timing=%u (sample=%u, pll=%u)\n",
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mmc->ios.timing, host->optimal_sample_count,
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host->optimal_pll_shift);
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return 0;
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}
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/* Validate SDIO tuning opcode
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* MMC_SEND_TUNING_BLOCK or UINT_MAX for custom tuning
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*/
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if (opcode != MMC_SEND_TUNING_BLOCK && opcode != UINT_MAX) {
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dev_err(&host->pdev->dev, "Unsupported tuning opcode: %u\n", opcode);
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return -EINVAL;
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}
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/* Valid bus widths is 4-bit */
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if (mmc->ios.bus_width != MMC_BUS_WIDTH_4) {
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dev_warn(&host->pdev->dev,
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"UHS-I Tuning only supported for 4-bit bus width, current width=%d\n",
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mmc->ios.bus_width);
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return -EINVAL;
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}
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bus_width = 4;
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/* max_sample_count should match clk_div - sample count can't exceed
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* clock divider
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*/
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/* Use actual clock divider */
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max_sample_count = host->clk_div ? host->clk_div : 1;
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dev_dbg(&host->pdev->dev,
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"Starting tuning algorithm (bus_width=%d, max_sample=%u)\n",
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bus_width, max_sample_count);
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/* Dynamically allocate tuning result map */
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tuning_result_map = kmalloc(max_sample_count *
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sizeof(u8[EFX_SDIO_MAX_PLL_SHIFT]),
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GFP_KERNEL);
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if (!tuning_result_map) {
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dev_err(&host->pdev->dev, "Failed to allocate tuning result map\n");
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return -ENOMEM;
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}
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// Init entire map to 1
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memset(tuning_result_map, 1,
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max_sample_count * sizeof(u8[EFX_SDIO_MAX_PLL_SHIFT]));
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dev_dbg(&host->pdev->dev, "Using clk_div=%u for sample count\n",
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max_sample_count);
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/* Set tuning timeout to 10 seconds */
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timeout = jiffies + msecs_to_jiffies(10000);
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/* Tuning loop */
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for (tuning_loop = 0; tuning_loop < 10; tuning_loop++) {
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dev_dbg(&host->pdev->dev, "Tuning loop %d:\n", tuning_loop + 1);
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/* Phase 2: Timing configuration search */
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dev_dbg(&host->pdev->dev, "Testing %d samples × %d PLL positions\n",
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max_sample_count, EFX_SDIO_MAX_PLL_SHIFT);
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for (sample_count = 0; sample_count < max_sample_count; sample_count++) {
|
||
|
||
int consecutive_passes = 0;
|
||
for (pll_shift = 0; pll_shift < EFX_SDIO_MAX_PLL_SHIFT; pll_shift++) {
|
||
|
||
dev_dbg(&host->pdev->dev,
|
||
"Tuning loop %d: Testing sample_count=%u, pll_shift=%u\n",
|
||
tuning_loop + 1, sample_count, pll_shift);
|
||
|
||
/* Apply timing configuration */
|
||
efx_sdio_set_timing_config(host, sample_count, pll_shift);
|
||
|
||
/* Execute validation test */
|
||
if (opcode == MMC_SEND_TUNING_BLOCK) {
|
||
success = efx_sdio_execute_tuning_command(host, bus_width);
|
||
} else {
|
||
/* Custom tuning - implement specific test if needed */
|
||
success = efx_sdio_execute_custom_tuning_command(host, bus_width);
|
||
}
|
||
|
||
/* Update result map */
|
||
if (!success) {
|
||
dev_dbg(&host->pdev->dev,
|
||
"Tuning [%u][%u]: FAIL\n",
|
||
sample_count, pll_shift);
|
||
|
||
// Only update the unsuccessful result
|
||
tuning_result_map[sample_count][pll_shift] = 0;
|
||
consecutive_passes = 0;
|
||
} else {
|
||
//SA tuning_result_map[sample_count][pll_shift] = 1;
|
||
consecutive_passes++;
|
||
}
|
||
|
||
dev_dbg(&host->pdev->dev,
|
||
"Tuning [%u][%u]: %s (consecutive: %d)\n",
|
||
sample_count, pll_shift, success ? "PASS" : "FAIL",
|
||
consecutive_passes);
|
||
|
||
/* Check timeout */
|
||
if (time_after(jiffies, timeout)) {
|
||
dev_warn(&host->pdev->dev, "Tuning timeout after 10 seconds\n");
|
||
goto find_optimal;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
find_optimal:
|
||
|
||
/* Print timing map results - only for new timing modes */
|
||
if (!test_bit(mmc->ios.timing, &host->tuned_timing_modes)) {
|
||
dev_info(&host->pdev->dev, "Tuning result map:\n");
|
||
for (sample_count = 0; sample_count < max_sample_count;
|
||
sample_count++) {
|
||
char row_str[32] = "";
|
||
for (pll_shift = 0; pll_shift < EFX_SDIO_MAX_PLL_SHIFT;
|
||
pll_shift++) {
|
||
sprintf(row_str + strlen(row_str), "%d",
|
||
tuning_result_map[sample_count][pll_shift]);
|
||
}
|
||
dev_info(&host->pdev->dev, "Sample[%u]: [%s]\n",
|
||
sample_count, row_str);
|
||
}
|
||
}
|
||
|
||
/* Phase 4: Find optimal timing configuration using dynamic map */
|
||
ret = efx_sdio_find_optimal_timing(host, tuning_result_map,
|
||
max_sample_count);
|
||
if (ret == 0) {
|
||
/* Use optimal timing found by tuning algorithm */
|
||
efx_sdio_set_timing_config(host, host->optimal_sample_count,
|
||
host->optimal_pll_shift);
|
||
|
||
/* Show detailed results only for new timing modes */
|
||
if (!test_bit(mmc->ios.timing, &host->tuned_timing_modes)) {
|
||
dev_info(&host->pdev->dev,
|
||
"Tuning completed: sample=%u, pll=%u, margin=%u\n",
|
||
host->optimal_sample_count, host->optimal_pll_shift,
|
||
host->optimal_margin);
|
||
} else {
|
||
dev_info(&host->pdev->dev,
|
||
"Tuning reconfirmed: sample=%u, pll=%u\n",
|
||
host->optimal_sample_count, host->optimal_pll_shift);
|
||
}
|
||
|
||
host->tuning_done = true;
|
||
/* Mark this timing mode as successfully tuned */
|
||
set_bit(mmc->ios.timing, &host->tuned_timing_modes);
|
||
} else {
|
||
/* Fallback to safe timing configuration */
|
||
dev_warn(&host->pdev->dev,
|
||
"Tuning failed: %d, using fallback configuration\n",
|
||
ret);
|
||
if (max_sample_count == 1) {
|
||
efx_sdio_set_timing_config(host, 0, 2); /* Safe for 200MHz */
|
||
host->optimal_sample_count = 0;
|
||
host->optimal_pll_shift = 2;
|
||
} else {
|
||
/* Conservative default timing */
|
||
efx_sdio_set_timing_config(host, 1, 1);
|
||
host->optimal_sample_count = 1;
|
||
host->optimal_pll_shift = 1;
|
||
}
|
||
host->tuning_done = true; /* Mark as done to prevent retry loops */
|
||
/* Mark this timing mode as successfully tuned (fallback) */
|
||
set_bit(mmc->ios.timing, &host->tuned_timing_modes);
|
||
ret = 0; /* Return success to allow operation to continue */
|
||
}
|
||
|
||
/* Update previous timing for reference */
|
||
spin_lock_irqsave(&host->lock, flags);
|
||
host->prev_timing = mmc->ios.timing;
|
||
spin_unlock_irqrestore(&host->lock, flags);
|
||
|
||
/* Free dynamically allocated tuning result map */
|
||
kfree(tuning_result_map);
|
||
|
||
/* Clear tuning in progress flag */
|
||
host->tuning_in_progress = false;
|
||
|
||
if (ret == 0) {
|
||
dev_dbg(&host->pdev->dev, "Tuning completed successfully\n");
|
||
} else {
|
||
dev_err(&host->pdev->dev, "Tuning failed: %d\n", ret);
|
||
}
|
||
|
||
return ret;
|
||
}
|