Initial commit

src/fpga_sim/fpga_sim.py

@@ -0,0 +1,92 @@
+from ast import parse
+from email.mime import base
+import os
+
+import argparse
+
+from cocotb.runner import get_runner
+
+from rtl_manifest import rtl_manifest
+
+import yaml
+
+
+def fpga_sim():
+    # 1: Parse Arguments.
+
+    parser = argparse.ArgumentParser(
+        prog="sim",
+        description="Tool to simulate"
+    )
+
+    parser.add_argument("yaml")
+
+    args = parser.parse_args()
+
+    # print(args.yaml)
+
+    with open(args.yaml) as cfg_file:
+        cfg = yaml.safe_load(cfg_file)
+
+    # print(cfg)
+
+    # 2: Get source files
+
+    repo_top = os.getenv("REPO_TOP")
+
+    sources = rtl_manifest.read_sources(f"{repo_top}/src/sources.list") # hack
+    sources.extend(rtl_manifest.read_sources(f"{repo_top}/sim/sources.list")) # hack
+
+    print(sources)
+
+    # 3: Figure out which tests to run
+
+    base_path = os.path.split(os.path.abspath(args.yaml))[0]
+    print(base_path)
+
+    tests = []
+
+    def parse_cfg(_cfg, _base_path=None):
+        for test in _cfg:
+            if test["type"] == "yaml":
+                with open(f"{_base_path}/{test["yaml"]}") as _cfg_file:
+                    __cfg = yaml.safe_load(_cfg_file)
+                    parse_cfg(__cfg, f"{base_path}/{os.path.split(test["yaml"])[0]}")
+            if test["type"] == "test":
+                tests.append({
+                        "name": test["name"],
+                        "toplevel": test["toplevel"],
+                        "modules": test["modules"],
+                        "waves": test["waves"],
+                    })
+
+    parse_cfg(cfg, base_path)
+
+    # 4: Run those tests
+    sim = os.getenv("SIM", "verilator")
+    runner = get_runner(sim)
+
+    os.environ["MAKEFLAGS"] = "-j"
+
+    try:
+        os.mkdir(f"{os.getenv("REPO_TOP")}/results")
+    except FileExistsError:
+        pass
+
+    for test in tests:
+
+        runner.build(
+            verilog_sources=sources,
+            hdl_toplevel=test["toplevel"],
+            always=True,
+            clean=True,
+            waves=test["waves"]
+        )
+
+        result_xml = f"../results/{test["name"]}_results.xml".replace(" ", "_")
+
+        runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
+
+
+if __name__ == "__main__":
+    main()