From 1b1d3f8def0f2d31b9ed95d3f43ad5717e53cfa7 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Fri, 21 Mar 2025 05:45:28 +0000 Subject: [PATCH] Experimental/incdirs --- pyproject.toml | 4 ++-- requirements.txt | 4 ++++ src/fpga_sim/fpga_sim.py | 5 ++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index 4e96454..0c519f1 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami # https://packaging.python.org/guides/single-sourcing-package-version/ # dynamic = ["version"] -version = "0.2.2" # REQUIRED, although can be dynamic +version = "0.3.0" # REQUIRED, although can be dynamic # This is a one-line description or tagline of what your project does. This # corresponds to the "Summary" metadata field: @@ -123,7 +123,7 @@ classifiers = [ dependencies = [ "pyyaml", "cocotb", - "rtl-manifest" + "rtl-manifest>=0.3.1" ] # List additional groups of dependencies here (e.g. development diff --git a/requirements.txt b/requirements.txt index 51f4f68..fe06a70 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,4 +1,8 @@ +-i https://git.byronlathi.com/api/v4/projects/95/packages/pypi/simple setuptools wheel build twine +cocotb +rtl-manifest +pyyaml \ No newline at end of file diff --git a/src/fpga_sim/fpga_sim.py b/src/fpga_sim/fpga_sim.py index fcc61eb..d6bf863 100644 --- a/src/fpga_sim/fpga_sim.py +++ b/src/fpga_sim/fpga_sim.py @@ -1,5 +1,3 @@ -from ast import parse -from email.mime import base import os import sys @@ -95,10 +93,11 @@ def fpga_sim_main(): # Turn this into a multiprocessing pool for test in tests_to_run: - sources = rtl_manifest.read_sources(f"{test['base_path']}/{test['sources']}") + sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}") runner.build( verilog_sources=sources, + includes=incdirs, hdl_toplevel=test["toplevel"], build_dir=f"{test['base_path']}/sim_build", waves=test["waves"],