Experimental/incdirs

src/fpga_sim/fpga_sim.py

@@ -1,5 +1,3 @@
-from ast import parse
-from email.mime import base
 import os
 import sys
 
@@ -95,10 +93,11 @@ def fpga_sim_main():
     # Turn this into a multiprocessing pool
     for test in tests_to_run:
 
-        sources = rtl_manifest.read_sources(f"{test['base_path']}/{test['sources']}")
+        sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
 
         runner.build(
             verilog_sources=sources,
+            includes=incdirs,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",
             waves=test["waves"],