Filter out only verilog sources (and verilator lint files)

src/fpga_sim/fpga_sim.py

@@ -95,8 +95,11 @@ def fpga_sim_main():
 
         sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
 
+        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
+
+
         runner.build(
-            verilog_sources=sources,
+            verilog_sources=verilog_sources,
             includes=incdirs,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",