From 77e02698006bf1481cda9df64ac7683b4f846ae0 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sat, 29 Mar 2025 19:28:30 -0700 Subject: [PATCH] Filter out only verilog sources (and verilator lint files) --- pyproject.toml | 2 +- src/fpga_sim/fpga_sim.py | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index 0c519f1..019bc58 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami # https://packaging.python.org/guides/single-sourcing-package-version/ # dynamic = ["version"] -version = "0.3.0" # REQUIRED, although can be dynamic +version = "0.3.1" # REQUIRED, although can be dynamic # This is a one-line description or tagline of what your project does. This # corresponds to the "Summary" metadata field: diff --git a/src/fpga_sim/fpga_sim.py b/src/fpga_sim/fpga_sim.py index d6bf863..2e0c67c 100644 --- a/src/fpga_sim/fpga_sim.py +++ b/src/fpga_sim/fpga_sim.py @@ -95,8 +95,11 @@ def fpga_sim_main(): sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}") + verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources)) + + runner.build( - verilog_sources=sources, + verilog_sources=verilog_sources, includes=incdirs, hdl_toplevel=test["toplevel"], build_dir=f"{test['base_path']}/sim_build",