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Filter out only verilog sources (and verilator lint files)

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Byron Lathi
2025-03-29 19:28:30 -07:00
parent a443af41a1
commit 77e0269800
2 changed files with 5 additions and 2 deletions
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pyproject.toml
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@@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami
# https://packaging.python.org/guides/single-sourcing-package-version/
# dynamic = ["version"]
version = "0.3.0" # REQUIRED, although can be dynamic
version = "0.3.1" # REQUIRED, although can be dynamic
# This is a one-line description or tagline of what your project does. This
# corresponds to the "Summary" metadata field: