From bc49915ba0cc3b1c531f3aadbc146fd45dafebd8 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Wed, 11 Feb 2026 21:25:30 -0800 Subject: [PATCH] Add back FST (use verilator 5.036 or greater) --- pyproject.toml | 2 +- src/fpga_sim/fpga_sim.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index 85dba59..359cbca 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami # https://packaging.python.org/guides/single-sourcing-package-version/ # dynamic = ["version"] -version = "0.5.3" # REQUIRED, although can be dynamic +version = "0.5.4" # REQUIRED, although can be dynamic # This is a one-line description or tagline of what your project does. This # corresponds to the "Summary" metadata field: diff --git a/src/fpga_sim/fpga_sim.py b/src/fpga_sim/fpga_sim.py index 22d93d0..0a3a0d5 100644 --- a/src/fpga_sim/fpga_sim.py +++ b/src/fpga_sim/fpga_sim.py @@ -107,8 +107,8 @@ def fpga_sim_main(): build_args = ["--timing"] # By default, verilator only uses vcd instead of fst, but fst is better. - #if test["waves"]: - # build_args.append("--trace-fst") + if test["waves"]: + build_args.append("--trace-fst") try: runner.build(