Set language type to verilog

hate vhdl

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.4.0a1"  # REQUIRED, although can be dynamic
+version = "0.5.2"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:
@@ -122,7 +122,7 @@ classifiers = [
 # https://packaging.python.org/discussions/install-requires-vs-requirements/
 dependencies = [
   "pyyaml",
-  "cocotb",
+  "cocotb>=2",
   "rtl-manifest>=0.3.1"
 ]
 

src/fpga_sim/fpga_sim.py

@@ -3,7 +3,9 @@ import sys
 
 import argparse
 
-from cocotb.runner import get_runner
+import subprocess
+
+from cocotb_tools.runner import get_runner, VerilatorControlFile
 
 from rtl_manifest import rtl_manifest
 
@@ -95,8 +97,12 @@ def fpga_sim_main():
 
         sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
 
-        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
+        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv")), sources))
+        verilator_sources = [VerilatorControlFile(s) for s in list(filter(lambda s: (s.endswith(".vlt")), sources))]
 
+        sources = []
+        sources.extend(verilog_sources)
+        sources.extend(verilator_sources)
 
         build_args = ["--timing"]
 
@@ -104,19 +110,23 @@ def fpga_sim_main():
         if test["waves"]:
             build_args.append("--trace-fst")
 
-        runner.build(
-            verilog_sources=verilog_sources,
-            includes=incdirs,
-            hdl_toplevel=test["toplevel"],
-            build_dir=f"{test['base_path']}/sim_build",
-            waves=test["waves"],
-            defines=defines,
-            build_args=build_args
-        )
+        try:
+            runner.build(
+                sources=sources,
+                includes=incdirs,
+                hdl_toplevel=test["toplevel"],
+                build_dir=f"{test['base_path']}/sim_build",
+                waves=test["waves"],
+                defines=defines,
+                build_args=build_args
+            )
+        except subprocess.CalledProcessError:
+            print("Failed to compile")
+            return
 
         result_xml = f"../sim_build/{test['name']}_results.xml".replace(" ", "_")
 
         sys.path.append(test["base_path"])
 
-        runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
+        runner.test(hdl_toplevel_lang="verilog", hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)