from ast import parse
from email.mime import base
import os
import sys

import argparse

from cocotb.runner import get_runner

from rtl_manifest import rtl_manifest

import yaml


def fpga_sim_main():
    # 1: Parse Arguments.

    parser = argparse.ArgumentParser(
        prog="sim",
        description="Tool to simulate"
    )

    parser.add_argument("yaml")

    args = parser.parse_args()

    # print(args.yaml)

    with open(args.yaml) as cfg_file:
        cfg = yaml.safe_load(cfg_file)

    # 2: Figure out which tests to run

    base_path = os.path.split(os.path.abspath(args.yaml))[0]

    tests = []

    def parse_cfg(_cfg, _base_path=None):
        for test in _cfg:
            if test["type"] == "yaml":
                with open(f"{_base_path}/{test["yaml"]}") as _cfg_file:
                    __cfg = yaml.safe_load(_cfg_file)
                    parse_cfg(__cfg, f"{_base_path}/{os.path.split(test["yaml"])[0]}")
            if test["type"] == "test":
                waves = test["waves"] if "waves" in test else None
                tests.append({
                        "base_path": _base_path,
                        "name": test["name"],
                        "toplevel": test["toplevel"],
                        "modules": test["modules"],
                        "waves": waves,
                        "sources": test["sources"]
                    })

    parse_cfg(cfg, base_path)

    # 4: Run those tests
    sim = os.getenv("SIM", "verilator")
    runner = get_runner(sim)

    os.environ["MAKEFLAGS"] = "-j"

    try:
        os.mkdir(f"{os.getenv("REPO_TOP")}/results")
    except FileExistsError:
        pass

    for test in tests:

        sources = rtl_manifest.read_sources(f"{test["base_path"]}/{test["sources"]}")

        runner.build(
            verilog_sources=sources,
            hdl_toplevel=test["toplevel"],
            build_dir=f"{test["base_path"]}/sim_build",
            waves=test["waves"]
        )

        result_xml = f"../sim_build/{test["name"]}_results.xml".replace(" ", "_")

        sys.path.append(test["base_path"])

        runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)