// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.288.2.10
// IP Version: 7.1
// =============================================================================

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//                                                                       
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//                                                                       
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.                                                
//
////////////////////////////////////////////////////////////////////////////////

`define IP_UUID _4c19f37180ff465ca20760e199a0613f
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module gTSE
(
    input mac_reset,
    input proto_reset,
    output rx_mac_aclk,
    input tx_mac_aclk,
    output [2:0] eth_speed,
    input rx_axis_clk,
    output rx_axis_mac_tuser,
    output rx_axis_mac_tlast,
    output rx_axis_mac_tvalid,
    input rx_axis_mac_tready,
    input tx_axis_clk,
    input tx_axis_mac_tvalid,
    input tx_axis_mac_tlast,
    input tx_axis_mac_tuser,
    output tx_axis_mac_tready,
    output [3:0] rgmii_txd_HI,
    output [3:0] rgmii_txd_LO,
    output rgmii_tx_ctl_HI,
    output rgmii_tx_ctl_LO,
    output rgmii_txc_HI,
    output rgmii_txc_LO,
    input [3:0] rgmii_rxd_HI,
    input [3:0] rgmii_rxd_LO,
    input rgmii_rx_ctl_HI,
    input rgmii_rx_ctl_LO,
    input rgmii_rxc,
    input s_axi_aclk,
    output [7:0] rx_axis_mac_tdata,
    input [7:0] tx_axis_mac_tdata,
    input [0:0] tx_axis_mac_tstrb,
    output [0:0] rx_axis_mac_tstrb,
    output MdoEn,
    output Mdo,
    input Mdi,
    output Mdc,
    input [9:0] s_axi_araddr,
    output s_axi_arready,
    input s_axi_arvalid,
    input [9:0] s_axi_awaddr,
    output s_axi_awready,
    input s_axi_awvalid,
    input s_axi_bready,
    output [1:0] s_axi_bresp,
    output s_axi_bvalid,
    output [31:0] s_axi_rdata,
    input s_axi_rready,
    output [1:0] s_axi_rresp,
    output s_axi_rvalid,
    input [31:0] s_axi_wdata,
    output s_axi_wready,
    input s_axi_wvalid
);
`IP_MODULE_NAME(efx_mac1gbe)
#(
    .VERSION (16),
    .TXFIFO_EN (1'b1),
    .RXFIFO_EN (1'b1),
    .TXFIFO_DTH (4096),
    .RXFIFO_DTH (4096),
    .PHY_INTF_MODE (0),
    .AXIS_DW (8),
    .RGMII_RXC_EDGE (1'b1),
    .RGMII_TXC_DLY (1'b1),
    .INTER_PACKET_GAP (6'd12),
    .MTU_FRAME_LENGTH (16'd1518),
    .MAC_SOURCE_ADDRESS (48'd0),
    .ENABLE_BROADCAST_FILTERING (1'b1),
    .LOOPBACK_EN (1'b1),
    .APBIF (1'b0),
    .FAMILY ("TITANIUM")
)
u_efx_mac1gbe
(
    .mac_reset ( mac_reset ),
    .proto_reset ( proto_reset ),
    .rx_mac_aclk ( rx_mac_aclk ),
    .tx_mac_aclk ( tx_mac_aclk ),
    .eth_speed ( eth_speed ),
    .rx_axis_clk ( rx_axis_clk ),
    .rx_axis_mac_tuser ( rx_axis_mac_tuser ),
    .rx_axis_mac_tlast ( rx_axis_mac_tlast ),
    .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ),
    .rx_axis_mac_tready ( rx_axis_mac_tready ),
    .tx_axis_clk ( tx_axis_clk ),
    .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ),
    .tx_axis_mac_tlast ( tx_axis_mac_tlast ),
    .tx_axis_mac_tuser ( tx_axis_mac_tuser ),
    .tx_axis_mac_tready ( tx_axis_mac_tready ),
    .rgmii_txd_HI ( rgmii_txd_HI ),
    .rgmii_txd_LO ( rgmii_txd_LO ),
    .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
    .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
    .rgmii_txc_HI ( rgmii_txc_HI ),
    .rgmii_txc_LO ( rgmii_txc_LO ),
    .rgmii_rxd_HI ( rgmii_rxd_HI ),
    .rgmii_rxd_LO ( rgmii_rxd_LO ),
    .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
    .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
    .rgmii_rxc ( rgmii_rxc ),
    .s_axi_aclk ( s_axi_aclk ),
    .rx_axis_mac_tdata ( rx_axis_mac_tdata ),
    .tx_axis_mac_tdata ( tx_axis_mac_tdata ),
    .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ),
    .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ),
    .MdoEn ( MdoEn ),
    .Mdo ( Mdo ),
    .Mdi ( Mdi ),
    .Mdc ( Mdc ),
    .s_axi_araddr ( s_axi_araddr ),
    .s_axi_arready ( s_axi_arready ),
    .s_axi_arvalid ( s_axi_arvalid ),
    .s_axi_awaddr ( s_axi_awaddr ),
    .s_axi_awready ( s_axi_awready ),
    .s_axi_awvalid ( s_axi_awvalid ),
    .s_axi_bready ( s_axi_bready ),
    .s_axi_bresp ( s_axi_bresp ),
    .s_axi_bvalid ( s_axi_bvalid ),
    .s_axi_rdata ( s_axi_rdata ),
    .s_axi_rready ( s_axi_rready ),
    .s_axi_rresp ( s_axi_rresp ),
    .s_axi_rvalid ( s_axi_rvalid ),
    .s_axi_wdata ( s_axi_wdata ),
    .s_axi_wready ( s_axi_wready ),
    .s_axi_wvalid ( s_axi_wvalid )
);
endmodule

//pragma protect
//pragma protect begin
`protected

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`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

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    Jo+#NH5,T8l@s~dE^=7*}T$BeHu,#z3[?Q?.'Bz17TX\Q3v[8<-UK+Go,
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

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`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

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    ;Blri_mXlil?wR{JnvZhzZok*W'XK_rE]$lkRAZUrmnA{OGAF1lKepBGkBkVa&MlT3-7~JQa_7vA
    je~pCJ1KX1pIk{RcBiRKu]_sJCGiCu+@\=~pVO1Y}>e?la^I#h?$IzHw{=[siHieK~Ok~Hlm{AN'
    X-HUDTQ[^E3HV2k}kXjI\B!::r3~$Vjl]Y5XxUNIm*UxCAwawo;U<*2f?XwFO;<srB_>]2W[h^dM
    mCEE1*BZ
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#Crl^]Q3n5XwJ'5x]rIvQHEIRar\~Xa;;Fl~*7|Q~zeIGWO$vjUGZjv\3-<Z^GOh}+Ri^?vi
    ws@5<eXazxC[EfkQ'Be-e]iXa[zx^QI}VCX$s$$2[zN!hdYC={mhO?3B)=,${-DB>LTj@$<<YiL,
    _HI^Gvo=C>,m};Gla+C$Vr*Duxm^;j+~Y@K[-m#r#rJ'veE'7_KeQe'eRr-iTI22];pVG_@T7a3A
    1n7IP\^aT<R#I,s2AFY-|B}vQD+j!1J7vJ7mV5WRiCE*5a<][k1iuUE@rw5K~k+ae1+AXCrD!1*>
    alBn?Z8q-8In$kJT]{'2e]@U!5Fi5r>k+'k[TpE]u\$$~rA<]Q*DYw!RAIn,eRwwr^_*jJE]!@VT
    p$<'B{EC!n$gP[}'e@DJsGaxO%YH$Z~CY'I6%=owE5UOJXEa$v@J!-10=?oDnl7;'+aK5<{25r~$
    JTrJBeX+jYxHs}+;7{mJZ]ZG7='GklakiXaZ'paJo$#3lmj,XD7='v5#g{xZ's2EvVs?~5HEz=w7
    {j<=^**5@5QKRr}jX<wBl3]1^]Qz!u+Z7#=5US\'D=H_>,$}r5]^$z{}+}x[#[\u]\7KuQ]Vsk!=
    'KQjuzlZ*xD3Tx!aGum+sQIm{O^'<w2B@1nYBA;}nzF'{@;E[Tk=,}Zis2>#RXk0E}2U-]T[YIrG
    so$pH'UaN1<O-{'KT^R{JU}=;#q,o<B-'<wpR>l^]m{v,UE>5*<^?D'3+3AC5XeVOlW]\jzi=mJe
    RTuciDmkx>AYl^$AR[IO1k33BZIrzOu3Cjpo[pTsEmY]uE+xR=T3CEC7O*ewlB}vIW+-]rzB*aQX
    IxxIATD~'I?YJ>z=TB#!QXDsxjzm=o+=l*YY"FB]Z{k{aIz'xAv\^pTzC;zuTKk1jT#w;@l!$mAX
    B\a'K~Q;QSjriw,E7o#e-2vZJQrQ_[%,~ensGe=-_*-=D?I_zXJDHoUI>nDmEBOx>^@Dw[,#>'=^
    7n;uXe@1B\^ElnKx3W=$xJTs>x>'BY}_YkaJ,s?6~{QGP^$$]5*K+~B>J^%ECIZHa<XpOE<Kxo*a
    R+u}5R#v3uvIluJG%glaK?7^R,@YKVX{5x'QiYeKBiECBQBHBaB>TkT$#*u=o@OB{$N[Cx=~<z]]
    $=2O@BJ,#l{qmA^#p-]?i1,*rrI!xn\2o#ZJ5a[w\=,}rv1VkwG;aY+J$C>Y;<C~$x@$#'>}y)n{
    w~law$Hl+n;rVToC+xRW7Rwo1#[nx!Hxn_'><'3j\]J\CT$<D[X1{EWr\T=^j{1+uHujHJ-X*sN*
    ~s'}27EjD;zhe3pXpvwz[o,[0O7rEU}'W{\52e}pl}n',bEJ~o$K$+2jTpY]DK(<]{~4*^!<+U2r
    -wuO1}K-ZYDKf;D0!$x2,EA1IoelH5-ZzS,I^7x2K+vX>{IO1^WtjV$saR?7^y'sB>DT]?HUd$6n
    $puezro]aDC^2^o[JIXB-wU8aHH29>aNI;<!,Q51B!wwQxB2[i}_\7Hs"OE5v1xrraa~>jJC?DRa
    ^s!a2Y-AH*{nu]OmoOpUoH[$rA7-IJ[ws/i1iDoKmsk7v7;E><DnH7[7^'IIDBQUIok_5Q=;},T+
    !_S/:#r?<F>X;@UB~!;\E*'}VXRT<-<TU'~n2C=X]ra*^@!731m7CpWv3sv.pmU7OJzJ{x#Og7jA
    m|w5<,5w7TV$V^qE;{>wD\3XAH\MlNBWurvB~?Q@-K)''aGs[23G\TXG\1n>D[u*al[OI-A'<+}W
    7T#?AwVk9]?s2[$Vep&sr{+BuoViE@;5iBE%S7l=YG<x]~^H5%LnHj[1xP]Z'Ex\ZH7InxTx!IN_
    sOZ]r3+rNByE}>_JVmI;_x3QEWesRlibC!ABs2\Ijw_]Ii=,Z{+[Q~JeQu1uM[WamFEl,u}iV\Vs
    aeB25T*XKrzCU#O2+{z\[~Mcz2EmO'vi[vT3=>=jQnVzeAsQi\}QDIAa*}BQ_tIZY[e'>XM@[#{9
    {{5I^2U^9heUCO#T'[{YVC}wr=q'6Q];vPHO\{CXZ!]YZXRn_\Vk8'RRpw*ou$GKYRIG}I35Eo>G
    !\ZlW\!'a.Qw<o*\E~aBUo(*ZTj{$ax4oAKE4~UU?lRD[AeavKOIZy<a$\\G{}m+xrw,XucAju_{
    {Qx\cX1IAxTaWM/7Pzm<Hps#;aB5?o3>vupQJv1>l-Oz^GBWvTwBT!<o;Bn]X-AGaUBO<9^R7pBa
    oR=B5[WQ1[25s{O2\]XI@Rt{j!B7$_=k}$XQ}!EH[VKr<]'hkTKA:;Gk2?U]vf\>7eA*poEaYUCv
    W7%?H^WBdH<wC|$J$\v@=wKs$k-ResxX<XxvYDlO~p*vm=.R=,anG+?kHXUeYk^5jHm&7O$ZEB^m
    ]l;>/W$wuxZ]'QGXoN\Wz}zO__7I^Q?w}n[}^@]hs*]ussYT@7]G0z\7x7ZVZ7#XYpBHHCj[+K[{
    AT=eEp<a<K}~rp3~Uw5vpZDa>=\p<F0Tz@H;X__C+RoGmWp)7VQw5J=^WT*,\D[;1u=2q;Aju7e;
    RsJ1vCXQ'j_XY#,@Kexu!,#@B^m;$]splE7<!s*VDzY,AsKpHZB[2[a\-oJ7rF^pl~{Gk{Q;e1jT
    j{$#VkUn~pS_gRwXovJ5w'5N{UE]@jWp~a$mx2D##$BEW1,+Gl,A1{Rk;'A\XO[o3<{nF||AE_eC
    7UkE>YXnwQH\3GWV-Dso;7UoYY[T9Je>Q^-m[U*Wwp?I{<s~!R{>kBr,!#lB[F[*aW\VwYUlk_ve
    ;#GneT_lrrv!!=i'[a_HXxX+KDs<]]]zA<@eEe-jm$~E-@>^Sa-_s\;[svsBIk,2Yn*Yp9R-{uk<
    +#JjuKD;$sTnvmo?\R@p'aZ'a![;Ur7{}!uTB@neT#{Q}iIdm=op_v{ZOa*C\a*#G}KZ9i<{]Z>I
    #,Cf[?sI'~Q#iz,2*x!*5c-jp^F"epC}^WYz>NRlKUV?CTw]px2w7{Q72QU,up1{;sU{W2T';YBB
    eCBO1{WBk[ZlIY11Wwel$wJOKu3nKsT<[<DuE[VOa*X\XB#<2{eBB+,,u$KO\<4"<>NYs*iYk-,p
    5$k![
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!##AT7WBH3;8ZX+=WY;?}a7,]wA?7IY-+t&wa1[yN}-[2o1WQ!+E#1^5D|DksiGZD]Mv3Wx5<
    j*VTm[rZ,%lwJ#*+[[o_n=['CW!Ul$HUlIC7BA,O#vGi[wp3xag7Jl-1R7IwsGr}?RJ|R*#I~n7@
    (FoC1Dre5U;IKH.t(e2~w7K@zG7n}}lSIQeZI@'2j|VY~O2[{p~V)TnW@$R25|BB\2Pze-j|~Tpp
    7v@2RR1-XY[OEBuZmYJwv!}[oj_#W5R-bq9Z6:JT{[}<\2E+H*JHK<rV.eNesw<Co>JDG=<$$1GD
    kw#'+ze1-]kIO{-xzvW,#~n'ijJ~r@$GTQr_=],J\za^;VTu53xo]!r>Dj[[e=C%i<nK#X-;!}[B
    r?K@aGDun[alMvi\Ryl<x}3Y\oXU_a[;+1i-~~arlDf=WJ!XQw^:n']WvdJDr]mIEmB#bUEAYJ7X
    2w+mA]W]Vf|m<Uu\3<_27kY^Z>{jZCZI.Im>R5uGR#$k+B9eZ}H&):vIi[IiJx'<_QN~wB'r_e{I
    R\$jOAX}QUA72!*+r_xD}EDtawl,=sY>!nl,{TKW}iD@72_J*WGAEQp>l-o[SV\+;^lzmBx\V{E'
    }?we{yIlKkaGTFI\+E~RJ_Zjr-1<t,@=a5?!#Qw'[8Ta{<@H1!K5{1ftv,p,zIT-:E<z\-Iit^?]
    j_Kn$taaC}^rY?<H3$GWjELoUz^1S>_peOZn@p1Q,I~Z}ljlWlY^[#}>IV>$j6s?@ooCkKLvWA,B
    UwU}Hj@XYaw#eu{B[X''px3_GWrNC+l17]KI1A@uJT,sb<nUz2lja<{KTs}a=FQ,nM<n3-r{WR[i
    7)Ar<Q~$^I<\#Bwr{]T}a["eTBo*z7Z#wx3?S4vEnnp_Vz
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#+lk@ojQ<1TmH*e<EEa2QbWIJ]7'Wa]2^i&wa1[y<Cb?'Oz}oW14'\-1B_?JZ-=@woX<}Q;}
    25'TX7+2U{){Ck;G$k\s{ErsSKwJUz^;};-z@z'CX<Y\W=&~{'iHa*++}Vrsk@m72OoBDQ}Gms?.
    E*;zJYzGoCA5O}a-e*$[_EBo}n@~pnKu\?EB*3,,7iOem']i{=e<0<EQkow~zu7vBf[JCT9Y*iDq
    [pl?h=ImE${-r&_EZHvOU]kY#^<,A]:rx*sJRivlH,DGH2Ao_ouVL;-p2QCJXIYT11Tv<XAj#J7,
    ^z\ivOmv7}3oZXj\XjY+wT5vXsCC>lUX,DTnak7WRzJO]8iwrKRr*krHI=V!C]rmp'zE1VFDG[@H
    vuI!-E3}msvVUv?uDo^WeVul1iQW'_kWD+Q8]@JG>xeW}\p$h3Y*xCk,o@jIuYs7*X\^J}s=Z[k>
    UTB<xT}ne~R>o3O?Tpj2,RziXx\,Aa$X5_o-RY$v7qs;Ewl*UOm'Z=HX2I/'\:|[2+;^z}R:k'Bv
    rkY1lUzD$OOW'*k_onoG8-=j5z+u_}@'iQ?Z@U77v~aTopT~'CXpG[j?Xvm*VuDO<#1w[[k+?12J
    \\$,u^5U\xpon7o+n,}JZxE7wJ[@Yl{Z@bQoQ>r;Vu5\VK=>rAQ~<u+HO5fQT~U51C_^$rK+1*\T
    ww;r3-I:ar12^?z<)\G71{vu}r5B#-sVY=='ra'Xr"Es#D+UB~;Ejxg[uwKUA+7O/7il3TEEB97r
    K;l>vZ*-x=dl4"gJ-X]VG+D-G_21cn+_ajWZATsH<wLRETv}uCGrnx[*O7D%0!C[xJlB_5n{DVw]
    [7lIk&T+Tx\eH}='EBxlHxU';X)Xe1Hl2<?2+Y!3'r_suontYU@*|R}113nzp]mxznE]'rE@I7\\
    YNu_B=}pX'CIZ?.Qj?j!j\~Ir+wUAn]w-'l([ajaTOlpOv1=eG+WQBuI/5Z}H1m[=\5TTI1Di9Ke
    J^H'Z<<pv>:ru$J$2OD$QjGCl-CAsuC#jls}2e3H6@,s3kjUnrjZn^[=s9]5o-P]*p<(kYkT%MO[
    ?<?l=v5(^i
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#,Y_D6>Ckm{CoWR\,'4~r;<CnJ?[Q#u-7k[6EtE3R36lAK?nvVnanL4FhxOOTp-]my?oHE>5
    zT<'k$_rPlwJ#*+[[o_n=['CW!Ul$HUl1U<@BIM+1a-iIAH-Xzi0[3oK'3e_]W=5AO<'3j&njzGo
    U'X\SR3*'s@QeIg}mUoE>~=S1@3Ac"4bA}<IiYwIR+loIZVvP<UTwI-m$e*v]cl#_Et}Jxz}<mII
    ZZEDv;<hBC,!^<}O#aAs^kv?{vmm6[oAe]Wj$CJO?~ATTu+<_\'ACv7u_*-Vr,]J[OKu{9U'7pok
    W\*nv$%ZB5#opz[K'@@l,zz$;Glr'$53sW+I4)[>,\=>n2{Uu\r1<$\'sJ3l!*j_XEzaZx]e]U>A
    '!r{O@e2z'<>s;eTp,7$YGTwJY}a^ZD2xl[#@zHo~j{9UsT~.-w2X^e}K<EUIY=CI>5T<UE@2H_@
    _RY[E1>ujrvQ-F?{<kH5_Hj2\~#-;C?5uln1+BNN*?]m|z;=#~wQ5rr#C5;1iXx<T,O-zfH-j7RK
    vnUYZH,-n>t1qE"}k$_|s>>7L5d?+aV],T2=;*Z+XQCYx*>G1G>wjQ^-U*ZrR#UmoD=u^weZTwX,
    Ena~A!<*VAUx>~mrRoxIiEx_^[_^Q1!GY\#QnEW>\sKhkUUID?<<IY'],OBC6VT{E5}7ZR$j1HYj
    v|rz}[\^<jV'-?f']\D]j'AUXUWeJXQIB#oo#DrzG,UR].e^ZlIzpjvZKjUX*Tj*[=yZ^r#\AIVs
    zjIkIxX*!Y;pCkwEX5uV,weos#p>'a-l2]T#wDkrTERg#]BOG>$s^O=J=i-*2}s#?x[[WrTr1WKl
    RCDn,=Ymf~=\~=u73UD<'x]Do_apje*,DTrV\.$zT1>[~a^!AaBA-U<][K{I'em]KGT]\Z,p2?RC
    VmvlW\G+~->AuCqaTeQD3Uz1m$CQwsa1#JzDe5C;},B}\4Tz5{V#3,RC5e+7A[<^KE?zrvr_mwV{
    <~Z56*ko'Y;1e_[2aX's[:3_\nInHK
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#J[kZ#}{]Y<,WEjNs7z3\yCnJ?[Q#~,[k[6EtEuJI6lXRmnpjT5nn[6}0^!R2;]Q[9^@2Ken
    C?pHQzvjk}]irz!w$wIi@DFzx^QI}VCXvopV'[QNP7uZzs@;ABHQ1RXBYQ+ji:eBA{Gn5kp;]#l'
    kQ'ZQis+O?r]WT(&F)M"3.M#j=;Gj+XtOa\VsH,ivO'=T[OG=[-oarAsy]Bv{;VQ]=xR{;l{V5[w
    74DA{jxx1D$pr\lDv7rHA_3^7IxeG<1o+k@[\*K>'[3_dTxlHw]>zp@uOnCmQTIxH9TXX+wj5aQ!
    _WI,?zJsXIr+,YOBU{!pIs~|v;@+]7QTpj\Jf*X-x/e7DJviDYYqVu_aJC2_WUnB-Dp-_KZ],\3E
    ~<Js?qsz<7Z>]X^\9Ip;@2>sz_5?'wxm]bYX$k@<'s/r$nV#n*s\m>z-s5k@e$r}bJOAp;lO5Zl7
    +>Un<TEKwUD<ABWHX~tlT\inxTO+AzU#Snw'_j*#efTLC!zQ'A3\o-$<,7lR-TZ7UTW7rYXm^#T2
    2sRn\?QusvvpL[zA^E<}Ek+OBu}l[iI,Ta][ZW{Xe3p?_&U}]T+rH+]s7Y#>'<85]piC1RR]V$>J
    oTK^_mC@_K{$V{7HG;UtTr[V<X7?B$1eq#pwrYl7~(p,CVe2OTMeRTCz>$i,Yw@>E'=jGBeTl<$v
    ^-W^neQ2Y\<tDK@U7aU-D*;s};JolA^GOw;u:!wv-xA5i.^aR?r7Y2OxE?jw{zUz}7Y<['BX3W^W
    CR,{~p-V^k}KIQD01vz}rlR'HjQ;XVo7@aE7jj~^B-~OI?\$dUH><'-_,l#_V2YxW<jYG*pJ!L,k
    QruQlW+xGujA}[G;3{iIW,OemGUe]QQFkp+eGon[_]o>,ZX2Xz{KCrUv!5X+Y1eRXB+3R$HuI2IV
    3'[H*,pvrxRGI!Cv[VD}'rZXzuIsejxn[HQxi{jBQwW@0Q'me#}Br3>^DiI?,vGRjVs\U)5J}Af5
    @l}/o+a^u7*uH_TvI#~@[{Bp]*3IuB2kn$IT0Ei+Bi+\[,CX-o[2UVzD*rT1lk]ID[;HaEBI~***
    5vV+Q=rxpG*QJI'=e~DBiE5[Iaaln3Lnr]jHRQA5aKICiWuj2A'r5pvB=s'wC{aOB~r;^\#7i+RE
    'okpYCEo^HvYeB57~,sWB}^)+>O>q]'TOKo+TdrvmOT-sV#Dks*7VVTsR$lm1<}I5-w1in=a-~r!
    ZaV@n7Z1X}*{}u<{uDwto]?aaAw^]2I_GsYUr,'T8E{_psH[T2s*GpJBG.LsD;T=a>I}H+Tt{vG@
    [W2l{^JU2Q;aU*r7lul[1_u+fY2'Be[sx'EzZDrva=mvz}i@zpw;DX5QZvHpKExCU4lXZA;Iv<BV
    +~]r7ni\>~D@G+'>E1QUCX-Q;$]~{QoKjAHI?OHGvp=ZQW;$oi:,HQVwO,]I*z_Ovsn*1R@I-5Te
    jv\q5DAz61>K@IK)DRuJqwjr7<TV2spx@ye{-CYj<suCYTR#!O:wXVjB3[;?rB<kYJKHoBZYAsKZ
    Lv~j7EEOw[+I#ivxJ#7E1l}HI~7sB-j~*rvR]jY]rQ#K+,'~ZH^XDr2*;Jx][*;XXm=sY_{2s/l+
    CR2B#[TE?<_v#U<<1Ii>Jn[e!;L-[D*F-vZjVj2j#<UVweB$~5ne*wT5}m'ID5RO~<_,!QK\i7K,
    @={;'H1W}-aev[[J}[B^#,5>F1ope(V}XJ=3u+?[lGBJux=KO1bRroY:^<IE^Cwo,sC7'B$VNV]3
    p@xYIQH+E{^ml,nRBYQx75YRDjx_#.,jX>aUzmR1C=$R{m$]UH1R\}E7$,~5plv,?RTV+jNOCio=
    u5W+wlvE?}B7BBT|,Cv+^wJ!|Q?vOouQ!BRXa\\Y@bRo?TqY~e{x#AKBI@A+Q;o^Tj['G_lEAH-E
    D?kx;~B4E[5\gnswkJOB7M_<YB]Kz,=oTJY+oY'\~7#<Ok'\B~[CVDxX+=[!Deu]QCkAnJ{<Xkus
    laYzinmA}u~,jCK\kx_"_EAGCBx1m<s5[^~opCiXoUm-o#Brkz]{&(,KwX-UVJ%LYG!@q/#TC}k1
    mTe1-Y{ppGbH1ejj5kRtv2$=9v~xUpIJmCpxZ*zZ?7zx3)7m<B$$mZ-IQ}[\CEAB]]a[A$n'kB,H
    GjyT[}BPaI~JZ<*=p+l$A^Ur<*+TsQ+*ye{]=:HvsQ<oUlisx*E[T2joQ#>YmrR;J,,LnsoYB,<^
    eCK<z!maR#X'}^^,IO=X$xG]'_Q\[*ATLAen>}r*CJ7zp0z{a]%2{[X<G[2D#5Q}x][UHT?OVZv>
    +5QmBk+QIA7{'C{DBKW<^p!urVi~RkEQne#,pxB#]=OvIW;BOAZl2;3TTGrsQK*J>Ro1?QO_YEIj
    E*[[wlT5&5VVl<a(oa+?rp^{Cxj[;B+}z{=e;q}YI$GQVXTv!Ai1H>zi5aiO]n)!X(AHZz#RG};^
    sW3(z1,+8UOi!W}YE3H>E!_{'r$B;R;<'mCjv[;77c1>Tj7I]EjR;KIUQ1:Q~R{pwv-^TJBhrC!C
    R\i$CI'-DsZUkO+EtuDI}*'iD2,ua*;7ltAl[mrIua#O7u]<aZo;]I+5H-$a^Blw>XH<1a}2+D'>
    ID$Q|:Qi5;I\u@PB{v1A<T7vJp]R\YoIsK7!x<;\Q?2H^C'C!>AXsrjmXO^k$iO5,Imwj2~*^exJ
    pjUmCDRoRI\Q;zEvy#X\G<j,OaUaJnsnA?UCC193$kKsj2jnn7Beei+YG\o'Kp$X=[ZBsl5r*H+-
    nJnYa>Y!=7EXjn!kCV~++lCDA7_w7[s$9.Rxvx7o~3=}'U[KlirEs}9!^i#Y>H$3C=?v3GjU5ZJK
    '=O[aRQkV<UU.ejjn^D]$Zz@T|ar139<Q#o}U-5iXm@'i\BO-;}3<ppf;<'Dww7'}lsO51us8C-m
    ;p*zmp-}D!T~5}?@v@[AB^KUkoBJ}}<BIAC1=LJ\U,m<YD5v<=moWuUTmphG57\vKYsjo>ns\I3'
    [?s[DnJq|>jv>DY+Tv{!~?5X]iv2u@_~RlkaRDYBwKeWEwYG}AQ0]e_{@>5!k};zeU{Otsp$3Ep{
    _vJQ*I!*@>r3=/=l#r0nHlROo]WfjI,Q}XmjT}[r[zE]kl>X1s{{#7lYC1^Q,[mRVjvlOnpw2CI1
    z15H7noXp]zx%vUU-CGkW2oY*_!<oiVADffl\T}JDouIow$";lW'i*;uE21_IZ;HBkJ[xC77N@,o
    XQHWEFID<*zIz-(\Urz*mG3a^kv3*o^QlGjJlWW]ECeBJ$<rQ1w&G;jWrxG=1-*2}A]@~OQIeDT=
    EWQrX>^^-*1r1QW>)XIO{ATK><DI;En,HGI~[Vp{r$3>J';sYu[azGkjJQR-C*XpWGE@71<17CK[
    ?{a^55x{5EBj^XOzV\RKj9CBK^ZT[='\H3DB,ev@vC{O~p>Ozo}W>{*e$TurVv,J}1#G$'~XonV7
    THW-+!l5GvXp~l}?n=\vz~CIvQYH_#[GTl[7_GmGDK^Ew>W$rY<>TXebksY#.(x2E~$zjasll-uw
    JR]v!CUjYz,ApDPwYAO'KO*'np,*1Wp\Z;<ieIBUj+E?D7+XB@#F=x={^mZVrC~?Y_wm^[1YtGaE
    TJs,^$[EHPqZe[=:aD2*p*Y{N.3'Ek_T,kOJGCtzXJ+^Yzo9X'p~<^a[B?Iz1a-jmD~@zB1A]'HZ
    v?ET_CAjz]7X$W^eh^n}D,oAK<ap~}w}a'\1InD,@suQ3=7vlazTzS^V$XJT+s1-Ep$-!aT>v<mY
    G<&Qi;^g<Y+{jk=xR*}nB^kHjDskh,]uY$<BaW[3=pUZ@xx#xs!\*HjzoR{A5a711=nZpv[_Ol@[
    $ZnQI4euY3?-n>8?s+@,jJ+IAH,a<'TU^OJ[VW1=!W}gk7-{37*GSr'jo?${pFf=7I;'EzXLDGQH
    3V]J^ZZRuGr^eI@__+Qr<D=mE*XWC?5{;*r*WQlUHwXG;IQZ;nJ##sn+KT!e*]}Jl-J!{BsoK*AD
    Gv#{+E[kpp2#(ml=QRl![^+R;u*[u[QTZ~{$;{e'~LwAID|kG2n:~pY]s}Z-8nQ@=e1=r%>vwWU7
    z#,k}r0;wX@j#w5{OunZ^G>%FNRj*ox;Ds-sBuZw<KpKWD7#D~1vir>Cj}*npUBTvkGo5-OaW_li
    @p(rj-BBXT]l^]Ym-\r!C3j);,7$l!!axk~*~wDQYor!wjj#,inBJeW5RmKu@DYwnw3{,_mU|$*s
    J_}2avrl!Bq[^XW)<5<3j{$T3}aZ~z[nkrw=wnCV:$YxK^7Hx]XxO(I}1\V6!+lDrz>3XxE=^GDi
    U[13+,so6Oms]m_[!-^'\SkOYI1=]lI31e#r5<-+~E8~ATB$aC@3o@~GJ1KHrKjj7-n7<e#1\Vxp
    YOus+$<C+!IBosuLsIRC5w{a}'KO1mUkIpmYpXW=6V,OKO\>jO'n-{zA$eUeY[],WEuY>F2Y1OrE
    XA^BI<l\l+uGKE~An~^*$Vj_]\uI@nE-E56mDwYE>X~_jn{s[+uGK7Bk_YaDRWw;XY!uz#_4OGw{
    x<JB]H$[v*n!RkD3HYZ\Brz$X+,<UUr#B*W-v1D2@+E]=,EJYwpnKYJ5^WOO;ts><~52n77#W}v{
    mHX--[!oQXY'rJ;BmsCa\l"KYJJ-YX,qd>C!z-e+JZ-wzBe]zT9a<Il*><_g_pX^*7##$KTuYr7x
    xuG~5uZ;G2~EOZR;(<'?BYOxoI}Ol?E=zA^HxqOEX=sIZC,\IXiY>D$A1+XTrw~a]QT5]w^uj\'Y
    KUe+^GLw>K<n7]r'}B[P,W<I2OE#2nAnt]'zG'j,n]KOuXeICVRjC']7JoZJU+Hua_Ix'[~pu;<O
    #^071a2J&D&T\in{YIU$^7-wHB\eW1D#1YE[OJHjvvrxY$}~waDGklAC'xr7*Cj[uY{lu${O*ZVE
    ~>CWCpXY\HeTEDK>s1X\kxa@<mW]mR~Hl~=;1AsMBOk\=(V_uuzzJEs^WJow~A>V@JGEroAnoAH_
    G^Qob]oXeBGm*M*w+5k]:3r'lO2J}ouO~'&pzCja<<~=,$3[kHDOxajsI;_D]!EQ5VW:RR3@2Qev
    0BiVYuTR+b_+T7C~}^e1+XbOC]vK\2sJ5GQGJ{m'<{AoHeRZ\A73eITRGA!Z_{W_J+JD_;oHGU?O
    Z;7a_=K:]35Jn>7^l3DAe'w>Ox_YpA~5p#Qpfgw'[[om'_|qRI-?r;~$|_2+\kB=DL
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#VEJ'R$IWv0GBq{sOk-Gn-lArsmD+*+E#$AY}[^@,?t^n=?IjOA}T,?%FPzpe$uUD-CJ_eU$
    jmjum[rZ,%lwJ#*+[[o_n=['CW!Ul$HUls5QxGR_#^xkUUp~T+HU[7K<&]JK*N5[i#IUAA^0Se>Q
    GOAKj7!ZV_s!r_<QOX}#5e@wv$sv$i7#z|UR{[Y]}!jD^_F-r]X^-zGsI,x$;'UMqoun}q@U]{G2
    -HzwBsz5\Znx~#C7aC6_V{7o2K\X^^,RlQGZX<pI$O3|67S<j}pK$oKRnQXL,{UmDk$J][[k}Q#r
    k$#^BQ>^T1,UrXD!;p^-^m7@R';;5XJ?*^zuOz}]*]<#W'aTPpkWk~G@kaEYH)uY]WI1{'eHKUn_
    =-JpAl\>HZ{opARz]Q!l_CCU{v,*~2-YxVolE5$anY4Q2QDOzeA,T=!*@v$s\{ZpBGHPFs{W_lH1
    #]=YG[\pj2Vi#z+-{&f>Ym,[@>p'+w>n=K=BC{-aG=7$Bkl7kARTBk\nDm3vQw#7QXmi51nJ<{ow
    EHap>R}lRJ@nr7+:_f~HoUE'2m2>'rT}Dmw\Y}'ul'2$HJH{$^_R?YZ(o?3sjl>;jRWl5KCkP--H
    >!-$RgZY]-&7k2?_ZE<&=Z!~3^!-Gp#ui_lTz7W>ox3r_k1;y>}3[[OXmh,_^I!>z]RsY?*@~[mx
    !?ri+'OWz$j_e;V@RoVAo{/F-E}-#e1put(o]=i'B*vje=O*1U*QAe$va^A}=Y5'W3vX*_]s1ZT#
    <_Rm_mxYH}-UY4C#@K'75r--,]Ua_X~'pkE${AxF|RJ]mX1aQ_\-Bieks+GmRw<a*iA\,[uuoQmK
    #nUOofC3$m7'=OXHXu1IxaJ]]1';lVA\*\u+<-VBET'oT@YrZHm^>!kEm{l~j7s[<m~OiT:eZrZK
    Ho=lX@\m>OO'2<z>]HrFNzV_2y*z*7nHr2Y7p#M0#7Der_avba1C,[VUnZ'AT[gWa3>^Gir$nT~>
    E=e/HeK]csz@\vrU]CjnTYi2uIKr7BToo\XIZ(@x;7ln+D7[T2+sQ#a7H3Rh}YZ~R-W?AYrDS>6h
    s<7ZD[B~Ra'jF-{^o::#+~r3ww!erOz\3'\a>vAWxRE2Q,pevsiH^lAA.Gn^2+Bi~]xW#rEz}vRw
    _7e[EI#$xV1v[FDEH-q>G}7$!>mgAjQ1njA>c?7OO"6cIQ+]yTYnU^'+@Bk2D/*H++(aRpk<a2a1
    H=E${DXL"!G*2^V3W#TUpB5A@oe@,vi<@]e*X:H}!~DkA=*H]A*ICC;er[|l3&[~@2BHB=-]k37G
    v[^'r+*OBRfH-V7REvn\G\n>X+z[#$ZW7KIE<3\EE\jHj']ZE?m}#^'vAj#JI?OrTuaQUZxoj;QK
    ws1uBa^En<}+DA=~\-@(XswJpGvTR^7^=!p_t_2Y>l3;pK\#<6=9cGx?AB#Q?#n_sjBT-l+T?V=>
    xpWW~BWX>\Ooe,2EQ@G_wKo\E+\0$u2'=KX'(Y$BRcf_EH2{Tan'X{s]I@HpTpGf[=J5B#m~Y>n[
    gWCpY]-3OHp\Kux'',{11IHReb{7nC_[uZ!5+RRr7wl@OT|VoRp'5Y#7slz<}T[x$T@IG_C]@*G@
    v_jD?7o[IQjGp\<>'\<XxsoEGEihrUHCGWa2UrwX;C5e\VI\hk*WoIOupe\EvI:)R$B5p#=<75Z+
    $<KTH\\>~'@@\o#G@<x5%=}nQPIq~\jlIinaC<GAk{JkBx[}1-ZTlW~xsoRW<-!rDNSBZDmsa75A
    A]ngkNKDQ@a+{7V~sQj|xu[!Y!o*?H~_iT}2{jJW!E~*{X3UsiCO/Ava33sVDCZ-msoX~oaXsp3B
    m-E1*_2x5{o7!]S5iKuR_@=[RxKCu~n]~=p7[Q{_Ir=pU<e*!>~msx*E{n;T>r,C$v'vC{2^C@I^
    GZABWs2$O}joe+AvW,;1,?*(v[A2$w;?Un6L*}G#*\^=>O~xgZaD'@_kx]$v,j}v=h,aG~\[\C$s
    B\5rkBV+OiEo{s&GZ~sIr}_Z[D!\RmThC[IZ5Ow#OCVu[nHa#o{,3Gs}2r>X7JY7o}E\!xQ*u>3-
    BZW~Hj@=VoC~Ue[YYp']Sx\\e>AGB[zkHvEK'Wr'>e7H'aoRs;p=n4(3},piQJ_o=ZVwT_e^\I~D
    n}vj\5}l2Bak\p{!_754z[VT:]eA2#Y7eyceV[V{jZ;ao#?IWW[wxC[7@K_q]_,,~tTQ\AP:zi-Q
    *_xDYTQ><Ex'@-C''!=+Sk>^weXnnGmDY^1jx(X\3-p1w{ka;$*AY1Okwj3-2]k*~xjz12GGHHHa
    +UDD@jW,D*1xoR$QlC;TB{fj[ol{eVGD2Xr2{'m_}W\('R{<H$#G\r*jjX5{yrJ_$2plro^[}"?j
    mZUTOjsHpQU=r{MI{lZkU<WhnTvOTj+*H'nx_G}>:~*>@$Enn^1u}'p\i=p#R}?<'EXTe=JlC|~p
    o@<p;{wI'Y-'VaB~]CpG$Bl,W,>Dlv#z+j$6xnH_VZxKA=s>*eeWQQkj}2RnEJ*~LQunR}1WR_mm
    GC{,2XAT>B_o^Tn}{*$^KV?lOrD=i:!_ETz^ATx7zs.;vVevoiE:j~s3.~pQ,<>a,TwO*TIuwxTV
    i#^{_Ol@'p\pu='-@T_3rl=5YP4GIu*R!nk>^I[*C[,nC,#se{D$-5w?^T[tr$K=z_ZZEY<BW]W;
    CnVXRI,?X,$@|;R}[:l$]#=lA-ulUDk}A*r'TEprjYxYvI\?~x=a{^XxR[~l-C}\w^5H_{#H;pi]
    <Do(B\U2rO\$-_[>Q3KT_DA5m[O7UBlRsQW[Vi\<Ci=Vs5lQA$QJr\+@'}ekOl@7Z>ACXQaaor*U
    1w3^!=D=cJU}BuD=-lmlr|^nu[;'xxAU-Ck{[7Ga{Kio,UdI%ip-7lmo@?a^}AG,la'GKG\!]d[@
    K5HXx'jD;[}F~p#C<pw$$R*@xXr,&QGr]~^Y>EsA#ZrvD<v<TtiQ?s$B+3vk_}GiAz%7G@7i5AU,
    Bun,D>YV2zu_@*GxZ\lnI?7^xQs3w~YIE-{<YC_:Cw}@EXA{VVX$[Cnea=Z1*'@<AG{'(l7+\NZE
    ]AQ*XYH\^2nIz\d?Y-}xdO'H>CR^z3j~lqa><p5,YU*7~}tuX@+UoQS<TUTnliR:que-aI7]@fe0
    ~rwUC(OQ*ElUA-}UzX@|m=]$.]sk>j?;k7?ak%=C,pq)pM*>sQ*p>KIwIpNXIvvv;-Dr*CrIX!?t
    er-'WH$u!BBp5/iHY^uECH2tr,_;6e?={krZ1vv!#>oBT5kJ5z"z~xH^~2u}GDKmsHDE<J?2l=Wj
    #*-{pVYa1+Qsj,CnQ3G965RD^~$HG^J~{-\YVr?WuJvk$#l3TI#1r'TDv%vH;G;7@,w-V3T,xR$,
    CVEoiu!*EOlK^2VUr^GTalB=k$;zA5YAY~=7\z{]_I^GU#We>C5i@@#Qn-!]\X['<EQnI[$a7Bzl
    jT}E]W1p@WX=Tx;-1!_X@@^3VYnColIOmI]5u>x^Ix{C-Hrw--{-lVDpWD'!rT7WAvJ[ARC}+J#}
    ={D=5#7RT3',eROVA<2o{}EiQRZT$p$p=+IBgl3$uTn7OB+KT.j*>xCV>B=3Z'aY'jV}EERpIE^e
    _^1MS@[sCCmj7Rp,}hua$1.C-K?mEw_Bj2k<}tr}{G&uGu~/B*2TRO=~|MrRkszRZ;fAn*AaDam.
    IVX2#<RJ_{QY$D>o]O[WZ_rXBBO;7_$HC&e^@=c%ma-~s}>jwp*zI,Xw5hA7W,_KX$=M7_Z-~\*$
    ;*VX7D7\$@+s![ns5pWBO',+o{5ZT_#7Aj{A!<~IY{wx*CrIM9Uw*Jl!+Qq}z[jrww{1#^O$;zI]
    {V-AC~z*aj,E1w-I5l}?<Jw:Y$-uVQW!,T[UzT+E_<$kRJ{]5D}GJI*v=vBBrT'3gCG$aqaekpJY
    'UBv[,&$Y<]@wRCQz5;=>lr^Bz^@>]E"2}UYZO<5B?{\W]~;\\^J)kQ+>Q11{_l^2y?T1E}&zGk=
    *BKan*ZkX,4jmXpB>Wv3\1-YR-TV<,>ZQVRC\H-u'aI_ZuoQ[7W1JVZ=i{!+X;UXE5<};\sQKw$n
    Bx_<=mocY;TV]a^[vevJ=vipfo{X,u,OV$\Z*V}WD^#~sV<vkG~aka5O-{*!*3wIsQRz~$w-ripY
    A%<IW{~j]3Vr~Bx~<=,,X{nR^{p#nH:-7a3qir_<U>W2w]#D>x!U15$E]vsrd'[,sH_o2QHC$'JW
    ,U,\$xxz3p2*CRIV?T1u!dBeGQ!B^GX&/k<T[jWOY{\'XD*@,Y;x[=R3CDYu~#TvQ'soxB3=emQn
    {DOvUzD5][VAjROTz3ra{Uv5#IaC'Q'*J_]'-on=X1-BE~TsWCUC*[Di>EQ!@RXz;zYe1wjXD\#{
    T?\o,=}sowxVuJCVUxCx#3-D!P=prrTs}<ip2Ar-z+=iU-~>3nVRjsY}_J>,m+@lGA5wlerU1U#}
    -Ea'kQYwraO~_~$][,DYGw\EQJ$pjV5RZ#f?]x;.=i\H~9kx_uDZwIfUo7ep<2p#s}15\1J'<nlw
    zGo"B_G'B~-KHDKAN3jQ3ln^wWBHXQ=TIzEJsH+}#_O'7~vG1IYG#h*uDjul@@CHHGD-E<E=Hu_N
    X}D*PTGV5h&GYWsNR\$Ro[z[x5Y@RRH5tS'BHKpr2nHpA,\3pK_GBBCiU^I7X,=#rKir5vzJ7lHo
    <lZlXve@^n)O2j@T]1X^aU,xRiv|L)DA>;lB+Ek7p-r$rp^J{@x_>,x>JxeB<rSuQ~ERMeDTepO'
    <un1O7xr[D=UTx7H[8:_l#X1_DYzXJGopTOJ'm'[[>7zK@K3*'?WC*~^WE#1z_Jl+Z+$B.RGRB,+
    }Et8kVKJ3<+I]7#aYepElYi1L!>@u}+,Y@SGA,\EB*1-I<X^apx!I<Q%EimT}e^AOJjRheTpsJz!
    De^@5E4v<+[UYungUadjuG?$r^-sx~G*DK$rYj@ja^{e^oB}Iu+pkvm2^13H1nw1rR{{<zApK\kI
    3<<je=W^<~5+Ql3ZQADCTHBsf[K>O7ZvI5{vBe^?T'w><4;>@jYer'*o$+U<vj'\$>A,$R~Tj{xw
    }jz-z1C3UZdx]uKQvuH2oe>@]zruY?xR>oB}Y]~;oRn&><A~szipY?a+pBEIX[_U*zw2QeC*[U5p
    }GeE$UV\K^wOeAzRG#mBrXEZuBmpz1GpJ{*jN#r\!!a-UzIlvq5IojMS="v[@K7%=o7\VHonzCnl
    }Jjwg^T7sG@TU5,e+zVajH}DH#7=K\$+o$I2XwjzlvvAY,*5>FxlIO2TD^w[Z22]KH~sZ1DjQiiY
    TE5VVpK_A}/^lIlzRkKD[lk>]TaEn7#~]<$OW{[/z\'iY2}{[V?;;SVmJ~oYw-2[
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#kB=pu+li!5oR^n,YeTXY'pZ@Wo=sH_r_}Z-WKYk]?Ov{^X'mIDGT}T,*yekZ'*R7{1tzZa~
    {rn1-*X!zCC[EfkQ'Be-e]iXa[zx^QI}VCXvo=Iz<DNW}#n[z77B'kU'j}BJDQr-8NQ+gu1U~={}
    sBWzVHj#<iSsH~'1Hz!$x[@w<*E(In-8dm7j[]YYYK5w#o,A=\_@]>slaq/-$_\K{+YV${Zu}AHz
    {XAge;KOfY$Y[BVOUkXsOvVmwWX7$e@H}Gu_lC+2pipT\Rrs?tz5We;Xs-eo#XY5;rp._#AjI+aK
    xev5=OQ5!=[Ux2><rAz;HzB5#Y!@y{<2lY?<@L#z=a-$1~}q]m\KnxE5NYwz^wYp@~pn<m+;ox{K
    ^=#Y'sOZ[0?ARGRe5$)Y\YKHeO[=VHZtx/GzwJj@BXlwE'}YR=3Ye^ZIR1x5{k'w5DjW]D#Q1E_j
    73!s],IF~,kv'+!@oo~]HU-I^!j,BiB<vJIm=aJ-D~nmG&Np$*_]_}^:7lB~VvUE<_zV=e1pW7?~
    V*Di@5Q-~GjzRYe@Yu_\7[oHvCH~R\n5R2<7BxZB-^rsIT\x$i*l]2nXXaj!=UoH:,?RX[H+2o<H
    V*-!D,A,u=!=R1in@2jv]p2s,@7GRIeK1~pa24wj!uTEIXE<\HG@ul1@*WpVOJu\=s_Z~A<jNUO7
    [<H+eUDk-Xri*5m;Ti$o}MnTl$H{pYB({jiC^U+D[5=B4Op@7*oB2,oDY5GTRQ\+@^s\wJEpUVZ_
    *Vx*@*^C,uB?m}$}XTRIrdYGwOt^QAAJTzl7VlDeX<}N]U~C{}x$jA5-&[\2-1KCnJzn[}$7v39\
    ~O55[U;Qv{K'YBBQrD-VVY]U_RJ?h]A+7H1jnb7@Vs]2={A1jExnH^{[o$GqYar]B^Y7?\=u!l![
    }_]B[J15ap$-D7AeveEEY,wa2\1s+=pjW5JvtJ7m}+j2KBsW7YIAGZlAo4=U'D!}5]G*<-p-[,\U
    -~5olD2]AI*[I;7mnEHRI>g&''>Hs\2,[Ri$~j3~}RD<!AUpo+{2z;~]xl\pVp$O?7R??}vQKU=o
    @$a3olE1xi$[}HQuy\uH*)oCF?l5E>O#$1sJu,p^xEgB'i*aQ]j#Rkpf|'pr\.CYknz,R!is?^uB
    wQ*RAwCs}?YTo'n*'3pUDYwYlaW*Eu^Kx^bZ{e*_!pHjVZZI~3oz'x3RD,Djer?Z+CmxJwwj;on0
    OUaI5{DrRm,{DY131A2TKa-ws_KwrojWfv,'I!RzD$7pGg*,+v,noi^x+-{+'+I_i!Az\Ra<;!as
    H{i{I~lal3vu1^OG+7iO!_koUB#Y_kEonTQ-!-Qz[]JY><}e2J$T]a',uTj+C]I{jm|5s1DlkAsi
    Q@#A',jw>m>;'lHmAIs:>Vv3k+r2{j-B'xu+xrnr~o#oX+l!>wZ$8$2^R~-)C;}1*@-x2QG+*>v?
    IE_as$oe>H>7}*ZZ>QDl@o;_IaWE3T>kVrY[McHDX]Xzk;wa[~EiJ-]2I127pTr=u;tW*~ouArQ+
    A=,IDCs]nOu;EIJD\JzqzwE+>{A[Cxs;$lCv2'#1'?<u1{!\=ATDtCJ7Wd5Hn+Qev1Yl~[D29CaE
    T?>p!x]{!%iEGa!Ym3zzI?RG$>B^#]FO[@a<+;Y'0<\;vewZpl,eElKoB5#<a13-<n}\2Y-^2_H<
    >YAVi]a,_k{1V-Ev3<e_3p1aA}Y?p7YYBM(toV!4IpA$}XoDX(NB+si8ROaBz-XYnDn^{,?#'Vrs
    {H!IVuA^;nUp${a7CJ^pY:\'$J$#D?YIoa%tj3Z{BxjT!O*!x?}pz3jOjZjnE7@]~U@'/mEYQ_vY
    _["5#T[]>W</m\jIY@Deko{@\~Hvws(!>W+ji\C.;'HwQ3rB1s?O}uz_p?Vo#nG'Ri@,]5pa,]>#
    ?oQp<lk$v-<XH'#<{1Ou@UxnB+w;uooBrQ$H5QOi<+UQ/R!-]^oor_7I#=-nO1aHaMIvR<,jQrmw
    OU*@]+A-wUO\Zu[^,~+o{KC<OE|K-sC3a5'keEC~RRRuD:i-rei,e]Q'iFs*X{DzTzor{-ve;RRu
    n{h#OvY~x[\Ha[lyvpk*#VaUvK@QIG]Y1WpGi}vJW+v-BKpVQ5!51#\*V7G[G[an4r5[k>a\>f55
    ^2W_TC@OH3o5xKZX,I?E#'pQ=\1X};7$XlG;VKu>j}pn<>1ap=$C~usK[-zj1DV?vaUH{@[_@,-n
    u[<UGkfDxK@'UBX1DT1BY2$<^pUz:oo,_y{+=3}_5*W7EH.C]}*j+VvX_<kDRT#iUo]#po}^XaoA
    -KlQn[-1<z7bY]*=P|u5I]S]#@J^%\JRrkCm[\-u!K1JUsp3Ct"FJsw[F$r{O&f=?v~I4,WweOaG
    [>r}-zjlAi=#CvGCit1*7r|<6FB>r?Yl_,.=YBo7}aEUz,@_T1V|d,k@e>-T@uw$XtWeWl}R[pC7
    ?~mnxwq7svVX}}~sYHU75}R-e??^kuGS5a[C"\eHurk^Z]cajZ[?E[IMKRT*I$ikwG5]1ao'Ar5X
    Ck+\<E}YE$p=aC1@UQ#!lA3?Kp[>,eO7zV+nT>K;:IG{J\U]As5{Iv3'Vl@YX^zWoXIRuOIAJ}<o
    G"-_-eE{oAteG7uW[+GPLCD>zHLsu2$]wApRG_~'YQi1ivDlH[Kr{$Ul-xu<p@!+^-El1-u$[]w[
    AmT@-{@op,J__XZVj1e,[1QOCX}TsBR^wmulmrmYWpOr\$[oXK*oD\oRIK}*5pHVl?]IyPO}x5oA
    uzO7G;wHa=QA<[CpQUvc<}.C5e^qRvwwT}\nY+-'a*Yv**1T,o=g1$!_-rIVBBane^Zo,]!>n$Gr
    BUu}CHT'iI1}%#$5l+[?+6rpT2G=zp.![-wj;QTDGRV=JQnaG{~JIGonj=CRT<me'Q-9\IQU?E;B
    8\m'YxpABv5J'?__JF_loX)V@j=c}J\o]#AkBU'<Z$W]WG+{WG$^84B<3#02_RnKGaE:;IJuzjiV
    C,n;ETlk~=?px^2XGH-mb(oH_<$*?V4VY?>2C$=^sXu,r3;Q(T{<7~+$}Y3[v{6%*A7kNr{+Z-s@
    5oaeZse7+ITWs-=zOz3R2$5+rxDj'h_eO_5mvpPlnn}2QJsHe?l*]71G;YUOnET=+}DF$wKAt,jG
    zQrv_=XICI~<'oG}B+1G{07jUxtK^j_\spaBk,[gBo,s'jDRErZs=m@zk+;[-ae$N1B>kW'!]BTV
    spUCKGi^;5V>j;LRoEx-HjKYZAuzWGY>U$7NRzx'JV}}%DWjvYwajkE#u-jZa2nXxq2j}n2+nEz\
    VzZQ.I3!u#R[1OisV==^BDH]zj]UDSX*GEDiv1=#~eU\snGK12^+}CHnHK]-rn]wQpVW;;?,XY7Y
    ,]=a3]_@Wa2o^-W^G-q<}=w=R$-2=<skIzYjD$OA-~R;C\jCH=pDz,u_Op}szj@[A~5BZ,AwnKj1
    BST*-Zri$]=~wjuoJ3G=!7k+DRym$l~kD*BBu[sV1TX*CxBKC{KIxrjD}s[1j^jerem3{>[TRmoR
    'Z{A}$1xXaE31okn^TIxp^zl?Bw~+Ua'21IQU-5euvjU|^^,?*1QBC!_ao=uE,$<E,KOB<R:IAo]
    }C_'v5Ir5'U]}]iD*+@;jA,{qx]^G;epzNkGZHv[r@15$$]@m;XTraGevAUlJkeBxrnp;$euw@I}
    #v_n]}x>E=;Xu$6<,;Y/Q!zplTR}rB1H:KXZ*IWlstA+r7AaV,2D3$o5u!ID#K\r@51C^D|*piJ4
    u*x3B?'?C@j\'Wr\DG=7v}E+<_!pv'-WiA_{i'=@GoQT+RKGPRupUv+s'#v$n;I$u<ps{xu!I:2A
    7<jZe=BEow_U_uRv~u;^v[I$[O9G2H<+q[UJ1}jQZ>qAInwo?+1lGImHY3?[@$]W}-<e^aaQvGaL
    E~vQV@2D:>jo~@vww'']R1!u^{{owAj}$-5J~T[>zBZQ;];B$JaB\1?j;w>1+_i$TUnzQJ*>KHjk
    J\ar_*}s7O,uIw[I<RLVp72XG1KC_E3u}Z2k=eYQ{WTBrQOjTsKKC's[wH<{,KI#pXRElQWzC$io
    ;Q=|woQ-U=xol_J2UolKAAms=Jp$_}AKreieXzvIQ=U#b*3!AEaY@j<AZeu-aD;~[NSs5=CVeRHV
    z]rr=ADnsuY,+AsBmH~RxB+0-Q{@e,ZoN<w\;1<WU'U7{5[3x5?z+Y=e~kG2B:vO2aq;8{>aU}s7
    _*T*i131zQToxY$m~|WXYWJs}saAAQEsuCuVZD^n;=C#vsZCBs#]Ispyk=]#-<XG3*'KQ'AUUEU3
    ?1H+p']UwrX^a1VCj+O&,Rw;UjGGW[7-u5kVtLWGu7X17#c]@2W/[o>DYZuZ~IlCR\KUWDVz;*\p
    ZIsJ.YN1a1Y+1,\VIE;gAz2;^}13F1w,Wb)C_ZxnYl+QsBU*dj2GG!$^#GqH'$Rl#m-RRGrGE^2V
    _*o<o=J?=^Td_Dj@s1$aIv<+rD]DH5<7><4OREp:BinCO[=rB_Q525SV3uxria_<]]pKwO'zDuOe
    ^Y5v)+8v;Cll5pHmRxk}sKrk7UZC5=-unZ?}#>TT**To]m]I>O-$V2r~EVD*el<{+YUaw{{$HKQd
    JQ\TlzBzqvVTYBHZzXCTGVi,[%D*@sw+Z#$TEZGn'[A+E2F=;-3t7#C'?C]ze5~O1\Un)-p+'3DQ
    Zn$CDVoY33x>~b+RsZ![1T0,eiEin=;e>E#,CU{T=2l5o}@$H<RW,T@D+nlNUDwAE!1rv}w#!_m!
    <,?!hQZvC}jok#UE!8ra{3]^C$G'BW~*B=*Dw,EVmsRsol^e7#rR{Tkx~725C>-B<xpZH^qF~5o;
    #wWz45@Zp375xRpWWjooZ@Buj{^!uGU;K;XR5z>E{]krK_^#1b=B+{I-7iX'_@+X3VjI;-[@mI1@
    aXiRZWrQQADKZ*ECirnwHXn]nr~pw2C>7?}32aP_z^H&[55Imzu>TXVOnU$*Ih+a},E@3_cQ@{O~
    DWly8q#^r'lH@Wz+rwGUnm>G,wHA<x4C]BC@={3o?~pj\YQ9Z1Y\j27QPGxw@$vw-K]$,-w~+2[^
    KJXV7OmKm}o3E^x[Z=[Cmoz!R2_<7fi1vs$z#<p[35i>31[Z_?u57;cl7isWopp,mEW?}*>>1BVo
    ^j@1=I[}ZJlM:zj!l_W$rfe;GA[GI<x#^I#O3uyo3Im}\17@{QG&Y6\~a',_Doc2[3H=O3'^aoix
    .|Z<[JSQa^Bw{V-IA>7%Im~XjH3Bx?n+?QZvIXS2HU;1?JChe*1j#sn~7x}[<9UT!1Y*}#c;TTmZ
    YIs#QKVL@-;\8cxWY~'a*E?a^z$xa2*w1~]!5<D=AAYvBUaTp1E'D**pB5,*?R-7$<XQ+u$3xmS<
    XU2u-Zn1zj7CZ,kJ^k>vjKC'>Ol%Ii3];>~D>D'o*kE\f+H$~iG}53\}51o1ZW$mRZI#ARK7ai}Y
    3Q<]A?BB?vzDAonn>UEQa=EI1m>R<?e!,X{EVnpX,}{aeGK!X}O\ZIUVaGR~#@w]x?{\7&#o,!j$
    ;u3[@v%_A'-ji@KvT7$tP-r_=7k\T=<DrX7#,up'Ax}@3][ZjC+}WEsIsKG]\J,e^KVG7dEo~]Jo
    mYM~a,p.iEV#G7;']QaC~$;JnRD7KEK7^I+!(!*^~Q?]@so$G;O-s.oBKppD,!Aj!ji5}Jmsr^UD
    JXVuGjBOuI<E#-x=ewLe-wjPnU[H\G+m);-@7qGmJDZjC\{Aa{xp_^2X>kv:rl$xZjJw#R}3@,z>
    F)Y]Txe1U++,'impe_^!7YeR}>$V!-ZA2nf*lplDv?_m']+)oi]Ww5awer{G?=;[]~QOd0a1m+Gn
    ]V~^^>-}Ra-U]EBzK<Ir~=+Dp3HBh12_C~U]2lv}3R\#;GAT[2]OU_#$}[iss*ZEAb}n!1oO7Do2
    ~HVZ_*W[;+RITk1*-C+<s]i_@zJnv{7JexXwYej^lBCs1De@X~$+Y3l*?oE[XO'5JI@pQ3G@l-D$
    !o<n*WBw+;!T}1TrCA-{nJuV@':6rlj[tu5I*GA~!${e_HDQ2#7wTBNQWT'eATuWTHR1rV'4vTaB
    ,e7iv>eKsCK7;D<OV[s{Q>oB.OWA25kDKWaJm{w5G.OlmjRzT;V@zoZ>VioG2OfN'=u{C2=7p3'v
    ^w-;1GmI%Cn[]*B5oWn=GGuUl,]>WGiaEXEHw1UXGir;XvRX+zC,^wwW;\1!a]JH2{YX[,3Y,T<-
    R!]K@jo?B[@3ICH=50]aQ58~o5_%3r=I*ur,J+3[QoujXQVnuxK{\w<AA<s^Yj{XXB\C*@\zm=Hw
    :DXu{pz'~*z_Cin\]HY3GsIUR!C6v>e+fsQaup;Y<!BIJ6^,5@?nA]DnjzIiz<z71sT\YxDWB'Q~
    j@Hx^<I!7x|JT71Y3nv+*{x0jW=!X]+e%eQ#Dx+{^\}^IjR*+jYT#Ap!w]5{?lRRX<G-RDok$,lZ
    QzOuAg_e2<oQEH5#{@Qx<px3$OnG{~t=TU-TU+}kroe/\]aI$-]?'7'n\CWApC=mx;lpE\ir[o\s
    )Ejv{>}\K-H5WZ_KwG;npXaOCqo!Xm@r]=[WAe}z^\Res<-AK[[Ej@/}vov;<RG2<'_+US5ipYAG
    K37^rGjB$<u7n2^jBDoe3s77{-\rYXSw+D$=vT$W^TeB}XWS_+nCCY$BoC{}eu*^E<H5ZQVGA_JR
    l>]IC-3Hg;'s5=T$OCEE\j7#w(G$k3r7<#k7nGr7^@vuAKivR$=rG*vVYI\aT,2-pU}nGeo!2}*;
    <O#nY_J1#A~}7VAN7}wBwHX!G1pKBBmn3rzYxvKUPNw{=W3VkAO]vaFx2,i_J3Et\6AYu^H1Vl*i
    s=-xH>p@V^\_1CHXeKJT>Du==m0Qj{x~H>}u]v'Vm+*,7X!-a>]*7ZuopXXsjKRz7Rp}uOH4m\k{
    rKAAS*UWX\BHT@x\'l-ZEW+e2}Y7@2rH[X5J37HT\7Ge]c>X7T_>Tln>ZpeknsiVu1YsiIq?*l['
    m1#Brz@tD=keXp{Ck$ED\+ZD~sXv^,^-s\HoC\@D}TIG,^iw8~,OJ396{zCrVD=$D#CrkBU*@sK#
    jU'~'YCm[!r?C[\ksrj~l=2w9ICk'=,2Y*Y-!Ae_l[3eHE}}=n{OY7Oev,-V]yM*W1^!_VsIzXG5
    <j,c$Ku!lK[QO2YUr!;1e@w}1_]\zn,}[!j;OXmOpT!$G-G]$}"1Dj7e\=2CDa@+V,Ozx:YG2=3A
    ;nO}T@oCa*-p>1]}rD/IDB^u_@'p[$2|3p}UG7ur2vT@VRJwzsnxl3jna$Gs]iRw-\kW;C1,Go~^
    <G-KIx1-'OB$G]e]~-\Uo+=VAljUrI~<7\Bs7_}UnpIv3o!>sUU?2$]^;5HTK[]=F1KZBJCopqwx
    2TD[WRx>@Hc"lXJ>MHCWmzRvVr2DvPJw!nUR_#?n>53^'?QC^{1ZIZBLVGIIzm$Bwx>@wzjjJs2'
    Z<rJZ_poN'J2OAA*zC-!\6Q2Zvc=C<a*lQ,Y^rQ@pAeZjp>*a3px?ZRo1n}IVR{v-7jPvw~kT.Yj
    7Y$<TB7>pZ;[AIU5D-_1!TTw>'U'l@,J->\W+kG;$pfzJu<C2*iBo,'pd$lEU~BZUV;zl{n2T5X3
    RLD^G!iEGO,O=CRxUH**U'4!wo#}CIp\9;\~1Fw-1'zjT-2TDZ\?lsvl#^*2xmu_]x+UCT0^C$[l
    sm$$]<lsi@A^<>R,Y-$Un5e;-VRYwETpDl1Z<^-'#$79vZV,5$1Wb*eElmj~jE#5Aje^mn+~ssXV
    Bp2<OAYpO@-Xp!woRRxBZ}\pU~p<sea73<ClXC*2[<5]mTa;DoEumwzQK==UkY2]Rk\3s1*wU,uO
    olVDK>n*jXR_e6_G\-RtzZ7=u^R5]7W>N#a{W^U$?vXG!nnnuV[*~G_lzRV${v?7llB>'ea-mXO\
    R2$O@l,eRQ{m<o*'euR\*CjX!KzK^:XjjE7pvRYep;F+a$'*k]HB|8rjBo?V[l-X5$U}?[@GvKC*
    \\
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#Gxr1z*oX#>}wV7*^5V\;pvZ@Wo=sH5sV}Z-WKYk]DB#{^X'mIDGT}T,*yeKJr*171%=JYuC
    =}x-TZnp;,+|EfkQ'Be-e]iXa[zx^QI}VCXvo=Iz!'Nm'i>l_$wB2YUjX}BJs7'-(E4$\-3*Jp3O
    QQu^zIJNv#@*x^Ix1Hz!$x[@w<BE(I-{ag0laFy#w-^1e3B*zl;CjJnJ'GKY3]TE-HzG@<]VaYiP
    O^B*%BIJ]v'Om7@BYEY#k3>ls~Yxm'um~5_<I5{HeBd!Qn,qjRD7~{HOTrJo$35Ix-<Q,nG@vz@D
    -AR!YB@l$rVxx_]mB}={$!oU}BH\p3Allz-~Erw'xv'$[u~7bw+TvL-r;@7Da3m5-Al,AQ^kT^Y6
    exoKvRE'v~HukIBnIB#*Z']llkarRi]-IxB_?{$wm*kp,CA{xsp-,j^V$H}<:l+]]ul[Z}xuB3]v
    eA.UY;useH}NR1j5n.wwj7{oIwH>5QtqgVjHo8I?W{2vr^EBkrH[H+&m<HQfOWZ]@rjup$A;WYGk
    K{][/|Q<T$}'w,nCv$HYi_}wz<x@^*@V@J2a-l^sRwx7oU_HeAR?,U<_a1sBYD{1@@i,k7^;^{]@
    [OGz$'OYA]v[2XY2uHw_z{nwTCNYTEYB@W}j*V_13W!s;u'z+*l@Ei'QV>m#RR[nT{3]'W-s$j{]
    'GBu$OO2+K'oZ!v\vQ?mTvY#z-YQBU*^!l?[KV5z},ai_@=gn{'o5v@@xW21iYr'eGW]T=dQ*kER
    3!Z^'3@=X*RmIwAdrQ@O$vBkj*;{wRu#[BJ2w[i3[a,3p<ErY#[k1!Y'LYs]$n5oTq'WVQ'KTO;=
    Q2r#xx=UQ]]{esw[nRu[E'Yi3EVXm{axRIuY=#j_J?'G2TIp'O.yx-{BHNv5$*YJ\KllHC=-Tk?n
    z]d_]vGLrM=OZXf9zI]uYIGU7\Em7BgeIE?_B@=E[Z?EsI]o!R,*X[ZFk=s<?jmCp5Vsn\p>QV2m
    Z1-]}?A2Gz'x#n,>VJGU[C{}]OIA+*|#1kG~UG[1^-J;p7v:av}5aXmIlZW_KIG^{X~$aB1s2O^s
    %QY$iQ@[X{TX@RNpvI7'#o@_!-@EO?}5OKr%*DTuFcr,o^_Jxr1<7#=axT{IRa*X;!u}DZj_mIPR
    r@^K[U7'zz[TtZ]DBw_U'E*QOispxPuCIJ@vnSF7[G~|1u}m(,O~$*)_'QT1E~szp*u\^AHq>=r+
    ^C#+oG<3EQ*E=^oj>-Qo%mUCO}T*O?z}oA{-pf<sY>lu=vDKo-z%OC1xeDv3_ZweI~D@,O3[|,^]
    #Thk_m;QvmU=!'lu^*#<G;31?UzZ=nY{eAXGiKUv-aJB7}Ec}mZ287m{w!_@{Zr}A6CkC,W<IkBj
    }2OA7o_E_,RroC]aAv\sE2gG3$CUQV;uvRn@Y#J$+r=QH@Ve_$OvR<'<>Ek\ua$3CDT[UCI7e<v-
    j]~iQw{Eb3rxnxfJp5?9$L[O1A_\^WOx-Gps!ux[lUb!{TUIY{HGH<*1~_zwDG\+1]<aj1{~7FB~
    <rIB*Z^\TpvK-+5l'Gsz}lijvxk,ZGHCv@o'w^$A^}_CGiH-J~!Ir<\GwJk7O3Ou5V@}C;H[',>}
    umTEw{WIvnJ>B$[WOR>Xz1kQ@Ge*2T71I+oxku,HHaCk7'a]3}pko''m>$C;@KfZ7}JNY}1+wR<2
    #1K]BkH_?AxDa51$zR+Ul_V}Ip\5;p$VeW2ZN@oXXoTHjK7m<raYHl2;3^^O5Pe$nAzYH>e~Q!?{
    n$gTxoVp+rJQ5Ce35{=\pp>'mKE{7AU{C,7;U]*{R$Hr$snQwo#a\~rns]lDBZ+5Ew}@nw-6jx?x
    l1j}zW3D3zCwG]OPzI]CZ<E[mYx;'IC356I,?n<DR+$EpZaxGQGjBnnUYA\[>ZlBeB=G!{cA77\J
    [z;JoI5@OXQ-}2Y@sm2xR?+g4OwD7?=;R=>^1r>T,exVpx-*;_w=<p{xuT,^?\Dk!\}s<lDA}IGZ
    {^n2-\#!G3x=VqZY,JijeCU+TGRHXJCEv,kn~TvCVn~V=2@llZ]'3p;Cm@_2K][n$5aQ5rek,Omz
    nOprkpQ,1~C\j<xXJ1An<~jSOpjw=T5pVuH_c1p[_J}o$pi+>;}}H}V7u:r73_Xz>D3joiuoEYY~
    Wa.\z;{Hj_Gf[!Z]/I#>Z!+Kar**p*eeRe*'YIUpGs;{2TlGZH7]^#HT2?C5-t'V>n?IRnmTwH+$
    *K}E+nA*a}6oz\Q{D-O3}joE~B$IHl7HOK2-VrEs7i}#-<nIT,V,A<sjDOp8WeWvrYC!CprDlWZJ
    ERz*_i,?k$IpZx]ou^_ikv+XVl<#^=]Xps#3GzW+\;p7ZnK\~U{'!7v$)p=\V5_voZzx!2'WsD-C
    ^BmK'CmAIBkuGl@Yvmo-Oa<T5Y*k{=X@G9I^*eGz*{TlKR@$Dl>XAKkp<XHj?[[Z5}e$jY[,i+~[
    k7MRWeYKXT
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#,wR,7$aD#*eDhDIlQ$z[uTUT,mYIpx;W[Cu=EF^;-JTEnOkRHe6}TI*yeW@]*=l5||j?~#{
    sn5<eXazxC[EfkQ'Be-e]iXa[zx^QI}VCXvE=IzaEN!H$E$1iAB2YUX<^[YJT?2sDlR1TrmBri=z
    pjY-Z$'__To_GiQdovYi'k;?eu_pKU^#--xG{7iQ;_-[P:OXAuB;~Xjj=_@H{{e@;}bN2Y>a2nD?
    AC_;6/"RVX]e\7U1jv2GuMbABAVDWu2wG?[#G3Key04=nTWaT,\:V<xapnpxte~R~+D!?{T^$^Zn
    $i}ru:GIo!21mp{7*iO=!zE+U]A*a~TO5uJs*O#D[]:{}1B8!I^_o-^xQA'EwQAVbJ6$HaTmw\C(
    O,j1@^CJ,5~oP{rT]zGGz,aj1{w~2.r\'![QO>Im2_QX$}J>PXe]_K>r!I@*_[=Z<,*Yap>sp}k}
    EBT\i'aV+pmU1ul[Yj!J-kvv=o1KYI<T[z*K{~7jHFUC3p'\Q[&l7?w$*{p;V};sX{p$aXxBnv?0
    R+5C7Jm{%Ez'$tMxh\*7p7<'r~XA>%o7{@rN-'X;Eo1K_k>O,]}{0*ZAQ;l^}xs57My;<zmizKU3
    DU3Dv2}K-rpDwOA*$3_iIB~D;!$77B]3+xV"r5=]3{{O9!_?=CYO}HrRe2>aCVHW7s#naO,7USNa
    -m;QZr#e5oBQ2o[jO!5?GoY'$BY'1j~vKZQLN9nRiWB}Xjv51wfmH\a_Ri>}kW{6Is7eH1W=J57~
    2sTHKo@_S<]$?YiO{u_1l1HG{J'i1EMFzTTO$71\c~swj}D#UYV]B_IK$s\]aQ<w-nElpp5m;qeU
    1YI>\+@'k=TDG$?a<K#,Z]fpp+aIK7Qx=l{5jDim+^\Qx2*!]ov]ulWxmnprO+?-^o["-o*OCI?'
    GW~}lF\xaj'U2nW<,+}pCGH5n]l3VC]}X];]TTEAI2L7-aW=?a#1YT,1sO^fM(m]DJ=BUIUw^Z^@
    e>K,DJ1]+k=*n~j!GIzR=jz1}=%XA\JC]U5-}JRwGX1V$#X2^Vnz~eG^+op@[Hm;}^BGTVK~EVCC
    zVE,>x!{=~,}o^3;|a*~VVli^O$Dim>VK^E}=>[lI|C{+#Kwuz=vKTr;jpU5!\evaVh/]p{nX=+*
    \<HE}I$CBmlKxV-_Dj!Z_IE'=K*rV[jvB[^wD!eGa]x?XGme=wx;j^EIg;r\\Z8=CV'H5j,vT+-<
    $<r1ea-{$KI}@oKRC-#5I5]UlXDT]3I<I37$E++^BV_ACi;YRX2G[kxCj@A~r*1G]x]Mc!OU1_!3
    *YA+]Dwwj^+pa7-_?,^ZH{Yz_lU!~,pws;RT#}T$2r3VH$E\K3{aj1Hj^aTl-2*<p3R[}EnI@:B>
    R'fE!W^i+7*}O{,2=U7ziJVQ;+]oO+UWYI\7ev*)H<AK}Gx$$XZ*>BxGN#'\^J}i~R-W{z_v3#rT
    ="x-mp7aua#>*UlRz5on~}8wvI~-smuG>VsfBUK}[,]}*KCu([z'pQr{=fCj+Oe~7kZV2B}$T]Hw
    x\a>lkIRrCo}a?T1H}pp2V]2<D^Cv<sz75I{v{rHW1jjR_q5u5RA_Gj>5Co\eOjj*5]S]+D[hp2r
    mUC+x5+s]]uAR)ekZ5@7'~VT{^UvW3WRIT*DJlj;~'^wsw=J^^QZ]Yz$+Qo{vv#Yl#}Y}[H][kOO
    R7v3u=D5jxFj+WJ!]OTom{\;Eo;z}}A,m\_=3{;$~WHWo7@~w<*'W1K5}iDEBx@},VD=HTeBr?5r
    *vuiTWr\Ov$<[]#as_n7XA5'CzCIR-#AV$;[CIj=K<W~ru@s;D~G4EJ!Ev1YY^Q1W,#QJnToXuTV
    @@T<v~*=>ODD@hLVv;TH1#;se^^uj\ouHj~5]QE<7Ae)+}][/eiH[1e@;=3_e!hF6pkpp3Twl]\?
    _ppp1a'k}#UG3r;~*TOYEA=iG)F[_;u>x{uKV@\Rsl<Wv#I2lE*te<1kA53Jju7BjK\!#{+!+7Wo
    RUUQv+^*'_[krGI'sOUs]KxEl5<=WeaKWC1+3}Jlk=]{YIUxaUAZ#_?=G@IHeCn]kv3C'$xH-<<3
    +'!G8xRkRQ,CH5Qu$Aa}I\z}aQnT[KO*5G*@,5sj#s-{!^!ATe5pB{^CunLo,p~R1_xO_\5nwj7D
    EQX<Ul@TU,V>s+pCGO;R*-VE>*+?Q^xaw]zUnv_C3I=7GY+iC]vF@]xU-CW{iXHY_'aUiDrCIko[
    ]_QV[rEO<eYuVY-u3]Rrajj3QYusCUnoc.2>1E?DD$[{en3<,WaQ~A8}2'K}lI^Q,?BYnuwx-*r8
    #'E*xPoZg!aY!>YuBg{pkl5<rT/h}-o~O?Cju]<E]_5T#<Qln,VpP{B$[n>{nLsr,UvVe{?AlJHp
    {sJ5iCVsDECIJ?I1V2Njo*i[j5u6{jDm=o>atVVX=aRe{'3,]?Vl}LI3@kD=OYpXW{|;$1\D7#r~
    QGZQ2apiQDs-p-QkEx1O[WrR^~58aoGDU$~T!^$u8#xCkHv+$qa=?B<1UZBzv+Q5_'?1]r1G+r\_
    <{OvOYqYJnW[j]Dw=5;ul?<VD1]@U7;,?\B]Rp{ITzRsK=$#zR\ee=oe>vxIYBvx5W2p@Qv|Bm5'
    ?=w'7sl*,CB\Wjv{[WGVCH;C7I;p%~s@V1OZH[?wKVDu7Nu}slwIp#^=W\[!nv3,A@fEH{CL+XR~
    \DOzDE*]QVC~$+xswpg~*G1e$>G'vK;jHls(#1[\v#l{Pfewu<#TW\cvj[o6MPK[5EEa-E}WQzUX
    ZoCs!'!o*uO}!,e7Y$U-\C-rl@DeEs.CnmBtxJH3~x5nv7O=$I<+wRAZ0Y5Y_B+Hj%4+{lBqr+X%
    v}jC~Oiu[EY}GCpX)c7s+kI7spsTvn7lG,<aU?kEu@ez!-oOs;Ce;RK{j-JB^xi{Qp]vkOM+j_iU
    >3TyYW^u*m_JIpa-HQ#o3Bsuv_\+_7}T=s-n>Q;U,IG!|E_nOx?*up}v_COTI[@'!mjD!'\uHveI
    57C~uo5-!{nCwTG8AR?@U,pUWUXI$s{7EZ$pK5VEa=Zv_Oz{;zZodVvn[kxuneZWY>e##eT!$wj{
    RvO<Ze\?WvZ+oBHK,>e1@I7]1<jZk#>~lrKGspZEXQIHlY6z_}mr-@R_TJY14O<-eE{+Hh*1<K@O
    I'ao^p~_BoB3C>RER;x\;2-Q$I0^}Wr/lYe'8OOn;i-!akBoOw7U$d8'Jp7^>-^P[GY~viJDaYAw
    -]*YI3_3_^3Dl*JWf[P3V^}zuu~^uashxwl#Ks]as+aAKT=I^e]>U<@o6_HTw+V}$LGO|_JwUtfl
    xwpJ{~o1QI_ZsDxv%#=oWLA<=E3R!U3Y]{xY!$lKavXV!Xlom_@vQDL,75il>VI}5i<7Y\eG]AC7
    1sWxa_k\*GDA=KjuI\E)<^VE25r3_n;Q_>eZ*'[I@a+On*KKCE>IDa'=xlI~]Eor;+rQU*2=Rl]7
    k$DpB\IUy'IVW3q<Ys@V>C_?<oQ[O~J='Ix|vvD]C2+eIW]3Ez'$9IJ[~\@O_$_EHeSYp~IHsn1=
    I-o/-j+]=sU#1?,e1B##I<_]c7k\_O~!DCZ@Y(lRrK2='>cWVQOwEi~_v[1ZpVD:w5KG{DZ7-Yi@
    ^U_xpA,{CeR,dTIo[UO<3z>pX(U]}Gz6zrE$ArpBUU;T1k!JBsr,LUG$Ws}7,OxWZ,aJe>'x;#l5
    Yaxx@#[1UG2Q5kC7iapJoG?,lcrv'@wH{-rLZs+1#<m[H*PCZZ2Yapu2O1x2TQ,=V<B6]EKEi=x}
    <,sor-jz<^BsWB1x"R1mz*K$rBJ$eR*;JGezmCxXUpd9']DTW[I2K{=ZXr]=7s;Wc4{T1JAzT#pk
    xB[<1KTC=JBK2W^^XBe*I'\+E*E]'!;D>]z1*U~[eOvIw,YWsVBXaxQmQ3}~}nc|iGeCLTA>e~Tm
    ]v?CZC}^k@D77*KI-aGKH[bpk;$5EQpLv<w;:O5vU{}zR7>VD;<n~\a~ITEv+jQxjo-jJx0CVIGH
    [uv7$lGx{os'Om+l@'\KnE*Y}2R3G1nE*Vjo!5DQUVKvZv}*=v+}GX1~XR?qe[aKIO[usI1usUj+
    <rG*o-wzce3[wfITCAxJK+I3ewRx{*1<1~C!U{D5Q<*vEX3EaQ0e}YR3]r3_kuxIW=p_W{+OZpms
    ~l;1~'_'R,W^iV{x}QR^x~_J1OQ>w\x{A>V<eO]!t'>*>Hl5Wl?aO2]weeA,R:-nTQQJ=!YXzE7@
    ;>}X\zGpv2lD73[2*BHU!3.=@OUwE+zXY{#b[Z\3ruoC7*X]^*\uC]\W7-nlG=@1zJjs*kzn-a2E
    VC*r,s[7Hs3vx>'$PZU}JxxG#R<,jF^x+7;Im}AsAZ5\3Zo$1DJrH@>=kre[+?a'}er!{-OwTZjn
    C1D#z5)kapj4G!T'mBA!peToKU-ss'$[v_;u^@~ER:hfZ_$opK$sMpI*V1eAl**jKY+Gj"];_AYe
    BCr[XQT>7aI2vvx{*<}+!-_<B{pJm_x;-3ZVe\p<ZR{Q5@'?Zo'<lpN*KuQv$Zx_E-E,AUDIed=Z
    @2cI{XQ@G[k(^lO>o]B@$XlAiRX*)1X1;V;w2v*v*CiX<;BI;-ABz=?V7rC5i}j'+~wA@;l-,;=B
    uqGrQ]&$oCn<B}#vG^70WC],(;'s2z\BH[s2p7Zn}eun<l!CD6A,]GCBu#ulo[m\-Y!lnXEKIY1-
    C*UUJ;7ml5}o$r2[[~YnwYQ}CkWs{3P1+ZKz@>;ka>BQi@'VrI>r72<*~,$:l1\r2VT$TsCV}+Wx
    $om#[Q2jYzouKVW3I,#HoG]Tu[p@nvIrf^AzTs5*{Ol#ex\_uxKG]Y[X[rYV/A*Dz#-lXMz^A?7s
    Wu@&Y{}s;xoEEp@5WrEkw+Z*}JQ]KY'U{H5C$\zKmw@~x3]mnQl}@_CpsexW6_2<jz*V_E[*JQ<a
    o_Dr5rn_-?nRe=wu]}}zWj]$}m*BVTD3^7lGHRUY];+IVEXCBlo1!O{]uY3BD7NwsOeon$;7Y$CR
    xrEa=C'1<ZUgyU>rX[AK]irE_U7<~TD3,ix}oa+sielp\IU$uX}WD3Ez*j-KV+TE!LDpC{eZ=-Vz
    [U'C${$nB?=$wW*zaTGK7;D[wK@}p;@7IXz^v?Ur'OGXOe{-s}2rRj+lDx[QA7]+m[]wAE{VG--s
    5u,r*v,E^7T7Al_BaDIRp3#1|np1u?,v7f|eri*B<;kTX1rspXRPi(mSs_u*=;**$vu'$_Wu#Q{o
    em@=s3G3Q3\,2Eu1Sk+=mK7Uw-Q[EOTeVA[_eW}v<k{R_fk}1a$,rn#jWmqG/uBD}->AzCV3DU'Q
    enDerjmplSH=u@m[Bkb05uj@NHYU,>+Km+1KE1CY{0[=}Ibiv^iQACioz<-{a+T=3,JG3^u]e}oE
    p#DZ]zJwwAx[[ls*7HD3]Bn_HQz$rks^j\1TOj!v7xsvZnT1vuurUBpcsB_l@<7AZ^Z{KsO*iGr,
    -}{=ej~['<z!xZZwG=X5{AQ3}?esu=[]!*kes_'TlC5l37$Y:-C\'y|iX<sO~=zu7$$L0d7^13[T
    -m!-n=b]>m]8o)xv;KLr@B[p{JeirC#[QA}qGv}!oH!e:Ox$IDbjs'pN~^kJ]-W~vsEH^k\EQT!2
    ,aBIV{7?$K_$7^E{}TlziRE=F$xm@T\OrkEQAT5O+$YCK#1Za9H\jz\_2T?w-vY;xuCae3Wj2^?q
    "]l}ple?ZAnBBu,n7o~u;w,~a/UIYY;Cl]-vWC]2!mrp5=UsxRnBH7}]?$AHJ-eEk>YCi!wI+nDo
    ~15z=w@z?5VUxRXY2kBp;oT'2r}7VJ>YXnWnEl[oDl*2E]WVOrGQ>X35-E?{JJB{*Y,o3D$B=+U$
    WVvo3E)ceEe[p_?QNS3DVocYunz+{H?XE;R_n'mc,O<ewO>,C}iE9xul7NvC;$Ed}mCs,t^,w}u^
    -Y}B$TB'wZl{vrBRx}T$l-!e}U>TCC$=+$s5[1>*2,Zvv>WwJaRaX@;OT!W_<<vekr!l{;r@Gn@T
    rTuE!^i8sC>Z=Gp,u\W'E_AjRs<3]B'=$U=wiAD^"RK<zpkeu\av{W\_7}7C]Wv.l"f'b<*CrHI>
    @kUuY-^@XE'e-rE}*cH_'#E**kvKAeH-<EfjDvV,UwJ|O]w'*XvU=Keu(r7e{35AeL$z=!,ulj;e
    l~@5AV'+!W-n<5R;UuQezpM=,}<Q*-=~zCor]Cm}dDhL'k2#=g~$~!P[lwYgu\Q~fpGwOz7e\;rp
    Y2>zeC2<\VB\Jjsa^~l!-fP/-*>sW}xQxnsTTIu,sO<@AC<$\_mkx5+IixX^uCe,5[rR2w*l@DGm
    ]W2WiO[m\_wDkvJ$aj{{@1J11-->^$Wo_^#*]~J*_3aGC=3p>r*oaaVpBA~r%B3EmAvl3ZR~T<AG
    R<5~#xVheHW;v@Q+$Y3zkIWzxTQ3Os=r!^B2o?XZRNvAx_jUvwkXCGir1[C,eOY_#?@-eXsBpQN4
    |,sAup'l@Y\}TnaGAI?_{+YIGOD<r>IUXr<'~x!nw=CwKv}Gm;<[QsD]KoxiV^u;wkV~3JxG$=B!
    @+*U+@TEI#=lVpCU#CVX>o;[EOe!Hnj!\Droao@ev_xQwBAJluY\,a'jn\A><Je'+2Se}upIwGj]
    H!GxlVD8}v2uRCD~Y]T<ir}i57uk*3Kn<n~mYj#I?<D3{azV<xYk3jsjko>5K<Aop;_Wp5X3vz+J
    QvTH*EH7*_{]rir}}{7Kre+?!'ol+YTGr+o^*Ua{AG]i=OJs>vD{@rK2zeZ;_VZnsjjCe]no*A}-
    Te+T.i7V}[ZIxQo[HE>VvO>}XNl<R~nUm1\CTJB{T='1o#n>s-?r-3smOx[?!QUQri=j!TQ'\Xu{
    '!nxlx#_e{}sT*\R#Eb-TCV,WCe#eUmq+'jpDpu>=D-Vj5m-R1TaKXJ1^-5{uVm^Z[x!_2sz!e]?
    *k3@+I\wk+Cj'!XlW7r7<LKq1s[{HD@UQ:wU\[E2_wxi\EFWRV*,;Y$RW<XjJ=J&K'T@VI?Z,GIU
    s,!uF1Ea\\pH!eE7vsBH$rEpuvZpZ775DDn\]YTKmQXJHk+[Ii7],p#@\5nnO^<$;}V!j[WwG4]v
    xKIj,me3W[6}G1=gIa{~+Ix['p>1G-o#T1nXsvr3us,'MUT_poS57o]YZ<ZG1A@;,Kmq<|^rH$IV
    {opv5YR1R?/aI}BR]Dn#1!GNk<[WuXs[=R}Wzs{_,@J-11x!}5a']KIjnr+XB'XweVvC&;w,p}5T
    BXe720-Xze,KB[BV7BD-sR$XjiDOpGz,^QO-J\]a,UW>Zpo-CY6uxvO*Gn@IJo!3xCrTV#5<Cs{8
    +QiEBpuloIm#WAT$GlRR<j,l7z{<lO?r$BuOHwA;,em^RaW7w]R,fpQxpjZoW{Y{k]7ZeZ>xuZO,
    R[\Q'RHRB$YX[^Gq^\~\>-Djko?C[1jjf1U[QGbUjwJYsO>,}3nn>^*Xo_na-Y~7VI'R=~VBvr#[
    E,!=p<pYvW]@AC$>A}wZT\HBWv=kIVo^IDkk,KoRHT-aHzp;>~zxo$\vZ;OUO-zQ-5}I2onTI}eB
    -^*}$p=&]e$\*2{Qn]m]Wlr_~5BX^Iw*=^eCYrR^{si~h$-Hxo5{~<jm,r>\-C3-DTsx*vBJkA<w
    ,3D;xl,oDjB7{lReX3A>56"3[}kZrjHWwm]^Ze3oI$3QtVaDp]eB;^Z[2[eA<7pa3|VzzDlmo-$K
    HmV>QpervnpXGVpo{2V5jHwT>{Oe5>Hj2DU{xsQVeU7jDw^kAJ3>_-wIn=qE2VWI{+;[R$uiRZO>
    p}p~VK2l3K^;w]p2CJ-:7b'\asgE@Q!7EAxZr@]R2;}.lBRe=>+,Q~=r$p^jd'G?u[n]'lr5m\2T
    -AnAm52aT#Qp!{YVrG3m_AGBW]BK=*wHEXCrrG$_$5menkC=Vr\CTDa@pYB^_7IXrBwXE2oUw@G^
    }5-_>,OTn>'!D\{~YB>u_\ICm<TU'n+Z[*\ZQ_sAO[@xkD*s'tBp6kUI^{jXOGip5{_>xC<x35A{
    $X-OaC?zO^O7@nCOTpeWzUDEjTEI<PX,WZ,\QVLEC^1:bo}GvYdU]E=7k{n=JA3,Q^$7<zOC3$CO
    J17__kmEv!*Wl}IctA1#*ao@Gs7s}}{R3kxoe\W@RlDwYosXJ^;n=ToA]@R7}n\ws,[n+XvH!j1;
    K}JB@}^]k}\uC7C'^]}imFe=O?k5;l<OXUleK{*oa^@w5xrpmHZ5C#0lT+s\J{5UYUuts^D;xI+Q
    U-UI+a$*O&pH^?;O1a$QY{1luK|-1$T$-,eR=,]rRYOSCo'CT,{#nliYv\!RH7pZH+G}O_a[|0Un
    B\D3*?[!Bl=Wl}$en~<j[
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#!*p=}KvU@xxuOr{XrpDI}KIRar\~Xw*kFl~*7|Q?l3I3W77vRUmXJjMU'?2<a$TA{~rv~Wn
    _KjVV$m[rZ,%lwJ#*+[[o_n=['CW!Ul$HUl}5QxOx_#o1nB2oma+Hri=T$+o'+xZyYZ{<|Q,lVYw
    U_-QUrOf0oOZ,wrAVC}=2RYX~qY6}pJe'rozCeH]Y1+#^->mroUX;vvv}?Qk0Ho'VH1-p],[7MQk
    wrz?$*BD\U7Z1]ojXTXjvBCv@>s}?e3'z{xp!?]VBe:9u=Y^|Cz$@kXA'=TXv;n'-:=2u1QD'n=>
    CQaT-I($;33es#G*IO$D;KQRB}DwT>mw=Djz<@}[@-}Cvxp'e{<*5e5,jv3E3-Us>QQ[mr5:7m5a
    IK];~NQ\mpT<!]il-[[55-v=[z;xERJTx$N=[5TC5UH$O~o>_7IBzzwnxU{gw_B-pn7;B~vm!OUQ
    @=!BP{$rGF?'+_Eer_>Xu!=o{^<o]19~1Y~ChC/N[Xsr$>3kI]_nRW<@A,~}v[wW,?[UU[1>d]Tx
    1~_J$_or\G>=$yP}RV2l?'rdAY;{@D2owII}><1p]K*e|$D7k2rHDZR^^9Hpu]G>ROnxpIEjT@D^
    BsB5{ZSoxa1x#=#]$]kmI-?GXT,i+lr3^k}#AoG]CH5~U>o3r{O<-Ja+B_I:vr$raw~#i,uKzU->
    +^[3&lD=x+\7@jfVn<HoB\!=@^\ZYo#!1mGXe^1C5*C2UUEoo3srGpHnwVlIja<m5j5w$?CR;{2m
    YRB1UAV?a]wEk*aBxm?sxYV>7TmaE?#aDUoR\I72v$@sNvJ*]K51Rn<p2-v~?<H&1n<]K]xK$mVs
    ~<KTv!V=iVAm$<22%=[aBOJH;ZaQ#k52s!wX~ev[Jm'OTRs@Y$_pQL'}V@KjC@dQwR5NC5p3#=i2
    Ts<,wH5TGBJ+xHl$S$2V$;o~W5E_OM|AD5!n]m]eJ$Z<\R{$2'ns5v<$kIR*?IH_>[ARE?TR?Y~5
    U}ettrO]YxnQrV1C*c"^le]U=}Q*$=+N^Q_uBYe2bYY>on{o{U1Y>jIv]Gw*C?$neKs]]DG<}ojm
    1]>BDq^#jx=R?;Qi]?&DuXlCBQ5Bv]JE$Q1?vGWv@TeV$}<$$j><I!7_7_l<=<aQ$YYY'i#gp-]_
    lk{uN1J5I|urA_FTx$D[Z17m\^V@5RvT<!\xXmxl{2]*Rw\+eQ$v+;@#=w=WO[oGl5J3voCkj>$m
    rBHUein+R\'=O\=[;j7ElKxBX\vC=JEDzziKa5!lO3Ad1u\\YvA]p<{<NRO$WN'TEvaA\zBk,3h[
    *'^R?Kn]WBJ)xW_J$#D+i_=XQEn2DJIB%Y7EOK7Q3eL?p[3<xuJ]kX>[!HWZv;pq1D^pp{I7oIXj
    z7wDj\w=)tas33F'!z,,V=GxW,R>-=}$;1l5;+ZkUEIRmmUJ*m@0epkmC?lxex{@[eJ*Q~<*{YTm
    w'H~4@z!]V1mADmTQ7{[\Q@B*lxCpkUA!5s=ED!m7+vm2+_X,,R}WmV{JJ[JXV{{KBw7^"a7d,j>
    32R$v0~=Y]5nKQIv{!Gn@pn^;2J'<-k}<Za$lX^Axmrx#XVVaZ=@OGCA-jA<mH}5>kT7=!Qe@V<'
    @$O1mvpOV#~^u]7D}zr+aX+,[*2>YzO}rmNBm;}WCov*2aTQ?m11msw-Ts5V\WKx0OaV[fYu\?\?
    ^GK\;Q6=<xIc<^[aO'U'[]{2}<THV${UVVAB;*=W[lDV_<zZB-+2+Y>^)kQD~SexTuW{p'rp$Two
    ^n5-Tu,om;V'm='!sE<{=oQx=zAA{,m}{'Z-xmIACKuBk!j[uo-O'@rJ\rQpA]T<J?n[1Jx@l{l_
    kK95,wJk-I,?<uo\j<2KA7E;E]kwB<GLB+U3WR$'1,[wx]C][mAsY{@@Q{BJoa-wss]xsUH$l5v*
    bqkHe1E!xB}mD*$p-X{weBQ}sw'7p'ffwT=anEE<V@D$BzEz%uQYT3B$-1m;KviA#X$W@@Q?}mn5
    V_=3TC_pZa<;=jTDoV<;BjO[>#wRe)9x@o@}^oJlaRK__\^*JOAQ7GHLhGJ1Al1^#n}-Y\mK}s@O
    TI6,]$Yo-oD<T!'jYQBITv-%rrlOaAjTEu2QHA*u#_p]Zo}76<TB3$GX<3XBx5Gu[$Q=^yAnu5Yv
    ED*[AoIo;Yp\zZPs@lG3YrVK[l^BkBQue7'BgU[\[uQmXD\++Z=J!;G=KRKGwu}mH?pYD\?,p1k7
    5noO*K}ARuA;BKa1owUmeKxJ}O>=u${}Xuxjk}rlO-U!']$VX<vJ7{Cj]77p]^vA5CYJr<v#JBnU
    _u+Xr(e<rV!T<{>_]<xC:=coz!x^]z*8*+QOt8lU,lpAzY'5I7w<_>ARQ=^e'i(QUTz$m*Z'!^Er
    jTT5GT[]6Yw!7$VErYyjeWxRv^Ww{\~]5K1C$>EDa<azuBzW9+GmCFE*^{,<R12>rj2$@$Zz{[j<
    3Z'ozu}!UZNs~X]wQ}GMvT+;R*\k2HUG\-;*=sx]lv}<RXZX'1$C3E=w#CSA>],~=~II#-^eB+T.
    X[[^^wp-^o2w+jC~3seY9\Qj!Q\o-W=e!p!*xCp;<{XQGP',wTzjTOr'\*QJr-EBiQU=5_BQ$iDu
    G-NAC;1/7pGiKnsv'OjG]xD?wrUz--11+TXXx};K<G]ufTD>rqKIOoO3Du=O-7gizXX=5onm6vj~
    z^#RY_lW{Qv$pzk5\=?A~x'7vHw$_s?X>FsCosMZ]i!B[wQZ7!RIW'OTwl?WjUDIOm+$RpO9^iU@
    TX3u-+WR*+},Ck=sG?\{-wse~q}B1o[>eo^5{Vl@2x>,A<,H]lvz,I_?^w_vC]}Yo}e+Rks41rx@
    OQk=xBim{[<^r#5'@*Y^as11m$2ZHovKhJ=^$Ivrp1ku373<3l]V?JEm'RYJX#5-D~s#AxvpBBZw
    *OD@[Fa={!TXB=Qa5*<oDm7'CG5pGp<6EZm{_@CD,JC\qioiavCXXFHz~[rk{putG;v*7R>D$CD~
    O}U,H]YCEJTjI{1Q?jYo#CRY[~2x$Hv]xrsmJxQ}o=}a*<Eu!1+,a\JxS^EwAWTQvEaIrFR^[~L[
    <Uo#*}YjJvn-+A]=wA;vH$RD?O*R$H@7*+{ep5T7eH-Q{,{?}_HF*,[[4l*u]<EQVGJ{XYal$7Z$
    z$ZnY!jaxSTx75VW@1[Uoemn7^^2p$hupYR$p~_ER<k+EGw0eYaD-}QEUAsCf[Jw-e?7nk5E[,2j
    #v=uGN1mT\!]A+xuW;<n}iv[_]QG7r<I*Rj^*G]aY-vpHGe^2$NKI\,MfcpO^UJ{=JEJTaYG=Wo]
    5X=+Kw_A*;oJ~uZYA}i_!XRH~+\yn}e]=+WDL@n@j<A!7YQiC>va3o2vulAW[_5?E]w\^np[v_z>
    V_T_~AVJDi1R#,GCC\XE?Z53klvK_kXjVeZ7;$o[vQ*!-L\7pE]CTwY,$'\IWWZEJwOHH>xUj,y&
    Bl+H{>Hv@oDVtR#]zZ\xu]zi-H[^RRJ*Hn>Xrp#'pZO#nkQ~Ey]B$$Ob.@*]\J\K{Z,aRi';n]#l
    2gKsXU1F]G3uSZ7YXaUBsW[VV5$~Z=CKYzR[=Q\Z+l>o!r$I]}mj{}WU'1@@k-7W}^i_\n<<T!DD
    [e?o@[JE~5xo'>Yma'^Uv}{Bi*&q?ppBbI+5=-<H-lU@T=rTWk}CJGE~oqK[k2$,oj/pTUw3G<W^
    l1\(+\-j|1Q3eZw~Aq+l!T{G?OUp]$jJl\nj^[~r=V{eK=}5CZIKamrWXpGJ75t7{lHVx>BSqv%6
    +V>'GXJ-lC1_|lHVmZxl^]{u}R;*]]\VKWI7D~C-p4[VQe,,XGIK+xI2_,5rmzXo;T7u>[N=lJ55
    i{rCGQ3*V7;xEr<]H~_D]E[=s;D>{slR~+VQ#n$p+OJ^C$iksV?11a{.TI,<QZ7r?za2@1Y=Vp3'
    C7*3cS]2H3l,T\$\*o;<K#7u{QeGlKp=1eBA=_Zpvu[{5'y<e]\8r%o=*7UCAU?-Y?Yu,j57BBK>
    ~W}?CY:O3;@?o$\5va<K\JR-ED~$suOz,$!kj3*esD'n-{?9!-<oRG-_C;7*wQ7*reYB-}z=5]p*
    HRA>}JjY$n={^[xrQKIzplX*RHT2O71]epC;lXQOoQTue{+T2'HH}Rp$$GBi4\^YB$mxlwCHHxnp
    D~al7~O;7OAva2ax5[CC35XO-zAvm!,>mjX'T}}5mJ*lY'5{?a'!pv-Vn8315ui]W~}iz[CwHIJ>
    Ip'BIJ|2n_;[$Yp4du-n5'OKrO*R=^<*EjjTJC?>$WxK]xGnY;O]^EI[,B]==G,?wl?O'.e+E1?e
    skDGvrerBToaw>nxl;A_Zs=UnOu+_z>\3Xp~'*E7EHmV*j2EIQ,_}$'NWB#^lkE@2=A]BI-5\IQX
    OTI?+nY7fDoew&,NI1X-mrAsB|EWB*'$1H,MSZ5XDV_HUi(zRkp.y;HsCIDw=5_"aDA]#eHDm>zV
    X]7G3ri7wC^}n$K[{51l!_uEkH3B9C$$}B{BusJ-<Wp}_Bw1YhWjUX%WX5*i_J_VA{#sskpIavDn
    'jag+DKK$][]pG$HlTw@g^<D]+QR}^Ex]CTZ3v~l$Yz11ElHBEp~>k[]Yo;n~FeTB>GXG}G5}'1U
    x{^JQU1RTraOo>'?=C~]AIe^_1X_{m}Qu{e]]OK$?>1Ho*U7Y]R{>AVa{*R+{-CHVuavp,;+}see
    u@XrvpM]2Bz\Om}~T1TT=V@E{K]=p7]}5G\$]p10Q*la]o#o5;zX^,skJpi[r{@lQ\axxi~Rs-w/
    KDI1G}BDKzRm~[u#2.DwK;OD;O:x,mm,2rWw_EjU^Gl9a]v#B@s-aV\I?p2~iRKu~pXYYR*_lk2D
    ['wu(>v_TR~RHBUzpv3_G?[}Y5=R>U\@HR5UQv6?HB5?rsTUXz3kwOE<=QnnT{lQGHa+CsB_2_'O
    -DI5T^'by1HuHDX\TWHo]k-ei3lQ{TjI#r<ve<pQ^SHwIG>D=v%xp_2!Q$?Vp3Vp<a[M$\VxI@>n
    'wG3e'-5]-AR#{TVR\@TAArj1VYETo^ItOOV#i<x3'pk}x[+G=5]{QwBkn-p'pluXT'@D(vw]<n>
    @{xr+[c",J\RC-j>*J7m7Za;60|'iHEw^u\*HnXrzl!T\<U^aQ$LFh,]!uDWDQE+Ha{Q+QQr*lE<
    o,$Qn,Z5QrJGR~'r'_&1wX2BB!;$iox%5\DX/^~Or'EEW+j#k[,Qime^#-Q533nj>$X$pXe>{Xo5
    kAw$JlVx[Dp#I+H+sG@o!Fn\$2l}7AU1;O_3x;~1nCr!aaVzawl{OG@_o<xzA{EK\}*$OBpJj+m[
    *Q0IlewA1jrL'^~l*7k3'{J-47KYnZ]{O]_Z;7{''^pKDo,VJ#G1QH^]I[Wu;DA+KWo!TOoi2V2>
    l0BEQv=UUC$;7lYZ;Kk-n2W<Ua?E1KR<]2vrT~()?=EstE!V2OvGVqH+a>C+2{5Bk*EnWYu5_=H=
    e=;XoC?1?H}mGo_XC2*5Jl?U@\vll<Uvmo<X2I$h4@5[<@pk#D~$KxB(lAUxNC!Y?OmvXeB3u/NQ
    JpR)yZ>QKCD[zB@5I4"5TY*!vVk'JZjwz]<n1X{@5I7V|Fsmu73[-Jja!2NK5=*}5;,}OW_nr>Qb
    [AG--1!edu.=O1[v^>HD;Xe@<Z>^a~U=kB1nVRk]j1uR7&},;$>x1>5u!nzmx;v!1iVZr2IK*<F'
    'jiIr{VC;1Z>CG$]^GOV?1l]CQskI1X{A[#}~[G~tGEoRJC$i$*p=^+XHVX|^a3{;o}BHTUW\w{m
    B$}QWnJ+jr31^?j[S#aew,>>owO{#+U>Bhn=xDw\2am]}<(!X[';es'<'n[R[AV\@*7\>5$D]#Ha
    sG2*X4IvKY=G7i5}IKwXHuVs@+2z7H1!lDRJ*#-joW?Ez?WjR\D>;^.]2uI!Aw?/'ZKTi}3ule[^
    #E#jIX_;_rA#?n**"5j+siIQ\Vx@x52+@<r2TI,{rTT{jsWnEE^v=*@XajUxBM-<]@JBDu@s-[,V
    +Ja_Akn}+5}sl\$<V[QY$@*z,H}VD^EomJQCemFXC25Rl5u_O<2z-jXb9OmlID,QiU7*JXQ?@Ds^
    >a=3K7XK{QIOW_x>m81{IApI+2$a5!Q_OKQ}D+vs=#:;_*HWTW_m}@Ie\O<V^#7i=ERP3OW#gzpA
    ,DI~@v_;KmT^m!vvv_RDJT$$oxk>;\<*]k-,Z#C{?D<Iz{'a=Xsn+$pa$-C*R0nB$,C+oukr<~om
    +U*1sHQ<_QBXlnOp=@@$Bwu[u-x3pwxRu*>^u^\O>pKTR=l}XwXRnv*IQZYx>T[{rI>\?Qz<Hx_p
    J>++*;qjY=w1rH7_j$'pv[2~{C\wa@'c#'n*$*~v4{<Wr$Zoud"d]Y2Z/Vur]hVZJ5Gz1''3u57}
    O+!+xUTREW\3n]JDmD]>_w!osT}IUxUrxImw-T+BD@[u=]$G^'Kq@1-x${{>pOKI~Hn#+<1X[BiW
    B3@jxl<}^Ea^K}**};+o0$vr7YaS>5lx_b^*E\?xi}CK'OQA~[D;AQB;!*_}XU[7!}#\kTux]I1E
    v~H5Q!WR^_3<CWZjz,SzOkKBjv7jH$!v-XZ.H$KVdmVoCVwO{c5${?XG-_;OB?'-2T--z$D=\@'H
    nnX[sO\$[!nAIw}]Ok@1Tmmn@xR1aZ}+AX-QVsl'1@/r^z\8LU'CH}X1$\@w>?pe?oxwnIs@Y=wz
    Bl!GYVT>Q2I*_yDC}V-H$An$K31JQ+G2*}A=p+e^;2~r^~lb5}x}3QaWJTmJVj-#?Iol~,#nTvYv
    pm^kVWAVBu'1?\+Elk{w5;OrlOvI-w*~-*Ja,5ao]2}>Ra3?Bs*{nEzeNl,jQl\B~Wo@oZ,v<K->
    xa,#ZeYApC?vRx?=n5J6Mx{epDsnljW@?x[VwpRr-6=kGsBKARa5VDIS\AVaq\\Gw'j,?c{'v;'v
    J{y?r~T2Rx{w=z$O?AO1w}RkYI]]W21s@D5vW{x6=WaH{,>[m<,iQkUl;Q!HO?1CTv@?21T]vY=T
    e^Gm2zpCK+3D%[#\^YzVwOxe*Qo$pL<OY3YWTWliK*=$YDwT3\_rKv~[DaeYZ]+{C@Y#}{n^I{DQ
    Z3xHn72[]o^}I\mwIJ[?G}-Y}x5aAaytKwDKZ-,-v;<K{wHes]>,_^*oE5Dn]nmI_uQ=zU>o[@3{
    R#+x\aBZ!^u=#,<OiR;2~l~1sU]_jjJ7iajwX><{Kl2*$^#*q^H[u$imZ^}CVh1ApB[^*v+ojJ[B
    JUh=@=ppIXe;ViY2E,}m>w$[zpmaO3AkOT5rziX#As$/BaG'&[,z@x;BCCQlAgU7j2w(Jokmi{D7
    $kaWvFkRwkz*pzlGDwl7rvjZKvs|sSR=OoXpaA%5U+_/!Q,~'X{ZBG#??sVE'hjVipX{B5G{!OMn
    7+5$?GI7o+26^Uun$3XRIY5Dp=mw[Auo7}k?VCG*]Vj}fj+jOBK_C_Jne\X2TV>wZ*{2Jw\kEL6,
    l[]-,m{qr;OUQK-pn\[ig:-,I{e11',o{la'Z_3sEj|6o<I_tW}Q!2>njI_Ts#Y^@_uKIrx?eaTC
    UD?Y~\i~s2$7a[Y'zwp{I>x[e;TAVw7aX*}-,!H1Y-HJY[;jKiRGl^G\[bNXw<vulJn_Q*WQoBwI
    ,Ekl^>a#pCzZx1irGrm'~3@[Q2{V\HH*QrrV+xrriI2v#Z?=B^\Qn!lI2UYZG~G,{<prrXvcj[E[
    P&J+@]T1Qr7BnQJsCx{'BB:G!Qn]K;{e;--C1iEo3-2[?zAXjZK[D7r+=x2<HRUo=}=jwo+4Rajv
    VYKuY'^EwOZG{_+m57^]l[{z]1>CoQwHm$1@[VDJB~a~Si-=$Hza7TwR3[rVaG3YI\wX51v*s?jm
    mAGJ+e*QQ]WzQ]'uA9X[BJ@7n-Ej,xV3l!eo7s]}kQji\Z1Xsiwx?TjVe;{^+l*s#s/H+3\^Xr,]
    U[oE=a<@O<3T_*+C3($1I=q\wmKBI}XGz@,fc!Gz>lH7]<B^}A{K^eeQ^-TGU$Ok^ow]RND[J5XA
    Ynr'J7c)H+}Z>_u*[IJsAr+xO1!p-V<VEUe#t5K$GJ<]<TsZXEB5+Kwpp^KvGrWxsQm{#]oH5oRZ
    HQk^2*#s7&}KvxFR~+jE\-s/jR~!QDK*]!pR[Rr^K-I^{l*<\psTQwZZ^moTJIIj[Cxu'5$\E1@k
    _;j{5e=Y[eVVxR8o,#Qp7,p)VoBhUV#KC~]]*{QuDC[XE$UD+w-v]#=TLBj\7x9?]11_v^O\'H#{
    {pEz?O[qmro*'xB52A]nwT>Zo,s~7kP\xA+k\xu5,U1i^_BV~Ya7+CkVi-YI!>xa,+_xw~3F<*2J
    xHBx5uR75]$vUO,$z~nzBv#p~wQ5OH}j4.s!Cw.DZ$iQ=DJ3]@\[OC@GQWa]<A!^;nU]AxeN>r{}
    QXnIoH;ue'#,vTKIjoXjKCI1*n}jIE>RQXE2R[Z5$m@=OHHQI$j72<EwO-rEa,mR,HeRHXVnrsE+
    \x3+e7^O>7]\Yp2X;oTAQm,}IV!*l}}{Vl>lzZrT]C@R2DYRw<K;#j~@C3ox"^Q,UccrA=~^+DAK
    ]CaQOlB\O_lgf]K!<+Tp70Pexs\j$[=,}H5x[RrT7Jk7>WCO|Hzrr,S}n37!UG#eKCp-C\l_,pOW
    [<X_Im_YXGK!5,,Qi5<e1EG^eJJ=+!u$Cp=Vz{vKw+B~^R*E,2v?^jYEK>C+OY>B=~jL1{}a\nnZ
    -{KCrW_=AR!,CX$@{>Wzq],*Q}5]Zl;zeslJY5YB;v;xD^<0>U;B{]pW!x2H1*j{s1{\>\@3!7r'
    D[Xls55EgG+X7aH_snr[W5*T{uAmBN=YpUo>2#\_k<v#*D$;N'?WWuXYYG1lJ1a+1TH{UWG<K{U+
    _UR5e%*wozB}T3EGi5zeiG/_?Q_wwBBnEDQ]E!A\vVl~\TD7-{{AE]A,#=7][~zGzn,\D5{sgpAJ
    ^cOz=1S!X\uB+e5wORYi,ksQ<wTOeJY}jDn^r~B(V5Bv^xE\i'QV1B~Oe\UwH=,+S=#u@H^jrXB]
    +$}]D3]HV\aDxsA$GnETI-BGI9>l3KpSo;'wrpBzwva*+GY*x9q^BDvu$\[G>~Wmar*35WXwx\i}
    }^$W_wk@I7Tjz]p,I<_)oaGVzK>A+l5{ua+R{e~oAEe7=DG3K]7E\=_zK7<$nH2*D^z]H]?,moao
    WGA1W''$'D=Rv{OE-Qk*#>sK#Rw54C_@r-IEBQUw@TIU;+OHxV]k#sY2z?CA*TH<ae}jA=>m+|#$
    v$.fXYY>]WH^]]Z!}D'>Q[z<G?zxXs$<jnEHZ1}_CJEe2{x^^>ls!^\[Yv-[RXBv[OQ=IIa<}WV?
    v2K*^HYC^E{Zv;mVkOpKD#XDHn2+.3jIBU=Z\]{]~ir2VK[]wv+Re:8-<zl{5sp_^IE[?\3W}r^]
    =IX/[7OIBR@$p\sC13Ts2$U#U1<poxsKiEpx#ErG5U2_l{3;Ii;nhYI;'se-]-a-}1znQXH<^Za4
    IY$O3vGo+,x<1><a+5ozC\1w!R_,<GrAOu@~o&*xB_GmEEuvB*CZKaz3*!ERr=e-3Z1BH7j$+K@]
    ;U#ew+B+$I0?A7{=}_kU{v7h2B5rVW\oQ~R_Ez*\XTv{ER$Ij]iI%i]B\$+JjGXG[wY2~e]Tm<RH
    n#<OA*mVHsWsO9VmC5,V>B#]r+\9*Rlj4,_$~'XWXjlwzu*vuXH,vDo\w{<C}lYXUuTJJZ][QJ}e
    X+,H^1VmwB\l\oG?vx+_*v/Yz{?)x@vewE*I_X^14YR3W*_;oj-np\A@#paea,n_@u*5ODO1K7\?
    V=\V^>THVQJ~H_{KsCC7YLfRHXo,$5vCk,*x}Um\*Q}pU(HziW}\+sRIIzW]s+FHT1x*w^rV*537
    nZG.Xee7jGl3L,0^#,mQV[eO^l]=REk7IIlI*2{hmlmwaB\U-'XaT>2QCvkxCm,AQ7TJApZX;I]O
    N$PZTUZk'kp_B7GKCe-lWVsi1v3R!*2;RC+xX*;}^zD${EezLF_3QH=?{~}^oRnOQz'><rAvKW:B
    ,{xljv$T*C,T>\m2>2x*1VuaHjv${loC>Z#ctyK1r3}8mDllHI>52<A<Q}_TsR{'b%7+!1K$[zGV
    !JY,?!TO-=Cs5uS,}x^*]jODjWn:xZ@R71E@OU3\sr?-$e=mbpKwGzxz>z}Y?;[z-'OBRYO!A<1\
    3^<'_A>apnH7!H}p597Z[14x>\{ppu\6wHp}V}[w]\Ql2VRJ[Dk=\Z@QQmAn'RAm*=z?\}zU/AYO
    nG>o7]!1@\H_A*jAT:uvv]pw'-~}=]r5GAYIes,E{~^A=[[#K}{j^Bw\=OYYYpQ;7<C@Es!xD$]T
    X!'}ZHsTUw}B\Ev~@QeuDCYK$3l$1#Go$$msEw#YmQqanJ+}3A!on1*Cr$G$CsUG3~mQC;W<*1QL
    ,,57l+G!|nG[BoO7KlxDjYeksV?HE\'?DvrzT@^Yw*Um+CR>R"r\AI?+=~'l5J^?_?-^Qv~5}C_G
    ]I[5zrE?<Ra<u]us_eAaI{L;Ds'>DAs+Ykk[\'i#'Dsu[QX[8DXZRnD_Io*$3Zorny$-ZoTa^AI'
    Q'j*1j*~3OxS?UrO>$7<vvEI@n{Q:Wa!'G+GxV~]OOi^@}^TW_uR;rzRIK*7$zi<el]'BAwes^7'
    -.w[V<['TR\uJjoJDsHD!U~-@^JRQs[5'mzs1m,Hmj#<}aK-e;^<w]pXK?2|\v{1vUJTurD$-'kW
    B5CO\5XvkpZ=s-*O3a1nO[l'CveYHplUvOw^e>;X^]mG.s#jun$D=QW~?b[}T#IYizH5\{Q*HVsA
    1[?1viOv@>awwx\xXx$JoU5}5'_-1_*oZgWvBJ@IuDZH[@[3R>'Kv~i_B+kxz7lr#m!55TY?aX]z
    Umk_p{!a$wDnC@!IuGxklXkvo#oo-Q_rwTlTYaGCT-QD2+<VW]CEEeXl]V,Z-[|3,a~G-,$%*5Te
    rGuHo1{OGUalevj_G,RHIJ[,RV^l+*aI<wT$zAw1OUGRW]w\TTrZxK1ne77s^WxkW--1YYu_JX-O
    [oXY]7xXrGEKY\m{l~jJzQ=$x\?QrAVA>-z5]5az\Z,a,{+ZVzl3#*2za\]oa7!r_s}K3VUlu,UW
    AjX~<XO{<D^r,7GE_ICRma^[,v,zLH>j7sxpJ^Oo}xR[+N3[_vmQi5oXo^rp_{s~ReaX\7Crv,7l
    {;eHVVwa-a_Z<J^COZ*2uXPuEiJFTz>,^-Gol?*pRVI7#D<?anl#IX=%,*>@]'a+p5~57wBlADDK
    {]Bu<VkVixxvrB[O<luu~]Iu@]Go}5_J_i\\UwJ;Ij?;W>=O<xjnrxCA8@veE0C|DA1H*WeZ,Y,o
    \Vl^W_H[kIex{]@nP"3A>!z7TJeFWoRCs>[@L6j\AWEu>wFMHnA-YW!#A}Wn~e$*_K1e,wHw9]Y\
    ;OQ$vhlOB;K<EoeEOpV*CDar?$TR^]AUe33'a_AU_CI{RR$=AnF<]ae-zC~1ZEJWn5zYzmYT1sK)
    EE?D,#,rDW=_*iTpI5+J0A5AE+]=RBX$ZXXDQT'u$cSmQ33>12CUYrR$#Hzsv]IP8CHlJ)A{l''$
    VJ]Rkppl,Guhf;jJY<&~ejix'v1.D>uWXO2rZ[z~m7+>rTX~W<5^o?Qus2!OsJIU~vnU]]<>lA5;
    >_jJ\A}H'1i<D^XUmHv\;]j@7;'uZ+mazw\DGze]+'VnG@XU0_^u=GEnj{AEDlYKXI'^Tr<@~>r7
    Q1)w^^,S{=;kqx!HW+a@H#Co$ArjV4#AzC}Ye3U*w^^3ZJ7<*@C_uW\rik2+Vx1+w7Qks@-w1u0}
    ZB]ueew?+mO*<5o>]'u01Ou\eH>]@=KW2CJ2;\aC[mGI\@D*q2xsZ,5X{ne;mPo{3?]QRjWTJBNx
    ]A-7j#j^<jA~nU;l2^J'}=#'7>pr[X^^Ja?s<=lvD#xl+_BDCxYGCoR2\<>8OHVG-wjlo,H~7j+^
    5EA1JAoRpQpU+lwWYBO@rB<e?-9)mTvu7#-e_I]Olu*5H52}77>rY7uuGBnTdKDz_k.x2DG3UE!W
    vvD#]TIY*72+wWEWrr[UsaoMdHwK#BGK=1^{vk5sp:*[~-t7A}+KpXzT}V5En,'T*+2HAjoZ[I\Q
    aJ!lX<VE*>ju5>^Z^upHoI#BX^}5$XpROm[vUGU#{K?~BYTx*CUYbrkxjYr@\rF(~T=#]V}T7p$3
    5zWldVB5k{GmOV?17'n*TkR+k<CAs8S*?1;iwXaTxX}[u=;xx#uO!K7B7?xjAwua_KA[?QxXnmmx
    KapKlV\FGk2,p5jov[
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#>lU{DH>w0n1_{{H=]}-O7e\IYoUpH*[i[l~*7|"]I_D,,_<+HWr_e+[o3;s]eUmAY2r$_2*
    {[nkl2uX>YT}aap<+1$'Q,AmOoXA31,['>KjG"]ZlWLw7BW=HDj=V#mi7iuf$JZorn}G?n\[$*<@
    lNwavZq31lPlF+Up'i7z~5r}[CA{}c^3wVrowUsGUm7@p!-wl>W'5R=n}QO?CGK1v3EwIZ:oHjV'
    p71*B}J|,V'XZzeTHwnk_'--+x-rG'EW1sUoGOr#*jmJB;[B%HXE$I<npwAV#<n+#FQ1W;!aH,iC
    TI[3{#jijJ]3s}]DkCu{YT6EK{JG*33?1QKzAaGWjx2{x{++RXkDu-r_{o*B~AVyF@B^<7C@X^Z<
    #,pn7{Aoin1vEHtnRV7c+Az?Y[xw6B+@k>lkJ2l~UUDn]KAA]l^_XREW='7e<+O)L1mp;#5K*GD>
    5{r?l^@2Ol#zr$-BAs$VAJV1p#r]vQDanuV,rs3rs}QE<OJT=Jx3C9W^5]XAIU^2uHDpo,vE}e4-
    >mA$5@al5,7HH[?pG-ok}>EBCs2X<h+R[$\\vBE{TY%$@}+T[aWu55JWnx!UVAXC5=*H=B['!-,^
    ?CunQxG^DS:$D+B[U\jma7aok3a3=<?\$,^'^}l+*#V2os#uv?~']K^{*EAD,B[#a_5QIEEr[1'D
    ZAT?<^HmRVXJn<GVV;#'3K~'3}*+zA-=[v[51Z\z$Uw'7pi-R+1=Gr\7^GG=?RUE?H^cgLO^<$%^
    vueIAZEI>jGn>j775+H5*'kouVT\Y~@K-J~Q}-Hosx1H^QvTDiJV$Bp*pD[Cau[r?{zIE1i$#w_5
    iaBopZ^-nmne_-W5-U~i}o7nDp=Q?ZnYjrkc+BXEliu'$eW\BJsT3-1R]dBsoZ1nARKV-Z&OQYvZ
    }{{'1C_Y2VWqnll^vf'GQIi$KT{on,zKCw=K2nCpKsZ=?$hh[ZB3}iQ<,WxnnOrpJoAsjU=mr>Q\
    7oXDg!r+z3H+lB2'7s}EC."LpKmX$+B2v<]}XzXzn][xk++CkHoni+'zW7{EGpkIp<T'[aR]zOm*
    V=^x$']=SIs-'up{['TCw~HYxIezapcl>*XR3O!l_-]TV7\$p#E>EKepjIplUwKVkwnvWp[mx]Tu
    CVCa9}->p7z>XZGrwxsT?~^Z!}jea|)Xs{@\VK'--_\HrJC)1tp3Hp>{YV1KneKp\Tuvjr'D!u\x
    {2'BA3-jU}E2xCiX--#,xiw{+>ex++!xA>!Q<DDuvvLJnE^7_V!-Y>=xG;_GjC3Im<J7]J+VxOUn
    X]{]$],B'TWzD$uzZG7rY?Y_a_OZ>'mYK,72\TrvKKms7GTSGmp7'WoZTsD?$O7v>I~~*3]Qz=j5
    >jeK#G*aYU5HkpR}J=sHmvTnXxOGl}*o[}^vh2VCVr@,~X^<7\_#;ne;jb\a,r(vY5=rWOzD{Q{E
    spZT$7r#$W'-Y->vk=I<}i7<*D@%l[C{GCC<N?nI^\WEo{XD31UmY}RHIn]n$Z_pjrV+TR?l>r[@
    UPhj{{;'XUI2}jx,-{!]l?O~ORlVH!,G\CKrzVjI3EEZw2<x>}TR$7C[m*_-V1_:I|eEwJOO^*TG
    w7^v-#i>=OYDd.C~Jpx5TB!*nC!>3mjEwO]eOsX\UkvQ^-e4orZEj_]BQ$WDIl1EQ;1uD{OE>-C[
    ,Q=CX_+~ve;lsx^kx7TvSwnjYfjKC^RZmRr^xW{C\pxVn~5Vs7\Q;HJx^is'$m^A_WdsizGS7/EK
    J{${A7E'X[e3!E2[CH|7,*js}%U*ZKlrVI
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#+\zz)pJZCom3KB}nA,E+*WIJ]7'Wap[6&wa1[yTQ2a%o1WQ!+E#1^_J|dD,H$}>xzG3RU+a
    $QQ$k[sZz%lwJ#*+[[o_n=['CW!Ul$HUlIH-BAIz#^^BU7B!$#m|2|yE@}E=&BF;,!H<}?Tr#C'7
    A<@io#ult6/*O7BlW=k72]s]{E[v{G@$:7*-3TCC+wNQ*$Chem2v'>[nH+<!gCzvI[R*@[S?AVu,
    lA,0ywY?Zq><=ux@nB[Kn{B@$J#HJnY3pUp@j-Ia^^&'\]\Aa;p]5Kw*5~^VQ1o1_5$Iko\=kaT\
    !S'=1ETs^UkxA,,7AAXG]-]^2Al_-CXv2lZ7'?AQTp~n21-<pZpG!KEX_sx^C{k$JO2as?HB1;os
    C=RG5vt*JnC>aV+7GU;5+{Hw5oiW$!7*GD<_]ZC'luB&Iaw3(_N[yZ[i2=vHT12eVG'WRTE+~\vG
    KKT>n<_A7Wp2+H_;v49o{I{Wv1j1d;<X?j%?TzExIHe3[B~C$_!z=<Zvw$mD\X1@=$Qm',*u{[;T
    1H$N,w\~t]_u*7~*RB7ZZ]p5;k+r!?7]slX@r*C,O5b1xnaKpl_A7#717<~}R+x}E1EuX]I^>7R"
    }>AOm}<a!9j'{\bOT-,Nzi=~Imsw+ED*5<xRDQkJTr]Xl{I^1Rln'!=zvOG{s_lZ&\Z-nvs3+po,
    s;lGW;U$pa_2zZR,sCxvK3[rB$!H<]rBpKYRK2xBu@o[\kAJTUA@2GeD'zDoTY{+3XClB\kEDExO
    +]o'Y?]1u}AG-RkOY9/~aw*:=xuA|XsRCc>$o}uR>I{lUX}zi=Aoo*K,rsT=?H_]W_X1'es~nu1i
    Ywa+pI5IHGW\j<}EUJ>ra?2_KR,[A^I2~pl\s@L'rkw}x]*5raz"2p]ZCka]^HWnQ,\i*{R_GXY=
    *rn1K{^!\k__-VWB\}]}{}v^{YX!7Zekl*XOz[R[os@$,!s1l{l3#Or3o}#s;w\\DaUKE]VGWXRZ
    1mY]x3T'}\Jw64owx{#E,,GIl[#j}{/@\O@<vW{A-ue/XH,WV_T,]O$]:+]m-#TC#x?[@5BH$-<v
    zeeoiuwU<zko}}BmzzOl'2e;$kO+oDzpz$'DR<ru'Q_UOu\^T>^1oo\?u^BIiJnY!DZ~<zW^pNY2
    -Iup]wC)i{R;,Gm[#pYnG?5QCUoI[@32sD{<>7B#(f#>z@r?s<T5fC>\*c+EY^MRA,e-1xu{==GU
    5#7Ur'QVVw{7>-jwp{7#oU7waj]H\DG2I,#I_E*[Y7i*-VnE$Ip|>]T2=R>3m$RYoo<Ha<]#*un\
    1l<RPF}mA},X\}VUW>oQDTXREi^J}B?A'lHRDumO*<B?eJVX\GLs+,[8zDvXqE(hkl7]DW'RCx<a
    MLUp2'A],iJAD@*Eloi,V*nzWu#VjkY1=ll{3{CA-axQX!*3A;NJrT2X>>,uU35D]\J-G]{x>sjI
    ~plQ+r@aLG>XXEs]ipz$>C+BosX*Ax++{sT\5&p3;awGW<1<meVn=>532aU\X\G]C]?pU>s#KX[D
    ~GaGv$7?jkH_mpI\JHnenOQRka\o?]7QXQIr[~p=YZKlNJNC&gt#aAlT{ppIW27N^ueO<=rnuDD}
    3$-[J^]s\al\TxrTJz$;]<lau,?p!G3;O\w2KRe}T$A}W<YT$={@s?3!BH7+7]Ov$+xo|%$Y~sGj
    X[TrW'I,]$<ev@[=1[aa!wPNKCT<'k3=L\Jr}'^Ys!$C}MHl3aeDFaR}jl;7j}Iu3k]ap-E@op\2
    w6U7o?[-Rz}aoDW'?=VE#=<,iE~EOAP[-o]B{7jGBlYH-AZ5_>$}c+.r!+=\zIX?pjl_!vpdsQ7@
    !5X'Z'Ozx]+osDx5r<'rI$C#i^jvuRuC"3HCR>>U_0''oY^:r<T=2=J3C-Z}v^_=zL(3]GR]]5#=
    >A~>=1XGpov{Bm$VA,v0<Q|D=wD]G~~?n}!G->{Ue+og5UJ-JD'<1>Q!IX1i6m|x_z?E#X>dR~CK
    AS4xYZnB>OV
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#kRR!xmEuACR?ao\X_Ikz;Qs-^2;?Df^$#!wa1["*wUw>$5sr\2<Y5r[rZ7,2s3B[=2a3'R*
    sBG#^2$+>YT}aap<+1$'Q,AmOoXA31,['>Kjrl1D_$x]T7TAj'_s1+G?a{}uf^M'C~a!U+7BYX1R
    ZW$RmlVG=*QnxV'kE_XpOE<9aE<+Y~A~7R+$Vv^j?'ZRD\*3O_iXO=vW=x],szQVVpZjzTRxRW@Q
    [{Bl"~'R<U>~EH*uuUY^<[Oa1.@+[?ZI?VWn[pEC#]2l=lA'U1}5!Z$sp'S[TVkBWO\I]}se~KAC
    Y*U(oWpCH<VxEy|DzsD'IzA*HWrAl<Q{H^eF&*G}7Q~u,1E=R#ojO1_O[];D#v_Y2]=1,M:*Zo{1
    2l3jknRb!D*ezjLU7y('VZ>2'BlKD/l_\!6jII@l;AK7;Q7at!D7D-SEA{WjTT1N.1x-Ze>HEi_l
    T<hG~^[|{O{~H]2sJ<D@Bs-[9{TaB~_Q<Mzn[T7>=re_@aCs+CoTV_npjmS'lXE2r2v5<p@f/#z$
    nWU!!YCW>1P5[GwE?wJ=$k}zYBoV#vK'm$n?]?3roZlk=B7!UB=Kv}2yEF?'O?W<e![revvIZ=}a
    ,]}OHC;o{3T=>TIew'QG+}-lG}S_VTp\gp_n?'-zu#<AAR{B@7"gD}n~R$QHl]moZo<Be!][_Ymo
    3{+5?*@Bv=}}mn@-2BDpAl'r'BzKR)vZa<e<YCjD-KRe\vRsmHUE!jRYDlGEklGjllt[$11Y$HQ0
    os>n#X^!vk7O*Y}GBeZC^$mXz+lE\e'mRJ<O>VQT/eV2^lGxm3+\=\JIDO'<O6TRWC2HXZxp;W~U
    =$OooUu+wrCe^+B;nzU}==Je[>Ar[5%$;>p!X^<oU]lnQt+wnT?w,jzH<U(nBZVvK>pYC2zL.?]o
    \s^n~5[}iT'An3l-YH${^"2xK@#<;1\k-kdN3{;,5[X?&{[EwpH@E5\z'BsOs-5Xwv]2uKEv~3>1
    <Jnn1;x{J<<!+kri1AAK!osBB{'[,x5B>Cnn7ss\?}\ep],J{D$rx}eBQ]Qn2?}7Z<o?]O_<Ge1z
    +j#xYQ@eBC's~1,[xRKJsiSXan-ww^=[E\'p_[BE1^ub+oG*bi=?CvkB'1JYkw[^i,1HvHB}zY+~
    2HpVXEi=?=2BWme$TE;Va@<AGHUYkX]iH\X2{!z$T<,?sOSVi153+\pOi
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#gQ~R'rn@,'\_~H$'~x,v$WIJ]7'WaYCIi&wa1[yWs'i?'Oz}oW1O;m$E^R7e^?O~wxCO$W;
    zQWO4X[+2U{){Ck;G$k\s{ErsSKwJUz^;})do2Vnn]]_oz}[~XuK,aY5TE,io?wE2rp=lQAG!RG2
    eM\aaI[Bp^gvnuCI#EA}u1Eu'I{iYkKD$A\u^EkjD~}l]=il^]z$DoGV1KJ}BD^81nezuT<B53JT
    36%+5][#5!oh8CTxQQ4[3Wk-r'u'$=W]4+^x~A*<K$ADUUaC,Dx'OiID,g^Ax]=j]Dl{eEx7L;o~
    ]15O{HtDr$@rElijupAll$Zep3'PQ2;ViaT>HjUW0a}EaxK{_YZOm^HQ*{aUHjxZlI@IKl!XuR~+
    w3BsvaoWk$[#A2'QvUrYZur{HiH;'VVJD_OR3sAQ7rz3+;lmehWaZUx1w{\<*a9bU90#RoR,WuC~
    {Jrxow_j]JGiUoo+'ieX,IDQA7wBw*vzU1+$D~}!oT[~sK!-+[>oj-$L-zU}V[Axu\Olv'j}yJR#
    *LkG-;,I+aTXKV][J<v!eTT7z1pO,'Pz?7xMi{K;[D{1HVm[R&#A*jHG]1eO~z8evy]w\['?X{6^
    rJ>r?'!vO~Eir*1pJJHu'rsx=X?@]*;/4JzBB7QY#Aw3nYwDKJrW5EDU_B-zUXa<OU5?WoT_K[En
    D~AnU37Eu@HC,2eEu<BV2~,m[g['mA:Exlu]UYRUs-KUIE_,o*pmQl1}e[ZeVum^k}@QI$ecVijr
    v@+]X}>*dC7VsWCKXzC5kE>Oekzaj1,@$2IoHQM@<jkkQQ?^#-p,O;a$}>YvC[}pUzoF3nAGO1Vw
    E?1!?T]UOWz]X,TkG+1pB\[7v5QzoUX=,2DUu_-{Hv]kc~>KG&GU7D^G!CxVXY]eHYIAUrQvXlxj
    s3zDQ=pT,pHG<KrG)WoHj"!ep_n7=K7H+TCr+1Qp2JuDW?YinrF&$EUp;5?Bp*{^=W[+a+D#YHf7
    lD2'Uw~LoY?2*%|\0J{BZq7+~Y|-RRVo~*VHE?\VOp;]pAD:71?J]UeGDs+-\3In*uv3L2x]+5<x
    e7jru]3ss\?H3KnO#x5BwjR_On\XD12n{lZE#w{^ZazIv&CEBmvlleIT<;dO!zVE1Hu*;zi7*@>*
    xs?Rrm~I!W=x~OQ7eA}A\#pzs=s#1'~irz-YY^iBzU=&;7Xpp@zIKaR<D+Q^?DJ3+CnCr*-w/R33
    omHQZ=Bx]x7[-Q;WUyn$l[~<B'YOA*;CuGSIVjBRovezI\}$A!^HU>$37jHTT5#@[EzY\oGW$<#7
    ZxKC3K@2e-vXa-RQWBrEuYH'Tl!BCJK$^V[s[nTLk$;lP#]*Ov;D>7sv!]GH7PpW]u(KpDw7Ej,N
    3wlR^MC[2;[Ov!BQppjYE?j3W7k}inQ-VCO{m<tD}ZX!=7\F~z^*_1K;E}A=>RX']+7~1'2r0y^O
    Vmw>uvbx@+!AO_+)-=<{7f>nU5!{CpQzB_Na}7152B*>eA,*D'H#YwWMmA{7M{]>s3oG[<,5\n>z
    Gn_}RGUo!e5VZj$u$yfm|x\!Gp,n@k[OIv@7#E7B7!UJmT-uu=C,YCDlv;qR{7?,_#VlkW}]pDiv
    <HXXVm=}~z}\Q_Yp;3\@Crw[5:?zGB6^Toa1JU-;aB~+=~UUO1n*X>IQpm7iUZG1rsE]ulpvU+=-
    pe'XwAavZje-,?Gxp$_RpzvXR!<p_\l7v7@inV-/,X\[(!o_HU<~>a5{}<r#mUD!Hw>oC@Tn]1xr
    m_K;<QGU+Sqh^ZJpeVD5olzu^>m}n'+YUnmQ0yQ~}D\GVu],7*\KZXB?W^%*vZ@'3jH+RARR^YDV
    DE?XXIj#*X>%y!+HBl-r]7U;=2DW*Uv#@U_nvaY,e6a,mEz/IX<B'IV{mp57zH'Zu7$Is5W[ZYX2
    +x}#qYG#jWw,}Z}wnnX~kDCE<*=7WjRns6d0>r7ao+BaGkQH=rl^\EVao{5\j@-$;R2@&A<7r[+1
    Bg+Gom~n^ZDo[O@xQeqr$-'!Y;jv+1JX&[s$wJE]z_W^AnHD@KD}Gv?YJ$sx-jR7dieEGuB[2vuB
    ;?D;OVDg25Xu{.[_e_<jWaE^=YI^IrUva1k9YwTY\n\J+YUC@aoI|-Cw!Zl#X#AjzZvT<B{3^XO}
    n#{D_e7oW+}3H)vEAT-n$B}m*V$'KnGX^vrQ\_*+l@2\3j_>-[YmE@5IJJRCkT77MsWDJp,.']*1
    =C^CCemT@OsJ9Eisx^*Es:N|WCeKrzW>.C\Jnp2>7~5'<GlRk'3>}E~UJIG<Es[BmH$^utQ;Qr{o
    r>A'X7[E2}_-JDk\E<,aHpQve!_oAQX=]rB5\;zG-emjZ,QA1>^CUQi$k@u-vZ1unneJJIT[7B-=
    ,Dx-GYzTRa=EAv!vEn+'kDA}~C3<CGvO]Iz?*u]\Y]xB!\mjJ^[j~?eY~*IMR2o=\)rZ'7l_}~#1
    ;;;e*+#z-$!wuo#az!F+nzIYz]VO?lTCXmU:E+$I3]vieT]H-a3m@HY_w$2aB!X{mUE^dp4_Gj=v
    {><Rmnu7x[<+*UGrJavIKnl*Ekv2Go!aO~s*lT^'CsU\^@JRZuE]"P@EBsHUA{}+<Ki$Z72,;X*k
    lpxlJ[#Aou}!OOP{^H+|DCG'@w\Bcrw3HpG77HvG!YT[vjKp<DQ~W<sJ[T[#5I><z-}XrE\XrIWl
    <Dso$O\+B%W*aur\\^koW;:]w<JBk*[r~mJ;Rvr-p,Yv}+72ajnsCl_c#QO]I@vE<vJDrUA>DAuK
    }>!GH{Cl@O!U\as$|5.&>=i7ja{E,O?QC3]^roE5{<1D8l]RwO$wK]uApx]^H}5@'UL~{Z#EQX<'
    ~UlHBY]>E,z$+nEI7]wll3Tk{BAITOW;v_[]3O<CwG$^kj$vhYI1[SsH~$z]*n#RVzOGOiJ[!#1+
    *u<}rEo!R!8mxi+pEaaI!xAI3s=v-eJFQ>'JS}Ewo)!_CoI7ZvI{u'WI[1RYR<BeCe,_\w,Wn?WQ
    EWDi5j7sTJOzWBA*J[z1s;>--1*i=~os<Z&b=v*2BX$GQe+\Uw<RK_z7_>Tv?$ikMe,m+o=QjjVV
    ?WlQj?,+7\J11wx_Q;1V!WBo{#*=oW[R$b7unjQ{~e={m;bG^TWvU,kOpI7o2C]t+z~JUo5E4'GD
    xABCr:5lTH^7X'ITo\meDlgH^Uv0QC!s]Cv^1XE513J!S[>+WoXDnIQ~Qmr]1e]u3w[_5&]1}~oX
    @!=QViZ]2EYi'X5slxp[wr|oZ1nXzDXZw*eMl+uE4I^k2ur[OO@=Ru5x]uU-ms1kYk<~QwaO_nXK
    e#>rHr;InvHn\Kvuaz\oTio-1!+U!r^@<--|JRru;*o#{xT\JDjj\EAE3*a7j5ClH>CRp*VT72ap
    VV1#DzGJ3EAK2U+,$D++]*T>[J*XC=zAIzMm,B'vlpECpRDk]?*is7{]5]uCGYRX5YJGo@*Q#I]>
    ]XQ_a!;=s?YLBhk,nDrY;WVAz=5[n5O^{YC[RCH*!Q(Kn+$CoQevoI,owC=WA[J3Y]!OU<>^xo>u
    v?<E<*]T{D@KzX#e2]agK-[K1n,~Qv<rjBUoS'kVTAY]Yz3{RpYrjG<'Z7}wAK<\@10l;'lD[I\I
    ]5pH-I2Ap-j'R-zxiYK?{uIpOx,GiI'<GJp*7i\,\i<t;IvxvuD1%HpnpuIl+}R+QBywG\,aTW^n
    <J~/T5k<u_rv*5x~v}o74+C*pLC$D7k}Qe"feJ7QTaVIGZvzzrs]{O^VfW$m@;\wzsRB>oE_~:-^
    $_NoWCg7TrQT]sUWvRnx>Cm+'5231WD^7'7!s3wEBHv>Xe*~lelD_V^!zv3m[A$1pT;Wo}7/QVI#
    }!E@w13v@Bk$p!$OYAv5^rBiH+KW*I[x"^{51RHZ>A+znR\>l=e*Em1U}s;<pp;$BYoxZ,*jJQ*T
    O57u<_Ko1a'{[piR$lk;s?*,$*;TA7lkJIa5Gs,jEYi3VJxua#GOKBGQ^^E!nj*l]X'KjYWrxEu~
    Bue@}HnR7rGvBp}p1eJ@1zOR]#5=pOQ~1O1}i{+KR5\!OMomIwuBQ~'K3B+}DE$R<Q~vk_z7zIOU
    ,zY-+lBA_'[r],TG@HUE$Tz<vWAVV;Ym!GC2j?~75m+G'w~+^T1n5OeEun\BYYsz7s^Y>]lYTJZr
    K*]s,DOJDz}I^wWj2!m'vC?ok'/J1rx~j_J2[=<q@,73_KOUIA!-#E|Z}rn,zD*2\+~?a=@[uv_w
    YnOoTXj#laea,7>SRu2<V[sEva>eJp!>uj@Wk>m!)[27$%oZ}$%eXVR1ssJCm;J[I'K$]kr'5rxD
    U*#GM3Vr_Zl$K/sAG~'eY^H\-s8iOiE\w>;]Z'C{,s;C~]sADBj|QE]j+GOJ!o2IQ^wKVaXGl7O!
    WX_EBr*jV+r@'2l$<\Wx+DeXEo+w#BW~n_KA]U<1s,^o\GupRs=zA,GXe0M5CTuW1Z^@}k~e#,E$
    KZ\,Yk_IJ_Vr_v+;{~7r5Cj5*u2\>jik=x1e*!UI,a}Z}{m8I5lke\DC<j-Wmvj74^XeVRKE>Z+[
    [r}<!Wn2xk|{A=V~^um]Xr-4U{*'2[w}^><@\Q*3:'i{,P\V[VBWl]{ej!UG+emAU#m>ZafEDkow
    <5WN}rC,K5<kC+<X}w[J)CQ!H\}rinA3xCBor,#TXR|z2~^BAel.vpzjxDn^z=u!,YRe~}EmICJB
    3QHQCB$=hlr-331Ar#plJR3$?(QK\iVOTv!UnR#,IEeyZ<A5C_e3wDzG!rEH!1Hx3A'V<HU*m}U7
    ~r;KYEwKvJQEJv-Kk1vYgVDrIkvo]go_k@[,?DlY3kjmI}geXBApI3jXl+l;r+*B5-kCE**=}xOp
    -+#*~noGDET<p}rBBQr'7wR2R?^k^O+w&=?ze"]#Ap!Ern6iXwJ-EB==R+IB~J[2CCmw<BZ<TJ}<
    G~11K[Han=DkjG!ee^K9}zjiY21;J+msL5KlKFvaD]U*Vk#*_~MzzH'J<+RY=JYCYkZ]]A~>oxU!
    s@a1[iI1=|\VAC6(O2\#PD!aC,;OCIL+}z{}z_;IY[[9t5RKH+zsVnw{oXDI}5{D[6QB3El3\T^0
    5,o-q=v5'x3,Cvz~=pmrVEolZ5w[@,jr-GGViLp\WOBEGU}^7s1*7@zHQ_is_I#]~2coU\Te]p!C
    *T]J=+[rqk1!pe]Ho$sDz\jQsKv}OGj+ec(_a7Z=G>o{-WG^l>I_X_Cse#aoZ]xat*Jv?J'TY;_H
    Q}n^<,~m37k~DB,$n.#vp*FnUTRH-C#_~<m{^u\-rX'=ZXKcR37VO>]wo+1B'#1~z,X>RKnx1CvQ
    hL;$=*|2<3ED?z~7Uw]B#ew$_~$>Q#W9ERTE{z;3_KX_jQ'e.[={!]+]=k{>sJ$Oog\p?urWI<'3
    Q\$Y<^7_[lCD7wBQTz^<>uu>=#*YEwXI$?p[x;DiIZx#*EWlo;_}nU(jNqqmRH*>pHTa[lUciX,,
    R!XWKRB$ZTXpJ77eoKo'#U2!<G@p^iQBAsXmZ<aI^|~Xa-!7XEOK5<(2zw#ua>JH*&sJ5V5_Uws@
    W*bjO1-&eXQ7=+jkIk>IUwK2Gv5J=O>z#<IGKC5Xuw>?[+@opD@V3j]_FkQauJ^+l-$O3$X1#_1w
    $]@Emv3RT$YI'e*?7}JU#m$JJ_pmkI;oO-\?3^mA;>TW2<'XOkY+eG)p~X7\11,};;H^E!Q$'Ei$
    GDkCx\7iU=C}Q-;#IA~uaVEHCr7xi{ZJAI@Ha[$iDZ}un;_v@Yv5!Wn@\,vmAEYrD}=::wV1@z-Q
    +1$<@Ew<7@U$$zC;j-=Er{Y=R3O>*;QR\5p?Ek}T$JVvI#'RRoRkoRue3\AR@'-oZ&rEpvwzjuY>
    AQm^seBrG7B_H>o1~Ew^x3--'ZWUeZoKx+s}+_KYR\_Qwv7GwCaE*wcV#;A{>>k<{JR.3>+rC@A,
    4yEC+TY'[Q|-E[#8lw]*hF3AnB/ura]*'}+eK\u@l}pGK=-*m^xr]k]]DuAT-]OwG+u^_k=QDr+l
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    n:~H^aQ1e1#YIjw[[+~DXW^n7Yj?^*O>a@|@o+UmH[$~5DDh=oU@~1*n,AGDOZ2C]]kGlkD{*Gu!
    -aa2V0$HmVa\~,K=oU31]n#s+v]*$'[Dx\#lo>3N[7kDU]oOp2G;.s?}eKTGl#_C2@'=sCE{GZVz
    ;/\z[VBkZ7L'a^<o*KuuCpun1RJUVnl[uKn^E~ma+ZI]5-;9jOw5m++UvQ1oDl=1V&YV=A)\v#JY
    n]J,8=]>!W\'@jp_s[wBrBAauI[O2\@]v2'@wkEA5$Q;5!TL~n!kt\ipXS)\S\jp=&O#]1]+OOIu
    j'1j?=~-WU)-njn?CCon5B-}^Rjr~7z}EIv]QV_*sXjExEHWA7A;YQO7!Y#j\O#aVr]MTAnsdi^\
    Qj$lOv7WO~\^lw-CuR7*JIpjOaU{azGl,jRQ{)#sl5G;m];[n!R3>$B~wQmVDiU+}Kae!+Fl+}E>
    'T}p=7B^j-!}~~ItTOm!.iE@xupG]z$k15TsmW$mpYO~#6ww=VTC}l^lE\I,WGi^oH%13^<RR}u2
    &Ru^*,5lZHYpIT7A]t-IKp2$$#kRTBt:Aa[QaYx1i>{Z#ER^x3D3k\1XGVT<J=_ZeUUI~553U5lU
    m}I22H;-BIIvQ;I\^npGn^7W(Y{D1]/*<R-w{,BIw*a=WU\=BBH#sk,,xrX~=kpTsB$arnYD~ov;
    [pz=XK?Re<oIo)Q;OxjZ\'_kHsTw@2Q;43=!n:>GW-<R@[:!eB>^oe?[AzUonO!z#5UC}~GEvzYl
    J2K(zqmzXpG2UBvWT2?}^xIk=ojDe7IHEWp3[KKvV?B^2~\Zrr<UCaQx$YcjWTraAxsLr=?j,=eD
    6opv_}u@[a5ZJGEHY*-N+EGk=},5mE>Ju-xZ_OHYEi'W*CIQ,i<Jfm+Ke+_]u]'~pxY__aEC$as-
    {~U[Ra'Rkw*lU/X'!<;v37okCI5$~;V2jrY5{7GX@^@<mv5ZCX>aXvjv[KV&CG@}*z?}x^#KG$Vv
    ;roVy+Iw?5uJrjv\xz'[#3D1;Px~A]K^mrtHnrs!H!DbZn,!LRr'rj{Hw9v9E}\_(ODCjXR_@2R'
    [4>ozW2=!z[V{wsu!n1}w~wI@RQ@RYVIUEq1auG9k>pY}3_>'pV*UBuJ={BO@9C?,*4hus+JjzEr
    w=^o0[Bl{?[vl^GkGpH{^<O}]RGb$,IKx[nUQ>Kw{>zze!x_Plzk?HjCOa,'pm-T3Q]I2UGu\{rx
    Uj$H@^rlDj]aJIwe_O'X!#YC!#V}#UaC@!A@o)*{Yk}kUCE7ZI@DGuKpk}<HVos]~$veRpRTsrv!
    A^U]nCRQiB\ex=j[>l=oum_oB=vie*C\7EVWn;vAT,3p-]z#nWVUuxlzZ]$,Cr=p;Rxz5!^OlY3l
    }Jn6M-]A<C<{@#5$=3RG!0C\BeO3T?*l=B=u$Tm7m$EH[rYmV]~aWCP$}a@OwnHF(mBj=|(W+$^L
    EmQ,{_ijIjZ<-*vsI_~I'v1G?xk#\oOkX'vO!$zr,>IlKw-D2r*UA*Eu,^j<u]lK'Q^[]u<kevHJ
    _Ux~m]$K7\GQ,>~xT\J[TaXpC_!$B{esCJ=WVXYKla\#mDa;R'e~2$D#VA!ZqrTxr:ow<awEeBpt
    uE2QzrJ!}YoYCGs@7r[le+dxVeBQ3YsTsoexEa5lw]]rz}<CC=zmO$wV]iK5B5\JG<oBJpT3j<$^
    -Anq*C$ro}XOAA-GRuZ*@$E_p@>Q3]![xrD^enmVr~uxgHE@+Rwv'YVnEx($;G2r]{IT>vJ=A~Bp
    )@+]Yp_n>@p@{^-=Gv}u]>\25KVxBKRoa![Qp_Xl!;<aWps^u{V~E[AXw]ujmnjV+RBH,luO[}>s
    }pu_m-}-G_uBmyoI[ex<}wIaA]LrB^=T\,r/jY!'=AGlHx~]Jwm^8RPu+!AlKW/z^$1pT\{r>\5R
    u-WH^K!R$DAsDpvSr4V<~D#w\a#x;,RR$*x4G{ti_,'J,H1Ur}=O!]JOBAHx<+>zGEV"XYsi1#H>
    ,7'_C!!r^Y~;@T5[E>Kjk('#TuDzE!3xEDzBnX_EJ,zv{TvwQ$OQ+T@^TwQ5I~V^5l<e7AR;VDa\
    EHi-Ci#7nZ'w[$xo-zy\aE'7$Q0WsAZODH{iQpo"spWRI=v=T}HZ2r-Y\U2D$G,,k[+=y|AGK<D'
    m;=D#OYC;1;+5JI=mw,<@G@Qp^nGZ,2*w}4p'Xu=Y,\XT>\"$elXWNzE$Q=Qp,A[=V$2YW-oZv=r
    >R5}Z2>7xJX+'>;ji,_B;BR7,sT-_pI~QpRuuu{\\nRinnomxpz*TY:+1-u-HTD#l_+-\OmnxlrI
    n}ixTT?]Ymu1AAJlJR+rB-WOV<*52K{=lC_xr,*\>YI7BaDJs~uO[3r^O7VaEn\eW_;3*7n,SE<>
    3|GY1H'[s+_}Y>Rm@*e;rl#'z_oTEpsV3+>CICeIoi*]X@ZXD[>'!UrT_mk],l@[7Y=m5-RUU*I$
    zosse_O-JoAo?leJmWNw-\eRi\k,EC^m<X*&O2D='C#{!{<J?RW2+lW1$W2^-Ca>Q'Yv3+sJv3nj
    C5CKIUmIBK^I'wRUNR+jkQKp#Rlp5&c(HBmWG}j+-V<KVG>Y*C}A^o}$W={HgxWg;QwEJR><2l+5
    ^O+og:V{=j7m\r@UVi1?>X*AlpznAQo>XkwIOjC@;+e57\D+nH]*pepCX^ZG~!ZvWR2]C$Ye]]$p
    ]3r;-@pw~1RuRC5V~zv>VXZ}OZAn>$3[sY5IY@7D^nUz,WCRCZvk[azl1{3xexJC,1oEI=Wx]\1=
    v'"paaTH5;uzbjK1EGwpEm7
`endprotected
//pragma protect end


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_top) # (
    parameter FAMILY             = "TRION",       // New Param
    parameter SYNC_CLK           = 0,
    parameter BYPASS_RESET_SYNC  = 0,             // New Param
    parameter SYNC_STAGE         = 2,             // New Param
    parameter MODE               = "STANDARD",
    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
    parameter OPTIONAL_FLAGS     = 1,             // Reverted
    parameter OUTPUT_REG         = 0,
    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_FULL_ASSERT   = 27,
    parameter PROG_FULL_NEGATE   = 23,
    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_EMPTY_ASSERT  = 5,
    parameter PROG_EMPTY_NEGATE  = 7,
    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter WADDR_WIDTH        = depth2width(DEPTH),
    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
    parameter ENDIANESS		      = 0,
    parameter OVERFLOW_PROTECT   = 1,
    parameter UNDERFLOW_PROTECT  = 1,
    parameter RAM_STYLE          = "block_ram"

)(
    input  wire                   a_rst_i,
    input  wire                   a_wr_rst_i,
    input  wire                   a_rd_rst_i,
    input  wire                   clk_i,
    input  wire                   wr_clk_i,
    input  wire                   rd_clk_i,
    input  wire                   wr_en_i,
    input  wire                   rd_en_i,
    input  wire [DATA_WIDTH-1:0]  wdata,
    output wire                   almost_full_o,
    output wire                   prog_full_o,
    output wire                   full_o,
    output wire                   overflow_o,
    output wire                   wr_ack_o,
    output wire [WADDR_WIDTH :0]  datacount_o,
    output wire [WADDR_WIDTH :0]  wr_datacount_o,
    output wire                   empty_o,
    output wire                   almost_empty_o,
    output wire                   prog_empty_o,
    output wire                   underflow_o,
    output wire                   rd_valid_o,
    output wire [RDATA_WIDTH-1:0] rdata,
    output wire [RADDR_WIDTH :0]  rd_datacount_o,
    output wire                   rst_busy
); 

localparam WR_DEPTH      = DEPTH;
localparam WDATA_WIDTH   = DATA_WIDTH;
localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           

wire                   wr_rst_int;
wire                   rd_rst_int;
wire                   wr_en_int;
wire                   rd_en_int;
wire [WADDR_WIDTH-1:0] waddr;
wire [RADDR_WIDTH-1:0] raddr;
wire                   wr_clk_int;
wire                   rd_clk_int;
wire [WADDR_WIDTH :0]  wr_datacount_int;
wire [RADDR_WIDTH :0]  rd_datacount_int;

generate
    if (ASYM_WIDTH_RATIO == 4) begin
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
            assign datacount_o    = wr_datacount_int;
            assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}};
            assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}};
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
            assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
            assign wr_datacount_o = wr_datacount_int;
            assign rd_datacount_o = rd_datacount_int;
        end
    end
    else begin
        assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
        assign wr_datacount_o = wr_datacount_int;
        assign rd_datacount_o = rd_datacount_int;
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
        end
    end    

    if (!SYNC_CLK) begin
        //(* async_reg = "true" *) reg [1:0] wr_rst;
        //(* async_reg = "true" *) reg [1:0] rd_rst;
        //
        //always @ (posedge wr_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        wr_rst <= 2'b11;
        //    else 
        //        wr_rst <= {wr_rst[0],1'b0};            
        //end
        //
        //always @ (posedge rd_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        rd_rst <= 2'b11;
        //    else 
        //        rd_rst <= {rd_rst[0],1'b0};            
        //end
        

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_wr_rst_i;
            assign rd_rst_int = a_rd_rst_i; 
            assign rst_busy   = 1'b0;
        end 
        else begin
            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_wr_rst (
               .clk   (wr_clk_int),
               .reset (a_rst_i),
               .d_o   (wr_rst_int)
            );

            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_rd_rst (
               .clk   (rd_clk_int),
               .reset (a_rst_i),
               .d_o   (rd_rst_int)
            );
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end

    end
    else begin
        //(* async_reg = "true" *) reg [1:0] a_rst;
        //
        //always @ (posedge clk_i or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        a_rst <= 2'b11;
        //    else 
        //        a_rst <= {a_rst[0],1'b0};            
        //end
        wire   a_rst;

        `IP_MODULE_NAME(efx_resetsync) #(
           .ACTIVE_LOW (0)
        ) efx_resetsync_a_rst (
           .clk   (clk_i),
           .reset (a_rst_i),
           .d_o   (a_rst)
        );

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_rst_i;
            assign rd_rst_int = a_rst_i;
            assign rst_busy   = 1'b0;
        end
        else begin
            assign wr_rst_int = a_rst;
            assign rd_rst_int = a_rst;   
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end
    end 
endgenerate

`IP_MODULE_NAME(efx_fifo_ram) # (
    .FAMILY        (FAMILY),
    .WR_DEPTH      (WR_DEPTH),
    .RD_DEPTH      (RD_DEPTH),
    .WDATA_WIDTH   (WDATA_WIDTH),
    .RDATA_WIDTH   (RDATA_WIDTH),
    .WADDR_WIDTH   (WADDR_WIDTH),
    .RADDR_WIDTH   (RADDR_WIDTH),
    .OUTPUT_REG    (OUTPUT_REG),
    .RAM_MUX_RATIO (RAM_MUX_RATIO),
    .ENDIANESS	    (ENDIANESS),
    .RAM_STYLE     (RAM_STYLE)
) xefx_fifo_ram (
    .wdata (wdata), 
    .waddr (waddr),
    .raddr (raddr), 
    .we    (wr_en_int), 
    .re    (rd_en_int),
    .wclk  (wr_clk_int),
    .rclk  (rd_clk_int),
    .rdata (rdata)
);

`IP_MODULE_NAME(efx_fifo_ctl) # (
    .SYNC_CLK           (SYNC_CLK),
    .SYNC_STAGE         (SYNC_STAGE),
    .MODE               (MODE),
    .WR_DEPTH           (WR_DEPTH),
    .WADDR_WIDTH        (WADDR_WIDTH),
    .RADDR_WIDTH        (RADDR_WIDTH),
    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
    .PIPELINE_REG       (PIPELINE_REG),
    .ALMOST_FLAG        (ALMOST_FLAG),
    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
    .OUTPUT_REG         (OUTPUT_REG),
    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG),
    .OVERFLOW_PROTECT   (OVERFLOW_PROTECT),
    .UNDERFLOW_PROTECT  (UNDERFLOW_PROTECT)
) xefx_fifo_ctl (
    .wr_rst          (wr_rst_int),
    .rd_rst          (rd_rst_int),
    .wclk            (wr_clk_int),
    .rclk            (rd_clk_int),
    .we              (wr_en_i),
    .re              (rd_en_i),
    .wr_full         (full_o),
    .wr_ack          (wr_ack_o),
    .rd_empty        (empty_o),
    .wr_almost_full  (almost_full_o),
    .rd_almost_empty (almost_empty_o),
    .wr_prog_full    (prog_full_o),
    .rd_prog_empty   (prog_empty_o),
    .wr_en_int       (wr_en_int),
    .rd_en_int       (rd_en_int),
    .waddr           (waddr),
    .raddr           (raddr),
    .wr_datacount    (wr_datacount_int),
    .rd_datacount    (rd_datacount_int),
    .rd_vld          (rd_valid_o),
    .wr_overflow     (overflow_o),
    .rd_underflow    (underflow_o)
);

function integer depth2width;
input [31:0] depth;
begin : fnDepth2Width
    if (depth > 1) begin
        depth = depth - 1;
        for (depth2width=0; depth>0; depth2width = depth2width + 1)
            depth = depth>>1;
        end
    else
       depth2width = 0;
end
endfunction 

function integer width2depth;
input [31:0] width;
begin : fnWidth2Depth
    width2depth = width**2;
end
endfunction

function integer rdwidthcompute;
input [31:0] asym_option;
input [31:0] wr_width;
begin : RdWidthCompute
    rdwidthcompute = (asym_option==0)? wr_width/16 :
                     (asym_option==1)? wr_width/8  :
                     (asym_option==2)? wr_width/4  :
                     (asym_option==3)? wr_width/2  :
                     (asym_option==4)? wr_width/1  :
                     (asym_option==5)? wr_width*2  :
                     (asym_option==6)? wr_width*4  :
                     (asym_option==7)? wr_width*8  :
                     (asym_option==8)? wr_width*16 : wr_width/1;
end
endfunction

function integer rddepthcompute;
input [31:0] wr_depth;
input [31:0] wr_width;
input [31:0] rd_width;
begin : RdDepthCompute
    rddepthcompute = (wr_depth * wr_width) / rd_width;
end
endfunction

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ram) #(
    parameter FAMILY        = "TRION",
    parameter WR_DEPTH      = 512,
    parameter RD_DEPTH      = 512,
    parameter WDATA_WIDTH   = 8,
    parameter RDATA_WIDTH   = 8,
    parameter WADDR_WIDTH   = 9,
    parameter RADDR_WIDTH   = 9,
    parameter OUTPUT_REG    = 1,
    parameter RAM_MUX_RATIO = 4,
    parameter ENDIANESS 	 = 0, //0: Big endian (default)   1: Little endian 
    parameter RAM_STYLE     = "block_ram"
) (
    input  wire                     wclk,
    input  wire                     rclk,
    input  wire                     we,
    input  wire                     re,
    input  wire [(WDATA_WIDTH-1):0] wdata,
    input  wire [(WADDR_WIDTH-1):0] waddr,
    input  wire [(RADDR_WIDTH-1):0] raddr,
    output wire [(RDATA_WIDTH-1):0] rdata
);

localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";

(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
reg [RDATA_WIDTH-1:0]    r_rdata_1P;
reg [RDATA_WIDTH-1:0]    r_rdata_2P;

wire                     re_int;

generate
    if (FAMILY == "TRION") begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                end
                r_rdata_2P <= r_rdata_1P;
            end
        end
        
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            if (ENDIANESS == 0) begin 
            	integer i;
            	always @ (posedge wclk) begin
                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                    end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                	end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
        end
        
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
            //integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end 
            end
            else begin //endianess == 1
            	always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end
            end
        end
        if (OUTPUT_REG) begin
            assign re_int = re;
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end
    end
    else begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                    r_rdata_2P <= r_rdata_1P;
                end
            end
        end 
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            //integer i;
            if (ENDIANESS == 0) begin
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
            
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
        end
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
        	//integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
            
            else begin //endianess ==1
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
        end
        // NIC
        //if (MODE == "STANDARD") begin     
        //    if (OUTPUT_REG) begin
        //        reg re_r;
        //        always @ (posedge rclk) begin
        //            re_r <= re;
        //        end
        //        assign re_int = re | re_r;        
        //        assign rdata  = r_rdata_2P;            
        //    end
        //    else begin
        //        assign re_int = re;
        //        assign rdata  = r_rdata_1P;
        //    end
        //end
        //else begin
        //    assign re_int = re;
        //    assign rdata  = r_rdata_1P;
        //end    
        if (OUTPUT_REG) begin
            reg re_r;
            always @ (posedge rclk) begin
                re_r <= re;
            end
            assign re_int = re | re_r;        
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end    
    end
endgenerate

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   gray2bin.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Gray to Binary Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_gray2bin)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] bin_o,
 // input
 input [WIDTH-1:0] gray_i);

//---------------------------------------------------------------------
// Recursive Module
// Description: reduction xor
generate
   if (WIDTH > 1) begin
      wire [1:0] bin_1;
      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
      if (WIDTH == 2) begin
	 assign bin_o = bin_1;
      end
      else begin
	 assign bin_o[WIDTH-1] = bin_1[1];
	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
      end
   end
   else /* if (WIDTH == 1) */
     assign bin_o = gray_i;
endgenerate
   
endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   pipe_reg.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Parallel Pipelining Shift Register
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_datasync) #(
    parameter STAGE = 32,
    parameter WIDTH = 4
) (
 input  wire             clk_i,
 input  wire [WIDTH-1:0] d_i,
 output wire [WIDTH-1:0] d_o
);

(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
integer i;

always @(posedge clk_i) begin
  for (i=STAGE-1; i>0; i = i - 1) begin
    pipe_reg[i] <= pipe_reg[i-1];
  end
  pipe_reg[0] <= d_i;
end
assign d_o = pipe_reg[STAGE-1];
   

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_resetsync) #(
    parameter ASYNC_STAGE = 2,
    parameter ACTIVE_LOW = 1
) (
    input  wire             clk,
    input  wire             reset,
    output wire             d_o
);


generate
   if (ACTIVE_LOW == 1) begin: active_low
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (1),
         .RST_VALUE  (0)
      ) efx_resetsync_active_low (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b1),
         .d_o     (d_o)
      );
   end
   else begin: active_high
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (0),
         .RST_VALUE  (1)
      ) efx_resetsync_active_high (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b0),
         .d_o     (d_o)
      );
   end
endgenerate

endmodule



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_asyncreg) #(
    parameter ASYNC_STAGE = 2,
    parameter WIDTH = 4,
    parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
    parameter RST_VALUE = 0,
    parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance 
) (
    input  wire             clk,
    input  wire             reset_n,
    input  wire [WIDTH-1:0] d_i,
    output wire [WIDTH-1:0] d_o
);










`pragma protect begin_protected
`pragma protect version = 1
`pragma protect author = "author-a" , author_info = "author-a-details"
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V
o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE
El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY
kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc
/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1
uYJaS5tuGEuFInBHa7oO8g==
`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3
fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa
rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq
PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL
DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w
K3OoKmk3zFeArSsql8B4/Q==
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M
GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l
6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI=
`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf
RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk
1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw
Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz
eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0
2HflB1HYKxojQCcZU7qUgQ==
`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx
Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB
rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr
XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD
e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod
B2Zpo2FQ//YDRSAaEa9ksQ==
`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze
vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2
ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2
06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP
fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN
ZoPzFCMjGk5ZmMyIlytNCw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 )
`pragma protect data_block
0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2
Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr
MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI
01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k
egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p
yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU
De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF
GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh
0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r
mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q
z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO
g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H
bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5
60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D
7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ
uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3
aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4
sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV
feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW
aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b
85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk
ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb
szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl
yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok
9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn
GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP
A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR
F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ
YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl
fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI
B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx
MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw
kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa
em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk
YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e
ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE
szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw
jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI
k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t
vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp
GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK
7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC
SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7
Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5
07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/
a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b
LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6
DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA
Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p
C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN
eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w
pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw
Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U
A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx
2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+
tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk
wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6
XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo
LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99
Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1
9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6
/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl
Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS
leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj
niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR
SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD
Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M
p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV
pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe
9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL
T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy
7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM
DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI
8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7
JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD
UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1
g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY
XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0
eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ
PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r
uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/
OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx
X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI
bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe
/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV
Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL
qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/
4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa
XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc
Ei7EaFpheCmlTJyxUg8TdA==
`pragma protect end_protected


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ctl) # (
    parameter SYNC_CLK           = 1,
    parameter SYNC_STAGE         = 2,
    parameter MODE               = "STANDARD",
    parameter WR_DEPTH           = 512,
    parameter WADDR_WIDTH        = 9,
    parameter RADDR_WIDTH        = 9,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter RAM_MUX_RATIO      = 1,
    parameter PIPELINE_REG       = 1,
    parameter ALMOST_FLAG        = 1,
    parameter PROGRAMMABLE_FULL  = "NONE",
    parameter PROG_FULL_ASSERT   = 0,
    parameter PROG_FULL_NEGATE   = 0,
    parameter PROGRAMMABLE_EMPTY = "NONE",
    parameter PROG_EMPTY_ASSERT  = 0,
    parameter PROG_EMPTY_NEGATE  = 0,
    parameter OUTPUT_REG         = 0,
    parameter HANDSHAKE_FLAG     = 1, 
    parameter OVERFLOW_PROTECT   = 0,
    parameter UNDERFLOW_PROTECT  = 0
)(
    input   wire                   wr_rst,
    input   wire                   rd_rst,
    input   wire                   wclk,
    input   wire                   rclk,
    input   wire                   we,
    input   wire                   re,
    output  wire                   wr_full,
    output  reg                    wr_ack,
    output  wire                   wr_almost_full,
    output  wire                   rd_empty,
    output  wire                   rd_almost_empty,
    output  wire                   wr_prog_full,
    output  wire                   rd_prog_empty,
    output  wire                   wr_en_int,
    output  wire                   rd_en_int,
    output  wire [WADDR_WIDTH-1:0] waddr,
    output  wire [RADDR_WIDTH-1:0] raddr,
    output  wire [WADDR_WIDTH:0]   wr_datacount,
    output  wire [RADDR_WIDTH:0]   rd_datacount,
    output  wire                   rd_vld,
    output  reg                    wr_overflow,
    output  reg                    rd_underflow
);

reg  [WADDR_WIDTH:0] waddr_cntr;
reg  [WADDR_WIDTH:0] waddr_cntr_r;
reg  [RADDR_WIDTH:0] raddr_cntr;
reg                  rd_valid;

wire [WADDR_WIDTH:0] waddr_int;
wire [RADDR_WIDTH:0] raddr_int;
wire                 rd_empty_int;
wire [WADDR_WIDTH:0] wr_datacount_int;
wire [RADDR_WIDTH:0] rd_datacount_int;

assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
// NIC
wire [RADDR_WIDTH:0] ram_raddr;
assign raddr     = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0];
//assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
//assign wr_en_int = we & ~wr_full;
assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we;

assign wr_datacount  = wr_datacount_int;
assign rd_datacount  = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int;


generate
    if (MODE == "FWFT") begin    
        // NIC
        //assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
        //assign rd_empty      = rd_empty_fwft;

        assign rd_en_int     = 1'b1;
        //assign rd_empty      = rd_empty_int;
        
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        init_set <= 1'b1;
        //    end
        //    else if (~init_set & rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //    else if (~rd_empty_int) begin
        //        init_set <= 1'b0;            
        //    end
        //    else if (rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //end
        // NIC 
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        rd_empty_fwft <= 1'b1;
        //    end
        //    else if (rd_en_int) begin
        //        rd_empty_fwft <= 1'b0;            
        //    end
        //    else if (re) begin
        //        rd_empty_fwft <= 1'b1;            
        //    end
        //end          
        
        //if (FAMILY == "TRION") begin
        if (OUTPUT_REG) begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid <= 1'b0;
                end
                else begin
                    rd_valid <= ~rd_empty;
                end
            end
            assign rd_vld = rd_valid;                
        end    
        else begin
            assign rd_vld = ~rd_empty;                
        end
        
        assign rd_empty = rd_empty_int;
    end
    else begin
        assign rd_en_int     = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re;
        assign rd_empty      = rd_empty_int;
        
        if (OUTPUT_REG) begin
            reg rd_valid_r;
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid_r <= 'h0;
                    rd_valid   <= 'h0;
                end
                else begin
                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
                end
            end
            assign rd_vld = rd_valid;            
        end
        else begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid  <= 'h0;
                end
                else begin
                    rd_valid <= rd_en_int;
                end
            end
            assign rd_vld = rd_valid;
        end
    end
    
    if (ALMOST_FLAG) begin
        assign wr_almost_full   = wr_datacount >= WR_DEPTH-1;
        assign rd_almost_empty  = rd_datacount <= 'd1;
    end
    else begin
        assign wr_almost_full   = 1'b0;
        assign rd_almost_empty  = 1'b0;        
    end
    
    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end  
    end
    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   

        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end              
    end
    else begin
        assign wr_prog_full  = 1'b0; 
    end
        
    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end
    end
    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end  
    end
    else begin
        assign rd_prog_empty  = 1'b0; 
    end
    
    if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_ack <= 1'b0;
            end
            else begin
                // NIC
                //wr_ack <= wr_en_int & ~wr_overflow;
                wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int;
            end
        end
    end

    if (OVERFLOW_PROTECT) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else if (we && wr_full) begin
                wr_overflow <= 1'b1;
            end
            else begin
                wr_overflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else begin
                wr_overflow <= we && wr_full ? 1'b1 : wr_overflow;
            end
        end
    end

    if (UNDERFLOW_PROTECT) begin     
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else if (re && rd_empty) begin
                rd_underflow <= 1'b1;
            end
            else begin
                rd_underflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else begin
                rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow;
            end
        end
    end
    
    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
    
    if (ASYM_WIDTH_RATIO < 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
    end
    // NIC
    else if (ASYM_WIDTH_RATIO == 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - raddr_int;
        assign rd_datacount_int = waddr_int - raddr_cntr;
    end
    else begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
        // NIC
        //assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr;
    end
endgenerate

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr   <= 'h0;
    end
    else if (wr_en_int) begin
        waddr_cntr   <= waddr_cntr + 1'b1;
    end
end

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr_r  <= 'h0;
    end
    else begin
        waddr_cntr_r  <= waddr_cntr;
    end
end

always @ (posedge rclk or posedge rd_rst) begin
    if (rd_rst) begin
        raddr_cntr   <= 'h0;
    end
    // NIC
    //else if (rd_en_int) begin
    else begin
        //raddr_cntr   <= raddr_cntr + 1'b1;
        //raddr_cntr   <= raddr_cntr + (re & ~rd_empty_int);
        raddr_cntr   <= ram_raddr;
    end
end
// NIC
assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re);


generate
    if (SYNC_CLK) begin : sync_clk
       if (MODE == "FWFT") begin
          assign waddr_int = waddr_cntr_r;
          assign raddr_int        = raddr_cntr;
       end
       else begin
          assign waddr_int        = waddr_cntr;
          assign raddr_int        = raddr_cntr;
       end
    end
    else begin : async_clk
        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
        
        wire [RADDR_WIDTH:0] raddr_cntr_gry;
        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
        wire [WADDR_WIDTH:0] waddr_cntr_gry;
        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;

        if (PIPELINE_REG) begin
            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
        
            assign waddr_int        = waddr_cntr_sync_g2b_r;
            assign raddr_int        = raddr_cntr_sync_g2b_r;
            
            always @ (posedge wclk or posedge wr_rst) begin
                if (wr_rst) begin
                    raddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
                end
            end
            
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    waddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
                end
            end
        end
        else begin
            assign waddr_int        = waddr_cntr_sync_g2b;
            assign raddr_int        = raddr_cntr_sync_g2b;        
        end
      
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                raddr_cntr_gry_r <= 'h0;
            end
            else begin
                raddr_cntr_gry_r <= raddr_cntr_gry;
            end
        end
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_bin2gray    (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync   (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                waddr_cntr_gry_r <= 'h0;
            end
            else begin
                waddr_cntr_gry_r <= waddr_cntr_gry;
            end
        end        
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        

    end
endgenerate
endmodule


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   bin2gray.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Binary to Gray Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_bin2gray)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] gray_o,
 // input
 input [WIDTH-1:0] bin_i
 );

//---------------------------------------------------------------------
// Function :   bit_xor
// Description: reduction xor
function bit_xor (
  input [31:0] nex_bit,
  input [31:0] curr_bit,
  input [WIDTH-1:0] xor_in);
  begin : fn_bit_xor
    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
  end
endfunction

// Convert Binary to Gray, bit by bit
generate 
begin
  genvar bit_idx;
  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
  end
  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
end
endgenerate

endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


module `IP_MODULE_NAME(mii_if) #(
   parameter NO_PREAMBLE = 0
) (
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//MII Interface
input                           mii_txc,
output  reg     [3:0]           mii_txd,
output  reg                     mii_tx_dv,
output  reg                     mii_tx_err,

input                           mii_rxc,
input           [3:0]           mii_rxd,
input                           mii_rx_dv,
input                           mii_rx_err

//Status and  Error Signals
);
// Parameter Define 
//localparam                      SPEED_100M_DIV = (TX_REFCLK == 125) ? 10 : 2;
//localparam                      SPEED_10M_DIV  = SPEED_100M_DIV*10;
//localparam                      SPEED_CLK_DIV = (TX_REFCLK == 125) ? SPEED_100M_DIV/2 + 1 : 0 ;
// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [3:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_dv_pre;
reg                             rx_dv_dl1;
reg     [3:0]                   rxd_pre;
reg     [3:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;
reg     [3:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [3:0]                   gm_tx_d_h;
reg     [7:0]                   gm_tx_d_r;
reg                             gm_tx_en_r;
reg                             gm_tx_err_r;
reg                             preamble_flg;
reg     [1:0]                   cur_st;
reg     [1:0]                   nxt_st;
reg                             add_preamble;


// Wire Define
wire                            add_preamble_w;

assign add_preamble_w = mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err && cur_st == 2'b01 && preamble_flg;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else
      tx_mac_aclk_en <= ~tx_mac_aclk_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_r <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_r <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_en_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_en_r <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_err_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_err_r <= gm_tx_err;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd <= 4'h0;
   else if (gm_tx_en_r == 1'b1) begin
      if (tx_mac_aclk_en == 1'b0)
          txd <= gm_tx_d_r[3:0];
      else
          txd <= gm_tx_d_r[7:4];
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_en <= 1'b0;
   else 
       tx_en <= gm_tx_en_r;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else 
       tx_er <= gm_tx_err_r;
end

always @ (posedge mii_txc or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      mii_tx_dv  <= 1'b0;
      mii_txd    <= 4'h0;
      mii_tx_err <= 1'b0;
   end
   else begin
      mii_tx_dv  <= tx_en;
      mii_txd    <= txd[3:0];
      mii_tx_err <= tx_er;
   end
end
/*----------------------- Rx Region ----------------------------*/
always @ (posedge mii_rxc or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 4'h0;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else if (add_preamble_w && NO_PREAMBLE != 1) begin
      rxd   <= 4'h5;
      rx_dv <= 1'b1;
      rx_er <= rx_er;
   end
   else if (add_preamble && NO_PREAMBLE != 1) begin
      rxd   <= rxd_pre;
      rx_dv <= rx_dv_pre;
      rx_er <= rx_er;
   end
   else begin
      rxd   <= mii_rxd;
      rx_dv <= mii_rx_dv;
      rx_er <= mii_rx_err;
   end
end

assign rx_mac_aclk = mii_rxc;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd_pre <= 4'h0;
      rx_dv_pre <= 1'b0;
   end
   else if (add_preamble_w || add_preamble) begin
      rxd_pre <= mii_rxd;
      rx_dv_pre <= mii_rx_dv;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
    if (rx_reset == 1'b1)
       add_preamble <= 1'b0;
    else if (add_preamble_w)
       add_preamble <= 1'b1;
    else if (!mii_rx_dv)
       add_preamble <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else
      rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      cur_st <= 2'b00;
   end
   else begin
      cur_st <= nxt_st;
   end
end

always @ (*) begin
   case (cur_st)
      2'b00: begin
         if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else
            nxt_st = 2'b00;
      end
      2'b01: begin
         if (mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b10;
         else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else 
            nxt_st = 2'b00;
      end
      2'b10: begin
         if (mii_rx_dv) 
            nxt_st = 2'b10;
         else
            nxt_st = 2'b00;
         end
      default: nxt_st = 2'b00;
   endcase
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      preamble_flg <= 1'b0;
   end
   else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err && cur_st == 2'b01) begin
      preamble_flg <= ~preamble_flg;
   end
   else begin
      preamble_flg <= 1'b0;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rx_dv_dl1 <= 1'b0;
      rxd_dl1   <= 4'h0;
   end
   else begin
      rx_dv_dl1 <= rx_dv;
      rxd_dl1   <= rxd;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else
      gm_rx_dv <= rx_dv_dl1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 1'b0;
   else if (rx_dv == 1'b0)
      rx_odd_data_ptr <= 1'b0;
   else
      rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if ((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
      gm_rx_d <= {rxd[3:0], rxd_dl1[3:0]};
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       gm_rx_err <= 1'b0;
   else begin
      if (rx_er == 1'b1)               gm_rx_err <= 1'b1;
      else if (rx_mac_aclk_en == 1'b1) gm_rx_err <= 1'b0;
   end
end


endmodule



/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii_if)#(
    parameter                       RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                           tx_mac_aclk,
   output  reg                     tx_mac_aclk_en,
   input                           tx_reset,
   output  wire                    rx_mac_aclk,
   output  reg                     rx_mac_aclk_en,
   input                           rx_reset,
   //Configuration Signals
   input           [2:0]           eth_speed,
   input                           rgmii_rxc_edge,//0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   input                           rgmii_txc_dly,//0:rgmii tx clock delay disable; 1:rgmii tx clock delay enable;
   //GMII Interface
   output  reg     [7:0]           gm_rx_d,
   output  reg                     gm_rx_dv,
   output  reg                     gm_rx_err,
   input           [7:0]           gm_tx_d,
   input                           gm_tx_en,
   input                           gm_tx_err,
   //RGMII Interface
   output  wire    [3:0]           rgmii_txd_HI,
   output  wire    [3:0]           rgmii_txd_LO,
   output  wire                    rgmii_tx_ctl_HI,
   output  wire                    rgmii_tx_ctl_LO,
   output  wire                    rgmii_txc_HI,//if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  wire                    rgmii_txc_LO,
   input           [3:0]           rgmii_rxd_HI,
   input           [3:0]           rgmii_rxd_LO,
   input                           rgmii_rx_ctl_HI,
   input                           rgmii_rx_ctl_LO,
   input                           rgmii_rxc
   //Status and  Error Signals
);

// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [7:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg     [1:0]                   txc;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;

// Wire Define
wire                            rx_dv;
wire    [7:0]                   rxd;
wire                            rx_er;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if ((eth_speed == 3'h4) ||
           ((eth_speed == 3'h2) && (aclk_en_cnt == 7'd9)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd99)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[7:4] <= 4'h0;
   else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[7:4] <= gm_tx_d[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[3:0] <= 4'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[3:0] <= gm_tx_d[3:0];
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd6)) ||
            ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd51)))
      txd[3:0] <= txd[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_en <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_er <= gm_tx_err;
end
/*
always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
        3'h4 :
            txc <= 2'b01;
        3'h2 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b00;
            endcase
        3'h1 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
                    txc <= 2'b00;
            endcase
        default :
            txc <= 2'b0;
        endcase
end

*/
reg [1:0]    txc_100m_r;
reg [1:0]    txc_10m_r;

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_100m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
          1'b0 : //rgmii tx clock delay disable.
             if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                txc_100m_r <= 2'b00;
          1'b1 ://rgmii tx clock delay enable.
             if ((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b00;
       endcase
   end
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_10m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
       1'b0 ://rgmii tx clock delay disable.
           if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
               txc_10m_r <= 2'b00;
       1'b1 ://rgmii tx clock delay enable.
           if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
               txc_10m_r <= 2'b00;
       endcase
   end
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
            3'h4 :
                txc <= 2'b01;
            3'h2 :
                txc <= txc_100m_r;
            3'h1 :
                txc <= txc_10m_r;
            default :
                txc <= 2'b0;
        endcase
end

/*----------------------- Rx Region ----------------------------*/
assign rx_mac_aclk = rgmii_rxc;

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_mac_aclk_en <= 1'b0;
    else if(eth_speed[2] == 1'b1)
        rx_mac_aclk_en <= 1'b1;
    else
        rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        begin
            rx_dv_dl1 <= 1'b0;
            rxd_dl1 <= 8'h0;
        end
    else
        begin
            rx_dv_dl1 <= rx_dv;
            rxd_dl1 <= rxd;
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_dv <= 1'b0;
    else
        gm_rx_dv <= rx_dv_dl1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_odd_data_ptr <= 1'b0;
    else if(rx_dv == 1'b0)
        rx_odd_data_ptr <= 1'b0;
    else
        rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_d <= 8'h0;
    else
        begin
            if((eth_speed[2] == 1'b1) && (rx_dv_dl1 == 1'b1))
                gm_rx_d <= rxd_dl1;
            else if((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
                gm_rx_d <= {rxd[3:0],rxd_dl1[3:0]};
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_err <= 1'b0;
    else
        begin
            if(rx_er == 1'b1)
                gm_rx_err <= 1'b1;
            else if(rx_mac_aclk_en == 1'b1)
                gm_rx_err <= 1'b0;
        end
end

/*----------------------- PHY Interface ----------------------------*/
`IP_MODULE_NAME(rgmii) #(
    .RGMII_SYNC_EN                      (RGMII_SYNC_EN                      )
)
u_rgmii
(
//Globle Signals
    .tx_mac_aclk                        (tx_mac_aclk                        ),
    .tx_reset                           (tx_reset                           ),
    .rx_reset                           (rx_reset                           ),
//Configuration Signals
    .eth_speed                          (eth_speed                          ),
    .rgmii_rxc_edge                     (rgmii_rxc_edge                     ),
//Phy Interface
    .txd                                (txd                                ),
    .tx_en                              (tx_en                              ),
    .tx_er                              (tx_er                              ),
    .txc                                (txc                                ),
    .rxd                                (rxd                                ),
    .rx_dv                              (rx_dv                              ),
    .rx_er                              (rx_er                              ),
//RGMII Interface
    .rgmii_txd_HI                       (rgmii_txd_HI                       ),
    .rgmii_txd_LO                       (rgmii_txd_LO                       ),
    .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI                    ),
    .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO                    ),
    .rgmii_txc_HI                       (rgmii_txc_HI                       ),
    .rgmii_txc_LO                       (rgmii_txc_LO                       ),
    .rgmii_rxd_HI                       (rgmii_rxd_HI                       ),
    .rgmii_rxd_LO                       (rgmii_rxd_LO                       ),
    .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI                    ),
    .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO                    ),
    .rgmii_rxc                          (rgmii_rxc                          )
);

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
module `IP_MODULE_NAME(rgmii_sync)
(
//Globle Signals
input                           rgmii_rxc,
input                           rx_reset,
input           [2:0]           eth_speed,
//RGMII Rx Interface Input
input           [3:0]           rgmii_rxd_HI_i,
input           [3:0]           rgmii_rxd_LO_i,
input                           rgmii_rx_ctl_HI_i,
input                           rgmii_rx_ctl_LO_i,
//RGMII Rx Interface Output
output  reg     [3:0]           rgmii_rxd_HI_o,
output  reg     [3:0]           rgmii_rxd_LO_o,
output  reg                     rgmii_rx_ctl_HI_o,
output  reg                     rgmii_rx_ctl_LO_o
);


// Parameter Define 
parameter State_idle     = 2'd0;
parameter State_preamble = 2'd1;
parameter State_data_dl1 = 2'd2;
parameter State_data_dl2 = 2'd3;


// Register Define 
reg     [1:0]                   cur_state;
reg     [1:0]                   next_state;
reg                             preamble_odd;
reg     [3:0]                   rx_d_dl1;
reg                             rx_dv_dl1;
reg     [3:0]                   rx_d_dl2;
reg                             rx_dv_dl2;

// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rx_d_dl1      <= 4'h0;
      rx_dv_dl1     <= 1'b0;
      rx_d_dl2      <= 4'h0;
      rx_dv_dl2     <= 1'b0;
   end
   else begin
      rx_d_dl1      <= rgmii_rxd_LO_i;
      rx_dv_dl1     <= rgmii_rx_ctl_HI_i;
      rx_d_dl2      <= rx_d_dl1;
      rx_dv_dl2     <= rx_dv_dl1;
   end
end

/*----------------------- FSM Region ----------------------------*/
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) cur_state <= State_idle;
	else          cur_state <= next_state;
end

always @ (*) begin
	case (cur_state)
      State_idle :
         if ((rx_dv_dl1 == 1'b1) && (rx_d_dl1 == 4'h5))
             next_state = State_preamble;
         else
             next_state = State_idle;

      State_preamble : 
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b0))
            next_state = State_data_dl1;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
            next_state = State_data_dl2;
         else if (rx_d_dl1 != 4'h5)
            next_state = State_idle;
         else
            next_state = State_preamble;
          
      State_data_dl1 :
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl1;

      State_data_dl2 :
         if (rx_dv_dl2 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl2;

      default :
         next_state = State_idle;
    endcase
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
    if (rx_reset) 
       preamble_odd <= 1'b0;
    else if (cur_state == State_preamble)
       preamble_odd <= ~preamble_odd;
    else
       preamble_odd <= 1'b0;
end

/*----------------------- Sync Output Region ----------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rxd_LO_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_LO_o <= rgmii_rxd_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rxd_LO_o <= 4'h5;
   else if (cur_state == State_data_dl2)
      rgmii_rxd_LO_o <= rx_d_dl2;
   else
      rgmii_rxd_LO_o <= rx_d_dl1;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) 
      rgmii_rxd_HI_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_HI_o <= rgmii_rxd_HI_i;
   else
      rgmii_rxd_HI_o <= 4'h0;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_HI_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_HI_o <= rgmii_rx_ctl_HI_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_HI_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_HI_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_HI_o <= rx_dv_dl1;
end

always @(posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_LO_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_LO_o <= rgmii_rx_ctl_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_LO_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_LO_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_LO_o <= rx_dv_dl1;
end

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii) #(
    parameter                   RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                        tx_mac_aclk,
   input                        tx_reset,
   input                        rx_reset,
   //Configuration Signals
   input           [2:0]        eth_speed,
   input                        rgmii_rxc_edge, //0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   //Phy Interface
   input           [7:0]        txd,
   input                        tx_en,
   input                        tx_er,
   input           [1:0]        txc, //if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  reg     [7:0]        rxd,
   output  reg                  rx_dv,
   output  reg                  rx_er,
   //RGMII Interface
   output  reg     [3:0]        rgmii_txd_HI,
   output  reg     [3:0]        rgmii_txd_LO,
   output  reg                  rgmii_tx_ctl_HI,
   output  reg                  rgmii_tx_ctl_LO,
   output  reg                  rgmii_txc_HI,
   output  reg                  rgmii_txc_LO,
   input           [3:0]        rgmii_rxd_HI,
   input           [3:0]        rgmii_rxd_LO,
   input                        rgmii_rx_ctl_HI,
   input                        rgmii_rx_ctl_LO,
   input                        rgmii_rxc
   //Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [3:0]                   rgmii_rxd_HI_d1;
reg                             rgmii_rx_ctl_HI_d1;
reg     [3:0]                   rgmii_txd_HI_r;
reg     [3:0]                   rgmii_txd_LO_r;
reg                             rgmii_tx_ctl_HI_r;
reg                             rgmii_tx_ctl_LO_r;
reg                             rgmii_txc_HI_r;
reg                             rgmii_txc_LO_r;
// Wire Define
wire                            tx_en_to_ddr;
wire                            rgmii_tx_ctl_int;
wire    [3:0]                   txd_falling;
/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- RGMII Tx Region ----------------------------*/
assign tx_en_to_ddr = (eth_speed[2] == 1'b1) ? tx_en : tx_en && (!tx_er);
assign rgmii_tx_ctl_int = tx_en ^ tx_er;

assign txd_falling = (eth_speed[2] == 1'b1) ? txd[7:4] : txd[3:0];

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI_r    <= 1'b0;
      rgmii_txc_LO_r    <= 1'b0;
      rgmii_tx_ctl_HI_r <= 1'b0;
      rgmii_tx_ctl_LO_r <= 1'b0;
      rgmii_txd_HI_r    <= 4'b0;
      rgmii_txd_LO_r    <= 4'b0;
   end 
   else begin
      rgmii_txc_HI_r    <= txc[0];
      rgmii_txc_LO_r    <= txc[1];     
      rgmii_tx_ctl_HI_r <= tx_en_to_ddr;
      rgmii_tx_ctl_LO_r <= rgmii_tx_ctl_int;
      rgmii_txd_HI_r    <= txd[3:0];
      rgmii_txd_LO_r    <= txd_falling;
   end
end


always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI    <= 1'b0;
      rgmii_txc_LO    <= 1'b0;
      rgmii_tx_ctl_HI <= 1'b0;
      rgmii_tx_ctl_LO <= 1'b0;
      rgmii_txd_HI    <= 4'b0;
      rgmii_txd_LO    <= 4'b0;
   end
   else begin
      rgmii_txc_HI    <= rgmii_txc_HI_r;
      rgmii_txc_LO    <= rgmii_txc_LO_r;
      rgmii_tx_ctl_HI <= rgmii_tx_ctl_HI_r;
      rgmii_tx_ctl_LO <= rgmii_tx_ctl_LO_r;
      rgmii_txd_HI    <= rgmii_txd_HI_r;
      rgmii_txd_LO    <= rgmii_txd_LO_r;
   end
end

/*----------------------- RGMII Rx Region ----------------------------*/
//rgmii_rxd & rgmii_rx_ctl
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rgmii_rxd_HI_d1    <= 4'h0;
      rgmii_rx_ctl_HI_d1 <= 1'b0;
   end 
   else begin
      rgmii_rxd_HI_d1    <= rgmii_rxd_HI;
      rgmii_rx_ctl_HI_d1 <= rgmii_rx_ctl_HI;
   end
end

generate
   if (RGMII_SYNC_EN == 0) begin
      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rxd[7:4] <= rgmii_rxd_LO;
               rxd[3:0] <= rgmii_rxd_HI_d1;
               rx_dv    <= rgmii_rx_ctl_HI_d1;
               rx_er    <= rgmii_rx_ctl_HI_d1^rgmii_rx_ctl_LO;
            end
            else begin//1:DDIO Falling Edge
               rxd[7:4] <= rgmii_rxd_HI;
               rxd[3:0] <= rgmii_rxd_LO;
               rx_dv    <= rgmii_rx_ctl_LO;
               rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI;
            end
        end
        else begin //100M or 10M
           rxd[7:4] <= 4'b0;
           rxd[3:0] <= rgmii_rxd_LO;
           rx_dv    <= rgmii_rx_ctl_LO;
           rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI_d1;
        end
     end
   end
   else begin
      reg  [3:0]  rgmii_rxd_HI_i;
      reg  [3:0]  rgmii_rxd_LO_i;
      reg         rgmii_rx_ctl_HI_i;
      reg         rgmii_rx_ctl_LO_i;
      wire [3:0]  rgmii_rxd_HI_sync;
      wire [3:0]  rgmii_rxd_LO_sync;
      wire        rgmii_rx_ctl_HI_sync;
      wire        rgmii_rx_ctl_LO_sync;

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rgmii_rxd_HI_i    <= 4'h0;
            rgmii_rxd_LO_i    <= 4'h0;
            rgmii_rx_ctl_HI_i <= 1'b0;
            rgmii_rx_ctl_LO_i <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_LO;
               rgmii_rxd_LO_i    <= rgmii_rxd_HI_d1;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI_d1;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
            else begin //1:DDIO Falling Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_HI;
               rgmii_rxd_LO_i    <= rgmii_rxd_LO;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
         end        
         else begin//100M or 10M
            rgmii_rxd_HI_i    <= rgmii_rxd_HI_d1;
            rgmii_rxd_LO_i    <= rgmii_rxd_LO;
            rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_LO;
            rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_HI_d1;
         end
      end

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else begin
            rxd[7:4] <= rgmii_rxd_HI_sync;
            rxd[3:0] <= rgmii_rxd_LO_sync;
            rx_dv    <= rgmii_rx_ctl_HI_sync;
            rx_er    <= rgmii_rx_ctl_HI_sync^rgmii_rx_ctl_LO_sync;
         end
      end
      
      /*----------------------- RGMII Rx Sync Module -----------------------*/
      `IP_MODULE_NAME(rgmii_sync) u_rgmii_sync
      (
      //Globle Signals
          .rgmii_rxc                  (rgmii_rxc                  ),
          .rx_reset                   (rx_reset                   ),
          .eth_speed                  (eth_speed                  ),
      //RGMII Rx Interface Input
          .rgmii_rxd_HI_i             (rgmii_rxd_HI_i             ),
          .rgmii_rxd_LO_i             (rgmii_rxd_LO_i             ),
          .rgmii_rx_ctl_HI_i          (rgmii_rx_ctl_HI_i          ),
          .rgmii_rx_ctl_LO_i          (rgmii_rx_ctl_LO_i          ),
      //RGMII Rx Interface Output
          .rgmii_rxd_HI_o             (rgmii_rxd_HI_sync          ),
          .rgmii_rxd_LO_o             (rgmii_rxd_LO_sync          ),
          .rgmii_rx_ctl_HI_o          (rgmii_rx_ctl_HI_sync       ),
          .rgmii_rx_ctl_LO_o          (rgmii_rx_ctl_LO_sync       )
      );
   end
endgenerate


endmodule


module `IP_MODULE_NAME(rmii_if)
(
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//RGMII Interface
input                           rmii_clk_ref,
output  reg     [1:0]           rmii_txd,
output  reg                     rmii_tx_en,

input           [1:0]           rmii_rxd,
input                           rmii_crs_dv,
input                           rmii_rx_err

//Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [6:0]                   rx_aclk_en_cnt;
reg     [1:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_err_dl1;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg     [6:0]                   rx_odd_data_ptr;
reg     [1:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [7:0]                   gm_tx_d_temp;
reg                             tx_en_temp;
reg     [6:0]                   txbit_cnt;
reg                             rx_dv_compensate;
reg                             rx_err_compensate;
reg                             rx_err_latch;
reg     [7:0]                   rx_d_compensate;
reg     [6:0]                   rx_compensate_cnt;
// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd39)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_temp <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_temp <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en_temp <= 1'b0;
   else if(tx_mac_aclk_en == 1'b1)
      tx_en_temp <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txbit_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (txbit_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (txbit_cnt == 7'd39)))
      txbit_cnt <= 7'd0;
   else if (tx_en_temp == 1'b1)
      txbit_cnt <= txbit_cnt + 1'b1;
   else
      txbit_cnt <= 7'd0; 
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txd <= 2'h0;
   else if (eth_speed == 3'h2) begin
      case(txbit_cnt[1:0])
         2'b00: txd <= gm_tx_d_temp[1:0];
         2'b01: txd <= gm_tx_d_temp[3:2];
         2'b10: txd <= gm_tx_d_temp[5:4];
         2'b11: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case(txbit_cnt[5:0])
         6'd00: txd <= gm_tx_d_temp[1:0];
         6'd10: txd <= gm_tx_d_temp[3:2];
         6'd20: txd <= gm_tx_d_temp[5:4];
         6'd30: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else 
      tx_en <= tx_en_temp;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
       tx_er <= gm_tx_err;
end

always @ (posedge rmii_clk_ref or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      rmii_tx_en <= 1'b0;
      rmii_txd   <= 2'b0;
   end
   else begin
      rmii_tx_en  <= tx_en;
      rmii_txd    <= txd[1:0];
   end
end

/*----------------------- Rx Region ----------------------------*/
always @(posedge rmii_clk_ref or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 2'b00;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else begin
      rxd   <= rmii_rxd;
      rx_dv <= rmii_crs_dv;
      rx_er <= rmii_rx_err;
   end
end

assign rx_mac_aclk = rmii_clk_ref;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_aclk_en_cnt == 7'd39)))
      rx_aclk_en_cnt <= 7'd0;
   else
      rx_aclk_en_cnt <= rx_aclk_en_cnt + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else if (rx_aclk_en_cnt == 7'd0)
      rx_mac_aclk_en <= 1'b1;
   else
      rx_mac_aclk_en <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_odd_data_ptr == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_odd_data_ptr == 7'd39)) || (rx_dv == 1'b0))
      rx_odd_data_ptr <= 7'd0;
   else 
      rx_odd_data_ptr <= rx_odd_data_ptr + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_dl1 <= 1'b0;
   else 
      rx_dv_dl1 <= rx_dv; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_dl1 <= 1'b0;
   else 
       rx_err_dl1 <= rx_er; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rxd_dl1 <= 8'h0;
   else if (eth_speed == 3'h2) begin
      case (rx_odd_data_ptr[1:0])
         2'b00: rxd_dl1[1:0] <= rxd;
         2'b01: rxd_dl1[3:2] <= rxd;
         2'b10: rxd_dl1[5:4] <= rxd;
         2'b11: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case (rx_odd_data_ptr[5:0])
         6'd00: rxd_dl1[1:0] <= rxd;
         6'd10: rxd_dl1[3:2] <= rxd;
         6'd20: rxd_dl1[5:4] <= rxd;
         6'd30: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end
   else;    
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (rx_dv_dl1 == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_compensate_cnt <= rx_compensate_cnt;
   else
      rx_compensate_cnt <= rx_compensate_cnt + 1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_dv_compensate <= 1'b0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_dv_compensate <= 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_latch <= 1'b0;
   else begin
      if (rx_dv & rx_er)                rx_err_latch <= 1'b1;
      else if (rx_odd_data_ptr == 7'd0) rx_err_latch <= 1'b0; 
      else                              rx_err_latch <= rx_err_latch;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_err_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_err_compensate <= 1'b0;
   else if (rx_odd_data_ptr == 7'd0)
      rx_err_compensate <= rx_err_latch;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_d_compensate <= 8'h0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_d_compensate <= rxd_dl1;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_dv <= rx_dv_compensate;
end


always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_d <= rx_d_compensate;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_err <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_err <= rx_err_compensate;
end

endmodule



//pragma protect
//pragma protect begin
`protected

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    *ze3\OR,rs]]'vIW=O3!$u@C6ipQRl^mls#V$DO_'wT,#i1QDCoQH<H,^#Vw-eY>G=/pY?,kw+A[
    s7vr~<GIA3AU*wRsWnCK+@DG'ur5\57/B!;A:ITzA!zI[GXo{KD!sjKR3qyh{,RJB?r~zI=krET@
    pp37'IB=,=uX12]!h[1-B<OGm}Z7=ETCV8/D}sj+CiK}?!a=Qvozk{Urr,i?}QBviG_=^~Y{TL2[
    VI7Yv=X}p_ToW}^r{R\UE=CZ*_E5{VlsO}nQn!me2wf_'@2s5IAkA]-2X=oTp]CjWp?N+QCnJeKD
    ['o,V~<vI2sw]!RnojTJ7GY}45,V#zv>>kU1}sbIIr\v1[?zlrU\KrApXAUUT~uEw,^$8yGwOI{j
    BsCrs2-OURjeH,ejQDl5^@UO_?!H_}:l]WGDHe<[3*V!\*wnopl2V]K3D${o+z\e5Uze'=$Gzz~\
    aU5KU{QV2v^We{s]*e3K]Ak\K-;^,=$\T_,fEXe!]\un~O@3Vlp!1Ea#,HmUODs[#'zJ[$}UUzx-
    GkXG]0kOiRTe2KTCe}Q_sEmje;\~}jQTAvKoiBclu\Yeevs+r{Xlm}QOre]q$lGk[^p/37{G7jI\
    ,'VV_xOHfI,@{sz2Y*K_w@Yw_+7B<^3}UY@=sv+rJVATl[xp*lRRHe<*Et1U7]K\~#9T7EB'\OTv
    OAG3752T}TQpToQ[RT;BVXjQR1JWaY?-7{ZQpI,}wI>ybG1-{Vp-+HU*V=aACs'^o/]R;s[OIkk+
    DBY57OB;*sr^swlzpH_B*Xz#J?ZBIjZ<;Ep6knpB~<5Ul,eT_WHDa\7Q!x~]7O{lL}}wAf5}1lji
    \]/FQJ1H|>=-R1@$vsJX-CA<ps[-Wa=Z?HRiVf^IGK+w{Jla'e5P},zDUB3]{aVGV]Qk5Y{ZTHQ@
    >wUQwn_o@[B3Xw^DB[k]C$2*;Aji!n+[m+KsoB;HIX+E\{B$7ZO^LrCJvMY3vWC]{Y^TV{#{*E*#
    ~T7iTHC5<'3}Q!ss-p[rul^?oGEKXs{<o,Rnm^D>p[kojjjm}jArHH/N-s3Xm}TZ,UXpH,x}CGJo
    M1_AlEez}lC*vHRC#M{RJz~R1r!Xna^_=iCiQuiOWroG^lVma1R[s>+zm#prD@I*?vAVxQQ~s[lJ
    5l=Ee's@J2^_>uX1>!K\<[D5ToXrw<:K$s\3v[ZAGA^B}w{(xk5ZO5JWRz5<1sn}Ae*?K\mY<T*n
    *^zwV$Z2!lXQ&}TBC\OiKmnx@TGasV-O^L[G'?t1C;#vVQn~wEE2HEXavH3sBpXIQR+I<o-;UYJ+
    R#o;C{e^k,5v#7e,|~el2Hron,D,$I<,sU7\oC55r^k7*,Bm25<wezmE+Dmm'l<n=x*KC}VY@CB<
    O>[j<+GU>V5zxpBQ2nTl?p_+zB>HKn*x[x#'A,JTv~>CVE[r;C<e1,DN]5xEema*l\HA?p,\8-}w
    <Yjpmi]?W2}@13+$x}_HWTEAx,=5Cve>#]$V@oEA>xT~snr5<2<^^*@s=Qa~R=!1YE{EBxT\C'Yv
    XZ\[73E=*2G@\gPR*X1~<se~7^e&<jO,zRsp2DJD>]k$z4p^'o^;\jT[Hrxb}Rpa6^km^<V5lIW=
    rl]QJ;$R7O$n2Ol{x,Te^[+A7#A^sd[,#{v][*Hn!Y}I^Hivr\62x]2zAX<OR3_pVpE\^T_s=TnM
    ZaX5ov~Ae@,O$^7Tjka,;]5oTh[wa3zks<_~eC'xprjK$[z'\3'asKxHO-i<XZ>s$;v!@v~x^!V!
    T,|DC5Js_HBp{ZkejO-#}j1j7iT$-2zZe!?qNMEe=^NJTw~ei]*~eoV>{l+m[_^l[O^C!TW=m![;
    El<{U[GvYe}AvDT}'A5<7<~r[1Qb^aa-EBwr^Br1$?WzOEVUxJT'=Eve_7K{m1VCizw}j]$uOj_>
    sVjR\5>Cs11RA=mk#l!'<-YOw-7@9-\#J@R!7T\\5#C,We{a=*!<W,[s{\~U7>aKr=+CInQo+#S2
    >^3EO~mM]@3HWQ=elz;uoZVBym>-+npB;g@GHK\B?O3>WC|O3Ei~5][<GJk11{5J7R#nBZXjX[KR
    On2vI>JjRTRPd$nl\4a=T?]U+IIJGzR<*_vmGu{1~\hT*{kEIV?@$hvm[{?napI'=w$K3nW[WOC$
    ]pQ1{@}!on7i~s>+11@>j$YuXa.v!nGOwDr]5Cv]ZU*!$,3uA$*oB\kYH1*7]^xIQY]f{R}W'{,C
    _BkWZp#]ev=~iU]+Bjxe=VRv_5;?*{_n!GxJ0uvGu]X+x^B;rBaz]Z'o]{rWu2U!Ke?[=ZHO'*pG
    15B[GQzo{xy>7VUvwo@{l2D71>E#$]Tkpn,*vQ$G27ez}$ns;W=^QwG+B,=m,}xwGB>V@o'WQaIV
    iU?ml=wJa;3-B#3\Y3[5}pBiHJ-}2{!]3JksTHanw>Xvck.kwne$>Rppaa?^+5_D_iW7_E~V!O\$
    >OD[aRQF#sQJK=-CMnUj#iHUDKC,O!,UJ[m~xRTz#A\,olHQnIH!aGvHWVs=I4QH]+mUU=R{x'H>
    AU++uj];>{xRU~O\^$+QjDIs<pI7Hn{1rwQ*,>Xoa1#^e^>-VY8zG_C?G^VV}U=|C_=~DEunRrX{
    u]7UBvj_Ii7IuA@!3pYX6C7ekB$^U{Iur*eA}xsXkm5+>o$Ip>V5D3GT^*?Br^[>{n+}av>vJs;X
    nMz2by~zn$?Xl<>n_r$*'XwvU{I@T*JYQu?1~5bl>\Jj$EW+,}21#D!l+EOVmwGpVZVAp_mf<1To
    CkaW^Dw~]U$\HDo@B@Ym$<]7}i<-1AnX}]ieE+lr+p'pCu[rk*r-!]-*#xvRGYK;uxeXX-=na=XC
    p~e[-jsrP^Z!Uu5JTe7,3Z}XCop@@BEn{l,l1H{'!MV{^}H<2a-oi$*k=Esria
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#/YeXKrl_sI!}5{Gea*amOjelTKYE@nTCiE#+BN"uE\ueQz#\xW]Zzp[RZnwuD_-3TM,~A?v
    *Hu:j-ns~{BBY6+1$'Q,AmOoXA31,['>Kj}<YGK$@]CiB2eLG5B{{R]i:c,_~-K7Bp6aC![7H-RN
    s]~Tyq}5$[|X>jEZ5awZ]?p_vil_2uJk5X5=lopk7lp$@DxxvQjvZeJlYa,1a&Xnx+]W]jGRB'B=
    1@,R72=sswnB#r,GU#smBx;R,3F]*+zrUT{<EQpVBU2em=Xa>;x+j_kX+l+yY+ZDJ',,ZwD1GXm[
    peJVrKERs[<jcw5Jo@DXpwEi+ECA@r53xn1}zQX~?{|Xw~~N-T$O},@{3Y\p0q9EG;wj#XJ=V?]m
    a{xCUj$HX<EYjE#a]TV*/;A23=C/C{{>GqW]Zz*{3{aC;uBjQiYXAU^=;~U'C{k-;Jy7CZ#jJ^uj
    v\v>]?\^m5wR@~[g\Y?#RTjuFV1wA[BkUpiZZX[{X*C]O<VVC[Z,ZBEEi~lG[oC@A^OBRA-X2_W!
    rH=>n=xiwbT*8,I\;wY#]1Zu{SSO\iQH$?vsEJEVC~^V*s<B^>\UUGrQ,BvE$;{yQjToBAB?|~l3
    @[=nYfl!7YBCTeNVnCGa5j$GIU5@jxrh}*xY^Gmn!_,>^+T}7I={xTDm{5*H\zz5OnYU1UbKl!Ye
    Bau|wV{o"+IW!eybCI<x#$U,kp!BI$}k5r{7C-AbzY~{w\3CW{$W_1W3SOM];=E51m$;*U^t#C2$
    <si}h*jR[@X}J-w<<,$i=.UY#sIHUkQOQ5WGn_*_?H]@5sjDivg.[n{YlIWw'\Q~aC+u_J_U!a2u
    sxuK<7n[]^D[D_1UlWnRCxA!J$Z1Y1k~IColVxxIR,wA%6iYiHJ<{oGz?YU_[<-RZ@2I1!KXuT}@
    Q$vGGjZ*RJ3vKDqeHXjLHRk;szxjQrQ#_eWuOuWJNCTm\rXREo&<Rnn13ZQ5+ZVj*H['kH7\BV>D
    UpGB@eWz2{Jl,,e#OE-P7Ikr}3m~{>GKZ_wx\_;axr2C|nVlr=2o5+5_,u>n}eK[{1V!2gYjXWVJ
    lKm$uz}7}n{1V=ur3xAY]KRCk{Tr;\{rC>DO5Xr{>l^B[->Uo$}p3{^>]s]5V''sJ]QAHO|5!5Up
    Sf-1]W^@\sKpZCeGv2\oJR2eD>T7xrB{]kG=}Yuj]~m7Y@s[H-bJ7W;iGJXX>pCm>Kv=or}*^Rv<
    [=?P:[-$IXaT{VOV=HjGTsz1m<IC[eEEW*m7Y=XV^~^K_I2>',lRva^uUr-IR6lmOo^CR3Q''k>T
    B;w$}Gn}@Vs]ZYlAlT1allZe+#JQ!]_C]RlcU^A>?nw$fXo;'[x{D~Rs*Q$UK0'}TxI#5z@[<ZQ=
    R\]*EE,k@3H5?YOAm,j#']5BuV$]Knz?CG,[\JvuA'AH\uDs*C{_=Y<xk*G1=kVu7>JODAIJ^u^2
    pa7wjnrUj!Dp!XCkKTk^zJBsEV<}#nf'Tj[kO-YTR<~.,TD\OQO<RmRa-on$v+@lR]C~^!'>x},>
    aTEjV2zV^bj7JH$X;wNG!27Q?DTf-1-O'lDEC]=Xp<DQ*tq$~!;hoAKj/;R!$";Q!#a$G?'xHzw\
    KV\<u='TYzFDGRUCEa,EnWT7>1@Es+r{_j$4TBD{,V=DClGBi_[3u^wpm7Ke:<v>EFUzE_72RWq<
    'D^kBQ$vi,UtkOn#~*Z<_ZouBkm2=o^[NGm{VrZpEYCJxxYY{RiQKRdRYWC,Y;^>E,CwQU5H1azL
    v$}ienuD';]\qR''$lT@VDjQ^Ee?~sO3sIAo@h-HVYmsoI}]CYW{uXE=1$jU*r\Q>o!15uo[-;>j
    <<R;a[=?A_]GWVQYXmKaZ[)]KvnG_Dz
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#kjE^n\#zRK^KjI<ajZ}'ZGE'6KYE@6i$k}@5c"k1mueQz#\xW]Zzp[RZTwuD_lUU;<Q^#?l
    *-u:j-ns~{BBY6+1$'Q,AmOoXA31,['>Kj}[J,_Zx]_7p~=r{z=ZGm}{}uI?B7i+,B<5Dn{EXK;j
    v[7'=Yu}V=sEmUGzei7+R,w[+Zdir#veq5>3=[#YkTYi*q*}onQ[O@av?n-5enI:D[I>I1k+J+ux
    DRACtYGVZJ>J;jKGXJ,RnsIX]VVemL*[Z!lxG;*Bm5'ZEO_@}-}673W\]\Ork1Qs(7G<K<\EkV~Z
    ]C'^T!5A1WT\V]zx7!o^}(mp2[:{T-E(r-U]oY[D$'--<O*#]JrEN;7vBW$}E2IDX*5}7j^?!\I+
    3oJpKX+l-e>_W^?]_.zVjJm[3Tq7o!s=IRKI,GR2[$Bj9m+m>'VwD;l;Y\uT#!Xr3!sujRK3Gu_W
    u7omrAra3DrJ15{RQ{$1?^;,{s}>7mE@CRTBXN_i_DI*IOm=Y<1v^AA$'l]w-XzT*CUn5pNUE{'p
    Wexg)jW>E_D^$^A*T2ez}r5aTBXDw=5~pOnQI=,@5s@Y>NBnX{OKDVoxaYIAY3_^D}~AKIjo}}7m
    T\a}Q[3xD,{IuxCozwp},kU]Y!'CUnGj}iLQ#u!GZ_<#5BHQ{X!A{B[-=TJ}mI_[WK{Up_ju<5JI
    __jC1IYxVh.J^i*v$k'Lme+o_Zn,Z{K;e7JpyDKYvNjl^G#vjD?D*e5z>]p@W';7]u}K1wn-_Kir
    {?p?K_/d_wB^FrGT2WluaE^>kWDBT\Z2[pji#l2[C;Aj#[,=[M6#w5pq^[@#VKp~|Fa7*BxE\-;L
    z-{O7Um<eGwj@zB?rd>_e3}U7X*snl<_osa'uGkCiZ]je>SfX}Zl_po{Op\^'EpkQBjH+,^]eJ5<
    meETtwUQa!lC-;v?pR3Ces'ClE5OYjojw3X*vHeeO$OXKITAOD+G\~{U7$H1{#r;'21-G;5*{E+A
    RYa^z=BaZ{r+ox~V>~'++Exs3z3H{IZzQVw-a/[A{#ut\1EGz2TDl*JDE5ex(,^3VvXa#HLrz}Yh
    |RUrsExX!'*7JQiGp,T3-=B~s1,';T-{C?*r?e#W,AC$T%7vWX,[mmJlB-TaVHOWYRd^+K\\k>'j
    \]nm{O5E{DAa{'u#[VO@,!k:U>E}E,\x>DZRpCO-ED!Y*zH+Rv=p+{3GRTAoApjed*Vp>u7\\m,k
    EpaTQ,>AC2o-el5^5+TEUQ-eJ<=)@_IiCj7(wQ5VW*u!lT[27[[Z12,j@,K\zCBjR}*a,ZEOH^[G
    \v2al>eEGm=YSDaZ1D\p2sl][xB7lsA]^oA}7pmm@AT^~{\=at%fVuB{=YjJUe}ZHQDCO!Y?U]*p
    #r=EWoTHa$A,#l1#5e<sdIznkW[<*_2;-#r7u6}@[#j@lQuD;v@nY*Q@v[8_O?v7nWK
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#kwD>5j#=]@[!K7-j>rTp73E'6KYE@n-fE#+BNY0rr#+[;w?#QIr'eAkUBiwHeZpvzKK=vOp
    PQl#>#Ull!r#~$!RVN^,]Eemp[KwJUz^;}W7;Jz'-XS~U\=P)mNI|Gx}$=3Yz}jiGJ=Q3$<~mreY
    VOiR+KHjp_5_-7*7mo-jul@>KTaRV[mj$]liHD_j!';QR[I?T5R@\+,J1B!X5?s\[\~!;J$E,3+$
    nGwEYUBV}JN*U;#Q]{ZO,eir,-z-wwzT$mH\[Z]R*XY][w-SQBz>CxAnh-aX,s=H]s~]Gl21sl]H
    aIUD1xz\{H-^GlwECrE+K5Y?<!sQjne7WhY3;ubv,ACT*V*xVJpX5uxm\JE^)kE7=V7uRYB}Hw'G
    xO]-m>=p1xvU-nE1\]Cn=a};~~CTQWUu5XR2WeT-$@wE{O?Q>NJV!XlOkQm|mjmA-aZ@5+OYT5Y?
    d!}<{Dv{\BmZ\?rZ3}\27_[IG]#JH7cuDjjpI>~]\ZG-Dr\=z}{\7GGa{DuzO~VR\o=}\=JKl}Y@
    QpQrIr<7$7Uj\z[v+zi;eDBB,2zei<;l]E{fl;Xu<wGITICvq?Eono7O!@eEmOVCV_<[TpmaVKp$
    i}#{s=?I@Js<lBj'oIvej$n+]#IU^kp$uyF]=A,\j~{\n[pB#o}iE+]nvkKQ4UeJ}}Y'i1@j\^i\
    [1Re7Ue<#C-!r7:BOB7mIG=l#;e27?]d=7xR<UAsn{@K?*\ofE.h~oCBAoXYBGAj1@\Iz1E*j_V<
    n<H}yG#-nsi[?5m$k]uR#$qa}lOHEk{wtl7?l6sA<xx}}nv#oD!A_ue5wvBzInKHBlB?[@F~EsKr
    #+ls-^[BERO'R?Jw-@wGk+\lkQ*'[XWyml!nADs!rB,]o!*VWG+lz2;sJIC~kY>~iX;@riZxV}}R
    M8QZ*w7T>#f$WJ@a}[Du5EEuX!o;AJE@+~I4$jxI2Y]VvZmsk7H_]?s,8Vl#RGW-;]GrCQJIlXa[
    IXsV'ge3{C#U$#KsI$ApjEWal[lUK,Vkap>rkuxAlRjoC]HD*]mBp'RoJOp2^kwD!v[!*+^5p$K]
    \JeX+[Vn\??VGjJ5EK*J~kTYX5G}>D3UHBE[$onEH?Ien,IaU@$aDGJ+mI{a--5Z5uG<Qu1}}%;a
    U7#U@j=3AzLn-!K5BQnXrT+k+B\GRvB8V$Te*irOOa[ChD[]==kB\s<Vpz^3~'#z';R[2rr~EVfw
    GsUjCAH#jCjE?*jQm=Jpsn#[-Yl>]_G=!++lBA=\A+]VB_<k}Qz{VG>#'{Qp\sRN,5QO72_?m^_p
    iVHDBR~a6QsI7sjjX3a$1mRTQ}wo*DasVH,$#K-Eu},[[ww]XOe{u/k'l'I]x,Xe!G*~lie~W~Aa
    3~$5*+1_<>eYTpG,E5_EI)nA<3eUeUCaCkEe<3j<<<#x]!@{x*WU~2mjV>'VJ!Y_Jj+sonflX@]a
    U2JuUp}G_2J6UT}]x_2@1'}}kj[W&^V~\FDr}?\;O*"B-'[urU=*.uYTBDOD-+5;[2\\YiQQBOxO
    <?j=!_~'k'DU2[-UEbxBr[59YFev5GWIjC,+^H,31DIK7m!]zRO{-{Rs;p-'$@rWZ+nnB-o<;{+O
    wZ0r}KpTeVTeJH-9+Dp\5Aew3^I)vx$^ET-56{HZH_]]~5kj5[_7^gpo?jzm5n+RU*VYw~YziQhs
    \#^>T2]_J>E3lArw<ux5vRo=!!?={UZ!T*5j*]A^<-BQ<x@-8OEz!V'Ez\X1{B<V(=l\wvk[[~5W
    {}?=;?nj3M-XQVlR/$1}o#Ip=77?as1?u?>=vR+TW
`endprotected
//pragma protect end


//pragma protect
//pragma protect begin
`protected

    MTI!#j)2zBXW_,'#]nWr'21.G@[V$u3?/q=[k[xmViRiz;_bQI'TnH-H$_#T=K[Ge1*1G0Y@[r1p
    @}qC|z3C[EfkQ'Be-e]iXa[zx^QI}VCX$sD72B*NmzaUQevW?rkUP[DYk'H^[D@VKurj=OQ<3\Ij
    iPiB#zCJ*![@WW$v'pi^HBf^Q5[QH,ul,[OdQm[l[b5#+3+jD2Ouop_!VpJs?vQepRVQx}Y*a#l?
    IZ=3ukZs_'uv3jO<ZX'mBIQW],DA+s"X7+Ty!rlOIQ]~kwBzH'KHeUw_RIRv7[xw1mzJ^Ej$~=@a
    [+_5S7aGI}7VY*D[pkX\=@<~]'F<,~E+l?[+&EHBr#wmJ][;H_As,4c\e?3'^r{wT,uAx2-M\I*t
    =wA_u'zmY?<B-OB3DK3r1[UrevprOz[.&wpTYKOxZy}HBkLM]#7,waAJkwzD5&[Bs5II;o{]n<+]
    IGb_N,z,+zP'hGH{@mj=ue0nYkpxYa3N+_+,^O3BszZX\jr*[~_uRQ\*7Ew^@xHV;o1B[-wA{O}?
    mlJ2we><1R3'BmD3yR5jawOm!)~wY5vW~lR@11f4l7]lIi+mP+Gu_@]UWB3rplI3ug3CRUwVCK[*
    2v$?JK*+e[YV>$jQ>@O]%;x={}3YK./1In=G;;Jh-1TJ'@C-$N~oHxmUuOyZ'XwIARpOC'2k{r=]
    {2mDE{k*CE!_5,YEI_UVzDo}2vOz)AGDw__BEb@l>onaIQH+<#ZY]ieQ<<R='prn13QQ#e5Zo!bH
    _EisQKZ$D~I9Ca7nHCXK<p_uAjR5A7m3*^^IQgkX>DvTun[Ee#C#_5[;-j}*#ZH-Gpl3WA7$_wZe
    'Az+]kppx['I[KBs#1IpC^e}u>=KX__'[kE!YunvmD;Ev[XUxv[1i'/E*[,!AD]#-I;LK}i<zRju
    O_e_j-eBB?j?EJX2?7epQ-++TV?$5KnG$_XCwXEG]-W]k{\iW}GJe#pYX}7Tu5DK{}[E3Xr'"x[$
    G~'mXC5pl;X{pGEsv^-H]Ek$wlG2G-Uu7,TwrE7_x15G]Om'-,WaJ/kY!eJD{#nTu2eKwI]sl5OA
    m*punDuE~Zlm<Jl}@<#\QWlCnvIk3@vp<zjGswaO\#b$ZneTDr71x<UAD!ZflwW2vAa1uBwKFy60
    2QWwxjC-OpDJA*jzu-_5WHB30_3j+UT>]OQs@VsZ}=I_ZkvH}eWvDV_$1}CmWwrCVVY-2%fPe3[J
    x*H~jonX?evnWxew~jnk[-}7_T]2@UI=xJjQp5Tu;jE}O3'\?Ci^B&CkK}DT_+_izOJIpW4D[Ho'
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`endprotected
//pragma protect end


module `IP_MODULE_NAME(efx_mac1gbe) #(
   parameter FAMILY = "TRION",
   parameter VERSION = 32'h20,
   parameter RXFIFO_EN = 1,
   parameter RXFIFO_DTH = 2048,
   parameter TXFIFO_EN = 1,
   parameter TXFIFO_DTH = 2048,
   parameter PHY_INTF_MODE = 0,  
   parameter LOOPBACK_EN = 1'b0,
   parameter GMII_DW = PHY_INTF_MODE == 4 ? 16 : 8,
   parameter AXIS_DW = 8,  
   parameter APBIF = 0,
   parameter NO_PREAMBLE = 0,
   parameter INTER_PACKET_GAP = 6'd12,
   parameter MTU_FRAME_LENGTH = 16'd1518,
   parameter MAC_SOURCE_ADDRESS = 48'h0,
   parameter ENABLE_BROADCAST_FILTERING = 1'b1,
   parameter RGMII_RXC_EDGE = 1'b1,
   parameter RGMII_TXC_DLY = 1'b1,
   parameter PKT_CNT_MAX = 256, 
   parameter SIP600 = 0 
) (
   input                  tx_mac_aclk,
   output                 rx_mac_aclk,
   input                  mac_reset,   
   input                  proto_reset, 
   input                  tx_axis_clk,
   input [AXIS_DW-1:0]    tx_axis_mac_tdata,
   input                  tx_axis_mac_tvalid,
   input                  tx_axis_mac_tlast,
   input [AXIS_DW/8-1:0]  tx_axis_mac_tstrb,
   input                  tx_axis_mac_tuser,
   output                 tx_axis_mac_tready,
   input                  rx_axis_clk,
   output [AXIS_DW-1:0]   rx_axis_mac_tdata,
   output                 rx_axis_mac_tvalid,
   output                 rx_axis_mac_tlast,
   output [AXIS_DW/8-1:0] rx_axis_mac_tstrb,
   output                 rx_axis_mac_tuser,
   input                  rx_axis_mac_tready,
   input                  gm_rx_c,
   input  [GMII_DW-1:0]   gm_rx_d,
   input  [GMII_DW/8-1:0] gm_rx_dv,
   input  [GMII_DW/8-1:0] gm_rx_err,
   output                 gm_tx_c,
   output [GMII_DW-1:0]   gm_tx_d,
   output [GMII_DW/8-1:0] gm_tx_en,
   output [GMII_DW/8-1:0] gm_tx_err,
   output [3:0]           rgmii_txd_HI,
   output [3:0]           rgmii_txd_LO,
   output                 rgmii_tx_ctl_HI,
   output                 rgmii_tx_ctl_LO,
   output                 rgmii_txc_HI,
   output                 rgmii_txc_LO,
   input  [3:0]           rgmii_rxd_HI,
   input  [3:0]           rgmii_rxd_LO,
   input                  rgmii_rx_ctl_HI,
   input                  rgmii_rx_ctl_LO,
   input                  rgmii_rxc,
   input                  mii_txc,
   output [3:0]           mii_txd,
   output                 mii_tx_dv,
   output                 mii_tx_err,
   input                  mii_rxc,
   input  [3:0]           mii_rxd,
   input                  mii_rx_dv,
   input                  mii_rx_err,
   input                  rmii_clk_ref,
   output [1:0]           rmii_txd,
   output                 rmii_tx_en,
   input  [1:0]           rmii_rxd,
   input                  rmii_crs_dv,
   input                  rmii_rx_err,
   input  [9:0]           s_paddr,
   input  [31:0]          s_pwdata,
   input                  s_pwrite,
   input                  s_penable,
   input                  s_psel,
   output [31:0]          s_prdata,
   output                 s_pready,
   output                 s_perr,
   input                  s_axi_aclk,    
   input  [9:0]           s_axi_awaddr,  
   input                  s_axi_awvalid, 
   output                 s_axi_awready, 
   input  [31:0]          s_axi_wdata,   
   input                  s_axi_wvalid,  
   output                 s_axi_wready,  
   output [1:0]           s_axi_bresp,   
   output                 s_axi_bvalid,  
   input                  s_axi_bready,  
   input  [9:0]           s_axi_araddr,  
   input                  s_axi_arvalid, 
   output                 s_axi_arready, 
   output [1:0]           s_axi_rresp,   
   output [31:0]          s_axi_rdata,   
   output                 s_axi_rvalid,  
   input                  s_axi_rready,  
`ifdef ONCHIP_PHY
   input  logic           init_clk,
   input  logic           init_rst_n,
   input  logic           PMA_CMN_READY,
   input  logic           PMA_XCVR_PLLCLK_EN_ACK,
   input  logic [3:0]     PMA_XCVR_POWER_STATE_ACK,
   input  logic           PMA_RX_SIGNAL_DETECT,
   output logic           PMA_XCVR_PLLCLK_EN,
   output logic [3:0]     PMA_XCVR_POWER_STATE_REQ,
   output logic           phy_init_done,
`else
   output                 Mdo,   
   output                 MdoEn, 
   input                  Mdi,   
   output                 Mdc,   
`endif
   output [2:0]           eth_speed
);
`ifdef ONCHIP_PHY
//pragma protect
//pragma protect begin
`protected

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`endprotected
//pragma protect end


// Module: efx_pulse_sync
// Description:
//   Safely transfers a single-cycle pulse from a source clock domain to a
//   destination clock domain using a toggle-based synchronization scheme.
//
// ==========================================================================

module `IP_MODULE_NAME(efx_pulse_sync) #(
   parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
   parameter OFF_ASSERTION = 0
) (
   input  src_clk,      // Source clock (e.g., tx_axis_clk)
   input  src_reset,    // Reset for source domain
   input  pulse_in,     // Single-cycle pulse in src_clk domain

   input  dst_clk,      // Destination clock (e.g., tx_clk)
   input  dst_reset,    // Reset for destination domain
   output pulse_out     // Single-cycle pulse in dst_clk domain
);

// Toggle generation in source clock domain
reg toggle_src;

// Synchronizer flops in destination clock domain
wire toggle_sync;
reg  toggle_sync_r;

generate
   if (ACTIVE_LOW == 1) begin
      always @ (posedge src_clk or negedge src_reset) begin
         if (!src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

     `IP_MODULE_NAME(efx_asyncreg) #(
        .WIDTH         (1),
        .OFF_ASSERTION (OFF_ASSERTION)
     ) efx_asyncreg_toggle_src (
        .clk     (dst_clk),
        .reset_n (dst_reset),
        .d_i     (toggle_src),
        .d_o     (toggle_sync)
     );
      
      always @ (posedge dst_clk or negedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
   else begin
      always @ (posedge src_clk or posedge src_reset) begin
         if (src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH         (1),
         .ACTIVE_HIGH   (0),
         .OFF_ASSERTION (OFF_ASSERTION)
      ) efx_asyncreg_toggle_src (
         .clk     (dst_clk),
         .reset_n (dst_reset),
         .d_i     (toggle_src),
         .d_o     (toggle_sync)
      );
      
      always @ (posedge dst_clk or posedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
endgenerate

// Generate one-cycle pulse in destination domain
assign pulse_out = toggle_sync ^ toggle_sync_r;

endmodule



module `IP_MODULE_NAME(efx_data_pipeline)  #(
    parameter HBP = 1,
    parameter DATA_WIDTH = 256,
    parameter MUX_IN = 1
)(
  input               upstream_valid_i,
  output              upstream_ready_o,
  input      [DATA_WIDTH-1:0]   upstream_data_i,
  output              downstream_valid_o,
  input               downstream_ready_i,
  output     [DATA_WIDTH-1:0]   downstream_data_o,
  input               clk,
  input               resetn
);
//pragma protect
//pragma protect begin
`protected

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`endprotected
//pragma protect end

`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME
