module verilog6502_external_memory (
    input           i_clk,
    input           i_rst,

    input  logic [15:0]     i_addr,
    input  logic [7:0]      i_data,
    output logic [7:0]      o_data,
    input  logic            i_rd,
    input  logic            i_we,
    output logic            o_rdy,

    input  logic [31:0]     i_axi_base_addr,


    taxi_axil_if.wr_mst     m_axil_wr,
    taxi_axil_if.rd_mst     m_axil_rd
);

taxi_apb_if internal_apb();
taxi_apb_if addr_shift_apb();

verilog6502_apb_adapter u_internal_apb_adapter (
    .i_clk      (i_clk),
    .i_rst      (i_rst),

    .i_addr     (i_addr),
    .i_data     (i_data),
    .o_data     (o_data),
    .i_rd       (i_rd),
    .i_we       (i_we),
    .o_rdy      (o_rdy),

    .m_apb      (internal_apb)
);

assign addr_shift_apb.paddr     = {i_axi_base_addr[31:12], {internal_apb.paddr[11:0]}};
assign addr_shift_apb.pprot     = internal_apb.pprot;
assign addr_shift_apb.psel      = internal_apb.psel;
assign addr_shift_apb.penable   = internal_apb.penable;
assign addr_shift_apb.pwrite    = internal_apb.pwrite;
assign addr_shift_apb.pwdata    = internal_apb.pwdata;
assign addr_shift_apb.pstrb     = internal_apb.pstrb;
assign internal_apb.pready      = addr_shift_apb.pready;
assign internal_apb.prdata      = addr_shift_apb.prdata;
assign internal_apb.pslverr     = addr_shift_apb.pslverr;
assign addr_shift_apb.pauser    = '0;
assign addr_shift_apb.pwuser    = '0;
assign internal_apb.pruser      = '0;
assign internal_apb.pbuser      = '0;

taxi_apb_axil_adapter u_apb_axil_adapter (
    .clk        (i_clk),
    .rst        (i_rst),

    .s_apb      (addr_shift_apb),

    .m_axil_wr  (m_axil_wr),
    .m_axil_rd  (m_axil_rd)
);

endmodule