// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.288.2.10
// IP Version: 7.1
// =============================================================================

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//                                                                       
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//                                                                       
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.                                                
//
////////////////////////////////////////////////////////////////////////////////

`define IP_UUID _4c19f37180ff465ca20760e199a0613f
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module gTSE
(
    input mac_reset,
    input proto_reset,
    output rx_mac_aclk,
    input tx_mac_aclk,
    output [2:0] eth_speed,
    input rx_axis_clk,
    output rx_axis_mac_tuser,
    output rx_axis_mac_tlast,
    output rx_axis_mac_tvalid,
    input rx_axis_mac_tready,
    input tx_axis_clk,
    input tx_axis_mac_tvalid,
    input tx_axis_mac_tlast,
    input tx_axis_mac_tuser,
    output tx_axis_mac_tready,
    output [3:0] rgmii_txd_HI,
    output [3:0] rgmii_txd_LO,
    output rgmii_tx_ctl_HI,
    output rgmii_tx_ctl_LO,
    output rgmii_txc_HI,
    output rgmii_txc_LO,
    input [3:0] rgmii_rxd_HI,
    input [3:0] rgmii_rxd_LO,
    input rgmii_rx_ctl_HI,
    input rgmii_rx_ctl_LO,
    input rgmii_rxc,
    input s_axi_aclk,
    output [7:0] rx_axis_mac_tdata,
    input [7:0] tx_axis_mac_tdata,
    input [0:0] tx_axis_mac_tstrb,
    output [0:0] rx_axis_mac_tstrb,
    output MdoEn,
    output Mdo,
    input Mdi,
    output Mdc,
    input [9:0] s_axi_araddr,
    output s_axi_arready,
    input s_axi_arvalid,
    input [9:0] s_axi_awaddr,
    output s_axi_awready,
    input s_axi_awvalid,
    input s_axi_bready,
    output [1:0] s_axi_bresp,
    output s_axi_bvalid,
    output [31:0] s_axi_rdata,
    input s_axi_rready,
    output [1:0] s_axi_rresp,
    output s_axi_rvalid,
    input [31:0] s_axi_wdata,
    output s_axi_wready,
    input s_axi_wvalid
);
`IP_MODULE_NAME(efx_mac1gbe)
#(
    .VERSION (16),
    .TXFIFO_EN (1'b1),
    .RXFIFO_EN (1'b1),
    .TXFIFO_DTH (4096),
    .RXFIFO_DTH (4096),
    .PHY_INTF_MODE (0),
    .AXIS_DW (8),
    .RGMII_RXC_EDGE (1'b1),
    .RGMII_TXC_DLY (1'b1),
    .INTER_PACKET_GAP (6'd12),
    .MTU_FRAME_LENGTH (16'd1518),
    .MAC_SOURCE_ADDRESS (48'd0),
    .ENABLE_BROADCAST_FILTERING (1'b1),
    .LOOPBACK_EN (1'b1),
    .APBIF (1'b0),
    .FAMILY ("TITANIUM")
)
u_efx_mac1gbe
(
    .mac_reset ( mac_reset ),
    .proto_reset ( proto_reset ),
    .rx_mac_aclk ( rx_mac_aclk ),
    .tx_mac_aclk ( tx_mac_aclk ),
    .eth_speed ( eth_speed ),
    .rx_axis_clk ( rx_axis_clk ),
    .rx_axis_mac_tuser ( rx_axis_mac_tuser ),
    .rx_axis_mac_tlast ( rx_axis_mac_tlast ),
    .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ),
    .rx_axis_mac_tready ( rx_axis_mac_tready ),
    .tx_axis_clk ( tx_axis_clk ),
    .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ),
    .tx_axis_mac_tlast ( tx_axis_mac_tlast ),
    .tx_axis_mac_tuser ( tx_axis_mac_tuser ),
    .tx_axis_mac_tready ( tx_axis_mac_tready ),
    .rgmii_txd_HI ( rgmii_txd_HI ),
    .rgmii_txd_LO ( rgmii_txd_LO ),
    .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
    .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
    .rgmii_txc_HI ( rgmii_txc_HI ),
    .rgmii_txc_LO ( rgmii_txc_LO ),
    .rgmii_rxd_HI ( rgmii_rxd_HI ),
    .rgmii_rxd_LO ( rgmii_rxd_LO ),
    .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
    .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
    .rgmii_rxc ( rgmii_rxc ),
    .s_axi_aclk ( s_axi_aclk ),
    .rx_axis_mac_tdata ( rx_axis_mac_tdata ),
    .tx_axis_mac_tdata ( tx_axis_mac_tdata ),
    .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ),
    .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ),
    .MdoEn ( MdoEn ),
    .Mdo ( Mdo ),
    .Mdi ( Mdi ),
    .Mdc ( Mdc ),
    .s_axi_araddr ( s_axi_araddr ),
    .s_axi_arready ( s_axi_arready ),
    .s_axi_arvalid ( s_axi_arvalid ),
    .s_axi_awaddr ( s_axi_awaddr ),
    .s_axi_awready ( s_axi_awready ),
    .s_axi_awvalid ( s_axi_awvalid ),
    .s_axi_bready ( s_axi_bready ),
    .s_axi_bresp ( s_axi_bresp ),
    .s_axi_bvalid ( s_axi_bvalid ),
    .s_axi_rdata ( s_axi_rdata ),
    .s_axi_rready ( s_axi_rready ),
    .s_axi_rresp ( s_axi_rresp ),
    .s_axi_rvalid ( s_axi_rvalid ),
    .s_axi_wdata ( s_axi_wdata ),
    .s_axi_wready ( s_axi_wready ),
    .s_axi_wvalid ( s_axi_wvalid )
);
endmodule

//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
AnxLCEXIwWGNUbKODuvDDj9z3+IsvyasQalysUi/itDT2wwInQ3bBdLVigviyZBs
KfNqHVcHh1PkyYw6Tc63TbVvrM0JlKHeRk9d4Ni755Frdl+e0Yeh82+Cu7JAI77V
toSbtXAPtD6vOVPzzed5ozvhLM0NSdRFehAG9pksl3iYjKFZP6TayMWce09NBstN
j+KnL6lB7cNlu0ejMJXS7VgJ8dx8NGBDtFHQEZ5XfZo3IKXu2RTPmQkW3pU8QhlH
F8qGcX2EikZvcV+7xxJnVc8CjsdqEa+f2tIVEtB7gpGdCQYhsfE4ScprrVpuFhH+
2Rn6AkA5iTdD385b26iafw==
//pragma protect end_key_block
//pragma protect digest_block
45gGFciNrCTJZXxwMOIqQD36VKE=
//pragma protect end_digest_block
//pragma protect data_block
/fAtlRv3M2ytzKM0VXXGACIycHPm8M1coZKa23W5ckG5VSaPQWRKFrb6mgu8TO0l
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//pragma protect end_data_block
//pragma protect digest_block
ccHJ1CIvmCRS+nbWgLQWKS78CiY=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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TdTlABcW1iLl/z9STeHQ+Q==
//pragma protect end_key_block
//pragma protect digest_block
n10L4UZBiziO4pZGJcyPwOagmTY=
//pragma protect end_digest_block
//pragma protect data_block
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//pragma protect end_data_block
//pragma protect digest_block
6Z3kBITlGBQ1queo/RSCimERKpE=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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mJ1+NJbHvwYN0VTqmYim+w==
//pragma protect end_key_block
//pragma protect digest_block
Hr63lrg3B3IJZh8a3CEdfiqq8kk=
//pragma protect end_digest_block
//pragma protect data_block
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//pragma protect end_data_block
//pragma protect digest_block
NoNN/+HOL/6XnNdLy3d9uw2O3HQ=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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afEEkSjZUwZJ8Gim6nx7fA==
//pragma protect end_key_block
//pragma protect digest_block
ANmuh8+Z/fi0NpDa8f8OOgJt3vE=
//pragma protect end_digest_block
//pragma protect data_block
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eZe/gvQQJsNIVq0A5fQoOWXoRXmKYtBSfd9VlXxbImc+Mm6OAHDk2LsYG0qNJ6hp
hPM/c2+wML7iK0uLJX6T28Gyw4dvKYEJT2pJn/RlVlggOV4vcO4VDaRLu2VPO6DY
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pGAxleOWkKh3F1p5lB5/oRievr0g3KiIskFHL2CxJvG2olL3OBmeL4x/QxELGj8N
m+1cKH3PsPsIbCPjDFFVLC6dEYQQ4bnY24/o5IBwxJDUm+gaiMRVX+JaSE54DqM4
VkEMQ8d+RTEcVlORJOYYRs7bNdH6s4bIz3rtH9cZHHRIBQAQzhe5nTtWWMr01dXw
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WbWpkOf8uqehUOTyZ5jnccJItbhFwhV2SnbVK5RMEn0=
//pragma protect end_data_block
//pragma protect digest_block
d1Onj9prOJmn4JcwcCCC8cvvcYw=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
AsnvdlQQG2G/k9b5qztkkW7Dv+FAZiPWR6QAUQ+DxyO86/iCpkBlRR6oSVI7Og+p
9CtGpeXkbt4RrFe90nWZGjqvKgB7RxmhXppMUa7bi5yTGg6r1eOI3gAVzAd0YjMy
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5eBEKR7/xyx/F+evqlp6SnUvcfFe0SuOopPUCAACMa/w2N6o2t6qUgzpnKjvfpyy
aL6wquWnMYxt1ZWghTs3ESImUnkDXkLHeOrJnpqOt4oal8yNil8aDRGPYogUCq9v
nwUaPfDpVSeVWP85S9g4tg==
//pragma protect end_key_block
//pragma protect digest_block
I+eFsI6owEDO8y+cCD4HefhLDZ4=
//pragma protect end_digest_block
//pragma protect data_block
YBr4Lz06/z/y6NMgOg+/Z4NSGk3d2hW5fBB2iuvreGqU+603ueDP6H/nW0GnOhQI
Xj/eGmbuXNLoAWPJ9TZFRHWxyqmOcc7QA1t7hn1cZc5pYVhlSK1YHkPzrzHjyBzw
4Qs3YLoyQf9hdSiKrEunzJrGyuX29UNzxDbEPrmSqs5p3HAkH4T+wKGx7HG89fUZ
RWK7+EVNWOdrjJB8czqOHNBUNWBPHfBC/PvM7GNNXQtV881N4wWJp4sxBdn++mgj
Iq4nQrC1ruOlYmYCAUgLyQrnyfwkcKXJ/UuX4Kf1y4xoq9dVINO/wU0cikRwvFrM
Mo7eNVLcm69LHFs4o580/Jcqdq43eNROGXm0exZGg4cq2sl3yf7ZVQ6i7x7v4Qfc
lzUZ8lRPr82Y/lXgLqBl9RGT4ClceSJ1b8NWmASpE+/erXTdU0kQYy8QDLCqa7OQ
cgnFXLpZfYu/vbOEbtOA6EYmhJim7zj6jxBVjDL++ci43I0oJys696sf4VIReENQ
g4xIg3yXN/+a8uoAqLi7EvjqzC373Jea2zOwBfmxzbQ8QsXD2uymeTcaNWTvkQiv
vmeof/DqISbjoj9RqraMVt/7Nn800xgtQlfS847/ToSA6IFE5dwAWUNTpG4lXjz8
FneCJduvQRHYTpyDgltyDQ7YFShoCt7u2p9AAPAzJTvfn24FThPFJLaNMp9bxJMx
/Dj6ZzxyBEKDWIR5iLTdVLvSyyqVeZxqeHL9Zcwc+Qpw9rCRyavlHBwKPsXeiq/n
Mqz9zyuR1kHvRA+WdESlZF+P4nQUaVPmR4r/Odu8NJXiD6eAWbcbqKXHca/1hyIK
T4oRI3G0iUZBKG5gMkjhLAuArxSYxOcwYTzeob9IArQrWtgqYmdZltSttLO87Mhf
6B118ZnS9ybnoUELJwhufoYKWmNwA7SfVBL74y86t4+tEDKRJDRURM3yfzlhwGVt
N6RKsIMAvX0MHrIGez3Ob/e6LS5RDxXvxMOOyXk7zVhzOQLqOBKjcoKsUWqV+si7
fiyZq2GyzAKSvfhEbiHxHgZaDOJTN7a6xhXzy/ZFcN+tjkE5GtVOKuU1avyqvj1+
Ijb5FeAhLJujDtBTCjqrE4plAtSjND/5tyAibv/SNclMHAxVlyVzsn+UDhTn6CO5
V6a+cJSiJarGUf8dOexjId8GB6LJNWg9JHD+ltpPqggwtEgxYXizJcOuNr2LIPy/
DdSYDCMJHGceEXX45h4XI0Lx9v1M/DplJA9WcIitE8WRuSg7e0Z8J2peCaJV+05R
nrN52K8FSbHlCq25kYzKzkibydmKO7qmiqI31SB+42lr6NlqoWwUmLf21CHtpQkb
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Jln3muh6n766T6bMjhuhm7QBJeFlziBT4B8zvPSS7ms=
//pragma protect end_data_block
//pragma protect digest_block
D7e/03/mF2BL9YuHkWwHU2Ux1m4=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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iiVHouTBWJlaPEyX51xzQA==
//pragma protect end_key_block
//pragma protect digest_block
pWD285A16E48GpWKY9w7PswvVQg=
//pragma protect end_digest_block
//pragma protect data_block
tbC5phADw5ibrgILsA6yzkwnDfSWH7zOwDaZ6EJLfQPfvj6SJKAsCZsnB8f+/eYy
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RgU45UCjhWK/9Zo3CeoXJjHyG0/5SufH155/hmltrpf/eInxz0oQ1ghwwgrvjTqZ
5as7CqOk+T6BTdOiBn3NzcQQHF/TuhOXs1b9OdVUritY6nA56Dh5UuG90Nc65Gef
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qmlooCBVplz3ZwCY6gTzGRNKu07UtAClI6P7Dm6Ctdk9G4AfJP05aAx4va1C2jVv
ua+Klymxl/Mws++p7tsE5wNBLg8/9hKw+SVprSFgwHLR5wKwjVVm3A+QyfsOEwDr
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QLvSKkbMbxPjq5/TDNvSAAfrxnSMwcQTyX7MJeJvRUQ=
//pragma protect end_data_block
//pragma protect digest_block
q8FQ8IPkH9SC749Sk1McZpJf12E=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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DMiMRT9V4xdB/+OwhRUdvnDdS8ZdNEzgQ16Gp2C+bb8C8fxGtMhNxkoUVWf587Kn
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QVYOONJeCKkvOy9Jgs+EaQ==
//pragma protect end_key_block
//pragma protect digest_block
8qSCHJneLBb6XVLZi9bJi6+NcUw=
//pragma protect end_digest_block
//pragma protect data_block
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dBsLSIqz3Xj5h4+aAzn60yoeeTXLFw5cpcYHXeOjazyGPRwBFvMXntIwwgyZtUf2
TgtGZUKJicZOcgx+INVrAWh7UykCu8GgEhP3gHz2FFWDaykgozYa+BdWlHYVZRnd
u4HttmarkcM1hDmIrDkN0xeI0R3B3cOYK93O+SfFZRjgPgWSgfe0Dniw4rFvSb/6
xfLwV2p8Tb6WjH43i5+zp5RLfqwh4GhPqUKiWdj/NRP+2jZI6DfnXdKpUtPqCD4Y
ie+t/1dmyPeAnHThwKsqhOjxXY3ektJOkC8tEfQQ+xQGqS6V2Yw98zDIGCBqR5tm
ykkfpn2EOiqZAF21pDpQNWKAbKFV4COTE244UTVwVRP8PvLm7MigAvstvPfogjle
pgwyeO54yhhf/t+I+dh7Ol2PbPIIKq6queTfDFK7iFP94L12lgHAdUAl+HE5fzlP
wFK0iM7gVC5Rpg4rP+y0e9vCX5DU3W7w5J0QRMnwnWPg+KQ8YczK3/W/spBaHZOB
kN4ZVGB0LvCTPyaJzGr5LoFnA+cYlUsazBidM8Xy3/br/sI2BprOeT0Bbq0pgZ+7
ZozDzNd7LZtVNGBHU0z30YjaArVNIbrxjGvrM1rMBiXMKMkBKnAK6OPDz/Cv81Bu
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A3wgJSwc1/R7mArGuO4d6V4WyrVjy1ay3Dn587sRxBoIEyYfQtbvw4Hp57EGMTmB
z3Wedc32RaQ/gYdi8W5ALb7e3ZugnCImvKAO9Zys41rR80jfZgDibRRE7R7eWBpx
Dca/tfPT/nm0kmLMrr+QLFj6NG+W46M/9s+RUPVjXmRQWYWn3DoL/urWcc4dA5ED
ZSW7QYb19DJ6uG9QHoeMzbPTheO3qpk3upfbp54jnvKXkTiEN8i2NN6WpJcByXVT
eYWrCmNsPKij4RylgCrk9+TnrF+SmUV1Qdg4qRveSj3oRXo9hVjlyJWbHhwdDhWh
aEdl+0aCT2cjFTiR8yeqW+vuoKioYN9qh8TLLuAdGLgmZtq9WxsyGkPKOtspDUMq
EWydQ0p+4RzUAulPvbwIKb0sGggpPGngkt6TyLp83Cs516Y40mH6DSaTl71MfUPN
6hVNGmJHFYj3tTvj0TQ5Yn6LDKZIFMYthZGHop+ROh+IEXUubzHm7a3cDCtqkTyE
b03LsJC6CbMnKI4XGecMXYfQw9IYR+L/5ks46VSRiptymUrTtRogrHb4JM3vMykV
eiowloo3C+iXYPHohrH0mtLiiPc6R58vOFVfL8nYoib2JO6D8+6Xy2g7xxq3mJAV
yqdbRTu0VObw/j4oDm3QhDtedNtGn5zFi6EsNsnD8Mo610kERxQ5JWUQ9pFn+Q8C
z25QzeOUO0xcG5p73pWvx/iYAmLe1udtKsweXltd/jqfrnxSd82xNUv+VYdzwn84
OelM0vLrTklkXPc4+OoI/t0vlN9HTKz71v9vN46rliiLEjWEK4q1O2f4rlqbyB5j
y2+8e26HbD3xg3kmwDYHKnBdp6BHGoal9KnDxzTz/eu9LNHlwf5zjck8iA3+97jz
HHwOnEGLRkzAUM3vr5Rh9YHCl4LPYSLVC1p3wLPAjbS6kIN2SxaHQmW2+qkCyeBK
ayJOmojJZvd2ytxxil979lOGyGnqssMnSOVD5y/xarNrTxcWneOD5zLaidEWVIeN
hcQwoNqbl9ou6rUMlFYsbbC1Sodw7eSpKhoIcISyqvzudaCOPOvydwvaKECE2AO8
kcNmqRNarkBd6EztjGGGjpo/VKwuSjjKmTTVG6UosMIu98rT8GMpN0XPDQLZcGUM
SZhPY7MvdYR+5IytmxaxPpwNtw2pXjPzyu+txd6Hc3qgeJJi+7qWWOwTGPbxgu2j
5gKuah3rKsqgRqDyspNjnaf4Jur338xZJSy4ei+FfF4Bzn4NEO1x/+SarhFS+Qi8
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DBDftqQtX/oHWfAmeZhmRBuj7LdF4fVNcnOSlb9RYYo=
//pragma protect end_data_block
//pragma protect digest_block
fISjrQLVTMznoejKTXLxneEH1rM=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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ScpwP3go0xQ69IrJdZ9wx9Z2Qb+mbafejlACthfrI/qHqz0+KfF7JU3xnktro9EK
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wWwZ5PjU8hN3vfbePgjZkA==
//pragma protect end_key_block
//pragma protect digest_block
TtmbDmxdMg1zJG/PERb8Ra+Pms8=
//pragma protect end_digest_block
//pragma protect data_block
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sk7FazVQEW2aJovwsGYvxEvifNXdLZOPIwTWeMMVRoewTnOmfFGup2RRdifqo3BF
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GwJl8wljjwbCdNHrAvQTerZYmjlLuDND3uaU8xqbqKBT0zkWlx7zMApJYisgL9a5
gvr3wqZj7IbSdZL49oLWQtawz6y9+vPchronN9xhEhgf6oo4N9CXE00eylTzdqFW
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DQR66hnhj5sr3fniKtsFFcXsW/wQ0McEfMPzmbaayvk869DgAGM/HhqN1lCpUdkz
//pragma protect end_data_block
//pragma protect digest_block
Dp33pnOzrjzNeFbe/SSVyHl2kAc=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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46L2gqFzbwedeQRHmEcDRA==
//pragma protect end_key_block
//pragma protect digest_block
XyTDHV4JZRt+wfV76/WwR7YhVcs=
//pragma protect end_digest_block
//pragma protect data_block
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bOo6QvArwAMunxkgWO64uM2mqoL5+2qqWIoX/kOIKSyhESp+emu738SYtaszE9av
//pragma protect end_data_block
//pragma protect digest_block
nWrq3EPDMtEXfKvYGGpSQArDy4k=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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g/VBlSVclqWtZDmfhCtSKb81AWK8TVGSJG8BSZvZv/QruxskN8UKeHq3mNnFNA0i
BAQDMmBq+wwHTXv4864ICQ==
//pragma protect end_key_block
//pragma protect digest_block
9CbqG9Bv4IqyciYIBinQCrA58GE=
//pragma protect end_digest_block
//pragma protect data_block
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//pragma protect end_data_block
//pragma protect digest_block
U9YB8/0V+ciChAhgBpR+Mjh1AqA=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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l9LZHRSmPOz3WQkMiwp+vA==
//pragma protect end_key_block
//pragma protect digest_block
LMsSFqJZAXHDtTSKQpoQfkCpEXM=
//pragma protect end_digest_block
//pragma protect data_block
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OkHBXHcbwZOdVzodwlrE+Z+E6nQLMf7ULJbNgjg/aL4rciCc2UJMcT60fpeXn/5j
w+aH/Yw2PEclqFqUOUZkT5aqB+8CwP/H8XPB17tlJq6nfVYr/uybp67MXIMHwdk8
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If+ihIXjoDu1KLHVsP9gdAfsnzihTP7tD2I8gYjb+HYo8BxEQJyOtA1j73lkMq3p
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//pragma protect end_data_block
//pragma protect digest_block
Yac1UeXsmBvviCciB/hrnaEqr10=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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2epty4jyyW9j/bg7csrOfA==
//pragma protect end_key_block
//pragma protect digest_block
Y5+OOUWvj9rO8MVfeQiy9t9WFcg=
//pragma protect end_digest_block
//pragma protect data_block
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//pragma protect end_data_block
//pragma protect digest_block
B3TkFI+3N0Wc2L+4rgj86RNP7kM=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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nxFVy3bqck4R+XXscCf5qQ==
//pragma protect end_key_block
//pragma protect digest_block
qtP42qWnCaGHeHrx5eafulg95k4=
//pragma protect end_digest_block
//pragma protect data_block
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//pragma protect end_data_block
//pragma protect digest_block
6N9u26hVMpcbyyfmRwuCf6Az/lU=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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eLKSDiJKdiLlAm3AiIYAxg==
//pragma protect end_key_block
//pragma protect digest_block
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//pragma protect end_digest_block
//pragma protect data_block
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knQYNzLuo/0bvSCkEVcmFb8ZOGNyNhMNm5QrNt1OEBA=
//pragma protect end_data_block
//pragma protect digest_block
oVKojFyDpw5GaFjaBy/xgPtTTkw=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
ALEP0YMKgY2hG6kMs04J3ytNSCr7F/iMNJKtSVcQNf2nURIh8tgmUuQpfKedON+G
spusQvansFOzVgoi8JYjVQQzMHgqtriLVUNC6Goo7dbuaEy3NYy5IyBYJ5iwOYdL
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Yi0+qmto+QZkkuAI0Lul2JJkTYGpQ6a3MMsia70DpLOnt4TBdRCMwsdmtCG4sLmS
MXuDTBs8Hpzg7J0glGHLRA==
//pragma protect end_key_block
//pragma protect digest_block
H0bopUu32ivTFDA3K9T8J8SS43U=
//pragma protect end_digest_block
//pragma protect data_block
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mWeiKaLpTPGDMCLExxB59sIZN8ESJwvTleBjAXJg2Lk=
//pragma protect end_data_block
//pragma protect digest_block
1Okcq3Bx+b3XH43kFoKz4zxqo5g=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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b2syN15Zt9silhfUS78i/Q==
//pragma protect end_key_block
//pragma protect digest_block
ITI7TKpnea8mGeIScDpwDiMkohE=
//pragma protect end_digest_block
//pragma protect data_block
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zfCJ03MvTDAjpYybyzHUV06rZnOGF08tZzDnRhRlBHJqvuKGfXzOkR/jJLCojJ6e
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6+D4xx5eqORujSoYZgilZLFVpzvhJuBi1clrTv8gs85SRJJkhtAQBe6OhoIhbfOm
//pragma protect end_data_block
//pragma protect digest_block
GB4TclGiedNPwOlCGOg+lt+8X2M=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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yKmksiA1VTS/ApNZ0EH+uw==
//pragma protect end_key_block
//pragma protect digest_block
0tRm4qYvLsm4+VVCglvfy7MBywQ=
//pragma protect end_digest_block
//pragma protect data_block
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P2AOvclZP5+DvLIqnfK8wOtD8kvDQOzj+nEvuWR4rgY=
//pragma protect end_data_block
//pragma protect digest_block
QmYdJtuhCo0aZM4+JP1v/m9eIME=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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3kwGS0I922iDeQiFN3Ir/w==
//pragma protect end_key_block
//pragma protect digest_block
6EuaYA9k9pp62W1ll3O8D6cdfeE=
//pragma protect end_digest_block
//pragma protect data_block
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//pragma protect end_data_block
//pragma protect digest_block
X+tWUYKDSvSQwlcpHm5Nf2KNUiQ=
//pragma protect end_digest_block
//pragma protect end_protected


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_top) # (
    parameter FAMILY             = "TRION",       // New Param
    parameter SYNC_CLK           = 0,
    parameter BYPASS_RESET_SYNC  = 0,             // New Param
    parameter SYNC_STAGE         = 2,             // New Param
    parameter MODE               = "STANDARD",
    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
    parameter OPTIONAL_FLAGS     = 1,             // Reverted
    parameter OUTPUT_REG         = 0,
    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_FULL_ASSERT   = 27,
    parameter PROG_FULL_NEGATE   = 23,
    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_EMPTY_ASSERT  = 5,
    parameter PROG_EMPTY_NEGATE  = 7,
    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter WADDR_WIDTH        = depth2width(DEPTH),
    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
    parameter ENDIANESS		      = 0,
    parameter OVERFLOW_PROTECT   = 1,
    parameter UNDERFLOW_PROTECT  = 1,
    parameter RAM_STYLE          = "block_ram"

)(
    input  wire                   a_rst_i,
    input  wire                   a_wr_rst_i,
    input  wire                   a_rd_rst_i,
    input  wire                   clk_i,
    input  wire                   wr_clk_i,
    input  wire                   rd_clk_i,
    input  wire                   wr_en_i,
    input  wire                   rd_en_i,
    input  wire [DATA_WIDTH-1:0]  wdata,
    output wire                   almost_full_o,
    output wire                   prog_full_o,
    output wire                   full_o,
    output wire                   overflow_o,
    output wire                   wr_ack_o,
    output wire [WADDR_WIDTH :0]  datacount_o,
    output wire [WADDR_WIDTH :0]  wr_datacount_o,
    output wire                   empty_o,
    output wire                   almost_empty_o,
    output wire                   prog_empty_o,
    output wire                   underflow_o,
    output wire                   rd_valid_o,
    output wire [RDATA_WIDTH-1:0] rdata,
    output wire [RADDR_WIDTH :0]  rd_datacount_o,
    output wire                   rst_busy
); 

localparam WR_DEPTH      = DEPTH;
localparam WDATA_WIDTH   = DATA_WIDTH;
localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           

wire                   wr_rst_int;
wire                   rd_rst_int;
wire                   wr_en_int;
wire                   rd_en_int;
wire [WADDR_WIDTH-1:0] waddr;
wire [RADDR_WIDTH-1:0] raddr;
wire                   wr_clk_int;
wire                   rd_clk_int;
wire [WADDR_WIDTH :0]  wr_datacount_int;
wire [RADDR_WIDTH :0]  rd_datacount_int;

generate
    if (ASYM_WIDTH_RATIO == 4) begin
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
            assign datacount_o    = wr_datacount_int;
            assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}};
            assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}};
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
            assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
            assign wr_datacount_o = wr_datacount_int;
            assign rd_datacount_o = rd_datacount_int;
        end
    end
    else begin
        assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
        assign wr_datacount_o = wr_datacount_int;
        assign rd_datacount_o = rd_datacount_int;
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
        end
    end    

    if (!SYNC_CLK) begin
        //(* async_reg = "true" *) reg [1:0] wr_rst;
        //(* async_reg = "true" *) reg [1:0] rd_rst;
        //
        //always @ (posedge wr_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        wr_rst <= 2'b11;
        //    else 
        //        wr_rst <= {wr_rst[0],1'b0};            
        //end
        //
        //always @ (posedge rd_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        rd_rst <= 2'b11;
        //    else 
        //        rd_rst <= {rd_rst[0],1'b0};            
        //end
        

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_wr_rst_i;
            assign rd_rst_int = a_rd_rst_i; 
            assign rst_busy   = 1'b0;
        end 
        else begin
            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_wr_rst (
               .clk   (wr_clk_int),
               .reset (a_rst_i),
               .d_o   (wr_rst_int)
            );

            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_rd_rst (
               .clk   (rd_clk_int),
               .reset (a_rst_i),
               .d_o   (rd_rst_int)
            );
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end

    end
    else begin
        //(* async_reg = "true" *) reg [1:0] a_rst;
        //
        //always @ (posedge clk_i or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        a_rst <= 2'b11;
        //    else 
        //        a_rst <= {a_rst[0],1'b0};            
        //end
        wire   a_rst;

        `IP_MODULE_NAME(efx_resetsync) #(
           .ACTIVE_LOW (0)
        ) efx_resetsync_a_rst (
           .clk   (clk_i),
           .reset (a_rst_i),
           .d_o   (a_rst)
        );

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_rst_i;
            assign rd_rst_int = a_rst_i;
            assign rst_busy   = 1'b0;
        end
        else begin
            assign wr_rst_int = a_rst;
            assign rd_rst_int = a_rst;   
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end
    end 
endgenerate

`IP_MODULE_NAME(efx_fifo_ram) # (
    .FAMILY        (FAMILY),
    .WR_DEPTH      (WR_DEPTH),
    .RD_DEPTH      (RD_DEPTH),
    .WDATA_WIDTH   (WDATA_WIDTH),
    .RDATA_WIDTH   (RDATA_WIDTH),
    .WADDR_WIDTH   (WADDR_WIDTH),
    .RADDR_WIDTH   (RADDR_WIDTH),
    .OUTPUT_REG    (OUTPUT_REG),
    .RAM_MUX_RATIO (RAM_MUX_RATIO),
    .ENDIANESS	    (ENDIANESS),
    .RAM_STYLE     (RAM_STYLE)
) xefx_fifo_ram (
    .wdata (wdata), 
    .waddr (waddr),
    .raddr (raddr), 
    .we    (wr_en_int), 
    .re    (rd_en_int),
    .wclk  (wr_clk_int),
    .rclk  (rd_clk_int),
    .rdata (rdata)
);

`IP_MODULE_NAME(efx_fifo_ctl) # (
    .SYNC_CLK           (SYNC_CLK),
    .SYNC_STAGE         (SYNC_STAGE),
    .MODE               (MODE),
    .WR_DEPTH           (WR_DEPTH),
    .WADDR_WIDTH        (WADDR_WIDTH),
    .RADDR_WIDTH        (RADDR_WIDTH),
    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
    .PIPELINE_REG       (PIPELINE_REG),
    .ALMOST_FLAG        (ALMOST_FLAG),
    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
    .OUTPUT_REG         (OUTPUT_REG),
    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG),
    .OVERFLOW_PROTECT   (OVERFLOW_PROTECT),
    .UNDERFLOW_PROTECT  (UNDERFLOW_PROTECT)
) xefx_fifo_ctl (
    .wr_rst          (wr_rst_int),
    .rd_rst          (rd_rst_int),
    .wclk            (wr_clk_int),
    .rclk            (rd_clk_int),
    .we              (wr_en_i),
    .re              (rd_en_i),
    .wr_full         (full_o),
    .wr_ack          (wr_ack_o),
    .rd_empty        (empty_o),
    .wr_almost_full  (almost_full_o),
    .rd_almost_empty (almost_empty_o),
    .wr_prog_full    (prog_full_o),
    .rd_prog_empty   (prog_empty_o),
    .wr_en_int       (wr_en_int),
    .rd_en_int       (rd_en_int),
    .waddr           (waddr),
    .raddr           (raddr),
    .wr_datacount    (wr_datacount_int),
    .rd_datacount    (rd_datacount_int),
    .rd_vld          (rd_valid_o),
    .wr_overflow     (overflow_o),
    .rd_underflow    (underflow_o)
);

function integer depth2width;
input [31:0] depth;
begin : fnDepth2Width
    if (depth > 1) begin
        depth = depth - 1;
        for (depth2width=0; depth>0; depth2width = depth2width + 1)
            depth = depth>>1;
        end
    else
       depth2width = 0;
end
endfunction 

function integer width2depth;
input [31:0] width;
begin : fnWidth2Depth
    width2depth = width**2;
end
endfunction

function integer rdwidthcompute;
input [31:0] asym_option;
input [31:0] wr_width;
begin : RdWidthCompute
    rdwidthcompute = (asym_option==0)? wr_width/16 :
                     (asym_option==1)? wr_width/8  :
                     (asym_option==2)? wr_width/4  :
                     (asym_option==3)? wr_width/2  :
                     (asym_option==4)? wr_width/1  :
                     (asym_option==5)? wr_width*2  :
                     (asym_option==6)? wr_width*4  :
                     (asym_option==7)? wr_width*8  :
                     (asym_option==8)? wr_width*16 : wr_width/1;
end
endfunction

function integer rddepthcompute;
input [31:0] wr_depth;
input [31:0] wr_width;
input [31:0] rd_width;
begin : RdDepthCompute
    rddepthcompute = (wr_depth * wr_width) / rd_width;
end
endfunction

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ram) #(
    parameter FAMILY        = "TRION",
    parameter WR_DEPTH      = 512,
    parameter RD_DEPTH      = 512,
    parameter WDATA_WIDTH   = 8,
    parameter RDATA_WIDTH   = 8,
    parameter WADDR_WIDTH   = 9,
    parameter RADDR_WIDTH   = 9,
    parameter OUTPUT_REG    = 1,
    parameter RAM_MUX_RATIO = 4,
    parameter ENDIANESS 	 = 0, //0: Big endian (default)   1: Little endian 
    parameter RAM_STYLE     = "block_ram"
) (
    input  wire                     wclk,
    input  wire                     rclk,
    input  wire                     we,
    input  wire                     re,
    input  wire [(WDATA_WIDTH-1):0] wdata,
    input  wire [(WADDR_WIDTH-1):0] waddr,
    input  wire [(RADDR_WIDTH-1):0] raddr,
    output wire [(RDATA_WIDTH-1):0] rdata
);

localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";

(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
reg [RDATA_WIDTH-1:0]    r_rdata_1P;
reg [RDATA_WIDTH-1:0]    r_rdata_2P;

wire                     re_int;

generate
    if (FAMILY == "TRION") begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                end
                r_rdata_2P <= r_rdata_1P;
            end
        end
        
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            if (ENDIANESS == 0) begin 
            	integer i;
            	always @ (posedge wclk) begin
                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                    end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                	end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
        end
        
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
            //integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end 
            end
            else begin //endianess == 1
            	always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end
            end
        end
        if (OUTPUT_REG) begin
            assign re_int = re;
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end
    end
    else begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                    r_rdata_2P <= r_rdata_1P;
                end
            end
        end 
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            //integer i;
            if (ENDIANESS == 0) begin
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
            
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
        end
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
        	//integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
            
            else begin //endianess ==1
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
        end
        // NIC
        //if (MODE == "STANDARD") begin     
        //    if (OUTPUT_REG) begin
        //        reg re_r;
        //        always @ (posedge rclk) begin
        //            re_r <= re;
        //        end
        //        assign re_int = re | re_r;        
        //        assign rdata  = r_rdata_2P;            
        //    end
        //    else begin
        //        assign re_int = re;
        //        assign rdata  = r_rdata_1P;
        //    end
        //end
        //else begin
        //    assign re_int = re;
        //    assign rdata  = r_rdata_1P;
        //end    
        if (OUTPUT_REG) begin
            reg re_r;
            always @ (posedge rclk) begin
                re_r <= re;
            end
            assign re_int = re | re_r;        
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end    
    end
endgenerate

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   gray2bin.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Gray to Binary Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_gray2bin)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] bin_o,
 // input
 input [WIDTH-1:0] gray_i);

//---------------------------------------------------------------------
// Recursive Module
// Description: reduction xor
generate
   if (WIDTH > 1) begin
      wire [1:0] bin_1;
      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
      if (WIDTH == 2) begin
	 assign bin_o = bin_1;
      end
      else begin
	 assign bin_o[WIDTH-1] = bin_1[1];
	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
      end
   end
   else /* if (WIDTH == 1) */
     assign bin_o = gray_i;
endgenerate
   
endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   pipe_reg.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Parallel Pipelining Shift Register
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_datasync) #(
    parameter STAGE = 32,
    parameter WIDTH = 4
) (
 input  wire             clk_i,
 input  wire [WIDTH-1:0] d_i,
 output wire [WIDTH-1:0] d_o
);

(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
integer i;

always @(posedge clk_i) begin
  for (i=STAGE-1; i>0; i = i - 1) begin
    pipe_reg[i] <= pipe_reg[i-1];
  end
  pipe_reg[0] <= d_i;
end
assign d_o = pipe_reg[STAGE-1];
   

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_resetsync) #(
    parameter ASYNC_STAGE = 2,
    parameter ACTIVE_LOW = 1
) (
    input  wire             clk,
    input  wire             reset,
    output wire             d_o
);


generate
   if (ACTIVE_LOW == 1) begin: active_low
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (1),
         .RST_VALUE  (0)
      ) efx_resetsync_active_low (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b1),
         .d_o     (d_o)
      );
   end
   else begin: active_high
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (0),
         .RST_VALUE  (1)
      ) efx_resetsync_active_high (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b0),
         .d_o     (d_o)
      );
   end
endgenerate

endmodule



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_asyncreg) #(
    parameter ASYNC_STAGE = 2,
    parameter WIDTH = 4,
    parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
    parameter RST_VALUE = 0,
    parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance 
) (
    input  wire             clk,
    input  wire             reset_n,
    input  wire [WIDTH-1:0] d_i,
    output wire [WIDTH-1:0] d_o
);










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`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
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`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 )
`pragma protect data_block
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`pragma protect end_protected


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ctl) # (
    parameter SYNC_CLK           = 1,
    parameter SYNC_STAGE         = 2,
    parameter MODE               = "STANDARD",
    parameter WR_DEPTH           = 512,
    parameter WADDR_WIDTH        = 9,
    parameter RADDR_WIDTH        = 9,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter RAM_MUX_RATIO      = 1,
    parameter PIPELINE_REG       = 1,
    parameter ALMOST_FLAG        = 1,
    parameter PROGRAMMABLE_FULL  = "NONE",
    parameter PROG_FULL_ASSERT   = 0,
    parameter PROG_FULL_NEGATE   = 0,
    parameter PROGRAMMABLE_EMPTY = "NONE",
    parameter PROG_EMPTY_ASSERT  = 0,
    parameter PROG_EMPTY_NEGATE  = 0,
    parameter OUTPUT_REG         = 0,
    parameter HANDSHAKE_FLAG     = 1, 
    parameter OVERFLOW_PROTECT   = 0,
    parameter UNDERFLOW_PROTECT  = 0
)(
    input   wire                   wr_rst,
    input   wire                   rd_rst,
    input   wire                   wclk,
    input   wire                   rclk,
    input   wire                   we,
    input   wire                   re,
    output  wire                   wr_full,
    output  reg                    wr_ack,
    output  wire                   wr_almost_full,
    output  wire                   rd_empty,
    output  wire                   rd_almost_empty,
    output  wire                   wr_prog_full,
    output  wire                   rd_prog_empty,
    output  wire                   wr_en_int,
    output  wire                   rd_en_int,
    output  wire [WADDR_WIDTH-1:0] waddr,
    output  wire [RADDR_WIDTH-1:0] raddr,
    output  wire [WADDR_WIDTH:0]   wr_datacount,
    output  wire [RADDR_WIDTH:0]   rd_datacount,
    output  wire                   rd_vld,
    output  reg                    wr_overflow,
    output  reg                    rd_underflow
);

reg  [WADDR_WIDTH:0] waddr_cntr;
reg  [WADDR_WIDTH:0] waddr_cntr_r;
reg  [RADDR_WIDTH:0] raddr_cntr;
reg                  rd_valid;

wire [WADDR_WIDTH:0] waddr_int;
wire [RADDR_WIDTH:0] raddr_int;
wire                 rd_empty_int;
wire [WADDR_WIDTH:0] wr_datacount_int;
wire [RADDR_WIDTH:0] rd_datacount_int;

assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
// NIC
wire [RADDR_WIDTH:0] ram_raddr;
assign raddr     = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0];
//assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
//assign wr_en_int = we & ~wr_full;
assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we;

assign wr_datacount  = wr_datacount_int;
assign rd_datacount  = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int;


generate
    if (MODE == "FWFT") begin    
        // NIC
        //assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
        //assign rd_empty      = rd_empty_fwft;

        assign rd_en_int     = 1'b1;
        //assign rd_empty      = rd_empty_int;
        
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        init_set <= 1'b1;
        //    end
        //    else if (~init_set & rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //    else if (~rd_empty_int) begin
        //        init_set <= 1'b0;            
        //    end
        //    else if (rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //end
        // NIC 
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        rd_empty_fwft <= 1'b1;
        //    end
        //    else if (rd_en_int) begin
        //        rd_empty_fwft <= 1'b0;            
        //    end
        //    else if (re) begin
        //        rd_empty_fwft <= 1'b1;            
        //    end
        //end          
        
        //if (FAMILY == "TRION") begin
        if (OUTPUT_REG) begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid <= 1'b0;
                end
                else begin
                    rd_valid <= ~rd_empty;
                end
            end
            assign rd_vld = rd_valid;                
        end    
        else begin
            assign rd_vld = ~rd_empty;                
        end
        
        assign rd_empty = rd_empty_int;
    end
    else begin
        assign rd_en_int     = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re;
        assign rd_empty      = rd_empty_int;
        
        if (OUTPUT_REG) begin
            reg rd_valid_r;
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid_r <= 'h0;
                    rd_valid   <= 'h0;
                end
                else begin
                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
                end
            end
            assign rd_vld = rd_valid;            
        end
        else begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid  <= 'h0;
                end
                else begin
                    rd_valid <= rd_en_int;
                end
            end
            assign rd_vld = rd_valid;
        end
    end
    
    if (ALMOST_FLAG) begin
        assign wr_almost_full   = wr_datacount >= WR_DEPTH-1;
        assign rd_almost_empty  = rd_datacount <= 'd1;
    end
    else begin
        assign wr_almost_full   = 1'b0;
        assign rd_almost_empty  = 1'b0;        
    end
    
    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end  
    end
    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   

        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end              
    end
    else begin
        assign wr_prog_full  = 1'b0; 
    end
        
    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end
    end
    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end  
    end
    else begin
        assign rd_prog_empty  = 1'b0; 
    end
    
    if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_ack <= 1'b0;
            end
            else begin
                // NIC
                //wr_ack <= wr_en_int & ~wr_overflow;
                wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int;
            end
        end
    end

    if (OVERFLOW_PROTECT) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else if (we && wr_full) begin
                wr_overflow <= 1'b1;
            end
            else begin
                wr_overflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else begin
                wr_overflow <= we && wr_full ? 1'b1 : wr_overflow;
            end
        end
    end

    if (UNDERFLOW_PROTECT) begin     
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else if (re && rd_empty) begin
                rd_underflow <= 1'b1;
            end
            else begin
                rd_underflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else begin
                rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow;
            end
        end
    end
    
    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
    
    if (ASYM_WIDTH_RATIO < 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
    end
    // NIC
    else if (ASYM_WIDTH_RATIO == 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - raddr_int;
        assign rd_datacount_int = waddr_int - raddr_cntr;
    end
    else begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
        // NIC
        //assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr;
    end
endgenerate

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr   <= 'h0;
    end
    else if (wr_en_int) begin
        waddr_cntr   <= waddr_cntr + 1'b1;
    end
end

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr_r  <= 'h0;
    end
    else begin
        waddr_cntr_r  <= waddr_cntr;
    end
end

always @ (posedge rclk or posedge rd_rst) begin
    if (rd_rst) begin
        raddr_cntr   <= 'h0;
    end
    // NIC
    //else if (rd_en_int) begin
    else begin
        //raddr_cntr   <= raddr_cntr + 1'b1;
        //raddr_cntr   <= raddr_cntr + (re & ~rd_empty_int);
        raddr_cntr   <= ram_raddr;
    end
end
// NIC
assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re);


generate
    if (SYNC_CLK) begin : sync_clk
       if (MODE == "FWFT") begin
          assign waddr_int = waddr_cntr_r;
          assign raddr_int        = raddr_cntr;
       end
       else begin
          assign waddr_int        = waddr_cntr;
          assign raddr_int        = raddr_cntr;
       end
    end
    else begin : async_clk
        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
        
        wire [RADDR_WIDTH:0] raddr_cntr_gry;
        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
        wire [WADDR_WIDTH:0] waddr_cntr_gry;
        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;

        if (PIPELINE_REG) begin
            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
        
            assign waddr_int        = waddr_cntr_sync_g2b_r;
            assign raddr_int        = raddr_cntr_sync_g2b_r;
            
            always @ (posedge wclk or posedge wr_rst) begin
                if (wr_rst) begin
                    raddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
                end
            end
            
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    waddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
                end
            end
        end
        else begin
            assign waddr_int        = waddr_cntr_sync_g2b;
            assign raddr_int        = raddr_cntr_sync_g2b;        
        end
      
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                raddr_cntr_gry_r <= 'h0;
            end
            else begin
                raddr_cntr_gry_r <= raddr_cntr_gry;
            end
        end
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_bin2gray    (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync   (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                waddr_cntr_gry_r <= 'h0;
            end
            else begin
                waddr_cntr_gry_r <= waddr_cntr_gry;
            end
        end        
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        

    end
endgenerate
endmodule


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   bin2gray.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Binary to Gray Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_bin2gray)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] gray_o,
 // input
 input [WIDTH-1:0] bin_i
 );

//---------------------------------------------------------------------
// Function :   bit_xor
// Description: reduction xor
function bit_xor (
  input [31:0] nex_bit,
  input [31:0] curr_bit,
  input [WIDTH-1:0] xor_in);
  begin : fn_bit_xor
    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
  end
endfunction

// Convert Binary to Gray, bit by bit
generate 
begin
  genvar bit_idx;
  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
  end
  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
end
endgenerate

endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


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//pragma protect end_data_block
//pragma protect digest_block
ttN5oYHd8WkRTKPQ4gjy7ImfYSw=
//pragma protect end_digest_block
//pragma protect end_protected


module `IP_MODULE_NAME(mii_if) #(
   parameter NO_PREAMBLE = 0
) (
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//MII Interface
input                           mii_txc,
output  reg     [3:0]           mii_txd,
output  reg                     mii_tx_dv,
output  reg                     mii_tx_err,

input                           mii_rxc,
input           [3:0]           mii_rxd,
input                           mii_rx_dv,
input                           mii_rx_err

//Status and  Error Signals
);
// Parameter Define 
//localparam                      SPEED_100M_DIV = (TX_REFCLK == 125) ? 10 : 2;
//localparam                      SPEED_10M_DIV  = SPEED_100M_DIV*10;
//localparam                      SPEED_CLK_DIV = (TX_REFCLK == 125) ? SPEED_100M_DIV/2 + 1 : 0 ;
// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [3:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_dv_pre;
reg                             rx_dv_dl1;
reg     [3:0]                   rxd_pre;
reg     [3:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;
reg     [3:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [3:0]                   gm_tx_d_h;
reg     [7:0]                   gm_tx_d_r;
reg                             gm_tx_en_r;
reg                             gm_tx_err_r;
reg                             preamble_flg;
reg     [1:0]                   cur_st;
reg     [1:0]                   nxt_st;
reg                             add_preamble;


// Wire Define
wire                            add_preamble_w;

assign add_preamble_w = mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err && cur_st == 2'b01 && preamble_flg;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else
      tx_mac_aclk_en <= ~tx_mac_aclk_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_r <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_r <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_en_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_en_r <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_err_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_err_r <= gm_tx_err;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd <= 4'h0;
   else if (gm_tx_en_r == 1'b1) begin
      if (tx_mac_aclk_en == 1'b0)
          txd <= gm_tx_d_r[3:0];
      else
          txd <= gm_tx_d_r[7:4];
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_en <= 1'b0;
   else 
       tx_en <= gm_tx_en_r;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else 
       tx_er <= gm_tx_err_r;
end

always @ (posedge mii_txc or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      mii_tx_dv  <= 1'b0;
      mii_txd    <= 4'h0;
      mii_tx_err <= 1'b0;
   end
   else begin
      mii_tx_dv  <= tx_en;
      mii_txd    <= txd[3:0];
      mii_tx_err <= tx_er;
   end
end
/*----------------------- Rx Region ----------------------------*/
always @ (posedge mii_rxc or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 4'h0;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else if (add_preamble_w && NO_PREAMBLE != 1) begin
      rxd   <= 4'h5;
      rx_dv <= 1'b1;
      rx_er <= rx_er;
   end
   else if (add_preamble && NO_PREAMBLE != 1) begin
      rxd   <= rxd_pre;
      rx_dv <= rx_dv_pre;
      rx_er <= rx_er;
   end
   else begin
      rxd   <= mii_rxd;
      rx_dv <= mii_rx_dv;
      rx_er <= mii_rx_err;
   end
end

assign rx_mac_aclk = mii_rxc;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd_pre <= 4'h0;
      rx_dv_pre <= 1'b0;
   end
   else if (add_preamble_w || add_preamble) begin
      rxd_pre <= mii_rxd;
      rx_dv_pre <= mii_rx_dv;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
    if (rx_reset == 1'b1)
       add_preamble <= 1'b0;
    else if (add_preamble_w)
       add_preamble <= 1'b1;
    else if (!mii_rx_dv)
       add_preamble <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else
      rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      cur_st <= 2'b00;
   end
   else begin
      cur_st <= nxt_st;
   end
end

always @ (*) begin
   case (cur_st)
      2'b00: begin
         if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else
            nxt_st = 2'b00;
      end
      2'b01: begin
         if (mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b10;
         else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else 
            nxt_st = 2'b00;
      end
      2'b10: begin
         if (mii_rx_dv) 
            nxt_st = 2'b10;
         else
            nxt_st = 2'b00;
         end
      default: nxt_st = 2'b00;
   endcase
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      preamble_flg <= 1'b0;
   end
   else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err && cur_st == 2'b01) begin
      preamble_flg <= ~preamble_flg;
   end
   else begin
      preamble_flg <= 1'b0;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rx_dv_dl1 <= 1'b0;
      rxd_dl1   <= 4'h0;
   end
   else begin
      rx_dv_dl1 <= rx_dv;
      rxd_dl1   <= rxd;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else
      gm_rx_dv <= rx_dv_dl1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 1'b0;
   else if (rx_dv == 1'b0)
      rx_odd_data_ptr <= 1'b0;
   else
      rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if ((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
      gm_rx_d <= {rxd[3:0], rxd_dl1[3:0]};
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       gm_rx_err <= 1'b0;
   else begin
      if (rx_er == 1'b1)               gm_rx_err <= 1'b1;
      else if (rx_mac_aclk_en == 1'b1) gm_rx_err <= 1'b0;
   end
end


endmodule



/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii_if)#(
    parameter                       RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                           tx_mac_aclk,
   output  reg                     tx_mac_aclk_en,
   input                           tx_reset,
   output  wire                    rx_mac_aclk,
   output  reg                     rx_mac_aclk_en,
   input                           rx_reset,
   //Configuration Signals
   input           [2:0]           eth_speed,
   input                           rgmii_rxc_edge,//0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   input                           rgmii_txc_dly,//0:rgmii tx clock delay disable; 1:rgmii tx clock delay enable;
   //GMII Interface
   output  reg     [7:0]           gm_rx_d,
   output  reg                     gm_rx_dv,
   output  reg                     gm_rx_err,
   input           [7:0]           gm_tx_d,
   input                           gm_tx_en,
   input                           gm_tx_err,
   //RGMII Interface
   output  wire    [3:0]           rgmii_txd_HI,
   output  wire    [3:0]           rgmii_txd_LO,
   output  wire                    rgmii_tx_ctl_HI,
   output  wire                    rgmii_tx_ctl_LO,
   output  wire                    rgmii_txc_HI,//if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  wire                    rgmii_txc_LO,
   input           [3:0]           rgmii_rxd_HI,
   input           [3:0]           rgmii_rxd_LO,
   input                           rgmii_rx_ctl_HI,
   input                           rgmii_rx_ctl_LO,
   input                           rgmii_rxc
   //Status and  Error Signals
);

// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [7:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg     [1:0]                   txc;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;

// Wire Define
wire                            rx_dv;
wire    [7:0]                   rxd;
wire                            rx_er;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if ((eth_speed == 3'h4) ||
           ((eth_speed == 3'h2) && (aclk_en_cnt == 7'd9)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd99)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[7:4] <= 4'h0;
   else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[7:4] <= gm_tx_d[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[3:0] <= 4'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[3:0] <= gm_tx_d[3:0];
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd6)) ||
            ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd51)))
      txd[3:0] <= txd[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_en <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_er <= gm_tx_err;
end
/*
always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
        3'h4 :
            txc <= 2'b01;
        3'h2 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b00;
            endcase
        3'h1 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
                    txc <= 2'b00;
            endcase
        default :
            txc <= 2'b0;
        endcase
end

*/
reg [1:0]    txc_100m_r;
reg [1:0]    txc_10m_r;

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_100m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
          1'b0 : //rgmii tx clock delay disable.
             if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                txc_100m_r <= 2'b00;
          1'b1 ://rgmii tx clock delay enable.
             if ((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b00;
       endcase
   end
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_10m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
       1'b0 ://rgmii tx clock delay disable.
           if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
               txc_10m_r <= 2'b00;
       1'b1 ://rgmii tx clock delay enable.
           if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
               txc_10m_r <= 2'b00;
       endcase
   end
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
            3'h4 :
                txc <= 2'b01;
            3'h2 :
                txc <= txc_100m_r;
            3'h1 :
                txc <= txc_10m_r;
            default :
                txc <= 2'b0;
        endcase
end

/*----------------------- Rx Region ----------------------------*/
assign rx_mac_aclk = rgmii_rxc;

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_mac_aclk_en <= 1'b0;
    else if(eth_speed[2] == 1'b1)
        rx_mac_aclk_en <= 1'b1;
    else
        rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        begin
            rx_dv_dl1 <= 1'b0;
            rxd_dl1 <= 8'h0;
        end
    else
        begin
            rx_dv_dl1 <= rx_dv;
            rxd_dl1 <= rxd;
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_dv <= 1'b0;
    else
        gm_rx_dv <= rx_dv_dl1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_odd_data_ptr <= 1'b0;
    else if(rx_dv == 1'b0)
        rx_odd_data_ptr <= 1'b0;
    else
        rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_d <= 8'h0;
    else
        begin
            if((eth_speed[2] == 1'b1) && (rx_dv_dl1 == 1'b1))
                gm_rx_d <= rxd_dl1;
            else if((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
                gm_rx_d <= {rxd[3:0],rxd_dl1[3:0]};
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_err <= 1'b0;
    else
        begin
            if(rx_er == 1'b1)
                gm_rx_err <= 1'b1;
            else if(rx_mac_aclk_en == 1'b1)
                gm_rx_err <= 1'b0;
        end
end

/*----------------------- PHY Interface ----------------------------*/
`IP_MODULE_NAME(rgmii) #(
    .RGMII_SYNC_EN                      (RGMII_SYNC_EN                      )
)
u_rgmii
(
//Globle Signals
    .tx_mac_aclk                        (tx_mac_aclk                        ),
    .tx_reset                           (tx_reset                           ),
    .rx_reset                           (rx_reset                           ),
//Configuration Signals
    .eth_speed                          (eth_speed                          ),
    .rgmii_rxc_edge                     (rgmii_rxc_edge                     ),
//Phy Interface
    .txd                                (txd                                ),
    .tx_en                              (tx_en                              ),
    .tx_er                              (tx_er                              ),
    .txc                                (txc                                ),
    .rxd                                (rxd                                ),
    .rx_dv                              (rx_dv                              ),
    .rx_er                              (rx_er                              ),
//RGMII Interface
    .rgmii_txd_HI                       (rgmii_txd_HI                       ),
    .rgmii_txd_LO                       (rgmii_txd_LO                       ),
    .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI                    ),
    .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO                    ),
    .rgmii_txc_HI                       (rgmii_txc_HI                       ),
    .rgmii_txc_LO                       (rgmii_txc_LO                       ),
    .rgmii_rxd_HI                       (rgmii_rxd_HI                       ),
    .rgmii_rxd_LO                       (rgmii_rxd_LO                       ),
    .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI                    ),
    .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO                    ),
    .rgmii_rxc                          (rgmii_rxc                          )
);

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
module `IP_MODULE_NAME(rgmii_sync)
(
//Globle Signals
input                           rgmii_rxc,
input                           rx_reset,
input           [2:0]           eth_speed,
//RGMII Rx Interface Input
input           [3:0]           rgmii_rxd_HI_i,
input           [3:0]           rgmii_rxd_LO_i,
input                           rgmii_rx_ctl_HI_i,
input                           rgmii_rx_ctl_LO_i,
//RGMII Rx Interface Output
output  reg     [3:0]           rgmii_rxd_HI_o,
output  reg     [3:0]           rgmii_rxd_LO_o,
output  reg                     rgmii_rx_ctl_HI_o,
output  reg                     rgmii_rx_ctl_LO_o
);


// Parameter Define 
parameter State_idle     = 2'd0;
parameter State_preamble = 2'd1;
parameter State_data_dl1 = 2'd2;
parameter State_data_dl2 = 2'd3;


// Register Define 
reg     [1:0]                   cur_state;
reg     [1:0]                   next_state;
reg                             preamble_odd;
reg     [3:0]                   rx_d_dl1;
reg                             rx_dv_dl1;
reg     [3:0]                   rx_d_dl2;
reg                             rx_dv_dl2;

// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rx_d_dl1      <= 4'h0;
      rx_dv_dl1     <= 1'b0;
      rx_d_dl2      <= 4'h0;
      rx_dv_dl2     <= 1'b0;
   end
   else begin
      rx_d_dl1      <= rgmii_rxd_LO_i;
      rx_dv_dl1     <= rgmii_rx_ctl_HI_i;
      rx_d_dl2      <= rx_d_dl1;
      rx_dv_dl2     <= rx_dv_dl1;
   end
end

/*----------------------- FSM Region ----------------------------*/
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) cur_state <= State_idle;
	else          cur_state <= next_state;
end

always @ (*) begin
	case (cur_state)
      State_idle :
         if ((rx_dv_dl1 == 1'b1) && (rx_d_dl1 == 4'h5))
             next_state = State_preamble;
         else
             next_state = State_idle;

      State_preamble : 
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b0))
            next_state = State_data_dl1;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
            next_state = State_data_dl2;
         else if (rx_d_dl1 != 4'h5)
            next_state = State_idle;
         else
            next_state = State_preamble;
          
      State_data_dl1 :
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl1;

      State_data_dl2 :
         if (rx_dv_dl2 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl2;

      default :
         next_state = State_idle;
    endcase
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
    if (rx_reset) 
       preamble_odd <= 1'b0;
    else if (cur_state == State_preamble)
       preamble_odd <= ~preamble_odd;
    else
       preamble_odd <= 1'b0;
end

/*----------------------- Sync Output Region ----------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rxd_LO_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_LO_o <= rgmii_rxd_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rxd_LO_o <= 4'h5;
   else if (cur_state == State_data_dl2)
      rgmii_rxd_LO_o <= rx_d_dl2;
   else
      rgmii_rxd_LO_o <= rx_d_dl1;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) 
      rgmii_rxd_HI_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_HI_o <= rgmii_rxd_HI_i;
   else
      rgmii_rxd_HI_o <= 4'h0;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_HI_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_HI_o <= rgmii_rx_ctl_HI_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_HI_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_HI_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_HI_o <= rx_dv_dl1;
end

always @(posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_LO_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_LO_o <= rgmii_rx_ctl_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_LO_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_LO_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_LO_o <= rx_dv_dl1;
end

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii) #(
    parameter                   RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                        tx_mac_aclk,
   input                        tx_reset,
   input                        rx_reset,
   //Configuration Signals
   input           [2:0]        eth_speed,
   input                        rgmii_rxc_edge, //0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   //Phy Interface
   input           [7:0]        txd,
   input                        tx_en,
   input                        tx_er,
   input           [1:0]        txc, //if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  reg     [7:0]        rxd,
   output  reg                  rx_dv,
   output  reg                  rx_er,
   //RGMII Interface
   output  reg     [3:0]        rgmii_txd_HI,
   output  reg     [3:0]        rgmii_txd_LO,
   output  reg                  rgmii_tx_ctl_HI,
   output  reg                  rgmii_tx_ctl_LO,
   output  reg                  rgmii_txc_HI,
   output  reg                  rgmii_txc_LO,
   input           [3:0]        rgmii_rxd_HI,
   input           [3:0]        rgmii_rxd_LO,
   input                        rgmii_rx_ctl_HI,
   input                        rgmii_rx_ctl_LO,
   input                        rgmii_rxc
   //Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [3:0]                   rgmii_rxd_HI_d1;
reg                             rgmii_rx_ctl_HI_d1;
reg     [3:0]                   rgmii_txd_HI_r;
reg     [3:0]                   rgmii_txd_LO_r;
reg                             rgmii_tx_ctl_HI_r;
reg                             rgmii_tx_ctl_LO_r;
reg                             rgmii_txc_HI_r;
reg                             rgmii_txc_LO_r;
// Wire Define
wire                            tx_en_to_ddr;
wire                            rgmii_tx_ctl_int;
wire    [3:0]                   txd_falling;
/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- RGMII Tx Region ----------------------------*/
assign tx_en_to_ddr = (eth_speed[2] == 1'b1) ? tx_en : tx_en && (!tx_er);
assign rgmii_tx_ctl_int = tx_en ^ tx_er;

assign txd_falling = (eth_speed[2] == 1'b1) ? txd[7:4] : txd[3:0];

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI_r    <= 1'b0;
      rgmii_txc_LO_r    <= 1'b0;
      rgmii_tx_ctl_HI_r <= 1'b0;
      rgmii_tx_ctl_LO_r <= 1'b0;
      rgmii_txd_HI_r    <= 4'b0;
      rgmii_txd_LO_r    <= 4'b0;
   end 
   else begin
      rgmii_txc_HI_r    <= txc[0];
      rgmii_txc_LO_r    <= txc[1];     
      rgmii_tx_ctl_HI_r <= tx_en_to_ddr;
      rgmii_tx_ctl_LO_r <= rgmii_tx_ctl_int;
      rgmii_txd_HI_r    <= txd[3:0];
      rgmii_txd_LO_r    <= txd_falling;
   end
end


always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI    <= 1'b0;
      rgmii_txc_LO    <= 1'b0;
      rgmii_tx_ctl_HI <= 1'b0;
      rgmii_tx_ctl_LO <= 1'b0;
      rgmii_txd_HI    <= 4'b0;
      rgmii_txd_LO    <= 4'b0;
   end
   else begin
      rgmii_txc_HI    <= rgmii_txc_HI_r;
      rgmii_txc_LO    <= rgmii_txc_LO_r;
      rgmii_tx_ctl_HI <= rgmii_tx_ctl_HI_r;
      rgmii_tx_ctl_LO <= rgmii_tx_ctl_LO_r;
      rgmii_txd_HI    <= rgmii_txd_HI_r;
      rgmii_txd_LO    <= rgmii_txd_LO_r;
   end
end

/*----------------------- RGMII Rx Region ----------------------------*/
//rgmii_rxd & rgmii_rx_ctl
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rgmii_rxd_HI_d1    <= 4'h0;
      rgmii_rx_ctl_HI_d1 <= 1'b0;
   end 
   else begin
      rgmii_rxd_HI_d1    <= rgmii_rxd_HI;
      rgmii_rx_ctl_HI_d1 <= rgmii_rx_ctl_HI;
   end
end

generate
   if (RGMII_SYNC_EN == 0) begin
      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rxd[7:4] <= rgmii_rxd_LO;
               rxd[3:0] <= rgmii_rxd_HI_d1;
               rx_dv    <= rgmii_rx_ctl_HI_d1;
               rx_er    <= rgmii_rx_ctl_HI_d1^rgmii_rx_ctl_LO;
            end
            else begin//1:DDIO Falling Edge
               rxd[7:4] <= rgmii_rxd_HI;
               rxd[3:0] <= rgmii_rxd_LO;
               rx_dv    <= rgmii_rx_ctl_LO;
               rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI;
            end
        end
        else begin //100M or 10M
           rxd[7:4] <= 4'b0;
           rxd[3:0] <= rgmii_rxd_LO;
           rx_dv    <= rgmii_rx_ctl_LO;
           rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI_d1;
        end
     end
   end
   else begin
      reg  [3:0]  rgmii_rxd_HI_i;
      reg  [3:0]  rgmii_rxd_LO_i;
      reg         rgmii_rx_ctl_HI_i;
      reg         rgmii_rx_ctl_LO_i;
      wire [3:0]  rgmii_rxd_HI_sync;
      wire [3:0]  rgmii_rxd_LO_sync;
      wire        rgmii_rx_ctl_HI_sync;
      wire        rgmii_rx_ctl_LO_sync;

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rgmii_rxd_HI_i    <= 4'h0;
            rgmii_rxd_LO_i    <= 4'h0;
            rgmii_rx_ctl_HI_i <= 1'b0;
            rgmii_rx_ctl_LO_i <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_LO;
               rgmii_rxd_LO_i    <= rgmii_rxd_HI_d1;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI_d1;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
            else begin //1:DDIO Falling Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_HI;
               rgmii_rxd_LO_i    <= rgmii_rxd_LO;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
         end        
         else begin//100M or 10M
            rgmii_rxd_HI_i    <= rgmii_rxd_HI_d1;
            rgmii_rxd_LO_i    <= rgmii_rxd_LO;
            rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_LO;
            rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_HI_d1;
         end
      end

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else begin
            rxd[7:4] <= rgmii_rxd_HI_sync;
            rxd[3:0] <= rgmii_rxd_LO_sync;
            rx_dv    <= rgmii_rx_ctl_HI_sync;
            rx_er    <= rgmii_rx_ctl_HI_sync^rgmii_rx_ctl_LO_sync;
         end
      end
      
      /*----------------------- RGMII Rx Sync Module -----------------------*/
      `IP_MODULE_NAME(rgmii_sync) u_rgmii_sync
      (
      //Globle Signals
          .rgmii_rxc                  (rgmii_rxc                  ),
          .rx_reset                   (rx_reset                   ),
          .eth_speed                  (eth_speed                  ),
      //RGMII Rx Interface Input
          .rgmii_rxd_HI_i             (rgmii_rxd_HI_i             ),
          .rgmii_rxd_LO_i             (rgmii_rxd_LO_i             ),
          .rgmii_rx_ctl_HI_i          (rgmii_rx_ctl_HI_i          ),
          .rgmii_rx_ctl_LO_i          (rgmii_rx_ctl_LO_i          ),
      //RGMII Rx Interface Output
          .rgmii_rxd_HI_o             (rgmii_rxd_HI_sync          ),
          .rgmii_rxd_LO_o             (rgmii_rxd_LO_sync          ),
          .rgmii_rx_ctl_HI_o          (rgmii_rx_ctl_HI_sync       ),
          .rgmii_rx_ctl_LO_o          (rgmii_rx_ctl_LO_sync       )
      );
   end
endgenerate


endmodule


module `IP_MODULE_NAME(rmii_if)
(
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//RGMII Interface
input                           rmii_clk_ref,
output  reg     [1:0]           rmii_txd,
output  reg                     rmii_tx_en,

input           [1:0]           rmii_rxd,
input                           rmii_crs_dv,
input                           rmii_rx_err

//Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [6:0]                   rx_aclk_en_cnt;
reg     [1:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_err_dl1;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg     [6:0]                   rx_odd_data_ptr;
reg     [1:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [7:0]                   gm_tx_d_temp;
reg                             tx_en_temp;
reg     [6:0]                   txbit_cnt;
reg                             rx_dv_compensate;
reg                             rx_err_compensate;
reg                             rx_err_latch;
reg     [7:0]                   rx_d_compensate;
reg     [6:0]                   rx_compensate_cnt;
// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd39)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_temp <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_temp <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en_temp <= 1'b0;
   else if(tx_mac_aclk_en == 1'b1)
      tx_en_temp <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txbit_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (txbit_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (txbit_cnt == 7'd39)))
      txbit_cnt <= 7'd0;
   else if (tx_en_temp == 1'b1)
      txbit_cnt <= txbit_cnt + 1'b1;
   else
      txbit_cnt <= 7'd0; 
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txd <= 2'h0;
   else if (eth_speed == 3'h2) begin
      case(txbit_cnt[1:0])
         2'b00: txd <= gm_tx_d_temp[1:0];
         2'b01: txd <= gm_tx_d_temp[3:2];
         2'b10: txd <= gm_tx_d_temp[5:4];
         2'b11: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case(txbit_cnt[5:0])
         6'd00: txd <= gm_tx_d_temp[1:0];
         6'd10: txd <= gm_tx_d_temp[3:2];
         6'd20: txd <= gm_tx_d_temp[5:4];
         6'd30: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else 
      tx_en <= tx_en_temp;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
       tx_er <= gm_tx_err;
end

always @ (posedge rmii_clk_ref or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      rmii_tx_en <= 1'b0;
      rmii_txd   <= 2'b0;
   end
   else begin
      rmii_tx_en  <= tx_en;
      rmii_txd    <= txd[1:0];
   end
end

/*----------------------- Rx Region ----------------------------*/
always @(posedge rmii_clk_ref or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 2'b00;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else begin
      rxd   <= rmii_rxd;
      rx_dv <= rmii_crs_dv;
      rx_er <= rmii_rx_err;
   end
end

assign rx_mac_aclk = rmii_clk_ref;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_aclk_en_cnt == 7'd39)))
      rx_aclk_en_cnt <= 7'd0;
   else
      rx_aclk_en_cnt <= rx_aclk_en_cnt + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else if (rx_aclk_en_cnt == 7'd0)
      rx_mac_aclk_en <= 1'b1;
   else
      rx_mac_aclk_en <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_odd_data_ptr == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_odd_data_ptr == 7'd39)) || (rx_dv == 1'b0))
      rx_odd_data_ptr <= 7'd0;
   else 
      rx_odd_data_ptr <= rx_odd_data_ptr + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_dl1 <= 1'b0;
   else 
      rx_dv_dl1 <= rx_dv; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_dl1 <= 1'b0;
   else 
       rx_err_dl1 <= rx_er; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rxd_dl1 <= 8'h0;
   else if (eth_speed == 3'h2) begin
      case (rx_odd_data_ptr[1:0])
         2'b00: rxd_dl1[1:0] <= rxd;
         2'b01: rxd_dl1[3:2] <= rxd;
         2'b10: rxd_dl1[5:4] <= rxd;
         2'b11: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case (rx_odd_data_ptr[5:0])
         6'd00: rxd_dl1[1:0] <= rxd;
         6'd10: rxd_dl1[3:2] <= rxd;
         6'd20: rxd_dl1[5:4] <= rxd;
         6'd30: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end
   else;    
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (rx_dv_dl1 == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_compensate_cnt <= rx_compensate_cnt;
   else
      rx_compensate_cnt <= rx_compensate_cnt + 1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_dv_compensate <= 1'b0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_dv_compensate <= 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_latch <= 1'b0;
   else begin
      if (rx_dv & rx_er)                rx_err_latch <= 1'b1;
      else if (rx_odd_data_ptr == 7'd0) rx_err_latch <= 1'b0; 
      else                              rx_err_latch <= rx_err_latch;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_err_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_err_compensate <= 1'b0;
   else if (rx_odd_data_ptr == 7'd0)
      rx_err_compensate <= rx_err_latch;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_d_compensate <= 8'h0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_d_compensate <= rxd_dl1;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_dv <= rx_dv_compensate;
end


always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_d <= rx_d_compensate;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_err <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_err <= rx_err_compensate;
end

endmodule



//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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t69l8BOBmXaHLSfmBmAxJw==
//pragma protect end_key_block
//pragma protect digest_block
ePVsN48yGEZh+oJ/8GPEgNrTsQ4=
//pragma protect end_digest_block
//pragma protect data_block
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O5ICg7+zYcsSsbJ+z0i3WXGsppIT8X+njQYnW2KUbs/JXNvITYA1w6D/Dh2GYbTD
ME9Sokv8drpY/5NdOcYWc/ifbovawoNBgk7DR5/vvA9SEWWx4UmhdbXTopoWFq76
aFrJr8FSDIBeMqzGbIpfIiMhaAppesmr0xmXaLKckw7XtgeWMB//fr+VOrCNvmsb
befeYPv36c0kfa3DiAfZGCWP4CaEq7uvZ4oTwbKSQ2UL1bdrhhDMinDWzBbPlKTR
4l/3pR+Rf9A07yE8MIVXaUau2ZaRgdKbw8ivAXKKUuTFRljepbz13oYUMGyDVdIr
zzK+rWmZw++E4q1foFt+LXkWCEy7yB/6ZKTONh5Y5qajYGmBa8Fhg1krTaHBSk9C
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fNWP3vqtUJtpk0C9BVe3lca0s3HILObFhGubOL99k0PBwdH3t/9W6GQwbcfW662Q
/uWU8yD4Lv1UJJBcoa279VuPwMTjBHvtPZk99la0Ul8oV3vzBlodSfibRZj8so72
E+bwBLaaIvuax8/IURAiVdS6lsMXaaChy241ZxiCNrgkVMcxhHwm6odMjrorgxR8
s6heCEYcewvF5Ix6+tMjKp7AT4Wieb21Z3hpLB1RILoN8Oa0Xd+UcRjNDntrXbJu
7pZzUg/hcnVCnih/JwkZ8eAFf3xb2EgfIE29AuJ/MWJlFnHGBRIaNBGsg/4TOz7t
qKlsoB+HP5M8rGtJGkYUs4IuxJvPvIISfQc3Z1BmMfFMHqrTRgX0kFIRptGeQ3ot
A1VPfi7gPUbttnm20QPyM6BHiXLTKmbI3aIkyeNqEWDxQedqPzs+GJo64fW7PIeD
KnqwcjvUCnnF1H7rhFwfAceMlyvSlgE5VCH/C/Vc697xZFd8nYDUFFWOSNtCMz5Q
JFlrPWMNU1mbpeNa6fDHvei4fFx8Bo8dFPTWUJCVEdU=
//pragma protect end_data_block
//pragma protect digest_block
4fgubcVSsGbsihJUaEnAoP/WOus=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
ArtFgEcTFuExxn3GR8FXMf8nwl3zKw461a9BondW1J0YUuXertNKCWOunZwIrdrk
kw2YzU9ydjX7blOfOkioZGvDDlgewjLov5Mm5pDGPknUvpOwcW4MZWQrEGy2pLBs
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YWiNMTyxxSK6A/fDoVY76cti8cxvT7LsA7n9t7wikAJZ4AjX9A0pT3o0a7/tfAKv
Y5rtMNAzAxGpKz3kT1HsEbG0900ME4mG3SE3k1voeJSSuBlO8Ien/845CEmfKiFt
0QXWlFyuoeA/Oh3YqqX89A==
//pragma protect end_key_block
//pragma protect digest_block
Y7TScLLhiz6ikFqRuivjMbSX+G0=
//pragma protect end_digest_block
//pragma protect data_block
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2VxZNxnNcgO9ayk39Pf0khJmS09NU1Sfzu9jZ6HOgXZfJm98AK86fw+AjO9rQrXi
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BmMMRh+KjDu8v6UN8SHgT+MGKhTbiz5dlofmkdFVp7HGkryYmW67eBwD0ZbSzx/Z
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pkWqFCHvge0F5LI/8eEBZ8Be9CYAQnyZYQb6E9uFAMHt7HPkwoBWUJv++SBZQHBZ
//pragma protect end_data_block
//pragma protect digest_block
xciDfX1Ldbg0C13jX2WprHhS4gs=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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FVUrqm7EADxShs4MTf6x4Q==
//pragma protect end_key_block
//pragma protect digest_block
ptYnyNqudo4cULGlJXYZ099X40A=
//pragma protect end_digest_block
//pragma protect data_block
B2BlJu9glwLJb56KeOuhxDsO8339difvmdpZMVP6zh1oko3V7e7IKrnVdS+JWCzf
hWlIzdCJuTFnKFk/71BekcgqYl0WVxToPqraYdzZ0ynrs+v1ksaANhtApwYm20om
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nvdgR12ZMB0ok1vkLpXri3fKCceuepKPe4gbsP+6SctyLJV8flBrd6OZ8ESv/qUX
DKNjYZ+04vn68E93vTKndcBf4JmEGuQFzuXvAm8if4P1HMV5n3BwZz1d6J6YGKbp
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L7KSnGASAUgTPLwhD/HvLg==
//pragma protect end_data_block
//pragma protect digest_block
8VZnDhHtC+Uqr3bipiiwbVqxO1U=
//pragma protect end_digest_block
//pragma protect end_protected


//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
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515V+5Xso72FipIBiEzqDg/rUT3GGR8W50dw9gd4++WdSDldeLL+7MJTKyoOxSh+
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0N1K7Ux2+jHd180YXAO+aQhx1kQiRuBeSasWhNatvSgPxivWJ+BP3Zk/JkifaIoR
Kg+XWdo3A3YzSGCCDBSbag==
//pragma protect end_key_block
//pragma protect digest_block
7HkkPzjj4KfGbdQvpN+onYkUc3Y=
//pragma protect end_digest_block
//pragma protect data_block
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sIaToAx6DwK3ul4jT5znpS0LzyFx+uDU/XEKOIBqKdkVtGp8vzpHyWzSH4hR/Xrl
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iXAhAHrPf0YnqQA0AqmBeI9QsxlCaxL4O7XcCvY0JsdUI8CL+aMjJfJXGJiYDE0h
neqNJd2qdrlmFLVq/3Fj/pVgDtY6d3opnUyaDwnenLiJUdF3cqOAjpGj5Am1dZsM
UyV+FVqpv/HIJq6DAUwyAbXSbSfwTFYe4WuUEjnjro69xQr467GYWCb7jRcHBXsg
ICvgVqfF7aV3w/lX7TpHQyHRI7PuSfIMJnMgMxA5R14kCaJ8gnYImsIIlgCCC+VP
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zskBxSIRx4Pgqkw4FJvmS+1CNp3um09EipNb3W18p4s=
//pragma protect end_data_block
//pragma protect digest_block
ufjESfjEyhxiHPCliZDKmztoS0g=
//pragma protect end_digest_block
//pragma protect end_protected


module `IP_MODULE_NAME(efx_mac1gbe) #(
   parameter FAMILY = "TRION",
   parameter VERSION = 32'h20,
   parameter RXFIFO_EN = 1,
   parameter RXFIFO_DTH = 2048,
   parameter TXFIFO_EN = 1,
   parameter TXFIFO_DTH = 2048,
   parameter PHY_INTF_MODE = 0,  
   parameter LOOPBACK_EN = 1'b0,
   parameter GMII_DW = PHY_INTF_MODE == 4 ? 16 : 8,
   parameter AXIS_DW = 8,  
   parameter APBIF = 0,
   parameter NO_PREAMBLE = 0,
   parameter INTER_PACKET_GAP = 6'd12,
   parameter MTU_FRAME_LENGTH = 16'd1518,
   parameter MAC_SOURCE_ADDRESS = 48'h0,
   parameter ENABLE_BROADCAST_FILTERING = 1'b1,
   parameter RGMII_RXC_EDGE = 1'b1,
   parameter RGMII_TXC_DLY = 1'b1,
   parameter PKT_CNT_MAX = 256, 
   parameter SIP600 = 0 
) (
   input                  tx_mac_aclk,
   output                 rx_mac_aclk,
   input                  mac_reset,   
   input                  proto_reset, 
   input                  tx_axis_clk,
   input [AXIS_DW-1:0]    tx_axis_mac_tdata,
   input                  tx_axis_mac_tvalid,
   input                  tx_axis_mac_tlast,
   input [AXIS_DW/8-1:0]  tx_axis_mac_tstrb,
   input                  tx_axis_mac_tuser,
   output                 tx_axis_mac_tready,
   input                  rx_axis_clk,
   output [AXIS_DW-1:0]   rx_axis_mac_tdata,
   output                 rx_axis_mac_tvalid,
   output                 rx_axis_mac_tlast,
   output [AXIS_DW/8-1:0] rx_axis_mac_tstrb,
   output                 rx_axis_mac_tuser,
   input                  rx_axis_mac_tready,
   input                  gm_rx_c,
   input  [GMII_DW-1:0]   gm_rx_d,
   input  [GMII_DW/8-1:0] gm_rx_dv,
   input  [GMII_DW/8-1:0] gm_rx_err,
   output                 gm_tx_c,
   output [GMII_DW-1:0]   gm_tx_d,
   output [GMII_DW/8-1:0] gm_tx_en,
   output [GMII_DW/8-1:0] gm_tx_err,
   output [3:0]           rgmii_txd_HI,
   output [3:0]           rgmii_txd_LO,
   output                 rgmii_tx_ctl_HI,
   output                 rgmii_tx_ctl_LO,
   output                 rgmii_txc_HI,
   output                 rgmii_txc_LO,
   input  [3:0]           rgmii_rxd_HI,
   input  [3:0]           rgmii_rxd_LO,
   input                  rgmii_rx_ctl_HI,
   input                  rgmii_rx_ctl_LO,
   input                  rgmii_rxc,
   input                  mii_txc,
   output [3:0]           mii_txd,
   output                 mii_tx_dv,
   output                 mii_tx_err,
   input                  mii_rxc,
   input  [3:0]           mii_rxd,
   input                  mii_rx_dv,
   input                  mii_rx_err,
   input                  rmii_clk_ref,
   output [1:0]           rmii_txd,
   output                 rmii_tx_en,
   input  [1:0]           rmii_rxd,
   input                  rmii_crs_dv,
   input                  rmii_rx_err,
   input  [9:0]           s_paddr,
   input  [31:0]          s_pwdata,
   input                  s_pwrite,
   input                  s_penable,
   input                  s_psel,
   output [31:0]          s_prdata,
   output                 s_pready,
   output                 s_perr,
   input                  s_axi_aclk,    
   input  [9:0]           s_axi_awaddr,  
   input                  s_axi_awvalid, 
   output                 s_axi_awready, 
   input  [31:0]          s_axi_wdata,   
   input                  s_axi_wvalid,  
   output                 s_axi_wready,  
   output [1:0]           s_axi_bresp,   
   output                 s_axi_bvalid,  
   input                  s_axi_bready,  
   input  [9:0]           s_axi_araddr,  
   input                  s_axi_arvalid, 
   output                 s_axi_arready, 
   output [1:0]           s_axi_rresp,   
   output [31:0]          s_axi_rdata,   
   output                 s_axi_rvalid,  
   input                  s_axi_rready,  
`ifdef ONCHIP_PHY
   input  logic           init_clk,
   input  logic           init_rst_n,
   input  logic           PMA_CMN_READY,
   input  logic           PMA_XCVR_PLLCLK_EN_ACK,
   input  logic [3:0]     PMA_XCVR_POWER_STATE_ACK,
   input  logic           PMA_RX_SIGNAL_DETECT,
   output logic           PMA_XCVR_PLLCLK_EN,
   output logic [3:0]     PMA_XCVR_POWER_STATE_REQ,
   output logic           phy_init_done,
`else
   output                 Mdo,   
   output                 MdoEn, 
   input                  Mdi,   
   output                 Mdc,   
`endif
   output [2:0]           eth_speed
);
`ifdef ONCHIP_PHY
//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
AMyoRL5/w7aGJMUAFjWdggMiBKf1mhnyB4tTNrQUAOHCO5ZmDsFpb964w4qkWZVN
XTiRjcc3GwM/Fmz7oO2RrXaSAbzLZGKR7DnzUuMenl8JrAwGEamBMGjpSL3aMEyl
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xGTO/3F/v5LdwzL2hgvz5A==
//pragma protect end_key_block
//pragma protect digest_block
GPFPDOqRYTtfroZsY3lH14yzT1E=
//pragma protect end_digest_block
//pragma protect data_block
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//pragma protect end_data_block
//pragma protect digest_block
gfSy+yjCs0cH8hBJH8nmuez3sig=
//pragma protect end_digest_block
//pragma protect end_protected


// Module: efx_pulse_sync
// Description:
//   Safely transfers a single-cycle pulse from a source clock domain to a
//   destination clock domain using a toggle-based synchronization scheme.
//
// ==========================================================================

module `IP_MODULE_NAME(efx_pulse_sync) #(
   parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
   parameter OFF_ASSERTION = 0
) (
   input  src_clk,      // Source clock (e.g., tx_axis_clk)
   input  src_reset,    // Reset for source domain
   input  pulse_in,     // Single-cycle pulse in src_clk domain

   input  dst_clk,      // Destination clock (e.g., tx_clk)
   input  dst_reset,    // Reset for destination domain
   output pulse_out     // Single-cycle pulse in dst_clk domain
);

// Toggle generation in source clock domain
reg toggle_src;

// Synchronizer flops in destination clock domain
wire toggle_sync;
reg  toggle_sync_r;

generate
   if (ACTIVE_LOW == 1) begin
      always @ (posedge src_clk or negedge src_reset) begin
         if (!src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

     `IP_MODULE_NAME(efx_asyncreg) #(
        .WIDTH         (1),
        .OFF_ASSERTION (OFF_ASSERTION)
     ) efx_asyncreg_toggle_src (
        .clk     (dst_clk),
        .reset_n (dst_reset),
        .d_i     (toggle_src),
        .d_o     (toggle_sync)
     );
      
      always @ (posedge dst_clk or negedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
   else begin
      always @ (posedge src_clk or posedge src_reset) begin
         if (src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH         (1),
         .ACTIVE_HIGH   (0),
         .OFF_ASSERTION (OFF_ASSERTION)
      ) efx_asyncreg_toggle_src (
         .clk     (dst_clk),
         .reset_n (dst_reset),
         .d_i     (toggle_src),
         .d_o     (toggle_sync)
      );
      
      always @ (posedge dst_clk or posedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
endgenerate

// Generate one-cycle pulse in destination domain
assign pulse_out = toggle_sync ^ toggle_sync_r;

endmodule



module `IP_MODULE_NAME(efx_data_pipeline)  #(
    parameter HBP = 1,
    parameter DATA_WIDTH = 256,
    parameter MUX_IN = 1
)(
  input               upstream_valid_i,
  output              upstream_ready_o,
  input      [DATA_WIDTH-1:0]   upstream_data_i,
  output              downstream_valid_o,
  input               downstream_ready_i,
  output     [DATA_WIDTH-1:0]   downstream_data_o,
  input               clk,
  input               resetn
);
//pragma protect begin_protected
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=CDS_KEY
//pragma protect key_method=RC5
//pragma protect key_block
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whq92/ag/nAdDF1Vy4sbDr5FINmqPPikptUUvL1vDUmBcBOK5GHbSA==
//pragma protect end_key_block
//pragma protect digest_block
MnZuDl/T4JMKytmOinMcApLLkiI=
//pragma protect end_digest_block
//pragma protect data_block
uSWIjUVRD9ulLt/eWaqhdxsq1An+eHPQBKJI0rkSzFsI3QY7wYW+FoTKIS2AB5qf
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K4vhL/IlI8Mj/z0kKlnD9A==
//pragma protect end_data_block
//pragma protect digest_block
/ZU5wr/v9FLKg6OANYaVJInQw6o=
//pragma protect end_digest_block
//pragma protect end_protected

`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME
