// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.288.2.10
// IP Version: 7.1
// =============================================================================

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//                                                                       
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//                                                                       
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.                                                
//
////////////////////////////////////////////////////////////////////////////////

`define IP_UUID _4c19f37180ff465ca20760e199a0613f
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module gTSE
(
    input mac_reset,
    input proto_reset,
    output rx_mac_aclk,
    input tx_mac_aclk,
    output [2:0] eth_speed,
    input rx_axis_clk,
    output rx_axis_mac_tuser,
    output rx_axis_mac_tlast,
    output rx_axis_mac_tvalid,
    input rx_axis_mac_tready,
    input tx_axis_clk,
    input tx_axis_mac_tvalid,
    input tx_axis_mac_tlast,
    input tx_axis_mac_tuser,
    output tx_axis_mac_tready,
    output [3:0] rgmii_txd_HI,
    output [3:0] rgmii_txd_LO,
    output rgmii_tx_ctl_HI,
    output rgmii_tx_ctl_LO,
    output rgmii_txc_HI,
    output rgmii_txc_LO,
    input [3:0] rgmii_rxd_HI,
    input [3:0] rgmii_rxd_LO,
    input rgmii_rx_ctl_HI,
    input rgmii_rx_ctl_LO,
    input rgmii_rxc,
    input s_axi_aclk,
    output [7:0] rx_axis_mac_tdata,
    input [7:0] tx_axis_mac_tdata,
    input [0:0] tx_axis_mac_tstrb,
    output [0:0] rx_axis_mac_tstrb,
    output MdoEn,
    output Mdo,
    input Mdi,
    output Mdc,
    input [9:0] s_axi_araddr,
    output s_axi_arready,
    input s_axi_arvalid,
    input [9:0] s_axi_awaddr,
    output s_axi_awready,
    input s_axi_awvalid,
    input s_axi_bready,
    output [1:0] s_axi_bresp,
    output s_axi_bvalid,
    output [31:0] s_axi_rdata,
    input s_axi_rready,
    output [1:0] s_axi_rresp,
    output s_axi_rvalid,
    input [31:0] s_axi_wdata,
    output s_axi_wready,
    input s_axi_wvalid
);
`IP_MODULE_NAME(efx_mac1gbe)
#(
    .VERSION (16),
    .TXFIFO_EN (1'b1),
    .RXFIFO_EN (1'b1),
    .TXFIFO_DTH (4096),
    .RXFIFO_DTH (4096),
    .PHY_INTF_MODE (0),
    .AXIS_DW (8),
    .RGMII_RXC_EDGE (1'b1),
    .RGMII_TXC_DLY (1'b1),
    .INTER_PACKET_GAP (6'd12),
    .MTU_FRAME_LENGTH (16'd1518),
    .MAC_SOURCE_ADDRESS (48'd0),
    .ENABLE_BROADCAST_FILTERING (1'b1),
    .LOOPBACK_EN (1'b1),
    .APBIF (1'b0),
    .FAMILY ("TITANIUM")
)
u_efx_mac1gbe
(
    .mac_reset ( mac_reset ),
    .proto_reset ( proto_reset ),
    .rx_mac_aclk ( rx_mac_aclk ),
    .tx_mac_aclk ( tx_mac_aclk ),
    .eth_speed ( eth_speed ),
    .rx_axis_clk ( rx_axis_clk ),
    .rx_axis_mac_tuser ( rx_axis_mac_tuser ),
    .rx_axis_mac_tlast ( rx_axis_mac_tlast ),
    .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ),
    .rx_axis_mac_tready ( rx_axis_mac_tready ),
    .tx_axis_clk ( tx_axis_clk ),
    .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ),
    .tx_axis_mac_tlast ( tx_axis_mac_tlast ),
    .tx_axis_mac_tuser ( tx_axis_mac_tuser ),
    .tx_axis_mac_tready ( tx_axis_mac_tready ),
    .rgmii_txd_HI ( rgmii_txd_HI ),
    .rgmii_txd_LO ( rgmii_txd_LO ),
    .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
    .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
    .rgmii_txc_HI ( rgmii_txc_HI ),
    .rgmii_txc_LO ( rgmii_txc_LO ),
    .rgmii_rxd_HI ( rgmii_rxd_HI ),
    .rgmii_rxd_LO ( rgmii_rxd_LO ),
    .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
    .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
    .rgmii_rxc ( rgmii_rxc ),
    .s_axi_aclk ( s_axi_aclk ),
    .rx_axis_mac_tdata ( rx_axis_mac_tdata ),
    .tx_axis_mac_tdata ( tx_axis_mac_tdata ),
    .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ),
    .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ),
    .MdoEn ( MdoEn ),
    .Mdo ( Mdo ),
    .Mdi ( Mdi ),
    .Mdc ( Mdc ),
    .s_axi_araddr ( s_axi_araddr ),
    .s_axi_arready ( s_axi_arready ),
    .s_axi_arvalid ( s_axi_arvalid ),
    .s_axi_awaddr ( s_axi_awaddr ),
    .s_axi_awready ( s_axi_awready ),
    .s_axi_awvalid ( s_axi_awvalid ),
    .s_axi_bready ( s_axi_bready ),
    .s_axi_bresp ( s_axi_bresp ),
    .s_axi_bvalid ( s_axi_bvalid ),
    .s_axi_rdata ( s_axi_rdata ),
    .s_axi_rready ( s_axi_rready ),
    .s_axi_rresp ( s_axi_rresp ),
    .s_axi_rvalid ( s_axi_rvalid ),
    .s_axi_wdata ( s_axi_wdata ),
    .s_axi_wready ( s_axi_wready ),
    .s_axi_wvalid ( s_axi_wvalid )
);
endmodule

/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_top) # (
    parameter FAMILY             = "TRION",       // New Param
    parameter SYNC_CLK           = 0,
    parameter BYPASS_RESET_SYNC  = 0,             // New Param
    parameter SYNC_STAGE         = 2,             // New Param
    parameter MODE               = "STANDARD",
    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
    parameter OPTIONAL_FLAGS     = 1,             // Reverted
    parameter OUTPUT_REG         = 0,
    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_FULL_ASSERT   = 27,
    parameter PROG_FULL_NEGATE   = 23,
    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_EMPTY_ASSERT  = 5,
    parameter PROG_EMPTY_NEGATE  = 7,
    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter WADDR_WIDTH        = depth2width(DEPTH),
    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
    parameter ENDIANESS		      = 0,
    parameter OVERFLOW_PROTECT   = 1,
    parameter UNDERFLOW_PROTECT  = 1,
    parameter RAM_STYLE          = "block_ram"

)(
    input  wire                   a_rst_i,
    input  wire                   a_wr_rst_i,
    input  wire                   a_rd_rst_i,
    input  wire                   clk_i,
    input  wire                   wr_clk_i,
    input  wire                   rd_clk_i,
    input  wire                   wr_en_i,
    input  wire                   rd_en_i,
    input  wire [DATA_WIDTH-1:0]  wdata,
    output wire                   almost_full_o,
    output wire                   prog_full_o,
    output wire                   full_o,
    output wire                   overflow_o,
    output wire                   wr_ack_o,
    output wire [WADDR_WIDTH :0]  datacount_o,
    output wire [WADDR_WIDTH :0]  wr_datacount_o,
    output wire                   empty_o,
    output wire                   almost_empty_o,
    output wire                   prog_empty_o,
    output wire                   underflow_o,
    output wire                   rd_valid_o,
    output wire [RDATA_WIDTH-1:0] rdata,
    output wire [RADDR_WIDTH :0]  rd_datacount_o,
    output wire                   rst_busy
); 

localparam WR_DEPTH      = DEPTH;
localparam WDATA_WIDTH   = DATA_WIDTH;
localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           

wire                   wr_rst_int;
wire                   rd_rst_int;
wire                   wr_en_int;
wire                   rd_en_int;
wire [WADDR_WIDTH-1:0] waddr;
wire [RADDR_WIDTH-1:0] raddr;
wire                   wr_clk_int;
wire                   rd_clk_int;
wire [WADDR_WIDTH :0]  wr_datacount_int;
wire [RADDR_WIDTH :0]  rd_datacount_int;

generate
    if (ASYM_WIDTH_RATIO == 4) begin
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
            assign datacount_o    = wr_datacount_int;
            assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}};
            assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}};
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
            assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
            assign wr_datacount_o = wr_datacount_int;
            assign rd_datacount_o = rd_datacount_int;
        end
    end
    else begin
        assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
        assign wr_datacount_o = wr_datacount_int;
        assign rd_datacount_o = rd_datacount_int;
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
        end
    end    

    if (!SYNC_CLK) begin
        //(* async_reg = "true" *) reg [1:0] wr_rst;
        //(* async_reg = "true" *) reg [1:0] rd_rst;
        //
        //always @ (posedge wr_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        wr_rst <= 2'b11;
        //    else 
        //        wr_rst <= {wr_rst[0],1'b0};            
        //end
        //
        //always @ (posedge rd_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        rd_rst <= 2'b11;
        //    else 
        //        rd_rst <= {rd_rst[0],1'b0};            
        //end
        

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_wr_rst_i;
            assign rd_rst_int = a_rd_rst_i; 
            assign rst_busy   = 1'b0;
        end 
        else begin
            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_wr_rst (
               .clk   (wr_clk_int),
               .reset (a_rst_i),
               .d_o   (wr_rst_int)
            );

            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_rd_rst (
               .clk   (rd_clk_int),
               .reset (a_rst_i),
               .d_o   (rd_rst_int)
            );
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end

    end
    else begin
        //(* async_reg = "true" *) reg [1:0] a_rst;
        //
        //always @ (posedge clk_i or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        a_rst <= 2'b11;
        //    else 
        //        a_rst <= {a_rst[0],1'b0};            
        //end
        wire   a_rst;

        `IP_MODULE_NAME(efx_resetsync) #(
           .ACTIVE_LOW (0)
        ) efx_resetsync_a_rst (
           .clk   (clk_i),
           .reset (a_rst_i),
           .d_o   (a_rst)
        );

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_rst_i;
            assign rd_rst_int = a_rst_i;
            assign rst_busy   = 1'b0;
        end
        else begin
            assign wr_rst_int = a_rst;
            assign rd_rst_int = a_rst;   
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end
    end 
endgenerate

`IP_MODULE_NAME(efx_fifo_ram) # (
    .FAMILY        (FAMILY),
    .WR_DEPTH      (WR_DEPTH),
    .RD_DEPTH      (RD_DEPTH),
    .WDATA_WIDTH   (WDATA_WIDTH),
    .RDATA_WIDTH   (RDATA_WIDTH),
    .WADDR_WIDTH   (WADDR_WIDTH),
    .RADDR_WIDTH   (RADDR_WIDTH),
    .OUTPUT_REG    (OUTPUT_REG),
    .RAM_MUX_RATIO (RAM_MUX_RATIO),
    .ENDIANESS	    (ENDIANESS),
    .RAM_STYLE     (RAM_STYLE)
) xefx_fifo_ram (
    .wdata (wdata), 
    .waddr (waddr),
    .raddr (raddr), 
    .we    (wr_en_int), 
    .re    (rd_en_int),
    .wclk  (wr_clk_int),
    .rclk  (rd_clk_int),
    .rdata (rdata)
);

`IP_MODULE_NAME(efx_fifo_ctl) # (
    .SYNC_CLK           (SYNC_CLK),
    .SYNC_STAGE         (SYNC_STAGE),
    .MODE               (MODE),
    .WR_DEPTH           (WR_DEPTH),
    .WADDR_WIDTH        (WADDR_WIDTH),
    .RADDR_WIDTH        (RADDR_WIDTH),
    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
    .PIPELINE_REG       (PIPELINE_REG),
    .ALMOST_FLAG        (ALMOST_FLAG),
    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
    .OUTPUT_REG         (OUTPUT_REG),
    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG),
    .OVERFLOW_PROTECT   (OVERFLOW_PROTECT),
    .UNDERFLOW_PROTECT  (UNDERFLOW_PROTECT)
) xefx_fifo_ctl (
    .wr_rst          (wr_rst_int),
    .rd_rst          (rd_rst_int),
    .wclk            (wr_clk_int),
    .rclk            (rd_clk_int),
    .we              (wr_en_i),
    .re              (rd_en_i),
    .wr_full         (full_o),
    .wr_ack          (wr_ack_o),
    .rd_empty        (empty_o),
    .wr_almost_full  (almost_full_o),
    .rd_almost_empty (almost_empty_o),
    .wr_prog_full    (prog_full_o),
    .rd_prog_empty   (prog_empty_o),
    .wr_en_int       (wr_en_int),
    .rd_en_int       (rd_en_int),
    .waddr           (waddr),
    .raddr           (raddr),
    .wr_datacount    (wr_datacount_int),
    .rd_datacount    (rd_datacount_int),
    .rd_vld          (rd_valid_o),
    .wr_overflow     (overflow_o),
    .rd_underflow    (underflow_o)
);

function integer depth2width;
input [31:0] depth;
begin : fnDepth2Width
    if (depth > 1) begin
        depth = depth - 1;
        for (depth2width=0; depth>0; depth2width = depth2width + 1)
            depth = depth>>1;
        end
    else
       depth2width = 0;
end
endfunction 

function integer width2depth;
input [31:0] width;
begin : fnWidth2Depth
    width2depth = width**2;
end
endfunction

function integer rdwidthcompute;
input [31:0] asym_option;
input [31:0] wr_width;
begin : RdWidthCompute
    rdwidthcompute = (asym_option==0)? wr_width/16 :
                     (asym_option==1)? wr_width/8  :
                     (asym_option==2)? wr_width/4  :
                     (asym_option==3)? wr_width/2  :
                     (asym_option==4)? wr_width/1  :
                     (asym_option==5)? wr_width*2  :
                     (asym_option==6)? wr_width*4  :
                     (asym_option==7)? wr_width*8  :
                     (asym_option==8)? wr_width*16 : wr_width/1;
end
endfunction

function integer rddepthcompute;
input [31:0] wr_depth;
input [31:0] wr_width;
input [31:0] rd_width;
begin : RdDepthCompute
    rddepthcompute = (wr_depth * wr_width) / rd_width;
end
endfunction

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ram) #(
    parameter FAMILY        = "TRION",
    parameter WR_DEPTH      = 512,
    parameter RD_DEPTH      = 512,
    parameter WDATA_WIDTH   = 8,
    parameter RDATA_WIDTH   = 8,
    parameter WADDR_WIDTH   = 9,
    parameter RADDR_WIDTH   = 9,
    parameter OUTPUT_REG    = 1,
    parameter RAM_MUX_RATIO = 4,
    parameter ENDIANESS 	 = 0, //0: Big endian (default)   1: Little endian 
    parameter RAM_STYLE     = "block_ram"
) (
    input  wire                     wclk,
    input  wire                     rclk,
    input  wire                     we,
    input  wire                     re,
    input  wire [(WDATA_WIDTH-1):0] wdata,
    input  wire [(WADDR_WIDTH-1):0] waddr,
    input  wire [(RADDR_WIDTH-1):0] raddr,
    output wire [(RDATA_WIDTH-1):0] rdata
);

localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";

(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
reg [RDATA_WIDTH-1:0]    r_rdata_1P;
reg [RDATA_WIDTH-1:0]    r_rdata_2P;

wire                     re_int;

generate
    if (FAMILY == "TRION") begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                end
                r_rdata_2P <= r_rdata_1P;
            end
        end
        
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            if (ENDIANESS == 0) begin 
            	integer i;
            	always @ (posedge wclk) begin
                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                    end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                	end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
        end
        
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
            //integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end 
            end
            else begin //endianess == 1
            	always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end
            end
        end
        if (OUTPUT_REG) begin
            assign re_int = re;
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end
    end
    else begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                    r_rdata_2P <= r_rdata_1P;
                end
            end
        end 
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            //integer i;
            if (ENDIANESS == 0) begin
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
            
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
        end
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
        	//integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
            
            else begin //endianess ==1
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
        end
        // NIC
        //if (MODE == "STANDARD") begin     
        //    if (OUTPUT_REG) begin
        //        reg re_r;
        //        always @ (posedge rclk) begin
        //            re_r <= re;
        //        end
        //        assign re_int = re | re_r;        
        //        assign rdata  = r_rdata_2P;            
        //    end
        //    else begin
        //        assign re_int = re;
        //        assign rdata  = r_rdata_1P;
        //    end
        //end
        //else begin
        //    assign re_int = re;
        //    assign rdata  = r_rdata_1P;
        //end    
        if (OUTPUT_REG) begin
            reg re_r;
            always @ (posedge rclk) begin
                re_r <= re;
            end
            assign re_int = re | re_r;        
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end    
    end
endgenerate

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   gray2bin.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Gray to Binary Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_gray2bin)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] bin_o,
 // input
 input [WIDTH-1:0] gray_i);

//---------------------------------------------------------------------
// Recursive Module
// Description: reduction xor
generate
   if (WIDTH > 1) begin
      wire [1:0] bin_1;
      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
      if (WIDTH == 2) begin
	 assign bin_o = bin_1;
      end
      else begin
	 assign bin_o[WIDTH-1] = bin_1[1];
	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
      end
   end
   else /* if (WIDTH == 1) */
     assign bin_o = gray_i;
endgenerate
   
endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   pipe_reg.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Parallel Pipelining Shift Register
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_datasync) #(
    parameter STAGE = 32,
    parameter WIDTH = 4
) (
 input  wire             clk_i,
 input  wire [WIDTH-1:0] d_i,
 output wire [WIDTH-1:0] d_o
);

(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
integer i;

always @(posedge clk_i) begin
  for (i=STAGE-1; i>0; i = i - 1) begin
    pipe_reg[i] <= pipe_reg[i-1];
  end
  pipe_reg[0] <= d_i;
end
assign d_o = pipe_reg[STAGE-1];
   

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_resetsync) #(
    parameter ASYNC_STAGE = 2,
    parameter ACTIVE_LOW = 1
) (
    input  wire             clk,
    input  wire             reset,
    output wire             d_o
);


generate
   if (ACTIVE_LOW == 1) begin: active_low
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (1),
         .RST_VALUE  (0)
      ) efx_resetsync_active_low (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b1),
         .d_o     (d_o)
      );
   end
   else begin: active_high
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (0),
         .RST_VALUE  (1)
      ) efx_resetsync_active_high (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b0),
         .d_o     (d_o)
      );
   end
endgenerate

endmodule



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_asyncreg) #(
    parameter ASYNC_STAGE = 2,
    parameter WIDTH = 4,
    parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
    parameter RST_VALUE = 0,
    parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance 
) (
    input  wire             clk,
    input  wire             reset_n,
    input  wire [WIDTH-1:0] d_i,
    output wire [WIDTH-1:0] d_o
);










`pragma protect begin_protected
`pragma protect version = 1
`pragma protect author = "author-a" , author_info = "author-a-details"
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V
o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE
El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY
kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc
/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1
uYJaS5tuGEuFInBHa7oO8g==
`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3
fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa
rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq
PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL
DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w
K3OoKmk3zFeArSsql8B4/Q==
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M
GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l
6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI=
`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf
RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk
1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw
Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz
eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0
2HflB1HYKxojQCcZU7qUgQ==
`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx
Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB
rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr
XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD
e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod
B2Zpo2FQ//YDRSAaEa9ksQ==
`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze
vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2
ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2
06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP
fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN
ZoPzFCMjGk5ZmMyIlytNCw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 )
`pragma protect data_block
[encoded data, 5785 characters]
Ei7EaFpheCmlTJyxUg8TdA==
`pragma protect end_protected


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ctl) # (
    parameter SYNC_CLK           = 1,
    parameter SYNC_STAGE         = 2,
    parameter MODE               = "STANDARD",
    parameter WR_DEPTH           = 512,
    parameter WADDR_WIDTH        = 9,
    parameter RADDR_WIDTH        = 9,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter RAM_MUX_RATIO      = 1,
    parameter PIPELINE_REG       = 1,
    parameter ALMOST_FLAG        = 1,
    parameter PROGRAMMABLE_FULL  = "NONE",
    parameter PROG_FULL_ASSERT   = 0,
    parameter PROG_FULL_NEGATE   = 0,
    parameter PROGRAMMABLE_EMPTY = "NONE",
    parameter PROG_EMPTY_ASSERT  = 0,
    parameter PROG_EMPTY_NEGATE  = 0,
    parameter OUTPUT_REG         = 0,
    parameter HANDSHAKE_FLAG     = 1, 
    parameter OVERFLOW_PROTECT   = 0,
    parameter UNDERFLOW_PROTECT  = 0
)(
    input   wire                   wr_rst,
    input   wire                   rd_rst,
    input   wire                   wclk,
    input   wire                   rclk,
    input   wire                   we,
    input   wire                   re,
    output  wire                   wr_full,
    output  reg                    wr_ack,
    output  wire                   wr_almost_full,
    output  wire                   rd_empty,
    output  wire                   rd_almost_empty,
    output  wire                   wr_prog_full,
    output  wire                   rd_prog_empty,
    output  wire                   wr_en_int,
    output  wire                   rd_en_int,
    output  wire [WADDR_WIDTH-1:0] waddr,
    output  wire [RADDR_WIDTH-1:0] raddr,
    output  wire [WADDR_WIDTH:0]   wr_datacount,
    output  wire [RADDR_WIDTH:0]   rd_datacount,
    output  wire                   rd_vld,
    output  reg                    wr_overflow,
    output  reg                    rd_underflow
);

reg  [WADDR_WIDTH:0] waddr_cntr;
reg  [WADDR_WIDTH:0] waddr_cntr_r;
reg  [RADDR_WIDTH:0] raddr_cntr;
reg                  rd_valid;

wire [WADDR_WIDTH:0] waddr_int;
wire [RADDR_WIDTH:0] raddr_int;
wire                 rd_empty_int;
wire [WADDR_WIDTH:0] wr_datacount_int;
wire [RADDR_WIDTH:0] rd_datacount_int;

assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
// NIC
wire [RADDR_WIDTH:0] ram_raddr;
assign raddr     = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0];
//assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
//assign wr_en_int = we & ~wr_full;
assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we;

assign wr_datacount  = wr_datacount_int;
assign rd_datacount  = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int;


generate
    if (MODE == "FWFT") begin    
        // NIC
        //assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
        //assign rd_empty      = rd_empty_fwft;

        assign rd_en_int     = 1'b1;
        //assign rd_empty      = rd_empty_int;
        
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        init_set <= 1'b1;
        //    end
        //    else if (~init_set & rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //    else if (~rd_empty_int) begin
        //        init_set <= 1'b0;            
        //    end
        //    else if (rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //end
        // NIC 
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        rd_empty_fwft <= 1'b1;
        //    end
        //    else if (rd_en_int) begin
        //        rd_empty_fwft <= 1'b0;            
        //    end
        //    else if (re) begin
        //        rd_empty_fwft <= 1'b1;            
        //    end
        //end          
        
        //if (FAMILY == "TRION") begin
        if (OUTPUT_REG) begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid <= 1'b0;
                end
                else begin
                    rd_valid <= ~rd_empty;
                end
            end
            assign rd_vld = rd_valid;                
        end    
        else begin
            assign rd_vld = ~rd_empty;                
        end
        
        assign rd_empty = rd_empty_int;
    end
    else begin
        assign rd_en_int     = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re;
        assign rd_empty      = rd_empty_int;
        
        if (OUTPUT_REG) begin
            reg rd_valid_r;
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid_r <= 'h0;
                    rd_valid   <= 'h0;
                end
                else begin
                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
                end
            end
            assign rd_vld = rd_valid;            
        end
        else begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid  <= 'h0;
                end
                else begin
                    rd_valid <= rd_en_int;
                end
            end
            assign rd_vld = rd_valid;
        end
    end
    
    if (ALMOST_FLAG) begin
        assign wr_almost_full   = wr_datacount >= WR_DEPTH-1;
        assign rd_almost_empty  = rd_datacount <= 'd1;
    end
    else begin
        assign wr_almost_full   = 1'b0;
        assign rd_almost_empty  = 1'b0;        
    end
    
    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end  
    end
    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   

        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end              
    end
    else begin
        assign wr_prog_full  = 1'b0; 
    end
        
    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end
    end
    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end  
    end
    else begin
        assign rd_prog_empty  = 1'b0; 
    end
    
    if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_ack <= 1'b0;
            end
            else begin
                // NIC
                //wr_ack <= wr_en_int & ~wr_overflow;
                wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int;
            end
        end
    end

    if (OVERFLOW_PROTECT) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else if (we && wr_full) begin
                wr_overflow <= 1'b1;
            end
            else begin
                wr_overflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else begin
                wr_overflow <= we && wr_full ? 1'b1 : wr_overflow;
            end
        end
    end

    if (UNDERFLOW_PROTECT) begin     
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else if (re && rd_empty) begin
                rd_underflow <= 1'b1;
            end
            else begin
                rd_underflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else begin
                rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow;
            end
        end
    end
    
    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
    
    if (ASYM_WIDTH_RATIO < 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
    end
    // NIC
    else if (ASYM_WIDTH_RATIO == 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - raddr_int;
        assign rd_datacount_int = waddr_int - raddr_cntr;
    end
    else begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
        // NIC
        //assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr;
    end
endgenerate

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr   <= 'h0;
    end
    else if (wr_en_int) begin
        waddr_cntr   <= waddr_cntr + 1'b1;
    end
end

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr_r  <= 'h0;
    end
    else begin
        waddr_cntr_r  <= waddr_cntr;
    end
end

always @ (posedge rclk or posedge rd_rst) begin
    if (rd_rst) begin
        raddr_cntr   <= 'h0;
    end
    // NIC
    //else if (rd_en_int) begin
    else begin
        //raddr_cntr   <= raddr_cntr + 1'b1;
        //raddr_cntr   <= raddr_cntr + (re & ~rd_empty_int);
        raddr_cntr   <= ram_raddr;
    end
end
// NIC
assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re);


generate
    if (SYNC_CLK) begin : sync_clk
       if (MODE == "FWFT") begin
          assign waddr_int = waddr_cntr_r;
          assign raddr_int        = raddr_cntr;
       end
       else begin
          assign waddr_int        = waddr_cntr;
          assign raddr_int        = raddr_cntr;
       end
    end
    else begin : async_clk
        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
        
        wire [RADDR_WIDTH:0] raddr_cntr_gry;
        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
        wire [WADDR_WIDTH:0] waddr_cntr_gry;
        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;

        if (PIPELINE_REG) begin
            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
        
            assign waddr_int        = waddr_cntr_sync_g2b_r;
            assign raddr_int        = raddr_cntr_sync_g2b_r;
            
            always @ (posedge wclk or posedge wr_rst) begin
                if (wr_rst) begin
                    raddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
                end
            end
            
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    waddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
                end
            end
        end
        else begin
            assign waddr_int        = waddr_cntr_sync_g2b;
            assign raddr_int        = raddr_cntr_sync_g2b;        
        end
      
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                raddr_cntr_gry_r <= 'h0;
            end
            else begin
                raddr_cntr_gry_r <= raddr_cntr_gry;
            end
        end
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_bin2gray    (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync   (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                waddr_cntr_gry_r <= 'h0;
            end
            else begin
                waddr_cntr_gry_r <= waddr_cntr_gry;
            end
        end        
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        

    end
endgenerate
endmodule


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   bin2gray.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Binary to Gray Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_bin2gray)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] gray_o,
 // input
 input [WIDTH-1:0] bin_i
 );

//---------------------------------------------------------------------
// Function :   bit_xor
// Description: reduction xor
function bit_xor (
  input [31:0] nex_bit,
  input [31:0] curr_bit,
  input [WIDTH-1:0] xor_in);
  begin : fn_bit_xor
    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
  end
endfunction

// Convert Binary to Gray, bit by bit
generate 
begin
  genvar bit_idx;
  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
  end
  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
end
endgenerate

endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
ah1CSP63MUmdoRE9KU/7qpW2mCUqZialbS7PMODpI5X3vEXsLaXDCKMwJ5XcKtMy
EIWdxIcdTHeEDiy9eQJ1S6CzeEtgqXJMVgxfPaErAghPwnMjNBMF6NyW3amjI80j
IK4Q0hvXX2CA7yAajPIFtWxKeCSCDkhFmgUTKFi9bnG5aNnMLN+6cIOabVJrl+AJ
hNkBxRJ2vrtVXbudId8+sn3kyglN4GE6ar9iXv81sZ81Y8Tyrcchu7B/uWvEYDjM
p4YgaPR8upa6DcHL7sHcv9zw9Ir/vjdD9/L75EElxWPgzlSMQHARtQ2bvkzdayxb
JmqVlrHqI8XXqzSddy8vAA==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8512 )
`pragma protect data_block
[encoded data, 11505 characters]
TofYyNjGyhFCZZt3+S+b6g==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
GqF8fCMCqX9cvfEFdHCUoOAphWf+efs4UveHi+vbq3T2X1Zxa6jJmB2i1HhKawNU
6qKVHV5bCrc5Wei/OmnnPkXMuLZIjVaGylQY6COudDNU68V7mYJG9CKXxhzyMUpc
Iy7adLz4sIeQth0v9LoFEipBz7q7UPPzu+YhHXW/QB3PIQx7yvf1ByHMczOaqA5o
QK/SgoYgw1nItbJ3vxlx+pueLJzlXhjQRlf3peFA06PF3XQk3/xVVP72t9SCdHWO
tsNfffCgrxsXaXqV6IUhAwJX8y1yhJUEfCDS9DiEZP3U4bfZcgNJtzQfjaVz073h
zvbvtlNgxOtw1SlR1dT0fw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 432 )
`pragma protect data_block
U7QRtGq/G8+nBIV5ojQNU45u3qkLJd45OqJWleyUjhcfNZoOYC+zseMBjpuXowB5
SeceD/sm/Jn21y7gT6j50503tgbbEsek0lXOWpx0coxe/cYDiGFCzhLodvbgCser
/neCuuXDaLvEN9S4c8pfP2i5+qcIMo52NONOIXuGqAaIuiPeeOv1XEYTr0IVI/qK
mdJlyWDvuaaAfacIVCRh1So/g/jW4Xm1HoDy0gsSJiuLvJTXt/P0ZCHzyr93EnBP
2RI6RDulUCfh5XAi7G/jwnT7PcO86ZQCmpKyndujBVrlW0RbYyR5KDUKKR4ncakH
cLZqScz+VabSZaSzygIv+1ir9KoPX5ChDqdQedWru1Bn91X6/7vNImOeVIgeWYv/
bdUFpYoVL/InbDtBQm1wvT+jmbOZPePzOwBrnCZAafBrApuPj2XQ5u23XqOCuG3H
oQaS4N9mgH/5F0wzQ/HzGBAJ7bw5rw/FuWRGNi48xDuBEt704i2H6gYM/aakqAU9
dsczrg/5zjz9m2X9Y2IO1l/xD86qyG6yuDce6c6gZYiMnBr3WnsHpHH4k7xUHTT3
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
NMJzeJcTsA8NtSPvBrIMXiRzk2+AEhtFj0ikM/FX3JZpQ4bP67J184nC8s+YQCx4
9sYWVtmnaSqePX2CL5mZ+aWIcsSqui2u73d/Bg+gzDtRmc4ATUuTWZv6/ZxhJ/5Z
u8B9L/ZvnBUuVSsyw0YVzE+XsUr0eXdh4Wg9xrR56a5C9tmqsVLT8AlEGAUDw4do
KDYC96nYXf/BEnphxyALqmrrHhzfASd/9GWnTl5tqi6eXo5d/0GnAg/TumQB9VtC
qzB2XmUFsov3D71Vk5rsfyMzlPQTKeY3gOZaSWhORjUs4q4Sc3PwiIsk6IfvDPdO
opyDuRj3IOUtvCE9y6XKfg==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6192 )
`pragma protect data_block
[encoded data, 8385 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
C+BVml/KQ8QAs+EWMqZgQUmxQ/16vMdYR8KdOJPROqxy/2R4KpsrucSPGrri3HB4
5cov4xTwlRrM0dVRTSy+IpnCNuCnG2GaPPZtEEtppsdZsawMQHHeny+aaAH8QWd/
P7xzXIpnkSehz3uCwjoRL5NvWWs5wrbBgpmkShYE4g8GrBceK4K3q0QHmWlo6biB
SkKv3keLl2LvqKRFsyI887loII5GMe7kOqUaT2UTX04i9pHvTYrmM1XPvL0/Z9e9
GeIJ0s6+ss+nZ/KRs2vD5iNWzBNR79Jb4/Hm+jPkUk90Ye/pb/zK3zbqaPGcFRbs
27BwV2nodZkA3Tx3XwynxA==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1152 )
`pragma protect data_block
DMuRrHGWbQdSTzf44BjqEweUP5/eFSF6jxJ15kKaS7oSO+bqyHLEBGXIth8bUjpY
4E3Tr1QTgQrV0ILL34icSd5LDGEA9lZTGooYF01Nqt7ydPZxvELA+XmXGEzFvW7e
DjX/FhycmD2GOxNdXfM1pXMIH54NYa/r/KDMosYS4oFmfzKJ5Rwu6A3rY57txwnA
aAwTTd+al4fGQdgydcHAZ1lGRYQr0VCFXfp9fTVYbQnH4Q2w+K2vp+YLharoxhXE
3krDYYXB7guER+j7nqNxl+myfsa5SZnaCwmZ77Y18PJoQ6vkVfBtw8zJ3pbGELvm
jGClvY9O/Zx5L8B0zCXh8jqEVYKkD8b6uG8alk1LddR/7OgIne8YDNvNeOluMkk1
X6DZNT5TmklsDcbt76KRimy844HtLhu/2K8RN8WBCaxNaJux1/+FjgmbyTx6mov/
eXPcDxHJWEsJsOYetGDv4gxFqPjO3n7FQMjN+1PXrVItAeke2zEUDEJSqejFQVaL
H0epnzxky8qeiy0IpJaECJGlinhs4NGARrxq9HRvjJGRRxLSaZ0zXt+kQt2t5iFc
i8OHCCw8dXWdKSlncq0tz6ddsu+SMvqmFIhayQXX0p4zgF6ngeE7mXfTBZJOp097
F8saaXCdDN+/RHPCoHeWzqeYSs/agnKbUUm8QhneLhr2R1BkxFm5YWtWcCYrZAUf
eqKjwuZKc/nhcEB4FnL/0Q8PlbTaNVin3npB/HRh0xZQm52SXu2x077O5pQT5WMC
M0LvIKulm+oVjw1Wmy0z9++T9Otyo+fF6hr+AtTzxj0TQwBmrlQZuOGkxRE/RUMf
z2DHZBpOC2LZGubhR26aJINPuX5lsV5hDuFGzzrOCyrEXFzV2cClku+gw+5cQAVd
43AgHBzNRQ5TXTXGPeCRjqZ9uq4iV5yrotjxE16Q/s+dB+6TuDyb7XpE6IjZBBAs
aYMAe8NbNZJ3FCcc8UbZX0BzA0JxGg+1L92bJ3fZlWAffpYDLX9h1ml2s9jjifEO
MDbmQX1b1QlDK2+XKEwLuX2/X6RFbY6JImgWGwB7RSS0/Lc+SE7YZQVbu0EoRMFl
B9WDj/iq0Ft+WJi3lW6IGTqYyGEZP4VkTqziKT350uKlIJZDweyR4Phez5+CJEDi
UgaeHwx5Y4HoLLvnJ2woS0nQjHnhVakiX01mnyfw2hkK0ybQBezEityyiSn+y7Hr
BtVC0IgsKJrN0oI6nQIIcw/AdonNmst88lfQRfpbs6psEYWo3C0d1OpJH6fypqdi
Cb3lxa1E14r1Z+80l2KaFP1E1Zy2YW0+OUg8IvXaLSyI6sBDi4HgscpjQhp4sc4Z
LpIz1mUBw9CNvB49cS7DHQxcL8n1WrXkQPhKq4vQxxECLJx0fAdrV2uUaVQnkQuN
Jju6Lp8S2hndlz5HdNfG2Q5TVkyb3Kc4FclA3RVBnXNvXroXbqeV2btnoMpyoGWJ
2hjBDvOI+6dwIcIhP0hXf/PR2tobPwsvQnZkLm2X2WVNQZachyyzvZz4q9q8jqEK
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
cLVeskjs110eTOqMsYncgUFfySXVoW4d6tb3cJlwOuYd6PEAZ6lxk7niwBoWi2Mt
8PXpt8sdYQGb5VTj+VswNd6k0HrGDFwR6J4y6ctrpSGGVdj0m/oXdUSBRZezKQc/
BMPVF32V2D+34NRif2oK0xSkguNq4WVsv1XqLapwafiuD8CIIh8q96E6ZyY8wvce
Io42sMnD7EnRbn6bENS1swM9hMftXg/MNm6yhKABn6QC71vE/EeqS/I0bDGwXqkH
Mq0OG9wUmE3YxsD3bHmI3D8iJar68Q6+upNFx/PNLxr0BSHvAMk1g8NT5XnxQXoM
35rZ1GU0MRkDPnVAYt7uMw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8208 )
`pragma protect data_block
[encoded data, 11115 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
Mx/CyR4oJ7UnPDvtA3BX4FDIIZJs4R3SDfnkQvx9oCzIiC8BFmOAAos2VSDBCELG
ADRD3CZLEIDfw1uFvu3m3XuwwHbRU0vxmVOzyBzMS7l+1WdAsowJ1t8fsjLxtcRU
GTCyFC/FKyp0BY5Gf1lWpPsikhMkJQNvOoMt5yb5Kc7HQ9AXqOut+35o3uUyGPkC
veBF4ZGCgHN3krTe2j4QGdErqAmlyNrOhbD2RzYjNVY4xRfNC+BcQ+k9tojE/Y6W
t3rRrxMwU0wYU0zQCIO3UmhOxa70JzbFqwxIcRfD9pEJ2YFHVd8z2WTcO6uUDbKy
EOBMff3t5I1hakBI5vHy9g==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1680 )
`pragma protect data_block
QECkuHBFgKBJ4Uio9zpXUwQRsh5ehfbm/UPw4cOJqbrXejS1+/zkt4jBjfQlD1te
heijPANaMsPScnFqCs0CXPt27CM5rPMrcKq0deGx2f7EnwXY+wL8MQmpW9AMj+jh
Evd3yWwzrVyFbRp6NNrn0pGCKADUYOIm3MGkFlTm5GzfVUjGufZWKNatgNKBOUFy
wiig9lnF9/DKZWuhm3lVUfWPR0jrlLtxm+efq/xZPSwLzfhF+XTTbpqDWuHtJqB4
FACf4z5HwVfVjlEWRatQiOI2GPkTfT6yAJKXpJRs9MeCdKw3GlFdsDgF8axtJ42Y
bM1aDDNimjz8jI2OW5OXEvRzpiwIMIZ8oNeo+q7zxT0lUwvcAPcL7xWLtdcKw1u4
3V2b2GJzYsRyn7iZPR9GONE+BI24UEvJeo4M9QYcx3TlRfdEeIgRnRRfT86BW/5h
/krcxRSNEs0HJkSAT+nmL0wBq0Wv3Vd8Pz0hZx0KS2jX757Jm91FOxwH+A4rNBP/
0Rm72t8oNw5C4ynC8DmBB5p9D2GH9DHk4m5jd4wU0VLTSumjMWAMQBp8Cj5Gzbs5
tT3XlO4lCVQ0ymg2XucKGg8FHhan6ssVAFEDzrCNBduN70W0yx+UzL7jm7a8K9w0
IpT9v/p44Vm9L0+wB+PYhhpPXKaXQ4CKRba0hLl8DOZMeXk4oQlQe2DGxyVaxNxh
r4XdPPOmeDuhfxBoLHhMwZZnKPufGANreeA+tAmtNyrVUpe4bXY6fp0YEDBSGsy4
E27B9UXBmUJtvUjITAy7bLy5nWFBCv1ok6bCRXSXsaZHACp9xo1CtPrrXdTLhouU
ZyTPHb2lCswdq1sQidhRwTX/AnMp8B+bdqyNHXauMO68mT1m8laDg+yY5bOsVV2n
OhR3liZFvZM8KIlz4GT9dZgZ8gHLLGMXCrJJc5xC6qwannA+QkQPRH1cPJs3gPo9
UdBQ95U8Cr/G0T+qKCM9UJTwCL4bqnyrZGW9gbEPWhq89Gln6+DSp7dT1chGYzBY
uhzLHPBPMwuUTad99zcR2C7U3KiVSk3shklTBMlFOoP1kySIwy8Z9ms3o8nIKOr1
CueUf8wCQIHolTZEtzB4CUOWp3dcbP7Ln2dhwIVZVDFP6ZsgMiw9YOy9hRpn9I8y
0wq3H4yQNQ8t7BUCGrkqJ3HHOX2EzbwafcpWeqtJj3MPNdBhywTbysRbrh+zsJp2
dWInr/eLRImXz4BokY+1jYqoVCvi3hku+9H3+IRGTvgjVO7zF0y7g/2u3R6jv7ll
IfwDD89GQ5MigzrwyVIn9XCnnyOK28q/BmegL0azsjAOFK9jHILt2DX4VPdAFnGn
IIYR8dkEHHyFzzP9obL3pLSmMgzdE/7yTDZ6CWY8mSZ4UddvWTZ24dprxuUUD+fb
fv4NCzflZmTG0tJqMVlKUzHy5KZTVTJ6wAA+DMjVc4je11vO8niKXQdAekeoe6v0
q/BsM58kflR+/f+VDsZTbENUuadwZYSqiU7MNYkmY7GG5P/kdK07d7HmBFJTcybY
jR5YCd/kQPQNQl2rU2z+PD3oaGbGKJ2dLNwpZOAe2UgwbqiLSozkmiCyvlMM2xKZ
MwVPv2+A1HAEZ38Ew6w27gtjbNu1QC4cb2nu0R2tk4qmg1m59oatDDI7akkqu3r6
sE9e2bq8pgFHrRzSjWlIApSGgNanQCTQ5u6sHpBbBUiCDvJN9CfWgPDHeX47AYFJ
S3ZVn6ZYB7fBnVnwBeEHmI1ezjEAXljIbvaL9C2WrGGp3NgXQpn4PinPuXRBBkUC
qJUoud9XWPacKkZapFWOZ9+/+CWHA49/6aLENpt1Fy1gv3BpwDHwQ7QTUTtjhD2f
pPg46fNERMTTm4iQP0Fca8jVYx3Z7SVEsYaXYPegnETjAH93Yem0f25R5nfbRxda
FjiPdO+7f0EHSJevhIrDgXpyf+HZK7bpHBJW5bK8eUBg7f4TcQNAODy66L959rkl
84A/KaPobenGs6whoIjitWPXpJJPTmxCn5Qkp8wx+hL1oGe82seMYxa/5WXGzqGN
Y7DyPr16txAWZTfkVEwTlAUDYetnm0NLvpMPa3aSjkLRYur6JL7hY6WDC5rERwd4
WKbq/9l2BRTt/zqqEXU9REkLfWiQfoJsyN79eIdfA9GGg0VlGtFBcadJb3wGzriH
3DGgX1JceIsXYCh7dJA0MgSf5snIpilMW9EmGHZAcEgpqQFqHXFRJfCk7HHV1SqM
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
K9sd/rk7NALXNDOKx4aiqZXmx2hjxMxMCh6nkYDD6nAWUGADiYKQ6UAbUfSRG3r5
riXc2Roc7jPMoDK5EttVkY+J5PzRw1yIUENrxVhXzwXzxFZfF9lNfKty5FtDaTHk
o5C7bR7OXrUxbNk/nYkY1GMAPzCQB2sNKGTWt30hSbRxjpMbiQgnV7cDppDcDIjh
iDJ2DFEO8XyT++xupIqONYkaVKA7jRjh5JNfgmNnoEiHHKJR/B071toJ/wJnRDR8
q0fslLM1CohIy2lOs2y492Spb/9ZVyHmGlpR7QMAtg84xBHWadXFLq6+NkV2TF2U
xumSOnIbobI82Iem2jX/2w==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1872 )
`pragma protect data_block
FoSEzb3gDi6u2m8nfyGbIl3I5OSIjZNnchtrkQiHUCpL/dXDqArowTUxPP1O7v6T
Zx1NHRSu3dYXHGntiMrE9eiiMfNXtwTd5VW8amqeEfqQ+lXs6fUubs8/SPe60529
5k2cSn8OrRFGt4RZribroT/SGZ/s4pttNTOtrHb5vDUwabTAPfAKEp8uspH2h5z4
ElUCFAOx/FaAlEnmhoQp6plQUY3LynF086PYkeWeJw12Ln2fOai1azK/93QZUXDz
fWvFkHrQuzfp9jqp3PyLQ3C71snYPj5MlXIAKSnRtH2KwDj+OQNsJWtity2WYgu/
8/IzXaNO0xeYXN2pKn8LhoKdUyrt1vimRYyhm+OZhXbeMrR6r7jG86kgi1dYFdg0
hg6+zrYT+ylgLen1r/PW8Tiojo0Oc8Jo/7+Ybk+5BwW1haUDUqKdw9yl2H4/WRSi
bn2pRWSupMPBw6wrQCTXpQLSCQteFraet8NK2CeqrsDpU49GOFHOrUn4vzdW9//M
bFLnArsZgFiqj/xvg/g0rBOAMarHyyj0m9VgbjFWWyNS6P2gB4t84gTZtN8uyO3J
E4lexSvp7M8uDqjdB9RxVhe9KfcODYEcq5D3noZs8bTe6dBO186oL7ORclj6H2bb
PKV7by/mCTQ+MAs2SKQ9SUvUtZTTv5o1TCccMVSFiXVaMezXMWshlYan2sjJXWAH
AYBwvTD5f0MrwPBc7W4zbdFNSSNzx/jlNyAobpKFo5eI/17AgqqHCffvmlNAb0KR
PlBAKwnobqQt7oSxXY5YPmRVc3S7eQ4RptibCHXtHeMxE7b98kF6i+vEB9AfQMW+
FC4qLZO3vlVe/klKomyN1VSzrYUK20iftPG8yFS1p2Ll6+w5XKko9BmiS3a3D9He
x9/t7Le2JLEfR6shfhWgmWdpIaOZYwZ5n/qMn0QLxfu4rRV96HWZH386dFvP+kzG
KFUdJx0bg80rHIgdtaTQ5Z9SQkD+Pha2IWK0dgFHC7XEUFp6VfrTqcz1lqchHpFI
gp/WI5MjCbtHArBNNX783o9pvjnQwmOmgYMzNA52S6+lYzG4HRJw092ME8gTakKX
u7XaJSPvuXB/8+mD4ICWLiRgLXEecpFAv80L/4TStUEMWlkpasFv5cqTU3/ctmjB
UfmjtSW+fSdf//dC8+mQARC1VQOe5F7ET/OYbZCgxvWA51Z4Jl9AcanJYuCAWII1
twkm1kgX4Hgf940xZmmGN6B+EQvekgeCMk2nIpsNZr3eEhjIr87E07iiOD1a0zmr
tiInbG4T8PEdqKghHJl6QYbzIM4fudmy/HM8yr+zmS0dylhBH3mXC1WjcF4i7kM6
OJSoLFYx7QiqNBFTNKotEP+BL51hjLKpfk1UsySTMAsNdc1/4szcTaFdAi/Jc/dx
rKPsCB69MD+r4131Pkl6yPy0E6mwjTGtdSr+UZlBG1TCzia/hOtI/NfpvjHYF+CR
jQO2LVnY/zeUdgyAk7BkmtbwVFvtVpWEAsCghzeLv/jeG3Mzy8P6SzB2cAJfg16s
+O7MNaxYzJ0H3E0k6RK9DxL3qUEDzKgWhIhML6BRosQgwe72Oe/ENucQxaOio89t
imgIEaQRXhpVsk9fenXIEhPeVYr4BQS1y5gbxj6fNORUHHAZI/Fkyod3mmuXKSEz
2Pf74nE/p3YjXswUndlmiAboIzq/oEWbpwjdt5zOMs1SKUDI1r+miqEb9EXYFb52
0s/0af6iEiHIQx93mPx30PDrtAFVfBm39BrjMGpJFpcPFA9hZkhVRD2u8zPZNpF5
xNHK2Oy7x0SuP2/mJeZQ0SMg+zTdwnEawSeezMk+NYR4fc1sr6ZI+AA43LHPAzBe
f8S2lNORLZ8qW02Cyn0PViro6nKxZtwiE1pWm8qAN26Cnpj15Y/MAD4TMdU8VmjU
5SOxlJhO3BS74n10MRhzB93xYv/A5OET+DrJqDqL4u9vjf4sfJLjkz7wTjPs+8Fz
JncZ5v65vknoxCgcCRHCYFrxSPWU3pPrcED0I5ACOfFFHUFgb1sze8V5Y0yGMpub
3+DH8nzomRod1ntCgL8jEtRTA/XK2Bw6krIRt47zyxo+Ho7XxnNCl897po7yiaLh
xmxkDrdgsdcnL1elRg+8GZgeEVXgymWUbmRj0tWj0vCTXGYifsyBeVb7+wfLkrga
Mug3Dg8xILOwcaNoHsZD44rDOb4BVKnaGfSS4Fxxw4w6Awi0NnoiXIxJw/ynX+13
ZgSvC1Clieim6SRU1BzzNdDl1mXJeXlaIXFcHSdQ0OTBSMsli5p/wBk3Iv93Uh3O
dfpAileio4x6Y00BC9JLt9pfF/ILpN54+vygl+g9DnajayEj/Jc7X/krYs7h/Ww+
BMuWK5eIzz7csT/iPaw2Cqpv0CcyKh+sW1ZksDUbchtnML7T7lMhsnIDeMesL4cP
y5/aNc/acTgp8iBAjApx8xIX7X+u3YsiA3ulfRmNWfc/F7rEdHz+GW0U/e68jZti
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
mLpV1Gu2KvI34siE3LduNiqfWM8GpvTz4hY+Oclo9dEXhsBCIki9ndhvV5XCBfvf
d5dp/+0WZjVJGeKMSGJNCvHYJNU5lbFaXs2kz5d3vi6zRZp7r9ehcyw+oPJwn2UR
UNnUAiBWJjmkP3FLlURtjM6c328hckzOcIIexVLpJiMlRact8GFrUGwaOKLnWjAx
AIeY0fYoI3k+3wnepNjmr9sV/4UQB9EWvvBHGY/7ST/snm8SjZUdxBzsEluOPw0p
nUHUyUmpdhDO47hCLxKLWwNGkEw9AV6rPf8xplCr2T7xy21zmD67Fc3imLT6k2dq
CQGyF3te7usnhm3VC52hPw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2656 )
`pragma protect data_block
xSNXPFIRDLIwsGEPD3qKw2vvY6C6OFmQJZfs2jaME9RUzZfCCM0az5MQlmCIXhXX
XCUJpndmKa9Gjk2/l1ewbkKfmt9A6jeXfuGSp63KMiFk3a6It1IuO6TbZEuN9LqN
MuovK1jjCHufXKe+6KmWQ3QpZtyQdu3RMJRdBL7xL1+Pu6XpM0Ce/jGb+/5+IWWY
PnU1v9xlDIRIJ1iQDHmUavUsDuMp66RcSdP8J+3win4w3DXy1NMXof87kW6HObVe
baMVtysEtNjjFuwVoCj62sr1gD/V+owrdhNZ7C7qYIENVImrn1HhyvW2KzMOZDd/
UHvUiwD6O2WWA0XrEWYqRJe24SXQOEnYZ0gfBekHA0S8KbtmGmlCI6lR1T/cPd/9
lZni/wktUBtj09i+sP7h5aVybOr5cNyyswfo7Z785xS0cctKBFyduWylGmufwUnA
o46LWV55ABNoHrvNrmrrT5Acq8Rs8mt9OgoeXg/JDI6GlCh6TxgvBns0/Es+Y1Fk
thpIP1MYuiPQpmA/Ke28zAmLs92tGxMA2AtD/xIwwwXy/wlN/mtaVn/Sagr0qYSa
UVR6CtZzqkP7GATqPs0tCDiwrkYtg5EawVW/YPqwRO8B3gkYH9eJDLyq5QJeUQKl
gz9qeLS4XYWTMwnOhU9eeJrLq7G7k1Cg+7AEfkDsrA6HXv21mGuXlCjszc3ypoms
RVHW/E99O1VZqL8Pnx/MDicbL+5qgWMj0uCSEePp06Z4BNn3h4mwqEQbCQJTQTkZ
rRprlCJ4QLTvxEfgiwrp9VoAQHKiMo0b53NGs/74RLADRTprvSrcTiwsL2a0kNJB
UuXIJLlrYOd076a0DMU+ULuqYqpYGkkuXFv58RV8EVUsccc5sz49+5t0x0NOkgD+
6jPfM2wbyVuJRoCcU7FbcZyTHaQeQ0JRbXKnG/lb+UHRg59TplQJngnBRLk4aVwa
NG0VeG8Q01O18FRt8dgTUyUtSP09UlSrcFN/6/GV0pUSy4x19cC1L8ntV8Ka1/rk
y6SshIg9XA+X8d5yocaf6cWWFAkKfdNPZkDNVjVITEwVc34/fk314qe3Fy8C7Mmp
OX+bGH2kl7KHY8WyzoD2bngdxDJXoODALN4tAkmvqwqUjB6ZXMezTryamSccKHm+
b92UurLl0ayy6D/ej/FT/16yxyOjQOert66eVLVjKJWeWlsU/kvnzLgDrXdyeUdR
9Rl430pnvM8cmeOwKm+h/zOPEm7ehn1f2UX1yChr+Iz/ebrJ8AJoCuZGJ4ZE8uJS
E3MV0F5wEf4cKlQTyx3F+JZ320q7g3LiD1z5IJlg/x7vgEMmMH0TkPsTYdiFZN62
lqxsaF3HnyeAhiFCtCIec6r3uPpEzVDAE5KU/q9SuYUaMNKHuZREPGbVd3frja7+
E+9MMvHuQE9nYLsZdLNcnT3Kub5aU2WfGLZR2h5mPU2WJKpKXDmUOEM4PDcI8mhn
uFeeUmU9ZO2rXTuwuzH8OC8JPkQFyd8lAyvJ9Qq80rfs/1yzwGA2hWJNerIjAwQf
jGD77PL0mWqhKkwAArWD710+lkmjJR1CCIP1n4njXvGAs8uW3zoy+sHbghv5Cmd3
Ojo+HtWi7B28ca9agh1lFFzzg1tv7PkkZreJeIe7Pi/lxQcqQ1I6SRk7kagwFYuC
DQQndY+VikkLmXSKGwRO2WMeTWWLmTuMrB7TivJBRHaFXuxC2quU4/b21llicdlg
+XJlEo3LpBN9YPnyGt57fA6u79b12/UVC6uYZXE7cqSOYlr9BCxVdX53VgkTfUG1
NnWAt/jVtVAb6bZI3E1JMHiA9GDRb8lDPiBBW3LlsMIZ1jcGli1lqnbyWT2jl3lE
gZea2O6dkPGC8ceH+i+Mmj5A8B/O1NwBzVZglepbRBcsLcxmfiQVjiCDRwikUfD8
rZFt/tNM5Mbv6tDtla1UDRfntGzJVaWkrxPms/pkbTPjcrU44FPHXdOzF/CquZd6
Zis67BAf+3f7DRSb+Bjm4808fk8gRvOrHc5qyG4S5MrGxCtE67gXtNoI0k3TMr0S
bD8Hr/HcawYBms/uLVWNYo/FFec/Nib9BA4ifIgp9zOAvGJTMCvXY+59L9uVaaCb
YMj2exTokddbnsrDlP2R6ScxU0XnLbCvDpjVs2Stht2gDhY3tmFxvz343JRy0X5R
Rl7WeDxdjqEkxoAcEc5gZG+6TEi1n3zTby25bxO/TNJC8bRGIdrPehWq5eACDW2B
BMHpGpNQ7mFHdUzq2UJsDquuW2uE954U4XITmw22IyxNzio4Zq7GwZqS1daXuVnA
d4ft6Mq80BhSoAaAVRvddjM94Dp9rCuTe2OGkNlo0GvST/Vg6JDlGfPyWKLFZlAY
VQxZqPfCqwwXxhysDndmJ88ReMxGVjHryDe58knGOb2UEra3Wo00l5vD9coFxCyp
BboTbMjJ0VMMhRPFcFFeqxuFfeAyR/NS9lUqpOY0B3kzJQ8fyh1y9WgY3CZ98EA1
E8HeRNqgHSm2DZIGzTCm1ryOjqY8pMyqCDvzUNcObXM4n4vjEDDbtIFHqyjM/mbc
8V6h99bxsufaJEZAIT8vSlfUw6Y2vtUwJFjblN06pKcu/MxPonaBDb87cAKQDPhA
lqXOkpw6H0qzqRTZ0IrXGbQuelXBeWSZ0p7YsQH4/cxPdKH+KhbjfsnBEaCieGJm
9UOPJF/Jug/N/uzJZQGgas2FNuGPm5NAusK1UlUVa6QK6fiE0+Ao4lcjl6Bt/5ll
sEEqoqkS3m5tG3dEw4+ugFCM3kJTEtsietF+nr7BswXpY+CcpyD7RYpK7JjAUWNU
TpyxEC3PHmyTqzSSqnTjTKAdgJADDxmQdVpxuGe2rqNDO0CZ3rtCnRTlFQ9tX9FM
souLp7RTBs3mv1ZKY8s3WcPCdOsaxjEKAP30Q+XEzVnDL5nJ4//HIGQEvLBjFPd3
oLf4CrjecS/lcko8bmcby+/15I6ju7M81qQsrWE48zjN7M32hXrcTrw5K0Eagrdr
swhZhnKRzFPiLVACsVP/MlR1gCP7U15k9I01ZMlJ9M1USo/Pcva/EqkySwPTxrAR
d8+6LEiA8EbP/rUTsOTymiepG7NLpVnZB0Xz3M+MFsYBl+buEicaFJyiFndbEw8h
1+eft25zGGbi/5/2Q2fGbRvL5RBqTqsm3vjGtweScA9sEe34eZbgpdksRFBUv1V2
LW4HemIXnyB79BocI0YAtZhy59KiBC3DIYlKrfj1+S+UCnnCNnvicm9TXZDjKw8W
b1HVUzIlF3By7wJc9KkUV6OCH81VYkLltlIdFzQ1pkWoCZOH8m8/DaEi6sWRbtou
fIY0iOkjwcxOh+Hc2Bf9otUfC58KnSRiR2vRuUGNaW6auja2V92vgbwByP6k72Ds
H0kuN3DUWpRNIrb1VghUTDw4AYtvjOwX8t5RNFV31YwfACV59pw1q8AcQoL/xaUw
dFT+blTfRmF6FGbU5oPKTNz0UQrrTDueJ6Sx/rvI3kDYbtP9hJal167jSLcwqs3C
JZy8v3VXdOgTEj+8jfJs3A==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
E+rPi8nZBBvxw5lnIJA25LiV1KGw4KuXoijON8/1OC2p7Tm9Zi0gAeRVMoR0eOZ9
eys5000osxYCejkvyNmaUmdk8FOKlK/5KAjo+e2V19HgqNTf3/LIbYsebhfxOTfb
xrhTgQYpPTAzlVxDAxz4R6MiX9xrX5EZe06iEc1u8bKilKhwUXTCJXHwkhpl1hI3
4GDwzh2SnoYB3W5SvkuQWjwYxp4wTZPZjw731TbGzdTeLMObSAexK9FPIt5pr8qc
R9qRFfFHPz48NVDe/d9GoT9uZmf/qNeI8XkB22AjAlfN8xkDl0JUpV844N8Qh29L
NXpHL0KzVcX0fpWtDG4GKA==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16720 )
`pragma protect data_block
[encoded data, 22620 characters]
JlNlfwJg26XD5xeV1r5DLA==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
m8zQ7sOBnWKqiHsA62YXaRT1XaKRgBHbFdvDVfiNbhvyTitkE/GnfunamJg7vX+8
A6OgV02VtKKhUm6inN7j5ZfdLsphIzI9y+zfVTuxInua9SnrS4ARdJt6+G9hVkYD
j+S5PDLlpbjywBZR5tRHCW/sFRdMjmdyc9HyT+u27rlntbZurvNvc3FOvaNMVW0a
uSJP4ZIpA+vlRG4XkkskySo66eLK2XwjqLhjvYDzBafWJh6UEjEKo1XBXjxLVm/c
vFIAZeeo3jBW9njjLxTkam0ilthxAJHqGN3u6W6LMXwnzj4x+V4PD08HL954xluq
hv6zwVQtIIiw2TJx4Q2AEQ==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 19056 )
`pragma protect data_block
[encoded data, 25805 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
SZj6J8FtLe6cJ0AGj+KDow9C2ECmGxXMhFK3w8kOOiPB/9q8lgPgeBzDFA/kQvwt
OYDTJFd5zRv7gtXhFucJfuPQFKfoK/2Dg53kVRFK+pVlcatcAtwCryhgr07sNHSr
KMHU+1aO8khJO3fEK6r2T8OolUQ65f0OoCSJ1/WMdNlZH1bVV7RbvN64zWuwfoRg
XYEjk5LkVs8jAsJS252OCo9ELjbXL/R9aVMgStk2xFN+fqcyPaKD9lxC4Z5fpXXS
5hnIHY99pWllVzGmwIm9q5pGWm9jUnJLmmsg2ul3aPqKpFGJWO3w+7z7ljX4TmLd
0bhGvIZEMfMUuZBDz7lPyw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 36512 )
`pragma protect data_block
[encoded data, 49400 characters]
mPvjDFgZGs143wCJfqonJCx+Cl/5RrQra+rHZY5/25M=
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
E2SFbCNaq0TEuS3fXmP6CZgrgGsaNpVBd2YIDkJPajyhmaVjofF/LBLYEQPPhK40
UkM62YEDHqDPX6ZGCwfRXP1Cso8ieIlLRbL6wj3Ab83bl7/EZEDjks1HbtKwIvUp
M+ryBC5DfH4Ix0SubIfAXdbkMyB6uw4O17ffOfub3aVJQpqhP9RvQqdE0FYdB/nu
DjIwQbzr0tJ2si/K7BGhb/b1159MacDc3/UlJ6YMk8PYOR6KpF1BN5CXJg9A3IzX
QH6gRP6807lSrjZn+pu3gHNENEF16FWiIApctPPdA17WgKCSw4VFu5EuYgv4riqr
QYD9+VIjURpbPE1HjHHuMQ==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6832 )
`pragma protect data_block
[encoded data, 9230 characters]
gVfflHUiitigi+qYuOd18A==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
CdzB9vrn96JT0IE6IbyMNorhPjPK1D6V9sWaj27tOIS63fCLLd3Fhdvi9U4TNSXM
q8Aby8b18QaGHXvwTCj1PhwfZee2liTibnFxiK8W4vCoXbMw9jTqRbsPO4lShdnP
AWGN2s+1g4cfEMemSoABngHvKt5l8/Qgitl8ePAWUnsIIBUZo2R3xRFsRn+N92il
oHNxpyevVhtVVhOdSgy7cDEeIHiByqsXmBrSBeDLKbk+3u3rOGP8eH9qSXVIII+3
SrA9wnnKrvVU/P3ugps2Evh+pPJ4AgvxeqRFdC7y6LU7iIX4P7HEhvLALIRt8emX
k6uJrX9IUEHTr/7EDHmkRw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5664 )
`pragma protect data_block
[encoded data, 7670 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
SzhXiz0zdDjGadNr9/3NJb9f26Yal/c1yok2yhYa2l7w/1wi1Pyk/kz4XcjMPamc
+O5VYbIVSO9foPFV2GH0JLidIbOSshsjGoGUOBMc7ObMFmzJM7j4UZB36UARICG1
NstY6evrJSd4SebtwNn96dwrSQ7GTpYTYzmWGRO6ARJ26Q0G2/BphNu8Kt0oToCP
cIeA7dPO+6D9pJEQ7ALva09JRDpJLFnYV3Q4rQqPQTf6rOz6aFVjoreUAwJJuS0I
fQOth0AbIPM3M+Ru32rBli/HkaVx1mIB8qwdywD4K0hYw3zpmQ85q2mxK60Kqia5
X2aToGNImLAoWhi0MXx71Q==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3504 )
`pragma protect data_block
[encoded data, 4745 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
SCSoKCk2twpZ/XqldguMzShzGf717UuAFnxMW2zppYwt38fXo4wITcAjX0LpMd8j
uzfq9S0n/7qyFYgiH5eZ1IqF9adAH429mXd//VXHEVv3KM3mYadbFj3FOWadj42u
Q5TXIFdGIO0q4QbI0IUjM33F4oDrXceECtvEue6HWrbL008xluHyoNiafdO3bVOp
D9XyhOAPuGywEDRS7vc7XzNE2A4SIV6xuB7g10yBKBDGWLSwMkmgd5OrdfeTA5VY
8BdV2Kc4qrXzuxvt8I1PX715ZMdAEA+MjnUheF+rt+WpZeXxQyP9tBhQhqYGKl65
JO2HM4jcVqBVdH0h2IMwyw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 31840 )
`pragma protect data_block
[encoded data, 43095 characters]
ZdUoTcYAr4S0L7IS+7TL7A==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
O7i5M8pYrQm+JQ0l5NqrBMWS2b2UssqPixYbS8eUEw7ILL4e6LjSj3SOVpEG0ULu
yAZh0AkCaG901algg6BBfFcEtJP0Hndzf2+sLpnv7PKjh5cT4ooroR8EhSrmWPdC
bA1K4Npa52M0XheVpZDqwoLU0KBho9h8r+m4NL6xmfDn9GQBXpwA3c1n3VUnHT1u
ZieFKdix/S7UjukvTCzdF0jXDufcdmFwmSW+5nBa6nE3kQhC+3nbc5b4GRBS/+pe
DdKi5crDQb8DO4ROwQEh9wtk5p/8px31bWKDiys3YM/ojVgoFZxqIp4FysoQJS6j
Bly1mbumtHuw6wk+dWz9CQ==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 29968 )
`pragma protect data_block
[encoded data, 40560 characters]
HNBGv9zuNYy/TFC/VG9qPw==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
FTBEK5JPQERAuJEsQjL23p9J0qttLi73b3WuzfDhPf+IxVX47RLiJRGeN52CEc/5
u6CZJSqGAM3Jg85kgQmNuPYdj3luun2JYUFKX9j2YtWqby0dor9daQeoaCKF1ZWm
cS/qwlh98ApjcaB8q/czfIDKcpNRT34BUeTyPyAWoahz0D3YdXcnoc3oYTrDmVhM
9ooIEhfkyHPd12yQVTAY9nv4rEq/7U3/ymJbN44GnhD6jawsr1NzfhMD32tJFixd
OjzgmYS8Tli7BqTiieUS0+ocTzkqohIPIdPMLsp1vcDm0RWBlSJpDoa2ckNYbxPE
ge5nKUOOarrTYjfpOUaeGA==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 50592 )
`pragma protect data_block
[encoded data, 68510 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
h+15C3D2vNJXmQt4KKJyIMiVFAOGkQoAiniVA1UCZ2chDe6HY0xKRJJ81Lu8rUsv
Se18buUMb0xcWjLppKS41PxbNn8Fr7C4qjTBbVxwBROd5o8zBBGD53UxB77Tf6T3
dI8u0hMFMjsSIwABC2EyooRyBigBSE7ooqwjY2CKc8ionISglea8xB9S7hbOM84D
cvMggYg+KnnghbvXZvlRjrXtJBFUwGEWyvrOXcr05o6CcPUr0w55hVft7kpaTG6g
w8o3gb2NIX2uumKAHkqi350dfeSj9l35+mAYuR1KHnERd8hcDVeFG3swLuyGG8NQ
zq2BZ9X5CgnNEJy4IUNJsg==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5088 )
`pragma protect data_block
[encoded data, 6890 characters]
`pragma protect end_protected

//pragma protect end


module `IP_MODULE_NAME(mii_if) #(
   parameter NO_PREAMBLE = 0
) (
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//MII Interface
input                           mii_txc,
output  reg     [3:0]           mii_txd,
output  reg                     mii_tx_dv,
output  reg                     mii_tx_err,

input                           mii_rxc,
input           [3:0]           mii_rxd,
input                           mii_rx_dv,
input                           mii_rx_err

//Status and  Error Signals
);
// Parameter Define 
//localparam                      SPEED_100M_DIV = (TX_REFCLK == 125) ? 10 : 2;
//localparam                      SPEED_10M_DIV  = SPEED_100M_DIV*10;
//localparam                      SPEED_CLK_DIV = (TX_REFCLK == 125) ? SPEED_100M_DIV/2 + 1 : 0 ;
// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [3:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_dv_pre;
reg                             rx_dv_dl1;
reg     [3:0]                   rxd_pre;
reg     [3:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;
reg     [3:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [3:0]                   gm_tx_d_h;
reg     [7:0]                   gm_tx_d_r;
reg                             gm_tx_en_r;
reg                             gm_tx_err_r;
reg                             preamble_flg;
reg     [1:0]                   cur_st;
reg     [1:0]                   nxt_st;
reg                             add_preamble;


// Wire Define
wire                            add_preamble_w;

assign add_preamble_w = mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err && cur_st == 2'b01 && preamble_flg;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else
      tx_mac_aclk_en <= ~tx_mac_aclk_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_r <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_r <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_en_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_en_r <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_err_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_err_r <= gm_tx_err;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd <= 4'h0;
   else if (gm_tx_en_r == 1'b1) begin
      if (tx_mac_aclk_en == 1'b0)
          txd <= gm_tx_d_r[3:0];
      else
          txd <= gm_tx_d_r[7:4];
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_en <= 1'b0;
   else 
       tx_en <= gm_tx_en_r;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else 
       tx_er <= gm_tx_err_r;
end

always @ (posedge mii_txc or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      mii_tx_dv  <= 1'b0;
      mii_txd    <= 4'h0;
      mii_tx_err <= 1'b0;
   end
   else begin
      mii_tx_dv  <= tx_en;
      mii_txd    <= txd[3:0];
      mii_tx_err <= tx_er;
   end
end
/*----------------------- Rx Region ----------------------------*/
always @ (posedge mii_rxc or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 4'h0;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else if (add_preamble_w && NO_PREAMBLE != 1) begin
      rxd   <= 4'h5;
      rx_dv <= 1'b1;
      rx_er <= rx_er;
   end
   else if (add_preamble && NO_PREAMBLE != 1) begin
      rxd   <= rxd_pre;
      rx_dv <= rx_dv_pre;
      rx_er <= rx_er;
   end
   else begin
      rxd   <= mii_rxd;
      rx_dv <= mii_rx_dv;
      rx_er <= mii_rx_err;
   end
end

assign rx_mac_aclk = mii_rxc;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd_pre <= 4'h0;
      rx_dv_pre <= 1'b0;
   end
   else if (add_preamble_w || add_preamble) begin
      rxd_pre <= mii_rxd;
      rx_dv_pre <= mii_rx_dv;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
    if (rx_reset == 1'b1)
       add_preamble <= 1'b0;
    else if (add_preamble_w)
       add_preamble <= 1'b1;
    else if (!mii_rx_dv)
       add_preamble <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else
      rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      cur_st <= 2'b00;
   end
   else begin
      cur_st <= nxt_st;
   end
end

always @ (*) begin
   case (cur_st)
      2'b00: begin
         if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else
            nxt_st = 2'b00;
      end
      2'b01: begin
         if (mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b10;
         else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else 
            nxt_st = 2'b00;
      end
      2'b10: begin
         if (mii_rx_dv) 
            nxt_st = 2'b10;
         else
            nxt_st = 2'b00;
         end
      default: nxt_st = 2'b00;
   endcase
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      preamble_flg <= 1'b0;
   end
   else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err && cur_st == 2'b01) begin
      preamble_flg <= ~preamble_flg;
   end
   else begin
      preamble_flg <= 1'b0;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rx_dv_dl1 <= 1'b0;
      rxd_dl1   <= 4'h0;
   end
   else begin
      rx_dv_dl1 <= rx_dv;
      rxd_dl1   <= rxd;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else
      gm_rx_dv <= rx_dv_dl1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 1'b0;
   else if (rx_dv == 1'b0)
      rx_odd_data_ptr <= 1'b0;
   else
      rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if ((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
      gm_rx_d <= {rxd[3:0], rxd_dl1[3:0]};
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       gm_rx_err <= 1'b0;
   else begin
      if (rx_er == 1'b1)               gm_rx_err <= 1'b1;
      else if (rx_mac_aclk_en == 1'b1) gm_rx_err <= 1'b0;
   end
end


endmodule



//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
k9tqoepDssa6U5WJoqOS9tgWB31ZsRZUTNA+uBlqqK4sYjYn5IQk423OuSrCt3DJ
QQIBNQeiuHujWzO/78gYEikwkd/l0vjo0F7MU3SE61prd3sroydFcjL3M6+IeQdT
P7Cs5ER6xxqXBNFAQjCE02LglYkvruSD6LXo/rEq7WmOWDOxQ9PJynpvBkZGN0gU
3blXkCaqz6yJqX6aqt7hTn7Spaoy28BsXHYDZNePtYBYNgB1/eu/SX33ydi1CQXt
X1aoa49Z3tymTM1jDePEPxzVC7g86GH9WovncycvpB+ig8RwxdUkw8JFz/eFwkJ5
KelIQbvR96Crn/O4wBCEGQ==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 22080 )
`pragma protect data_block
[encoded data, 29900 characters]
`pragma protect end_protected

//pragma protect end


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii_if)#(
    parameter                       RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                           tx_mac_aclk,
   output  reg                     tx_mac_aclk_en,
   input                           tx_reset,
   output  wire                    rx_mac_aclk,
   output  reg                     rx_mac_aclk_en,
   input                           rx_reset,
   //Configuration Signals
   input           [2:0]           eth_speed,
   input                           rgmii_rxc_edge,//0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   input                           rgmii_txc_dly,//0:rgmii tx clock delay disable; 1:rgmii tx clock delay enable;
   //GMII Interface
   output  reg     [7:0]           gm_rx_d,
   output  reg                     gm_rx_dv,
   output  reg                     gm_rx_err,
   input           [7:0]           gm_tx_d,
   input                           gm_tx_en,
   input                           gm_tx_err,
   //RGMII Interface
   output  wire    [3:0]           rgmii_txd_HI,
   output  wire    [3:0]           rgmii_txd_LO,
   output  wire                    rgmii_tx_ctl_HI,
   output  wire                    rgmii_tx_ctl_LO,
   output  wire                    rgmii_txc_HI,//if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  wire                    rgmii_txc_LO,
   input           [3:0]           rgmii_rxd_HI,
   input           [3:0]           rgmii_rxd_LO,
   input                           rgmii_rx_ctl_HI,
   input                           rgmii_rx_ctl_LO,
   input                           rgmii_rxc
   //Status and  Error Signals
);

// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [7:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg     [1:0]                   txc;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;

// Wire Define
wire                            rx_dv;
wire    [7:0]                   rxd;
wire                            rx_er;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if ((eth_speed == 3'h4) ||
           ((eth_speed == 3'h2) && (aclk_en_cnt == 7'd9)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd99)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[7:4] <= 4'h0;
   else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[7:4] <= gm_tx_d[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[3:0] <= 4'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[3:0] <= gm_tx_d[3:0];
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd6)) ||
            ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd51)))
      txd[3:0] <= txd[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_en <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_er <= gm_tx_err;
end
/*
always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
        3'h4 :
            txc <= 2'b01;
        3'h2 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b00;
            endcase
        3'h1 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
                    txc <= 2'b00;
            endcase
        default :
            txc <= 2'b0;
        endcase
end

*/
reg [1:0]    txc_100m_r;
reg [1:0]    txc_10m_r;

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_100m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
          1'b0 : //rgmii tx clock delay disable.
             if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                txc_100m_r <= 2'b00;
          1'b1 ://rgmii tx clock delay enable.
             if ((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b00;
       endcase
   end
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_10m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
       1'b0 ://rgmii tx clock delay disable.
           if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
               txc_10m_r <= 2'b00;
       1'b1 ://rgmii tx clock delay enable.
           if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
               txc_10m_r <= 2'b00;
       endcase
   end
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
            3'h4 :
                txc <= 2'b01;
            3'h2 :
                txc <= txc_100m_r;
            3'h1 :
                txc <= txc_10m_r;
            default :
                txc <= 2'b0;
        endcase
end

/*----------------------- Rx Region ----------------------------*/
assign rx_mac_aclk = rgmii_rxc;

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_mac_aclk_en <= 1'b0;
    else if(eth_speed[2] == 1'b1)
        rx_mac_aclk_en <= 1'b1;
    else
        rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        begin
            rx_dv_dl1 <= 1'b0;
            rxd_dl1 <= 8'h0;
        end
    else
        begin
            rx_dv_dl1 <= rx_dv;
            rxd_dl1 <= rxd;
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_dv <= 1'b0;
    else
        gm_rx_dv <= rx_dv_dl1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_odd_data_ptr <= 1'b0;
    else if(rx_dv == 1'b0)
        rx_odd_data_ptr <= 1'b0;
    else
        rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_d <= 8'h0;
    else
        begin
            if((eth_speed[2] == 1'b1) && (rx_dv_dl1 == 1'b1))
                gm_rx_d <= rxd_dl1;
            else if((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
                gm_rx_d <= {rxd[3:0],rxd_dl1[3:0]};
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_err <= 1'b0;
    else
        begin
            if(rx_er == 1'b1)
                gm_rx_err <= 1'b1;
            else if(rx_mac_aclk_en == 1'b1)
                gm_rx_err <= 1'b0;
        end
end

/*----------------------- PHY Interface ----------------------------*/
`IP_MODULE_NAME(rgmii) #(
    .RGMII_SYNC_EN                      (RGMII_SYNC_EN                      )
)
u_rgmii
(
//Globle Signals
    .tx_mac_aclk                        (tx_mac_aclk                        ),
    .tx_reset                           (tx_reset                           ),
    .rx_reset                           (rx_reset                           ),
//Configuration Signals
    .eth_speed                          (eth_speed                          ),
    .rgmii_rxc_edge                     (rgmii_rxc_edge                     ),
//Phy Interface
    .txd                                (txd                                ),
    .tx_en                              (tx_en                              ),
    .tx_er                              (tx_er                              ),
    .txc                                (txc                                ),
    .rxd                                (rxd                                ),
    .rx_dv                              (rx_dv                              ),
    .rx_er                              (rx_er                              ),
//RGMII Interface
    .rgmii_txd_HI                       (rgmii_txd_HI                       ),
    .rgmii_txd_LO                       (rgmii_txd_LO                       ),
    .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI                    ),
    .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO                    ),
    .rgmii_txc_HI                       (rgmii_txc_HI                       ),
    .rgmii_txc_LO                       (rgmii_txc_LO                       ),
    .rgmii_rxd_HI                       (rgmii_rxd_HI                       ),
    .rgmii_rxd_LO                       (rgmii_rxd_LO                       ),
    .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI                    ),
    .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO                    ),
    .rgmii_rxc                          (rgmii_rxc                          )
);

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
module `IP_MODULE_NAME(rgmii_sync)
(
//Globle Signals
input                           rgmii_rxc,
input                           rx_reset,
input           [2:0]           eth_speed,
//RGMII Rx Interface Input
input           [3:0]           rgmii_rxd_HI_i,
input           [3:0]           rgmii_rxd_LO_i,
input                           rgmii_rx_ctl_HI_i,
input                           rgmii_rx_ctl_LO_i,
//RGMII Rx Interface Output
output  reg     [3:0]           rgmii_rxd_HI_o,
output  reg     [3:0]           rgmii_rxd_LO_o,
output  reg                     rgmii_rx_ctl_HI_o,
output  reg                     rgmii_rx_ctl_LO_o
);


// Parameter Define 
parameter State_idle     = 2'd0;
parameter State_preamble = 2'd1;
parameter State_data_dl1 = 2'd2;
parameter State_data_dl2 = 2'd3;


// Register Define 
reg     [1:0]                   cur_state;
reg     [1:0]                   next_state;
reg                             preamble_odd;
reg     [3:0]                   rx_d_dl1;
reg                             rx_dv_dl1;
reg     [3:0]                   rx_d_dl2;
reg                             rx_dv_dl2;

// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rx_d_dl1      <= 4'h0;
      rx_dv_dl1     <= 1'b0;
      rx_d_dl2      <= 4'h0;
      rx_dv_dl2     <= 1'b0;
   end
   else begin
      rx_d_dl1      <= rgmii_rxd_LO_i;
      rx_dv_dl1     <= rgmii_rx_ctl_HI_i;
      rx_d_dl2      <= rx_d_dl1;
      rx_dv_dl2     <= rx_dv_dl1;
   end
end

/*----------------------- FSM Region ----------------------------*/
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) cur_state <= State_idle;
	else          cur_state <= next_state;
end

always @ (*) begin
	case (cur_state)
      State_idle :
         if ((rx_dv_dl1 == 1'b1) && (rx_d_dl1 == 4'h5))
             next_state = State_preamble;
         else
             next_state = State_idle;

      State_preamble : 
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b0))
            next_state = State_data_dl1;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
            next_state = State_data_dl2;
         else if (rx_d_dl1 != 4'h5)
            next_state = State_idle;
         else
            next_state = State_preamble;
          
      State_data_dl1 :
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl1;

      State_data_dl2 :
         if (rx_dv_dl2 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl2;

      default :
         next_state = State_idle;
    endcase
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
    if (rx_reset) 
       preamble_odd <= 1'b0;
    else if (cur_state == State_preamble)
       preamble_odd <= ~preamble_odd;
    else
       preamble_odd <= 1'b0;
end

/*----------------------- Sync Output Region ----------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rxd_LO_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_LO_o <= rgmii_rxd_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rxd_LO_o <= 4'h5;
   else if (cur_state == State_data_dl2)
      rgmii_rxd_LO_o <= rx_d_dl2;
   else
      rgmii_rxd_LO_o <= rx_d_dl1;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) 
      rgmii_rxd_HI_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_HI_o <= rgmii_rxd_HI_i;
   else
      rgmii_rxd_HI_o <= 4'h0;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_HI_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_HI_o <= rgmii_rx_ctl_HI_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_HI_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_HI_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_HI_o <= rx_dv_dl1;
end

always @(posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_LO_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_LO_o <= rgmii_rx_ctl_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_LO_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_LO_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_LO_o <= rx_dv_dl1;
end

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii) #(
    parameter                   RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                        tx_mac_aclk,
   input                        tx_reset,
   input                        rx_reset,
   //Configuration Signals
   input           [2:0]        eth_speed,
   input                        rgmii_rxc_edge, //0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   //Phy Interface
   input           [7:0]        txd,
   input                        tx_en,
   input                        tx_er,
   input           [1:0]        txc, //if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  reg     [7:0]        rxd,
   output  reg                  rx_dv,
   output  reg                  rx_er,
   //RGMII Interface
   output  reg     [3:0]        rgmii_txd_HI,
   output  reg     [3:0]        rgmii_txd_LO,
   output  reg                  rgmii_tx_ctl_HI,
   output  reg                  rgmii_tx_ctl_LO,
   output  reg                  rgmii_txc_HI,
   output  reg                  rgmii_txc_LO,
   input           [3:0]        rgmii_rxd_HI,
   input           [3:0]        rgmii_rxd_LO,
   input                        rgmii_rx_ctl_HI,
   input                        rgmii_rx_ctl_LO,
   input                        rgmii_rxc
   //Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [3:0]                   rgmii_rxd_HI_d1;
reg                             rgmii_rx_ctl_HI_d1;
reg     [3:0]                   rgmii_txd_HI_r;
reg     [3:0]                   rgmii_txd_LO_r;
reg                             rgmii_tx_ctl_HI_r;
reg                             rgmii_tx_ctl_LO_r;
reg                             rgmii_txc_HI_r;
reg                             rgmii_txc_LO_r;
// Wire Define
wire                            tx_en_to_ddr;
wire                            rgmii_tx_ctl_int;
wire    [3:0]                   txd_falling;
/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- RGMII Tx Region ----------------------------*/
assign tx_en_to_ddr = (eth_speed[2] == 1'b1) ? tx_en : tx_en && (!tx_er);
assign rgmii_tx_ctl_int = tx_en ^ tx_er;

assign txd_falling = (eth_speed[2] == 1'b1) ? txd[7:4] : txd[3:0];

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI_r    <= 1'b0;
      rgmii_txc_LO_r    <= 1'b0;
      rgmii_tx_ctl_HI_r <= 1'b0;
      rgmii_tx_ctl_LO_r <= 1'b0;
      rgmii_txd_HI_r    <= 4'b0;
      rgmii_txd_LO_r    <= 4'b0;
   end 
   else begin
      rgmii_txc_HI_r    <= txc[0];
      rgmii_txc_LO_r    <= txc[1];     
      rgmii_tx_ctl_HI_r <= tx_en_to_ddr;
      rgmii_tx_ctl_LO_r <= rgmii_tx_ctl_int;
      rgmii_txd_HI_r    <= txd[3:0];
      rgmii_txd_LO_r    <= txd_falling;
   end
end


always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI    <= 1'b0;
      rgmii_txc_LO    <= 1'b0;
      rgmii_tx_ctl_HI <= 1'b0;
      rgmii_tx_ctl_LO <= 1'b0;
      rgmii_txd_HI    <= 4'b0;
      rgmii_txd_LO    <= 4'b0;
   end
   else begin
      rgmii_txc_HI    <= rgmii_txc_HI_r;
      rgmii_txc_LO    <= rgmii_txc_LO_r;
      rgmii_tx_ctl_HI <= rgmii_tx_ctl_HI_r;
      rgmii_tx_ctl_LO <= rgmii_tx_ctl_LO_r;
      rgmii_txd_HI    <= rgmii_txd_HI_r;
      rgmii_txd_LO    <= rgmii_txd_LO_r;
   end
end

/*----------------------- RGMII Rx Region ----------------------------*/
//rgmii_rxd & rgmii_rx_ctl
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rgmii_rxd_HI_d1    <= 4'h0;
      rgmii_rx_ctl_HI_d1 <= 1'b0;
   end 
   else begin
      rgmii_rxd_HI_d1    <= rgmii_rxd_HI;
      rgmii_rx_ctl_HI_d1 <= rgmii_rx_ctl_HI;
   end
end

generate
   if (RGMII_SYNC_EN == 0) begin
      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rxd[7:4] <= rgmii_rxd_LO;
               rxd[3:0] <= rgmii_rxd_HI_d1;
               rx_dv    <= rgmii_rx_ctl_HI_d1;
               rx_er    <= rgmii_rx_ctl_HI_d1^rgmii_rx_ctl_LO;
            end
            else begin//1:DDIO Falling Edge
               rxd[7:4] <= rgmii_rxd_HI;
               rxd[3:0] <= rgmii_rxd_LO;
               rx_dv    <= rgmii_rx_ctl_LO;
               rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI;
            end
        end
        else begin //100M or 10M
           rxd[7:4] <= 4'b0;
           rxd[3:0] <= rgmii_rxd_LO;
           rx_dv    <= rgmii_rx_ctl_LO;
           rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI_d1;
        end
     end
   end
   else begin
      reg  [3:0]  rgmii_rxd_HI_i;
      reg  [3:0]  rgmii_rxd_LO_i;
      reg         rgmii_rx_ctl_HI_i;
      reg         rgmii_rx_ctl_LO_i;
      wire [3:0]  rgmii_rxd_HI_sync;
      wire [3:0]  rgmii_rxd_LO_sync;
      wire        rgmii_rx_ctl_HI_sync;
      wire        rgmii_rx_ctl_LO_sync;

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rgmii_rxd_HI_i    <= 4'h0;
            rgmii_rxd_LO_i    <= 4'h0;
            rgmii_rx_ctl_HI_i <= 1'b0;
            rgmii_rx_ctl_LO_i <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_LO;
               rgmii_rxd_LO_i    <= rgmii_rxd_HI_d1;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI_d1;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
            else begin //1:DDIO Falling Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_HI;
               rgmii_rxd_LO_i    <= rgmii_rxd_LO;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
         end        
         else begin//100M or 10M
            rgmii_rxd_HI_i    <= rgmii_rxd_HI_d1;
            rgmii_rxd_LO_i    <= rgmii_rxd_LO;
            rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_LO;
            rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_HI_d1;
         end
      end

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else begin
            rxd[7:4] <= rgmii_rxd_HI_sync;
            rxd[3:0] <= rgmii_rxd_LO_sync;
            rx_dv    <= rgmii_rx_ctl_HI_sync;
            rx_er    <= rgmii_rx_ctl_HI_sync^rgmii_rx_ctl_LO_sync;
         end
      end
      
      /*----------------------- RGMII Rx Sync Module -----------------------*/
      `IP_MODULE_NAME(rgmii_sync) u_rgmii_sync
      (
      //Globle Signals
          .rgmii_rxc                  (rgmii_rxc                  ),
          .rx_reset                   (rx_reset                   ),
          .eth_speed                  (eth_speed                  ),
      //RGMII Rx Interface Input
          .rgmii_rxd_HI_i             (rgmii_rxd_HI_i             ),
          .rgmii_rxd_LO_i             (rgmii_rxd_LO_i             ),
          .rgmii_rx_ctl_HI_i          (rgmii_rx_ctl_HI_i          ),
          .rgmii_rx_ctl_LO_i          (rgmii_rx_ctl_LO_i          ),
      //RGMII Rx Interface Output
          .rgmii_rxd_HI_o             (rgmii_rxd_HI_sync          ),
          .rgmii_rxd_LO_o             (rgmii_rxd_LO_sync          ),
          .rgmii_rx_ctl_HI_o          (rgmii_rx_ctl_HI_sync       ),
          .rgmii_rx_ctl_LO_o          (rgmii_rx_ctl_LO_sync       )
      );
   end
endgenerate


endmodule


module `IP_MODULE_NAME(rmii_if)
(
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//RGMII Interface
input                           rmii_clk_ref,
output  reg     [1:0]           rmii_txd,
output  reg                     rmii_tx_en,

input           [1:0]           rmii_rxd,
input                           rmii_crs_dv,
input                           rmii_rx_err

//Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [6:0]                   rx_aclk_en_cnt;
reg     [1:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_err_dl1;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg     [6:0]                   rx_odd_data_ptr;
reg     [1:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [7:0]                   gm_tx_d_temp;
reg                             tx_en_temp;
reg     [6:0]                   txbit_cnt;
reg                             rx_dv_compensate;
reg                             rx_err_compensate;
reg                             rx_err_latch;
reg     [7:0]                   rx_d_compensate;
reg     [6:0]                   rx_compensate_cnt;
// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd39)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_temp <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_temp <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en_temp <= 1'b0;
   else if(tx_mac_aclk_en == 1'b1)
      tx_en_temp <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txbit_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (txbit_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (txbit_cnt == 7'd39)))
      txbit_cnt <= 7'd0;
   else if (tx_en_temp == 1'b1)
      txbit_cnt <= txbit_cnt + 1'b1;
   else
      txbit_cnt <= 7'd0; 
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txd <= 2'h0;
   else if (eth_speed == 3'h2) begin
      case(txbit_cnt[1:0])
         2'b00: txd <= gm_tx_d_temp[1:0];
         2'b01: txd <= gm_tx_d_temp[3:2];
         2'b10: txd <= gm_tx_d_temp[5:4];
         2'b11: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case(txbit_cnt[5:0])
         6'd00: txd <= gm_tx_d_temp[1:0];
         6'd10: txd <= gm_tx_d_temp[3:2];
         6'd20: txd <= gm_tx_d_temp[5:4];
         6'd30: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else 
      tx_en <= tx_en_temp;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
       tx_er <= gm_tx_err;
end

always @ (posedge rmii_clk_ref or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      rmii_tx_en <= 1'b0;
      rmii_txd   <= 2'b0;
   end
   else begin
      rmii_tx_en  <= tx_en;
      rmii_txd    <= txd[1:0];
   end
end

/*----------------------- Rx Region ----------------------------*/
always @(posedge rmii_clk_ref or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 2'b00;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else begin
      rxd   <= rmii_rxd;
      rx_dv <= rmii_crs_dv;
      rx_er <= rmii_rx_err;
   end
end

assign rx_mac_aclk = rmii_clk_ref;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_aclk_en_cnt == 7'd39)))
      rx_aclk_en_cnt <= 7'd0;
   else
      rx_aclk_en_cnt <= rx_aclk_en_cnt + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else if (rx_aclk_en_cnt == 7'd0)
      rx_mac_aclk_en <= 1'b1;
   else
      rx_mac_aclk_en <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_odd_data_ptr == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_odd_data_ptr == 7'd39)) || (rx_dv == 1'b0))
      rx_odd_data_ptr <= 7'd0;
   else 
      rx_odd_data_ptr <= rx_odd_data_ptr + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_dl1 <= 1'b0;
   else 
      rx_dv_dl1 <= rx_dv; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_dl1 <= 1'b0;
   else 
       rx_err_dl1 <= rx_er; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rxd_dl1 <= 8'h0;
   else if (eth_speed == 3'h2) begin
      case (rx_odd_data_ptr[1:0])
         2'b00: rxd_dl1[1:0] <= rxd;
         2'b01: rxd_dl1[3:2] <= rxd;
         2'b10: rxd_dl1[5:4] <= rxd;
         2'b11: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case (rx_odd_data_ptr[5:0])
         6'd00: rxd_dl1[1:0] <= rxd;
         6'd10: rxd_dl1[3:2] <= rxd;
         6'd20: rxd_dl1[5:4] <= rxd;
         6'd30: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end
   else;    
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (rx_dv_dl1 == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_compensate_cnt <= rx_compensate_cnt;
   else
      rx_compensate_cnt <= rx_compensate_cnt + 1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_dv_compensate <= 1'b0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_dv_compensate <= 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_latch <= 1'b0;
   else begin
      if (rx_dv & rx_er)                rx_err_latch <= 1'b1;
      else if (rx_odd_data_ptr == 7'd0) rx_err_latch <= 1'b0; 
      else                              rx_err_latch <= rx_err_latch;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_err_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_err_compensate <= 1'b0;
   else if (rx_odd_data_ptr == 7'd0)
      rx_err_compensate <= rx_err_latch;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_d_compensate <= 8'h0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_d_compensate <= rxd_dl1;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_dv <= rx_dv_compensate;
end


always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_d <= rx_d_compensate;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_err <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_err <= rx_err_compensate;
end

endmodule



module `IP_MODULE_NAME(efx_mac1gbe) #(
   parameter FAMILY = "TRION",
   parameter VERSION = 32'h20,
   parameter RXFIFO_EN = 1,
   parameter RXFIFO_DTH = 2048,
   parameter TXFIFO_EN = 1,
   parameter TXFIFO_DTH = 2048,
   parameter PHY_INTF_MODE = 0,  
   parameter LOOPBACK_EN = 1'b0,
   parameter GMII_DW = PHY_INTF_MODE == 4 ? 16 : 8,
   parameter AXIS_DW = 8,  
   parameter APBIF = 0,
   parameter NO_PREAMBLE = 0,
   parameter INTER_PACKET_GAP = 6'd12,
   parameter MTU_FRAME_LENGTH = 16'd1518,
   parameter MAC_SOURCE_ADDRESS = 48'h0,
   parameter ENABLE_BROADCAST_FILTERING = 1'b1,
   parameter RGMII_RXC_EDGE = 1'b1,
   parameter RGMII_TXC_DLY = 1'b1,
   parameter PKT_CNT_MAX = 256, 
   parameter SIP600 = 0 
) (
   input                  tx_mac_aclk,
   output                 rx_mac_aclk,
   input                  mac_reset,   
   input                  proto_reset, 
   input                  tx_axis_clk,
   input [AXIS_DW-1:0]    tx_axis_mac_tdata,
   input                  tx_axis_mac_tvalid,
   input                  tx_axis_mac_tlast,
   input [AXIS_DW/8-1:0]  tx_axis_mac_tstrb,
   input                  tx_axis_mac_tuser,
   output                 tx_axis_mac_tready,
   input                  rx_axis_clk,
   output [AXIS_DW-1:0]   rx_axis_mac_tdata,
   output                 rx_axis_mac_tvalid,
   output                 rx_axis_mac_tlast,
   output [AXIS_DW/8-1:0] rx_axis_mac_tstrb,
   output                 rx_axis_mac_tuser,
   input                  rx_axis_mac_tready,
   input                  gm_rx_c,
   input  [GMII_DW-1:0]   gm_rx_d,
   input  [GMII_DW/8-1:0] gm_rx_dv,
   input  [GMII_DW/8-1:0] gm_rx_err,
   output                 gm_tx_c,
   output [GMII_DW-1:0]   gm_tx_d,
   output [GMII_DW/8-1:0] gm_tx_en,
   output [GMII_DW/8-1:0] gm_tx_err,
   output [3:0]           rgmii_txd_HI,
   output [3:0]           rgmii_txd_LO,
   output                 rgmii_tx_ctl_HI,
   output                 rgmii_tx_ctl_LO,
   output                 rgmii_txc_HI,
   output                 rgmii_txc_LO,
   input  [3:0]           rgmii_rxd_HI,
   input  [3:0]           rgmii_rxd_LO,
   input                  rgmii_rx_ctl_HI,
   input                  rgmii_rx_ctl_LO,
   input                  rgmii_rxc,
   input                  mii_txc,
   output [3:0]           mii_txd,
   output                 mii_tx_dv,
   output                 mii_tx_err,
   input                  mii_rxc,
   input  [3:0]           mii_rxd,
   input                  mii_rx_dv,
   input                  mii_rx_err,
   input                  rmii_clk_ref,
   output [1:0]           rmii_txd,
   output                 rmii_tx_en,
   input  [1:0]           rmii_rxd,
   input                  rmii_crs_dv,
   input                  rmii_rx_err,
   input  [9:0]           s_paddr,
   input  [31:0]          s_pwdata,
   input                  s_pwrite,
   input                  s_penable,
   input                  s_psel,
   output [31:0]          s_prdata,
   output                 s_pready,
   output                 s_perr,
   input                  s_axi_aclk,    
   input  [9:0]           s_axi_awaddr,  
   input                  s_axi_awvalid, 
   output                 s_axi_awready, 
   input  [31:0]          s_axi_wdata,   
   input                  s_axi_wvalid,  
   output                 s_axi_wready,  
   output [1:0]           s_axi_bresp,   
   output                 s_axi_bvalid,  
   input                  s_axi_bready,  
   input  [9:0]           s_axi_araddr,  
   input                  s_axi_arvalid, 
   output                 s_axi_arready, 
   output [1:0]           s_axi_rresp,   
   output [31:0]          s_axi_rdata,   
   output                 s_axi_rvalid,  
   input                  s_axi_rready,  
`ifdef ONCHIP_PHY
   input  logic           init_clk,
   input  logic           init_rst_n,
   input  logic           PMA_CMN_READY,
   input  logic           PMA_XCVR_PLLCLK_EN_ACK,
   input  logic [3:0]     PMA_XCVR_POWER_STATE_ACK,
   input  logic           PMA_RX_SIGNAL_DETECT,
   output logic           PMA_XCVR_PLLCLK_EN,
   output logic [3:0]     PMA_XCVR_POWER_STATE_REQ,
   output logic           phy_init_done,
`else
   output                 Mdo,   
   output                 MdoEn, 
   input                  Mdi,   
   output                 Mdc,   
`endif
   output [2:0]           eth_speed
);
`ifdef ONCHIP_PHY
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
H1QhdHwPCw4FTFVKfREEloX4Ul+jRhDrKdS6DAFqmR7d1Yc/YiaxRdFdhm/E6pG/
bVdqR9w77voWYg5JTKlSBfXgDWFAEUuMW/7WUzs6aQAC3Hx6XbXh9WZBIyadkXf0
dZnqlxxZSlaMuXnyEq5FKZB4a/mbzZotE0/jjDHZ48QsV7VxKpt2wPnrwHRzRwuZ
pFYg9SUPwbYS06jRoG4rGAnY9X8K2GIubhZbS5S2IAoSIw6Urykxl8J2raTBk7/Q
/kPv/d56MuDf+PqLWMWOtJLGu8FX4CyH3umRY6e9P5q0qJtv/0uUC21+xXvQbnWH
pV93YA7YL4/nAKB63762Lw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4864 )
`pragma protect data_block
[encoded data, 6565 characters]
m7eCK1ymdHqXLWqKpLfogg==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
mVvgvhMnm94S863IKYifMrYJ8xfsornOKZDgbMsVgTTwruDWBKzXogBG9y5Jlj6b
XxPsSERWYj5leeHtTs+Jcc8niKtaytfMmB2wr0w7AGIFJPm4a6HRr2CgcMXA/EgF
Wr4stv2xlMfuBJ22zmBSZHvjew8HSBWdx+bxKETVlgs1uIPfR2PqreXod30MhUKX
6dztGRSMURXuvohxIZ0x8mhcKhFK6/rfG1UGcimNX12je9YQ4IRVtRoTs3crHEkf
OJC45+yDyUujE0emiPRnQQs456SRPWrZTFZD6wQfqjH45sKauM16wFyeUi18kseE
HZYJHNunZ3i9Y+/GIw2pcA==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2992 )
`pragma protect data_block
0nilENdKo4TM2ot8dHQzKK6LgYCaSr0olrYhM7KJPNjgf1OQBk0SLLcfeYNRprG0
Fb7/s3k5MJZr7XGFxwwXKaTvw9/xxcz1ifYj4MIZ66CGruyn7Fiwrz+r48hzQ9rD
yHsgjBU6mBljDz4uK8FgP8krpam1K5rBFF9i9WeGpwyA09I+2zXcjqZ47WE2E/CJ
QpogaroS1vXzOVYdLYBh2XRQnS4UFOI548AwxnUKd5Z1WjC5Lo5pERy5SjzWAIZu
duDH6wOb3AoxRmWSbP6TNCVldw6FBjJkOVpuODD6YDdlpSLUTyyXVnzpJQ7ZUoMw
/Y6CDZpb/6D8a955omY8RNPnSdxkJJkDWuBxrJzZ4Y8fuciHTf7HYj2VflYQo1Fz
NnqZyuZkuhZcfA3Sb8SoQjy1A0b1EL73vlPdDIi0M20bP3Cc/bJ0i9cVZRcJ97GJ
kyoiIOBgCyORcPWxUJ7HMM9gJvxcWRrgwNFZh+3UvfSYYqdUhTIWi34nCbak8BzR
fVwL/cc/ccyoRvZ3q9fo41l+MvggpcjuqyR79KHmD+lgOKyT/TKoo7Ztz+bTgFYS
sFeYEJJV5dTSxBZEl0i3ObyqAL5IfY5UO5bZYxo52Qwsh5HvTjwGZgRBx0N0fZ2D
ne+3l0ELTAdYGBhMmGBEe/MiX0KNlmSmJPjZaHK0MIOLQQoS2AQZhKsWsCKNx8Mt
xg2gIFkIoxrJ0cRMvJFhbNFuczYvjAY6YtcKf1EAOnAMJIQEwqJOkMvlt0f7+pIc
E/3UXi/4zulx7QoSxkPwmVUJ3Vz0t1HsEAKq1fERUGsU2nyl9LOBjfsS96XXwCoA
oUY0dEHZ6lKZDlDvUN+vcMaB9+om3YIO22WWt+iz1NGDsB4L45RgdO1KeISXWwcf
l3LGba8DNjqDqb8qZApKLV5uwodI5wGRxURZ78yeH1Cv0XPn6blPAHsjpYOEtPCd
C3kcVFBAWXuCH9B9d3d1mWMof5COIElp3NDkGr9lQVCCQz4+/mYELxHzW81vWufl
/HnD4wF42CeF4fyVsG+xvuCoydvWvqdQwTXdNv3dr34MaunlELAPxzRkIL7h4Q30
UhsKWuoeoUPiY7VNzeM1v13HUhDty5MCGmfUjjVa3FajBt/gMwR+N3wBXPGBTsAS
Ljy5aA9PsXy20F8SdgoA9K355I5MYCoaRXbrjnamgjn2wLwHcg/i/39wGmoM+ry/
x3bgqCWV9yGWtjddsptAtgu3jOPa6ypT/2DMI5IGlJujqqv8RPVv0R5UTONXT4Gw
t9ngAz4qB39omY91UZELyAGIonFYo9rCPgW3YbLcbkv3hS2CNNEN1x+ZeLrCTw0m
9gBbya3/HxLpn44V2Zb9kniEb7XNZAXBE5gFpHMDFVTKeMQn+1dOeb+4ozBs6MNI
bge0sSRX/pNpyBDARUwksFDo1Bq8MDE357mC2fSFFcx4xjulhw/mHRAjzSe4EQrO
L6SKlXyPXp4XVlQou5vGyqkVI+/TTn4aG/nSNMuERLfiGchR654OG4hPid/WbZtw
/td0dE31/pi/Zv5bifocdFsNTlD3GllEJBYvNJ1Xb4kWPRV+6T2vEircloxuowvN
3WuzWSrBiVWIzVoSgAAvhGENzrOn5ZkvDDX+VBHeYYcvDkwxHXWBYY6l2YDY+PxH
1MS3NtQE1dw2p5kC344LMTILyHXpNcdmJzIBM0AlD+r8tM8ToKp3uB/ZCUScHM2i
V8Bmesnx7JYoGBTH5wP4AUAsJ7s56jOyiIV/Sqw+3Uno4/DnjsuKW5YDDZ5DNNKJ
Ls4DrOgQ8K6vhFDccLY6E220cEvPVVfV6Xk8Lr+GIsN6gm/CG4dELnvnrlGyCqBJ
+9734OCjaK2eRw6UFN8ICg4I1TsPTQEdkfevd47wjCWByhmf3W/qnaKqSOR5P1je
kEdHHAu91uMKeEXHBPyq4yfKBwUHjcIZVo50tpPH5g+TDNDIxnzRe6SAgrfh6klL
0q1dIZTj5FjqYn1Z7D/LpYM7AxtrCRhIOgteuDd3XBBZIJWXGqD0KRT4XXOQUgcr
NBRV6MCsNRg2Ur1NiEg0zKE1p6DUKUALy+ZY8poGNHx2S1bHKr6DKXKGxDygcRKb
QlyrnQr8jsqnK02OIPnXp0FbHd8aGCIPym//UkbKNYICs1qhtnb7vg5T/AadhEJJ
4Fjx6cjgKzpU6Nm1RewPJFOXqNMgZ8tHZ4Ylv79nHTEmEwdCWmOgzu66ldh6pdX+
1eWl+2JblvJ+tGVYW/sqbuOrITHFKO89pSNoVodujW/jQpQ6YG62uN3j5r+V0Nkr
9NnJNDMjmcz4iyr0E34xc+U3DyXCjuI80ui9kkzoczKlcEWjWgKy7Y2ACOPD7lRm
tGa3++wXZGf/ohGs2837T/hYbVgXUBCTu4dLmmLKOoZKnh5iz+0S++m+wMlUL9Dq
DepqzQH3yvybA7LPf4e/tMp9TovzTSbCCI1tv7BFA1yGzWHT0hGCkjzMg+7IJsx8
LjYX2+VUqOnYol/roS3G2c2qDk5tvp/udQEZGkpzsaP0ByhM6JGcpTzK1k+vnln8
3t+1fmSX3V9IyCrw7W5ugy5BJJ3oWN4X+rYfTbZmGU4g0X0u4oN2VVk0zohXjGou
2tdbOxJGru4oUtxgTk2TQ2xjApCcFaMz2BjkPxbUPPIjeXjfI/mi8fQ566gxqtPi
pZwskNXtMTSg2azMf5c/Zzy46uINm0GrAlYmCVUgFY++L1uNiZcagw0ciQ7xfJLp
cArYwFweBSJ6m2O/LYsbxm5PC7Hpn6pZj7lEax0fbWCwhKcBxOJT/pNN/xX5FdaF
NkSVVp8/5Ph9fnXnSk9+J+9rLdV9IjVFazHp7sdWu/RBwbx2b0c8l0Z8P6PuwP/H
GE8LqLpIB5Y8EOHggy9tNyv79ip79TV5HI7c2ueVV2/S6OaIhSZ8pcjF9EkZY0X/
STS+ZvGmnHhoSak7DTo0/1ZlskTKOCNZ5WuLvXd0RFQtmQ22bHT0oe8hSva4n+Kp
kDMeTcNgfl2gIUesjol9gKotWi4LAlhPF0ZRKfvo1UdT893vIh4RSGWyR3H987/Q
5A9RMQFdZ9VREf0ntHegKxCpvFtJ2gbHek7C/wwRX6a/vhbV4KRhT0ufo6i52UYG
J2Ovd6M2x/y5RAhdMSJb6hRQeVjVrhrQvQxJzbrXSJwWdwHlaZjvuY0lqDqMQoHW
C2uvxWOKadTwGsYRF/f5kER9z0mdlZz5RDUsiRVsvLi8H9eCWx+rd+utOzNs3z0y
PfQui1ukQNEiQaju0/UUDZ2ioD90WOg31mZfWTVx4mPkK4dogOm6prl6tTrrecXs
6+5lCPolcEEjZG3v4PdEJAuz9ntkrP+blTAafFVzDJ/2YWitx7CQvdcrzDHFJsrk
84ypMPgJYO/vAMjKFisyvzxMbUF7tO0HXx84H+9tC/Z0dBgTiJ4Lep/eA8O1r1Ps
+UoUzeMoqi9Y2QYI7TNTN/Pjb1UUL6mEMwoJB9yOyayGJoxcBo9Cq6bSmFO/DRFQ
XYuaI+FDwFIdEkkyiolabFRk+Y2E5CLw3MNtuXzJp6h0u3bSuGdwSfN9XYqlGDjh
8LzXo6lxY5JH1xTWQsf3buQAmrqdU/eEupQkzaudcKO6TaRF4vjcZ9F72YVaclG5
sN1aQVPP7vYzIghYjGEMtFGmWjLBh3bK2zAnkinCSoVblIYxfTePrGeIAwsUpTrm
1/OuWKBHxdOmbbLQJ/MGI1MLCiIJAX+GH5PzSBpixj7tS066X4+3mRTZcRqwW3JA
1uzLB1pxzwFjAcUk3WOxpKGcXaxmey2A6wWGkdjdL2FzIk+N5S281XiZVE9KBW97
7WCVW9WBy2+vHnQzlwMTxOeTkJCq57nWs7oHvJRaZO1W1Bbl2juMjcLp8GmA2xwB
tNY79BLceseJANcmiZz394WUvgLi2I9dxe8/8slvF7OsKonLzqdCpj2mhuyD0Tf7
8A70A61qnNcIErsfzPiyuw==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
Y27KIRKJjtKKh8+JhaOdD1HnMIAg1vAy91sb3yHSrZFQan4hrYUVe/4SCk08lPaA
PXSdtIBtBRQob9ZOSyO3lWXXTf7VA1SuyO4smLBwKsVdJOpkfLkl1gUwN1mjEhOF
cbprpE2BqJo6CbKFweajrCBc99YqxRgKnoAI1L8K4otrr4N/DN5JZmawAEUyKcTe
2Hq0vo+1GqvWw/FcUEmaN0xyzectw1YN5gkEW+9fdtQ/3TbGPmIQcNZlztvxAFF9
/bg9GpoVg1wXW6EiStOJXjquDqW0f6BwtmMt4jHyWok+Ep7ra+kkmyMPjADxQ9fT
XJcvfySoe3fbipaNYrwf0g==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4640 )
`pragma protect data_block
[encoded data, 6240 characters]
gPpRYQ0XCX0xiFJeiA8XfEMXFbjeZXjqumdVsaQCqR4=
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
a5V59/f/XBP/nAjarrsl/GQE8850CE8/fC9FKCy4HCDI+XK1qV8AJgmf5FwFbWkE
t45Zr7GI0Qj873B/LA+xlMjZPTl7Fsk9phWnOEFvFSj660Xz5NkKWd6uEyrc4ogU
dh17ioFf59d8S1h6kzq2FA7cTB9mh4VhJ+vi3DMLhYT0HGnL2tOAjQ+tSoPZNIfL
Eh3bbUOr39mLCZWK4W5jFYfYM/mBVryryNU5TJoaskxq2yi8b7W2mdTpHuwq/KhT
ZJsQXjxLm60Q6fplv0BsXxvFsgw9WG+JZ/fTZrODEz1MixxuM1QdPE93Nv6ct/9X
kVFYzxNo5gTVWvU5tCqF9w==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4800 )
`pragma protect data_block
[encoded data, 6500 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
n0jqjnfqyF03TrdlGtL2vaRSLWRFaTNK0YPdtS5NLgMBZqaZppLQWa+9QocgYbSa
c5cdHxHlVdxBv0w2ht/Kl0AnnTa3zXpQwpzLm+QZYWERA6CPGQ2iCknciqjkTANl
w3ursi1XnXRnebWfdtyjWpIs4UEfytecbUyUvUD4Ou8xwEqHD82QUpgoF8S1VErM
TXlUFlA+KLqtSnjxLsCJWgZu93+NcfAIrMnyVTMIDYSvq9EdOIgJGV0Hy9Y6sNhU
R06ok2RfjzN0/k1pZoWUA11e4xpRLWuvboDVQRLS662Mr+qC7GUzJw4KP0STpRtl
4AFN5zfv8ZpmxOv7kLZMMw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3936 )
`pragma protect data_block
[encoded data, 5330 characters]
`pragma protect end_protected

//pragma protect end


// Module: efx_pulse_sync
// Description:
//   Safely transfers a single-cycle pulse from a source clock domain to a
//   destination clock domain using a toggle-based synchronization scheme.
//
// ==========================================================================

module `IP_MODULE_NAME(efx_pulse_sync) #(
   parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
   parameter OFF_ASSERTION = 0
) (
   input  src_clk,      // Source clock (e.g., tx_axis_clk)
   input  src_reset,    // Reset for source domain
   input  pulse_in,     // Single-cycle pulse in src_clk domain

   input  dst_clk,      // Destination clock (e.g., tx_clk)
   input  dst_reset,    // Reset for destination domain
   output pulse_out     // Single-cycle pulse in dst_clk domain
);

// Toggle generation in source clock domain
reg toggle_src;

// Synchronizer flops in destination clock domain
wire toggle_sync;
reg  toggle_sync_r;

generate
   if (ACTIVE_LOW == 1) begin
      always @ (posedge src_clk or negedge src_reset) begin
         if (!src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

     `IP_MODULE_NAME(efx_asyncreg) #(
        .WIDTH         (1),
        .OFF_ASSERTION (OFF_ASSERTION)
     ) efx_asyncreg_toggle_src (
        .clk     (dst_clk),
        .reset_n (dst_reset),
        .d_i     (toggle_src),
        .d_o     (toggle_sync)
     );
      
      always @ (posedge dst_clk or negedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
   else begin
      always @ (posedge src_clk or posedge src_reset) begin
         if (src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH         (1),
         .ACTIVE_HIGH   (0),
         .OFF_ASSERTION (OFF_ASSERTION)
      ) efx_asyncreg_toggle_src (
         .clk     (dst_clk),
         .reset_n (dst_reset),
         .d_i     (toggle_src),
         .d_o     (toggle_sync)
      );
      
      always @ (posedge dst_clk or posedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
endgenerate

// Generate one-cycle pulse in destination domain
assign pulse_out = toggle_sync ^ toggle_sync_r;

endmodule



module `IP_MODULE_NAME(efx_data_pipeline)  #(
    parameter HBP = 1,
    parameter DATA_WIDTH = 256,
    parameter MUX_IN = 1
)(
  input               upstream_valid_i,
  output              upstream_ready_o,
  input      [DATA_WIDTH-1:0]   upstream_data_i,
  output              downstream_valid_o,
  input               downstream_ready_i,
  output     [DATA_WIDTH-1:0]   downstream_data_o,
  input               clk,
  input               resetn
);
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
Tbn82pu1TrLaH1marliQQwRv6gzQe4dLZbiaDdXI02ngU8GuXkrBXrMRr59b8z1W
VIDY04CDkib1XKwCnqKuOtwgLQ/IobuR8kVjPE6ORJsvRt7mgQZvd/BchqA7xGTe
USNNpjr8UPcpm4TNUTSau8V+9NUwFPyfZUDNuTfn9lcVyh1GKfhuCSdOBVUGzowg
Yo2JYOXIGIe/6FNi+6Idu7BDrgP6B/tqUcgYOnOYaioNvjCVcE9IXQULrsH7905T
hRKI25jvxMb2xnPR1/OvJwvf3vzIGlTkI0/MUkLFw4CYunwAwaCezIKHR2zeInPj
1mciaJyvntFSiQitqooJ/A==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2352 )
`pragma protect data_block
mGWPxotsC84tGPy4dIPR24U+6eaeMCS3RaL+7mj+l/0NV5umZXIMZOL9aL6X/pYh
R7VswRQ2NuoRjdYZT9fNqhdVYdmFKOaB5dOHdpOZtR0N2Rr35MfDl3yGD6z3nO+B
pc5QtTGnbZh6oM8XxWMfTK9v2XBkpAT5Q/M8sHvLCrR7Q9epwEbObtPvpzxT6NWR
nE4lil+6niY/H7wthGyf4CyKAf+rofC6yPexYTBUcrIZ1dV2AKIr5ewq//pZNcwo
tLEG0pezqmJavbBPHT4ZuYuVESYCTOlCfG3+4kPfEh61KpBFtteWcwZSHrAKdbno
m0+IoWUq539G+Bm+2iZvzBlGQOlEhvUTC9L4it4BNQNaeQHl5cOqODIOyTOIGmTQ
+QvOsgJ5DM4n2b2ZePs7DEpiEqDeJY0cQN9MOb/9lgRV9BDVgxg2YXr5Cegs7gF9
xXRoRPK+NGswnTD+F31eYl60qXnuM4sqYSaRAfL5UuUfGwHadHCp+34aYrhr4rMP
8VULb/pgo0Th/+QU9URy4jyKx0bOSwJn/usBr9rYEvjuyDn8JpaIdTnnLPferggs
OUzHF5ykgtk3DexdIGVZzJbU/KOspEOS2px6mjXtgXNMpXiPz/jUSxMqg+ZuxXBQ
bQO0fVMp6rnq7ECjmyhjxjmdp4WGZtylOqLThE1TRHA01ChSZdU6jTJDcNpWKG59
b1tNHxYsf04tyZVCtclhObbHwP78JYOiIsXl3Nq8mf082z6GjHFQqvAV7rPgrBnp
g4QKfcyA2pPO0Ji+JaC7DMTXjE/gwoXDEWItiKoGLHPgcHhOKMY31avm7t72Oh+6
HkmBSnYLhhU7eemM9ByorTew7AbWWl6j0R3bKlR8ybjt4xsptOnmlYnj8PNWXaAK
ljd8k1pVGfVW2hm/NwAvDNFf8SHY4wNoD2h61tlSb7BMxXHOv6OrFZWOHS1Gbx1q
MRB4sU8zYk6hqA8krlvovS3vZuMR3OFhw1SMD8S9OMn9xkU4t0ygUf6FcykwhcsN
kBOqiceP+jFNE28wfSFwD/hzfVnYDAzQp6AxlUL6merZyoYYPHLZpPea+SaTSczc
zT7RmDDRdG2hSIBMu9KTPJan3l4UHErjPudmN0+3SyZ4L/qlXwhVHE3ffSyXNp4x
VX4v9GBt2/6FmR3MjaiLbeLt0bUbSvDULhqniWM9SHLNXKywYlVir2cHcbn0Cf8y
gyBdb/fsgKr+Yawvu41iUeJ49sRnitJQbaNBDZswzTjPkPPbwAKDQdcGrGyguJJh
/b/EsoJ4YTKePY2Z6sv+1tlhaJUauV3tB11NoTNCvc2rn3lwNIOH6mLsxjFebQY+
m9WMgTBfFXBG7BJ3Ss230pW6+pEJpaoJyY1xRsE/aUwyaDnOaNway6bi0GcoONt9
yFvdROQZ+2EzhQcChx2a5AayrVhskQ4TWkES0CO4tjx/t2+gKBdIwDIRzYKAqPOG
g2ye8eezs8oQzb9FLNywPnzdQwjJ8YevmBtUSjowfeHyJhaXtFI/tsYs/K7+RCG+
yG+2H6q5vDsUz8cGpV/SmxUnKQEHit67N6x/SoQPoXQYIRzmKZmlErKoHUJ5gvGC
EObDPDdoJbhwKrN7aLT02ioTkDKXsvaKBBbyAHIen56jGmL0no7I5CD/Y+n+oZtj
RJhXRVeYMkisayULbTj4Gri1nkm3qFbulF2ytEbGYz4XM5VQZFF/hc2sP9Hmd0ur
IhN//AbA6n9ypIyDsysp3ULG77xoIYpeEnHbtQGZUNrIFPoTUWuP4Pqw9JDQ5UdL
IroehAksepDqSpIMIcjW7uFqos6xV5ByWMp0MyctulpleYS0MoVpBJCZQnCGrIqd
GW4wd7kBEo8zeRvctrmiflJkoeWi4NgenrnCzFvG0/o4qaSy7mr6jMgikmAKdjDw
aA3osQ1R9EMfCtZWDZ/ZpZkE+u2agZS6fVZweYsY6v0hZN1xbmbiDl+V4oyFjL7e
SoQ2rmVQcQ0xZ33BcllQABe8SyNG7voNcHzqkAZ/NN+6CqtOfRVEWUPjFYyyQVBB
v89N4kuZ7aeBzkJ1Kuey8qYsi2l4Xq4Dws6gb32FpUA4ylLmFxH+YkAUcv8z8j6J
LX3LO6QJ1MsSld4Fra76kjAAwZZ9ocQJxN9XfrMFjgZff75q1OfZA0az8HYK68YF
xfWFnPJPNIR18s8jCp+jHs9w7a3/7Kfz1FYFWotuk4cYRqDl8j+QxgZPRNKpeMsM
Bv4FJXWc/3mm6a3AXeh0TRBh7KjI3LpxtMmSCBLsU3dJ+6gDtsg/hUt2+u8qzR7m
jNUkGVLVVwRXrNtJT59eBQrs8TfnaaUT2wC7c3IKz69wHFGo4NteP3AYSl6lMG5K
1opG86pzp5MUoXwpU3byhaB161l+NsRBTA6dln4CjeWqjoifkutF2L3MX9WKzJov
cMFphd6JhkixhCQk13SS+Iblr1ddaEIkFX4Nl1zwUD4avkE+kOpZxKAeqEdayd2V
x8NvYx2ChV8e4G/qA/5TDdF62gaPzxhcd+1iCi5jcsqTHposrbCm6SXT7arzh8Um
LcAcxCBV251uT0i5R4H9WWobpghMjev4M8ajG+OSOMdg8Cksu9eZoGiN3tdrocqk
gsj/0rPvYhUqko+LN1jWBZIApVQbBKxfbfUPNgEKDfVzNzhprOqzBJDIYPeJdOYW
6UCDQVwlTMEM6XKdU0MTfnJ4yNz53EpmEBAESJ3/K8f73bbydoUzMEST8axxX64+
YRSmyHz8Ihwz7LkL3MGA1s1ygXdX3NSpvUbDmel4+JxnHas8+D9LBBXDd/wdDzSv
ITvT9m58r9+L3cPdagA186upPws3u4bEBmTVklHtwYc8eIjb6v6MU43HfuHIuCWD
prc/aj3Io0TFSvXi7k2Qp7/fZz5CHqP3FQ2fLOWIugNZoXwH90lcNBpquSGDdHoI
8UDYt1yaanSEcOHmgVg3jTc3UDjjfnH+XRb/3pzNVoOu6UP4GjspuH/SNKWl3w19
0WHHLR40RLGgEvws+X3QfaQqfN8yk63niGSxvQPtRHc0D+kEDg3khIm57tp7eINB
QNw39gPj8Q2jN11aV6VdGWfEFLv0ShnLC3+w8hnv+kIb8HxmQC0kFvijzUoCIu6v
`pragma protect end_protected

//pragma protect end

`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME
