{
    "args": [
        "-o",
        "gTSE_core_fifo_ctrl",
        "--base_path",
        "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
        "--vlnv",
        {
            "vendor": "efinixinc.com",
            "library": "memory",
            "name": "efx_fifo_top",
            "version": "8.1"
        }
    ],
    "conf": {
        "SYNC_CLK": "0",
        "SYNC_STAGE": "2",
        "DEPTH_2": "9",
        "DATA_WIDTH": "16",
        "MODE": "\"FWFT\"",
        "OUTPUT_REG": "0",
        "PROG_FULL_ASSERT": "128",
        "PROGRAMMABLE_FULL": "\"NONE\"",
        "PFN_INTERNAL": "127",
        "PEA_INTERNAL": "2",
        "PEN_INTERNAL": "3",
        "PROGRAMMABLE_EMPTY": "\"NONE\"",
        "OPTIONAL_FLAGS": "0",
        "PIPELINE_REG": "1",
        "ASYM_WIDTH_RATIO": "4",
        "BYPASS_RESET_SYNC": "0",
        "ENDIANESS": "0",
        "RAM_STYLE": "\"block_ram\"",
        "OVERFLOW_PROTECT": "0",
        "UNDERFLOW_PROTECT": "0"
    },
    "output": {
        "external_source_source": [
            "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv",
            "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh",
            "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv",
            "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd"
        ],
        "external_example_example": [
            "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.peri.xml",
            "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.xml",
            "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_top.v",
            "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_T20.sdc",
            "gTSE_core_fifo_ctrl/T20F256_devkit/efx_symmetric_width_fifo_top.sv",
            "gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl.sv",
            "gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl_define.svh"
        ],
        "external_example_2": [
            "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.peri.xml",
            "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.xml",
            "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_top.v",
            "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_Ti60.sdc",
            "gTSE_core_fifo_ctrl/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv",
            "gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl.sv",
            "gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl_define.svh"
        ],
        "external_testbench_testbench": [
            "gTSE_core_fifo_ctrl/Testbench/fifo_tb.sv",
            "gTSE_core_fifo_ctrl/Testbench/xrun.sh",
            "gTSE_core_fifo_ctrl/Testbench/msim.sh",
            "gTSE_core_fifo_ctrl/Testbench/flist",
            "gTSE_core_fifo_ctrl/Testbench/modelsim.do",
            "gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl.sv",
            "gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl_define.svh"
        ]
    },
    "ooc_synthesis": {},
    "sw_version": "2025.2.272",
    "generated_date": "2025-10-16T09:35:38.547531+00:00"
}