{
    "args": [
        "-o",
        "EfxSapphireHpSoc_slb",
        "--base_path",
        "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
        "--vlnv",
        {
            "vendor": "efinixinc.com",
            "library": "soc",
            "name": "efx_hard_soc",
            "version": "1.22.0"
        }
    ],
    "conf": {
        "PLL_SOC_SYS_CLK_NAME": "\"soc_pll_sys_clk\"",
        "PLL_SOC_SYS_CLK_REF_FREQ_HIDDEN": "\"100\"",
        "PLL_SOC_SYS_CLK_REF_FREQ": "\"100\"",
        "PLL_SOC_SYS_CLKOUT1_PHASE": "\"0\"",
        "PLL_SOC_SYS_CLKOUT2_PHASE": "\"0\"",
        "PLL_SOC_MEM_CLK_NAME": "\"soc_pll_peri_clk\"",
        "PLL_SOC_MEM_CLK_REF_FREQ": "\"25\"",
        "PLL_SOC_MEM_CLKOUT1_FREQ": "\"250\"",
        "PLL_SOC_MEM_CLKOUT1_PHASE": "\"0\"",
        "PLL_SOC_MEM_CLKOUT2_FREQ": "\"250\"",
        "PLL_SOC_MEM_CLKOUT2_PHASE": "\"0\"",
        "PLL_LPDDR4_NAME": "\"soc_ddr_pll\"",
        "PLL_LPDDR4_REF_FREQ": "\"25\"",
        "PLL_LPDDR4_CLKOUT0_FREQ": "\"100\"",
        "PLL_LPDDR4_CLKOUT0_PHASE": "\"0\"",
        "PLL_LPDDR4_CLKOUT3_FREQ": "\"533\"",
        "PLL_LPDDR4_CLKOUT3_PHASE": "\"0\"",
        "DDR_DATA_WIDTH": "32",
        "DDR_MEMORY_DENSITY": "\"8G\"",
        "DDR_MEMORY_TYPE": "\"LPDDR4x\"",
        "DDR_PHYSICAL_RANK": "1",
        "DDR_PIN_NAME": "\"soc_ddr_inst1\"",
        "INTF_AXIM": "1'b1",
        "INTF_CI_0": "1'b1",
        "INTF_CI_1": "1'b1",
        "INTF_CI_2": "1'b1",
        "INTF_CI_3": "1'b1",
        "CO_DEBUG": "1'b0",
        "INTF_JTAG_TYPE": "0",
        "INTF_UINTR": "9",
        "PERI_SPI_0": "1'b1",
        "PERI_SPI_1": "1'b0",
        "PERI_SPI_2": "1'b0",
        "PERI_I2C_0": "1'b1",
        "PERI_I2C_1": "1'b0",
        "PERI_I2C_2": "1'b0",
        "PERI_GPIO_0": "1'b1",
        "PERI_GPIO_1": "1'b0",
        "PERI_WDT_0": "1'b1",
        "PERI_APB_0": "1'b1",
        "PERI_APB_1": "1'b0",
        "PERI_APB_2": "1'b0",
        "PERI_APB_3": "1'b0",
        "PERI_APB_4": "1'b0",
        "PERI_GEN": "1'b1",
        "PERI_UART_0": "1'b1",
        "PERI_UART_1": "1'b0",
        "PERI_UART_2": "1'b0",
        "PERI_GPIO_0_WIDTH": "4",
        "PERI_GPIO_1_WIDTH": "4",
        "PERI_APB_0_SIZE": "65536",
        "PERI_APB_1_SIZE": "4096",
        "PERI_APB_2_SIZE": "4096",
        "PERI_APB_3_SIZE": "4096",
        "PERI_APB_4_SIZE": "4096",
        "PERI_FREQ": "200",
        "APP_OVERWRITE": "1'b0",
        "APP_OVERWRITE_PATH": "\"''\"",
        "INTF_JTAG_TAP_SEL": "8",
        "INTF_AXIS": "1'b1",
        "PERI_PIN_ASSIGN": "1'b1",
        "PLL_SOC_MEM_RESOURCE": "\"PLL_TR0\"",
        "SYS_FREQ": "1000",
        "SYS_FREQ_HIDDEN": "1000",
        "PLL_SOC_SYS_CLKOUT3_FREQ": "\"250\"",
        "PLL_SOC_SYS_CLKOUT3_PHASE": "\"0\"",
        "PLL_SOC_MEM_CLKOUT3_FREQ": "\"250\"",
        "PLL_SOC_MEM_CLKOUT3_PHASE": "\"0\"",
        "PLL_SOC_MEM_CLKOUT4_PHASE": "\"0\"",
        "PLL_SOC_SYS_RESOURCE": "\"PLL_BL0\"",
        "PLL_LPDDR4_RESOURCE": "\"PLL_BL2\"",
        "PLL_RES_ASSIGN": "1'b0",
        "PLL_SOC_SYS_CLKOUT0_FREQ": "\"100\"",
        "PLL_SOC_SYS_CLKOUT0_PHASE": "\"0\"",
        "PLL_SOC_MEM_CLKOUT0_FREQ": "\"100\"",
        "PLL_SOC_MEM_CLKOUT0_PHASE": "\"0\"",
        "PLL_LPDDR4_CLKOUT1_FREQ": "\"33\"",
        "PLL_LPDDR4_CLKOUT1_PHASE": "\"0\"",
        "MEM_FREQ": "250",
        "AXIM_FREQ": "250",
        "CFU_FREQ": "125",
        "DDR_FREQ": "800",
        "PLL_RES_ASSIGN_2": "1'b0",
        "DDR_RES_ASSIGN": "1'b0",
        "PERI_RES_ASSIGN": "1'b0",
        "PLL_SOC_SYS_EXT_CLK_SRC": "1",
        "PLL_SOC_MEM_EXT_CLK_SRC": "0",
        "PERI_SDHC": "1'b0",
        "PERI_TSEMAC": "1'b0",
        "SW_FTDI_CH_NUM": "6011",
        "SW_APP_SIZE": "2044",
        "SW_APP_SIZE_CUSTOM": "0",
        "SW_STACK_SIZE": "8",
        "SW_STACK_SIZE_CUSTOM": "0",
        "SW_BOARD": "\"Ti375C529 Development Kit\"",
        "SW_BOARD_CUSTOM": "\"\"",
        "SW_FTDI_TARGET_CH": "1",
        "SW_FTDI_CH_NUM_SOFT": "6011",
        "SW_FTDI_TARGET_CH_SOFT": "0",
        "SW_FRTOS_APP_SIZE": "16380",
        "SW_FRTOS_APP_SIZE_CUSTOM": "0",
        "SW_FRTOS_STACK_SIZE": "4",
        "SW_FRTOS_STACK_SIZE_CUSTOM": "0",
        "PACKAGE_TYPE": "\"529\"",
        "FAMILY_TYPE": "\"TITANIUM\"",
        "AXI_PIPELINE": "1'b0",
        "AXI_WRITE_BUFFER": "1'b0"
    },
    "output": {
        "external_script_Peripheral_Generator": [],
        "external_source_source": [
            "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd",
            "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v",
            "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v",
            "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh"
        ],
        "external_script_PT_Configuration": [],
        "external_script_Peripheral_Post_Script": [],
        "external_script_Embedded_SW": []
    },
    "ooc_synthesis": {},
    "sw_version": "2025.2.272",
    "generated_date": "2025-10-16T10:03:46.765007+00:00"
}