// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.288.2.10
// IP Version: 7.1
// =============================================================================

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//                                                                       
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//                                                                       
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.                                                
//
////////////////////////////////////////////////////////////////////////////////

`define IP_UUID _4c19f37180ff465ca20760e199a0613f
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module gTSE
(
    input mac_reset,
    input proto_reset,
    output rx_mac_aclk,
    input tx_mac_aclk,
    output [2:0] eth_speed,
    input rx_axis_clk,
    output rx_axis_mac_tuser,
    output rx_axis_mac_tlast,
    output rx_axis_mac_tvalid,
    input rx_axis_mac_tready,
    input tx_axis_clk,
    input tx_axis_mac_tvalid,
    input tx_axis_mac_tlast,
    input tx_axis_mac_tuser,
    output tx_axis_mac_tready,
    output [3:0] rgmii_txd_HI,
    output [3:0] rgmii_txd_LO,
    output rgmii_tx_ctl_HI,
    output rgmii_tx_ctl_LO,
    output rgmii_txc_HI,
    output rgmii_txc_LO,
    input [3:0] rgmii_rxd_HI,
    input [3:0] rgmii_rxd_LO,
    input rgmii_rx_ctl_HI,
    input rgmii_rx_ctl_LO,
    input rgmii_rxc,
    input s_axi_aclk,
    output [7:0] rx_axis_mac_tdata,
    input [7:0] tx_axis_mac_tdata,
    input [0:0] tx_axis_mac_tstrb,
    output [0:0] rx_axis_mac_tstrb,
    output MdoEn,
    output Mdo,
    input Mdi,
    output Mdc,
    input [9:0] s_axi_araddr,
    output s_axi_arready,
    input s_axi_arvalid,
    input [9:0] s_axi_awaddr,
    output s_axi_awready,
    input s_axi_awvalid,
    input s_axi_bready,
    output [1:0] s_axi_bresp,
    output s_axi_bvalid,
    output [31:0] s_axi_rdata,
    input s_axi_rready,
    output [1:0] s_axi_rresp,
    output s_axi_rvalid,
    input [31:0] s_axi_wdata,
    output s_axi_wready,
    input s_axi_wvalid
);
`IP_MODULE_NAME(efx_mac1gbe)
#(
    .VERSION (16),
    .TXFIFO_EN (1'b1),
    .RXFIFO_EN (1'b1),
    .TXFIFO_DTH (4096),
    .RXFIFO_DTH (4096),
    .PHY_INTF_MODE (0),
    .AXIS_DW (8),
    .RGMII_RXC_EDGE (1'b1),
    .RGMII_TXC_DLY (1'b1),
    .INTER_PACKET_GAP (6'd12),
    .MTU_FRAME_LENGTH (16'd1518),
    .MAC_SOURCE_ADDRESS (48'd0),
    .ENABLE_BROADCAST_FILTERING (1'b1),
    .LOOPBACK_EN (1'b1),
    .APBIF (1'b0),
    .FAMILY ("TITANIUM")
)
u_efx_mac1gbe
(
    .mac_reset ( mac_reset ),
    .proto_reset ( proto_reset ),
    .rx_mac_aclk ( rx_mac_aclk ),
    .tx_mac_aclk ( tx_mac_aclk ),
    .eth_speed ( eth_speed ),
    .rx_axis_clk ( rx_axis_clk ),
    .rx_axis_mac_tuser ( rx_axis_mac_tuser ),
    .rx_axis_mac_tlast ( rx_axis_mac_tlast ),
    .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ),
    .rx_axis_mac_tready ( rx_axis_mac_tready ),
    .tx_axis_clk ( tx_axis_clk ),
    .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ),
    .tx_axis_mac_tlast ( tx_axis_mac_tlast ),
    .tx_axis_mac_tuser ( tx_axis_mac_tuser ),
    .tx_axis_mac_tready ( tx_axis_mac_tready ),
    .rgmii_txd_HI ( rgmii_txd_HI ),
    .rgmii_txd_LO ( rgmii_txd_LO ),
    .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
    .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
    .rgmii_txc_HI ( rgmii_txc_HI ),
    .rgmii_txc_LO ( rgmii_txc_LO ),
    .rgmii_rxd_HI ( rgmii_rxd_HI ),
    .rgmii_rxd_LO ( rgmii_rxd_LO ),
    .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
    .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
    .rgmii_rxc ( rgmii_rxc ),
    .s_axi_aclk ( s_axi_aclk ),
    .rx_axis_mac_tdata ( rx_axis_mac_tdata ),
    .tx_axis_mac_tdata ( tx_axis_mac_tdata ),
    .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ),
    .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ),
    .MdoEn ( MdoEn ),
    .Mdo ( Mdo ),
    .Mdi ( Mdi ),
    .Mdc ( Mdc ),
    .s_axi_araddr ( s_axi_araddr ),
    .s_axi_arready ( s_axi_arready ),
    .s_axi_arvalid ( s_axi_arvalid ),
    .s_axi_awaddr ( s_axi_awaddr ),
    .s_axi_awready ( s_axi_awready ),
    .s_axi_awvalid ( s_axi_awvalid ),
    .s_axi_bready ( s_axi_bready ),
    .s_axi_bresp ( s_axi_bresp ),
    .s_axi_bvalid ( s_axi_bvalid ),
    .s_axi_rdata ( s_axi_rdata ),
    .s_axi_rready ( s_axi_rready ),
    .s_axi_rresp ( s_axi_rresp ),
    .s_axi_rvalid ( s_axi_rvalid ),
    .s_axi_wdata ( s_axi_wdata ),
    .s_axi_wready ( s_axi_wready ),
    .s_axi_wvalid ( s_axi_wvalid )
);
endmodule

//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
sLQfPbFHT4IbfnXBn9Hkox8G8bRjHwFQFIGDOrTJoSHCqYYXdoRk24dJuACAksHM
J57C0s8CHY2Y2A9VkbHGWYfap0I/O38JeB29IGcr0rRyL6g6KwXeaCu4tP1LM0xW
jRqj1frmj0piajirb5BwEBFDR8FYPTbJiAURMPMhRcQ=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8512 )
`pragma protect data_block
[encoded data, 11505 characters]
VQ+DF+P3OnGBV6yoAijU+w==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
L9bRAjOl+HUoyv55kXx77WhPg4FPOi9EpLW0iHc1x3oUQJcRH9s1WP5WiMsCkWzy
vQdpB7ALDfVOXtf0aXMkM4dnwafPVyu17c2A5piBvwLriI4UlCXHwqVRIt/DETxB
cHsuVb6IgzCe1raSsw+p5GJOIp2BZzOPBnQmK3plX4g=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 432 )
`pragma protect data_block
GR75OiizxwuqBYm8W2OCvDt7Gp/JLUCng3XIOwuoCquz9N1CsumV9nBJAcV3de45
id8UkaoJlIXWusJtLMNomImDgf0l2altdxaPVcXQQp3Y1oSTC8L9jqy/a8A4k8We
8uNmK8cVcLwoyFVckpMz8E55Kpp6xDpu+cUrCJ4s5PBzAZj0X614zftp7cZ5pYBB
Ku6Ag68q5N9RAQ56mvKAeXvRfI73xYHaw+YBHvqP0cg3F7uIkRkdkg+IkbiIM1Sp
nVvXsTA3iHu6f4J/41jQK4qJ9xMtxSMIFeRJF9m5RpHNWcmPb/0NVbbF99MTZkPu
oCMR2jR2wN/gFu0do5llaSxzxk5Qhj0uE+9hGWquDsgT8uDD4yo9WX68kwvyGH69
oDbPB0wN6KMadAx7E8azdYXF0qumbs6bZv31jbz3fdvMirRklH6j0qMppe9Aeg4e
MbHWMKMWmxwhoBLxgRayVPHOJw+YmMDrsqun5cp/RwcUq0LIk4vzc/MwJ9MAuCX+
X/nqs0IuMQtGlc7zfQBKTU/IZP/j+n+/tKy08a6jf7I7rW5BLQFERzF4lpX+hsYK
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
j3OYiaKnvM0NoUu4VCtliANf7pOIu/oKq5oHz8ytDRTuGg+fgZuZJ8MSZY07VFOr
IEBxW/zEZpTXwWNwPNYJLWgLohbDAZnlt+ZOZDzlYB698+P/yYmh1AG4Xivr9gEt
Od3PnfyWbasFQXBERii6jJEWjsCSs9ewKfaCCz4zc8k=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6192 )
`pragma protect data_block
[encoded data, 8385 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
X03DOnX7gcXRTMM2MXt98PhVj888pM+Nxzjdgk+kKVbimAfdmO4QqveDaUhzZAMb
mmV/QXT7nYdJ4A9Zd0Bno/L9Wew8PnstO1OwNl6/UydPwYyDryRNO5m2NT+duD3+
INn3SJ5fz9sIZDM66fAP30DL9seqfPPqsANiQJTJNVg=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1152 )
`pragma protect data_block
7EG+NzDBqN+I6QKHeNERJ22nQ6iQ64Ehxz9Tb52PPYm91zsG7n2MAKXn0rF96cfO
9fFLcNO484o+9XvmN1gsocAtRfXQDcKfBt20FFXWSs5dRcLkWABhwIh46FqbKMaz
P3cpt+qRqlXCjr9276ykbcIeaCngJuxPGL9wwwwDDqxZzAX2DfnHXSVU2pyZNpBb
dMEWkp1ibyPRNIekdVkgG5l8cje/Yhpsi5vAEDeA0hqIK7LP14y/0o5+VcKH31Tn
iywMNq3uubwR+f09jVZ3rd5c124KoL6vKnSTLPHMEnYGph7Ja5OG0UJolpHv/4L+
nK8ysjPqtL5GBiqO9PEBU3M+wJDL8OZmDUwPlHd+pcFsA+OscJJC+GlUrPyRaIHv
y7gHfqWf9dC85z2BLMU0mDCrGbyjRqJbsjm0WyWE0SsWOXR/vCUfxmVliNS/wTF5
FZfa8jLtRDCc34vvBqQoJdG/hIRqqflLVxThdHyG7UXOjS4ZnM970dxDvPF8n4rA
CGgJuuAME+1rbJYQGl/K/+7BuGUIsRVM82bQZ4zXF5Li+5+waDaMZhkPPCmi3W+F
G7sAGD6y1/TU04w3Y0878SngbuN/ljpssdc2JTh0A3NAwDyvfvwgE4OUW1IJTrRR
Zly8+7nXHI145SK3qnFlJQyDeB7ixnADkkHSLUNu7iKKWHVK3T6DUktmAklsV3Fd
KvgOpWmA6cZwOil8CRvamR9cidqUZrJc12zF8HS8E3glXg0pDydLx2O5RbvC0Lcl
zoG0ze2OUuuHC9lUweEOK8IPuFGY3EzX2XIex0djLh9T8dW4pix4Y2Gv20ZfEtuD
xZlhqtKmgzv/T+QgkCNacMIzS6ZIcGcpXOWrVTrZsisCwZZiEG41XUe3gOHVKMiS
dNBpU0fLIjPGlcQ9x2v7l4hPEV8y3DBQRCzNpMuXFIm39ZAjlD1JFtAL3nKdjGQE
kZFhcHD6O/9AjxkYzFV/iwP1ui9GZ+f76jnNj+oJMM2pwjfrV2CqyppT0A4JHvqI
7UnRagQCrDQZr49z/CHD1536oFWWD69OvakaSpG9QZLYrTGn+qshDyy+DT7VrfiR
ml2w4LS912VlPW0QYonkNMG048wkgd9rtlKbHwqmQWsyKb1i/YITbwItVbUnElnh
ipbJDMO6PFcnIfLvwSI1l03qnf40smUGd/lRvd3w28p8LUObbxkk2KclwmGDX7QF
XPIe0r2DfSTWu+uec5mgqU4rAw98Rh954b5BeWaugAsFpkM1C0gv9wX5Gm13LHIF
DpGG8dCv1GjAQ7529ZmiHyhIiKKKCGhRL8FsHMaStGri4LKy0hcl+GGzr1z2ZNpz
Sz6PnucYK+Gtn6ES0kujZs9DCk1nMig+rZa1FOHYvTvyOcSLNTcPXE8YHxAxSCA5
2zCMqaNvq2ylLu2vQ5DSwptugaWNiRit/S+ueYcjTAg0MjHUQtS2MlkHIQix2lea
3KwGb80jHq1sBu2L2nfKpaHe7CKRVstfmTYkbBfp9URCb3cns2KHSlQm52VyjyCz
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
UuaHaXzeOiZ7NaeZweb+R8hRUkyfyfnWrji8bpXwkCuMpzgOz5w8FnJ6mAtpgFE5
TS9pWrtEmzWKd5AyvfRZCt+Boecgx8FqFt3fYC79L7T+cnRZ8Z3HxZWFjgJNOyxv
9/UD11nrc+6i8g6jxOyvNVvxC42aH+8LwYwjtMEZNcc=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8208 )
`pragma protect data_block
[encoded data, 11115 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
pD0hYfITXNpcZzZ606oJ/smXe8GyLPdPoASXSxDd+zNtDaQTC5FWWpExGdZZ1rf/
qfHy8iWJHYzf/Xg0ojLa9Oz4Pg5DbdYGPxbqqz9OarPuzL8nm+rk/fetuY4m1moV
8GyBFX/b9QnwGOMHr2VsIMuNF54e/L+BrnXiia8CB9M=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1680 )
`pragma protect data_block
X9YvLvDhVMGWwUsKzDsR8Va2XSqijY5gT/MrGTfZLVT44ihwZbsaF0/TlCH/l4vI
ZcoJoIXj2yyd/wmT5G6C6QW3KJ5Y7BWCbFIrcdNJI9Q6CUzxrg7pj7WOv943j3ey
mQBwkWLx31MU6WVXJvINloKH0sdHH3h7UiQRaQpkZWXnqC4lLhoI7t/flFSttn06
OOIsCI/jT7/NMO3BoexoHWbUvBnpF0hrqwTnZvPxAX4tk3Q1pXbyLbK4/hYHxD3U
DWm75jFsbeCTsZlPS84Etz0A7hJ8ZqfEreMacAnr00vL7+VYKc2OUSw2iVUwsEEM
sdsCPuVniHNmSZpL4B2AVILBFcAfmnbCLIKkYYPmjooTBhm06/5+IFFD6G0FpTho
hrO02O8CAu6zQo724K2IgTnf7MuVP7HXZBpMOvvAgt4SuGgSM9WMvz38ZV+xJQca
osH51oAwWU1tOhwiMd+HCArk1cbvyBJvVGNCM2m7DT01oe6N0tks/qzZ9pImOLg8
hFEoSnxl+82B8ZDYLRB3rH3AJajDvjU5wo/Ljg7T5T7FV5ezMOepm8qkQs4f7tL7
vOEq89a26vqclv+OVqSamsDnajURTAV4xPlpm3dwzSVe73veVqV/B0YVxh+7Je+M
Larq4J3nzeczGWDqufczmtprXTKJ5pdhDWo37gtGO5npJ3zvJfdBg8deLDnS/1yM
Ev94C943ejtS9pxXh1FDO8JhOiG2lXHSOp2wXfv3qGVeZOSgF+IKj1xa2OQixdOn
jqk2+S8BQSst6IpthqUY1PZT0qvzKObe2jM/RYqG1tcbBVE8uyXo9SbFcAEKWi1u
LvwdiYAA5vQgEownBLF1todYnMGEDobfgLRxS37wximgQUjAfMtO00bThqr6k4Fr
YmTcPBmcpgLvoYvrHqFQ0A+fS8mcFdpMsD2Oiy+cuTAmByDfFaPl2jfeiGDEIT+9
GM8Q91tXX8o95n8kqqySyxltdXdCrfQJSnA3BlnMyBgVyghXmIdFoDoYhvTt2S9O
zB4V5N+A0DTcuu8WQlU6xIx/0DTERTYfoSNdSBnL+YHN/UMJxLalhFTgHE8XYcCM
JFJ/mjVTP4OCi5fCOWIpf8ODSD6JSYYp+IIfg68ocqrq6m1Nq+8RtYNinHgpsLgC
ofxH4izV0yjyKfP/UMLjJziAerqOSnJJPKSTOBtrQNTZ8XWGB9ZQEzxvfC3sstoO
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V8r9XB2l8RHc4e2Pccs5VzRCgXaBESxN4fDtegY1GjfA/kZ31vgFRr5pAINqqsdj
yoNvGSBHirfCXVbhHJlTPCYdl1msgegbPRKvvsXsYa+FbsH1eh8+5fpTFvuto47B
I2H2usy1H627d9fCFpepklDfXG0bI0yDnBOyNmH6BWn/+X7UsmRqQ8HR7vttRTeT
hAvTEwI+LG6k2Jz3ur0O82zML7nR3RxaYhrH+PDJVG3X8a+3e9OWYtxyhilqf+W9
F78uCSgd+DkSy2r8nuSpOMye8u6UM33Cm78BcDGuXgL1fLnm9D70aqu/QX6qp4+V
Q2AH/+cI8jgjMPZ8KPzQop07IZ3AqS+ZPMAn25rbof16udMsqkpyUri5qb0FpoXv
gyUsZZoe5qCNU1gcaP3PudE9zphDPek+ScBhto+EA6lTZ0Uv30lM0xGruL5bNVzL
PrXUWoyB2U1CkaZoDg3hjIOHUq7N5Q/OnWi8o/EI+Rh58taaLiWh3UVT9KsfT87z
AVRjU3GSE1jaJ0z5Pbyoe76NLux81mUurg4HFClHJaVGzGp7f7JBbOq1IilcrGx7
B5b+OvFVE5uOpsgrHzO5KmXgrSZdcu1DINaD9j+FmXLgtEWcByDEYc7R08SPtkaU
G2g/xx6JY/P31Hn8C1kJQIiOU1z2vTBoro3VEm1/4Dyv4O81U7AyrCrYHYgQrKBc
omxzuFnBi2QCKslCPELuQdNsOWT/oudLKAAGzhzw0g7h3BglLIMv3OF0BvqW+lRo
f8p1dB1spRtx0EInaXQETcPyA1Z1Lnr26ku+SxdcbbiYW4LmF6kfOCvOS1r0Q14n
vC681UCpDEQvnwhwjwgP9VaH1DoMeRBVbJPnKjhuwLdHab02aHqwZWPwd1pvoU/S
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
QstAZhgycLSqZv4lCZBRFo/wRrK+PIx9UO5T5g8vaqTwPejmgwjXvtdnzPRbb5ML
4dVuSLsQ5HwVNb53Qh89MeA2WwlfginIn6o3c4IrNnTxcnLMW09MAD+bWWiYwTIw
8WO7BizW767Wjcsp5aR099IgUMQ8d3q77x/OhoR/RIg=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1872 )
`pragma protect data_block
hQMI+J7RFsI8sqJUmUZedWLCNrdAIG1CC+qsjGsyDqDars4QtKturY1G/AhU6Z3v
Kc19eXSE8v+NbphTJgS4i0QPd/YG/87SqE0qp4APnlbjCT6FbcLqPMkmfi19CFoX
e2bFcOL59mvQTQ/w5K7QH47TE1joO2hyx2DLRyEBNdo/nPyOvFP7EUUfUL789HFJ
VdDAX+qDlWVa68jh5H2O8o3NS+FRGUs4j74k0NkeVVxZn/a2NB4qAdeCj2Ge0yR6
bjd5XCribrQ/aQavAPoJV2v2OXTP5ckEyRJUaKczbegZAn8bIZZGlO/3IFeN2L/j
GUoo4LbCaUJAxAHbgz8IM1HIoysf6DuuebcTZH4uW4/YKesx/bLHbsxAYM7iEG/d
DcFiORRksFi7h9hmTNnWvGK+UpGzyeNi15fsgEHNNk3SqFRcraZ6/7vUJrMrIQBx
i3WexC+O48e4CxirzLHgxClF9bfo9KpmQ4RQmNc+hge5LKQVYu/qt9M+IprgB41a
d4AHLF7xjHY5ImG8zB8rpPNxDhBUbWcnElAAaGn5b/61/z/9eR+XDFuFoTeSf7ES
mVQfEuDlItVv4olnCh6F3cbSmYDX/qa6QSkrvZXAJaS7kr8hJ2MFXFeA7e9aaqKZ
Dq+2VAsQi+5ZUe6FdTNqxdwwh4iIrPILG5XaNP3e9lU0njJrX3OXZOvjnlGxvsq6
oXD7BTfUQctJ/hiZSC+N+wN3S6dfOtXG7Pb/QS+Z0cCj6wDLlbRtIySF6cCTCaDj
ynWArmD+UzC1Q4y7ovYs2Ih22/00nlXIKXynmwmdflmPTku2TChI7pYVIx4hZ4Gp
3tN6VS1uVs12KqsX8wsQ5o9+Jm92zV5+Cu7579xp/rUHQNTksnYa0uAClIC5myis
JLHFjjaITphUuQbvaas6dpOzHQCZxu1xBqucFOcFP/9OraqILA+ZFOIK1imB7Knt
NuIPXHQiQfbDFbTE+9cHUUbX3MTxlhuyoztyL6D2/+7NjlenkEVqqFMllXC7T2xI
hq7QBPkfcDgOX1m7nNa7pkTN+jTUi5Z4uPvify6bhv6RLc77rZD+GRgA2U6QNCLW
WGS97vtCV/n6A/KwHwdOw7chfRpBhPrQnFBV7/NQ7hodHp7yyU5dEqMmnc/vuJ3s
RuyDvK/mR8f9w4Lg6bUNP1L8b2DCllgt66tcNDT+XTwPmEOttjiih80Qx00xh3BN
uG1fccTVtseZ+5t0C1WFzsS76a4CDYhofCWCKKgArxbzTTAJ/EQgRyFBmmzEkrJd
IdwPWcuQmjhKEBQotiHiCoUwmWwPyXgRDKcJD98NRFzxk4G8rlzEWIAFdBNBBT3i
7wnTt9w0B1Z1+izvjj+6DRl/heOSy14v+1llgqG14ValLM68EGhZ09WeUXmtXpdo
0GEpxkHKNnAVGyZ6+uR+vFQczXwNhngwhbn74n/Mukm/7f2bjAul+ZjOGakti7NG
rsdrPA/w/63gf9d5ijHzrgYhTZhSOOaKPph/w719lohCEXj4HtXJ+5/XGhlPcuT1
cP3cflKc/nbvuFiZJFeqDkx1f8W5CvXZbKMrgQW+VDhaSRFWKGgR/DVSp119II+X
5bpbN6lP2zU6KmMBSowMy1mmYm4N1IEsRfXSCmN51Cd2mLRW0+MvXYh++6m5m7zp
AyJJ8kkGT5VsJmjXvjSBM4n7GoUCP9yGoBbclwI/kjIqqsVBVgxHaey7A55hWWzk
xGSYsFrydwj8lTIOYU52dCJZcKszsk+Nz45sddzg1/+DPpHdKHSFUCHhEHrWbDwT
7BAhWekd/6si36RjgYWX1Q7ZeR0/PEF036GXp1euBwt8JQxNahcZZqtNKjd02/bb
rlLMWYqnXTAKA8JJCG9QCeJZIswHoBRYO3l3H+1HNl04idVWyjsiHnjlPbzK64ap
bRdzHNI6UHU71ZCioo+vErWrngejTUiWt082qDSdidV/YtIvGFcrMNq7eITm8aKw
eD2JWyvFmaLyonvA3PehLhYJF5D4c8V4GQjiuY//gZaxRncDoUvjuo35L/CFoS/O
oIBa0AErbtP/ZRwRYEy4x6a57QGNpWlxnLZUGanj0k1u5G6NThk9qY7UhBzkAdFM
1fUFKb90llKmrHF859AvsLWc2KamVPg2fd4mIgDuzLQlNYIeViabKSfzQNAkWeeC
TFvOwn2Di8TgL1/N1SEhUJtRB1UTi9/3UN32HlphPx/WsPM0qEjtvBSZoDkOt1Gh
TmN4jDfQOPmHFBFlriTEGIaF2sEaAwW5gpO+Cf6TCBW1EkrFldMTXTiZyU4wYezh
AjhLzmquk55MrJnLl4xJ6pDwtN3fnoJKtkymRpe7ze5naUQci03vHRL0+ca3A6Jm
JRD5fmFwckqWX3YeFigaheoWdmylWnSNJ7Q3+ev0t3QUxPUT8Tgxw7icy7gz+Rhx
99Oqfr5aUtjbml2r5r0kAu0QIuGIRTJr3pPT/YfTS0B4kE3Ncsg7G+nYIQ4ODNDF
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
MSHitJOTxAEcMMhBpMAw3fXdGlW3/AK04uyTpgbVAcRZpOZz/RUBoURz30r3bQoI
HcBvA0GLI/fPeAPMihXwPJCKFh7bNMGS8vtrXwS3hcpddGNAs1tI6k4rEKEohW2k
X+MAwzTm7YTJdY0mz0fzD+Qjri4rdQSppF6o7DcgFC0=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2656 )
`pragma protect data_block
0H6ycVIQP1nrwrSz8nE/41RdaN/AGJE/4SiI39Xhj4Geqk0scXAzLgJAM7WCcEYt
ROTbMaFmLcbjmY6Sbh76M/YG6mktpwDC4DX2sdGJomzam4JpnladccriWKc0O+Pw
RD4HI6A92Dr3cYEcn5xRkFczGAFcE6hrrZNQ/diUGcod+r4PmeV+yT9eXHF/avkA
HDY5qFQEJx1Z4l0nGOT5DkqFdwrzts0IVQ1TmEcByNWBchIg8SYEik83TxUTsNki
q/miBjEgNa8VO12tta9ZYxRD2eJ1D7yGB5oyRdYqgC8MR+EJHQIDlfZG+cfEsLkB
RHog8F6FPL7YbuyE3AgOwTjkGazOzxe8hpbnBwzs4cakK+KvigTF5izjZbC5jLCh
SF6eA7J2srfwjvGYaUgm2kFUohxkH3a4YADAu60EscJfkb7DcejinsQzVtqVz4+I
lEo9Oe0pgA/h68CPpcJW+5iOPAGfx/MgFBIdhMZBw/KKvL8fDi+tSY0BrXE131+g
AXoTL2BtinTp0SrzxfzmCG+p/8OfizUOEfIuImzzLsmAQahADRLG/fQxf/rDwhUC
4aI0L5/zYeX/T66JiCL9au8O3jQVuHitly/4b8ZS15NKRVo5Ivov/KQjwzUzfBk1
xUUUWjz2vTTpf2WUzag/mvRd6nL/TwDIeYjmFbhKHp4Yfh1O8qwk7sp0cgk9o4c3
1hA/cYkf5RNy/oM9ctLL5pQFil4goJUScoQRNhd/D+D4TEk+SgUIg79nJM4lTpmL
I5JyDV5TgQe+Yb+Xq0mk4eZMrrQFAf4xYKFQ8xOoIlsYfb4K3/Buw1xOuLr5SuZ4
tZbWV/8KXwrViQhVfrMG9YCGdbimv463V8TbKGpI/YAcWGTA3LFqscF2KTY3Psdi
mh38B6yWfihm7yCkXHdYvIIMCa7jpkTRMdLoWDuiLpE93ZY3sH6ETGgOnlRWnFlO
Dyn9M0R6e6iGEidE/p+gvyRD/BL2/Rd5/6sjvdA7xnODu+4xkjVob2mF1oMhv9nn
EzYQT/X/vUDNsqG3IVA2O+ATfco1wNmWWd3aC9a2qekvbgc4ldFEpxgmla4oddk3
dO1D3lsL3iOefUS5sb39J+Sjv7P/6YUP2woEUKb5VqN7/MgKixHbCgeGtrsjrlPh
HFdrawH5zTfEo8oIJHtDZKwpppx0b3UdXbUd6azqPTEMd3NQWpbdcivlMctXD84P
T37RdK3+32Z9zEpZWwuZa3uwmO2peR/d4j0STU2kpE1YU9DVND9ZL07HBC4Pvzn7
6qeL4U1OhX16HgrIzd+j4E8cnioWd3eWKQ35o4gqy+XQJsnr4Fe6CRTAINKRl6Yn
92vKrbswicD19UjS2kTtYWmXjVw6Uye5/6ExxVTKye8a8yjCDvBGZT7dva27sLnF
C3qOOksXsc3ac9rZapAGEwrGuHyOaU+giN1FaMj6bnl9KiBshYQP/jiuyRbmeBJT
U4n+k8LseVMwjMPEdbod3HB8ZTp3OovoXSyLbY7z5o/LIYI1OzmeKB5A4G7aZ0gn
bnuT1H5nm0YSMMmrKhhNoOoIDSzLqhYOzSP75ma0BBPrACKY2gMTRwQHi0bt/xFx
NTwQ79JCKo8xQgPwd5qDCVfkUZh7N9+X6Z3jeLPLlRJY5lIgb4dmYz8iCAbUBm1P
gGd9bNv3Eg+bZhZ3CRYk/adLXSvJMafLN23fsw0KrSNl3OkBs+Pwrj07t40v5UvF
U4UYTVaqDFBnCDhURVQtP4jsH79drC+emjRHoTwu95WI0fO9LdO9rhRh677x4sMR
d7igGRCPeTYYeevOYf8+PBGQS42CWTUmtXcgkdw1fUPVs2RYTbgZ0JXJFQ855aSm
bTnVXtRVBkiIr8G9gnU4oI8uZsjtQeiWFyHIfqzS+fdcprPtWIwN72e9zWcO0Jz6
GQCV0TR/uvEr+SkH0VnzoKKrrlHapLUtkExAv97VmiSz8GbKf3XfO3ukFeIm2UIe
Cj3T09EaC7JIIzUNrZkuh8rA7glP9bSXw6aeVwRwj0HnJCzp2lGL+XxK3iXwcMmN
HJ+RahINT/VnsKUIH6dJ9K53QGRFMgr1WBgjPfTddxvVPJ0Kce06/AHKTvU1JlJL
LMwREmf9iF0p+eO2GbbNSocPAibsmG4J+X9+nsOxPXYD7Rg7OPFCq23wZ8U48tS/
HOGt2O67o6ra3ONFFClXcYlxlCdQ9yFNJsIyoKe8Eu/jKdf0MfTcPcly/u3r0Yr3
fNA9H9S2lJ3K7/WeEHqYTVDXPJ/hvCaqmr+4dXpgpJGGDvu4BDMh6E7b3UlnPzJb
o/B+E9qXM6e5Ki2QV77S5pMLxNh7bdoNjW0k3h0ANsDrzaTGHFD1LKd97D9ekeJ+
y4y09xLQKZkSiFbNjMlCG3tISmtnBcl6pw3xxU41xR7Au1g5ZAHf9BQD8MTIuWDo
MWbYy3IzAXufPEKLIhTKs6tJkk8WioUJBGIXbrTaZgbLOkG+p+FANHlPHuvK+jjL
2C/wiZ4a9ZDuWFnrBy3nEJ/KTeBNX+jwYFfxm5Vjf3ddUy7byXgp7zoOtaVugjsV
+NiPNtvSTYd9+/qOBHrUy8uV+hYQbaoCyRIBEl73i9ql4AJH9Wz9XxltLvinEmur
wMXCrx9/9pS9z+JVRNIW1fcLCjjg9wD40bdlbyUBtfgqxNbJzxVsZ842phVZj+/f
YSEvN9VCiaZKEmmDS7lNspDkXhRwdP8M3Ee6PE1nUhzH7e2qeDGt3bLp+K5SPVL6
l0R8p5Oq+nUs4DTHZpyM6KWRtYeTrDla+p1zKdzk/DsNahAPaJZxN6ZGMtOHAWrg
uwVeqD6K+Mr97T5+/S8QKh2kWC/L7qD2y8fIe/EyWduj2g1Eo8m8Iu4PBU3OPkRV
V+wRFpoxQsj04sqTTgWydL1DALRadNHflPyAmmvlTJ6HY5fr4lcsp7lEl2ER1gg2
7qoLoeCmrnF69rZgRKlCquhm/j6SfbeFiR5QABigbJrXNOmkLoDBXtl+JxECvKIz
sWhV9DzuMuvz5CDRZz7Ds1/VAdQlhnNr7ohqx5yKyPYhaiR4RzXVjPXoW5bm4lh7
EHf/uFYgmNHzkv6ZULpcuu1vEaiJqASNRtS9zFq/nxZDIU1oy7ZzVAspx1iu0MEE
O8ujomctOMbA/L5mwNi7PGc+agTuodEmuD9+2p7UBQ/vyc3WxgZAXEj6MF29A8H2
DXDXSl3ziJD63WxXyI7BOWGGSf/hJFq8S4ITVZUDiWYiOqRRHyNb4AJVLII+1FdE
wGgFUx3d3hzTEpr0IBKOjuiFAmzxSojQMGIvlsuskz0IQDy13DU7aZtObJaadkuf
1ejIfLPhAheGS5oWH0ltlSGLB/yoy3UgFV6lyL9Y+U9sox+WIiwZ76DhFmpJ3LSE
yuQwzTQullhsVLOU3a0yTqfaBpvwpwUjn82oWdJ/H/3tHLIW+83GmlKHJwWngk3j
VAupMbqFwtpVDrAPFKry19zumxxv08XtcA6Z7uD6f1T15QiE7Z49qo8gKh8FGGAR
pIrrnDFKZ6M+/mqw3wek8Q==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
Pr0evHmMtos0YmPup5QQnFYnWvPQyeyG5RizEFMV1FN3g7TP7ZBeBi55Z/HqvFVO
9AscWtl/s/R9OoKoKwHEkarZcPNM3VjGNrUfnfuUEnmbP4M3KFSTgwxJWMV5AETs
Zm65Qe1qeTrj4i5oVwxOWvZPECxu33VDrumLADSu1L4=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16720 )
`pragma protect data_block
[encoded data, 22620 characters]
p0pRvm34P8lGQ+F0nm0tRA==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
s84D+pqqyNKL5jSJS1pRQe6+XKrqK/D7HkIcMFZB1fTUp0zXclY+we6jMje9b/Eh
fV5wTm9vGy6p1tTtcW6QGu/BY0boLo4FLMRrkF9PAbmXBs23rA5X9VpH7pE88IMx
6nHv70l4S2SNnxYIDk8WESkfkVRsy/au+ZQtVL1Q1i8=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 19056 )
`pragma protect data_block
[encoded data, 25805 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
Cj8tD35T05jFrRu7cb6EVNd3vJw2X408CCHW4Bh7I3cCQlVWi3myGsKyifTYqQr1
mS1bugi8L3QoSZ2jORS3+D7avdcN+1GndL1bwDGU6kmAGT/nma1PFqvOOo8Io0A0
biHdGaRoCCvP/vBvv9Rcdqg2JceXm2MM629aHsVQzAE=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 36512 )
`pragma protect data_block
[encoded data, 49400 characters]
xKhNWXsO7R5alWL0882aHGOMntTB2cgR86sEcFwNZMM=
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
eWrLA8wpdbo3OijMPMfutcYUCKRbMi1GYu8Yr1CqMHpO2n3O1n42p/HNytQEBu8/
poD0kqYhm537V1zyOiGmn1C6YgUqX9TbzLIPJsiZDK7tRKDwMFPcim9S9WjxenJ7
KywHXWxf1MEZFG1B/8QB6/tEYgGU+hgJJjT4Jc4G7XY=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6832 )
`pragma protect data_block
[encoded data, 9230 characters]
1sCqNLkDLkxTbmJZRY+kng==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
qbOqIf6MjOwQu0JG8jONqdoSv2BN7ojf0IErrZ2VMI1Q6C1STz+KQ3fHyvxvop+1
GIg3KQZfeoKZlczDtak7GhO4pAa9nviCMtidd7zzNL6AermFWxarYyKPPQNECt5j
PtbL7anWwTaIHvCXnQPCK4fBvQEi2ykaHML6qOOHtUw=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 29968 )
`pragma protect data_block
[encoded data, 40560 characters]
C81Mx6xdw57uXZmlllOd3w==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
Wx0fV/YnQxwFAvRLRJswRNSR2h6Hlr1bfwMeCYEq6V0IAxnsi1oJN5EtK+CtmAIJ
34/q1WNXeUyiyYgjvPtRFaJXGpP3ivDofnscXZue82OD93rK26EIsFMb6cEXBVRB
ViMw/ZETGXn8GzUQTQ8E3irOzHABlq52xpwAJm+6y90=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 50592 )
`pragma protect data_block
[encoded data, 68510 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
VIk3MftzUG1yzD+HSUFjudlGZhAa86V/YPyB6Jimo1XX1I3QbaufeswiH3Uenwt6
7Gfk0vLPxxu+T9GF7sYk8Kji66hwFpQKyHc8IGNuinsQhQUaj6F3diviPweBR9SJ
yqQ6WsY/T5BZm1oWio/bKAnWfvT2iaBtEYf9lx49wng=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5088 )
`pragma protect data_block
[encoded data, 6890 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
bYWJSpX/mXvxJ4bUKiF2XAU8GaXksRdvYYaHe1GlRhk3CmzrYzdx77YuD18ZzhjP
UcqJT3slh452kVv/cBFF+XrUupd2raAS32V9qsGrZZtXp7avrggchoXwryzJUC4r
08dMdEEY5m7Mk669YINSj/ovv7BKJZhV6I1nHXboKFg=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5664 )
`pragma protect data_block
[encoded data, 7670 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
PcyspWqEN0UYWFWW+dU16FNBi6TrVKkPjw7hJN3Br0nPN9gzuGz/MombzMNMR3bo
nYhE1fssfPrjgbiUqKA6jNY2D3M4IqRTzhdPftopGjnrEwxpWkU59TVuqAz1VWxM
KVPLTHVytzO57L+iUd1WO4WyyiQBMXEL6Osrx7QVNtA=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3504 )
`pragma protect data_block
[encoded data, 4745 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
KL4BjpxBykCTbtDcWuq0UG8LiDQE6ZyUxWy9pM51iDr6dwLgh8xVbK7w1AHjyOIN
DWMoUcdLGVQ3TiZAhmQy3mg8DJzXTnmrklXiGOPbWiEekUVhRog5gZk0vfuJZn+h
3pPvyNvb65d2JnyFikLI1nIDsncJv/D9oXgPSXo6lVA=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 31840 )
`pragma protect data_block
[encoded data, 43095 characters]
2ZZ7m2SMCsfvUNfnLkBqMA==
`pragma protect end_protected

//pragma protect end


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_top) # (
    parameter FAMILY             = "TRION",       // New Param
    parameter SYNC_CLK           = 0,
    parameter BYPASS_RESET_SYNC  = 0,             // New Param
    parameter SYNC_STAGE         = 2,             // New Param
    parameter MODE               = "STANDARD",
    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
    parameter OPTIONAL_FLAGS     = 1,             // Reverted
    parameter OUTPUT_REG         = 0,
    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_FULL_ASSERT   = 27,
    parameter PROG_FULL_NEGATE   = 23,
    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_EMPTY_ASSERT  = 5,
    parameter PROG_EMPTY_NEGATE  = 7,
    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter WADDR_WIDTH        = depth2width(DEPTH),
    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
    parameter ENDIANESS		      = 0,
    parameter OVERFLOW_PROTECT   = 1,
    parameter UNDERFLOW_PROTECT  = 1,
    parameter RAM_STYLE          = "block_ram"

)(
    input  wire                   a_rst_i,
    input  wire                   a_wr_rst_i,
    input  wire                   a_rd_rst_i,
    input  wire                   clk_i,
    input  wire                   wr_clk_i,
    input  wire                   rd_clk_i,
    input  wire                   wr_en_i,
    input  wire                   rd_en_i,
    input  wire [DATA_WIDTH-1:0]  wdata,
    output wire                   almost_full_o,
    output wire                   prog_full_o,
    output wire                   full_o,
    output wire                   overflow_o,
    output wire                   wr_ack_o,
    output wire [WADDR_WIDTH :0]  datacount_o,
    output wire [WADDR_WIDTH :0]  wr_datacount_o,
    output wire                   empty_o,
    output wire                   almost_empty_o,
    output wire                   prog_empty_o,
    output wire                   underflow_o,
    output wire                   rd_valid_o,
    output wire [RDATA_WIDTH-1:0] rdata,
    output wire [RADDR_WIDTH :0]  rd_datacount_o,
    output wire                   rst_busy
); 

localparam WR_DEPTH      = DEPTH;
localparam WDATA_WIDTH   = DATA_WIDTH;
localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           

wire                   wr_rst_int;
wire                   rd_rst_int;
wire                   wr_en_int;
wire                   rd_en_int;
wire [WADDR_WIDTH-1:0] waddr;
wire [RADDR_WIDTH-1:0] raddr;
wire                   wr_clk_int;
wire                   rd_clk_int;
wire [WADDR_WIDTH :0]  wr_datacount_int;
wire [RADDR_WIDTH :0]  rd_datacount_int;

generate
    if (ASYM_WIDTH_RATIO == 4) begin
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
            assign datacount_o    = wr_datacount_int;
            assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}};
            assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}};
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
            assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
            assign wr_datacount_o = wr_datacount_int;
            assign rd_datacount_o = rd_datacount_int;
        end
    end
    else begin
        assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
        assign wr_datacount_o = wr_datacount_int;
        assign rd_datacount_o = rd_datacount_int;
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
        end
    end    

    if (!SYNC_CLK) begin
        //(* async_reg = "true" *) reg [1:0] wr_rst;
        //(* async_reg = "true" *) reg [1:0] rd_rst;
        //
        //always @ (posedge wr_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        wr_rst <= 2'b11;
        //    else 
        //        wr_rst <= {wr_rst[0],1'b0};            
        //end
        //
        //always @ (posedge rd_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        rd_rst <= 2'b11;
        //    else 
        //        rd_rst <= {rd_rst[0],1'b0};            
        //end
        

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_wr_rst_i;
            assign rd_rst_int = a_rd_rst_i; 
            assign rst_busy   = 1'b0;
        end 
        else begin
            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_wr_rst (
               .clk   (wr_clk_int),
               .reset (a_rst_i),
               .d_o   (wr_rst_int)
            );

            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_rd_rst (
               .clk   (rd_clk_int),
               .reset (a_rst_i),
               .d_o   (rd_rst_int)
            );
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end

    end
    else begin
        //(* async_reg = "true" *) reg [1:0] a_rst;
        //
        //always @ (posedge clk_i or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        a_rst <= 2'b11;
        //    else 
        //        a_rst <= {a_rst[0],1'b0};            
        //end
        wire   a_rst;

        `IP_MODULE_NAME(efx_resetsync) #(
           .ACTIVE_LOW (0)
        ) efx_resetsync_a_rst (
           .clk   (clk_i),
           .reset (a_rst_i),
           .d_o   (a_rst)
        );

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_rst_i;
            assign rd_rst_int = a_rst_i;
            assign rst_busy   = 1'b0;
        end
        else begin
            assign wr_rst_int = a_rst;
            assign rd_rst_int = a_rst;   
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end
    end 
endgenerate

`IP_MODULE_NAME(efx_fifo_ram) # (
    .FAMILY        (FAMILY),
    .WR_DEPTH      (WR_DEPTH),
    .RD_DEPTH      (RD_DEPTH),
    .WDATA_WIDTH   (WDATA_WIDTH),
    .RDATA_WIDTH   (RDATA_WIDTH),
    .WADDR_WIDTH   (WADDR_WIDTH),
    .RADDR_WIDTH   (RADDR_WIDTH),
    .OUTPUT_REG    (OUTPUT_REG),
    .RAM_MUX_RATIO (RAM_MUX_RATIO),
    .ENDIANESS	    (ENDIANESS),
    .RAM_STYLE     (RAM_STYLE)
) xefx_fifo_ram (
    .wdata (wdata), 
    .waddr (waddr),
    .raddr (raddr), 
    .we    (wr_en_int), 
    .re    (rd_en_int),
    .wclk  (wr_clk_int),
    .rclk  (rd_clk_int),
    .rdata (rdata)
);

`IP_MODULE_NAME(efx_fifo_ctl) # (
    .SYNC_CLK           (SYNC_CLK),
    .SYNC_STAGE         (SYNC_STAGE),
    .MODE               (MODE),
    .WR_DEPTH           (WR_DEPTH),
    .WADDR_WIDTH        (WADDR_WIDTH),
    .RADDR_WIDTH        (RADDR_WIDTH),
    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
    .PIPELINE_REG       (PIPELINE_REG),
    .ALMOST_FLAG        (ALMOST_FLAG),
    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
    .OUTPUT_REG         (OUTPUT_REG),
    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG),
    .OVERFLOW_PROTECT   (OVERFLOW_PROTECT),
    .UNDERFLOW_PROTECT  (UNDERFLOW_PROTECT)
) xefx_fifo_ctl (
    .wr_rst          (wr_rst_int),
    .rd_rst          (rd_rst_int),
    .wclk            (wr_clk_int),
    .rclk            (rd_clk_int),
    .we              (wr_en_i),
    .re              (rd_en_i),
    .wr_full         (full_o),
    .wr_ack          (wr_ack_o),
    .rd_empty        (empty_o),
    .wr_almost_full  (almost_full_o),
    .rd_almost_empty (almost_empty_o),
    .wr_prog_full    (prog_full_o),
    .rd_prog_empty   (prog_empty_o),
    .wr_en_int       (wr_en_int),
    .rd_en_int       (rd_en_int),
    .waddr           (waddr),
    .raddr           (raddr),
    .wr_datacount    (wr_datacount_int),
    .rd_datacount    (rd_datacount_int),
    .rd_vld          (rd_valid_o),
    .wr_overflow     (overflow_o),
    .rd_underflow    (underflow_o)
);

function integer depth2width;
input [31:0] depth;
begin : fnDepth2Width
    if (depth > 1) begin
        depth = depth - 1;
        for (depth2width=0; depth>0; depth2width = depth2width + 1)
            depth = depth>>1;
        end
    else
       depth2width = 0;
end
endfunction 

function integer width2depth;
input [31:0] width;
begin : fnWidth2Depth
    width2depth = width**2;
end
endfunction

function integer rdwidthcompute;
input [31:0] asym_option;
input [31:0] wr_width;
begin : RdWidthCompute
    rdwidthcompute = (asym_option==0)? wr_width/16 :
                     (asym_option==1)? wr_width/8  :
                     (asym_option==2)? wr_width/4  :
                     (asym_option==3)? wr_width/2  :
                     (asym_option==4)? wr_width/1  :
                     (asym_option==5)? wr_width*2  :
                     (asym_option==6)? wr_width*4  :
                     (asym_option==7)? wr_width*8  :
                     (asym_option==8)? wr_width*16 : wr_width/1;
end
endfunction

function integer rddepthcompute;
input [31:0] wr_depth;
input [31:0] wr_width;
input [31:0] rd_width;
begin : RdDepthCompute
    rddepthcompute = (wr_depth * wr_width) / rd_width;
end
endfunction

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ram) #(
    parameter FAMILY        = "TRION",
    parameter WR_DEPTH      = 512,
    parameter RD_DEPTH      = 512,
    parameter WDATA_WIDTH   = 8,
    parameter RDATA_WIDTH   = 8,
    parameter WADDR_WIDTH   = 9,
    parameter RADDR_WIDTH   = 9,
    parameter OUTPUT_REG    = 1,
    parameter RAM_MUX_RATIO = 4,
    parameter ENDIANESS 	 = 0, //0: Big endian (default)   1: Little endian 
    parameter RAM_STYLE     = "block_ram"
) (
    input  wire                     wclk,
    input  wire                     rclk,
    input  wire                     we,
    input  wire                     re,
    input  wire [(WDATA_WIDTH-1):0] wdata,
    input  wire [(WADDR_WIDTH-1):0] waddr,
    input  wire [(RADDR_WIDTH-1):0] raddr,
    output wire [(RDATA_WIDTH-1):0] rdata
);

localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";

(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
reg [RDATA_WIDTH-1:0]    r_rdata_1P;
reg [RDATA_WIDTH-1:0]    r_rdata_2P;

wire                     re_int;

generate
    if (FAMILY == "TRION") begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                end
                r_rdata_2P <= r_rdata_1P;
            end
        end
        
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            if (ENDIANESS == 0) begin 
            	integer i;
            	always @ (posedge wclk) begin
                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                    end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                	end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
        end
        
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
            //integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end 
            end
            else begin //endianess == 1
            	always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end
            end
        end
        if (OUTPUT_REG) begin
            assign re_int = re;
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end
    end
    else begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                    r_rdata_2P <= r_rdata_1P;
                end
            end
        end 
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            //integer i;
            if (ENDIANESS == 0) begin
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
            
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
        end
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
        	//integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
            
            else begin //endianess ==1
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
        end
        // NIC
        //if (MODE == "STANDARD") begin     
        //    if (OUTPUT_REG) begin
        //        reg re_r;
        //        always @ (posedge rclk) begin
        //            re_r <= re;
        //        end
        //        assign re_int = re | re_r;        
        //        assign rdata  = r_rdata_2P;            
        //    end
        //    else begin
        //        assign re_int = re;
        //        assign rdata  = r_rdata_1P;
        //    end
        //end
        //else begin
        //    assign re_int = re;
        //    assign rdata  = r_rdata_1P;
        //end    
        if (OUTPUT_REG) begin
            reg re_r;
            always @ (posedge rclk) begin
                re_r <= re;
            end
            assign re_int = re | re_r;        
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end    
    end
endgenerate

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   gray2bin.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Gray to Binary Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_gray2bin)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] bin_o,
 // input
 input [WIDTH-1:0] gray_i);

//---------------------------------------------------------------------
// Recursive Module
// Description: reduction xor
generate
   if (WIDTH > 1) begin
      wire [1:0] bin_1;
      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
      if (WIDTH == 2) begin
	 assign bin_o = bin_1;
      end
      else begin
	 assign bin_o[WIDTH-1] = bin_1[1];
	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
      end
   end
   else /* if (WIDTH == 1) */
     assign bin_o = gray_i;
endgenerate
   
endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   pipe_reg.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Parallel Pipelining Shift Register
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_datasync) #(
    parameter STAGE = 32,
    parameter WIDTH = 4
) (
 input  wire             clk_i,
 input  wire [WIDTH-1:0] d_i,
 output wire [WIDTH-1:0] d_o
);

(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
integer i;

always @(posedge clk_i) begin
  for (i=STAGE-1; i>0; i = i - 1) begin
    pipe_reg[i] <= pipe_reg[i-1];
  end
  pipe_reg[0] <= d_i;
end
assign d_o = pipe_reg[STAGE-1];
   

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_resetsync) #(
    parameter ASYNC_STAGE = 2,
    parameter ACTIVE_LOW = 1
) (
    input  wire             clk,
    input  wire             reset,
    output wire             d_o
);


generate
   if (ACTIVE_LOW == 1) begin: active_low
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (1),
         .RST_VALUE  (0)
      ) efx_resetsync_active_low (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b1),
         .d_o     (d_o)
      );
   end
   else begin: active_high
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (0),
         .RST_VALUE  (1)
      ) efx_resetsync_active_high (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b0),
         .d_o     (d_o)
      );
   end
endgenerate

endmodule



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_asyncreg) #(
    parameter ASYNC_STAGE = 2,
    parameter WIDTH = 4,
    parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
    parameter RST_VALUE = 0,
    parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance 
) (
    input  wire             clk,
    input  wire             reset_n,
    input  wire [WIDTH-1:0] d_i,
    output wire [WIDTH-1:0] d_o
);










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`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
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`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
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`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
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`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
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`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 )
`pragma protect data_block
[encoded data, 5785 characters]
Ei7EaFpheCmlTJyxUg8TdA==
`pragma protect end_protected


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ctl) # (
    parameter SYNC_CLK           = 1,
    parameter SYNC_STAGE         = 2,
    parameter MODE               = "STANDARD",
    parameter WR_DEPTH           = 512,
    parameter WADDR_WIDTH        = 9,
    parameter RADDR_WIDTH        = 9,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter RAM_MUX_RATIO      = 1,
    parameter PIPELINE_REG       = 1,
    parameter ALMOST_FLAG        = 1,
    parameter PROGRAMMABLE_FULL  = "NONE",
    parameter PROG_FULL_ASSERT   = 0,
    parameter PROG_FULL_NEGATE   = 0,
    parameter PROGRAMMABLE_EMPTY = "NONE",
    parameter PROG_EMPTY_ASSERT  = 0,
    parameter PROG_EMPTY_NEGATE  = 0,
    parameter OUTPUT_REG         = 0,
    parameter HANDSHAKE_FLAG     = 1, 
    parameter OVERFLOW_PROTECT   = 0,
    parameter UNDERFLOW_PROTECT  = 0
)(
    input   wire                   wr_rst,
    input   wire                   rd_rst,
    input   wire                   wclk,
    input   wire                   rclk,
    input   wire                   we,
    input   wire                   re,
    output  wire                   wr_full,
    output  reg                    wr_ack,
    output  wire                   wr_almost_full,
    output  wire                   rd_empty,
    output  wire                   rd_almost_empty,
    output  wire                   wr_prog_full,
    output  wire                   rd_prog_empty,
    output  wire                   wr_en_int,
    output  wire                   rd_en_int,
    output  wire [WADDR_WIDTH-1:0] waddr,
    output  wire [RADDR_WIDTH-1:0] raddr,
    output  wire [WADDR_WIDTH:0]   wr_datacount,
    output  wire [RADDR_WIDTH:0]   rd_datacount,
    output  wire                   rd_vld,
    output  reg                    wr_overflow,
    output  reg                    rd_underflow
);

reg  [WADDR_WIDTH:0] waddr_cntr;
reg  [WADDR_WIDTH:0] waddr_cntr_r;
reg  [RADDR_WIDTH:0] raddr_cntr;
reg                  rd_valid;

wire [WADDR_WIDTH:0] waddr_int;
wire [RADDR_WIDTH:0] raddr_int;
wire                 rd_empty_int;
wire [WADDR_WIDTH:0] wr_datacount_int;
wire [RADDR_WIDTH:0] rd_datacount_int;

assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
// NIC
wire [RADDR_WIDTH:0] ram_raddr;
assign raddr     = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0];
//assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
//assign wr_en_int = we & ~wr_full;
assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we;

assign wr_datacount  = wr_datacount_int;
assign rd_datacount  = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int;


generate
    if (MODE == "FWFT") begin    
        // NIC
        //assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
        //assign rd_empty      = rd_empty_fwft;

        assign rd_en_int     = 1'b1;
        //assign rd_empty      = rd_empty_int;
        
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        init_set <= 1'b1;
        //    end
        //    else if (~init_set & rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //    else if (~rd_empty_int) begin
        //        init_set <= 1'b0;            
        //    end
        //    else if (rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //end
        // NIC 
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        rd_empty_fwft <= 1'b1;
        //    end
        //    else if (rd_en_int) begin
        //        rd_empty_fwft <= 1'b0;            
        //    end
        //    else if (re) begin
        //        rd_empty_fwft <= 1'b1;            
        //    end
        //end          
        
        //if (FAMILY == "TRION") begin
        if (OUTPUT_REG) begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid <= 1'b0;
                end
                else begin
                    rd_valid <= ~rd_empty;
                end
            end
            assign rd_vld = rd_valid;                
        end    
        else begin
            assign rd_vld = ~rd_empty;                
        end
        
        assign rd_empty = rd_empty_int;
    end
    else begin
        assign rd_en_int     = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re;
        assign rd_empty      = rd_empty_int;
        
        if (OUTPUT_REG) begin
            reg rd_valid_r;
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid_r <= 'h0;
                    rd_valid   <= 'h0;
                end
                else begin
                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
                end
            end
            assign rd_vld = rd_valid;            
        end
        else begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid  <= 'h0;
                end
                else begin
                    rd_valid <= rd_en_int;
                end
            end
            assign rd_vld = rd_valid;
        end
    end
    
    if (ALMOST_FLAG) begin
        assign wr_almost_full   = wr_datacount >= WR_DEPTH-1;
        assign rd_almost_empty  = rd_datacount <= 'd1;
    end
    else begin
        assign wr_almost_full   = 1'b0;
        assign rd_almost_empty  = 1'b0;        
    end
    
    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end  
    end
    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   

        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end              
    end
    else begin
        assign wr_prog_full  = 1'b0; 
    end
        
    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end
    end
    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end  
    end
    else begin
        assign rd_prog_empty  = 1'b0; 
    end
    
    if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_ack <= 1'b0;
            end
            else begin
                // NIC
                //wr_ack <= wr_en_int & ~wr_overflow;
                wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int;
            end
        end
    end

    if (OVERFLOW_PROTECT) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else if (we && wr_full) begin
                wr_overflow <= 1'b1;
            end
            else begin
                wr_overflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else begin
                wr_overflow <= we && wr_full ? 1'b1 : wr_overflow;
            end
        end
    end

    if (UNDERFLOW_PROTECT) begin     
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else if (re && rd_empty) begin
                rd_underflow <= 1'b1;
            end
            else begin
                rd_underflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else begin
                rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow;
            end
        end
    end
    
    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
    
    if (ASYM_WIDTH_RATIO < 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
    end
    // NIC
    else if (ASYM_WIDTH_RATIO == 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - raddr_int;
        assign rd_datacount_int = waddr_int - raddr_cntr;
    end
    else begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
        // NIC
        //assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr;
    end
endgenerate

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr   <= 'h0;
    end
    else if (wr_en_int) begin
        waddr_cntr   <= waddr_cntr + 1'b1;
    end
end

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr_r  <= 'h0;
    end
    else begin
        waddr_cntr_r  <= waddr_cntr;
    end
end

always @ (posedge rclk or posedge rd_rst) begin
    if (rd_rst) begin
        raddr_cntr   <= 'h0;
    end
    // NIC
    //else if (rd_en_int) begin
    else begin
        //raddr_cntr   <= raddr_cntr + 1'b1;
        //raddr_cntr   <= raddr_cntr + (re & ~rd_empty_int);
        raddr_cntr   <= ram_raddr;
    end
end
// NIC
assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re);


generate
    if (SYNC_CLK) begin : sync_clk
       if (MODE == "FWFT") begin
          assign waddr_int = waddr_cntr_r;
          assign raddr_int        = raddr_cntr;
       end
       else begin
          assign waddr_int        = waddr_cntr;
          assign raddr_int        = raddr_cntr;
       end
    end
    else begin : async_clk
        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
        
        wire [RADDR_WIDTH:0] raddr_cntr_gry;
        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
        wire [WADDR_WIDTH:0] waddr_cntr_gry;
        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;

        if (PIPELINE_REG) begin
            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
        
            assign waddr_int        = waddr_cntr_sync_g2b_r;
            assign raddr_int        = raddr_cntr_sync_g2b_r;
            
            always @ (posedge wclk or posedge wr_rst) begin
                if (wr_rst) begin
                    raddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
                end
            end
            
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    waddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
                end
            end
        end
        else begin
            assign waddr_int        = waddr_cntr_sync_g2b;
            assign raddr_int        = raddr_cntr_sync_g2b;        
        end
      
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                raddr_cntr_gry_r <= 'h0;
            end
            else begin
                raddr_cntr_gry_r <= raddr_cntr_gry;
            end
        end
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_bin2gray    (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync   (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                                                               ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                waddr_cntr_gry_r <= 'h0;
            end
            else begin
                waddr_cntr_gry_r <= waddr_cntr_gry;
            end
        end        
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                                                               ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        

    end
endgenerate
endmodule


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   bin2gray.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Binary to Gray Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_bin2gray)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] gray_o,
 // input
 input [WIDTH-1:0] bin_i
 );

//---------------------------------------------------------------------
// Function :   bit_xor
// Description: reduction xor
function bit_xor (
  input [31:0] nex_bit,
  input [31:0] curr_bit,
  input [WIDTH-1:0] xor_in);
  begin : fn_bit_xor
    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
  end
endfunction

// Convert Binary to Gray, bit by bit
generate 
begin
  genvar bit_idx;
  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
  end
  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
end
endgenerate

endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
lJQSO0RK2H2ogiwqEX0EF9W73Mi46nhSMrjpYujGSQby+xfLpTE+gG4Bcq9pG6uf
pBg/m/x04spvzjzXtCyY99jNAmzIBKMkCWgf5qi4mFTJb+MCgX5SBGeUjYCLDPH8
wIonHgim1OFOk+7Fqusq1hUQ4O0nEcSkdFoFjguIA/g=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 22080 )
`pragma protect data_block
[encoded data, 29900 characters]
`pragma protect end_protected

//pragma protect end


module `IP_MODULE_NAME(mii_if) #(
   parameter NO_PREAMBLE = 0
) (
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//MII Interface
input                           mii_txc,
output  reg     [3:0]           mii_txd,
output  reg                     mii_tx_dv,
output  reg                     mii_tx_err,

input                           mii_rxc,
input           [3:0]           mii_rxd,
input                           mii_rx_dv,
input                           mii_rx_err

//Status and  Error Signals
);
// Parameter Define 
//localparam                      SPEED_100M_DIV = (TX_REFCLK == 125) ? 10 : 2;
//localparam                      SPEED_10M_DIV  = SPEED_100M_DIV*10;
//localparam                      SPEED_CLK_DIV = (TX_REFCLK == 125) ? SPEED_100M_DIV/2 + 1 : 0 ;
// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [3:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_dv_pre;
reg                             rx_dv_dl1;
reg     [3:0]                   rxd_pre;
reg     [3:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;
reg     [3:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [3:0]                   gm_tx_d_h;
reg     [7:0]                   gm_tx_d_r;
reg                             gm_tx_en_r;
reg                             gm_tx_err_r;
reg                             preamble_flg;
reg     [1:0]                   cur_st;
reg     [1:0]                   nxt_st;
reg                             add_preamble;


// Wire Define
wire                            add_preamble_w;

assign add_preamble_w = mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err && cur_st == 2'b01 && preamble_flg;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else
      tx_mac_aclk_en <= ~tx_mac_aclk_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_r <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_r <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_en_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_en_r <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_err_r <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      gm_tx_err_r <= gm_tx_err;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd <= 4'h0;
   else if (gm_tx_en_r == 1'b1) begin
      if (tx_mac_aclk_en == 1'b0)
          txd <= gm_tx_d_r[3:0];
      else
          txd <= gm_tx_d_r[7:4];
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_en <= 1'b0;
   else 
       tx_en <= gm_tx_en_r;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else 
       tx_er <= gm_tx_err_r;
end

always @ (posedge mii_txc or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      mii_tx_dv  <= 1'b0;
      mii_txd    <= 4'h0;
      mii_tx_err <= 1'b0;
   end
   else begin
      mii_tx_dv  <= tx_en;
      mii_txd    <= txd[3:0];
      mii_tx_err <= tx_er;
   end
end
/*----------------------- Rx Region ----------------------------*/
always @ (posedge mii_rxc or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 4'h0;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else if (add_preamble_w && NO_PREAMBLE != 1) begin
      rxd   <= 4'h5;
      rx_dv <= 1'b1;
      rx_er <= rx_er;
   end
   else if (add_preamble && NO_PREAMBLE != 1) begin
      rxd   <= rxd_pre;
      rx_dv <= rx_dv_pre;
      rx_er <= rx_er;
   end
   else begin
      rxd   <= mii_rxd;
      rx_dv <= mii_rx_dv;
      rx_er <= mii_rx_err;
   end
end

assign rx_mac_aclk = mii_rxc;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd_pre <= 4'h0;
      rx_dv_pre <= 1'b0;
   end
   else if (add_preamble_w || add_preamble) begin
      rxd_pre <= mii_rxd;
      rx_dv_pre <= mii_rx_dv;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
    if (rx_reset == 1'b1)
       add_preamble <= 1'b0;
    else if (add_preamble_w)
       add_preamble <= 1'b1;
    else if (!mii_rx_dv)
       add_preamble <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else
      rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      cur_st <= 2'b00;
   end
   else begin
      cur_st <= nxt_st;
   end
end

always @ (*) begin
   case (cur_st)
      2'b00: begin
         if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else
            nxt_st = 2'b00;
      end
      2'b01: begin
         if (mii_rxd == 4'hd && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b10;
         else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err)
            nxt_st = 2'b01;
         else 
            nxt_st = 2'b00;
      end
      2'b10: begin
         if (mii_rx_dv) 
            nxt_st = 2'b10;
         else
            nxt_st = 2'b00;
         end
      default: nxt_st = 2'b00;
   endcase
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      preamble_flg <= 1'b0;
   end
   else if (mii_rxd == 4'h5 && mii_rx_dv && !mii_rx_err && cur_st == 2'b01) begin
      preamble_flg <= ~preamble_flg;
   end
   else begin
      preamble_flg <= 1'b0;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rx_dv_dl1 <= 1'b0;
      rxd_dl1   <= 4'h0;
   end
   else begin
      rx_dv_dl1 <= rx_dv;
      rxd_dl1   <= rxd;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else
      gm_rx_dv <= rx_dv_dl1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 1'b0;
   else if (rx_dv == 1'b0)
      rx_odd_data_ptr <= 1'b0;
   else
      rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if ((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
      gm_rx_d <= {rxd[3:0], rxd_dl1[3:0]};
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       gm_rx_err <= 1'b0;
   else begin
      if (rx_er == 1'b1)               gm_rx_err <= 1'b1;
      else if (rx_mac_aclk_en == 1'b1) gm_rx_err <= 1'b0;
   end
end


endmodule



/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii_if)#(
    parameter                       RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                           tx_mac_aclk,
   output  reg                     tx_mac_aclk_en,
   input                           tx_reset,
   output  wire                    rx_mac_aclk,
   output  reg                     rx_mac_aclk_en,
   input                           rx_reset,
   //Configuration Signals
   input           [2:0]           eth_speed,
   input                           rgmii_rxc_edge,//0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   input                           rgmii_txc_dly,//0:rgmii tx clock delay disable; 1:rgmii tx clock delay enable;
   //GMII Interface
   output  reg     [7:0]           gm_rx_d,
   output  reg                     gm_rx_dv,
   output  reg                     gm_rx_err,
   input           [7:0]           gm_tx_d,
   input                           gm_tx_en,
   input                           gm_tx_err,
   //RGMII Interface
   output  wire    [3:0]           rgmii_txd_HI,
   output  wire    [3:0]           rgmii_txd_LO,
   output  wire                    rgmii_tx_ctl_HI,
   output  wire                    rgmii_tx_ctl_LO,
   output  wire                    rgmii_txc_HI,//if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  wire                    rgmii_txc_LO,
   input           [3:0]           rgmii_rxd_HI,
   input           [3:0]           rgmii_rxd_LO,
   input                           rgmii_rx_ctl_HI,
   input                           rgmii_rx_ctl_LO,
   input                           rgmii_rxc
   //Status and  Error Signals
);

// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [7:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg     [1:0]                   txc;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;

// Wire Define
wire                            rx_dv;
wire    [7:0]                   rxd;
wire                            rx_er;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if ((eth_speed == 3'h4) ||
           ((eth_speed == 3'h2) && (aclk_en_cnt == 7'd9)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd99)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[7:4] <= 4'h0;
   else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[7:4] <= gm_tx_d[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txd[3:0] <= 4'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      txd[3:0] <= gm_tx_d[3:0];
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd6)) ||
            ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd51)))
      txd[3:0] <= txd[7:4];
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_en <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
      tx_er <= gm_tx_err;
end
/*
always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
        3'h4 :
            txc <= 2'b01;
        3'h2 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b00;
            endcase
        3'h1 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
                    txc <= 2'b00;
            1'b1 ://rgmii tx clock delay enable.
                if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
                    txc <= 2'b00;
            endcase
        default :
            txc <= 2'b0;
        endcase
end

*/
reg [1:0]    txc_100m_r;
reg [1:0]    txc_10m_r;

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_100m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
          1'b0 : //rgmii tx clock delay disable.
             if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                txc_100m_r <= 2'b00;
          1'b1 ://rgmii tx clock delay enable.
             if ((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                txc_100m_r <= 2'b11;
             else if ((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b00;
       endcase
   end
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txc_10m_r <= 2'b0;
   else begin
       case(rgmii_txc_dly)
       1'b0 ://rgmii tx clock delay disable.
           if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
               txc_10m_r <= 2'b00;
       1'b1 ://rgmii tx clock delay enable.
           if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
               txc_10m_r <= 2'b11;
           else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
               txc_10m_r <= 2'b00;
       endcase
   end
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
            3'h4 :
                txc <= 2'b01;
            3'h2 :
                txc <= txc_100m_r;
            3'h1 :
                txc <= txc_10m_r;
            default :
                txc <= 2'b0;
        endcase
end

/*----------------------- Rx Region ----------------------------*/
assign rx_mac_aclk = rgmii_rxc;

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_mac_aclk_en <= 1'b0;
    else if(eth_speed[2] == 1'b1)
        rx_mac_aclk_en <= 1'b1;
    else
        rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        begin
            rx_dv_dl1 <= 1'b0;
            rxd_dl1 <= 8'h0;
        end
    else
        begin
            rx_dv_dl1 <= rx_dv;
            rxd_dl1 <= rxd;
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_dv <= 1'b0;
    else
        gm_rx_dv <= rx_dv_dl1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_odd_data_ptr <= 1'b0;
    else if(rx_dv == 1'b0)
        rx_odd_data_ptr <= 1'b0;
    else
        rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_d <= 8'h0;
    else
        begin
            if((eth_speed[2] == 1'b1) && (rx_dv_dl1 == 1'b1))
                gm_rx_d <= rxd_dl1;
            else if((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
                gm_rx_d <= {rxd[3:0],rxd_dl1[3:0]};
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_err <= 1'b0;
    else
        begin
            if(rx_er == 1'b1)
                gm_rx_err <= 1'b1;
            else if(rx_mac_aclk_en == 1'b1)
                gm_rx_err <= 1'b0;
        end
end

/*----------------------- PHY Interface ----------------------------*/
`IP_MODULE_NAME(rgmii) #(
    .RGMII_SYNC_EN                      (RGMII_SYNC_EN                      )
)
u_rgmii
(
//Globle Signals
    .tx_mac_aclk                        (tx_mac_aclk                        ),
    .tx_reset                           (tx_reset                           ),
    .rx_reset                           (rx_reset                           ),
//Configuration Signals
    .eth_speed                          (eth_speed                          ),
    .rgmii_rxc_edge                     (rgmii_rxc_edge                     ),
//Phy Interface
    .txd                                (txd                                ),
    .tx_en                              (tx_en                              ),
    .tx_er                              (tx_er                              ),
    .txc                                (txc                                ),
    .rxd                                (rxd                                ),
    .rx_dv                              (rx_dv                              ),
    .rx_er                              (rx_er                              ),
//RGMII Interface
    .rgmii_txd_HI                       (rgmii_txd_HI                       ),
    .rgmii_txd_LO                       (rgmii_txd_LO                       ),
    .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI                    ),
    .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO                    ),
    .rgmii_txc_HI                       (rgmii_txc_HI                       ),
    .rgmii_txc_LO                       (rgmii_txc_LO                       ),
    .rgmii_rxd_HI                       (rgmii_rxd_HI                       ),
    .rgmii_rxd_LO                       (rgmii_rxd_LO                       ),
    .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI                    ),
    .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO                    ),
    .rgmii_rxc                          (rgmii_rxc                          )
);

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
module `IP_MODULE_NAME(rgmii_sync)
(
//Globle Signals
input                           rgmii_rxc,
input                           rx_reset,
input           [2:0]           eth_speed,
//RGMII Rx Interface Input
input           [3:0]           rgmii_rxd_HI_i,
input           [3:0]           rgmii_rxd_LO_i,
input                           rgmii_rx_ctl_HI_i,
input                           rgmii_rx_ctl_LO_i,
//RGMII Rx Interface Output
output  reg     [3:0]           rgmii_rxd_HI_o,
output  reg     [3:0]           rgmii_rxd_LO_o,
output  reg                     rgmii_rx_ctl_HI_o,
output  reg                     rgmii_rx_ctl_LO_o
);


// Parameter Define 
parameter State_idle     = 2'd0;
parameter State_preamble = 2'd1;
parameter State_data_dl1 = 2'd2;
parameter State_data_dl2 = 2'd3;


// Register Define 
reg     [1:0]                   cur_state;
reg     [1:0]                   next_state;
reg                             preamble_odd;
reg     [3:0]                   rx_d_dl1;
reg                             rx_dv_dl1;
reg     [3:0]                   rx_d_dl2;
reg                             rx_dv_dl2;

// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rx_d_dl1      <= 4'h0;
      rx_dv_dl1     <= 1'b0;
      rx_d_dl2      <= 4'h0;
      rx_dv_dl2     <= 1'b0;
   end
   else begin
      rx_d_dl1      <= rgmii_rxd_LO_i;
      rx_dv_dl1     <= rgmii_rx_ctl_HI_i;
      rx_d_dl2      <= rx_d_dl1;
      rx_dv_dl2     <= rx_dv_dl1;
   end
end

/*----------------------- FSM Region ----------------------------*/
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) cur_state <= State_idle;
	else          cur_state <= next_state;
end

always @ (*) begin
	case (cur_state)
      State_idle :
         if ((rx_dv_dl1 == 1'b1) && (rx_d_dl1 == 4'h5))
             next_state = State_preamble;
         else
             next_state = State_idle;

      State_preamble : 
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b0))
            next_state = State_data_dl1;
         else if ((rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
            next_state = State_data_dl2;
         else if (rx_d_dl1 != 4'h5)
            next_state = State_idle;
         else
            next_state = State_preamble;
          
      State_data_dl1 :
         if (rx_dv_dl1 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl1;

      State_data_dl2 :
         if (rx_dv_dl2 == 1'b0)
            next_state = State_idle;
         else
            next_state = State_data_dl2;

      default :
         next_state = State_idle;
    endcase
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
    if (rx_reset) 
       preamble_odd <= 1'b0;
    else if (cur_state == State_preamble)
       preamble_odd <= ~preamble_odd;
    else
       preamble_odd <= 1'b0;
end

/*----------------------- Sync Output Region ----------------------------*/

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rxd_LO_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_LO_o <= rgmii_rxd_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rxd_LO_o <= 4'h5;
   else if (cur_state == State_data_dl2)
      rgmii_rxd_LO_o <= rx_d_dl2;
   else
      rgmii_rxd_LO_o <= rx_d_dl1;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) 
      rgmii_rxd_HI_o <= 4'h0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rxd_HI_o <= rgmii_rxd_HI_i;
   else
      rgmii_rxd_HI_o <= 4'h0;
end

always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_HI_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_HI_o <= rgmii_rx_ctl_HI_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_HI_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_HI_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_HI_o <= rx_dv_dl1;
end

always @(posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset)
      rgmii_rx_ctl_LO_o <= 1'b0;
   else if (eth_speed[2] == 1'b1)
      rgmii_rx_ctl_LO_o <= rgmii_rx_ctl_LO_i;
   else if ((cur_state == State_preamble) && (rx_d_dl1 == 4'hd) && (preamble_odd == 1'b1))
      rgmii_rx_ctl_LO_o <= 1'b1;
   else if (cur_state == State_data_dl2)
      rgmii_rx_ctl_LO_o <= rx_dv_dl2;
   else
      rgmii_rx_ctl_LO_o <= rx_dv_dl1;
end

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(rgmii) #(
    parameter                   RGMII_SYNC_EN = 1
) (
   //Globle Signals
   input                        tx_mac_aclk,
   input                        tx_reset,
   input                        rx_reset,
   //Configuration Signals
   input           [2:0]        eth_speed,
   input                        rgmii_rxc_edge, //0:DDIO Rising Edge; 1:DDIO Falling Edge; 
   //Phy Interface
   input           [7:0]        txd,
   input                        tx_en,
   input                        tx_er,
   input           [1:0]        txc, //if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
   output  reg     [7:0]        rxd,
   output  reg                  rx_dv,
   output  reg                  rx_er,
   //RGMII Interface
   output  reg     [3:0]        rgmii_txd_HI,
   output  reg     [3:0]        rgmii_txd_LO,
   output  reg                  rgmii_tx_ctl_HI,
   output  reg                  rgmii_tx_ctl_LO,
   output  reg                  rgmii_txc_HI,
   output  reg                  rgmii_txc_LO,
   input           [3:0]        rgmii_rxd_HI,
   input           [3:0]        rgmii_rxd_LO,
   input                        rgmii_rx_ctl_HI,
   input                        rgmii_rx_ctl_LO,
   input                        rgmii_rxc
   //Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [3:0]                   rgmii_rxd_HI_d1;
reg                             rgmii_rx_ctl_HI_d1;
reg     [3:0]                   rgmii_txd_HI_r;
reg     [3:0]                   rgmii_txd_LO_r;
reg                             rgmii_tx_ctl_HI_r;
reg                             rgmii_tx_ctl_LO_r;
reg                             rgmii_txc_HI_r;
reg                             rgmii_txc_LO_r;
// Wire Define
wire                            tx_en_to_ddr;
wire                            rgmii_tx_ctl_int;
wire    [3:0]                   txd_falling;
/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- RGMII Tx Region ----------------------------*/
assign tx_en_to_ddr = (eth_speed[2] == 1'b1) ? tx_en : tx_en && (!tx_er);
assign rgmii_tx_ctl_int = tx_en ^ tx_er;

assign txd_falling = (eth_speed[2] == 1'b1) ? txd[7:4] : txd[3:0];

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI_r    <= 1'b0;
      rgmii_txc_LO_r    <= 1'b0;
      rgmii_tx_ctl_HI_r <= 1'b0;
      rgmii_tx_ctl_LO_r <= 1'b0;
      rgmii_txd_HI_r    <= 4'b0;
      rgmii_txd_LO_r    <= 4'b0;
   end 
   else begin
      rgmii_txc_HI_r    <= txc[0];
      rgmii_txc_LO_r    <= txc[1];     
      rgmii_tx_ctl_HI_r <= tx_en_to_ddr;
      rgmii_tx_ctl_LO_r <= rgmii_tx_ctl_int;
      rgmii_txd_HI_r    <= txd[3:0];
      rgmii_txd_LO_r    <= txd_falling;
   end
end


always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset) begin
      rgmii_txc_HI    <= 1'b0;
      rgmii_txc_LO    <= 1'b0;
      rgmii_tx_ctl_HI <= 1'b0;
      rgmii_tx_ctl_LO <= 1'b0;
      rgmii_txd_HI    <= 4'b0;
      rgmii_txd_LO    <= 4'b0;
   end
   else begin
      rgmii_txc_HI    <= rgmii_txc_HI_r;
      rgmii_txc_LO    <= rgmii_txc_LO_r;
      rgmii_tx_ctl_HI <= rgmii_tx_ctl_HI_r;
      rgmii_tx_ctl_LO <= rgmii_tx_ctl_LO_r;
      rgmii_txd_HI    <= rgmii_txd_HI_r;
      rgmii_txd_LO    <= rgmii_txd_LO_r;
   end
end

/*----------------------- RGMII Rx Region ----------------------------*/
//rgmii_rxd & rgmii_rx_ctl
always @ (posedge rgmii_rxc or posedge rx_reset) begin
   if (rx_reset) begin
      rgmii_rxd_HI_d1    <= 4'h0;
      rgmii_rx_ctl_HI_d1 <= 1'b0;
   end 
   else begin
      rgmii_rxd_HI_d1    <= rgmii_rxd_HI;
      rgmii_rx_ctl_HI_d1 <= rgmii_rx_ctl_HI;
   end
end

generate
   if (RGMII_SYNC_EN == 0) begin
      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rxd[7:4] <= rgmii_rxd_LO;
               rxd[3:0] <= rgmii_rxd_HI_d1;
               rx_dv    <= rgmii_rx_ctl_HI_d1;
               rx_er    <= rgmii_rx_ctl_HI_d1^rgmii_rx_ctl_LO;
            end
            else begin//1:DDIO Falling Edge
               rxd[7:4] <= rgmii_rxd_HI;
               rxd[3:0] <= rgmii_rxd_LO;
               rx_dv    <= rgmii_rx_ctl_LO;
               rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI;
            end
        end
        else begin //100M or 10M
           rxd[7:4] <= 4'b0;
           rxd[3:0] <= rgmii_rxd_LO;
           rx_dv    <= rgmii_rx_ctl_LO;
           rx_er    <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI_d1;
        end
     end
   end
   else begin
      reg  [3:0]  rgmii_rxd_HI_i;
      reg  [3:0]  rgmii_rxd_LO_i;
      reg         rgmii_rx_ctl_HI_i;
      reg         rgmii_rx_ctl_LO_i;
      wire [3:0]  rgmii_rxd_HI_sync;
      wire [3:0]  rgmii_rxd_LO_sync;
      wire        rgmii_rx_ctl_HI_sync;
      wire        rgmii_rx_ctl_LO_sync;

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rgmii_rxd_HI_i    <= 4'h0;
            rgmii_rxd_LO_i    <= 4'h0;
            rgmii_rx_ctl_HI_i <= 1'b0;
            rgmii_rx_ctl_LO_i <= 1'b0;
         end
         else if (eth_speed[2] == 1'b1) begin //1000M
            if (rgmii_rxc_edge == 1'b0) begin //0:DDIO Rising Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_LO;
               rgmii_rxd_LO_i    <= rgmii_rxd_HI_d1;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI_d1;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
            else begin //1:DDIO Falling Edge
               rgmii_rxd_HI_i    <= rgmii_rxd_HI;
               rgmii_rxd_LO_i    <= rgmii_rxd_LO;
               rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI;
               rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
            end
         end        
         else begin//100M or 10M
            rgmii_rxd_HI_i    <= rgmii_rxd_HI_d1;
            rgmii_rxd_LO_i    <= rgmii_rxd_LO;
            rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_LO;
            rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_HI_d1;
         end
      end

      always @ (posedge rgmii_rxc or posedge rx_reset) begin
         if (rx_reset) begin
            rxd[7:4] <= 4'h0;
            rxd[3:0] <= 4'h0;
            rx_dv    <= 1'b0;
            rx_er    <= 1'b0;
         end
         else begin
            rxd[7:4] <= rgmii_rxd_HI_sync;
            rxd[3:0] <= rgmii_rxd_LO_sync;
            rx_dv    <= rgmii_rx_ctl_HI_sync;
            rx_er    <= rgmii_rx_ctl_HI_sync^rgmii_rx_ctl_LO_sync;
         end
      end
      
      /*----------------------- RGMII Rx Sync Module -----------------------*/
      `IP_MODULE_NAME(rgmii_sync) u_rgmii_sync
      (
      //Globle Signals
          .rgmii_rxc                  (rgmii_rxc                  ),
          .rx_reset                   (rx_reset                   ),
          .eth_speed                  (eth_speed                  ),
      //RGMII Rx Interface Input
          .rgmii_rxd_HI_i             (rgmii_rxd_HI_i             ),
          .rgmii_rxd_LO_i             (rgmii_rxd_LO_i             ),
          .rgmii_rx_ctl_HI_i          (rgmii_rx_ctl_HI_i          ),
          .rgmii_rx_ctl_LO_i          (rgmii_rx_ctl_LO_i          ),
      //RGMII Rx Interface Output
          .rgmii_rxd_HI_o             (rgmii_rxd_HI_sync          ),
          .rgmii_rxd_LO_o             (rgmii_rxd_LO_sync          ),
          .rgmii_rx_ctl_HI_o          (rgmii_rx_ctl_HI_sync       ),
          .rgmii_rx_ctl_LO_o          (rgmii_rx_ctl_LO_sync       )
      );
   end
endgenerate


endmodule


module `IP_MODULE_NAME(rmii_if)
(
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//RGMII Interface
input                           rmii_clk_ref,
output  reg     [1:0]           rmii_txd,
output  reg                     rmii_tx_en,

input           [1:0]           rmii_rxd,
input                           rmii_crs_dv,
input                           rmii_rx_err

//Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [6:0]                   rx_aclk_en_cnt;
reg     [1:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_err_dl1;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg     [6:0]                   rx_odd_data_ptr;
reg     [1:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [7:0]                   gm_tx_d_temp;
reg                             tx_en_temp;
reg     [6:0]                   txbit_cnt;
reg                             rx_dv_compensate;
reg                             rx_err_compensate;
reg                             rx_err_latch;
reg     [7:0]                   rx_d_compensate;
reg     [6:0]                   rx_compensate_cnt;
// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/
always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd39)))
      aclk_en_cnt <= 7'd0;
   else
      aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_mac_aclk_en <= 1'b0;
   else if (aclk_en_cnt == 7'd0)
      tx_mac_aclk_en <= 1'b1;
   else
      tx_mac_aclk_en <= 1'b0;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      gm_tx_d_temp <= 8'h0;
   else if ((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
      gm_tx_d_temp <= gm_tx_d;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en_temp <= 1'b0;
   else if(tx_mac_aclk_en == 1'b1)
      tx_en_temp <= gm_tx_en;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      txbit_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (txbit_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (txbit_cnt == 7'd39)))
      txbit_cnt <= 7'd0;
   else if (tx_en_temp == 1'b1)
      txbit_cnt <= txbit_cnt + 1'b1;
   else
      txbit_cnt <= 7'd0; 
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       txd <= 2'h0;
   else if (eth_speed == 3'h2) begin
      case(txbit_cnt[1:0])
         2'b00: txd <= gm_tx_d_temp[1:0];
         2'b01: txd <= gm_tx_d_temp[3:2];
         2'b10: txd <= gm_tx_d_temp[5:4];
         2'b11: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case(txbit_cnt[5:0])
         6'd00: txd <= gm_tx_d_temp[1:0];
         6'd10: txd <= gm_tx_d_temp[3:2];
         6'd20: txd <= gm_tx_d_temp[5:4];
         6'd30: txd <= gm_tx_d_temp[7:6];
         default; 
      endcase 
   end
   else;    
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
      tx_en <= 1'b0;
   else 
      tx_en <= tx_en_temp;
end

always @ (posedge tx_mac_aclk or posedge tx_reset) begin
   if (tx_reset == 1'b1)
       tx_er <= 1'b0;
   else if (tx_mac_aclk_en == 1'b1)
       tx_er <= gm_tx_err;
end

always @ (posedge rmii_clk_ref or posedge tx_reset) begin 
   if (tx_reset == 1'b1) begin
      rmii_tx_en <= 1'b0;
      rmii_txd   <= 2'b0;
   end
   else begin
      rmii_tx_en  <= tx_en;
      rmii_txd    <= txd[1:0];
   end
end

/*----------------------- Rx Region ----------------------------*/
always @(posedge rmii_clk_ref or posedge rx_reset) begin
   if (rx_reset == 1'b1) begin
      rxd   <= 2'b00;
      rx_dv <= 1'b0;
      rx_er <= 1'b0;
   end
   else begin
      rxd   <= rmii_rxd;
      rx_dv <= rmii_crs_dv;
      rx_er <= rmii_rx_err;
   end
end

assign rx_mac_aclk = rmii_clk_ref;

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_aclk_en_cnt <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_aclk_en_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_aclk_en_cnt == 7'd39)))
      rx_aclk_en_cnt <= 7'd0;
   else
      rx_aclk_en_cnt <= rx_aclk_en_cnt + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_mac_aclk_en <= 1'b0;
   else if (rx_aclk_en_cnt == 7'd0)
      rx_mac_aclk_en <= 1'b1;
   else
      rx_mac_aclk_en <= 1'b0;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_odd_data_ptr <= 7'd0;
   else if (((eth_speed == 3'h2) && (rx_odd_data_ptr == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_odd_data_ptr == 7'd39)) || (rx_dv == 1'b0))
      rx_odd_data_ptr <= 7'd0;
   else 
      rx_odd_data_ptr <= rx_odd_data_ptr + 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_dl1 <= 1'b0;
   else 
      rx_dv_dl1 <= rx_dv; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_dl1 <= 1'b0;
   else 
       rx_err_dl1 <= rx_er; 
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rxd_dl1 <= 8'h0;
   else if (eth_speed == 3'h2) begin
      case (rx_odd_data_ptr[1:0])
         2'b00: rxd_dl1[1:0] <= rxd;
         2'b01: rxd_dl1[3:2] <= rxd;
         2'b10: rxd_dl1[5:4] <= rxd;
         2'b11: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end 
   else if (eth_speed == 3'h1) begin
      case (rx_odd_data_ptr[5:0])
         6'd00: rxd_dl1[1:0] <= rxd;
         6'd10: rxd_dl1[3:2] <= rxd;
         6'd20: rxd_dl1[5:4] <= rxd;
         6'd30: rxd_dl1[7:6] <= rxd;
         default; 
      endcase 
   end
   else;    
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (rx_dv_dl1 == 1'b1)
      rx_compensate_cnt <= 7'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_compensate_cnt <= rx_compensate_cnt;
   else
      rx_compensate_cnt <= rx_compensate_cnt + 1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_dv_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_dv_compensate <= 1'b0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_dv_compensate <= 1'b1;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
       rx_err_latch <= 1'b0;
   else begin
      if (rx_dv & rx_er)                rx_err_latch <= 1'b1;
      else if (rx_odd_data_ptr == 7'd0) rx_err_latch <= 1'b0; 
      else                              rx_err_latch <= rx_err_latch;
   end
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_err_compensate <= 1'b0;
   else if (((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
           ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
      rx_err_compensate <= 1'b0;
   else if (rx_odd_data_ptr == 7'd0)
      rx_err_compensate <= rx_err_latch;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      rx_d_compensate <= 8'h0;
   else if ((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
      rx_d_compensate <= rxd_dl1;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_dv <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_dv <= rx_dv_compensate;
end


always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_d <= 8'h0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_d <= rx_d_compensate;
   else;
end

always @ (posedge rx_mac_aclk or posedge rx_reset) begin
   if (rx_reset == 1'b1)
      gm_rx_err <= 1'b0;
   else if (rx_mac_aclk_en == 1'b1)
      gm_rx_err <= rx_err_compensate;
end

endmodule



//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
q8PcJMXl5LfGKk+3/kHHW66DrlE5KqEuUAmsMzgIaWRoTlHraOs4iUBfXKEyx3nc
HDsoWsS0O+n8TRTjZT+1WPh2wKbqi6uTszyz9gqd+vNQ35No23AaTUpznEyd7Ihy
OJdwGJo0bOtEevqr/VR2h52oBt5PRDhcMqjKksCtobA=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4800 )
`pragma protect data_block
[encoded data, 6500 characters]
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
RXb7/MnIF2KgPR79dgq+gyXCna6BCL8z9TYT98a0voV58Z8evdelJJw2M1oxPwc4
+OkOsaipE4C6Aa8ormkApIquk862GhxmzkIh0Mb/VT65POJP/H63CbOh7X+dSlv6
Mtjn10EyLFhUGfgTSufOLfPxTgfQ7mToMRfsNI8FWbA=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2992 )
`pragma protect data_block
rCfelTs5GgU8MzxkXfOv872lFRq0+m+1LlbYy7LqxHpfcbQ2+o4uFZ3hhEPPUQlh
LxD4V94GuRz+JLwBVwxsEf+izxm0U4B+31vVTLBq8/aGep+IlP02ohM1h1VrZJik
Lpw59jXq3dFK9Otm/F15jk6PndOAjvlmhWjh+Td/iKmTjXD0+knJ/U6eBtg1MVKL
jjE7TZqPkvi+8ENJAnZinw+enJTrBjpt4dWm4NwbYHLTysblyuoAmf7QESywDoKn
H+ynwSm8yO+EqrjRCGB7MQjgdRfNWbuU14RP7Bn8RvBIWd9u2fPbMZvAYDwhkDrI
s6VCWUOewaUWy10gnx33yeVYq6uPLtLWag4X8yILCWX7/HVrl9l7xJgGwF33VRxw
pX2vw0+Au1RpGdH3MYmpb7hdiEoUFKNfXYNJlVj5wPlKCiqvf02temX3u782IIub
7TwbSwSI+Rj75X/Nz0ZN50XlGoyT+P61oQoaZBwW50hEoBMfpUQTAUyNFzJFuGVd
ua4uhtJWpoVMaNA6V6nPpT1k2uqiqbBa2zSAGyQQItgP/+rwLoHvvVaZO7vBfMig
zjp8NIxgVvc/5eUgIBv0bSL93P+RqMGlp8e4ynMPzW4Zfp8X8IgHOTCtxxpmwwcJ
/h/ShRhb8D8F8RS8HCLO83IjcqUd7xRdABpFn7UGGLmbiXYLbap7yEvyvMPd5Xj7
L7I4GuQ7M7BBacHM1zNii0pJCeoI1mxRqN3kq4z2WmdWpCd3oEZVyciSgO7a030h
C3kjy/QxwZOimkL4xU3SznVUv3cVjEHCFOz0gUxHYgyRqMbw8g9onaAjllikT9ol
iyMTBJwwyXAa0NVHIl0BGv7VE6VGkTm537Bew4OAT347oflIdcBweT5RhQf1WHqe
O7Bo+g4AzSyxZ+6TbZ+xK+dKw6d4ptpOxXbfLwVCwRH+gDBzaDALgyne+s1+4muA
xiRCZtR0sEuQvumdWPBax32ag5EQYtkdMeVxZYtR3pL8dfgTW3E6P2/0YpSKZ5gT
IFQ4HwXJ/O6Q0hx5ik5twgi+ZV7I8bKBzyUgKlwPuGNmGDpe/e5UH4PKKC6Fp/58
1eXGiQ0euW2y2HcTLtpz3TadVWGQKdc3rz+k5ekT6a4msTfBY1AGk/ZJmdYdlP9h
FBPnfUidGv8FLpzunysXatbu1evdSmgORBElQYYucyQK/qL/pH8MdrCQP039rFXS
nXr2IjsrLM325zI4OR5WmLfc2CpHZwou8l1DbUfeq3yfP+9SW6fRKf8VGM+e7bZI
qIdpHXbVFagKWwg+V5jHabulXCi2D8c9HErmJ2mpbYdBn3j833Z7BZkZwG48z66X
IRNtkhSVXjdo3Dhfz6Yw7N+RZ9UMK3Kn1dBWkuEdxlNBN4IVxhEbbWsc8eVQYoAn
v4/37Qhwr3KuYIEWqEpCme3fbdDprNZK3VWoTIwb4ViCvsfVyWPVYH+ga1sU54Vl
kvqZCIrpFMKipQx+u4Msz+jNeynSwR0CfKSqgpNDP/uU9rGfM4oeMoFDIWN3GPb+
Qc7PMRgJE9ysoNWpvitaFp43L4flQqJxEFQ3Udbt61Tcp83sezCyYfqRiVTYLENx
vYV7+LzDTX/YwEp55IZbArGXm6KhSYJ3lhFayXWDU7cER2mdqw7THeY2R5P9ejEy
74rSvO+2PS35R5HfGIYW2rJfVJqfDsPg6yiqeXaKIWjteOJr3DoV7XydZXnvS75V
P/K0LkyQAhZUPq210lXfFXU0ZLCLIJyhzLuyIS7wvFyHVjXpu3kodZhmVbaEjwvw
yanh4CpeMAUG1ZLM2Y18ukC65W2P0scTGpJNmiXlShS8SetsWjMC4rbm4b53Y5VH
xScfs1v1shfvHR480dEbPGPFhKhmPMU6cS1eCyG4Jej73YOhZX/Q8QBj0LlRzEWG
/DLr1Yhxk4p+eC04kA+/NtWR8iZAurihUiHy3YZ3Q1yeEikj/L3EPACVE/Lw8ekk
WGTwKmoaZlXjvdIkwpo0IMIBFpfmM6/XdJg7YVcz6l2j9Z3WjAFzZuEPV6k5tlTk
esmwk0bAFn6g4iEO3NMjrHGlTwZznzEgXHrPg4tBDwX3Mgg/5NX0TkHY55uP/J62
duA4g9UCamCBEbxyTjKXQ7421IOJaT4PIZ42eixOVWYPotVzufz5pmrLEeBMH8D2
Rp3a4BYy/E1KabpvGBAdD0DdkG4phuxZ2Q2gUF72CivMKquejicyfJp2pxAPI2tC
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be0oYK+OitIA8dg4+DZ0cLCSEMefVr91ED0S0QW31oXSew9+LC7Zw1gDQQAQFzUp
MHvZkZAM0TX+p4PxAtPgNh2+wg0Wi4KspVvHiCdYtGK1fHK2bjyQCzcC7d+KUsCk
C4K6V2oRBS8mYZmY8mu8Co3zqvvd7urtpL3gW8PgQe3klHa+bX8JU+Hzq9CFGDsc
HFyoqHXP+8QU04O5Sn8hl1eDzdpwQPk5mKGnkPwtCplXrGC+SAmgBTOA+BpJFl7c
ldf5V/R9KdavG+sTdCZ0fB5d+XE0spUKHJe3TKx3Tb/vBIIfj9oezJOyfUT5lE6D
P15Ds75IFDmyIrRXW8y6GlfIxtXsrImt5gNpIn9XUx42OZWnfL8+/cz9xB/QTSnO
jm64n53hFG1eRByK8drP7X1fsIbbTv7q+5UoslBh23GIInoV1RMSvWdN2w1dn6pP
ex7l/KvkRorgvxqwNrXo9o3mqEQ29blNR7Q0P2UYcvi5cGjAaV0QSi9jrTcCaadB
xhQ7K+4Fg8e5kU07MAheqvZB/X/JJIrjDBf0sHcK003K/+mHNeh8pLKBa7Scj3Hc
tF5MVNjL10glJlZBLxOhrX+kxmYBeO2fqxi6CJ/RNwLDDu1NNCPJC4dHl73oIu6N
MjAh8KZ5BwLBNtK9+saL5rBO9M+acyGGcN8/zuauCgIjJj+QKbEg3AKttAqPKIcl
AthLEEnwQAOlAHkLDHxDOLWXnRPv6zGyLCE4Ft+0Lu7JedO7SMogUkTO1UKt0bvT
g41XaYuQPFbHhDbzE3XozEpxfvR94MbbzDvJIWFxR9DosmE8VAm5Gn7r6gkOVgVb
NEtvfxLSXdAnkclJWY21GMXOnO9OTIqtJQcAMUSrM/qmiRYsGi9yqTfHYFw15ZiC
xOC/cTZFVEcjKro0pAkvG6NsLZwzBlaYKF6e7jG84VBqNr6lFQmLWOL2kdtnDEdo
UaSDr5Yg1ewhFVIyM5oqjLYav+gSH+7no8A5lqCld3sZqhC8xQlL7rnnCkbYfY90
ivdd4pN1nt9vlit7Wu6ZS/uW0aJXD68p07CiYmFWOA6fs0qoGfhQ0OYHjuGpWFeu
SXmSrAiCOYD9nEvcRtzBZcwJAnf8SI5zphxsky8/KcQRsP2S4CFb6m5YF242Wibj
oWxZUigRr33oqlM/MI33I/Pm2ZINDM5gHUlcsA3CfQqpAWR0oRkLZTjYyhuP7xFU
z16TQmZv4fBBev5cb9cLmp6R+XcQfjMBCQtaJq0Iemp1TmpSNwezeo4K2m3EE4tB
2cD/+icey4ftAuDa6sDhh/PpIg7OnDCw2QHE/MY6MO1agMgTNafAHBhRIfPaOgSF
1y5dy86sfwpH9x0KIJmoWQHWor7IkWM/beRvgPHwvcCZKmh2nLYWPYllWOpuWaIr
OmAkTMQEsIVPzgE/yWkgWB/IpyTyzBGDx5tTj4CDW9dmPpBbcrqis0nJwlVy6f19
n4mQeqj1xJZVh7+Hux5tvuA+FE9Y7VbO7w13jiOzWHXVpfYHr24619qYHz292VB1
Yo/GlUkVYSKMeZUQLCWukCAHtQt3oRNiCogd3Oy8qHvgZlAhb/3Yf3k9nskksysX
I/CzpfO+pgi2nb3hlnyvrl4s+tk8Ixr0+7OvSXIo+4E5M+0uRCY3IAr9ifKzOA50
Dfzw+oxCbfNnxGVzvGZqkw==
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
tyRA8q+GIVvhzUoLCt5OquZ7W4mh8VySEiFjY8lt2VEIw7HGJZXwP5ZQGNO0pCHA
dQ1DETRwEXOvEodbLf2vuORjxLW1qosVcagxgRTOPEzmVKWwwGpgxN9up0y7bA9D
L+C4LToewkTgNql98xIcIAin0UpV+OUPf95D0m+X9v0=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4640 )
`pragma protect data_block
[encoded data, 6240 characters]
4D/xIakmPdEOpWbrBYgmlXoHnEIvCkEgyeCKlG+wVgc=
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
U/5y1MEBEaTmlQC7LqO0Tj0iT886nCX6c5pUT7jlgtUvSQnmUALfc31TW5BlLjMA
uxAHwMXDPDIRw7oDd6++JCn950RgorT+ETQ2WIph5/HXeuA5xJY4NkxaWhtOojTL
FyqudPjCaNJf2ipSrrzjJuyfVs78Q0+ZeXqzxFobYDY=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3936 )
`pragma protect data_block
[encoded data, 5330 characters]
`pragma protect end_protected

//pragma protect end


module `IP_MODULE_NAME(efx_mac1gbe) #(
   parameter FAMILY = "TRION",
   parameter VERSION = 32'h20,
   parameter RXFIFO_EN = 1,
   parameter RXFIFO_DTH = 2048,
   parameter TXFIFO_EN = 1,
   parameter TXFIFO_DTH = 2048,
   parameter PHY_INTF_MODE = 0,  
   parameter LOOPBACK_EN = 1'b0,
   parameter GMII_DW = PHY_INTF_MODE == 4 ? 16 : 8,
   parameter AXIS_DW = 8,  
   parameter APBIF = 0,
   parameter NO_PREAMBLE = 0,
   parameter INTER_PACKET_GAP = 6'd12,
   parameter MTU_FRAME_LENGTH = 16'd1518,
   parameter MAC_SOURCE_ADDRESS = 48'h0,
   parameter ENABLE_BROADCAST_FILTERING = 1'b1,
   parameter RGMII_RXC_EDGE = 1'b1,
   parameter RGMII_TXC_DLY = 1'b1,
   parameter PKT_CNT_MAX = 256, 
   parameter SIP600 = 0 
) (
   input                  tx_mac_aclk,
   output                 rx_mac_aclk,
   input                  mac_reset,   
   input                  proto_reset, 
   input                  tx_axis_clk,
   input [AXIS_DW-1:0]    tx_axis_mac_tdata,
   input                  tx_axis_mac_tvalid,
   input                  tx_axis_mac_tlast,
   input [AXIS_DW/8-1:0]  tx_axis_mac_tstrb,
   input                  tx_axis_mac_tuser,
   output                 tx_axis_mac_tready,
   input                  rx_axis_clk,
   output [AXIS_DW-1:0]   rx_axis_mac_tdata,
   output                 rx_axis_mac_tvalid,
   output                 rx_axis_mac_tlast,
   output [AXIS_DW/8-1:0] rx_axis_mac_tstrb,
   output                 rx_axis_mac_tuser,
   input                  rx_axis_mac_tready,
   input                  gm_rx_c,
   input  [GMII_DW-1:0]   gm_rx_d,
   input  [GMII_DW/8-1:0] gm_rx_dv,
   input  [GMII_DW/8-1:0] gm_rx_err,
   output                 gm_tx_c,
   output [GMII_DW-1:0]   gm_tx_d,
   output [GMII_DW/8-1:0] gm_tx_en,
   output [GMII_DW/8-1:0] gm_tx_err,
   output [3:0]           rgmii_txd_HI,
   output [3:0]           rgmii_txd_LO,
   output                 rgmii_tx_ctl_HI,
   output                 rgmii_tx_ctl_LO,
   output                 rgmii_txc_HI,
   output                 rgmii_txc_LO,
   input  [3:0]           rgmii_rxd_HI,
   input  [3:0]           rgmii_rxd_LO,
   input                  rgmii_rx_ctl_HI,
   input                  rgmii_rx_ctl_LO,
   input                  rgmii_rxc,
   input                  mii_txc,
   output [3:0]           mii_txd,
   output                 mii_tx_dv,
   output                 mii_tx_err,
   input                  mii_rxc,
   input  [3:0]           mii_rxd,
   input                  mii_rx_dv,
   input                  mii_rx_err,
   input                  rmii_clk_ref,
   output [1:0]           rmii_txd,
   output                 rmii_tx_en,
   input  [1:0]           rmii_rxd,
   input                  rmii_crs_dv,
   input                  rmii_rx_err,
   input  [9:0]           s_paddr,
   input  [31:0]          s_pwdata,
   input                  s_pwrite,
   input                  s_penable,
   input                  s_psel,
   output [31:0]          s_prdata,
   output                 s_pready,
   output                 s_perr,
   input                  s_axi_aclk,    
   input  [9:0]           s_axi_awaddr,  
   input                  s_axi_awvalid, 
   output                 s_axi_awready, 
   input  [31:0]          s_axi_wdata,   
   input                  s_axi_wvalid,  
   output                 s_axi_wready,  
   output [1:0]           s_axi_bresp,   
   output                 s_axi_bvalid,  
   input                  s_axi_bready,  
   input  [9:0]           s_axi_araddr,  
   input                  s_axi_arvalid, 
   output                 s_axi_arready, 
   output [1:0]           s_axi_rresp,   
   output [31:0]          s_axi_rdata,   
   output                 s_axi_rvalid,  
   input                  s_axi_rready,  
`ifdef ONCHIP_PHY
   input  logic           init_clk,
   input  logic           init_rst_n,
   input  logic           PMA_CMN_READY,
   input  logic           PMA_XCVR_PLLCLK_EN_ACK,
   input  logic [3:0]     PMA_XCVR_POWER_STATE_ACK,
   input  logic           PMA_RX_SIGNAL_DETECT,
   output logic           PMA_XCVR_PLLCLK_EN,
   output logic [3:0]     PMA_XCVR_POWER_STATE_REQ,
   output logic           phy_init_done,
`else
   output                 Mdo,   
   output                 MdoEn, 
   input                  Mdi,   
   output                 Mdc,   
`endif
   output [2:0]           eth_speed
);
`ifdef ONCHIP_PHY
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4"
`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 )
`pragma protect key_block
LyznSVfsT/QtbT6eanx7nWulnCFr2VHPkh8sRRF2JDG7gO8/HJcMTh4Zk6NhoalF
HACF6ZiOeiTKY7CqkFlYT+nSRqLaFdUyzGrapdVLLiZ0HKetIhPqvxwnpPVsPaRR
MjVPO3LkNyDMf+op8W83C1e+2N0uJ2Xqdo1JJZI4G+M=
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4864 )
`pragma protect data_block
[encoded data, 6565 characters]
6TB9Y89hmRp3+nI2rSt3NQ==
`pragma protect end_protected

//pragma protect end


// Module: efx_pulse_sync
// Description:
//   Safely transfers a single-cycle pulse from a source clock domain to a
//   destination clock domain using a toggle-based synchronization scheme.
//
// ==========================================================================

module `IP_MODULE_NAME(efx_pulse_sync) #(
   parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
   parameter OFF_ASSERTION = 0
) (
   input  src_clk,      // Source clock (e.g., tx_axis_clk)
   input  src_reset,    // Reset for source domain
   input  pulse_in,     // Single-cycle pulse in src_clk domain

   input  dst_clk,      // Destination clock (e.g., tx_clk)
   input  dst_reset,    // Reset for destination domain
   output pulse_out     // Single-cycle pulse in dst_clk domain
);

// Toggle generation in source clock domain
reg toggle_src;

// Synchronizer flops in destination clock domain
wire toggle_sync;
reg  toggle_sync_r;

generate
   if (ACTIVE_LOW == 1) begin
      always @ (posedge src_clk or negedge src_reset) begin
         if (!src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

     `IP_MODULE_NAME(efx_asyncreg) #(
        .WIDTH         (1),
        .OFF_ASSERTION (OFF_ASSERTION)
     ) efx_asyncreg_toggle_src (
        .clk     (dst_clk),
        .reset_n (dst_reset),
        .d_i     (toggle_src),
        .d_o     (toggle_sync)
     );
      
      always @ (posedge dst_clk or negedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
   else begin
      always @ (posedge src_clk or posedge src_reset) begin
         if (src_reset)
            toggle_src <= 1'b0;
         else if (pulse_in)
            toggle_src <= ~toggle_src;
         else
            toggle_src <= toggle_src;
      end

      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH         (1),
         .ACTIVE_HIGH   (0),
         .OFF_ASSERTION (OFF_ASSERTION)
      ) efx_asyncreg_toggle_src (
         .clk     (dst_clk),
         .reset_n (dst_reset),
         .d_i     (toggle_src),
         .d_o     (toggle_sync)
      );
      
      always @ (posedge dst_clk or posedge dst_reset) begin
         if (!dst_reset) begin
            toggle_sync_r <= 1'b0;
         end 
         else begin
            toggle_sync_r <= toggle_sync;  // Delay for edge detect
         end
      end
   end
endgenerate

// Generate one-cycle pulse in destination domain
assign pulse_out = toggle_sync ^ toggle_sync_r;

endmodule



module `IP_MODULE_NAME(efx_data_pipeline)  #(
    parameter HBP = 1,
    parameter DATA_WIDTH = 256,
    parameter MUX_IN = 1
)(
  input               upstream_valid_i,
  output              upstream_ready_o,
  input      [DATA_WIDTH-1:0]   upstream_data_i,
  output              downstream_valid_o,
  input               downstream_ready_i,
  output     [DATA_WIDTH-1:0]   downstream_data_o,
  input               clk,
  input               resetn
);
//pragma protect
//pragma protect begin
`protected
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Z0E4/+)&+4F&8=R?>A8H4ICZ3cca>dT0Z##VWI^bg9,e_2ARQ4cESBD:^#X8&4EF
^)(+6O#1BVAT4F1I4Q7S/)1KURg-U]@DU3,+.bC_Y<&RUOVYGa]^QS2-#/[@DA/N
U#Gb=Qg?OaP0Y8[-U.G00VE.ISMfeX;M#/&@F7JE+dZFZK,P^\L<Jde6C8=RW[9O
W5FX_0;&P=)<,+J(I;OC/NCN0b_MU[9V_#NL,JK3C?#N.I8+8[M/-gCN?F,NBJ9I
Y58-3CR:+Nb[+(J)7:J(EcVPJ\ZDE016J8Y.O#:2U_]MZ\4#:a,cPgbRZ:\aB](S
e+_/\Oc.bLa&[#;7UP-NCJV+G^+?78McEM902;5I9dRME$
`endprotected

//pragma protect end

`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME
