{
    "args": [
        "-o",
        "gDMA",
        "--base_path",
        "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
        "--vlnv",
        {
            "vendor": "efinixinc.com",
            "library": "bridges_and_adaptors",
            "name": "efx_dma",
            "version": "6.4.2"
        }
    ],
    "conf": {
        "PriorityEncode": "1'b0",
        "WrQueue": "1'b0",
        "CTRL_ASYNC_MODE": "1'b1",
        "EfinixDDR": "1'b0",
        "RdQueue": "1'b0",
        "BufferWidth": "64",
        "BufferWords": "512",
        "MemExtWidth": "128",
        "CH0_SGMode": "1'b1",
        "CH0_Output": "1'b0",
        "CH0_Input": "1'b1",
        "CH4_Input": "1'b1",
        "CH4_Width": "32",
        "CH4_Output": "1'b1",
        "CH4_SGMode": "1'b0",
        "CH4_SR": "1'b0",
        "CH5_BurstSize": "64",
        "CH5_BufferSize": "1024",
        "CH5_SR": "1'b0",
        "CH6_Output": "1'b1",
        "CH6_SGMode": "1'b0",
        "CH6_SR": "1'b0",
        "CH7_Output": "1'b1",
        "CH7_SGMode": "1'b0",
        "CH7_SR": "1'b0",
        "CH7_Input": "1'b1",
        "CH7_Width": "32",
        "CH7_BurstSize": "64",
        "CH7_BufferSize": "1024",
        "CH6_Width": "32",
        "CH6_Input": "1'b1",
        "CH6_BurstSize": "64",
        "CH6_BufferSize": "1024",
        "CH5_Width": "32",
        "CH5_Output": "1'b1",
        "CH5_SGMode": "1'b0",
        "CH5_Input": "1'b1",
        "CH4_BurstSize": "64",
        "CH4_BufferSize": "1024",
        "CH3_SR": "1'b0",
        "CH3_SGMode": "1'b0",
        "CH3_Output": "1'b1",
        "CH3_Width": "32",
        "CH3_Input": "1'b1",
        "CH3_BufferSize": "1024",
        "CH3_BurstSize": "64",
        "BufferCount": "2",
        "CH0_Enable": "1'b1",
        "CH1_Enable": "1'b1",
        "CH1_AsyncMode": "1'b1",
        "CH6_AsyncMode": "1'b0",
        "CH5_AsyncMode": "1'b0",
        "CH7_AsyncMode": "1'b0",
        "CH0_AsyncMode": "1'b1",
        "CH3_AsyncMode": "1'b0",
        "CH2_AsyncMode": "1'b0",
        "CH4_AsyncMode": "1'b0",
        "CH0_BufferSize": "4096",
        "CH0_BurstSize": "1024",
        "CH0_SR": "1'b0",
        "CH0_Width": "8",
        "CH1_Input": "1'b0",
        "CH1_Width": "8",
        "CH1_Output": "1'b1",
        "CH1_SGMode": "1'b1",
        "CH1_SR": "1'b0",
        "CH2_BufferSize": "1024",
        "CH2_BurstSize": "64",
        "CH2_Width": "32",
        "CH2_SR": "1'b0",
        "CH2_SGMode": "1'b0",
        "CH2_Output": "1'b1",
        "CH2_Input": "1'b1",
        "CH1_BufferSize": "4096",
        "CH1_BurstSize": "1024",
        "CH2_Enable_user": "1'b0",
        "CH2_Enable_default": "1'b0",
        "CH3_Enable_default": "1'b0",
        "CH3_Enable_user": "1'b0",
        "CH4_Enable_default": "1'b0",
        "CH4_Enable_user": "1'b0",
        "CH5_Enable_user": "1'b0",
        "CH5_Enable_default": "1'b0",
        "CH6_Enable_user": "1'b0",
        "CH6_Enable_default": "1'b0",
        "CH7_Enable_user": "1'b0",
        "CH7_Enable_default": "1'b0",
        "CustomSGBus": "1'b0",
        "CH0_MemMode": "1'b0",
        "CH1_MemMode": "1'b0",
        "CH2_MemMode": "1'b0",
        "CH3_MemMode": "1'b0",
        "CH4_MemMode": "1'b0",
        "CH5_MemMode": "1'b0",
        "CH6_MemMode": "1'b0",
        "CH7_MemMode": "1'b0"
    },
    "output": {
        "external_script_generator": [],
        "external_source_source": [
            "gDMA/gDMA_define.vh",
            "gDMA/gDMA.v",
            "gDMA/gDMA_tmpl.v",
            "gDMA/gDMA_tmpl.vhd"
        ],
        "external_script_script": []
    },
    "ooc_synthesis": {},
    "sw_version": "2025.2.272",
    "generated_date": "2025-10-16T09:35:15.778966+00:00"
}