From 470bbc39ec66a0aacd9fad9709383589d8479b58 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sat, 18 Apr 2026 19:19:55 -0700 Subject: [PATCH] Grand refactor --- fpga/fpga6502.xml | 104 +- fpga/ip/EfxSapphireHpSoc_slb/.gitignore | 3 + .../EfxSapphireHpSoc_slb.v | 8651 ---------- .../EfxSapphireHpSoc_slb_define.vh | 46 - .../EfxSapphireHpSoc_slb_tmpl.v | 148 - .../EfxSapphireHpSoc_slb_tmpl.vhd | 251 - .../EfxSapphireHpSoc_wrapper.v | 402 - fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini | 224 - .../EfxSapphireHpSoc_slb/ipm/component.pickle | Bin 153558 -> 0 bytes fpga/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle | Bin 346344 -> 0 bytes fpga/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json | 20 - fpga/ip/EfxSapphireHpSoc_slb/settings.json | 10 +- .../source/Axi4PeripheralTop.v | 8070 --------- .../EfxSapphireHpSoc_slb/source/peri_config | 8 - fpga/ip/gAXIM_2to1_switch/.gitignore | 3 + fpga/ip/gAXIM_2to1_switch/axi_interconnect.vh | 2 - fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v | 1349 -- .../gAXIM_2to1_switch_define.vh | 53 - .../gAXIM_2to1_switch_tmpl.v | 137 - .../gAXIM_2to1_switch_tmpl.vhd | 229 - .../ip/gAXIM_2to1_switch/ipm/component.pickle | Bin 55707 -> 0 bytes fpga/ip/gAXIM_2to1_switch/ipm/graph.pickle | Bin 110820 -> 0 bytes fpga/ip/gAXIS_1to3_switch/.gitignore | 3 + fpga/ip/gAXIS_1to3_switch/axi_interconnect.vh | 2 - fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v | 1349 -- .../gAXIS_1to3_switch_define.vh | 53 - .../gAXIS_1to3_switch_tmpl.v | 137 - .../gAXIS_1to3_switch_tmpl.vhd | 229 - .../ip/gAXIS_1to3_switch/ipm/component.pickle | Bin 55704 -> 0 bytes fpga/ip/gAXIS_1to3_switch/ipm/graph.pickle | Bin 110808 -> 0 bytes fpga/ip/gDMA/.gitignore | 3 + fpga/ip/gDMA/gDMA.v | 11641 ------------- fpga/ip/gDMA/gDMA_define.vh | 45 - fpga/ip/gDMA/gDMA_tmpl.v | 114 - fpga/ip/gDMA/gDMA_tmpl.vhd | 183 - fpga/ip/gDMA/ipm/component.pickle | Bin 156601 -> 0 bytes fpga/ip/gDMA/ipm/graph.pickle | Bin 360974 -> 0 bytes fpga/ip/gDMA/source/EfxDMA.v | 11449 ------------- fpga/ip/gDMA/source/dma_config.json | 71 - fpga/ip/gSDHC/.gitignore | 3 + fpga/ip/gSDHC/gSDHC.v | 12571 -------------- fpga/ip/gSDHC/gSDHC_define.vh | 47 - fpga/ip/gSDHC/gSDHC_tmpl.v | 111 - fpga/ip/gSDHC/gSDHC_tmpl.vhd | 177 - fpga/ip/gSDHC/ipm/component.pickle | Bin 53757 -> 0 bytes fpga/ip/gSDHC/ipm/graph.pickle | Bin 111412 -> 0 bytes fpga/ip/gTSE/.gitignore | 3 + fpga/ip/gTSE/T120F324_devkit/DaulClkFifo.v | 498 - .../gTSE/T120F324_devkit/apb3_2_axi4_lite.v | 215 - fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v | 61 - fpga/ip/gTSE/T120F324_devkit/gTSE.sv | 9844 ----------- fpga/ip/gTSE/T120F324_devkit/gTSE_define.svh | 61 - fpga/ip/gTSE/T120F324_devkit/header.v | 2 - ...toplevel_system_ramA_logic_ram_symbol0.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol1.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol2.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol3.bin | 8192 --------- .../T120F324_devkit/ip/sapphire/sapphire.v | 14222 ---------------- .../ip/sapphire/sapphire_define.vh | 45 - .../ip/sapphire/sapphire_tmpl.v | 76 - .../ip/sapphire/sapphire_tmpl.vhd | 118 - .../T120F324_devkit/ip/sapphire/settings.json | 156 - .../source/hardware/netlist/EfxSapphireSoc.v | 14093 --------------- ...toplevel_system_ramA_logic_ram_symbol0.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol1.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol2.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol3.bin | 8192 --------- .../ip/sapphire/source/soc_config | 23 - fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v | 241 - fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v | 139 - fpga/ip/gTSE/T120F324_devkit/reg_apb3.v | 333 - fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v | 206 - .../ip/gTSE/T120F324_devkit/temac_ex.peri.xml | 131 - fpga/ip/gTSE/T120F324_devkit/temac_ex.v | 563 - fpga/ip/gTSE/T120F324_devkit/temac_ex.xml | 92 - fpga/ip/gTSE/T120F324_devkit/timing.sdc | 53 - fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v | 497 - fpga/ip/gTSE/Testbench/DaulClkFifo.v | 498 - fpga/ip/gTSE/Testbench/ODDR.v | 159 - fpga/ip/gTSE/Testbench/aldec/gTSE.sv | 9845 ----------- fpga/ip/gTSE/Testbench/apb3_2_axi4_lite.v | 215 - fpga/ip/gTSE/Testbench/axi4_st_mux.v | 61 - fpga/ip/gTSE/Testbench/gTSE.sv | 9844 ----------- fpga/ip/gTSE/Testbench/gTSE_define.svh | 61 - fpga/ip/gTSE/Testbench/glbl.v | 71 - fpga/ip/gTSE/Testbench/mac_pat_gen.v | 241 - fpga/ip/gTSE/Testbench/mac_rx2tx.v | 139 - fpga/ip/gTSE/Testbench/modelsim.do | 6 - fpga/ip/gTSE/Testbench/modelsim/gTSE.sv | 4617 ----- fpga/ip/gTSE/Testbench/ncsim/gTSE.sv | 9954 ----------- fpga/ip/gTSE/Testbench/reg_apb3.v | 333 - fpga/ip/gTSE/Testbench/rgmii_2_rmii.v | 206 - fpga/ip/gTSE/Testbench/synopsys/gTSE.sv | 9754 ----------- fpga/ip/gTSE/Testbench/tb_header.v | 1 - fpga/ip/gTSE/Testbench/tb_top.v | 831 - fpga/ip/gTSE/Testbench/temac_ex.v | 563 - fpga/ip/gTSE/Testbench/udp_pat_gen.v | 497 - fpga/ip/gTSE/Ti60F225_devkit/DaulClkFifo.v | 498 - .../gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v | 215 - fpga/ip/gTSE/Ti60F225_devkit/axi4_st_mux.v | 61 - fpga/ip/gTSE/Ti60F225_devkit/gTSE.sv | 9844 ----------- fpga/ip/gTSE/Ti60F225_devkit/gTSE_define.svh | 61 - fpga/ip/gTSE/Ti60F225_devkit/header.v | 2 - ...toplevel_system_ramA_logic_ram_symbol0.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol1.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol2.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol3.bin | 8192 --------- .../Ti60F225_devkit/ip/sapphire/sapphire.v | 14222 ---------------- .../ip/sapphire/sapphire_define.vh | 45 - .../ip/sapphire/sapphire_tmpl.v | 76 - .../ip/sapphire/sapphire_tmpl.vhd | 118 - .../Ti60F225_devkit/ip/sapphire/settings.json | 156 - .../source/hardware/netlist/EfxSapphireSoc.v | 14093 --------------- ...toplevel_system_ramA_logic_ram_symbol0.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol1.bin | 8192 --------- ...toplevel_system_ramA_logic_ram_symbol2.bin | 8192 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.../gTSE_1to2_switch_define.vh | 53 - .../gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v | 97 - .../gTSE_1to2_switch_tmpl.vhd | 149 - fpga/ip/gTSE_1to2_switch/ipm/component.pickle | Bin 55706 -> 0 bytes fpga/ip/gTSE_1to2_switch/ipm/graph.pickle | Bin 110804 -> 0 bytes fpga/ip/gTSE_core_fifo_ctrl/.gitignore | 3 + .../gTSE_core_fifo_ctrl.sv | 1587 -- .../gTSE_core_fifo_ctrl_define.svh | 66 - .../gTSE_core_fifo_ctrl_tmpl.sv | 60 - .../gTSE_core_fifo_ctrl_tmpl.vhd | 75 - .../gTSE_core_fifo_ctrl/ipm/component.pickle | Bin 47078 -> 0 bytes fpga/ip/gTSE_core_fifo_ctrl/ipm/graph.pickle | Bin 99769 -> 0 bytes fpga/ip/gTSE_core_fifo_data/.gitignore | 3 + .../gTSE_core_fifo_data.sv | 1587 -- .../gTSE_core_fifo_data_define.svh | 66 - .../gTSE_core_fifo_data_tmpl.sv | 60 - .../gTSE_core_fifo_data_tmpl.vhd | 75 - .../gTSE_core_fifo_data/ipm/component.pickle | Bin 47086 -> 0 bytes fpga/ip/gTSE_core_fifo_data/ipm/graph.pickle | Bin 99780 -> 0 bytes src/fpga6502_top.sv | 354 + .../source => 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fpga/ip/gTSE_core_fifo_data/ipm/graph.pickle create mode 100644 src/fpga6502_top.sv rename {fpga/source => src/soc}/MacRxCheckSumChecker.v (100%) rename {fpga/source => src/soc}/MacTxLso.v (100%) rename {fpga/source => src/soc}/design_modules.v (100%) rename {fpga/source => src/soc}/top_soc.v (96%) rename {fpga/source => src/soc}/tseCore.v (100%) diff --git a/fpga/fpga6502.xml b/fpga/fpga6502.xml index e421b36..b3c3086 100644 --- a/fpga/fpga6502.xml +++ b/fpga/fpga6502.xml @@ -1,18 +1,106 @@ - + - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ip/EfxSapphireHpSoc_slb/.gitignore b/fpga/ip/EfxSapphireHpSoc_slb/.gitignore new file mode 100644 index 0000000..4e31dc3 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!settings.json \ No newline at end of file diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v deleted file mode 100644 index 80a2457..0000000 --- a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v +++ /dev/null @@ -1,8651 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 1.22.0 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _035069daf0ad4fb491e9c65d79bd2ddd -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module EfxSapphireHpSoc_slb -( - input io_peripheralClk, - input io_peripheralReset, - output io_asyncReset, - input io_gpio_sw_n, - input pll_peripheral_locked, - input pll_system_locked, - output jtagCtrl_capture, - output jtagCtrl_enable, - output jtagCtrl_reset, - output jtagCtrl_shift, - output jtagCtrl_tdi, - input jtagCtrl_tdo, - output jtagCtrl_update, - input ut_jtagCtrl_capture, - input ut_jtagCtrl_enable, - input ut_jtagCtrl_reset, - input ut_jtagCtrl_shift, - input ut_jtagCtrl_tdi, - output ut_jtagCtrl_tdo, - input ut_jtagCtrl_update, - input system_spi_0_io_data_0_read, - output system_spi_0_io_data_0_write, - output system_spi_0_io_data_0_writeEnable, - input system_spi_0_io_data_1_read, - output system_spi_0_io_data_1_write, - output system_spi_0_io_data_1_writeEnable, - input system_spi_0_io_data_2_read, - output system_spi_0_io_data_2_write, - output system_spi_0_io_data_2_writeEnable, - input system_spi_0_io_data_3_read, - output system_spi_0_io_data_3_write, - output system_spi_0_io_data_3_writeEnable, - output system_spi_0_io_sclk_write, - output [3:0] system_spi_0_io_ss, - input system_uart_0_io_rxd, - output system_uart_0_io_txd, - input system_i2c_0_io_scl_read, - output system_i2c_0_io_scl_write, - input system_i2c_0_io_sda_read, - input [3:0] system_gpio_0_io_read, - output [3:0] system_gpio_0_io_write, - output [3:0] system_gpio_0_io_writeEnable, - input cfg_done, - output cfg_start, - output cfg_sel, - output cfg_reset, - output axiAInterrupt, - input [31:0] axiA_awaddr, - input [7:0] axiA_awlen, - input [2:0] axiA_awsize, - input [1:0] axiA_awburst, - input axiA_awlock, - input [3:0] axiA_awcache, - input [2:0] axiA_awprot, - input [3:0] axiA_awqos, - input [3:0] axiA_awregion, - input axiA_awvalid, - output axiA_awready, - input [31:0] axiA_wdata, - input [3:0] axiA_wstrb, - input axiA_wvalid, - input axiA_wlast, - output axiA_wready, - output [1:0] axiA_bresp, - output axiA_bvalid, - input axiA_bready, - input [31:0] axiA_araddr, - input [7:0] axiA_arlen, - input [2:0] axiA_arsize, - input [1:0] axiA_arburst, - input axiA_arlock, - input [3:0] axiA_arcache, - input [2:0] axiA_arprot, - input [3:0] axiA_arqos, - input [3:0] axiA_arregion, - input axiA_arvalid, - output axiA_arready, - output [31:0] axiA_rdata, - output [1:0] axiA_rresp, - output axiA_rlast, - output axiA_rvalid, - input axiA_rready, - output userInterruptA, - output userInterruptB, - output userInterruptC, - output userInterruptD, - output userInterruptE, - output userInterruptF, - output [31:0] io_apbSlave_0_PADDR, - output io_apbSlave_0_PENABLE, - input [31:0] io_apbSlave_0_PRDATA, - input io_apbSlave_0_PREADY, - output io_apbSlave_0_PSEL, - input io_apbSlave_0_PSLVERROR, - output [31:0] io_apbSlave_0_PWDATA, - output io_apbSlave_0_PWRITE, - output system_i2c_0_io_sda_write, - output system_i2c_0_io_sda_writeEnable, - output system_i2c_0_io_scl_writeEnable, - output system_watchdog_hardPanic_reset -); -`IP_MODULE_NAME(Axi4Peripheral_wrapper) -#( - .PERI_FREQ (200) -) -u_Axi4Peripheral_wrapper -( - .io_peripheralClk ( io_peripheralClk ), - .io_peripheralReset ( io_peripheralReset ), - .io_asyncReset ( io_asyncReset ), - .io_gpio_sw_n ( io_gpio_sw_n ), - .pll_peripheral_locked ( pll_peripheral_locked ), - .pll_system_locked ( pll_system_locked ), - .jtagCtrl_capture ( jtagCtrl_capture ), - .jtagCtrl_enable ( jtagCtrl_enable ), - .jtagCtrl_reset ( jtagCtrl_reset ), - .jtagCtrl_shift ( jtagCtrl_shift ), - .jtagCtrl_tdi ( jtagCtrl_tdi ), - .jtagCtrl_tdo ( jtagCtrl_tdo ), - .jtagCtrl_update ( jtagCtrl_update ), - .ut_jtagCtrl_capture ( ut_jtagCtrl_capture ), - .ut_jtagCtrl_enable ( ut_jtagCtrl_enable ), - .ut_jtagCtrl_reset ( ut_jtagCtrl_reset ), - .ut_jtagCtrl_shift ( ut_jtagCtrl_shift ), - .ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ), - .ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ), - .ut_jtagCtrl_update ( ut_jtagCtrl_update ), - .system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), - .system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), - .system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), - .system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), - .system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), - .system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), - .system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), - .system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), - .system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), - .system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), - .system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), - .system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), - .system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), - .system_spi_0_io_ss ( system_spi_0_io_ss ), - .system_uart_0_io_rxd ( system_uart_0_io_rxd ), - .system_uart_0_io_txd ( system_uart_0_io_txd ), - .system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ), - .system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ), - .system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ), - .system_gpio_0_io_read ( system_gpio_0_io_read ), - .system_gpio_0_io_write ( system_gpio_0_io_write ), - .system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ), - .cfg_done ( cfg_done ), - .cfg_start ( cfg_start ), - .cfg_sel ( cfg_sel ), - .cfg_reset ( cfg_reset ), - .axiAInterrupt ( axiAInterrupt ), - .axiA_awaddr ( axiA_awaddr ), - .axiA_awlen ( axiA_awlen ), - .axiA_awsize ( axiA_awsize ), - .axiA_awburst ( axiA_awburst ), - .axiA_awlock ( axiA_awlock ), - .axiA_awcache ( axiA_awcache ), - .axiA_awprot ( axiA_awprot ), - .axiA_awqos ( axiA_awqos ), - .axiA_awregion ( axiA_awregion ), - .axiA_awvalid ( axiA_awvalid ), - .axiA_awready ( axiA_awready ), - .axiA_wdata ( axiA_wdata ), - .axiA_wstrb ( axiA_wstrb ), - .axiA_wvalid ( axiA_wvalid ), - .axiA_wlast ( axiA_wlast ), - .axiA_wready ( axiA_wready ), - .axiA_bresp ( axiA_bresp ), - .axiA_bvalid ( axiA_bvalid ), - .axiA_bready ( axiA_bready ), - .axiA_araddr ( axiA_araddr ), - .axiA_arlen ( axiA_arlen ), - .axiA_arsize ( axiA_arsize ), - .axiA_arburst ( axiA_arburst ), - .axiA_arlock ( axiA_arlock ), - .axiA_arcache ( axiA_arcache ), - .axiA_arprot ( axiA_arprot ), - .axiA_arqos ( axiA_arqos ), - .axiA_arregion ( axiA_arregion ), - .axiA_arvalid ( axiA_arvalid ), - .axiA_arready ( axiA_arready ), - .axiA_rdata ( axiA_rdata ), - .axiA_rresp ( axiA_rresp ), - .axiA_rlast ( axiA_rlast ), - .axiA_rvalid ( axiA_rvalid ), - .axiA_rready ( axiA_rready ), - .userInterruptA ( userInterruptA ), - .userInterruptB ( userInterruptB ), - .userInterruptC ( userInterruptC ), - .userInterruptD ( userInterruptD ), - .userInterruptE ( userInterruptE ), - .userInterruptF ( userInterruptF ), - .io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), - .io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), - .io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), - .io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), - .io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), - .io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), - .io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), - .io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), - .system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ), - .system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ), - .system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ), - .system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset ) -); -endmodule - -module `IP_MODULE_NAME(Axi4Peripheral_wrapper) #( -parameter PERI_FREQ=250 -)( -output system_i2c_0_io_sda_writeEnable, -output system_i2c_0_io_sda_write, -input system_i2c_0_io_sda_read, -output system_i2c_0_io_scl_writeEnable, -output system_i2c_0_io_scl_write, -input system_i2c_0_io_scl_read, -output userInterruptB, -input [3:0] system_gpio_0_io_read, -output [3:0] system_gpio_0_io_write, -output [3:0] system_gpio_0_io_writeEnable, -output userInterruptD, -output system_spi_0_io_sclk_write, -output system_spi_0_io_data_0_writeEnable, -input system_spi_0_io_data_0_read, -output system_spi_0_io_data_0_write, -output system_spi_0_io_data_1_writeEnable, -input system_spi_0_io_data_1_read, -output system_spi_0_io_data_1_write, -output system_spi_0_io_data_2_writeEnable, -input system_spi_0_io_data_2_read, -output system_spi_0_io_data_2_write, -output system_spi_0_io_data_3_writeEnable, -input system_spi_0_io_data_3_read, -output system_spi_0_io_data_3_write, -output [3:0] system_spi_0_io_ss, -output userInterruptE, -output userInterruptF, -output [15:0] io_apbSlave_0_PADDR, -output io_apbSlave_0_PSEL, -output io_apbSlave_0_PENABLE, -input io_apbSlave_0_PREADY, -output io_apbSlave_0_PWRITE, -output [31:0] io_apbSlave_0_PWDATA, -input [31:0] io_apbSlave_0_PRDATA, -input io_apbSlave_0_PSLVERROR, -output jtagCtrl_tdi, -input jtagCtrl_tdo, -output jtagCtrl_enable, -output jtagCtrl_capture, -output jtagCtrl_shift, -output jtagCtrl_update, -output jtagCtrl_reset, -input ut_jtagCtrl_tdi, -output ut_jtagCtrl_tdo, -input ut_jtagCtrl_enable, -input ut_jtagCtrl_capture, -input ut_jtagCtrl_shift, -input ut_jtagCtrl_update, -input ut_jtagCtrl_reset, -output system_uart_0_io_txd, -input system_uart_0_io_rxd, -output userInterruptA, -output userInterruptC, -output system_watchdog_hardPanic_reset, -input [31:0] axiA_awaddr, -input [7:0] axiA_awlen, -input [2:0] axiA_awsize, -input [1:0] axiA_awburst, -input axiA_awlock, -input [3:0] axiA_awcache, -input [2:0] axiA_awprot, -input [3:0] axiA_awqos, -input [3:0] axiA_awregion, -input axiA_awvalid, -output axiA_awready, -input [31:0] axiA_wdata, -input [3:0] axiA_wstrb, -input axiA_wvalid, -input axiA_wlast, -output axiA_wready, -output [1:0] axiA_bresp, -output axiA_bvalid, -input axiA_bready, -input [31:0] axiA_araddr, -input [7:0] axiA_arlen, -input [2:0] axiA_arsize, -input [1:0] axiA_arburst, -input axiA_arlock, -input [3:0] axiA_arcache, -input [2:0] axiA_arprot, -input [3:0] axiA_arqos, -input [3:0] axiA_arregion, -input axiA_arvalid, -output axiA_arready, -output [31:0] axiA_rdata, -output [1:0] axiA_rresp, -output axiA_rlast, -output axiA_rvalid, -input axiA_rready, -output axiAInterrupt, -input cfg_done, -output cfg_start, -output cfg_sel, -output cfg_reset, -input io_peripheralClk, -input io_peripheralReset, -output io_asyncReset, -input io_gpio_sw_n, -input pll_peripheral_locked, -input pll_system_locked -); - -wire flag_ok; -wire system_watchdog_softPanic_interrupt; -wire system_i2c_0_io_interrupt; -wire system_gpio_0_io_interrupt_0; -wire system_gpio_0_io_interrupt_1; -wire system_uart_0_io_interrupt; -wire system_spi_0_io_interrupt; - - -`IP_MODULE_NAME(lppdr4_init) u_lppdr4_init ( -.io_peripheralClk (io_peripheralClk), -.io_peripheralReset (io_peripheralReset), -.io_gpio_sw_n (io_gpio_sw_n), -.flag_ok (flag_ok), -.cfg_done (cfg_done), -.cfg_start (cfg_start), -.cfg_sel (cfg_sel), -.cfg_reset (cfg_reset) -); - -assign io_asyncReset = ~(io_gpio_sw_n & - pll_peripheral_locked & - pll_system_locked & - flag_ok); - -assign userInterruptA = system_uart_0_io_interrupt; -assign userInterruptB = system_spi_0_io_interrupt; -assign userInterruptC = system_i2c_0_io_interrupt; -assign userInterruptD = system_gpio_0_io_interrupt_0; -assign userInterruptE = system_gpio_0_io_interrupt_1; -assign userInterruptF = system_watchdog_softPanic_interrupt; - -assign jtagCtrl_capture = ut_jtagCtrl_capture; -assign jtagCtrl_enable = ut_jtagCtrl_enable; -assign jtagCtrl_reset = ut_jtagCtrl_reset; -assign jtagCtrl_shift = ut_jtagCtrl_shift; -assign jtagCtrl_tdi = ut_jtagCtrl_tdi; -assign jtagCtrl_update = ut_jtagCtrl_update; -assign ut_jtagCtrl_tdo = jtagCtrl_tdo; - - -assign system_i2c_0_io_sda_writeEnable=!system_i2c_0_io_sda_write; -assign system_i2c_0_io_scl_writeEnable=!system_i2c_0_io_scl_write; - - -//axi4 bridge to various I/O -Axi4PeripheralTop_035069daf0ad4fb491e9c65d79bd2ddd u_Axi4PeripheralTop( -.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR), -.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL), -.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE), -.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY), -.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE), -.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA), -.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA), -.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR), -.system_uart_0_io_interrupt(system_uart_0_io_interrupt), -.system_uart_0_io_txd(system_uart_0_io_txd), -.system_uart_0_io_rxd(system_uart_0_io_rxd), -.system_spi_0_io_interrupt(system_spi_0_io_interrupt), -.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write), -.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable), -.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read), -.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write), -.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable), -.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read), -.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write), -.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable), -.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read), -.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write), -.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable), -.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read), -.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write), -.system_spi_0_io_ss(system_spi_0_io_ss), -.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset), -.system_watchdog_logic_panics_0(system_watchdog_softPanic_interrupt), -.system_gpio_0_io_interrupts_0(system_gpio_0_io_interrupt_0), -.system_gpio_0_io_interrupts_1(system_gpio_0_io_interrupt_1), -.system_gpio_0_io_read(system_gpio_0_io_read), -.system_gpio_0_io_write(system_gpio_0_io_write), -.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable), -.system_i2c_0_io_interrupt(system_i2c_0_io_interrupt), -.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write), -.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read), -.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write), -.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read), -.axi_awvalid(axiA_awvalid), -.axi_awready(axiA_awready), -.axi_awaddr(axiA_awaddr[23:0]), -.axi_awlen(axiA_awlen), -.axi_awsize(axiA_awsize), -.axi_awcache(axiA_awcache), -.axi_awprot(axiA_awprot), -.axi_wvalid(axiA_wvalid), -.axi_wready(axiA_wready), -.axi_wdata(axiA_wdata), -.axi_wstrb(axiA_wstrb), -.axi_wlast(axiA_wlast), -.axi_bvalid(axiA_bvalid), -.axi_bready(axiA_bready), -.axi_bresp(axiA_bresp), -.axi_arvalid(axiA_arvalid), -.axi_arready(axiA_arready), -.axi_araddr(axiA_araddr[23:0]), -.axi_arlen(axiA_arlen), -.axi_arsize(axiA_arsize), -.axi_arcache(axiA_arcache), -.axi_arprot(axiA_arprot), -.axi_rvalid(axiA_rvalid), -.axi_rready(axiA_rready), -.axi_rdata(axiA_rdata), -.axi_rresp(axiA_rresp), -.axi_rlast(axiA_rlast), -.clk(io_peripheralClk), -.reset(io_peripheralReset) -); -assign axiAInterrupt = 1'b0; - -endmodule - - -module `IP_MODULE_NAME(lppdr4_init) ( - input io_peripheralClk, - input io_peripheralReset, - input io_gpio_sw_n, - output reg flag_ok, - input cfg_done, - output cfg_start, - output cfg_sel, - output cfg_reset -); - -localparam [1:0] IDLE = 2'b00, - CFG_START = 2'b01, - CFG_DONE = 2'b11; - -reg [1:0] cfg_st, - cfg_next; -reg [7:0] cfg_count; -wire cfg_ok; -reg [1:0] buf_reset; -wire dmReset; - -always@(posedge io_peripheralClk) -begin - buf_reset[1] <= io_peripheralReset; - buf_reset[0] <= buf_reset[1]; -end - -assign dmReset = (~buf_reset[0] & buf_reset[1]); - -always@(posedge io_peripheralClk or negedge io_gpio_sw_n) -begin - if(!io_gpio_sw_n) - flag_ok <= 1'b0; - else - begin - if(cfg_st == CFG_DONE) - flag_ok <= 1'b1; - else - flag_ok <= flag_ok; - end -end - -always@(posedge io_peripheralClk or negedge io_gpio_sw_n) -begin - if(!io_gpio_sw_n || dmReset) - cfg_st <= IDLE; - else - cfg_st <= cfg_next; -end - -always@(*) -begin - cfg_next = cfg_st; - case(cfg_st) - IDLE: - begin - if(cfg_count == 'hff) - cfg_next = CFG_START; - else - cfg_next = IDLE; - end - CFG_START: - begin - if(cfg_done) - cfg_next = CFG_DONE; - else - cfg_next = CFG_START; - end - CFG_DONE: - cfg_next = CFG_DONE; - default: - cfg_next = IDLE; - endcase -end - -assign cfg_start = (cfg_st != IDLE); -assign cfg_ok = (cfg_st == CFG_DONE); -assign cfg_reset = (cfg_st == IDLE); -assign cfg_sel = 1'b0; - -always@(posedge io_peripheralClk) -begin - if(cfg_st == IDLE) - cfg_count <= cfg_count + 1'b1; - else - cfg_count <= 'h0; -end - -endmodule - - -// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 -// Component : Axi4PeripheralTop_035069daf0ad4fb491e9c65d79bd2ddd -// Git hash : 176b956330f07bda5e095857b387c403a78f8448 - -`timescale 1ns/1ps - -module Axi4PeripheralTop_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire axi_awvalid, - output wire axi_awready, - input wire [23:0] axi_awaddr, - input wire [7:0] axi_awlen, - input wire [2:0] axi_awsize, - input wire [3:0] axi_awcache, - input wire [2:0] axi_awprot, - input wire axi_wvalid, - output wire axi_wready, - input wire [31:0] axi_wdata, - input wire [3:0] axi_wstrb, - input wire axi_wlast, - output wire axi_bvalid, - input wire axi_bready, - output wire [1:0] axi_bresp, - input wire axi_arvalid, - output wire axi_arready, - input wire [23:0] axi_araddr, - input wire [7:0] axi_arlen, - input wire [2:0] axi_arsize, - input wire [3:0] axi_arcache, - input wire [2:0] axi_arprot, - output wire axi_rvalid, - input wire axi_rready, - output wire [31:0] axi_rdata, - output wire [1:0] axi_rresp, - output wire axi_rlast, - output wire system_uart_0_io_txd, - input wire system_uart_0_io_rxd, - output wire system_i2c_0_io_sda_write, - input wire system_i2c_0_io_sda_read, - output wire system_i2c_0_io_scl_write, - input wire system_i2c_0_io_scl_read, - input wire [3:0] system_gpio_0_io_read, - output wire [3:0] system_gpio_0_io_write, - output wire [3:0] system_gpio_0_io_writeEnable, - output wire [15:0] io_apbSlave_0_PADDR, - output wire [0:0] io_apbSlave_0_PSEL, - output wire io_apbSlave_0_PENABLE, - input wire io_apbSlave_0_PREADY, - output wire io_apbSlave_0_PWRITE, - output wire [31:0] io_apbSlave_0_PWDATA, - input wire [31:0] io_apbSlave_0_PRDATA, - input wire io_apbSlave_0_PSLVERROR, - output wire system_uart_0_io_interrupt, - output wire system_spi_0_io_interrupt, - output wire [0:0] system_spi_0_io_sclk_write, - output wire system_spi_0_io_data_0_writeEnable, - input wire [0:0] system_spi_0_io_data_0_read, - output wire [0:0] system_spi_0_io_data_0_write, - output wire system_spi_0_io_data_1_writeEnable, - input wire [0:0] system_spi_0_io_data_1_read, - output wire [0:0] system_spi_0_io_data_1_write, - output wire system_spi_0_io_data_2_writeEnable, - input wire [0:0] system_spi_0_io_data_2_read, - output wire [0:0] system_spi_0_io_data_2_write, - output wire system_spi_0_io_data_3_writeEnable, - input wire [0:0] system_spi_0_io_data_3_read, - output wire [0:0] system_spi_0_io_data_3_write, - output wire [3:0] system_spi_0_io_ss, - output wire system_i2c_0_io_interrupt, - output wire system_gpio_0_io_interrupts_0, - output wire system_gpio_0_io_interrupts_1, - output wire system_watchdog_logic_panics_0, - output wire system_watchdog_hardPanic_reset, - input wire clk, - input wire reset -); - - wire streamArbiter_io_inputs_0_ready; - wire streamArbiter_io_inputs_1_ready; - wire streamArbiter_io_output_valid; - wire [23:0] streamArbiter_io_output_payload_addr; - wire [7:0] streamArbiter_io_output_payload_len; - wire [2:0] streamArbiter_io_output_payload_size; - wire [3:0] streamArbiter_io_output_payload_cache; - wire [2:0] streamArbiter_io_output_payload_prot; - wire [0:0] streamArbiter_io_chosen; - wire [1:0] streamArbiter_io_chosenOH; - wire axiToBmb_io_axi_arw_ready; - wire axiToBmb_io_axi_w_ready; - wire axiToBmb_io_axi_b_valid; - wire [1:0] axiToBmb_io_axi_b_payload_resp; - wire axiToBmb_io_axi_r_valid; - wire [31:0] axiToBmb_io_axi_r_payload_data; - wire [1:0] axiToBmb_io_axi_r_payload_resp; - wire axiToBmb_io_axi_r_payload_last; - wire axiToBmb_io_bmb_cmd_valid; - wire axiToBmb_io_bmb_cmd_payload_last; - wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_source; - wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_opcode; - wire [23:0] axiToBmb_io_bmb_cmd_payload_fragment_address; - wire [9:0] axiToBmb_io_bmb_cmd_payload_fragment_length; - wire [31:0] axiToBmb_io_bmb_cmd_payload_fragment_data; - wire [3:0] axiToBmb_io_bmb_cmd_payload_fragment_mask; - wire axiToBmb_io_bmb_rsp_ready; - wire bmbHandle_decoder_io_input_cmd_ready; - wire bmbHandle_decoder_io_input_rsp_valid; - wire bmbHandle_decoder_io_input_rsp_payload_last; - wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_source; - wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] bmbHandle_decoder_io_input_rsp_payload_fragment_data; - wire bmbHandle_decoder_io_outputs_0_cmd_valid; - wire bmbHandle_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source; - wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [23:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [9:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask; - wire bmbHandle_decoder_io_outputs_0_rsp_ready; - wire bmbHandle_unburstify_io_input_cmd_ready; - wire bmbHandle_unburstify_io_input_rsp_valid; - wire bmbHandle_unburstify_io_input_rsp_payload_last; - wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_source; - wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode; - wire [31:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_data; - wire bmbHandle_unburstify_io_output_cmd_valid; - wire bmbHandle_unburstify_io_output_cmd_payload_last; - wire [0:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; - wire [23:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_address; - wire [1:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_length; - wire [31:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_data; - wire [3:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; - wire [2:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_context; - wire bmbHandle_unburstify_io_output_rsp_ready; - wire bmbPeripheral_bmb_decoder_io_input_cmd_ready; - wire bmbPeripheral_bmb_decoder_io_input_rsp_valid; - wire bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - wire [0:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - wire [2:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; - wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; - wire system_uart_0_io_logic_io_bus_cmd_ready; - wire system_uart_0_io_logic_io_bus_rsp_valid; - wire system_uart_0_io_logic_io_bus_rsp_payload_last; - wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - wire [2:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - wire system_uart_0_io_logic_io_uart_txd; - wire system_uart_0_io_logic_system_uart_0_io_interrupt_source; - wire system_spi_0_io_logic_io_ctrl_cmd_ready; - wire system_spi_0_io_logic_io_ctrl_rsp_valid; - wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; - wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - wire [2:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; - wire [3:0] system_spi_0_io_logic_io_spi_ss; - wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; - wire system_spi_0_io_logic_io_spi_data_0_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; - wire system_spi_0_io_logic_io_spi_data_1_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; - wire system_spi_0_io_logic_io_spi_data_2_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; - wire system_spi_0_io_logic_io_spi_data_3_writeEnable; - wire system_spi_0_io_logic_system_spi_0_io_interrupt_source; - wire system_i2c_0_io_logic_io_ctrl_cmd_ready; - wire system_i2c_0_io_logic_io_ctrl_rsp_valid; - wire system_i2c_0_io_logic_io_ctrl_rsp_payload_last; - wire [0:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - wire [31:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; - wire [2:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; - wire system_i2c_0_io_logic_io_i2c_scl_write; - wire system_i2c_0_io_logic_io_i2c_sda_write; - wire system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; - wire [3:0] system_gpio_0_io_logic_io_gpio_write; - wire [3:0] system_gpio_0_io_logic_io_gpio_writeEnable; - wire system_gpio_0_io_logic_io_bus_cmd_ready; - wire system_gpio_0_io_logic_io_bus_rsp_valid; - wire system_gpio_0_io_logic_io_bus_rsp_payload_last; - wire [0:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; - wire [2:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; - wire [3:0] system_gpio_0_io_logic_io_interrupt; - wire system_watchdog_logic_logic_io_bus_cmd_ready; - wire system_watchdog_logic_logic_io_bus_rsp_valid; - wire system_watchdog_logic_logic_io_bus_rsp_payload_last; - wire [0:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; - wire [2:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; - wire [1:0] system_watchdog_logic_logic_io_panics; - wire io_apbSlave_0_logic_io_input_cmd_ready; - wire io_apbSlave_0_logic_io_input_rsp_valid; - wire io_apbSlave_0_logic_io_input_rsp_payload_last; - wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - wire [2:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - wire [15:0] io_apbSlave_0_logic_io_output_PADDR; - wire [0:0] io_apbSlave_0_logic_io_output_PSEL; - wire io_apbSlave_0_logic_io_output_PENABLE; - wire io_apbSlave_0_logic_io_output_PWRITE; - wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; - wire _zz_axiShared_b_ready; - wire _zz_axiShared_r_ready; - wire axi_aw_halfPipe_valid; - wire axi_aw_halfPipe_ready; - wire [23:0] axi_aw_halfPipe_payload_addr; - wire [7:0] axi_aw_halfPipe_payload_len; - wire [2:0] axi_aw_halfPipe_payload_size; - wire [3:0] axi_aw_halfPipe_payload_cache; - wire [2:0] axi_aw_halfPipe_payload_prot; - reg axi_aw_rValid; - wire axi_aw_halfPipe_fire; - reg [23:0] axi_aw_rData_addr; - reg [7:0] axi_aw_rData_len; - reg [2:0] axi_aw_rData_size; - reg [3:0] axi_aw_rData_cache; - reg [2:0] axi_aw_rData_prot; - wire axi_w_halfPipe_valid; - wire axi_w_halfPipe_ready; - wire [31:0] axi_w_halfPipe_payload_data; - wire [3:0] axi_w_halfPipe_payload_strb; - wire axi_w_halfPipe_payload_last; - reg axi_w_rValid; - wire axi_w_halfPipe_fire; - reg [31:0] axi_w_rData_data; - reg [3:0] axi_w_rData_strb; - reg axi_w_rData_last; - wire _zz_axi_bvalid; - reg _zz_axi_bvalid_1; - reg [1:0] _zz_axi_bresp; - wire axi_ar_halfPipe_valid; - wire axi_ar_halfPipe_ready; - wire [23:0] axi_ar_halfPipe_payload_addr; - wire [7:0] axi_ar_halfPipe_payload_len; - wire [2:0] axi_ar_halfPipe_payload_size; - wire [3:0] axi_ar_halfPipe_payload_cache; - wire [2:0] axi_ar_halfPipe_payload_prot; - reg axi_ar_rValid; - wire axi_ar_halfPipe_fire; - reg [23:0] axi_ar_rData_addr; - reg [7:0] axi_ar_rData_len; - reg [2:0] axi_ar_rData_size; - reg [3:0] axi_ar_rData_cache; - reg [2:0] axi_ar_rData_prot; - wire _zz_axi_rvalid; - reg _zz_axi_rvalid_1; - reg [31:0] _zz_axi_rdata; - reg [1:0] _zz_axi_rresp; - reg _zz_axi_rlast; - wire axiShared_arw_valid; - wire axiShared_arw_ready; - wire [23:0] axiShared_arw_payload_addr; - wire [7:0] axiShared_arw_payload_len; - wire [2:0] axiShared_arw_payload_size; - wire [3:0] axiShared_arw_payload_cache; - wire [2:0] axiShared_arw_payload_prot; - wire axiShared_arw_payload_write; - wire axiShared_w_valid; - wire axiShared_w_ready; - wire [31:0] axiShared_w_payload_data; - wire [3:0] axiShared_w_payload_strb; - wire axiShared_w_payload_last; - wire axiShared_b_valid; - wire axiShared_b_ready; - wire [1:0] axiShared_b_payload_resp; - wire axiShared_r_valid; - wire axiShared_r_ready; - wire [31:0] axiShared_r_payload_data; - wire [1:0] axiShared_r_payload_resp; - wire axiShared_r_payload_last; - wire bmbPeripheral_bmb_cmd_valid; - wire bmbPeripheral_bmb_cmd_ready; - wire bmbPeripheral_bmb_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_rsp_valid; - wire bmbPeripheral_bmb_rsp_ready; - wire bmbPeripheral_bmb_rsp_payload_last; - wire [0:0] bmbPeripheral_bmb_rsp_payload_fragment_opcode; - wire [31:0] bmbPeripheral_bmb_rsp_payload_fragment_data; - wire [2:0] bmbPeripheral_bmb_rsp_payload_fragment_context; - wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_gpio_0_io_interrupts_0_source; - wire system_gpio_0_io_interrupts_1_source; - wire system_gpio_0_io_interrupts_2; - wire system_gpio_0_io_interrupts_3; - wire system_watchdog_logic_panics_0_source; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; - wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; - wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; - wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; - reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; - reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - reg [2:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; - wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; - wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; - wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; - reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; - reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; - wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; - wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; - wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; - wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; - wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; - reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; - reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [7:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [7:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire bmbPeripheral_bmb_withoutMask_cmd_valid; - wire bmbPeripheral_bmb_withoutMask_cmd_ready; - wire bmbPeripheral_bmb_withoutMask_cmd_payload_last; - wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; - wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - wire bmbPeripheral_bmb_withoutMask_rsp_valid; - wire bmbPeripheral_bmb_withoutMask_rsp_ready; - wire bmbPeripheral_bmb_withoutMask_rsp_payload_last; - wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; - wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; - wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; - wire bmbPeripheral_bmb_withoutMask_cmd_valid_1; - wire bmbPeripheral_bmb_withoutMask_cmd_ready_1; - wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; - wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - wire bmbPeripheral_bmb_withoutMask_rsp_valid_1; - wire bmbPeripheral_bmb_withoutMask_rsp_ready_1; - wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; - wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; - wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; - wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; - wire bmbPeripheral_bmb_withoutMask_cmd_valid_2; - wire bmbPeripheral_bmb_withoutMask_cmd_ready_2; - wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; - wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - wire bmbPeripheral_bmb_withoutMask_rsp_valid_2; - wire bmbPeripheral_bmb_withoutMask_rsp_ready_2; - wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; - wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; - wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; - wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; - wire bmbPeripheral_bmb_withoutMask_cmd_valid_3; - wire bmbPeripheral_bmb_withoutMask_cmd_ready_3; - wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; - wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - wire bmbPeripheral_bmb_withoutMask_rsp_valid_3; - wire bmbPeripheral_bmb_withoutMask_rsp_ready_3; - wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; - wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; - wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; - wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; - wire bmbPeripheral_bmb_withoutMask_cmd_valid_4; - wire bmbPeripheral_bmb_withoutMask_cmd_ready_4; - wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; - wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - wire bmbPeripheral_bmb_withoutMask_rsp_valid_4; - wire bmbPeripheral_bmb_withoutMask_rsp_ready_4; - wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; - wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; - wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; - wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; - wire bmbPeripheral_bmb_withoutMask_cmd_valid_5; - wire bmbPeripheral_bmb_withoutMask_cmd_ready_5; - wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; - wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; - wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5; - wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; - wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; - wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; - wire bmbPeripheral_bmb_withoutMask_rsp_valid_5; - wire bmbPeripheral_bmb_withoutMask_rsp_ready_5; - wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_5; - wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5; - wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5; - wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5; - - Axi4PeripheralStreamArbiter_035069daf0ad4fb491e9c65d79bd2ddd streamArbiter ( - .io_inputs_0_valid (axi_ar_halfPipe_valid ), //i - .io_inputs_0_ready (streamArbiter_io_inputs_0_ready ), //o - .io_inputs_0_payload_addr (axi_ar_halfPipe_payload_addr[23:0] ), //i - .io_inputs_0_payload_len (axi_ar_halfPipe_payload_len[7:0] ), //i - .io_inputs_0_payload_size (axi_ar_halfPipe_payload_size[2:0] ), //i - .io_inputs_0_payload_cache (axi_ar_halfPipe_payload_cache[3:0] ), //i - .io_inputs_0_payload_prot (axi_ar_halfPipe_payload_prot[2:0] ), //i - .io_inputs_1_valid (axi_aw_halfPipe_valid ), //i - .io_inputs_1_ready (streamArbiter_io_inputs_1_ready ), //o - .io_inputs_1_payload_addr (axi_aw_halfPipe_payload_addr[23:0] ), //i - .io_inputs_1_payload_len (axi_aw_halfPipe_payload_len[7:0] ), //i - .io_inputs_1_payload_size (axi_aw_halfPipe_payload_size[2:0] ), //i - .io_inputs_1_payload_cache (axi_aw_halfPipe_payload_cache[3:0] ), //i - .io_inputs_1_payload_prot (axi_aw_halfPipe_payload_prot[2:0] ), //i - .io_output_valid (streamArbiter_io_output_valid ), //o - .io_output_ready (axiShared_arw_ready ), //i - .io_output_payload_addr (streamArbiter_io_output_payload_addr[23:0]), //o - .io_output_payload_len (streamArbiter_io_output_payload_len[7:0] ), //o - .io_output_payload_size (streamArbiter_io_output_payload_size[2:0] ), //o - .io_output_payload_cache (streamArbiter_io_output_payload_cache[3:0]), //o - .io_output_payload_prot (streamArbiter_io_output_payload_prot[2:0] ), //o - .io_chosen (streamArbiter_io_chosen ), //o - .io_chosenOH (streamArbiter_io_chosenOH[1:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralAxi4SharedToBmb_035069daf0ad4fb491e9c65d79bd2ddd axiToBmb ( - .io_axi_arw_valid (axiShared_arw_valid ), //i - .io_axi_arw_ready (axiToBmb_io_axi_arw_ready ), //o - .io_axi_arw_payload_addr (axiShared_arw_payload_addr[23:0] ), //i - .io_axi_arw_payload_len (axiShared_arw_payload_len[7:0] ), //i - .io_axi_arw_payload_size (axiShared_arw_payload_size[2:0] ), //i - .io_axi_arw_payload_cache (axiShared_arw_payload_cache[3:0] ), //i - .io_axi_arw_payload_prot (axiShared_arw_payload_prot[2:0] ), //i - .io_axi_arw_payload_write (axiShared_arw_payload_write ), //i - .io_axi_w_valid (axiShared_w_valid ), //i - .io_axi_w_ready (axiToBmb_io_axi_w_ready ), //o - .io_axi_w_payload_data (axiShared_w_payload_data[31:0] ), //i - .io_axi_w_payload_strb (axiShared_w_payload_strb[3:0] ), //i - .io_axi_w_payload_last (axiShared_w_payload_last ), //i - .io_axi_b_valid (axiToBmb_io_axi_b_valid ), //o - .io_axi_b_ready (axiShared_b_ready ), //i - .io_axi_b_payload_resp (axiToBmb_io_axi_b_payload_resp[1:0] ), //o - .io_axi_r_valid (axiToBmb_io_axi_r_valid ), //o - .io_axi_r_ready (axiShared_r_ready ), //i - .io_axi_r_payload_data (axiToBmb_io_axi_r_payload_data[31:0] ), //o - .io_axi_r_payload_resp (axiToBmb_io_axi_r_payload_resp[1:0] ), //o - .io_axi_r_payload_last (axiToBmb_io_axi_r_payload_last ), //o - .io_bmb_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //o - .io_bmb_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //i - .io_bmb_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //o - .io_bmb_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //o - .io_bmb_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //o - .io_bmb_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //o - .io_bmb_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //o - .io_bmb_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //o - .io_bmb_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //o - .io_bmb_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //i - .io_bmb_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //o - .io_bmb_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //i - .io_bmb_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //i - .io_bmb_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //i - .io_bmb_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0]) //i - ); - Axi4PeripheralBmbDecoder_035069daf0ad4fb491e9c65d79bd2ddd bmbHandle_decoder ( - .io_input_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //i - .io_input_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //i - .io_input_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //i - .io_input_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //i - .io_input_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //o - .io_outputs_0_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o - .io_outputs_0_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //i - .io_outputs_0_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //i - .io_outputs_0_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbUnburstify_035069daf0ad4fb491e9c65d79bd2ddd bmbHandle_unburstify ( - .io_input_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //i - .io_input_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0] ), //i - .io_input_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //i - .io_input_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_input_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //o - .io_input_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //i - .io_input_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_output_cmd_valid (bmbHandle_unburstify_io_output_cmd_valid ), //o - .io_output_cmd_ready (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (bmbHandle_unburstify_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (bmbHandle_unburstify_io_output_cmd_payload_fragment_address[23:0] ), //o - .io_output_cmd_payload_fragment_length (bmbHandle_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (bmbHandle_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (bmbHandle_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (bmbHandle_unburstify_io_output_cmd_payload_fragment_context[2:0] ), //o - .io_output_rsp_valid (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (bmbHandle_unburstify_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[2:0]), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbDecoder_1_035069daf0ad4fb491e9c65d79bd2ddd bmbPeripheral_bmb_decoder ( - .io_input_cmd_valid (bmbPeripheral_bmb_cmd_valid ), //i - .io_input_cmd_ready (bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (bmbPeripheral_bmb_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (bmbPeripheral_bmb_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (bmbPeripheral_bmb_cmd_payload_fragment_address[23:0] ), //i - .io_input_cmd_payload_fragment_length (bmbPeripheral_bmb_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (bmbPeripheral_bmb_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (bmbPeripheral_bmb_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (bmbPeripheral_bmb_cmd_payload_fragment_context[2:0] ), //i - .io_input_rsp_valid (bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (bmbPeripheral_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[2:0] ), //o - .io_outputs_0_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o - .io_outputs_0_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[2:0] ), //o - .io_outputs_0_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid ), //i - .io_outputs_0_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[2:0] ), //i - .io_outputs_1_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i - .io_outputs_1_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o - .io_outputs_1_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[2:0] ), //o - .io_outputs_1_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i - .io_outputs_1_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i - .io_outputs_1_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i - .io_outputs_1_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[2:0] ), //i - .io_outputs_2_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o - .io_outputs_2_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i - .io_outputs_2_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o - .io_outputs_2_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o - .io_outputs_2_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o - .io_outputs_2_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_2_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_2_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_2_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[2:0] ), //o - .io_outputs_2_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i - .io_outputs_2_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o - .io_outputs_2_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i - .io_outputs_2_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i - .io_outputs_2_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i - .io_outputs_2_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[2:0] ), //i - .io_outputs_3_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o - .io_outputs_3_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i - .io_outputs_3_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o - .io_outputs_3_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o - .io_outputs_3_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o - .io_outputs_3_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_3_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_3_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_3_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[2:0] ), //o - .io_outputs_3_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i - .io_outputs_3_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o - .io_outputs_3_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i - .io_outputs_3_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i - .io_outputs_3_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i - .io_outputs_3_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[2:0] ), //i - .io_outputs_4_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o - .io_outputs_4_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i - .io_outputs_4_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o - .io_outputs_4_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o - .io_outputs_4_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o - .io_outputs_4_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_4_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_4_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_4_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[2:0] ), //o - .io_outputs_4_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i - .io_outputs_4_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o - .io_outputs_4_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i - .io_outputs_4_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i - .io_outputs_4_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i - .io_outputs_4_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[2:0] ), //i - .io_outputs_5_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid ), //o - .io_outputs_5_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_5 ), //i - .io_outputs_5_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last ), //o - .io_outputs_5_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode ), //o - .io_outputs_5_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address[23:0]), //o - .io_outputs_5_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_5_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_5_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_5_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context[2:0] ), //o - .io_outputs_5_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_5 ), //i - .io_outputs_5_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready ), //o - .io_outputs_5_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 ), //i - .io_outputs_5_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 ), //i - .io_outputs_5_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5[31:0] ), //i - .io_outputs_5_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5[2:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd system_uart_0_io_logic ( - .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i - .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i - .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i - .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o - .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o - .io_uart_rxd (system_uart_0_io_rxd ), //i - .system_uart_0_io_interrupt_source (system_uart_0_io_logic_system_uart_0_io_interrupt_source ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbSpiXdrMasterCtrl_035069daf0ad4fb491e9c65d79bd2ddd system_spi_0_io_logic ( - .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o - .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i - .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0] ), //i - .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o - .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o - .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o - .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o - .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o - .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i - .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i - .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i - .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i - .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o - .io_spi_ss (system_spi_0_io_logic_io_spi_ss[3:0] ), //o - .system_spi_0_io_interrupt_source (system_spi_0_io_logic_system_spi_0_io_interrupt_source ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbI2cCtrl_035069daf0ad4fb491e9c65d79bd2ddd system_i2c_0_io_logic ( - .io_ctrl_cmd_valid (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_ctrl_cmd_ready (system_i2c_0_io_logic_io_ctrl_cmd_ready ), //o - .io_ctrl_cmd_payload_last (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_ctrl_cmd_payload_fragment_opcode (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_ctrl_cmd_payload_fragment_address (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[7:0]), //i - .io_ctrl_cmd_payload_fragment_length (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_ctrl_cmd_payload_fragment_data (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_ctrl_cmd_payload_fragment_context (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i - .io_ctrl_rsp_valid (system_i2c_0_io_logic_io_ctrl_rsp_valid ), //o - .io_ctrl_rsp_ready (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_ctrl_rsp_payload_last (system_i2c_0_io_logic_io_ctrl_rsp_payload_last ), //o - .io_ctrl_rsp_payload_fragment_opcode (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o - .io_ctrl_rsp_payload_fragment_data (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o - .io_ctrl_rsp_payload_fragment_context (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o - .io_i2c_sda_write (system_i2c_0_io_logic_io_i2c_sda_write ), //o - .io_i2c_sda_read (system_i2c_0_io_sda_read ), //i - .io_i2c_scl_write (system_i2c_0_io_logic_io_i2c_scl_write ), //o - .io_i2c_scl_read (system_i2c_0_io_scl_read ), //i - .system_i2c_0_io_interrupt_source (system_i2c_0_io_logic_system_i2c_0_io_interrupt_source ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbGpio2_035069daf0ad4fb491e9c65d79bd2ddd system_gpio_0_io_logic ( - .io_gpio_read (system_gpio_0_io_read[3:0] ), //i - .io_gpio_write (system_gpio_0_io_logic_io_gpio_write[3:0] ), //o - .io_gpio_writeEnable (system_gpio_0_io_logic_io_gpio_writeEnable[3:0] ), //o - .io_bus_cmd_valid (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_bus_cmd_ready (system_gpio_0_io_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i - .io_bus_cmd_payload_fragment_length (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i - .io_bus_rsp_valid (system_gpio_0_io_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_bus_rsp_payload_last (system_gpio_0_io_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o - .io_interrupt (system_gpio_0_io_logic_io_interrupt[3:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbWatchdog_035069daf0ad4fb491e9c65d79bd2ddd system_watchdog_logic_logic ( - .io_bus_cmd_valid (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_bus_cmd_ready (system_watchdog_logic_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i - .io_bus_cmd_payload_fragment_length (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i - .io_bus_rsp_valid (system_watchdog_logic_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_bus_rsp_payload_last (system_watchdog_logic_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o - .io_panics (system_watchdog_logic_logic_io_panics[1:0] ), //o - .io_heartBeat (1'b0 ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralBmbToApb3Bridge_035069daf0ad4fb491e9c65d79bd2ddd io_apbSlave_0_logic ( - .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0] ), //i - .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[2:0] ), //o - .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o - .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o - .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o - .io_output_PREADY (io_apbSlave_0_PREADY ), //i - .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o - .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o - .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i - .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign axi_aw_halfPipe_fire = (axi_aw_halfPipe_valid && axi_aw_halfPipe_ready); - assign axi_awready = (! axi_aw_rValid); - assign axi_aw_halfPipe_valid = axi_aw_rValid; - assign axi_aw_halfPipe_payload_addr = axi_aw_rData_addr; - assign axi_aw_halfPipe_payload_len = axi_aw_rData_len; - assign axi_aw_halfPipe_payload_size = axi_aw_rData_size; - assign axi_aw_halfPipe_payload_cache = axi_aw_rData_cache; - assign axi_aw_halfPipe_payload_prot = axi_aw_rData_prot; - assign axi_aw_halfPipe_ready = streamArbiter_io_inputs_1_ready; - assign axi_w_halfPipe_fire = (axi_w_halfPipe_valid && axi_w_halfPipe_ready); - assign axi_wready = (! axi_w_rValid); - assign axi_w_halfPipe_valid = axi_w_rValid; - assign axi_w_halfPipe_payload_data = axi_w_rData_data; - assign axi_w_halfPipe_payload_strb = axi_w_rData_strb; - assign axi_w_halfPipe_payload_last = axi_w_rData_last; - assign axi_w_halfPipe_ready = axiShared_w_ready; - assign _zz_axiShared_b_ready = (! _zz_axi_bvalid_1); - assign _zz_axi_bvalid = _zz_axi_bvalid_1; - assign axi_bvalid = _zz_axi_bvalid; - assign axi_bresp = _zz_axi_bresp; - assign axi_ar_halfPipe_fire = (axi_ar_halfPipe_valid && axi_ar_halfPipe_ready); - assign axi_arready = (! axi_ar_rValid); - assign axi_ar_halfPipe_valid = axi_ar_rValid; - assign axi_ar_halfPipe_payload_addr = axi_ar_rData_addr; - assign axi_ar_halfPipe_payload_len = axi_ar_rData_len; - assign axi_ar_halfPipe_payload_size = axi_ar_rData_size; - assign axi_ar_halfPipe_payload_cache = axi_ar_rData_cache; - assign axi_ar_halfPipe_payload_prot = axi_ar_rData_prot; - assign axi_ar_halfPipe_ready = streamArbiter_io_inputs_0_ready; - assign _zz_axiShared_r_ready = (! _zz_axi_rvalid_1); - assign _zz_axi_rvalid = _zz_axi_rvalid_1; - assign axi_rvalid = _zz_axi_rvalid; - assign axi_rdata = _zz_axi_rdata; - assign axi_rresp = _zz_axi_rresp; - assign axi_rlast = _zz_axi_rlast; - assign axiShared_arw_valid = streamArbiter_io_output_valid; - assign axiShared_arw_payload_addr = streamArbiter_io_output_payload_addr; - assign axiShared_arw_payload_len = streamArbiter_io_output_payload_len; - assign axiShared_arw_payload_size = streamArbiter_io_output_payload_size; - assign axiShared_arw_payload_cache = streamArbiter_io_output_payload_cache; - assign axiShared_arw_payload_prot = streamArbiter_io_output_payload_prot; - assign axiShared_arw_payload_write = streamArbiter_io_chosenOH[1]; - assign axiShared_w_valid = axi_w_halfPipe_valid; - assign axiShared_w_payload_data = axi_w_halfPipe_payload_data; - assign axiShared_w_payload_strb = axi_w_halfPipe_payload_strb; - assign axiShared_w_payload_last = axi_w_halfPipe_payload_last; - assign axiShared_b_ready = _zz_axiShared_b_ready; - assign axiShared_r_ready = _zz_axiShared_r_ready; - assign axiShared_arw_ready = axiToBmb_io_axi_arw_ready; - assign axiShared_w_ready = axiToBmb_io_axi_w_ready; - assign axiShared_b_valid = axiToBmb_io_axi_b_valid; - assign axiShared_b_payload_resp = axiToBmb_io_axi_b_payload_resp; - assign axiShared_r_valid = axiToBmb_io_axi_r_valid; - assign axiShared_r_payload_data = axiToBmb_io_axi_r_payload_data; - assign axiShared_r_payload_last = axiToBmb_io_axi_r_payload_last; - assign axiShared_r_payload_resp = axiToBmb_io_axi_r_payload_resp; - assign bmbPeripheral_bmb_cmd_valid = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = bmbPeripheral_bmb_cmd_ready; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = bmbPeripheral_bmb_rsp_valid; - assign bmbPeripheral_bmb_rsp_ready = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign bmbPeripheral_bmb_cmd_payload_last = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = bmbPeripheral_bmb_rsp_payload_last; - assign bmbPeripheral_bmb_cmd_payload_fragment_opcode = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_cmd_payload_fragment_address = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_cmd_payload_fragment_length = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_cmd_payload_fragment_data = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_cmd_payload_fragment_mask = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign bmbPeripheral_bmb_cmd_payload_fragment_context = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = bmbPeripheral_bmb_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = bmbPeripheral_bmb_rsp_payload_fragment_context; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbHandle_unburstify_io_output_cmd_valid; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbHandle_unburstify_io_output_rsp_ready; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbHandle_unburstify_io_output_cmd_payload_last; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbHandle_unburstify_io_output_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbHandle_unburstify_io_output_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbHandle_unburstify_io_output_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; - assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbHandle_unburstify_io_output_cmd_payload_fragment_context; - assign bmbPeripheral_bmb_cmd_ready = bmbPeripheral_bmb_decoder_io_input_cmd_ready; - assign bmbPeripheral_bmb_rsp_valid = bmbPeripheral_bmb_decoder_io_input_rsp_valid; - assign bmbPeripheral_bmb_rsp_payload_last = bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - assign bmbPeripheral_bmb_rsp_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_rsp_payload_fragment_data = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_rsp_payload_fragment_context = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; - assign system_i2c_0_io_sda_write = system_i2c_0_io_logic_io_i2c_sda_write; - assign system_i2c_0_io_scl_write = system_i2c_0_io_logic_io_i2c_scl_write; - assign system_gpio_0_io_write = system_gpio_0_io_logic_io_gpio_write; - assign system_gpio_0_io_writeEnable = system_gpio_0_io_logic_io_gpio_writeEnable; - assign system_gpio_0_io_interrupts_0_source = system_gpio_0_io_logic_io_interrupt[0]; - assign system_gpio_0_io_interrupts_1_source = system_gpio_0_io_logic_io_interrupt[1]; - assign system_gpio_0_io_interrupts_2 = system_gpio_0_io_logic_io_interrupt[2]; - assign system_gpio_0_io_interrupts_3 = system_gpio_0_io_logic_io_interrupt[3]; - assign system_watchdog_logic_panics_0_source = system_watchdog_logic_logic_io_panics[0]; - assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; - assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; - assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; - assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; - assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; - assign _zz_io_bus_rsp_ready = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); - assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_uart_0_io_interrupt = system_uart_0_io_logic_system_uart_0_io_interrupt_source; - assign system_spi_0_io_interrupt = system_spi_0_io_logic_system_spi_0_io_interrupt_source; - assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; - assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; - assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; - assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; - assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; - assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; - assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; - assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; - assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; - assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_i2c_0_io_logic_io_ctrl_cmd_ready; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_i2c_0_io_logic_io_ctrl_rsp_valid; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_i2c_0_io_logic_io_ctrl_rsp_payload_last; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; - assign system_i2c_0_io_interrupt = system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_gpio_0_io_logic_io_bus_cmd_ready; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_gpio_0_io_logic_io_bus_rsp_valid; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_gpio_0_io_logic_io_bus_rsp_payload_last; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; - assign system_gpio_0_io_interrupts_0 = system_gpio_0_io_interrupts_0_source; - assign system_gpio_0_io_interrupts_1 = system_gpio_0_io_interrupts_1_source; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_watchdog_logic_logic_io_bus_cmd_ready; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_watchdog_logic_logic_io_bus_rsp_valid; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_watchdog_logic_logic_io_bus_rsp_payload_last; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; - assign system_watchdog_logic_panics_0 = system_watchdog_logic_panics_0_source; - assign system_watchdog_hardPanic_reset = system_watchdog_logic_logic_io_panics[1]; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - assign bmbPeripheral_bmb_withoutMask_cmd_valid = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - assign bmbPeripheral_bmb_withoutMask_rsp_ready = bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_last = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid; - assign bmbPeripheral_bmb_withoutMask_cmd_ready = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign bmbPeripheral_bmb_withoutMask_rsp_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[5:0]; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign bmbPeripheral_bmb_withoutMask_cmd_valid_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - assign bmbPeripheral_bmb_withoutMask_rsp_ready_1 = bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_1; - assign bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_1; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[11:0]; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign bmbPeripheral_bmb_withoutMask_cmd_valid_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - assign bmbPeripheral_bmb_withoutMask_rsp_ready_2 = bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_2; - assign bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_2; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[7:0]; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign bmbPeripheral_bmb_withoutMask_cmd_valid_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - assign bmbPeripheral_bmb_withoutMask_rsp_ready_3 = bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_3; - assign bmbPeripheral_bmb_withoutMask_cmd_ready_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign bmbPeripheral_bmb_withoutMask_rsp_valid_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_3; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[7:0]; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign bmbPeripheral_bmb_withoutMask_cmd_valid_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - assign bmbPeripheral_bmb_withoutMask_rsp_ready_4 = bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_4; - assign bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_4; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[7:0]; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign bmbPeripheral_bmb_withoutMask_cmd_valid_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; - assign bmbPeripheral_bmb_withoutMask_rsp_ready_5 = bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_5; - assign bmbPeripheral_bmb_withoutMask_cmd_ready_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign bmbPeripheral_bmb_withoutMask_rsp_valid_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_5; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5[15:0]; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(posedge clk) begin - if(reset) begin - axi_aw_rValid <= 1'b0; - axi_w_rValid <= 1'b0; - _zz_axi_bvalid_1 <= 1'b0; - axi_ar_rValid <= 1'b0; - _zz_axi_rvalid_1 <= 1'b0; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end else begin - if(axi_awvalid) begin - axi_aw_rValid <= 1'b1; - end - if(axi_aw_halfPipe_fire) begin - axi_aw_rValid <= 1'b0; - end - if(axi_wvalid) begin - axi_w_rValid <= 1'b1; - end - if(axi_w_halfPipe_fire) begin - axi_w_rValid <= 1'b0; - end - if(axiShared_b_valid) begin - _zz_axi_bvalid_1 <= 1'b1; - end - if((_zz_axi_bvalid && axi_bready)) begin - _zz_axi_bvalid_1 <= 1'b0; - end - if(axi_arvalid) begin - axi_ar_rValid <= 1'b1; - end - if(axi_ar_halfPipe_fire) begin - axi_ar_rValid <= 1'b0; - end - if(axiShared_r_valid) begin - _zz_axi_rvalid_1 <= 1'b1; - end - if((_zz_axi_rvalid && axi_rready)) begin - _zz_axi_rvalid_1 <= 1'b0; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_uart_0_io_logic_io_bus_rsp_valid) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; - end - if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(axi_awready) begin - axi_aw_rData_addr <= axi_awaddr; - axi_aw_rData_len <= axi_awlen; - axi_aw_rData_size <= axi_awsize; - axi_aw_rData_cache <= axi_awcache; - axi_aw_rData_prot <= axi_awprot; - end - if(axi_wready) begin - axi_w_rData_data <= axi_wdata; - axi_w_rData_strb <= axi_wstrb; - axi_w_rData_last <= axi_wlast; - end - if(_zz_axiShared_b_ready) begin - _zz_axi_bresp <= axiShared_b_payload_resp; - end - if(axi_arready) begin - axi_ar_rData_addr <= axi_araddr; - axi_ar_rData_len <= axi_arlen; - axi_ar_rData_size <= axi_arsize; - axi_ar_rData_cache <= axi_arcache; - axi_ar_rData_prot <= axi_arprot; - end - if(_zz_axiShared_r_ready) begin - _zz_axi_rdata <= axiShared_r_payload_data; - _zz_axi_rresp <= axiShared_r_payload_resp; - _zz_axi_rlast <= axiShared_r_payload_last; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - end - - -endmodule - -module Axi4PeripheralBmbToApb3Bridge_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [15:0] io_input_cmd_payload_fragment_address, - input wire [1:0] io_input_cmd_payload_fragment_length, - input wire [31:0] io_input_cmd_payload_fragment_data, - input wire [2:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [31:0] io_input_rsp_payload_fragment_data, - output wire [2:0] io_input_rsp_payload_fragment_context, - output wire [15:0] io_output_PADDR, - output wire [0:0] io_output_PSEL, - output wire io_output_PENABLE, - input wire io_output_PREADY, - output wire io_output_PWRITE, - output wire [31:0] io_output_PWDATA, - input wire [31:0] io_output_PRDATA, - input wire io_output_PSLVERROR, - input wire clk, - input wire reset -); - - wire bmbBuffer_cmd_valid; - reg bmbBuffer_cmd_ready; - wire bmbBuffer_cmd_payload_last; - wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; - wire [15:0] bmbBuffer_cmd_payload_fragment_address; - wire [1:0] bmbBuffer_cmd_payload_fragment_length; - wire [31:0] bmbBuffer_cmd_payload_fragment_data; - wire [2:0] bmbBuffer_cmd_payload_fragment_context; - reg bmbBuffer_rsp_valid; - reg bmbBuffer_rsp_ready; - wire bmbBuffer_rsp_payload_last; - reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_payload_fragment_data; - wire [2:0] bmbBuffer_rsp_payload_fragment_context; - wire io_input_rsp_isStall; - wire _zz_io_input_cmd_ready; - wire bmbBuffer_rsp_m2sPipe_valid; - wire bmbBuffer_rsp_m2sPipe_ready; - wire bmbBuffer_rsp_m2sPipe_payload_last; - wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; - wire [2:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; - reg bmbBuffer_rsp_rValid; - reg bmbBuffer_rsp_rData_last; - reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; - reg [31:0] bmbBuffer_rsp_rData_fragment_data; - reg [2:0] bmbBuffer_rsp_rData_fragment_context; - wire when_Stream_l375; - reg state; - wire when_BmbToApb3Bridge_l46; - - assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); - assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); - assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; - assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - always @(*) begin - bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; - if(when_Stream_l375) begin - bmbBuffer_rsp_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! bmbBuffer_rsp_m2sPipe_valid); - assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; - assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; - assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; - assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; - assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; - always @(*) begin - bmbBuffer_cmd_ready = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_cmd_ready = 1'b1; - end - end - end - - assign io_output_PSEL[0] = bmbBuffer_cmd_valid; - assign io_output_PENABLE = state; - assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); - assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; - assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; - always @(*) begin - bmbBuffer_rsp_valid = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_rsp_valid = 1'b1; - end - end - end - - assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; - assign when_BmbToApb3Bridge_l46 = (! state); - assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign bmbBuffer_rsp_payload_last = 1'b1; - always @(*) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b0; - if(io_output_PSLVERROR) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b1; - end - end - - always @(posedge clk) begin - if(reset) begin - bmbBuffer_rsp_rValid <= 1'b0; - state <= 1'b0; - end else begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; - end - if(when_BmbToApb3Bridge_l46) begin - state <= bmbBuffer_cmd_valid; - end else begin - if(io_output_PREADY) begin - state <= 1'b0; - end - end - end - end - - always @(posedge clk) begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; - bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; - bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; - bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; - end - end - - -endmodule - -module Axi4PeripheralBmbWatchdog_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_bus_cmd_valid, - output wire io_bus_cmd_ready, - input wire io_bus_cmd_payload_last, - input wire [0:0] io_bus_cmd_payload_fragment_opcode, - input wire [7:0] io_bus_cmd_payload_fragment_address, - input wire [1:0] io_bus_cmd_payload_fragment_length, - input wire [31:0] io_bus_cmd_payload_fragment_data, - input wire [2:0] io_bus_cmd_payload_fragment_context, - output wire io_bus_rsp_valid, - input wire io_bus_rsp_ready, - output wire io_bus_rsp_payload_last, - output wire [0:0] io_bus_rsp_payload_fragment_opcode, - output wire [31:0] io_bus_rsp_payload_fragment_data, - output wire [2:0] io_bus_rsp_payload_fragment_context, - output wire [1:0] io_panics, - input wire io_heartBeat, - input wire clk, - input wire reset -); - - wire wd_prescaler_io_clear; - wire wd_prescaler_io_overflow; - wire wd_counters_0_timer_io_full; - wire [15:0] wd_counters_0_timer_io_value; - wire wd_counters_1_timer_io_full; - wire [15:0] wd_counters_1_timer_io_value; - reg [1:0] wd_api_enables; - reg wd_api_heartbeat; - reg [1:0] wd_api_panics; - wire wd_counters_0_clear; - reg wd_counters_0_full; - wire wd_counters_1_clear; - reg wd_counters_1_full; - wire busCtrl_readErrorFlag; - wire busCtrl_writeErrorFlag; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - reg [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [2:0] busCtrl_rsp_payload_fragment_context; - wire _zz_busCtrl_rsp_ready; - reg _zz_busCtrl_rsp_ready_1; - wire _zz_io_bus_rsp_valid; - reg _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [2:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l375; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_bus_cmd_fire; - wire busCtrl_doWrite; - wire busCtrl_doRead; - wire when_BmbSlaveFactory_l33; - wire when_BmbSlaveFactory_l35; - reg driver_unlocked; - reg _zz_when_Watchdog_l42; - wire when_Watchdog_l42; - reg _zz_when_Watchdog_l43; - wire when_Watchdog_l43; - reg _zz_wd_api_heartbeat; - wire [1:0] _zz_when_Watchdog_l52; - reg _zz_when_Watchdog_l50; - wire when_Watchdog_l50; - wire when_Watchdog_l52; - wire when_Watchdog_l52_1; - reg _zz_when_Watchdog_l55; - wire when_Watchdog_l55; - wire when_Watchdog_l57; - wire when_Watchdog_l57_1; - reg [23:0] _zz_io_limit; - reg [15:0] _zz_io_limit_1; - reg [15:0] _zz_io_limit_2; - - Axi4PeripheralPrescaler_035069daf0ad4fb491e9c65d79bd2ddd wd_prescaler ( - .io_clear (wd_prescaler_io_clear ), //i - .io_limit (_zz_io_limit[23:0] ), //i - .io_overflow (wd_prescaler_io_overflow), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd wd_counters_0_timer ( - .io_tick (wd_prescaler_io_overflow ), //i - .io_clear (wd_counters_0_clear ), //i - .io_limit (_zz_io_limit_1[15:0] ), //i - .io_full (wd_counters_0_timer_io_full ), //o - .io_value (wd_counters_0_timer_io_value[15:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd wd_counters_1_timer ( - .io_tick (wd_prescaler_io_overflow ), //i - .io_clear (wd_counters_1_clear ), //i - .io_limit (_zz_io_limit_2[15:0] ), //i - .io_full (wd_counters_1_timer_io_full ), //o - .io_value (wd_counters_1_timer_io_value[15:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - assign wd_prescaler_io_clear = (wd_api_heartbeat || (wd_api_enables == 2'b00)); - assign wd_counters_0_clear = ((! wd_api_enables[0]) || wd_api_heartbeat); - always @(*) begin - wd_api_panics[0] = wd_counters_0_full; - wd_api_panics[1] = wd_counters_1_full; - end - - assign wd_counters_1_clear = ((! wd_api_enables[1]) || wd_api_heartbeat); - assign busCtrl_readErrorFlag = 1'b0; - assign busCtrl_writeErrorFlag = 1'b0; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); - always @(*) begin - _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; - if(when_Stream_l375) begin - _zz_busCtrl_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); - assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - busCtrl_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 8'hc0 : begin - busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_0_timer_io_value; - end - 8'hc4 : begin - busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_1_timer_io_value; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - always @(*) begin - _zz_when_Watchdog_l42 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 8'h0 : begin - if(busCtrl_doWrite) begin - _zz_when_Watchdog_l42 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_Watchdog_l42 = (_zz_when_Watchdog_l42 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b925)); - always @(*) begin - _zz_when_Watchdog_l43 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 8'h0 : begin - if(busCtrl_doWrite) begin - _zz_when_Watchdog_l43 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_Watchdog_l43 = (_zz_when_Watchdog_l43 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b924)); - always @(*) begin - _zz_wd_api_heartbeat = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 8'h0 : begin - if(busCtrl_doWrite) begin - _zz_wd_api_heartbeat = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - wd_api_heartbeat = (_zz_wd_api_heartbeat && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'had68e70d)); - if(io_heartBeat) begin - wd_api_heartbeat = 1'b1; - end - end - - always @(*) begin - _zz_when_Watchdog_l50 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 8'h04 : begin - if(busCtrl_doWrite) begin - _zz_when_Watchdog_l50 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_Watchdog_l50 = (_zz_when_Watchdog_l50 && driver_unlocked); - assign when_Watchdog_l52 = _zz_when_Watchdog_l52[0]; - assign when_Watchdog_l52_1 = _zz_when_Watchdog_l52[1]; - always @(*) begin - _zz_when_Watchdog_l55 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 8'h08 : begin - if(busCtrl_doWrite) begin - _zz_when_Watchdog_l55 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_Watchdog_l55 = (_zz_when_Watchdog_l55 && driver_unlocked); - assign when_Watchdog_l57 = _zz_when_Watchdog_l52[0]; - assign when_Watchdog_l57_1 = _zz_when_Watchdog_l52[1]; - assign io_panics = wd_api_panics; - assign _zz_when_Watchdog_l52 = io_bus_cmd_payload_fragment_data[1 : 0]; - always @(posedge clk) begin - if(reset) begin - wd_counters_0_full <= 1'b0; - wd_counters_1_full <= 1'b0; - _zz_io_bus_rsp_valid_1 <= 1'b0; - driver_unlocked <= 1'b1; - wd_api_enables <= 2'b00; - _zz_io_limit <= 24'h0; - _zz_io_limit_1 <= 16'h0; - _zz_io_limit_2 <= 16'h0; - end else begin - if(wd_counters_0_timer_io_full) begin - wd_counters_0_full <= 1'b1; - end - if(wd_counters_0_clear) begin - wd_counters_0_full <= 1'b0; - end - if(wd_counters_1_timer_io_full) begin - wd_counters_1_full <= 1'b1; - end - if(wd_counters_1_clear) begin - wd_counters_1_full <= 1'b0; - end - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); - end - if(when_Watchdog_l42) begin - driver_unlocked <= 1'b1; - end - if(when_Watchdog_l43) begin - driver_unlocked <= 1'b0; - end - if(when_Watchdog_l50) begin - if(when_Watchdog_l52) begin - wd_api_enables[0] <= 1'b1; - end - if(when_Watchdog_l52_1) begin - wd_api_enables[1] <= 1'b1; - end - end - if(when_Watchdog_l55) begin - if(when_Watchdog_l57) begin - wd_api_enables[0] <= 1'b0; - end - if(when_Watchdog_l57_1) begin - wd_api_enables[1] <= 1'b0; - end - end - case(io_bus_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - if(driver_unlocked) begin - _zz_io_limit <= io_bus_cmd_payload_fragment_data[23 : 0]; - end - end - end - 8'h80 : begin - if(busCtrl_doWrite) begin - if(driver_unlocked) begin - _zz_io_limit_1 <= io_bus_cmd_payload_fragment_data[15 : 0]; - end - end - end - 8'h84 : begin - if(busCtrl_doWrite) begin - if(driver_unlocked) begin - _zz_io_limit_2 <= io_bus_cmd_payload_fragment_data[15 : 0]; - end - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - end - - -endmodule - -module Axi4PeripheralBmbGpio2_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire [3:0] io_gpio_read, - output reg [3:0] io_gpio_write, - output reg [3:0] io_gpio_writeEnable, - input wire io_bus_cmd_valid, - output wire io_bus_cmd_ready, - input wire io_bus_cmd_payload_last, - input wire [0:0] io_bus_cmd_payload_fragment_opcode, - input wire [7:0] io_bus_cmd_payload_fragment_address, - input wire [1:0] io_bus_cmd_payload_fragment_length, - input wire [31:0] io_bus_cmd_payload_fragment_data, - input wire [2:0] io_bus_cmd_payload_fragment_context, - output wire io_bus_rsp_valid, - input wire io_bus_rsp_ready, - output wire io_bus_rsp_payload_last, - output wire [0:0] io_bus_rsp_payload_fragment_opcode, - output wire [31:0] io_bus_rsp_payload_fragment_data, - output wire [2:0] io_bus_rsp_payload_fragment_context, - output reg [3:0] io_interrupt, - input wire clk, - input wire reset -); - - wire mapper_readErrorFlag; - wire mapper_writeErrorFlag; - wire mapper_readHaltTrigger; - wire mapper_writeHaltTrigger; - wire mapper_rsp_valid; - wire mapper_rsp_ready; - wire mapper_rsp_payload_last; - reg [0:0] mapper_rsp_payload_fragment_opcode; - reg [31:0] mapper_rsp_payload_fragment_data; - wire [2:0] mapper_rsp_payload_fragment_context; - wire _zz_mapper_rsp_ready; - reg _zz_mapper_rsp_ready_1; - wire _zz_io_bus_rsp_valid; - reg _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [2:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l375; - wire mapper_askWrite; - wire mapper_askRead; - wire io_bus_cmd_fire; - wire mapper_doWrite; - wire mapper_doRead; - wire when_BmbSlaveFactory_l33; - wire when_BmbSlaveFactory_l35; - reg [3:0] io_gpio_read_delay_1; - reg [3:0] syncronized; - reg [3:0] last; - reg _zz_io_gpio_write; - reg _zz_io_gpio_writeEnable; - reg _zz_io_gpio_write_1; - reg _zz_io_gpio_writeEnable_1; - reg _zz_io_gpio_write_2; - reg _zz_io_gpio_writeEnable_2; - reg _zz_io_gpio_write_3; - reg _zz_io_gpio_writeEnable_3; - reg [3:0] interrupt_enable_high; - reg [3:0] interrupt_enable_low; - reg [3:0] interrupt_enable_rise; - reg [3:0] interrupt_enable_fall; - wire [3:0] interrupt_valid; - reg _zz_mapper_rsp_payload_fragment_data; - reg _zz_mapper_rsp_payload_fragment_data_1; - reg _zz_mapper_rsp_payload_fragment_data_2; - reg _zz_mapper_rsp_payload_fragment_data_3; - reg _zz_mapper_rsp_payload_fragment_data_4; - reg _zz_mapper_rsp_payload_fragment_data_5; - reg _zz_mapper_rsp_payload_fragment_data_6; - reg _zz_mapper_rsp_payload_fragment_data_7; - - assign mapper_readErrorFlag = 1'b0; - assign mapper_writeErrorFlag = 1'b0; - assign mapper_readHaltTrigger = 1'b0; - assign mapper_writeHaltTrigger = 1'b0; - assign _zz_mapper_rsp_ready = (! (mapper_readHaltTrigger || mapper_writeHaltTrigger)); - assign mapper_rsp_ready = (_zz_mapper_rsp_ready_1 && _zz_mapper_rsp_ready); - always @(*) begin - _zz_mapper_rsp_ready_1 = io_bus_rsp_ready; - if(when_Stream_l375) begin - _zz_mapper_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); - assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign mapper_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign mapper_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign mapper_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign mapper_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign mapper_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = mapper_rsp_ready; - assign mapper_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (mapper_doWrite && mapper_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - mapper_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - mapper_rsp_payload_fragment_opcode = 1'b1; - end else begin - mapper_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (mapper_doRead && mapper_readErrorFlag); - always @(*) begin - mapper_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 8'h0 : begin - mapper_rsp_payload_fragment_data[0 : 0] = syncronized[0]; - mapper_rsp_payload_fragment_data[1 : 1] = syncronized[1]; - mapper_rsp_payload_fragment_data[2 : 2] = syncronized[2]; - mapper_rsp_payload_fragment_data[3 : 3] = syncronized[3]; - end - 8'h04 : begin - mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_write; - mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_write_1; - mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_write_2; - mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_write_3; - end - 8'h08 : begin - mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_writeEnable; - mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_writeEnable_1; - mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_writeEnable_2; - mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_writeEnable_3; - end - 8'h20 : begin - mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data; - mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_4; - end - 8'h24 : begin - mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_1; - mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_5; - end - 8'h28 : begin - mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_2; - mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_6; - end - 8'h2c : begin - mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_3; - mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_7; - end - default : begin - end - endcase - end - - assign mapper_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - always @(*) begin - io_gpio_write[0] = _zz_io_gpio_write; - io_gpio_write[1] = _zz_io_gpio_write_1; - io_gpio_write[2] = _zz_io_gpio_write_2; - io_gpio_write[3] = _zz_io_gpio_write_3; - end - - always @(*) begin - io_gpio_writeEnable[0] = _zz_io_gpio_writeEnable; - io_gpio_writeEnable[1] = _zz_io_gpio_writeEnable_1; - io_gpio_writeEnable[2] = _zz_io_gpio_writeEnable_2; - io_gpio_writeEnable[3] = _zz_io_gpio_writeEnable_3; - end - - assign interrupt_valid = ((((interrupt_enable_high & syncronized) | (interrupt_enable_low & (~ syncronized))) | (interrupt_enable_rise & (syncronized & (~ last)))) | (interrupt_enable_fall & ((~ syncronized) & last))); - always @(*) begin - io_interrupt[0] = interrupt_valid[0]; - io_interrupt[1] = interrupt_valid[1]; - io_interrupt[2] = 1'b0; - io_interrupt[3] = 1'b0; - end - - always @(*) begin - interrupt_enable_rise[0] = _zz_mapper_rsp_payload_fragment_data; - interrupt_enable_rise[1] = _zz_mapper_rsp_payload_fragment_data_4; - interrupt_enable_rise[2] = 1'b0; - interrupt_enable_rise[3] = 1'b0; - end - - always @(*) begin - interrupt_enable_fall[0] = _zz_mapper_rsp_payload_fragment_data_1; - interrupt_enable_fall[1] = _zz_mapper_rsp_payload_fragment_data_5; - interrupt_enable_fall[2] = 1'b0; - interrupt_enable_fall[3] = 1'b0; - end - - always @(*) begin - interrupt_enable_high[0] = _zz_mapper_rsp_payload_fragment_data_2; - interrupt_enable_high[1] = _zz_mapper_rsp_payload_fragment_data_6; - interrupt_enable_high[2] = 1'b0; - interrupt_enable_high[3] = 1'b0; - end - - always @(*) begin - interrupt_enable_low[0] = _zz_mapper_rsp_payload_fragment_data_3; - interrupt_enable_low[1] = _zz_mapper_rsp_payload_fragment_data_7; - interrupt_enable_low[2] = 1'b0; - interrupt_enable_low[3] = 1'b0; - end - - always @(posedge clk) begin - if(reset) begin - _zz_io_bus_rsp_valid_1 <= 1'b0; - _zz_io_gpio_writeEnable <= 1'b0; - _zz_io_gpio_writeEnable_1 <= 1'b0; - _zz_io_gpio_writeEnable_2 <= 1'b0; - _zz_io_gpio_writeEnable_3 <= 1'b0; - _zz_mapper_rsp_payload_fragment_data <= 1'b0; - _zz_mapper_rsp_payload_fragment_data_1 <= 1'b0; - _zz_mapper_rsp_payload_fragment_data_2 <= 1'b0; - _zz_mapper_rsp_payload_fragment_data_3 <= 1'b0; - _zz_mapper_rsp_payload_fragment_data_4 <= 1'b0; - _zz_mapper_rsp_payload_fragment_data_5 <= 1'b0; - _zz_mapper_rsp_payload_fragment_data_6 <= 1'b0; - _zz_mapper_rsp_payload_fragment_data_7 <= 1'b0; - end else begin - if(_zz_mapper_rsp_ready_1) begin - _zz_io_bus_rsp_valid_1 <= (mapper_rsp_valid && _zz_mapper_rsp_ready); - end - case(io_bus_cmd_payload_fragment_address) - 8'h08 : begin - if(mapper_doWrite) begin - _zz_io_gpio_writeEnable <= io_bus_cmd_payload_fragment_data[0]; - _zz_io_gpio_writeEnable_1 <= io_bus_cmd_payload_fragment_data[1]; - _zz_io_gpio_writeEnable_2 <= io_bus_cmd_payload_fragment_data[2]; - _zz_io_gpio_writeEnable_3 <= io_bus_cmd_payload_fragment_data[3]; - end - end - 8'h20 : begin - if(mapper_doWrite) begin - _zz_mapper_rsp_payload_fragment_data <= io_bus_cmd_payload_fragment_data[0]; - _zz_mapper_rsp_payload_fragment_data_4 <= io_bus_cmd_payload_fragment_data[1]; - end - end - 8'h24 : begin - if(mapper_doWrite) begin - _zz_mapper_rsp_payload_fragment_data_1 <= io_bus_cmd_payload_fragment_data[0]; - _zz_mapper_rsp_payload_fragment_data_5 <= io_bus_cmd_payload_fragment_data[1]; - end - end - 8'h28 : begin - if(mapper_doWrite) begin - _zz_mapper_rsp_payload_fragment_data_2 <= io_bus_cmd_payload_fragment_data[0]; - _zz_mapper_rsp_payload_fragment_data_6 <= io_bus_cmd_payload_fragment_data[1]; - end - end - 8'h2c : begin - if(mapper_doWrite) begin - _zz_mapper_rsp_payload_fragment_data_3 <= io_bus_cmd_payload_fragment_data[0]; - _zz_mapper_rsp_payload_fragment_data_7 <= io_bus_cmd_payload_fragment_data[1]; - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(_zz_mapper_rsp_ready_1) begin - _zz_io_bus_rsp_payload_last <= mapper_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= mapper_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= mapper_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= mapper_rsp_payload_fragment_context; - end - io_gpio_read_delay_1 <= io_gpio_read; - syncronized <= io_gpio_read_delay_1; - last <= syncronized; - case(io_bus_cmd_payload_fragment_address) - 8'h04 : begin - if(mapper_doWrite) begin - _zz_io_gpio_write <= io_bus_cmd_payload_fragment_data[0]; - _zz_io_gpio_write_1 <= io_bus_cmd_payload_fragment_data[1]; - _zz_io_gpio_write_2 <= io_bus_cmd_payload_fragment_data[2]; - _zz_io_gpio_write_3 <= io_bus_cmd_payload_fragment_data[3]; - end - end - default : begin - end - endcase - end - - -endmodule - -module Axi4PeripheralBmbI2cCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_ctrl_cmd_valid, - output wire io_ctrl_cmd_ready, - input wire io_ctrl_cmd_payload_last, - input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, - input wire [7:0] io_ctrl_cmd_payload_fragment_address, - input wire [1:0] io_ctrl_cmd_payload_fragment_length, - input wire [31:0] io_ctrl_cmd_payload_fragment_data, - input wire [2:0] io_ctrl_cmd_payload_fragment_context, - output wire io_ctrl_rsp_valid, - input wire io_ctrl_rsp_ready, - output wire io_ctrl_rsp_payload_last, - output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, - output wire [31:0] io_ctrl_rsp_payload_fragment_data, - output wire [2:0] io_ctrl_rsp_payload_fragment_context, - output wire io_i2c_sda_write, - input wire io_i2c_sda_read, - output wire io_i2c_scl_write, - input wire io_i2c_scl_read, - output wire system_i2c_0_io_interrupt_source, - input wire clk, - input wire reset -); - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT = 4'd0; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE = 4'd1; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 = 4'd2; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 = 4'd3; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 = 4'd4; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW = 4'd5; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH = 4'd6; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART = 4'd7; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 = 4'd8; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 = 4'd9; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 = 4'd10; - localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF = 4'd11; - localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; - localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; - localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; - localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; - localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; - localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; - localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; - - reg i2cCtrl_io_config_timeoutClear; - reg i2cCtrl_io_bus_rsp_valid; - reg i2cCtrl_io_bus_rsp_enable; - reg i2cCtrl_io_bus_rsp_data; - wire i2cCtrl_io_i2c_scl_write; - wire i2cCtrl_io_i2c_sda_write; - wire [2:0] i2cCtrl_io_bus_cmd_kind; - wire i2cCtrl_io_bus_cmd_data; - wire i2cCtrl_io_timeout; - wire i2cCtrl_io_internals_inFrame; - wire i2cCtrl_io_internals_sdaRead; - wire i2cCtrl_io_internals_sclRead; - wire [6:0] _zz_bridge_addressFilter_hits_0; - wire [6:0] _zz_bridge_addressFilter_hits_1; - wire [0:0] _zz_bridge_masterLogic_start; - wire [0:0] _zz_bridge_masterLogic_stop; - wire [0:0] _zz_bridge_masterLogic_drop; - wire [0:0] _zz_bridge_masterLogic_recover; - wire [11:0] _zz_bridge_masterLogic_timer_value; - wire [0:0] _zz_bridge_masterLogic_timer_value_1; - wire [0:0] _zz_bridge_masterLogic_fsm_dropped_start; - wire [0:0] _zz_bridge_masterLogic_fsm_dropped_stop; - wire [0:0] _zz_bridge_masterLogic_fsm_dropped_recover; - wire [2:0] _zz_io_bus_rsp_data; - wire [2:0] _zz_bridge_rxData_value; - wire [0:0] _zz_bridge_interruptCtrl_start_flag; - wire [0:0] _zz_bridge_interruptCtrl_restart_flag; - wire [0:0] _zz_bridge_interruptCtrl_end_flag; - wire [0:0] _zz_bridge_interruptCtrl_drop_flag; - wire [0:0] _zz_bridge_interruptCtrl_filterGen_flag; - wire [0:0] _zz_bridge_interruptCtrl_clockGenExit_flag; - wire [0:0] _zz_bridge_interruptCtrl_clockGenEnter_flag; - wire busCtrl_readErrorFlag; - wire busCtrl_writeErrorFlag; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - reg [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [2:0] busCtrl_rsp_payload_fragment_context; - wire _zz_busCtrl_rsp_ready; - reg _zz_busCtrl_rsp_ready_1; - wire _zz_io_ctrl_rsp_valid; - reg _zz_io_ctrl_rsp_valid_1; - reg _zz_io_ctrl_rsp_payload_last; - reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; - reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; - wire when_Stream_l375; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_ctrl_cmd_fire; - wire busCtrl_doWrite; - wire busCtrl_doRead; - wire when_BmbSlaveFactory_l33; - wire when_BmbSlaveFactory_l35; - wire bridge_busCtrlWithOffset_readErrorFlag; - wire bridge_busCtrlWithOffset_writeErrorFlag; - reg bridge_frameReset; - reg bridge_i2cBuffer_sda_write; - wire bridge_i2cBuffer_sda_read; - reg bridge_i2cBuffer_scl_write; - wire bridge_i2cBuffer_scl_read; - reg bridge_rxData_event; - reg bridge_rxData_listen; - reg bridge_rxData_valid; - reg [7:0] bridge_rxData_value; - reg when_I2cCtrl_l224; - reg bridge_rxAck_listen; - reg bridge_rxAck_valid; - reg bridge_rxAck_value; - reg when_I2cCtrl_l237; - reg bridge_txData_valid; - reg bridge_txData_repeat; - reg bridge_txData_enable; - reg [7:0] bridge_txData_value; - reg bridge_txData_forceDisable; - reg bridge_txData_disableOnDataConflict; - reg bridge_txAck_valid; - reg bridge_txAck_repeat; - reg bridge_txAck_enable; - reg bridge_txAck_value; - reg bridge_txAck_forceAck; - reg bridge_txAck_disableOnDataConflict; - reg bridge_addressFilter_addresses_0_enable; - reg [9:0] bridge_addressFilter_addresses_0_value; - reg bridge_addressFilter_addresses_0_is10Bit; - reg bridge_addressFilter_addresses_1_enable; - reg [9:0] bridge_addressFilter_addresses_1_value; - reg bridge_addressFilter_addresses_1_is10Bit; - reg [1:0] bridge_addressFilter_state; - reg [7:0] bridge_addressFilter_byte0; - reg [7:0] bridge_addressFilter_byte1; - wire bridge_addressFilter_byte0Is10Bit; - wire bridge_addressFilter_hits_0; - wire bridge_addressFilter_hits_1; - wire when_I2cCtrl_l306; - wire _zz_when_I2cCtrl_l310; - reg _zz_when_I2cCtrl_l310_1; - wire when_I2cCtrl_l310; - reg bridge_masterLogic_start; - reg when_BusSlaveFactory_l377; - wire when_BusSlaveFactory_l379; - reg bridge_masterLogic_stop; - reg when_BusSlaveFactory_l377_1; - wire when_BusSlaveFactory_l379_1; - reg bridge_masterLogic_drop; - reg when_BusSlaveFactory_l377_2; - wire when_BusSlaveFactory_l379_2; - reg bridge_masterLogic_recover; - reg when_BusSlaveFactory_l377_3; - wire when_BusSlaveFactory_l379_3; - reg [11:0] bridge_masterLogic_timer_value; - reg [11:0] bridge_masterLogic_timer_tLow; - reg [11:0] bridge_masterLogic_timer_tHigh; - reg [11:0] bridge_masterLogic_timer_tBuf; - wire bridge_masterLogic_timer_done; - wire bridge_masterLogic_txReady; - wire bridge_masterLogic_fsm_wantExit; - reg bridge_masterLogic_fsm_wantStart; - wire bridge_masterLogic_fsm_wantKill; - reg bridge_masterLogic_fsm_dropped_start; - reg bridge_masterLogic_fsm_dropped_stop; - reg bridge_masterLogic_fsm_dropped_recover; - reg bridge_masterLogic_fsm_dropped_trigger; - reg bridge_masterLogic_fsm_inFrameLate; - wire when_I2cCtrl_l363; - wire when_I2cCtrl_l363_1; - wire bridge_masterLogic_fsm_outOfSync; - wire bridge_masterLogic_fsm_isBusy; - reg when_BusSlaveFactory_l341; - wire when_BusSlaveFactory_l347; - reg when_BusSlaveFactory_l341_1; - wire when_BusSlaveFactory_l347_1; - reg when_BusSlaveFactory_l341_2; - wire when_BusSlaveFactory_l347_2; - reg [2:0] bridge_dataCounter; - reg bridge_inAckState; - reg bridge_wasntAck; - wire when_I2cCtrl_l523; - wire when_I2cCtrl_l546; - wire when_I2cCtrl_l566; - wire when_I2cCtrl_l570; - wire when_I2cCtrl_l574; - wire when_I2cCtrl_l578; - wire when_I2cCtrl_l588; - wire when_I2cCtrl_l601; - reg bridge_interruptCtrl_rxDataEnable; - reg bridge_interruptCtrl_rxAckEnable; - reg bridge_interruptCtrl_txDataEnable; - reg bridge_interruptCtrl_txAckEnable; - reg bridge_interruptCtrl_interrupt; - wire when_I2cCtrl_l634; - reg bridge_interruptCtrl_start_enable; - reg bridge_interruptCtrl_start_flag; - wire when_I2cCtrl_l634_1; - reg when_BusSlaveFactory_l341_3; - wire when_BusSlaveFactory_l347_3; - wire when_I2cCtrl_l634_2; - reg bridge_interruptCtrl_restart_enable; - reg bridge_interruptCtrl_restart_flag; - wire when_I2cCtrl_l634_3; - reg when_BusSlaveFactory_l341_4; - wire when_BusSlaveFactory_l347_4; - wire when_I2cCtrl_l634_4; - reg bridge_interruptCtrl_end_enable; - reg bridge_interruptCtrl_end_flag; - wire when_I2cCtrl_l634_5; - reg when_BusSlaveFactory_l341_5; - wire when_BusSlaveFactory_l347_5; - wire when_I2cCtrl_l634_6; - reg bridge_interruptCtrl_drop_enable; - reg bridge_interruptCtrl_drop_flag; - wire when_I2cCtrl_l634_7; - reg when_BusSlaveFactory_l341_6; - wire when_BusSlaveFactory_l347_6; - wire _zz_when_I2cCtrl_l634; - reg _zz_when_I2cCtrl_l634_1; - wire when_I2cCtrl_l634_8; - reg bridge_interruptCtrl_filterGen_enable; - reg bridge_interruptCtrl_filterGen_flag; - wire when_I2cCtrl_l634_9; - reg when_BusSlaveFactory_l341_7; - wire when_BusSlaveFactory_l347_7; - reg bridge_masterLogic_fsm_isBusy_regNext; - wire when_I2cCtrl_l634_10; - reg bridge_interruptCtrl_clockGenExit_enable; - reg bridge_interruptCtrl_clockGenExit_flag; - wire when_I2cCtrl_l634_11; - reg when_BusSlaveFactory_l341_8; - wire when_BusSlaveFactory_l347_8; - reg bridge_masterLogic_fsm_isBusy_regNext_1; - wire when_I2cCtrl_l634_12; - reg bridge_interruptCtrl_clockGenEnter_enable; - reg bridge_interruptCtrl_clockGenEnter_flag; - wire when_I2cCtrl_l634_13; - reg when_BusSlaveFactory_l341_9; - wire when_BusSlaveFactory_l347_9; - reg [9:0] _zz_io_config_samplingClockDivider; - reg [19:0] _zz_io_config_timeout; - reg [5:0] _zz_io_config_tsuData; - reg bridge_timeoutClear; - wire when_I2cCtrl_l659; - reg [3:0] bridge_masterLogic_fsm_stateReg; - reg [3:0] bridge_masterLogic_fsm_stateNext; - reg i2cCtrl_io_internals_inFrame_regNext; - wire when_I2cCtrl_l367; - wire when_I2cCtrl_l369; - wire when_I2cCtrl_l380; - wire when_I2cCtrl_l392; - wire when_I2cCtrl_l418; - wire when_I2cCtrl_l422; - wire when_I2cCtrl_l442; - wire when_I2cCtrl_l450; - wire when_I2cCtrl_l474; - wire when_StateMachine_l253; - wire when_StateMachine_l253_1; - wire when_StateMachine_l253_2; - wire when_StateMachine_l253_3; - wire when_StateMachine_l253_4; - wire when_StateMachine_l253_5; - wire when_I2cCtrl_l350; - reg bridge_slaveOverride_sda; - reg bridge_slaveOverride_scl; - wire when_I2cCtrl_l673; - wire when_I2cCtrl_l674; - reg bridge_i2cBuffer_scl_write_regNext; - reg bridge_i2cBuffer_sda_write_regNext; - `ifndef SYNTHESIS - reg [55:0] bridge_masterLogic_fsm_stateReg_string; - reg [55:0] bridge_masterLogic_fsm_stateNext_string; - `endif - - - assign _zz_bridge_addressFilter_hits_0 = (bridge_addressFilter_byte0 >>> 1'd1); - assign _zz_bridge_addressFilter_hits_1 = (bridge_addressFilter_byte0 >>> 1'd1); - assign _zz_bridge_masterLogic_start = 1'b1; - assign _zz_bridge_masterLogic_stop = 1'b1; - assign _zz_bridge_masterLogic_drop = 1'b1; - assign _zz_bridge_masterLogic_recover = 1'b1; - assign _zz_bridge_masterLogic_timer_value_1 = (! bridge_masterLogic_timer_done); - assign _zz_bridge_masterLogic_timer_value = {11'd0, _zz_bridge_masterLogic_timer_value_1}; - assign _zz_bridge_masterLogic_fsm_dropped_start = 1'b0; - assign _zz_bridge_masterLogic_fsm_dropped_stop = 1'b0; - assign _zz_bridge_masterLogic_fsm_dropped_recover = 1'b0; - assign _zz_io_bus_rsp_data = (3'b111 - bridge_dataCounter); - assign _zz_bridge_rxData_value = (3'b111 - bridge_dataCounter); - assign _zz_bridge_interruptCtrl_start_flag = 1'b0; - assign _zz_bridge_interruptCtrl_restart_flag = 1'b0; - assign _zz_bridge_interruptCtrl_end_flag = 1'b0; - assign _zz_bridge_interruptCtrl_drop_flag = 1'b0; - assign _zz_bridge_interruptCtrl_filterGen_flag = 1'b0; - assign _zz_bridge_interruptCtrl_clockGenExit_flag = 1'b0; - assign _zz_bridge_interruptCtrl_clockGenEnter_flag = 1'b0; - Axi4PeripheralI2cSlave_035069daf0ad4fb491e9c65d79bd2ddd i2cCtrl ( - .io_i2c_sda_write (i2cCtrl_io_i2c_sda_write ), //o - .io_i2c_sda_read (bridge_i2cBuffer_sda_read ), //i - .io_i2c_scl_write (i2cCtrl_io_i2c_scl_write ), //o - .io_i2c_scl_read (bridge_i2cBuffer_scl_read ), //i - .io_config_samplingClockDivider (_zz_io_config_samplingClockDivider[9:0]), //i - .io_config_timeout (_zz_io_config_timeout[19:0] ), //i - .io_config_tsuData (_zz_io_config_tsuData[5:0] ), //i - .io_config_timeoutClear (i2cCtrl_io_config_timeoutClear ), //i - .io_bus_cmd_kind (i2cCtrl_io_bus_cmd_kind[2:0] ), //o - .io_bus_cmd_data (i2cCtrl_io_bus_cmd_data ), //o - .io_bus_rsp_valid (i2cCtrl_io_bus_rsp_valid ), //i - .io_bus_rsp_enable (i2cCtrl_io_bus_rsp_enable ), //i - .io_bus_rsp_data (i2cCtrl_io_bus_rsp_data ), //i - .io_timeout (i2cCtrl_io_timeout ), //o - .io_internals_inFrame (i2cCtrl_io_internals_inFrame ), //o - .io_internals_sdaRead (i2cCtrl_io_internals_sdaRead ), //o - .io_internals_sclRead (i2cCtrl_io_internals_sclRead ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - initial begin - `ifndef SYNTHESIS - _zz_io_config_timeout = {$urandom}; - _zz_io_config_tsuData = {$urandom}; - `endif - end - - `ifndef SYNTHESIS - always @(*) begin - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateReg_string = "BOOT "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateReg_string = "IDLE "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateReg_string = "START1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateReg_string = "START2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateReg_string = "START3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateReg_string = "LOW "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateReg_string = "HIGH "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateReg_string = "RESTART"; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateReg_string = "STOP1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateReg_string = "STOP2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateReg_string = "STOP3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateReg_string = "TBUF "; - default : bridge_masterLogic_fsm_stateReg_string = "???????"; - endcase - end - always @(*) begin - case(bridge_masterLogic_fsm_stateNext) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateNext_string = "BOOT "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateNext_string = "IDLE "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateNext_string = "START1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateNext_string = "START2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateNext_string = "START3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateNext_string = "LOW "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateNext_string = "HIGH "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateNext_string = "RESTART"; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateNext_string = "STOP1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateNext_string = "STOP2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateNext_string = "STOP3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateNext_string = "TBUF "; - default : bridge_masterLogic_fsm_stateNext_string = "???????"; - endcase - end - `endif - - assign busCtrl_readErrorFlag = 1'b0; - assign busCtrl_writeErrorFlag = 1'b0; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); - always @(*) begin - _zz_busCtrl_rsp_ready_1 = io_ctrl_rsp_ready; - if(when_Stream_l375) begin - _zz_busCtrl_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); - assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign busCtrl_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - busCtrl_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h08 : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxData_valid; - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_rxData_value; - end - 8'h0c : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxAck_valid; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_rxAck_value; - end - 8'h0 : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txData_valid; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txData_enable; - end - 8'h04 : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txAck_valid; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txAck_enable; - end - 8'h80 : begin - busCtrl_rsp_payload_fragment_data[1 : 0] = {bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}; - end - 8'h84 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_addressFilter_byte0[0]; - end - 8'h40 : begin - busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_masterLogic_start; - busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_masterLogic_stop; - busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_masterLogic_drop; - busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_masterLogic_recover; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_masterLogic_fsm_isBusy; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_masterLogic_fsm_dropped_start; - busCtrl_rsp_payload_fragment_data[10 : 10] = bridge_masterLogic_fsm_dropped_stop; - busCtrl_rsp_payload_fragment_data[11 : 11] = bridge_masterLogic_fsm_dropped_recover; - end - 8'h20 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_rxDataEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_rxAckEnable; - busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_interruptCtrl_txDataEnable; - busCtrl_rsp_payload_fragment_data[3 : 3] = bridge_interruptCtrl_txAckEnable; - busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_enable; - busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_enable; - busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_enable; - busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_enable; - busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_enable; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_enable; - busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_enable; - end - 8'h24 : begin - busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_flag; - busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_flag; - busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_flag; - busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_flag; - busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_flag; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_flag; - busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_flag; - end - 8'h44 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = i2cCtrl_io_internals_inFrame; - busCtrl_rsp_payload_fragment_data[1 : 1] = i2cCtrl_io_internals_sdaRead; - busCtrl_rsp_payload_fragment_data[2 : 2] = i2cCtrl_io_internals_sclRead; - end - 8'h48 : begin - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_slaveOverride_sda; - busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_slaveOverride_scl; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - assign bridge_busCtrlWithOffset_readErrorFlag = 1'b0; - assign bridge_busCtrlWithOffset_writeErrorFlag = 1'b0; - always @(*) begin - bridge_frameReset = 1'b0; - case(i2cCtrl_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_START : begin - bridge_frameReset = 1'b1; - end - Axi4PeripheralI2cSlaveCmdMode_RESTART : begin - bridge_frameReset = 1'b1; - end - Axi4PeripheralI2cSlaveCmdMode_STOP : begin - bridge_frameReset = 1'b1; - end - Axi4PeripheralI2cSlaveCmdMode_DROP : begin - bridge_frameReset = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - bridge_i2cBuffer_sda_write = i2cCtrl_io_i2c_sda_write; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_I2cCtrl_l673) begin - bridge_i2cBuffer_sda_write = 1'b0; - end - end - - always @(*) begin - bridge_i2cBuffer_scl_write = i2cCtrl_io_i2c_scl_write; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - bridge_i2cBuffer_scl_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - if(bridge_masterLogic_timer_done) begin - if(when_I2cCtrl_l418) begin - bridge_i2cBuffer_scl_write = 1'b0; - end else begin - if(when_I2cCtrl_l422) begin - bridge_i2cBuffer_scl_write = 1'b0; - end - end - end else begin - bridge_i2cBuffer_scl_write = 1'b0; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - bridge_i2cBuffer_scl_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_I2cCtrl_l674) begin - bridge_i2cBuffer_scl_write = 1'b0; - end - end - - always @(*) begin - when_I2cCtrl_l224 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h08 : begin - if(busCtrl_doRead) begin - when_I2cCtrl_l224 = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - when_I2cCtrl_l237 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h0c : begin - if(busCtrl_doRead) begin - when_I2cCtrl_l237 = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - bridge_txData_forceDisable = 1'b0; - if(when_I2cCtrl_l601) begin - bridge_txData_forceDisable = 1'b0; - end - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - if(bridge_masterLogic_timer_done) begin - if(when_I2cCtrl_l418) begin - bridge_txData_forceDisable = 1'b1; - end else begin - if(when_I2cCtrl_l422) begin - bridge_txData_forceDisable = 1'b1; - end - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - end - - always @(*) begin - bridge_txAck_forceAck = 1'b0; - if(when_I2cCtrl_l306) begin - bridge_txAck_forceAck = 1'b1; - end - end - - assign bridge_addressFilter_byte0Is10Bit = (bridge_addressFilter_byte0[7 : 3] == 5'h1e); - assign bridge_addressFilter_hits_0 = (bridge_addressFilter_addresses_0_enable && ((! bridge_addressFilter_addresses_0_is10Bit) ? ((_zz_bridge_addressFilter_hits_0 == bridge_addressFilter_addresses_0_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_0_value) && (bridge_addressFilter_state == 2'b10)))); - assign bridge_addressFilter_hits_1 = (bridge_addressFilter_addresses_1_enable && ((! bridge_addressFilter_addresses_1_is10Bit) ? ((_zz_bridge_addressFilter_hits_1 == bridge_addressFilter_addresses_1_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_1_value) && (bridge_addressFilter_state == 2'b10)))); - assign when_I2cCtrl_l306 = ((bridge_addressFilter_byte0Is10Bit && (bridge_addressFilter_state == 2'b01)) && (|{((bridge_addressFilter_addresses_1_enable && bridge_addressFilter_addresses_1_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_1_value[9 : 8])),((bridge_addressFilter_addresses_0_enable && bridge_addressFilter_addresses_0_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_0_value[9 : 8]))})); - assign _zz_when_I2cCtrl_l310 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); - assign when_I2cCtrl_l310 = (_zz_when_I2cCtrl_l310 && (! _zz_when_I2cCtrl_l310_1)); - always @(*) begin - when_BusSlaveFactory_l377 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379 = io_ctrl_cmd_payload_fragment_data[4]; - always @(*) begin - when_BusSlaveFactory_l377_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_1 = io_ctrl_cmd_payload_fragment_data[5]; - always @(*) begin - when_BusSlaveFactory_l377_2 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_2 = io_ctrl_cmd_payload_fragment_data[6]; - always @(*) begin - when_BusSlaveFactory_l377_3 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_3 = io_ctrl_cmd_payload_fragment_data[7]; - assign bridge_masterLogic_timer_done = (bridge_masterLogic_timer_value == 12'h0); - assign bridge_masterLogic_fsm_wantExit = 1'b0; - always @(*) begin - bridge_masterLogic_fsm_wantStart = 1'b0; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - bridge_masterLogic_fsm_wantStart = 1'b1; - end - endcase - end - - assign bridge_masterLogic_fsm_wantKill = 1'b0; - always @(*) begin - bridge_masterLogic_fsm_dropped_trigger = 1'b0; - if(when_I2cCtrl_l350) begin - bridge_masterLogic_fsm_dropped_trigger = 1'b1; - end - end - - assign when_I2cCtrl_l363 = (! i2cCtrl_io_internals_sclRead); - assign when_I2cCtrl_l363_1 = (! i2cCtrl_io_internals_inFrame); - assign bridge_masterLogic_fsm_outOfSync = ((! i2cCtrl_io_internals_inFrame) && ((! i2cCtrl_io_internals_sdaRead) || (! i2cCtrl_io_internals_sclRead))); - assign bridge_masterLogic_fsm_isBusy = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && (! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF))); - always @(*) begin - when_BusSlaveFactory_l341 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347 = io_ctrl_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l341_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_1 = io_ctrl_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l341_2 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_2 = io_ctrl_cmd_payload_fragment_data[11]; - assign bridge_masterLogic_txReady = (bridge_inAckState ? bridge_txAck_valid : bridge_txData_valid); - assign when_I2cCtrl_l523 = (! bridge_inAckState); - always @(*) begin - if(when_I2cCtrl_l523) begin - i2cCtrl_io_bus_rsp_valid = ((bridge_txData_valid && (! (bridge_rxData_valid && bridge_rxData_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); - if(bridge_txData_forceDisable) begin - i2cCtrl_io_bus_rsp_valid = 1'b1; - end - end else begin - i2cCtrl_io_bus_rsp_valid = ((bridge_txAck_valid && (! (bridge_rxAck_valid && bridge_rxAck_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); - if(bridge_txAck_forceAck) begin - i2cCtrl_io_bus_rsp_valid = 1'b1; - end - end - if(when_I2cCtrl_l546) begin - i2cCtrl_io_bus_rsp_valid = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE); - end - end - - always @(*) begin - if(when_I2cCtrl_l523) begin - i2cCtrl_io_bus_rsp_enable = bridge_txData_enable; - if(bridge_txData_forceDisable) begin - i2cCtrl_io_bus_rsp_enable = 1'b0; - end - end else begin - i2cCtrl_io_bus_rsp_enable = bridge_txAck_enable; - if(bridge_txAck_forceAck) begin - i2cCtrl_io_bus_rsp_enable = 1'b1; - end - end - if(when_I2cCtrl_l546) begin - i2cCtrl_io_bus_rsp_enable = 1'b0; - end - end - - always @(*) begin - if(when_I2cCtrl_l523) begin - i2cCtrl_io_bus_rsp_data = bridge_txData_value[_zz_io_bus_rsp_data]; - end else begin - i2cCtrl_io_bus_rsp_data = bridge_txAck_value; - if(bridge_txAck_forceAck) begin - i2cCtrl_io_bus_rsp_data = 1'b0; - end - end - end - - assign when_I2cCtrl_l546 = (bridge_wasntAck && (! bridge_masterLogic_fsm_isBusy)); - assign when_I2cCtrl_l566 = (! bridge_inAckState); - assign when_I2cCtrl_l570 = (i2cCtrl_io_bus_rsp_data != i2cCtrl_io_bus_cmd_data); - assign when_I2cCtrl_l574 = (bridge_dataCounter == 3'b111); - assign when_I2cCtrl_l578 = (bridge_txData_valid && (! bridge_txData_repeat)); - assign when_I2cCtrl_l588 = (bridge_txAck_valid && (! bridge_txAck_repeat)); - assign when_I2cCtrl_l601 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP) || (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP)); - always @(*) begin - bridge_interruptCtrl_interrupt = ((((bridge_interruptCtrl_rxDataEnable && bridge_rxData_valid) || (bridge_interruptCtrl_rxAckEnable && bridge_rxAck_valid)) || (bridge_interruptCtrl_txDataEnable && (! bridge_txData_valid))) || (bridge_interruptCtrl_txAckEnable && (! bridge_txAck_valid))); - if(bridge_interruptCtrl_start_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_restart_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_end_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_drop_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_filterGen_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_clockGenExit_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_clockGenEnter_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - end - - assign when_I2cCtrl_l634 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_START); - assign when_I2cCtrl_l634_1 = (! bridge_interruptCtrl_start_enable); - always @(*) begin - when_BusSlaveFactory_l341_3 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_3 = io_ctrl_cmd_payload_fragment_data[4]; - assign when_I2cCtrl_l634_2 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_RESTART); - assign when_I2cCtrl_l634_3 = (! bridge_interruptCtrl_restart_enable); - always @(*) begin - when_BusSlaveFactory_l341_4 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_4 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_4 = io_ctrl_cmd_payload_fragment_data[5]; - assign when_I2cCtrl_l634_4 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP); - assign when_I2cCtrl_l634_5 = (! bridge_interruptCtrl_end_enable); - always @(*) begin - when_BusSlaveFactory_l341_5 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_5 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_5 = io_ctrl_cmd_payload_fragment_data[6]; - assign when_I2cCtrl_l634_6 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || bridge_masterLogic_fsm_dropped_trigger); - assign when_I2cCtrl_l634_7 = (! bridge_interruptCtrl_drop_enable); - always @(*) begin - when_BusSlaveFactory_l341_6 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_6 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_6 = io_ctrl_cmd_payload_fragment_data[7]; - assign _zz_when_I2cCtrl_l634 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); - assign when_I2cCtrl_l634_8 = (_zz_when_I2cCtrl_l634 && (! _zz_when_I2cCtrl_l634_1)); - assign when_I2cCtrl_l634_9 = (! bridge_interruptCtrl_filterGen_enable); - always @(*) begin - when_BusSlaveFactory_l341_7 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_7 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_7 = io_ctrl_cmd_payload_fragment_data[17]; - assign when_I2cCtrl_l634_10 = ((! bridge_masterLogic_fsm_isBusy) && bridge_masterLogic_fsm_isBusy_regNext); - assign when_I2cCtrl_l634_11 = (! bridge_interruptCtrl_clockGenExit_enable); - always @(*) begin - when_BusSlaveFactory_l341_8 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_8 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_8 = io_ctrl_cmd_payload_fragment_data[15]; - assign when_I2cCtrl_l634_12 = (bridge_masterLogic_fsm_isBusy && (! bridge_masterLogic_fsm_isBusy_regNext_1)); - assign when_I2cCtrl_l634_13 = (! bridge_interruptCtrl_clockGenEnter_enable); - always @(*) begin - when_BusSlaveFactory_l341_9 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_9 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_9 = io_ctrl_cmd_payload_fragment_data[16]; - always @(*) begin - i2cCtrl_io_config_timeoutClear = bridge_timeoutClear; - if(when_I2cCtrl_l659) begin - i2cCtrl_io_config_timeoutClear = 1'b1; - end - end - - assign when_I2cCtrl_l659 = ((! i2cCtrl_io_internals_inFrame) && (! bridge_masterLogic_fsm_isBusy)); - always @(*) begin - bridge_masterLogic_fsm_stateNext = bridge_masterLogic_fsm_stateReg; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - if(when_I2cCtrl_l367) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; - end else begin - if(when_I2cCtrl_l369) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; - end else begin - if(bridge_masterLogic_recover) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; - end - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - if(when_I2cCtrl_l380) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - if(when_I2cCtrl_l392) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - if(bridge_masterLogic_timer_done) begin - if(when_I2cCtrl_l418) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1; - end else begin - if(when_I2cCtrl_l422) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART; - end else begin - if(i2cCtrl_io_internals_sclRead) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH; - end - end - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - if(when_I2cCtrl_l442) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - if(!when_I2cCtrl_l450) begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - if(!when_I2cCtrl_l474) begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3; - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - if(i2cCtrl_io_internals_sdaRead) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; - end - end - default : begin - end - endcase - if(when_I2cCtrl_l350) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; - end - if(bridge_masterLogic_fsm_wantStart) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; - end - if(bridge_masterLogic_fsm_wantKill) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; - end - end - - assign when_I2cCtrl_l367 = ((! i2cCtrl_io_internals_inFrame) && i2cCtrl_io_internals_inFrame_regNext); - assign when_I2cCtrl_l369 = (bridge_masterLogic_start && (! bridge_masterLogic_fsm_inFrameLate)); - assign when_I2cCtrl_l380 = (! bridge_masterLogic_fsm_outOfSync); - assign when_I2cCtrl_l392 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); - assign when_I2cCtrl_l418 = ((bridge_masterLogic_stop && (! bridge_inAckState)) || (bridge_masterLogic_recover && i2cCtrl_io_internals_sdaRead)); - assign when_I2cCtrl_l422 = (bridge_masterLogic_start && (! bridge_inAckState)); - assign when_I2cCtrl_l442 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); - assign when_I2cCtrl_l450 = (! i2cCtrl_io_internals_sclRead); - assign when_I2cCtrl_l474 = (! i2cCtrl_io_internals_sclRead); - assign when_StateMachine_l253 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)); - assign when_StateMachine_l253_1 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)); - assign when_StateMachine_l253_2 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)); - assign when_StateMachine_l253_3 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)); - assign when_StateMachine_l253_4 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)); - assign when_StateMachine_l253_5 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)); - assign when_I2cCtrl_l350 = (bridge_masterLogic_drop || ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || i2cCtrl_io_timeout))); - assign when_I2cCtrl_l673 = (! bridge_slaveOverride_sda); - assign when_I2cCtrl_l674 = (! bridge_slaveOverride_scl); - assign io_i2c_scl_write = bridge_i2cBuffer_scl_write_regNext; - assign io_i2c_sda_write = bridge_i2cBuffer_sda_write_regNext; - assign bridge_i2cBuffer_scl_read = io_i2c_scl_read; - assign bridge_i2cBuffer_sda_read = io_i2c_sda_read; - assign system_i2c_0_io_interrupt_source = bridge_interruptCtrl_interrupt; - always @(posedge clk) begin - if(reset) begin - _zz_io_ctrl_rsp_valid_1 <= 1'b0; - bridge_rxData_event <= 1'b0; - bridge_rxData_listen <= 1'b0; - bridge_rxData_valid <= 1'b0; - bridge_rxAck_listen <= 1'b0; - bridge_rxAck_valid <= 1'b0; - bridge_txData_valid <= 1'b1; - bridge_txData_repeat <= 1'b1; - bridge_txData_enable <= 1'b0; - bridge_txAck_valid <= 1'b1; - bridge_txAck_repeat <= 1'b1; - bridge_txAck_enable <= 1'b0; - bridge_addressFilter_addresses_0_enable <= 1'b0; - bridge_addressFilter_addresses_1_enable <= 1'b0; - bridge_addressFilter_state <= 2'b00; - bridge_masterLogic_start <= 1'b0; - bridge_masterLogic_stop <= 1'b0; - bridge_masterLogic_drop <= 1'b0; - bridge_masterLogic_recover <= 1'b0; - bridge_masterLogic_fsm_dropped_start <= 1'b0; - bridge_masterLogic_fsm_dropped_stop <= 1'b0; - bridge_masterLogic_fsm_dropped_recover <= 1'b0; - bridge_dataCounter <= 3'b000; - bridge_inAckState <= 1'b0; - bridge_wasntAck <= 1'b0; - bridge_interruptCtrl_rxDataEnable <= 1'b0; - bridge_interruptCtrl_rxAckEnable <= 1'b0; - bridge_interruptCtrl_txDataEnable <= 1'b0; - bridge_interruptCtrl_txAckEnable <= 1'b0; - bridge_interruptCtrl_start_enable <= 1'b0; - bridge_interruptCtrl_start_flag <= 1'b0; - bridge_interruptCtrl_restart_enable <= 1'b0; - bridge_interruptCtrl_restart_flag <= 1'b0; - bridge_interruptCtrl_end_enable <= 1'b0; - bridge_interruptCtrl_end_flag <= 1'b0; - bridge_interruptCtrl_drop_enable <= 1'b0; - bridge_interruptCtrl_drop_flag <= 1'b0; - bridge_interruptCtrl_filterGen_enable <= 1'b0; - bridge_interruptCtrl_filterGen_flag <= 1'b0; - bridge_interruptCtrl_clockGenExit_enable <= 1'b0; - bridge_interruptCtrl_clockGenExit_flag <= 1'b0; - bridge_interruptCtrl_clockGenEnter_enable <= 1'b0; - bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; - _zz_io_config_samplingClockDivider <= 10'h0; - bridge_masterLogic_fsm_stateReg <= Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; - bridge_slaveOverride_sda <= 1'b1; - bridge_slaveOverride_scl <= 1'b1; - bridge_i2cBuffer_scl_write_regNext <= 1'b1; - bridge_i2cBuffer_sda_write_regNext <= 1'b1; - end else begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_ctrl_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); - end - bridge_rxData_event <= 1'b0; - if(when_I2cCtrl_l224) begin - bridge_rxData_valid <= 1'b0; - end - if(when_I2cCtrl_l237) begin - bridge_rxAck_valid <= 1'b0; - end - if(bridge_rxData_event) begin - case(bridge_addressFilter_state) - 2'b00 : begin - bridge_addressFilter_state <= 2'b01; - end - 2'b01 : begin - bridge_addressFilter_state <= 2'b10; - end - default : begin - end - endcase - end - if(bridge_frameReset) begin - bridge_addressFilter_state <= 2'b00; - end - if(when_I2cCtrl_l310) begin - bridge_txAck_valid <= 1'b0; - end - if(when_BusSlaveFactory_l377) begin - if(when_BusSlaveFactory_l379) begin - bridge_masterLogic_start <= _zz_bridge_masterLogic_start[0]; - end - end - if(when_BusSlaveFactory_l377_1) begin - if(when_BusSlaveFactory_l379_1) begin - bridge_masterLogic_stop <= _zz_bridge_masterLogic_stop[0]; - end - end - if(when_BusSlaveFactory_l377_2) begin - if(when_BusSlaveFactory_l379_2) begin - bridge_masterLogic_drop <= _zz_bridge_masterLogic_drop[0]; - end - end - if(when_BusSlaveFactory_l377_3) begin - if(when_BusSlaveFactory_l379_3) begin - bridge_masterLogic_recover <= _zz_bridge_masterLogic_recover[0]; - end - end - if(when_BusSlaveFactory_l341) begin - if(when_BusSlaveFactory_l347) begin - bridge_masterLogic_fsm_dropped_start <= _zz_bridge_masterLogic_fsm_dropped_start[0]; - end - end - if(when_BusSlaveFactory_l341_1) begin - if(when_BusSlaveFactory_l347_1) begin - bridge_masterLogic_fsm_dropped_stop <= _zz_bridge_masterLogic_fsm_dropped_stop[0]; - end - end - if(when_BusSlaveFactory_l341_2) begin - if(when_BusSlaveFactory_l347_2) begin - bridge_masterLogic_fsm_dropped_recover <= _zz_bridge_masterLogic_fsm_dropped_recover[0]; - end - end - case(i2cCtrl_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_READ : begin - if(when_I2cCtrl_l566) begin - bridge_dataCounter <= (bridge_dataCounter + 3'b001); - if(when_I2cCtrl_l570) begin - if(bridge_txData_disableOnDataConflict) begin - bridge_txData_enable <= 1'b0; - end - if(bridge_txAck_disableOnDataConflict) begin - bridge_txAck_enable <= 1'b0; - end - end - if(when_I2cCtrl_l574) begin - if(bridge_rxData_listen) begin - bridge_rxData_valid <= 1'b1; - end - bridge_rxData_event <= 1'b1; - bridge_inAckState <= 1'b1; - if(when_I2cCtrl_l578) begin - bridge_txData_valid <= 1'b0; - end - end - end else begin - if(bridge_rxAck_listen) begin - bridge_rxAck_valid <= 1'b1; - end - bridge_inAckState <= 1'b0; - bridge_wasntAck <= i2cCtrl_io_bus_cmd_data; - if(when_I2cCtrl_l588) begin - bridge_txAck_valid <= 1'b0; - end - end - end - default : begin - end - endcase - if(bridge_frameReset) begin - bridge_inAckState <= 1'b0; - bridge_dataCounter <= 3'b000; - bridge_wasntAck <= 1'b0; - end - if(when_I2cCtrl_l601) begin - bridge_txData_valid <= 1'b1; - bridge_txData_enable <= 1'b0; - bridge_txData_repeat <= 1'b1; - bridge_txAck_valid <= 1'b1; - bridge_txAck_enable <= 1'b0; - bridge_txAck_repeat <= 1'b1; - bridge_rxData_listen <= 1'b0; - bridge_rxAck_listen <= 1'b0; - end - if(when_I2cCtrl_l634) begin - bridge_interruptCtrl_start_flag <= 1'b1; - end - if(when_I2cCtrl_l634_1) begin - bridge_interruptCtrl_start_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_3) begin - if(when_BusSlaveFactory_l347_3) begin - bridge_interruptCtrl_start_flag <= _zz_bridge_interruptCtrl_start_flag[0]; - end - end - if(when_I2cCtrl_l634_2) begin - bridge_interruptCtrl_restart_flag <= 1'b1; - end - if(when_I2cCtrl_l634_3) begin - bridge_interruptCtrl_restart_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_4) begin - if(when_BusSlaveFactory_l347_4) begin - bridge_interruptCtrl_restart_flag <= _zz_bridge_interruptCtrl_restart_flag[0]; - end - end - if(when_I2cCtrl_l634_4) begin - bridge_interruptCtrl_end_flag <= 1'b1; - end - if(when_I2cCtrl_l634_5) begin - bridge_interruptCtrl_end_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_5) begin - if(when_BusSlaveFactory_l347_5) begin - bridge_interruptCtrl_end_flag <= _zz_bridge_interruptCtrl_end_flag[0]; - end - end - if(when_I2cCtrl_l634_6) begin - bridge_interruptCtrl_drop_flag <= 1'b1; - end - if(when_I2cCtrl_l634_7) begin - bridge_interruptCtrl_drop_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_6) begin - if(when_BusSlaveFactory_l347_6) begin - bridge_interruptCtrl_drop_flag <= _zz_bridge_interruptCtrl_drop_flag[0]; - end - end - if(when_I2cCtrl_l634_8) begin - bridge_interruptCtrl_filterGen_flag <= 1'b1; - end - if(when_I2cCtrl_l634_9) begin - bridge_interruptCtrl_filterGen_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_7) begin - if(when_BusSlaveFactory_l347_7) begin - bridge_interruptCtrl_filterGen_flag <= _zz_bridge_interruptCtrl_filterGen_flag[0]; - end - end - if(when_I2cCtrl_l634_10) begin - bridge_interruptCtrl_clockGenExit_flag <= 1'b1; - end - if(when_I2cCtrl_l634_11) begin - bridge_interruptCtrl_clockGenExit_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_8) begin - if(when_BusSlaveFactory_l347_8) begin - bridge_interruptCtrl_clockGenExit_flag <= _zz_bridge_interruptCtrl_clockGenExit_flag[0]; - end - end - if(when_I2cCtrl_l634_12) begin - bridge_interruptCtrl_clockGenEnter_flag <= 1'b1; - end - if(when_I2cCtrl_l634_13) begin - bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_9) begin - if(when_BusSlaveFactory_l347_9) begin - bridge_interruptCtrl_clockGenEnter_flag <= _zz_bridge_interruptCtrl_clockGenEnter_flag[0]; - end - end - bridge_masterLogic_fsm_stateReg <= bridge_masterLogic_fsm_stateNext; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - if(!when_I2cCtrl_l367) begin - if(when_I2cCtrl_l369) begin - bridge_txData_valid <= 1'b0; - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_start <= 1'b0; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - if(i2cCtrl_io_internals_sdaRead) begin - bridge_masterLogic_stop <= 1'b0; - bridge_masterLogic_recover <= 1'b0; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_I2cCtrl_l350) begin - bridge_masterLogic_start <= 1'b0; - bridge_masterLogic_stop <= 1'b0; - bridge_masterLogic_drop <= 1'b0; - bridge_masterLogic_recover <= 1'b0; - if(bridge_masterLogic_start) begin - bridge_masterLogic_fsm_dropped_start <= 1'b1; - end - if(bridge_masterLogic_stop) begin - bridge_masterLogic_fsm_dropped_stop <= 1'b1; - end - end - bridge_i2cBuffer_scl_write_regNext <= bridge_i2cBuffer_scl_write; - bridge_i2cBuffer_sda_write_regNext <= bridge_i2cBuffer_sda_write; - case(io_ctrl_cmd_payload_fragment_address) - 8'h08 : begin - if(busCtrl_doWrite) begin - bridge_rxData_listen <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h0c : begin - if(busCtrl_doWrite) begin - bridge_rxAck_listen <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h0 : begin - if(busCtrl_doWrite) begin - bridge_txData_repeat <= io_ctrl_cmd_payload_fragment_data[10]; - bridge_txData_valid <= io_ctrl_cmd_payload_fragment_data[8]; - bridge_txData_enable <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h04 : begin - if(busCtrl_doWrite) begin - bridge_txAck_repeat <= io_ctrl_cmd_payload_fragment_data[10]; - bridge_txAck_valid <= io_ctrl_cmd_payload_fragment_data[8]; - bridge_txAck_enable <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h88 : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_0_enable <= io_ctrl_cmd_payload_fragment_data[15]; - end - end - 8'h8c : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_1_enable <= io_ctrl_cmd_payload_fragment_data[15]; - end - end - 8'h20 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_rxDataEnable <= io_ctrl_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_rxAckEnable <= io_ctrl_cmd_payload_fragment_data[1]; - bridge_interruptCtrl_txDataEnable <= io_ctrl_cmd_payload_fragment_data[2]; - bridge_interruptCtrl_txAckEnable <= io_ctrl_cmd_payload_fragment_data[3]; - bridge_interruptCtrl_start_enable <= io_ctrl_cmd_payload_fragment_data[4]; - bridge_interruptCtrl_restart_enable <= io_ctrl_cmd_payload_fragment_data[5]; - bridge_interruptCtrl_end_enable <= io_ctrl_cmd_payload_fragment_data[6]; - bridge_interruptCtrl_drop_enable <= io_ctrl_cmd_payload_fragment_data[7]; - bridge_interruptCtrl_filterGen_enable <= io_ctrl_cmd_payload_fragment_data[17]; - bridge_interruptCtrl_clockGenExit_enable <= io_ctrl_cmd_payload_fragment_data[15]; - bridge_interruptCtrl_clockGenEnter_enable <= io_ctrl_cmd_payload_fragment_data[16]; - end - end - 8'h28 : begin - if(busCtrl_doWrite) begin - _zz_io_config_samplingClockDivider <= io_ctrl_cmd_payload_fragment_data[9 : 0]; - end - end - 8'h48 : begin - if(busCtrl_doWrite) begin - bridge_slaveOverride_sda <= io_ctrl_cmd_payload_fragment_data[1]; - bridge_slaveOverride_scl <= io_ctrl_cmd_payload_fragment_data[2]; - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_ctrl_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - if(bridge_rxData_event) begin - case(bridge_addressFilter_state) - 2'b00 : begin - bridge_addressFilter_byte0 <= bridge_rxData_value; - end - 2'b01 : begin - bridge_addressFilter_byte1 <= bridge_rxData_value; - end - default : begin - end - endcase - end - _zz_when_I2cCtrl_l310_1 <= _zz_when_I2cCtrl_l310; - bridge_masterLogic_timer_value <= (bridge_masterLogic_timer_value - _zz_bridge_masterLogic_timer_value); - if(when_I2cCtrl_l363) begin - bridge_masterLogic_fsm_inFrameLate <= 1'b1; - end - if(when_I2cCtrl_l363_1) begin - bridge_masterLogic_fsm_inFrameLate <= 1'b0; - end - case(i2cCtrl_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_READ : begin - if(when_I2cCtrl_l566) begin - bridge_rxData_value[_zz_bridge_rxData_value] <= i2cCtrl_io_bus_cmd_data; - end else begin - bridge_rxAck_value <= i2cCtrl_io_bus_cmd_data; - end - end - default : begin - end - endcase - if(when_I2cCtrl_l601) begin - bridge_txData_disableOnDataConflict <= 1'b0; - bridge_txAck_disableOnDataConflict <= 1'b0; - end - _zz_when_I2cCtrl_l634_1 <= _zz_when_I2cCtrl_l634; - bridge_masterLogic_fsm_isBusy_regNext <= bridge_masterLogic_fsm_isBusy; - bridge_masterLogic_fsm_isBusy_regNext_1 <= bridge_masterLogic_fsm_isBusy; - bridge_timeoutClear <= 1'b0; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - if(when_I2cCtrl_l450) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - if(when_I2cCtrl_l474) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_StateMachine_l253) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - if(when_StateMachine_l253_1) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; - end - if(when_StateMachine_l253_2) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; - end - if(when_StateMachine_l253_3) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - if(when_StateMachine_l253_4) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - if(when_StateMachine_l253_5) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tBuf; - end - case(io_ctrl_cmd_payload_fragment_address) - 8'h0 : begin - if(busCtrl_doWrite) begin - bridge_txData_value <= io_ctrl_cmd_payload_fragment_data[7 : 0]; - bridge_txData_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; - end - end - 8'h04 : begin - if(busCtrl_doWrite) begin - bridge_txAck_value <= io_ctrl_cmd_payload_fragment_data[0]; - bridge_txAck_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; - end - end - 8'h88 : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_0_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; - bridge_addressFilter_addresses_0_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; - end - end - 8'h8c : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_1_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; - bridge_addressFilter_addresses_1_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; - end - end - 8'h50 : begin - if(busCtrl_doWrite) begin - bridge_masterLogic_timer_tLow <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 8'h54 : begin - if(busCtrl_doWrite) begin - bridge_masterLogic_timer_tHigh <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 8'h58 : begin - if(busCtrl_doWrite) begin - bridge_masterLogic_timer_tBuf <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 8'h2c : begin - if(busCtrl_doWrite) begin - _zz_io_config_timeout <= io_ctrl_cmd_payload_fragment_data[19 : 0]; - bridge_timeoutClear <= 1'b1; - end - end - 8'h30 : begin - if(busCtrl_doWrite) begin - _zz_io_config_tsuData <= io_ctrl_cmd_payload_fragment_data[5 : 0]; - end - end - default : begin - end - endcase - end - - always @(posedge clk) begin - if(reset) begin - i2cCtrl_io_internals_inFrame_regNext <= 1'b0; - end else begin - i2cCtrl_io_internals_inFrame_regNext <= i2cCtrl_io_internals_inFrame; - end - end - - -endmodule - -module Axi4PeripheralBmbSpiXdrMasterCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_ctrl_cmd_valid, - output wire io_ctrl_cmd_ready, - input wire io_ctrl_cmd_payload_last, - input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, - input wire [11:0] io_ctrl_cmd_payload_fragment_address, - input wire [1:0] io_ctrl_cmd_payload_fragment_length, - input wire [31:0] io_ctrl_cmd_payload_fragment_data, - input wire [2:0] io_ctrl_cmd_payload_fragment_context, - output wire io_ctrl_rsp_valid, - input wire io_ctrl_rsp_ready, - output wire io_ctrl_rsp_payload_last, - output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, - output wire [31:0] io_ctrl_rsp_payload_fragment_data, - output wire [2:0] io_ctrl_rsp_payload_fragment_context, - output wire [0:0] io_spi_sclk_write, - output wire io_spi_data_0_writeEnable, - input wire [0:0] io_spi_data_0_read, - output wire [0:0] io_spi_data_0_write, - output wire io_spi_data_1_writeEnable, - input wire [0:0] io_spi_data_1_read, - output wire [0:0] io_spi_data_1_write, - output wire io_spi_data_2_writeEnable, - input wire [0:0] io_spi_data_2_read, - output wire [0:0] io_spi_data_2_write, - output wire io_spi_data_3_writeEnable, - input wire [0:0] io_spi_data_3_read, - output wire [0:0] io_spi_data_3_write, - output wire [3:0] io_spi_ss, - output wire system_spi_0_io_interrupt_source, - input wire clk, - input wire reset -); - - wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; - wire ctrl_io_cmd_ready; - wire ctrl_io_rsp_valid; - wire [7:0] ctrl_io_rsp_payload_data; - wire [0:0] ctrl_io_spi_sclk_write; - wire [3:0] ctrl_io_spi_ss; - wire [0:0] ctrl_io_spi_data_0_write; - wire ctrl_io_spi_data_0_writeEnable; - wire [0:0] ctrl_io_spi_data_1_write; - wire ctrl_io_spi_data_1_writeEnable; - wire [0:0] ctrl_io_spi_data_2_write; - wire ctrl_io_spi_data_2_writeEnable; - wire [0:0] ctrl_io_spi_data_3_write; - wire ctrl_io_spi_data_3_writeEnable; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; - wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; - wire factory_readErrorFlag; - wire factory_writeErrorFlag; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - reg [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [2:0] factory_rsp_payload_fragment_context; - wire _zz_factory_rsp_ready; - reg _zz_factory_rsp_ready_1; - wire _zz_io_ctrl_rsp_valid; - reg _zz_io_ctrl_rsp_valid_1; - reg _zz_io_ctrl_rsp_payload_last; - reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; - reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; - wire when_Stream_l375; - wire factory_askWrite; - wire factory_askRead; - wire io_ctrl_cmd_fire; - wire factory_doWrite; - wire factory_doRead; - wire when_BmbSlaveFactory_l33; - wire when_BmbSlaveFactory_l35; - wire [31:0] mapping_cmdLogic_writeData; - reg mapping_cmdLogic_doRegular; - reg mapping_cmdLogic_doWriteLarge; - reg mapping_cmdLogic_doReadWriteLarge; - wire mapping_cmdLogic_streamUnbuffered_valid; - wire mapping_cmdLogic_streamUnbuffered_ready; - wire mapping_cmdLogic_streamUnbuffered_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_payload_read; - wire mapping_cmdLogic_streamUnbuffered_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - wire when_Stream_l375_1; - wire ctrl_io_rsp_toStream_valid; - wire ctrl_io_rsp_toStream_ready; - wire [7:0] ctrl_io_rsp_toStream_payload_data; - reg _zz_io_pop_ready; - reg _zz_io_pop_ready_1; - reg mapping_interruptCtrl_cmdIntEnable; - reg mapping_interruptCtrl_rspIntEnable; - wire mapping_interruptCtrl_cmdInt; - wire mapping_interruptCtrl_rspInt; - wire mapping_interruptCtrl_interrupt; - reg _zz_io_config_kind_cpol; - reg _zz_io_config_kind_cpha; - reg [1:0] _zz_io_config_mod; - reg [11:0] _zz_io_config_sclkToggle; - reg [11:0] _zz_io_config_ss_setup; - reg [11:0] _zz_io_config_ss_hold; - reg [11:0] _zz_io_config_ss_disable; - reg [3:0] _zz_io_config_ss_activeHigh; - wire [1:0] _zz_io_config_kind_cpol_1; - - Axi4PeripheralTopLevel_035069daf0ad4fb491e9c65d79bd2ddd ctrl ( - .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i - .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i - .io_config_sclkToggle (_zz_io_config_sclkToggle[11:0] ), //i - .io_config_mod (_zz_io_config_mod[1:0] ), //i - .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh[3:0] ), //i - .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i - .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i - .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i - .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i - .io_cmd_ready (ctrl_io_cmd_ready ), //o - .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i - .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i - .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i - .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i - .io_rsp_valid (ctrl_io_rsp_valid ), //o - .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o - .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (io_spi_data_0_read ), //i - .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (io_spi_data_1_read ), //i - .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (io_spi_data_2_read ), //i - .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (io_spi_data_3_read ), //i - .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o - .io_spi_ss (ctrl_io_spi_ss[3:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo_2_035069daf0ad4fb491e9c65d79bd2ddd mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( - .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i - .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o - .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i - .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i - .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i - .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i - .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o - .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ), //i - .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o - .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o - .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o - .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o - .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo_3_035069daf0ad4fb491e9c65d79bd2ddd ctrl_io_rsp_queueWithOccupancy ( - .io_push_valid (ctrl_io_rsp_toStream_valid ), //i - .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o - .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i - .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o - .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - assign factory_readErrorFlag = 1'b0; - assign factory_writeErrorFlag = 1'b0; - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_factory_rsp_ready = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready_1 && _zz_factory_rsp_ready); - always @(*) begin - _zz_factory_rsp_ready_1 = io_ctrl_rsp_ready; - if(when_Stream_l375) begin - _zz_factory_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); - assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (factory_doWrite && factory_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - factory_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - factory_rsp_payload_fragment_opcode = 1'b1; - end else begin - factory_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (factory_doRead && factory_readErrorFlag); - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - 12'h004 : begin - factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; - end - 12'h00c : begin - factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; - factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; - factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; - factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; - end - 12'h058 : begin - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - default : begin - end - endcase - end - - assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - always @(*) begin - mapping_cmdLogic_doRegular = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doRegular = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h050 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doReadWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h054 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doReadWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); - assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; - assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN)); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data); - always @(*) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - if(when_Stream_l375_1) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l375_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; - assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; - assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; - assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; - always @(*) begin - _zz_io_pop_ready = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doRead) begin - _zz_io_pop_ready = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - _zz_io_pop_ready_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h058 : begin - if(factory_doRead) begin - _zz_io_pop_ready_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); - assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); - assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); - assign io_spi_sclk_write = ctrl_io_spi_sclk_write; - assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; - assign io_spi_data_0_write = ctrl_io_spi_data_0_write; - assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; - assign io_spi_data_1_write = ctrl_io_spi_data_1_write; - assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; - assign io_spi_data_2_write = ctrl_io_spi_data_2_write; - assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; - assign io_spi_data_3_write = ctrl_io_spi_data_3_write; - assign io_spi_ss = ctrl_io_spi_ss; - assign system_spi_0_io_interrupt_source = mapping_interruptCtrl_interrupt; - assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; - assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; - always @(posedge clk) begin - if(reset) begin - _zz_io_ctrl_rsp_valid_1 <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; - mapping_interruptCtrl_cmdIntEnable <= 1'b0; - mapping_interruptCtrl_rspIntEnable <= 1'b0; - _zz_io_config_ss_activeHigh <= 4'b0000; - end else begin - if(_zz_factory_rsp_ready_1) begin - _zz_io_ctrl_rsp_valid_1 <= (factory_rsp_valid && _zz_factory_rsp_ready); - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b0; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h00c : begin - if(factory_doWrite) begin - mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; - mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; - end - end - 12'h030 : begin - if(factory_doWrite) begin - _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[3 : 0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(_zz_factory_rsp_ready_1) begin - _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h008 : begin - if(factory_doWrite) begin - _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; - _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; - _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; - end - end - 12'h020 : begin - if(factory_doWrite) begin - _zz_io_config_sclkToggle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h024 : begin - if(factory_doWrite) begin - _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h028 : begin - if(factory_doWrite) begin - _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h02c : begin - if(factory_doWrite) begin - _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - default : begin - end - endcase - end - - -endmodule - -module Axi4PeripheralBmbUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_bus_cmd_valid, - output wire io_bus_cmd_ready, - input wire io_bus_cmd_payload_last, - input wire [0:0] io_bus_cmd_payload_fragment_opcode, - input wire [5:0] io_bus_cmd_payload_fragment_address, - input wire [1:0] io_bus_cmd_payload_fragment_length, - input wire [31:0] io_bus_cmd_payload_fragment_data, - input wire [2:0] io_bus_cmd_payload_fragment_context, - output wire io_bus_rsp_valid, - input wire io_bus_rsp_ready, - output wire io_bus_rsp_payload_last, - output wire [0:0] io_bus_rsp_payload_fragment_opcode, - output wire [31:0] io_bus_rsp_payload_fragment_data, - output wire [2:0] io_bus_rsp_payload_fragment_context, - output wire io_uart_txd, - input wire io_uart_rxd, - output wire system_uart_0_io_interrupt_source, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - - reg uartCtrl_io_read_queueWithOccupancy_io_pop_ready; - wire uartCtrl_io_write_ready; - wire uartCtrl_io_read_valid; - wire [7:0] uartCtrl_io_read_payload; - wire uartCtrl_io_uart_txd; - wire uartCtrl_io_readError; - wire uartCtrl_io_readBreak; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; - wire uartCtrl_io_read_queueWithOccupancy_io_push_ready; - wire uartCtrl_io_read_queueWithOccupancy_io_pop_valid; - wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_pop_payload; - wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_occupancy; - wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_availability; - wire [0:0] _zz_bridge_misc_readError; - wire [0:0] _zz_bridge_misc_readOverflowError; - wire [0:0] _zz_bridge_misc_breakDetected; - wire [0:0] _zz_bridge_misc_doBreak; - wire [0:0] _zz_bridge_misc_doBreak_1; - wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; - wire busCtrl_readErrorFlag; - wire busCtrl_writeErrorFlag; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - reg [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [2:0] busCtrl_rsp_payload_fragment_context; - wire _zz_busCtrl_rsp_ready; - reg _zz_busCtrl_rsp_ready_1; - wire _zz_io_bus_rsp_valid; - reg _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [2:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l375; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_bus_cmd_fire; - wire busCtrl_doWrite; - wire busCtrl_doRead; - wire when_BmbSlaveFactory_l33; - wire when_BmbSlaveFactory_l35; - wire bridge_busCtrlWrapped_readErrorFlag; - wire bridge_busCtrlWrapped_writeErrorFlag; - reg [2:0] bridge_uartConfigReg_frame_dataLength; - reg [0:0] bridge_uartConfigReg_frame_stop; - reg [1:0] bridge_uartConfigReg_frame_parity; - reg [19:0] bridge_uartConfigReg_clockDivider; - reg _zz_bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_ready; - wire [7:0] bridge_write_streamUnbuffered_payload; - reg bridge_read_streamBreaked_valid; - reg bridge_read_streamBreaked_ready; - wire [7:0] bridge_read_streamBreaked_payload; - reg bridge_interruptCtrl_writeIntEnable; - reg bridge_interruptCtrl_readIntEnable; - wire bridge_interruptCtrl_readInt; - wire bridge_interruptCtrl_writeInt; - wire bridge_interruptCtrl_interrupt; - reg bridge_misc_readError; - reg when_BusSlaveFactory_l341; - wire when_BusSlaveFactory_l347; - reg bridge_misc_readOverflowError; - reg when_BusSlaveFactory_l341_1; - wire when_BusSlaveFactory_l347_1; - wire uartCtrl_io_read_isStall; - reg bridge_misc_breakDetected; - reg uartCtrl_io_readBreak_regNext; - wire when_UartCtrl_l155; - reg when_BusSlaveFactory_l341_2; - wire when_BusSlaveFactory_l347_2; - reg bridge_misc_doBreak; - reg when_BusSlaveFactory_l377; - wire when_BusSlaveFactory_l379; - reg when_BusSlaveFactory_l341_3; - wire when_BusSlaveFactory_l347_3; - wire [1:0] _zz_bridge_uartConfigReg_frame_parity; - wire [0:0] _zz_bridge_uartConfigReg_frame_stop; - wire when_BmbSlaveFactory_l77; - `ifndef SYNTHESIS - reg [23:0] bridge_uartConfigReg_frame_stop_string; - reg [31:0] bridge_uartConfigReg_frame_parity_string; - reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; - reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; - `endif - - - assign _zz_bridge_misc_readError = 1'b0; - assign _zz_bridge_misc_readOverflowError = 1'b0; - assign _zz_bridge_misc_breakDetected = 1'b0; - assign _zz_bridge_misc_doBreak = 1'b1; - assign _zz_bridge_misc_doBreak_1 = 1'b0; - assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); - Axi4PeripheralUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd uartCtrl ( - .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i - .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i - .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i - .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i - .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i - .io_write_ready (uartCtrl_io_write_ready ), //o - .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i - .io_read_valid (uartCtrl_io_read_valid ), //o - .io_read_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //i - .io_read_payload (uartCtrl_io_read_payload[7:0] ), //o - .io_uart_txd (uartCtrl_io_uart_txd ), //o - .io_uart_rxd (io_uart_rxd ), //i - .io_readError (uartCtrl_io_readError ), //o - .io_writeBreak (bridge_misc_doBreak ), //i - .io_readBreak (uartCtrl_io_readBreak ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd bridge_write_streamUnbuffered_queueWithOccupancy ( - .io_push_valid (bridge_write_streamUnbuffered_valid ), //i - .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i - .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_io_write_ready ), //i - .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd uartCtrl_io_read_queueWithOccupancy ( - .io_push_valid (uartCtrl_io_read_valid ), //i - .io_push_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (uartCtrl_io_read_payload[7:0] ), //i - .io_pop_valid (uartCtrl_io_read_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_io_read_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload (uartCtrl_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (uartCtrl_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (uartCtrl_io_read_queueWithOccupancy_io_availability[7:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(bridge_uartConfigReg_frame_stop) - Axi4PeripheralUartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; - default : bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(bridge_uartConfigReg_frame_parity) - Axi4PeripheralUartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; - default : bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_parity) - Axi4PeripheralUartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; - default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_stop) - Axi4PeripheralUartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; - default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - `endif - - assign io_uart_txd = uartCtrl_io_uart_txd; - assign busCtrl_readErrorFlag = 1'b0; - assign busCtrl_writeErrorFlag = 1'b0; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); - always @(*) begin - _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; - if(when_Stream_l375) begin - _zz_busCtrl_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); - assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - busCtrl_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; - end - 6'h04 : begin - busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_io_read_queueWithOccupancy_io_occupancy; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; - end - 6'h10 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; - busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_io_readBreak; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - assign bridge_busCtrlWrapped_readErrorFlag = 1'b0; - assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0; - always @(*) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doWrite) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; - assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; - assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - always @(*) begin - bridge_read_streamBreaked_valid = uartCtrl_io_read_queueWithOccupancy_io_pop_valid; - if(uartCtrl_io_readBreak) begin - bridge_read_streamBreaked_valid = 1'b0; - end - end - - always @(*) begin - uartCtrl_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; - if(uartCtrl_io_readBreak) begin - uartCtrl_io_read_queueWithOccupancy_io_pop_ready = 1'b1; - end - end - - assign bridge_read_streamBreaked_payload = uartCtrl_io_read_queueWithOccupancy_io_pop_payload; - always @(*) begin - bridge_read_streamBreaked_ready = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doRead) begin - bridge_read_streamBreaked_ready = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); - assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); - assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); - always @(*) begin - when_BusSlaveFactory_l341 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347 = io_bus_cmd_payload_fragment_data[0]; - always @(*) begin - when_BusSlaveFactory_l341_1 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_1 = io_bus_cmd_payload_fragment_data[1]; - assign uartCtrl_io_read_isStall = (uartCtrl_io_read_valid && (! uartCtrl_io_read_queueWithOccupancy_io_push_ready)); - assign when_UartCtrl_l155 = (uartCtrl_io_readBreak && (! uartCtrl_io_readBreak_regNext)); - always @(*) begin - when_BusSlaveFactory_l341_2 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_2 = io_bus_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l377 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379 = io_bus_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l341_3 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_3 = io_bus_cmd_payload_fragment_data[11]; - assign system_uart_0_io_interrupt_source = bridge_interruptCtrl_interrupt; - assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; - assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; - assign when_BmbSlaveFactory_l77 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); - always @(posedge clk) begin - if(reset) begin - _zz_io_bus_rsp_valid_1 <= 1'b0; - bridge_uartConfigReg_clockDivider <= 20'h0; - bridge_uartConfigReg_clockDivider <= 20'h000d8; - bridge_uartConfigReg_frame_dataLength <= 3'b111; - bridge_uartConfigReg_frame_parity <= Axi4PeripheralUartParityType_NONE; - bridge_uartConfigReg_frame_stop <= Axi4PeripheralUartStopType_ONE; - bridge_interruptCtrl_writeIntEnable <= 1'b0; - bridge_interruptCtrl_readIntEnable <= 1'b0; - bridge_misc_readError <= 1'b0; - bridge_misc_readOverflowError <= 1'b0; - bridge_misc_breakDetected <= 1'b0; - bridge_misc_doBreak <= 1'b0; - end else begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); - end - if(when_BusSlaveFactory_l341) begin - if(when_BusSlaveFactory_l347) begin - bridge_misc_readError <= _zz_bridge_misc_readError[0]; - end - end - if(uartCtrl_io_readError) begin - bridge_misc_readError <= 1'b1; - end - if(when_BusSlaveFactory_l341_1) begin - if(when_BusSlaveFactory_l347_1) begin - bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; - end - end - if(uartCtrl_io_read_isStall) begin - bridge_misc_readOverflowError <= 1'b1; - end - if(when_UartCtrl_l155) begin - bridge_misc_breakDetected <= 1'b1; - end - if(when_BusSlaveFactory_l341_2) begin - if(when_BusSlaveFactory_l347_2) begin - bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; - end - end - if(when_BusSlaveFactory_l377) begin - if(when_BusSlaveFactory_l379) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; - end - end - if(when_BusSlaveFactory_l341_3) begin - if(when_BusSlaveFactory_l347_3) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; - end - end - case(io_bus_cmd_payload_fragment_address) - 6'h0c : begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; - bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; - bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; - end - end - 6'h04 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; - end - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l77) begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_clockDivider[19 : 0] <= io_bus_cmd_payload_fragment_data[19 : 0]; - end - end - end - end - - always @(posedge clk) begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - uartCtrl_io_readBreak_regNext <= uartCtrl_io_readBreak; - end - - -endmodule - -module Axi4PeripheralBmbDecoder_1_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [23:0] io_input_cmd_payload_fragment_address, - input wire [1:0] io_input_cmd_payload_fragment_length, - input wire [31:0] io_input_cmd_payload_fragment_data, - input wire [3:0] io_input_cmd_payload_fragment_mask, - input wire [2:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input wire io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output wire [31:0] io_input_rsp_payload_fragment_data, - output reg [2:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input wire io_outputs_0_cmd_ready, - output wire io_outputs_0_cmd_payload_last, - output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_0_cmd_payload_fragment_address, - output wire [1:0] io_outputs_0_cmd_payload_fragment_length, - output wire [31:0] io_outputs_0_cmd_payload_fragment_data, - output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_0_cmd_payload_fragment_context, - input wire io_outputs_0_rsp_valid, - output wire io_outputs_0_rsp_ready, - input wire io_outputs_0_rsp_payload_last, - input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_0_rsp_payload_fragment_data, - input wire [2:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input wire io_outputs_1_cmd_ready, - output wire io_outputs_1_cmd_payload_last, - output wire [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_1_cmd_payload_fragment_address, - output wire [1:0] io_outputs_1_cmd_payload_fragment_length, - output wire [31:0] io_outputs_1_cmd_payload_fragment_data, - output wire [3:0] io_outputs_1_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_1_cmd_payload_fragment_context, - input wire io_outputs_1_rsp_valid, - output wire io_outputs_1_rsp_ready, - input wire io_outputs_1_rsp_payload_last, - input wire [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_1_rsp_payload_fragment_data, - input wire [2:0] io_outputs_1_rsp_payload_fragment_context, - output reg io_outputs_2_cmd_valid, - input wire io_outputs_2_cmd_ready, - output wire io_outputs_2_cmd_payload_last, - output wire [0:0] io_outputs_2_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_2_cmd_payload_fragment_address, - output wire [1:0] io_outputs_2_cmd_payload_fragment_length, - output wire [31:0] io_outputs_2_cmd_payload_fragment_data, - output wire [3:0] io_outputs_2_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_2_cmd_payload_fragment_context, - input wire io_outputs_2_rsp_valid, - output wire io_outputs_2_rsp_ready, - input wire io_outputs_2_rsp_payload_last, - input wire [0:0] io_outputs_2_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_2_rsp_payload_fragment_data, - input wire [2:0] io_outputs_2_rsp_payload_fragment_context, - output reg io_outputs_3_cmd_valid, - input wire io_outputs_3_cmd_ready, - output wire io_outputs_3_cmd_payload_last, - output wire [0:0] io_outputs_3_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_3_cmd_payload_fragment_address, - output wire [1:0] io_outputs_3_cmd_payload_fragment_length, - output wire [31:0] io_outputs_3_cmd_payload_fragment_data, - output wire [3:0] io_outputs_3_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_3_cmd_payload_fragment_context, - input wire io_outputs_3_rsp_valid, - output wire io_outputs_3_rsp_ready, - input wire io_outputs_3_rsp_payload_last, - input wire [0:0] io_outputs_3_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_3_rsp_payload_fragment_data, - input wire [2:0] io_outputs_3_rsp_payload_fragment_context, - output reg io_outputs_4_cmd_valid, - input wire io_outputs_4_cmd_ready, - output wire io_outputs_4_cmd_payload_last, - output wire [0:0] io_outputs_4_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_4_cmd_payload_fragment_address, - output wire [1:0] io_outputs_4_cmd_payload_fragment_length, - output wire [31:0] io_outputs_4_cmd_payload_fragment_data, - output wire [3:0] io_outputs_4_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_4_cmd_payload_fragment_context, - input wire io_outputs_4_rsp_valid, - output wire io_outputs_4_rsp_ready, - input wire io_outputs_4_rsp_payload_last, - input wire [0:0] io_outputs_4_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_4_rsp_payload_fragment_data, - input wire [2:0] io_outputs_4_rsp_payload_fragment_context, - output reg io_outputs_5_cmd_valid, - input wire io_outputs_5_cmd_ready, - output wire io_outputs_5_cmd_payload_last, - output wire [0:0] io_outputs_5_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_5_cmd_payload_fragment_address, - output wire [1:0] io_outputs_5_cmd_payload_fragment_length, - output wire [31:0] io_outputs_5_cmd_payload_fragment_data, - output wire [3:0] io_outputs_5_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_5_cmd_payload_fragment_context, - input wire io_outputs_5_rsp_valid, - output wire io_outputs_5_rsp_ready, - input wire io_outputs_5_rsp_payload_last, - input wire [0:0] io_outputs_5_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_5_rsp_payload_fragment_data, - input wire [2:0] io_outputs_5_rsp_payload_fragment_context, - input wire clk, - input wire reset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_4; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [2:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [2:0] logic_input_payload_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_hitsS0_2; - wire logic_hitsS0_3; - wire logic_hitsS0_4; - wire logic_hitsS0_5; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - wire _zz_io_outputs_2_cmd_payload_last; - wire _zz_io_outputs_3_cmd_payload_last; - wire _zz_io_outputs_4_cmd_payload_last; - wire _zz_io_outputs_5_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - reg logic_rspHits_2; - reg logic_rspHits_3; - reg logic_rspHits_4; - reg logic_rspHits_5; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire when_BmbDecoder_l60; - wire when_BmbDecoder_l60_1; - reg logic_rspNoHit_singleBeatRsp; - reg [2:0] logic_rspNoHit_context; - wire _zz_io_input_rsp_payload_last; - wire _zz_io_input_rsp_payload_last_1; - wire _zz_io_input_rsp_payload_last_2; - wire [2:0] _zz_io_input_rsp_payload_last_3; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last_3) - 3'b000 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - 3'b001 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - 3'b010 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_2_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; - end - 3'b011 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_3_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; - end - 3'b100 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_4_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_5_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_5_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_5_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_5_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign logic_noHitS0 = (! (|{logic_hitsS0_5,{logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}}})); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h030000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h020000); - always @(*) begin - io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS0_2); - if(logic_cmdWait) begin - io_outputs_2_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; - assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; - assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h040000); - always @(*) begin - io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS0_3); - if(logic_cmdWait) begin - io_outputs_3_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; - assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; - assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h050000); - always @(*) begin - io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS0_4); - if(logic_cmdWait) begin - io_outputs_4_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; - assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; - assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_5 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); - always @(*) begin - io_outputs_5_cmd_valid = (logic_input_valid && logic_hitsS0_5); - if(logic_cmdWait) begin - io_outputs_5_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_5_cmd_payload_last = logic_input_payload_last; - assign io_outputs_5_cmd_payload_last = _zz_io_outputs_5_cmd_payload_last; - assign io_outputs_5_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_5_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_5_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_5_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_5_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_5_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = ((|{(logic_hitsS0_5 && io_outputs_5_cmd_ready),{(logic_hitsS0_4 && io_outputs_4_cmd_ready),{(logic_hitsS0_3 && io_outputs_3_cmd_ready),{(logic_hitsS0_2 && io_outputs_2_cmd_ready),{(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)}}}}}) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (|{logic_rspHits_5,{logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}}})); - assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); - always @(*) begin - io_input_rsp_valid = ((|{io_outputs_5_rsp_valid,{io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}}}) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = ((logic_rspHits_1 || logic_rspHits_3) || logic_rspHits_5); - assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_2 = (logic_rspHits_4 || logic_rspHits_5); - assign _zz_io_input_rsp_payload_last_3 = {_zz_io_input_rsp_payload_last_2,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_4; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign io_outputs_2_rsp_ready = io_input_rsp_ready; - assign io_outputs_3_rsp_ready = io_input_rsp_ready; - assign io_outputs_4_rsp_ready = io_input_rsp_ready; - assign io_outputs_5_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && (((((((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || (logic_hitsS0_2 != logic_rspHits_2)) || (logic_hitsS0_3 != logic_rspHits_3)) || (logic_hitsS0_4 != logic_rspHits_4)) || (logic_hitsS0_5 != logic_rspHits_5)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge clk) begin - if(reset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - logic_rspHits_1 <= logic_hitsS0_1; - logic_rspHits_2 <= logic_hitsS0_2; - logic_rspHits_3 <= logic_hitsS0_3; - logic_rspHits_4 <= logic_hitsS0_4; - logic_rspHits_5 <= logic_hitsS0_5; - end - if(logic_input_fire) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - end - - -endmodule - -module Axi4PeripheralBmbUnburstify_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_input_cmd_valid, - output reg io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [23:0] io_input_cmd_payload_fragment_address, - input wire [9:0] io_input_cmd_payload_fragment_length, - input wire [31:0] io_input_cmd_payload_fragment_data, - input wire [3:0] io_input_cmd_payload_fragment_mask, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_source, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [31:0] io_input_rsp_payload_fragment_data, - output reg io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output reg [0:0] io_output_cmd_payload_fragment_opcode, - output reg [23:0] io_output_cmd_payload_fragment_address, - output reg [1:0] io_output_cmd_payload_fragment_length, - output wire [31:0] io_output_cmd_payload_fragment_data, - output wire [3:0] io_output_cmd_payload_fragment_mask, - output wire [2:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output reg io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [31:0] io_output_rsp_payload_fragment_data, - input wire [2:0] io_output_rsp_payload_fragment_context, - input wire clk, - input wire reset -); - - wire [7:0] _zz_buffer_last; - wire [0:0] _zz_buffer_last_1; - wire [11:0] _zz_buffer_addressIncr; - wire doResult; - reg buffer_valid; - reg [0:0] buffer_opcode; - reg [0:0] buffer_source; - reg [23:0] buffer_address; - reg [7:0] buffer_beat; - wire buffer_last; - wire [23:0] buffer_addressIncr; - wire buffer_isWrite; - wire io_output_cmd_fire; - wire [7:0] cmdTransferBeatCount; - wire requireBuffer; - reg cmdContext_drop; - reg cmdContext_last; - reg [0:0] cmdContext_source; - wire rspContext_drop; - wire rspContext_last; - wire [0:0] rspContext_source; - wire [2:0] _zz_rspContext_drop; - wire when_Stream_l445; - reg io_output_rsp_thrown_valid; - wire io_output_rsp_thrown_ready; - wire io_output_rsp_thrown_payload_last; - wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; - wire [31:0] io_output_rsp_thrown_payload_fragment_data; - wire [2:0] io_output_rsp_thrown_payload_fragment_context; - - assign _zz_buffer_last_1 = 1'b1; - assign _zz_buffer_last = {7'd0, _zz_buffer_last_1}; - assign _zz_buffer_addressIncr = (buffer_address[11 : 0] + 12'h004); - assign buffer_last = (buffer_beat == _zz_buffer_last); - assign buffer_addressIncr = {buffer_address[23 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; - assign buffer_isWrite = (buffer_opcode == 1'b1); - assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); - assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[9 : 2]; - assign requireBuffer = (cmdTransferBeatCount != 8'h0); - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_last = 1'b1; - assign io_output_cmd_payload_fragment_context = {cmdContext_source,{cmdContext_last,cmdContext_drop}}; - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_address = buffer_addressIncr; - end else begin - io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - if(requireBuffer) begin - io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; - end - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_opcode = buffer_opcode; - end else begin - io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - if(requireBuffer) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; - end - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_source = buffer_source; - end else begin - cmdContext_source = io_input_cmd_payload_fragment_source; - end - end - - always @(*) begin - io_input_cmd_ready = 1'b0; - if(buffer_valid) begin - io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); - end else begin - io_input_cmd_ready = io_output_cmd_ready; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); - end else begin - io_output_cmd_valid = io_input_cmd_valid; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_last = buffer_last; - end else begin - cmdContext_last = (! requireBuffer); - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_drop = buffer_isWrite; - end else begin - cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); - end - end - - assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; - assign rspContext_drop = _zz_rspContext_drop[0]; - assign rspContext_last = _zz_rspContext_drop[1]; - assign rspContext_source = _zz_rspContext_drop[2 : 2]; - assign when_Stream_l445 = (! (rspContext_last || (! rspContext_drop))); - always @(*) begin - io_output_rsp_thrown_valid = io_output_rsp_valid; - if(when_Stream_l445) begin - io_output_rsp_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_output_rsp_ready = io_output_rsp_thrown_ready; - if(when_Stream_l445) begin - io_output_rsp_ready = 1'b1; - end - end - - assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; - assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_input_rsp_valid = io_output_rsp_thrown_valid; - assign io_output_rsp_thrown_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = rspContext_last; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - always @(posedge clk) begin - if(reset) begin - buffer_valid <= 1'b0; - end else begin - if(io_output_cmd_fire) begin - if(buffer_last) begin - buffer_valid <= 1'b0; - end - end - if(!buffer_valid) begin - buffer_valid <= (requireBuffer && io_output_cmd_fire); - end - end - end - - always @(posedge clk) begin - if(io_output_cmd_fire) begin - buffer_beat <= (buffer_beat - 8'h01); - buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; - end - if(!buffer_valid) begin - buffer_opcode <= io_input_cmd_payload_fragment_opcode; - buffer_source <= io_input_cmd_payload_fragment_source; - buffer_address <= io_input_cmd_payload_fragment_address; - buffer_beat <= cmdTransferBeatCount; - end - end - - -endmodule - -module Axi4PeripheralBmbDecoder_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [23:0] io_input_cmd_payload_fragment_address, - input wire [9:0] io_input_cmd_payload_fragment_length, - input wire [31:0] io_input_cmd_payload_fragment_data, - input wire [3:0] io_input_cmd_payload_fragment_mask, - output reg io_input_rsp_valid, - input wire io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_source, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output wire [31:0] io_input_rsp_payload_fragment_data, - output reg io_outputs_0_cmd_valid, - input wire io_outputs_0_cmd_ready, - output wire io_outputs_0_cmd_payload_last, - output wire [0:0] io_outputs_0_cmd_payload_fragment_source, - output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_0_cmd_payload_fragment_address, - output wire [9:0] io_outputs_0_cmd_payload_fragment_length, - output wire [31:0] io_outputs_0_cmd_payload_fragment_data, - output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, - input wire io_outputs_0_rsp_valid, - output wire io_outputs_0_rsp_ready, - input wire io_outputs_0_rsp_payload_last, - input wire [0:0] io_outputs_0_rsp_payload_fragment_source, - input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_0_rsp_payload_fragment_data, - input wire clk, - input wire reset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_source; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [9:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire logic_hitsS0_0; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire when_BmbDecoder_l60; - wire when_BmbDecoder_l60_1; - reg logic_rspNoHit_singleBeatRsp; - reg [0:0] logic_rspNoHit_source; - reg [7:0] logic_rspNoHit_counter; - wire when_BmbDecoder_l81; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_noHitS0 = (! (|logic_hitsS0_0)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'hffffff)) == 24'h0); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - always @(*) begin - logic_input_ready = ((|(logic_hitsS0_0 && io_outputs_0_cmd_ready)) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (|logic_rspHits_0)); - assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); - always @(*) begin - io_input_rsp_valid = ((|io_outputs_0_rsp_valid) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b0; - if(when_BmbDecoder_l81) begin - io_input_rsp_payload_last = 1'b1; - end - if(logic_rspNoHit_singleBeatRsp) begin - io_input_rsp_payload_last = 1'b1; - end - end - end - - always @(*) begin - io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_source = logic_rspNoHit_source; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 8'h0); - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge clk) begin - if(reset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - end - if(logic_input_fire) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire) begin - logic_rspNoHit_source <= logic_input_payload_fragment_source; - end - if(logic_input_fire) begin - logic_rspNoHit_counter <= logic_input_payload_fragment_length[9 : 2]; - end - if(logic_rspNoHit_doIt) begin - if(io_input_rsp_fire) begin - logic_rspNoHit_counter <= (logic_rspNoHit_counter - 8'h01); - end - end - end - - -endmodule - -module Axi4PeripheralAxi4SharedToBmb_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_axi_arw_valid, - output wire io_axi_arw_ready, - input wire [23:0] io_axi_arw_payload_addr, - input wire [7:0] io_axi_arw_payload_len, - input wire [2:0] io_axi_arw_payload_size, - input wire [3:0] io_axi_arw_payload_cache, - input wire [2:0] io_axi_arw_payload_prot, - input wire io_axi_arw_payload_write, - input wire io_axi_w_valid, - output wire io_axi_w_ready, - input wire [31:0] io_axi_w_payload_data, - input wire [3:0] io_axi_w_payload_strb, - input wire io_axi_w_payload_last, - output wire io_axi_b_valid, - input wire io_axi_b_ready, - output reg [1:0] io_axi_b_payload_resp, - output wire io_axi_r_valid, - input wire io_axi_r_ready, - output wire [31:0] io_axi_r_payload_data, - output reg [1:0] io_axi_r_payload_resp, - output wire io_axi_r_payload_last, - output wire io_bmb_cmd_valid, - input wire io_bmb_cmd_ready, - output wire io_bmb_cmd_payload_last, - output wire [0:0] io_bmb_cmd_payload_fragment_source, - output wire [0:0] io_bmb_cmd_payload_fragment_opcode, - output wire [23:0] io_bmb_cmd_payload_fragment_address, - output wire [9:0] io_bmb_cmd_payload_fragment_length, - output wire [31:0] io_bmb_cmd_payload_fragment_data, - output wire [3:0] io_bmb_cmd_payload_fragment_mask, - input wire io_bmb_rsp_valid, - output wire io_bmb_rsp_ready, - input wire io_bmb_rsp_payload_last, - input wire [0:0] io_bmb_rsp_payload_fragment_source, - input wire [0:0] io_bmb_rsp_payload_fragment_opcode, - input wire [31:0] io_bmb_rsp_payload_fragment_data -); - - wire [9:0] _zz_io_bmb_cmd_payload_fragment_length; - wire hazard; - wire io_bmb_cmd_fire; - wire rspIsWrite; - wire when_Axi4SharedToBmb_l42; - wire when_Axi4SharedToBmb_l49; - - assign _zz_io_bmb_cmd_payload_fragment_length = ({2'd0,io_axi_arw_payload_len} <<< 2'd2); - assign hazard = (io_axi_arw_payload_write && (! io_axi_w_valid)); - assign io_bmb_cmd_valid = (io_axi_arw_valid && (! hazard)); - assign io_bmb_cmd_payload_fragment_source = io_axi_arw_payload_write; - assign io_bmb_cmd_payload_fragment_opcode = io_axi_arw_payload_write; - assign io_bmb_cmd_payload_fragment_address = io_axi_arw_payload_addr; - assign io_bmb_cmd_payload_fragment_length = (_zz_io_bmb_cmd_payload_fragment_length | 10'h003); - assign io_bmb_cmd_payload_fragment_data = io_axi_w_payload_data; - assign io_bmb_cmd_payload_fragment_mask = io_axi_w_payload_strb; - assign io_bmb_cmd_payload_last = ((! io_axi_arw_payload_write) || io_axi_w_payload_last); - assign io_bmb_cmd_fire = (io_bmb_cmd_valid && io_bmb_cmd_ready); - assign io_axi_arw_ready = (io_bmb_cmd_fire && io_bmb_cmd_payload_last); - assign io_axi_w_ready = (io_bmb_cmd_fire && (io_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign rspIsWrite = io_bmb_rsp_payload_fragment_source[0]; - assign io_axi_b_valid = (io_bmb_rsp_valid && rspIsWrite); - always @(*) begin - io_axi_b_payload_resp = 2'b00; - if(when_Axi4SharedToBmb_l42) begin - io_axi_b_payload_resp = 2'b11; - end - end - - assign when_Axi4SharedToBmb_l42 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); - assign io_axi_r_valid = (io_bmb_rsp_valid && (! rspIsWrite)); - assign io_axi_r_payload_data = io_bmb_rsp_payload_fragment_data; - assign io_axi_r_payload_last = io_bmb_rsp_payload_last; - always @(*) begin - io_axi_r_payload_resp = 2'b00; - if(when_Axi4SharedToBmb_l49) begin - io_axi_r_payload_resp = 2'b11; - end - end - - assign when_Axi4SharedToBmb_l49 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); - assign io_bmb_rsp_ready = (rspIsWrite ? io_axi_b_ready : io_axi_r_ready); - -endmodule - -module Axi4PeripheralStreamArbiter_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_inputs_0_valid, - output wire io_inputs_0_ready, - input wire [23:0] io_inputs_0_payload_addr, - input wire [7:0] io_inputs_0_payload_len, - input wire [2:0] io_inputs_0_payload_size, - input wire [3:0] io_inputs_0_payload_cache, - input wire [2:0] io_inputs_0_payload_prot, - input wire io_inputs_1_valid, - output wire io_inputs_1_ready, - input wire [23:0] io_inputs_1_payload_addr, - input wire [7:0] io_inputs_1_payload_len, - input wire [2:0] io_inputs_1_payload_size, - input wire [3:0] io_inputs_1_payload_cache, - input wire [2:0] io_inputs_1_payload_prot, - output wire io_output_valid, - input wire io_output_ready, - output wire [23:0] io_output_payload_addr, - output wire [7:0] io_output_payload_len, - output wire [2:0] io_output_payload_size, - output wire [3:0] io_output_payload_cache, - output wire [2:0] io_output_payload_prot, - output wire [0:0] io_chosen, - output wire [1:0] io_chosenOH, - input wire clk, - input wire reset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr); - assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len); - assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size); - assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache); - assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge clk) begin - if(reset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(io_output_fire) begin - locked <= 1'b0; - end - end - end - - -endmodule - -//Axi4PeripheralTimer_1 replaced by Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd - -module Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_tick, - input wire io_clear, - input wire [15:0] io_limit, - output wire io_full, - output wire [15:0] io_value, - input wire clk, - input wire reset -); - - wire [15:0] _zz_counter; - wire [0:0] _zz_counter_1; - reg [15:0] counter; - wire limitHit; - reg inhibitFull; - - assign _zz_counter_1 = (! limitHit); - assign _zz_counter = {15'd0, _zz_counter_1}; - assign limitHit = (counter == io_limit); - assign io_full = ((limitHit && io_tick) && (! inhibitFull)); - assign io_value = counter; - always @(posedge clk) begin - if(reset) begin - inhibitFull <= 1'b0; - end else begin - if(io_tick) begin - inhibitFull <= limitHit; - end - if(io_clear) begin - inhibitFull <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(io_tick) begin - counter <= (counter + _zz_counter); - end - if(io_clear) begin - counter <= 16'h0; - end - end - - -endmodule - -module Axi4PeripheralPrescaler_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_clear, - input wire [23:0] io_limit, - output wire io_overflow, - input wire clk, - input wire reset -); - - reg [23:0] counter; - wire when_Prescaler_l17; - - assign when_Prescaler_l17 = (io_clear || io_overflow); - assign io_overflow = (counter == io_limit); - always @(posedge clk) begin - counter <= (counter + 24'h000001); - if(when_Prescaler_l17) begin - counter <= 24'h0; - end - end - - -endmodule - -module Axi4PeripheralI2cSlave_035069daf0ad4fb491e9c65d79bd2ddd ( - output wire io_i2c_sda_write, - input wire io_i2c_sda_read, - output wire io_i2c_scl_write, - input wire io_i2c_scl_read, - input wire [9:0] io_config_samplingClockDivider, - input wire [19:0] io_config_timeout, - input wire [5:0] io_config_tsuData, - input wire io_config_timeoutClear, - output reg [2:0] io_bus_cmd_kind, - output wire io_bus_cmd_data, - input wire io_bus_rsp_valid, - input wire io_bus_rsp_enable, - input wire io_bus_rsp_data, - output wire io_timeout, - output wire io_internals_inFrame, - output wire io_internals_sdaRead, - output wire io_internals_sclRead, - input wire clk, - input wire reset -); - localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; - localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; - localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; - localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; - localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; - localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; - localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; - - wire io_i2c_scl_read_buffercc_io_dataOut; - wire io_i2c_sda_read_buffercc_io_dataOut; - reg [9:0] filter_timer_counter; - wire filter_timer_tick; - wire filter_sampler_sclSync; - wire filter_sampler_sdaSync; - wire filter_sampler_sclSamples_0; - wire filter_sampler_sclSamples_1; - wire filter_sampler_sclSamples_2; - wire _zz_filter_sampler_sclSamples_0; - reg _zz_filter_sampler_sclSamples_1; - reg _zz_filter_sampler_sclSamples_2; - wire filter_sampler_sdaSamples_0; - wire filter_sampler_sdaSamples_1; - wire filter_sampler_sdaSamples_2; - wire _zz_filter_sampler_sdaSamples_0; - reg _zz_filter_sampler_sdaSamples_1; - reg _zz_filter_sampler_sdaSamples_2; - reg filter_sda; - reg filter_scl; - wire when_Misc_l82; - wire when_Misc_l85; - wire sclEdge_rise; - wire sclEdge_fall; - wire sclEdge_toggle; - reg filter_scl_regNext; - wire sdaEdge_rise; - wire sdaEdge_fall; - wire sdaEdge_toggle; - reg filter_sda_regNext; - wire detector_start; - wire detector_stop; - reg [5:0] tsuData_counter; - wire tsuData_done; - reg tsuData_reset; - wire when_I2CSlave_l191; - reg ctrl_inFrame; - reg ctrl_inFrameData; - reg ctrl_sdaWrite; - reg ctrl_sclWrite; - wire ctrl_rspBufferIn_valid; - reg ctrl_rspBufferIn_ready; - wire ctrl_rspBufferIn_payload_enable; - wire ctrl_rspBufferIn_payload_data; - wire ctrl_rspBuffer_valid; - reg ctrl_rspBuffer_ready; - wire ctrl_rspBuffer_payload_enable; - wire ctrl_rspBuffer_payload_data; - reg ctrl_rspBufferIn_rValid; - reg ctrl_rspBufferIn_rData_enable; - reg ctrl_rspBufferIn_rData_data; - wire when_Stream_l375; - wire ctrl_rspAhead_valid; - wire ctrl_rspAhead_payload_enable; - wire ctrl_rspAhead_payload_data; - wire when_I2CSlave_l241; - wire when_I2CSlave_l245; - wire when_I2CSlave_l251; - wire [2:0] _zz_io_bus_cmd_kind; - reg timeout_enabled; - reg [19:0] timeout_counter; - wire timeout_tick; - wire when_I2CSlave_l270; - wire when_I2CSlave_l276; - wire [2:0] _zz_io_bus_cmd_kind_1; - `ifndef SYNTHESIS - reg [55:0] io_bus_cmd_kind_string; - reg [55:0] _zz_io_bus_cmd_kind_string; - reg [55:0] _zz_io_bus_cmd_kind_1_string; - `endif - - - (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd io_i2c_scl_read_buffercc ( - .io_dataIn (io_i2c_scl_read ), //i - .io_dataOut (io_i2c_scl_read_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd io_i2c_sda_read_buffercc ( - .io_dataIn (io_i2c_sda_read ), //i - .io_dataOut (io_i2c_sda_read_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_NONE : io_bus_cmd_kind_string = "NONE "; - Axi4PeripheralI2cSlaveCmdMode_START : io_bus_cmd_kind_string = "START "; - Axi4PeripheralI2cSlaveCmdMode_RESTART : io_bus_cmd_kind_string = "RESTART"; - Axi4PeripheralI2cSlaveCmdMode_STOP : io_bus_cmd_kind_string = "STOP "; - Axi4PeripheralI2cSlaveCmdMode_DROP : io_bus_cmd_kind_string = "DROP "; - Axi4PeripheralI2cSlaveCmdMode_DRIVE : io_bus_cmd_kind_string = "DRIVE "; - Axi4PeripheralI2cSlaveCmdMode_READ : io_bus_cmd_kind_string = "READ "; - default : io_bus_cmd_kind_string = "???????"; - endcase - end - always @(*) begin - case(_zz_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_string = "NONE "; - Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_string = "START "; - Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_string = "RESTART"; - Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_string = "STOP "; - Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_string = "DROP "; - Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_string = "DRIVE "; - Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_string = "READ "; - default : _zz_io_bus_cmd_kind_string = "???????"; - endcase - end - always @(*) begin - case(_zz_io_bus_cmd_kind_1) - Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_1_string = "NONE "; - Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_1_string = "START "; - Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_1_string = "RESTART"; - Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_1_string = "STOP "; - Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_1_string = "DROP "; - Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_1_string = "DRIVE "; - Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_1_string = "READ "; - default : _zz_io_bus_cmd_kind_1_string = "???????"; - endcase - end - `endif - - assign filter_timer_tick = (filter_timer_counter == 10'h0); - assign filter_sampler_sclSync = io_i2c_scl_read_buffercc_io_dataOut; - assign filter_sampler_sdaSync = io_i2c_sda_read_buffercc_io_dataOut; - assign _zz_filter_sampler_sclSamples_0 = filter_sampler_sclSync; - assign filter_sampler_sclSamples_0 = _zz_filter_sampler_sclSamples_0; - assign filter_sampler_sclSamples_1 = _zz_filter_sampler_sclSamples_1; - assign filter_sampler_sclSamples_2 = _zz_filter_sampler_sclSamples_2; - assign _zz_filter_sampler_sdaSamples_0 = filter_sampler_sdaSync; - assign filter_sampler_sdaSamples_0 = _zz_filter_sampler_sdaSamples_0; - assign filter_sampler_sdaSamples_1 = _zz_filter_sampler_sdaSamples_1; - assign filter_sampler_sdaSamples_2 = _zz_filter_sampler_sdaSamples_2; - assign when_Misc_l82 = (&{(filter_sampler_sdaSamples_2 != filter_sda),{(filter_sampler_sdaSamples_1 != filter_sda),(filter_sampler_sdaSamples_0 != filter_sda)}}); - assign when_Misc_l85 = (&{(filter_sampler_sclSamples_2 != filter_scl),{(filter_sampler_sclSamples_1 != filter_scl),(filter_sampler_sclSamples_0 != filter_scl)}}); - assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl); - assign sclEdge_fall = (filter_scl_regNext && (! filter_scl)); - assign sclEdge_toggle = (filter_scl_regNext != filter_scl); - assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda); - assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda)); - assign sdaEdge_toggle = (filter_sda_regNext != filter_sda); - assign detector_start = (filter_scl && sdaEdge_fall); - assign detector_stop = (filter_scl && sdaEdge_rise); - assign tsuData_done = (tsuData_counter == 6'h0); - always @(*) begin - tsuData_reset = 1'b0; - if(ctrl_inFrameData) begin - tsuData_reset = (! ctrl_rspAhead_valid); - end - end - - assign when_I2CSlave_l191 = (! tsuData_done); - always @(*) begin - ctrl_sdaWrite = 1'b1; - if(ctrl_inFrameData) begin - if(when_I2CSlave_l251) begin - ctrl_sdaWrite = ctrl_rspAhead_payload_data; - end - end - end - - always @(*) begin - ctrl_sclWrite = 1'b1; - if(ctrl_inFrameData) begin - if(when_I2CSlave_l245) begin - ctrl_sclWrite = 1'b0; - end - end - end - - always @(*) begin - ctrl_rspBufferIn_ready = ctrl_rspBuffer_ready; - if(when_Stream_l375) begin - ctrl_rspBufferIn_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! ctrl_rspBuffer_valid); - assign ctrl_rspBuffer_valid = ctrl_rspBufferIn_rValid; - assign ctrl_rspBuffer_payload_enable = ctrl_rspBufferIn_rData_enable; - assign ctrl_rspBuffer_payload_data = ctrl_rspBufferIn_rData_data; - assign ctrl_rspAhead_valid = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_valid : ctrl_rspBufferIn_valid); - assign ctrl_rspAhead_payload_enable = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_enable : ctrl_rspBufferIn_payload_enable); - assign ctrl_rspAhead_payload_data = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_data : ctrl_rspBufferIn_payload_data); - assign ctrl_rspBufferIn_valid = io_bus_rsp_valid; - assign ctrl_rspBufferIn_payload_enable = io_bus_rsp_enable; - assign ctrl_rspBufferIn_payload_data = io_bus_rsp_data; - always @(*) begin - ctrl_rspBuffer_ready = 1'b0; - if(ctrl_inFrame) begin - if(sclEdge_fall) begin - ctrl_rspBuffer_ready = 1'b1; - end - end - end - - always @(*) begin - io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_NONE; - if(ctrl_inFrame) begin - if(sclEdge_rise) begin - io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_READ; - end - end - if(ctrl_inFrameData) begin - if(when_I2CSlave_l241) begin - io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_DRIVE; - end - end - if(detector_start) begin - io_bus_cmd_kind = _zz_io_bus_cmd_kind; - end - if(when_I2CSlave_l276) begin - if(ctrl_inFrame) begin - io_bus_cmd_kind = _zz_io_bus_cmd_kind_1; - end - end - end - - assign io_bus_cmd_data = filter_sda; - assign when_I2CSlave_l241 = ((! ctrl_rspBuffer_valid) || ctrl_rspBuffer_ready); - assign when_I2CSlave_l245 = ((! ctrl_rspAhead_valid) || (ctrl_rspAhead_payload_enable && (! tsuData_done))); - assign when_I2CSlave_l251 = (ctrl_rspAhead_valid && ctrl_rspAhead_payload_enable); - assign _zz_io_bus_cmd_kind = (ctrl_inFrame ? Axi4PeripheralI2cSlaveCmdMode_RESTART : Axi4PeripheralI2cSlaveCmdMode_START); - assign timeout_tick = (timeout_enabled && (timeout_counter == 20'h0)); - assign when_I2CSlave_l270 = (((timeout_tick || sclEdge_toggle) || (((! ctrl_inFrame) && filter_scl) && filter_sda)) || io_config_timeoutClear); - assign io_timeout = timeout_tick; - assign when_I2CSlave_l276 = (detector_stop || timeout_tick); - assign _zz_io_bus_cmd_kind_1 = (timeout_tick ? Axi4PeripheralI2cSlaveCmdMode_DROP : Axi4PeripheralI2cSlaveCmdMode_STOP); - assign io_internals_inFrame = ctrl_inFrame; - assign io_internals_sdaRead = filter_sda; - assign io_internals_sclRead = filter_scl; - assign io_i2c_scl_write = ctrl_sclWrite; - assign io_i2c_sda_write = ctrl_sdaWrite; - always @(posedge clk) begin - if(reset) begin - filter_timer_counter <= 10'h0; - _zz_filter_sampler_sclSamples_1 <= 1'b1; - _zz_filter_sampler_sclSamples_2 <= 1'b1; - _zz_filter_sampler_sdaSamples_1 <= 1'b1; - _zz_filter_sampler_sdaSamples_2 <= 1'b1; - filter_sda <= 1'b1; - filter_scl <= 1'b1; - filter_scl_regNext <= 1'b1; - filter_sda_regNext <= 1'b1; - tsuData_counter <= 6'h0; - ctrl_inFrame <= 1'b0; - ctrl_inFrameData <= 1'b0; - ctrl_rspBufferIn_rValid <= 1'b0; - timeout_counter <= 20'h0; - end else begin - filter_timer_counter <= (filter_timer_counter - 10'h001); - if(filter_timer_tick) begin - filter_timer_counter <= io_config_samplingClockDivider; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sclSamples_1 <= _zz_filter_sampler_sclSamples_0; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sclSamples_2 <= _zz_filter_sampler_sclSamples_1; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sdaSamples_1 <= _zz_filter_sampler_sdaSamples_0; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sdaSamples_2 <= _zz_filter_sampler_sdaSamples_1; - end - if(filter_timer_tick) begin - if(when_Misc_l82) begin - filter_sda <= filter_sampler_sdaSamples_2; - end - if(when_Misc_l85) begin - filter_scl <= filter_sampler_sclSamples_2; - end - end - filter_scl_regNext <= filter_scl; - filter_sda_regNext <= filter_sda; - if(when_I2CSlave_l191) begin - tsuData_counter <= (tsuData_counter - 6'h01); - end - if(tsuData_reset) begin - tsuData_counter <= io_config_tsuData; - end - if(ctrl_rspBufferIn_ready) begin - ctrl_rspBufferIn_rValid <= ctrl_rspBufferIn_valid; - end - if(ctrl_inFrame) begin - if(sclEdge_fall) begin - ctrl_inFrameData <= 1'b1; - end - end - if(detector_start) begin - ctrl_inFrame <= 1'b1; - ctrl_inFrameData <= 1'b0; - end - timeout_counter <= (timeout_counter - 20'h00001); - if(when_I2CSlave_l270) begin - timeout_counter <= io_config_timeout; - end - if(when_I2CSlave_l276) begin - ctrl_inFrame <= 1'b0; - ctrl_inFrameData <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(ctrl_rspBufferIn_ready) begin - ctrl_rspBufferIn_rData_enable <= ctrl_rspBufferIn_payload_enable; - ctrl_rspBufferIn_rData_data <= ctrl_rspBufferIn_payload_data; - end - timeout_enabled <= (io_config_timeout != 20'h0); - end - - -endmodule - -module Axi4PeripheralStreamFifo_3_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_push_valid, - output wire io_push_ready, - input wire [7:0] io_push_payload_data, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [7:0] io_pop_payload_data, - input wire io_flush, - output wire [8:0] io_occupancy, - output wire [8:0] io_availability, - input wire clk, - input wire reset -); - - reg [7:0] logic_ram_spinal_port1; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [8:0] logic_ptr_push; - reg [8:0] logic_ptr_pop; - wire [8:0] logic_ptr_occupancy; - wire [8:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire io_push_fire; - wire logic_push_onRam_write_valid; - wire [7:0] logic_push_onRam_write_payload_address; - wire [7:0] logic_push_onRam_write_payload_data_data; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [7:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [7:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [7:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [7:0] logic_pop_sync_readPort_cmd_payload; - wire [7:0] logic_pop_sync_readPort_rsp_data; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; - wire logic_pop_sync_readArbitation_fire; - reg [8:0] logic_pop_sync_popReg; - reg [7:0] logic_ram [0:255]; - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_data; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); - assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); - assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); - assign io_push_ready = (! logic_ptr_full); - assign io_push_fire = (io_push_valid && io_push_ready); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; - assign logic_push_onRam_write_payload_data_data = io_push_payload_data; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp_data = logic_ram_spinal_port1[7 : 0]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (9'h100 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - logic_ptr_wentUp <= 1'b0; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 9'h0; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 9'h001); - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 9'h001); - end - if(io_flush) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 9'h0; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module Axi4PeripheralStreamFifo_2_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_push_valid, - output wire io_push_ready, - input wire io_push_payload_kind, - input wire io_push_payload_read, - input wire io_push_payload_write, - input wire [7:0] io_push_payload_data, - output wire io_pop_valid, - input wire io_pop_ready, - output wire io_pop_payload_kind, - output wire io_pop_payload_read, - output wire io_pop_payload_write, - output wire [7:0] io_pop_payload_data, - input wire io_flush, - output wire [8:0] io_occupancy, - output wire [8:0] io_availability, - input wire clk, - input wire reset -); - - reg [10:0] logic_ram_spinal_port1; - wire [10:0] _zz_logic_ram_port; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [8:0] logic_ptr_push; - reg [8:0] logic_ptr_pop; - wire [8:0] logic_ptr_occupancy; - wire [8:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire io_push_fire; - wire logic_push_onRam_write_valid; - wire [7:0] logic_push_onRam_write_payload_address; - wire logic_push_onRam_write_payload_data_kind; - wire logic_push_onRam_write_payload_data_read; - wire logic_push_onRam_write_payload_data_write; - wire [7:0] logic_push_onRam_write_payload_data_data; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [7:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [7:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [7:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [7:0] logic_pop_sync_readPort_cmd_payload; - wire logic_pop_sync_readPort_rsp_kind; - wire logic_pop_sync_readPort_rsp_read; - wire logic_pop_sync_readPort_rsp_write; - wire [7:0] logic_pop_sync_readPort_rsp_data; - wire [10:0] _zz_logic_pop_sync_readPort_rsp_kind; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire logic_pop_sync_readArbitation_translated_payload_kind; - wire logic_pop_sync_readArbitation_translated_payload_read; - wire logic_pop_sync_readArbitation_translated_payload_write; - wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; - wire logic_pop_sync_readArbitation_fire; - reg [8:0] logic_pop_sync_popReg; - reg [10:0] logic_ram [0:255]; - - assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_data,{logic_push_onRam_write_payload_data_write,{logic_push_onRam_write_payload_data_read,logic_push_onRam_write_payload_data_kind}}}; - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); - assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); - assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); - assign io_push_ready = (! logic_ptr_full); - assign io_push_fire = (io_push_valid && io_push_ready); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; - assign logic_push_onRam_write_payload_data_kind = io_push_payload_kind; - assign logic_push_onRam_write_payload_data_read = io_push_payload_read; - assign logic_push_onRam_write_payload_data_write = io_push_payload_write; - assign logic_push_onRam_write_payload_data_data = io_push_payload_data; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign _zz_logic_pop_sync_readPort_rsp_kind = logic_ram_spinal_port1; - assign logic_pop_sync_readPort_rsp_kind = _zz_logic_pop_sync_readPort_rsp_kind[0]; - assign logic_pop_sync_readPort_rsp_read = _zz_logic_pop_sync_readPort_rsp_kind[1]; - assign logic_pop_sync_readPort_rsp_write = _zz_logic_pop_sync_readPort_rsp_kind[2]; - assign logic_pop_sync_readPort_rsp_data = _zz_logic_pop_sync_readPort_rsp_kind[10 : 3]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_kind = logic_pop_sync_readPort_rsp_kind; - assign logic_pop_sync_readArbitation_translated_payload_read = logic_pop_sync_readPort_rsp_read; - assign logic_pop_sync_readArbitation_translated_payload_write = logic_pop_sync_readPort_rsp_write; - assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_kind = logic_pop_sync_readArbitation_translated_payload_kind; - assign io_pop_payload_read = logic_pop_sync_readArbitation_translated_payload_read; - assign io_pop_payload_write = logic_pop_sync_readArbitation_translated_payload_write; - assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (9'h100 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - logic_ptr_wentUp <= 1'b0; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 9'h0; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 9'h001); - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 9'h001); - end - if(io_flush) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 9'h0; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module Axi4PeripheralTopLevel_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_config_kind_cpol, - input wire io_config_kind_cpha, - input wire [11:0] io_config_sclkToggle, - input wire [1:0] io_config_mod, - input wire [3:0] io_config_ss_activeHigh, - input wire [11:0] io_config_ss_setup, - input wire [11:0] io_config_ss_hold, - input wire [11:0] io_config_ss_disable, - input wire io_cmd_valid, - output reg io_cmd_ready, - input wire io_cmd_payload_kind, - input wire io_cmd_payload_read, - input wire io_cmd_payload_write, - input wire [7:0] io_cmd_payload_data, - output wire io_rsp_valid, - output wire [7:0] io_rsp_payload_data, - output wire [0:0] io_spi_sclk_write, - output reg io_spi_data_0_writeEnable, - input wire [0:0] io_spi_data_0_read, - output reg [0:0] io_spi_data_0_write, - output reg io_spi_data_1_writeEnable, - input wire [0:0] io_spi_data_1_read, - output reg [0:0] io_spi_data_1_write, - output reg io_spi_data_2_writeEnable, - input wire [0:0] io_spi_data_2_read, - output reg [0:0] io_spi_data_2_write, - output reg io_spi_data_3_writeEnable, - input wire [0:0] io_spi_data_3_read, - output reg [0:0] io_spi_data_3_write, - output wire [3:0] io_spi_ss, - input wire clk, - input wire reset -); - - reg [0:0] _zz_outputPhy_dataWrite_3; - wire [2:0] _zz_outputPhy_dataWrite_4; - reg [1:0] _zz_outputPhy_dataWrite_5; - wire [1:0] _zz_outputPhy_dataWrite_6; - wire [2:0] _zz_outputPhy_dataWrite_7; - reg [3:0] _zz_outputPhy_dataWrite_8; - wire [0:0] _zz_outputPhy_dataWrite_9; - wire [2:0] _zz_outputPhy_dataWrite_10; - wire [3:0] _zz_inputPhy_dataRead; - wire [3:0] _zz_inputPhy_dataRead_1; - wire [3:0] _zz_inputPhy_dataRead_2; - wire [3:0] _zz_inputPhy_dataRead_3; - wire [3:0] _zz_inputPhy_dataRead_4; - wire [3:0] _zz_inputPhy_dataRead_5; - wire [3:0] _zz_inputPhy_dataRead_6; - wire [8:0] _zz_inputPhy_bufferNext; - wire [10:0] _zz_inputPhy_bufferNext_1; - reg [11:0] timer_counter; - reg timer_reset; - wire timer_ss_setupHit; - wire timer_ss_holdHit; - wire timer_ss_disableHit; - wire timer_sclkToggleHit; - reg fsm_state; - reg [2:0] fsm_counter; - reg [2:0] _zz_fsm_counterPlus; - wire [2:0] fsm_counterPlus; - reg fsm_fastRate; - reg fsm_isDdr; - reg [2:0] fsm_counterMax; - reg fsm_lateSampling; - reg fsm_readFill; - reg fsm_readDone; - reg [3:0] fsm_ss; - wire when_SpiXdrMasterCtrl_l741; - wire when_SpiXdrMasterCtrl_l744; - wire when_SpiXdrMasterCtrl_l751; - wire when_SpiXdrMasterCtrl_l753; - wire when_SpiXdrMasterCtrl_l760; - wire when_SpiXdrMasterCtrl_l766; - wire when_SpiXdrMasterCtrl_l783; - reg [0:0] outputPhy_sclkWrite; - wire [0:0] _zz_io_spi_sclk_write; - wire when_SpiXdrMasterCtrl_l798; - reg [3:0] outputPhy_dataWrite; - reg [2:0] outputPhy_widthSel; - reg [2:0] outputPhy_offset; - wire [7:0] _zz_outputPhy_dataWrite; - wire [7:0] _zz_outputPhy_dataWrite_1; - wire [7:0] _zz_outputPhy_dataWrite_2; - wire when_SpiXdrMasterCtrl_l841; - wire when_SpiXdrMasterCtrl_l841_1; - reg [1:0] io_config_mod_delay_1; - reg [1:0] inputPhy_mod; - reg fsm_readFill_delay_1; - reg inputPhy_readFill; - reg fsm_readDone_delay_1; - reg inputPhy_readDone; - reg [6:0] inputPhy_buffer; - reg [7:0] inputPhy_bufferNext; - reg [2:0] inputPhy_widthSel; - wire [3:0] inputPhy_dataWrite; - reg [3:0] inputPhy_dataRead; - reg fsm_state_delay_1; - reg fsm_state_delay_2; - wire when_SpiXdrMasterCtrl_l863; - reg [3:0] inputPhy_dataReadBuffer; - - assign _zz_outputPhy_dataWrite_4 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_6 = (_zz_outputPhy_dataWrite_7 >>> 1'd1); - assign _zz_outputPhy_dataWrite_7 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_9 = (_zz_outputPhy_dataWrite_10 >>> 2'd2); - assign _zz_outputPhy_dataWrite_10 = (outputPhy_offset - fsm_counter); - assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; - assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; - always @(*) begin - case(_zz_outputPhy_dataWrite_4) - 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; - 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; - 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; - 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; - 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; - 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; - 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; - default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_6) - 2'b00 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[1 : 0]; - 2'b01 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[3 : 2]; - 2'b10 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[5 : 4]; - default : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[7 : 6]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_9) - 1'b0 : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[3 : 0]; - default : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[7 : 4]; - endcase - end - - always @(*) begin - timer_reset = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - timer_reset = timer_sclkToggleHit; - end else begin - if(!when_SpiXdrMasterCtrl_l760) begin - if(when_SpiXdrMasterCtrl_l766) begin - if(timer_ss_holdHit) begin - timer_reset = 1'b1; - end - end - end - end - end - if(when_SpiXdrMasterCtrl_l783) begin - timer_reset = 1'b1; - end - end - - assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); - assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); - assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); - assign timer_sclkToggleHit = (timer_counter == io_config_sclkToggle); - always @(*) begin - _zz_fsm_counterPlus = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - _zz_fsm_counterPlus = 3'b001; - end - 2'b01 : begin - _zz_fsm_counterPlus = 3'b010; - end - 2'b10 : begin - _zz_fsm_counterPlus = 3'b100; - end - default : begin - end - endcase - end - - assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); - always @(*) begin - fsm_fastRate = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_fastRate = 1'b0; - end - 2'b01 : begin - fsm_fastRate = 1'b0; - end - 2'b10 : begin - fsm_fastRate = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_isDdr = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_isDdr = 1'b0; - end - 2'b01 : begin - fsm_isDdr = 1'b0; - end - 2'b10 : begin - fsm_isDdr = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_counterMax = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - fsm_counterMax = 3'b111; - end - 2'b01 : begin - fsm_counterMax = 3'b110; - end - 2'b10 : begin - fsm_counterMax = 3'b100; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_lateSampling = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_lateSampling = 1'b1; - end - 2'b01 : begin - fsm_lateSampling = 1'b1; - end - 2'b10 : begin - fsm_lateSampling = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_readFill = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(when_SpiXdrMasterCtrl_l744) begin - fsm_readFill = 1'b1; - end - end - end - end - - always @(*) begin - fsm_readDone = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(when_SpiXdrMasterCtrl_l744) begin - fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); - end - end - end - end - - assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); - always @(*) begin - io_cmd_ready = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(when_SpiXdrMasterCtrl_l751) begin - if(when_SpiXdrMasterCtrl_l753) begin - io_cmd_ready = 1'b1; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l760) begin - if(timer_ss_setupHit) begin - io_cmd_ready = 1'b1; - end - end else begin - if(!when_SpiXdrMasterCtrl_l766) begin - if(timer_ss_disableHit) begin - io_cmd_ready = 1'b1; - end - end - end - end - end - end - - assign when_SpiXdrMasterCtrl_l741 = (! io_cmd_payload_kind); - assign when_SpiXdrMasterCtrl_l744 = ((timer_sclkToggleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l751 = ((timer_sclkToggleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l753 = (fsm_counter == fsm_counterMax); - assign when_SpiXdrMasterCtrl_l760 = io_cmd_payload_data[7]; - assign when_SpiXdrMasterCtrl_l766 = (! fsm_state); - assign when_SpiXdrMasterCtrl_l783 = ((! io_cmd_valid) || io_cmd_ready); - always @(*) begin - outputPhy_sclkWrite = 1'b0; - if(when_SpiXdrMasterCtrl_l798) begin - case(io_config_mod) - 2'b00 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b01 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b10 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - default : begin - end - endcase - end - end - - assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; - assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); - assign when_SpiXdrMasterCtrl_l798 = (io_cmd_valid && (! io_cmd_payload_kind)); - always @(*) begin - outputPhy_widthSel = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_widthSel = 3'b000; - end - 2'b01 : begin - outputPhy_widthSel = 3'b001; - end - 2'b10 : begin - outputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_offset = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_offset = 3'b111; - end - 2'b01 : begin - outputPhy_offset = 3'b111; - end - 2'b10 : begin - outputPhy_offset = 3'b111; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_dataWrite = 4'bxxxx; - case(outputPhy_widthSel) - 3'b000 : begin - outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; - end - 3'b001 : begin - outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_5; - end - 3'b010 : begin - outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_8; - end - default : begin - end - endcase - end - - assign _zz_outputPhy_dataWrite = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; - always @(*) begin - io_spi_data_0_writeEnable = 1'b0; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_writeEnable = 1'b1; - end - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l841) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_writeEnable = 1'b0; - case(io_config_mod) - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l841) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_2_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_3_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_0_write = 1'bx; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); - end - 2'b01 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - 2'b10 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_write = 1'bx; - case(io_config_mod) - 2'b01 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - 2'b10 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_2_write[0] = outputPhy_dataWrite[2]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_3_write[0] = outputPhy_dataWrite[3]; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l841 = (io_cmd_valid && io_cmd_payload_write); - assign when_SpiXdrMasterCtrl_l841_1 = (io_cmd_valid && io_cmd_payload_write); - always @(*) begin - inputPhy_bufferNext = 8'bxxxxxxxx; - case(inputPhy_widthSel) - 3'b000 : begin - inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; - end - 3'b001 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; - end - 3'b010 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; - end - default : begin - end - endcase - end - - always @(*) begin - inputPhy_widthSel = 3'bxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_widthSel = 3'b000; - end - 2'b01 : begin - inputPhy_widthSel = 3'b001; - end - 2'b10 : begin - inputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l863 = (! fsm_state_delay_2); - always @(*) begin - inputPhy_dataRead = 4'bxxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; - end - 2'b01 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; - end - 2'b10 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; - inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; - inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; - end - default : begin - end - endcase - end - - assign io_rsp_valid = inputPhy_readDone; - assign io_rsp_payload_data = inputPhy_bufferNext; - always @(posedge clk) begin - timer_counter <= (timer_counter + 12'h001); - if(timer_reset) begin - timer_counter <= 12'h0; - end - io_config_mod_delay_1 <= io_config_mod; - inputPhy_mod <= io_config_mod_delay_1; - fsm_state_delay_1 <= fsm_state; - fsm_state_delay_2 <= fsm_state_delay_1; - if(when_SpiXdrMasterCtrl_l863) begin - inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - end - case(inputPhy_widthSel) - 3'b000 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b001 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b010 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - default : begin - end - endcase - end - - always @(posedge clk) begin - if(reset) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - fsm_ss <= 4'b0000; - fsm_readFill_delay_1 <= 1'b0; - inputPhy_readFill <= 1'b0; - fsm_readDone_delay_1 <= 1'b0; - inputPhy_readDone <= 1'b0; - end else begin - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(timer_sclkToggleHit) begin - fsm_state <= (! fsm_state); - end - if(when_SpiXdrMasterCtrl_l751) begin - fsm_counter <= fsm_counterPlus; - if(when_SpiXdrMasterCtrl_l753) begin - fsm_state <= 1'b0; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l760) begin - fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b1; - end else begin - if(when_SpiXdrMasterCtrl_l766) begin - if(timer_ss_holdHit) begin - fsm_state <= 1'b1; - end - end else begin - fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b0; - end - end - end - end - if(when_SpiXdrMasterCtrl_l783) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - end - fsm_readFill_delay_1 <= fsm_readFill; - inputPhy_readFill <= fsm_readFill_delay_1; - fsm_readDone_delay_1 <= fsm_readDone; - inputPhy_readDone <= fsm_readDone_delay_1; - end - end - - -endmodule - -//Axi4PeripheralStreamFifo_1 replaced by Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd - -module Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_push_valid, - output wire io_push_ready, - input wire [7:0] io_push_payload, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [7:0] io_pop_payload, - input wire io_flush, - output wire [7:0] io_occupancy, - output wire [7:0] io_availability, - input wire clk, - input wire reset -); - - reg [7:0] logic_ram_spinal_port1; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [7:0] logic_ptr_push; - reg [7:0] logic_ptr_pop; - wire [7:0] logic_ptr_occupancy; - wire [7:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire io_push_fire; - wire logic_push_onRam_write_valid; - wire [6:0] logic_push_onRam_write_payload_address; - wire [7:0] logic_push_onRam_write_payload_data; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [6:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [6:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [6:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [6:0] logic_pop_sync_readPort_cmd_payload; - wire [7:0] logic_pop_sync_readPort_rsp; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [7:0] logic_pop_sync_readArbitation_translated_payload; - wire logic_pop_sync_readArbitation_fire; - reg [7:0] logic_pop_sync_popReg; - reg [7:0] logic_ram [0:127]; - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 8'h80) == 8'h0); - assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); - assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); - assign io_push_ready = (! logic_ptr_full); - assign io_push_fire = (io_push_valid && io_push_ready); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push[6:0]; - assign logic_push_onRam_write_payload_data = io_push_payload; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop[6:0]; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (8'h80 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 8'h0; - logic_ptr_pop <= 8'h0; - logic_ptr_wentUp <= 1'b0; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 8'h0; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 8'h01); - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 8'h01); - end - if(io_flush) begin - logic_ptr_push <= 8'h0; - logic_ptr_pop <= 8'h0; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 8'h0; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module Axi4PeripheralUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire [2:0] io_config_frame_dataLength, - input wire [0:0] io_config_frame_stop, - input wire [1:0] io_config_frame_parity, - input wire [19:0] io_config_clockDivider, - input wire io_write_valid, - output reg io_write_ready, - input wire [7:0] io_write_payload, - output wire io_read_valid, - input wire io_read_ready, - output wire [7:0] io_read_payload, - output wire io_uart_txd, - input wire io_uart_rxd, - output wire io_readError, - input wire io_writeBreak, - output wire io_readBreak, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - - wire tx_io_write_ready; - wire tx_io_txd; - wire rx_io_read_valid; - wire [7:0] rx_io_read_payload; - wire rx_io_rts; - wire rx_io_error; - wire rx_io_break; - reg [19:0] clockDivider_counter; - wire clockDivider_tick; - reg clockDivider_tickReg; - reg io_write_thrown_valid; - wire io_write_thrown_ready; - wire [7:0] io_write_thrown_payload; - `ifndef SYNTHESIS - reg [23:0] io_config_frame_stop_string; - reg [31:0] io_config_frame_parity_string; - `endif - - - Axi4PeripheralUartCtrlTx_035069daf0ad4fb491e9c65d79bd2ddd tx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_write_valid (io_write_thrown_valid ), //i - .io_write_ready (tx_io_write_ready ), //o - .io_write_payload (io_write_thrown_payload[7:0] ), //i - .io_cts (1'b0 ), //i - .io_txd (tx_io_txd ), //o - .io_break (io_writeBreak ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralUartCtrlRx_035069daf0ad4fb491e9c65d79bd2ddd rx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_read_valid (rx_io_read_valid ), //o - .io_read_ready (io_read_ready ), //i - .io_read_payload (rx_io_read_payload[7:0] ), //o - .io_rxd (io_uart_rxd ), //i - .io_rts (rx_io_rts ), //o - .io_error (rx_io_error ), //o - .io_break (rx_io_break ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_config_frame_stop) - Axi4PeripheralUartStopType_ONE : io_config_frame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : io_config_frame_stop_string = "TWO"; - default : io_config_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_config_frame_parity) - Axi4PeripheralUartParityType_NONE : io_config_frame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : io_config_frame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : io_config_frame_parity_string = "ODD "; - default : io_config_frame_parity_string = "????"; - endcase - end - `endif - - assign clockDivider_tick = (clockDivider_counter == 20'h0); - always @(*) begin - io_write_thrown_valid = io_write_valid; - if(rx_io_break) begin - io_write_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_write_ready = io_write_thrown_ready; - if(rx_io_break) begin - io_write_ready = 1'b1; - end - end - - assign io_write_thrown_payload = io_write_payload; - assign io_write_thrown_ready = tx_io_write_ready; - assign io_read_valid = rx_io_read_valid; - assign io_read_payload = rx_io_read_payload; - assign io_uart_txd = tx_io_txd; - assign io_readError = rx_io_error; - assign io_readBreak = rx_io_break; - always @(posedge clk) begin - if(reset) begin - clockDivider_counter <= 20'h0; - clockDivider_tickReg <= 1'b0; - end else begin - clockDivider_tickReg <= clockDivider_tick; - clockDivider_counter <= (clockDivider_counter - 20'h00001); - if(clockDivider_tick) begin - clockDivider_counter <= io_config_clockDivider; - end - end - end - - -endmodule - -//Axi4PeripheralBufferCC_2 replaced by Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd - -module Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_dataIn, - output wire io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module Axi4PeripheralUartCtrlRx_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire [2:0] io_configFrame_dataLength, - input wire [0:0] io_configFrame_stop, - input wire [1:0] io_configFrame_parity, - input wire io_samplingTick, - output wire io_read_valid, - input wire io_read_ready, - output wire [7:0] io_read_payload, - input wire io_rxd, - output wire io_rts, - output reg io_error, - output wire io_break, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - localparam Axi4PeripheralUartCtrlRxState_IDLE = 3'd0; - localparam Axi4PeripheralUartCtrlRxState_START = 3'd1; - localparam Axi4PeripheralUartCtrlRxState_DATA = 3'd2; - localparam Axi4PeripheralUartCtrlRxState_PARITY = 3'd3; - localparam Axi4PeripheralUartCtrlRxState_STOP = 3'd4; - - wire io_rxd_buffercc_io_dataOut; - wire _zz_sampler_value; - wire _zz_sampler_value_1; - wire _zz_sampler_value_2; - wire _zz_sampler_value_3; - wire _zz_sampler_value_4; - wire _zz_sampler_value_5; - wire _zz_sampler_value_6; - wire [2:0] _zz_when_UartCtrlRx_l139; - wire [0:0] _zz_when_UartCtrlRx_l139_1; - reg _zz_io_rts; - wire sampler_synchroniser; - wire sampler_samples_0; - reg sampler_samples_1; - reg sampler_samples_2; - reg sampler_samples_3; - reg sampler_samples_4; - reg sampler_value; - reg sampler_tick; - reg [2:0] bitTimer_counter; - reg bitTimer_tick; - wire when_UartCtrlRx_l43; - reg [2:0] bitCounter_value; - reg [6:0] break_counter; - wire break_valid; - wire when_UartCtrlRx_l69; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg [7:0] stateMachine_shifter; - reg stateMachine_validReg; - wire when_UartCtrlRx_l93; - wire when_UartCtrlRx_l103; - wire when_UartCtrlRx_l111; - wire when_UartCtrlRx_l113; - wire when_UartCtrlRx_l125; - wire when_UartCtrlRx_l136; - wire when_UartCtrlRx_l139; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; - assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); - assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); - assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); - assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); - assign _zz_sampler_value_6 = 1'b1; - assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); - assign _zz_sampler_value_2 = 1'b1; - (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_035069daf0ad4fb491e9c65d79bd2ddd io_rxd_buffercc ( - .io_dataIn (io_rxd ), //i - .io_dataOut (io_rxd_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; - Axi4PeripheralUartCtrlRxState_START : stateMachine_state_string = "START "; - Axi4PeripheralUartCtrlRxState_DATA : stateMachine_state_string = "DATA "; - Axi4PeripheralUartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; - Axi4PeripheralUartCtrlRxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - io_error = 1'b0; - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : begin - end - Axi4PeripheralUartCtrlRxState_START : begin - end - Axi4PeripheralUartCtrlRxState_DATA : begin - end - Axi4PeripheralUartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(!when_UartCtrlRx_l125) begin - io_error = 1'b1; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - io_error = 1'b1; - end - end - end - endcase - end - - assign io_rts = _zz_io_rts; - assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; - assign sampler_samples_0 = sampler_synchroniser; - always @(*) begin - bitTimer_tick = 1'b0; - if(sampler_tick) begin - if(when_UartCtrlRx_l43) begin - bitTimer_tick = 1'b1; - end - end - end - - assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); - assign break_valid = (break_counter == 7'h68); - assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); - assign io_break = break_valid; - assign io_read_valid = stateMachine_validReg; - assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); - assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); - assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); - assign when_UartCtrlRx_l113 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); - assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); - assign when_UartCtrlRx_l136 = (! sampler_value); - assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); - assign io_read_payload = stateMachine_shifter; - always @(posedge clk) begin - if(reset) begin - _zz_io_rts <= 1'b0; - sampler_samples_1 <= 1'b1; - sampler_samples_2 <= 1'b1; - sampler_samples_3 <= 1'b1; - sampler_samples_4 <= 1'b1; - sampler_value <= 1'b1; - sampler_tick <= 1'b0; - break_counter <= 7'h0; - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - stateMachine_validReg <= 1'b0; - end else begin - _zz_io_rts <= (! io_read_ready); - if(io_samplingTick) begin - sampler_samples_1 <= sampler_samples_0; - end - if(io_samplingTick) begin - sampler_samples_2 <= sampler_samples_1; - end - if(io_samplingTick) begin - sampler_samples_3 <= sampler_samples_2; - end - if(io_samplingTick) begin - sampler_samples_4 <= sampler_samples_3; - end - sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); - sampler_tick <= io_samplingTick; - if(sampler_value) begin - break_counter <= 7'h0; - end else begin - if(when_UartCtrlRx_l69) begin - break_counter <= (break_counter + 7'h01); - end - end - stateMachine_validReg <= 1'b0; - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_START; - end - end - Axi4PeripheralUartCtrlRxState_START : begin - if(bitTimer_tick) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_DATA; - if(when_UartCtrlRx_l103) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end - end - end - Axi4PeripheralUartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l111) begin - if(when_UartCtrlRx_l113) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_PARITY; - end - end - end - end - Axi4PeripheralUartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l125) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end else begin - if(when_UartCtrlRx_l139) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end - end - end - end - endcase - end - end - - always @(posedge clk) begin - if(sampler_tick) begin - bitTimer_counter <= (bitTimer_counter - 3'b001); - end - if(bitTimer_tick) begin - bitCounter_value <= (bitCounter_value + 3'b001); - end - if(bitTimer_tick) begin - stateMachine_parity <= (stateMachine_parity ^ sampler_value); - end - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - bitTimer_counter <= 3'b010; - end - end - Axi4PeripheralUartCtrlRxState_START : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); - end - end - Axi4PeripheralUartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - stateMachine_shifter[bitCounter_value] <= sampler_value; - if(when_UartCtrlRx_l111) begin - bitCounter_value <= 3'b000; - end - end - end - Axi4PeripheralUartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module Axi4PeripheralUartCtrlTx_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire [2:0] io_configFrame_dataLength, - input wire [0:0] io_configFrame_stop, - input wire [1:0] io_configFrame_parity, - input wire io_samplingTick, - input wire io_write_valid, - output reg io_write_ready, - input wire [7:0] io_write_payload, - input wire io_cts, - output wire io_txd, - input wire io_break, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - localparam Axi4PeripheralUartCtrlTxState_IDLE = 3'd0; - localparam Axi4PeripheralUartCtrlTxState_START = 3'd1; - localparam Axi4PeripheralUartCtrlTxState_DATA = 3'd2; - localparam Axi4PeripheralUartCtrlTxState_PARITY = 3'd3; - localparam Axi4PeripheralUartCtrlTxState_STOP = 3'd4; - - wire [2:0] _zz_clockDivider_counter_valueNext; - wire [0:0] _zz_clockDivider_counter_valueNext_1; - wire [2:0] _zz_when_UartCtrlTx_l93; - wire [0:0] _zz_when_UartCtrlTx_l93_1; - reg clockDivider_counter_willIncrement; - wire clockDivider_counter_willClear; - reg [2:0] clockDivider_counter_valueNext; - reg [2:0] clockDivider_counter_value; - wire clockDivider_counter_willOverflowIfInc; - wire clockDivider_counter_willOverflow; - reg [2:0] tickCounter_value; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg stateMachine_txd; - wire when_UartCtrlTx_l58; - wire when_UartCtrlTx_l73; - wire when_UartCtrlTx_l76; - wire when_UartCtrlTx_l93; - wire [2:0] _zz_stateMachine_state; - reg _zz_io_txd; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - reg [47:0] _zz_stateMachine_state_string; - `endif - - - assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; - assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; - assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; - Axi4PeripheralUartCtrlTxState_START : stateMachine_state_string = "START "; - Axi4PeripheralUartCtrlTxState_DATA : stateMachine_state_string = "DATA "; - Axi4PeripheralUartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; - Axi4PeripheralUartCtrlTxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - always @(*) begin - case(_zz_stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE "; - Axi4PeripheralUartCtrlTxState_START : _zz_stateMachine_state_string = "START "; - Axi4PeripheralUartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA "; - Axi4PeripheralUartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY"; - Axi4PeripheralUartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP "; - default : _zz_stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - clockDivider_counter_willIncrement = 1'b0; - if(io_samplingTick) begin - clockDivider_counter_willIncrement = 1'b1; - end - end - - assign clockDivider_counter_willClear = 1'b0; - assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); - assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); - always @(*) begin - clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); - if(clockDivider_counter_willClear) begin - clockDivider_counter_valueNext = 3'b000; - end - end - - always @(*) begin - stateMachine_txd = 1'b1; - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - end - Axi4PeripheralUartCtrlTxState_START : begin - stateMachine_txd = 1'b0; - end - Axi4PeripheralUartCtrlTxState_DATA : begin - stateMachine_txd = io_write_payload[tickCounter_value]; - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - stateMachine_txd = stateMachine_parity; - end - default : begin - end - endcase - end - - always @(*) begin - io_write_ready = io_break; - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - end - Axi4PeripheralUartCtrlTxState_START : begin - end - Axi4PeripheralUartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - io_write_ready = 1'b1; - end - end - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - end - default : begin - end - endcase - end - - assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); - assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); - assign when_UartCtrlTx_l76 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); - assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); - assign _zz_stateMachine_state = (io_write_valid ? Axi4PeripheralUartCtrlTxState_START : Axi4PeripheralUartCtrlTxState_IDLE); - assign io_txd = _zz_io_txd; - always @(posedge clk) begin - if(reset) begin - clockDivider_counter_value <= 3'b000; - stateMachine_state <= Axi4PeripheralUartCtrlTxState_IDLE; - _zz_io_txd <= 1'b1; - end else begin - clockDivider_counter_value <= clockDivider_counter_valueNext; - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - if(when_UartCtrlTx_l58) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_START; - end - end - Axi4PeripheralUartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_DATA; - end - end - Axi4PeripheralUartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - if(when_UartCtrlTx_l76) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; - end else begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_PARITY; - end - end - end - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; - end - end - default : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l93) begin - stateMachine_state <= _zz_stateMachine_state; - end - end - end - endcase - _zz_io_txd <= (stateMachine_txd && (! io_break)); - end - end - - always @(posedge clk) begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= (tickCounter_value + 3'b001); - end - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); - end - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - end - Axi4PeripheralUartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); - tickCounter_value <= 3'b000; - end - end - Axi4PeripheralUartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - tickCounter_value <= 3'b000; - end - end - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module Axi4PeripheralBufferCC_035069daf0ad4fb491e9c65d79bd2ddd ( - input wire io_dataIn, - output wire io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh deleted file mode 100644 index bdfba5d..0000000 --- a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh +++ /dev/null @@ -1,46 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 1.22.0 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -localparam PERI_FREQ = 200; diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v deleted file mode 100644 index bf928f2..0000000 --- a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v +++ /dev/null @@ -1,148 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 1.22.0 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -EfxSapphireHpSoc_slb u_EfxSapphireHpSoc_slb -( - .io_peripheralClk ( io_peripheralClk ), - .io_peripheralReset ( io_peripheralReset ), - .io_asyncReset ( io_asyncReset ), - .io_gpio_sw_n ( io_gpio_sw_n ), - .pll_peripheral_locked ( pll_peripheral_locked ), - .pll_system_locked ( pll_system_locked ), - .jtagCtrl_capture ( jtagCtrl_capture ), - .jtagCtrl_enable ( jtagCtrl_enable ), - .jtagCtrl_reset ( jtagCtrl_reset ), - .jtagCtrl_shift ( jtagCtrl_shift ), - .jtagCtrl_tdi ( jtagCtrl_tdi ), - .jtagCtrl_tdo ( jtagCtrl_tdo ), - .jtagCtrl_update ( jtagCtrl_update ), - .ut_jtagCtrl_capture ( ut_jtagCtrl_capture ), - .ut_jtagCtrl_enable ( ut_jtagCtrl_enable ), - .ut_jtagCtrl_reset ( ut_jtagCtrl_reset ), - .ut_jtagCtrl_shift ( ut_jtagCtrl_shift ), - .ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ), - .ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ), - .ut_jtagCtrl_update ( ut_jtagCtrl_update ), - .system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), - .system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), - .system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), - .system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), - .system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), - .system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), - .system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), - .system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), - .system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), - .system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), - .system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), - .system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), - .system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), - .system_spi_0_io_ss ( system_spi_0_io_ss ), - .system_uart_0_io_rxd ( system_uart_0_io_rxd ), - .system_uart_0_io_txd ( system_uart_0_io_txd ), - .system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ), - .system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ), - .system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ), - .system_gpio_0_io_read ( system_gpio_0_io_read ), - .system_gpio_0_io_write ( system_gpio_0_io_write ), - .system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ), - .cfg_done ( cfg_done ), - .cfg_start ( cfg_start ), - .cfg_sel ( cfg_sel ), - .cfg_reset ( cfg_reset ), - .axiAInterrupt ( axiAInterrupt ), - .axiA_awaddr ( axiA_awaddr ), - .axiA_awlen ( axiA_awlen ), - .axiA_awsize ( axiA_awsize ), - .axiA_awburst ( axiA_awburst ), - .axiA_awlock ( axiA_awlock ), - .axiA_awcache ( axiA_awcache ), - .axiA_awprot ( axiA_awprot ), - .axiA_awqos ( axiA_awqos ), - .axiA_awregion ( axiA_awregion ), - .axiA_awvalid ( axiA_awvalid ), - .axiA_awready ( axiA_awready ), - .axiA_wdata ( axiA_wdata ), - .axiA_wstrb ( axiA_wstrb ), - .axiA_wvalid ( axiA_wvalid ), - .axiA_wlast ( axiA_wlast ), - .axiA_wready ( axiA_wready ), - .axiA_bresp ( axiA_bresp ), - .axiA_bvalid ( axiA_bvalid ), - .axiA_bready ( axiA_bready ), - .axiA_araddr ( axiA_araddr ), - .axiA_arlen ( axiA_arlen ), - .axiA_arsize ( axiA_arsize ), - .axiA_arburst ( axiA_arburst ), - .axiA_arlock ( axiA_arlock ), - .axiA_arcache ( axiA_arcache ), - .axiA_arprot ( axiA_arprot ), - .axiA_arqos ( axiA_arqos ), - .axiA_arregion ( axiA_arregion ), - .axiA_arvalid ( axiA_arvalid ), - .axiA_arready ( axiA_arready ), - .axiA_rdata ( axiA_rdata ), - .axiA_rresp ( axiA_rresp ), - .axiA_rlast ( axiA_rlast ), - .axiA_rvalid ( axiA_rvalid ), - .axiA_rready ( axiA_rready ), - .userInterruptA ( userInterruptA ), - .userInterruptB ( userInterruptB ), - .userInterruptC ( userInterruptC ), - .userInterruptD ( userInterruptD ), - .userInterruptE ( userInterruptE ), - .userInterruptF ( userInterruptF ), - .io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), - .io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), - .io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), - .io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), - .io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), - .io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), - .io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), - .io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), - .system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ), - .system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ), - .system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ), - .system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset ) -); diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd deleted file mode 100644 index e161e0a..0000000 --- a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd +++ /dev/null @@ -1,251 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component EfxSapphireHpSoc_slb is -port ( - io_peripheralClk : in std_logic; - io_peripheralReset : in std_logic; - io_asyncReset : out std_logic; - io_gpio_sw_n : in std_logic; - pll_peripheral_locked : in std_logic; - pll_system_locked : in std_logic; - jtagCtrl_capture : out std_logic; - jtagCtrl_enable : out std_logic; - jtagCtrl_reset : out std_logic; - jtagCtrl_shift : out std_logic; - jtagCtrl_tdi : out std_logic; - jtagCtrl_tdo : in std_logic; - jtagCtrl_update : out std_logic; - ut_jtagCtrl_capture : in std_logic; - ut_jtagCtrl_enable : in std_logic; - ut_jtagCtrl_reset : in std_logic; - ut_jtagCtrl_shift : in std_logic; - ut_jtagCtrl_tdi : in std_logic; - ut_jtagCtrl_tdo : out std_logic; - ut_jtagCtrl_update : in std_logic; - system_spi_0_io_data_0_read : in std_logic; - system_spi_0_io_data_0_write : out std_logic; - system_spi_0_io_data_0_writeEnable : out std_logic; - system_spi_0_io_data_1_read : in std_logic; - system_spi_0_io_data_1_write : out std_logic; - system_spi_0_io_data_1_writeEnable : out std_logic; - system_spi_0_io_data_2_read : in std_logic; - system_spi_0_io_data_2_write : out std_logic; - system_spi_0_io_data_2_writeEnable : out std_logic; - system_spi_0_io_data_3_read : in std_logic; - system_spi_0_io_data_3_write : out std_logic; - system_spi_0_io_data_3_writeEnable : out std_logic; - system_spi_0_io_sclk_write : out std_logic; - system_spi_0_io_ss : out std_logic_vector(3 downto 0); - system_uart_0_io_rxd : in std_logic; - system_uart_0_io_txd : out std_logic; - system_i2c_0_io_scl_read : in std_logic; - system_i2c_0_io_scl_write : out std_logic; - system_i2c_0_io_sda_read : in std_logic; - system_gpio_0_io_read : in std_logic_vector(3 downto 0); - system_gpio_0_io_write : out std_logic_vector(3 downto 0); - system_gpio_0_io_writeEnable : out std_logic_vector(3 downto 0); - cfg_done : in std_logic; - cfg_start : out std_logic; - cfg_sel : out std_logic; - cfg_reset : out std_logic; - axiAInterrupt : out std_logic; - axiA_awaddr : in std_logic_vector(31 downto 0); - axiA_awlen : in std_logic_vector(7 downto 0); - axiA_awsize : in std_logic_vector(2 downto 0); - axiA_awburst : in std_logic_vector(1 downto 0); - axiA_awlock : in std_logic; - axiA_awcache : in std_logic_vector(3 downto 0); - axiA_awprot : in std_logic_vector(2 downto 0); - axiA_awqos : in std_logic_vector(3 downto 0); - axiA_awregion : in std_logic_vector(3 downto 0); - axiA_awvalid : in std_logic; - axiA_awready : out std_logic; - axiA_wdata : in std_logic_vector(31 downto 0); - axiA_wstrb : in std_logic_vector(3 downto 0); - axiA_wvalid : in std_logic; - axiA_wlast : in std_logic; - axiA_wready : out std_logic; - axiA_bresp : out std_logic_vector(1 downto 0); - axiA_bvalid : out std_logic; - axiA_bready : in std_logic; - axiA_araddr : in std_logic_vector(31 downto 0); - axiA_arlen : in std_logic_vector(7 downto 0); - axiA_arsize : in std_logic_vector(2 downto 0); - axiA_arburst : in std_logic_vector(1 downto 0); - axiA_arlock : in std_logic; - axiA_arcache : in std_logic_vector(3 downto 0); - axiA_arprot : in std_logic_vector(2 downto 0); - axiA_arqos : in std_logic_vector(3 downto 0); - axiA_arregion : in std_logic_vector(3 downto 0); - axiA_arvalid : in std_logic; - axiA_arready : out std_logic; - axiA_rdata : out std_logic_vector(31 downto 0); - axiA_rresp : out std_logic_vector(1 downto 0); - axiA_rlast : out std_logic; - axiA_rvalid : out std_logic; - axiA_rready : in std_logic; - userInterruptA : out std_logic; - userInterruptB : out std_logic; - userInterruptC : out std_logic; - userInterruptD : out std_logic; - userInterruptE : out std_logic; - userInterruptF : out std_logic; - io_apbSlave_0_PADDR : out std_logic_vector(31 downto 0); - io_apbSlave_0_PENABLE : out std_logic; - io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0); - io_apbSlave_0_PREADY : in std_logic; - io_apbSlave_0_PSEL : out std_logic; - io_apbSlave_0_PSLVERROR : in std_logic; - io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0); - io_apbSlave_0_PWRITE : out std_logic; - system_i2c_0_io_sda_write : out std_logic; - system_i2c_0_io_sda_writeEnable : out std_logic; - system_i2c_0_io_scl_writeEnable : out std_logic; - system_watchdog_hardPanic_reset : out std_logic -); -end component EfxSapphireHpSoc_slb; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_EfxSapphireHpSoc_slb : EfxSapphireHpSoc_slb -port map ( - io_peripheralClk => io_peripheralClk, - io_peripheralReset => io_peripheralReset, - io_asyncReset => io_asyncReset, - io_gpio_sw_n => io_gpio_sw_n, - pll_peripheral_locked => pll_peripheral_locked, - pll_system_locked => pll_system_locked, - jtagCtrl_capture => jtagCtrl_capture, - jtagCtrl_enable => jtagCtrl_enable, - jtagCtrl_reset => jtagCtrl_reset, - jtagCtrl_shift => jtagCtrl_shift, - jtagCtrl_tdi => jtagCtrl_tdi, - jtagCtrl_tdo => jtagCtrl_tdo, - jtagCtrl_update => jtagCtrl_update, - ut_jtagCtrl_capture => ut_jtagCtrl_capture, - ut_jtagCtrl_enable => ut_jtagCtrl_enable, - ut_jtagCtrl_reset => ut_jtagCtrl_reset, - ut_jtagCtrl_shift => ut_jtagCtrl_shift, - ut_jtagCtrl_tdi => ut_jtagCtrl_tdi, - ut_jtagCtrl_tdo => ut_jtagCtrl_tdo, - ut_jtagCtrl_update => ut_jtagCtrl_update, - system_spi_0_io_data_0_read => system_spi_0_io_data_0_read, - system_spi_0_io_data_0_write => system_spi_0_io_data_0_write, - system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable, - system_spi_0_io_data_1_read => system_spi_0_io_data_1_read, - system_spi_0_io_data_1_write => system_spi_0_io_data_1_write, - system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable, - system_spi_0_io_data_2_read => system_spi_0_io_data_2_read, - system_spi_0_io_data_2_write => system_spi_0_io_data_2_write, - system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable, - system_spi_0_io_data_3_read => system_spi_0_io_data_3_read, - system_spi_0_io_data_3_write => system_spi_0_io_data_3_write, - system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable, - system_spi_0_io_sclk_write => system_spi_0_io_sclk_write, - system_spi_0_io_ss => system_spi_0_io_ss, - system_uart_0_io_rxd => system_uart_0_io_rxd, - system_uart_0_io_txd => system_uart_0_io_txd, - system_i2c_0_io_scl_read => system_i2c_0_io_scl_read, - system_i2c_0_io_scl_write => system_i2c_0_io_scl_write, - system_i2c_0_io_sda_read => system_i2c_0_io_sda_read, - system_gpio_0_io_read => system_gpio_0_io_read, - system_gpio_0_io_write => system_gpio_0_io_write, - system_gpio_0_io_writeEnable => system_gpio_0_io_writeEnable, - cfg_done => cfg_done, - cfg_start => cfg_start, - cfg_sel => cfg_sel, - cfg_reset => cfg_reset, - axiAInterrupt => axiAInterrupt, - axiA_awaddr => axiA_awaddr, - axiA_awlen => axiA_awlen, - axiA_awsize => axiA_awsize, - axiA_awburst => axiA_awburst, - axiA_awlock => axiA_awlock, - axiA_awcache => axiA_awcache, - axiA_awprot => axiA_awprot, - axiA_awqos => axiA_awqos, - axiA_awregion => axiA_awregion, - axiA_awvalid => axiA_awvalid, - axiA_awready => axiA_awready, - axiA_wdata => axiA_wdata, - axiA_wstrb => axiA_wstrb, - axiA_wvalid => axiA_wvalid, - axiA_wlast => axiA_wlast, - axiA_wready => axiA_wready, - axiA_bresp => axiA_bresp, - axiA_bvalid => axiA_bvalid, - axiA_bready => axiA_bready, - axiA_araddr => axiA_araddr, - axiA_arlen => axiA_arlen, - axiA_arsize => axiA_arsize, - axiA_arburst => axiA_arburst, - axiA_arlock => axiA_arlock, - axiA_arcache => axiA_arcache, - axiA_arprot => axiA_arprot, - axiA_arqos => axiA_arqos, - axiA_arregion => axiA_arregion, - axiA_arvalid => axiA_arvalid, - axiA_arready => axiA_arready, - axiA_rdata => axiA_rdata, - axiA_rresp => axiA_rresp, - axiA_rlast => axiA_rlast, - axiA_rvalid => axiA_rvalid, - axiA_rready => axiA_rready, - userInterruptA => userInterruptA, - userInterruptB => userInterruptB, - userInterruptC => userInterruptC, - userInterruptD => userInterruptD, - userInterruptE => userInterruptE, - userInterruptF => userInterruptF, - io_apbSlave_0_PADDR => io_apbSlave_0_PADDR, - io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE, - io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA, - io_apbSlave_0_PREADY => io_apbSlave_0_PREADY, - io_apbSlave_0_PSEL => io_apbSlave_0_PSEL, - io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR, - io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA, - io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE, - system_i2c_0_io_sda_write => system_i2c_0_io_sda_write, - system_i2c_0_io_sda_writeEnable => system_i2c_0_io_sda_writeEnable, - system_i2c_0_io_scl_writeEnable => system_i2c_0_io_scl_writeEnable, - system_watchdog_hardPanic_reset => system_watchdog_hardPanic_reset -); - ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v deleted file mode 100644 index dc09c96..0000000 --- a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v +++ /dev/null @@ -1,402 +0,0 @@ -module EfxSapphireHpSoc_wrapper ( -input cpu0_customInstruction_cmd_valid, -output cpu0_customInstruction_cmd_ready, -input [9:0] cpu0_customInstruction_function_id, -input [31:0] cpu0_customInstruction_inputs_0, -input [31:0] cpu0_customInstruction_inputs_1, -output cpu0_customInstruction_rsp_valid, -input cpu0_customInstruction_rsp_ready, -output [31:0] cpu0_customInstruction_outputs_0, -output userInterruptB, -output userInterruptE, -input cpu2_customInstruction_cmd_valid, -output cpu2_customInstruction_cmd_ready, -input [9:0] cpu2_customInstruction_function_id, -input [31:0] cpu2_customInstruction_inputs_0, -input [31:0] cpu2_customInstruction_inputs_1, -output cpu2_customInstruction_rsp_valid, -input cpu2_customInstruction_rsp_ready, -output [31:0] cpu2_customInstruction_outputs_0, -input io_cfuClk, -input io_cfuReset, -output system_spi_0_io_sclk_write, -output system_spi_0_io_data_0_writeEnable, -input system_spi_0_io_data_0_read, -output system_spi_0_io_data_0_write, -output system_spi_0_io_data_1_writeEnable, -input system_spi_0_io_data_1_read, -output system_spi_0_io_data_1_write, -output system_spi_0_io_data_2_writeEnable, -input system_spi_0_io_data_2_read, -output system_spi_0_io_data_2_write, -output system_spi_0_io_data_3_writeEnable, -input system_spi_0_io_data_3_read, -output system_spi_0_io_data_3_write, -output [3:0] system_spi_0_io_ss, -output userInterruptC, -output userInterruptH, -input cpu1_customInstruction_cmd_valid, -output cpu1_customInstruction_cmd_ready, -input [9:0] cpu1_customInstruction_function_id, -input [31:0] cpu1_customInstruction_inputs_0, -input [31:0] cpu1_customInstruction_inputs_1, -output cpu1_customInstruction_rsp_valid, -input cpu1_customInstruction_rsp_ready, -output [31:0] cpu1_customInstruction_outputs_0, -output jtagCtrl_tdi, -input jtagCtrl_tdo, -output jtagCtrl_enable, -output jtagCtrl_capture, -output jtagCtrl_shift, -output jtagCtrl_update, -output jtagCtrl_reset, -input ut_jtagCtrl_tdi, -output ut_jtagCtrl_tdo, -input ut_jtagCtrl_enable, -input ut_jtagCtrl_capture, -input ut_jtagCtrl_shift, -input ut_jtagCtrl_update, -input ut_jtagCtrl_reset, -output system_uart_0_io_txd, -input system_uart_0_io_rxd, -output io_ddrMasters_0_aw_valid, -input io_ddrMasters_0_aw_ready, -output [31:0] io_ddrMasters_0_aw_payload_addr, -output [3:0] io_ddrMasters_0_aw_payload_id, -output [3:0] io_ddrMasters_0_aw_payload_region, -output [7:0] io_ddrMasters_0_aw_payload_len, -output [2:0] io_ddrMasters_0_aw_payload_size, -output [1:0] io_ddrMasters_0_aw_payload_burst, -output io_ddrMasters_0_aw_payload_lock, -output [3:0] io_ddrMasters_0_aw_payload_cache, -output [3:0] io_ddrMasters_0_aw_payload_qos, -output [2:0] io_ddrMasters_0_aw_payload_prot, -output io_ddrMasters_0_aw_payload_allStrb, -output io_ddrMasters_0_w_valid, -input io_ddrMasters_0_w_ready, -output [127:0] io_ddrMasters_0_w_payload_data, -output [15:0] io_ddrMasters_0_w_payload_strb, -output io_ddrMasters_0_w_payload_last, -input io_ddrMasters_0_b_valid, -output io_ddrMasters_0_b_ready, -input [3:0] io_ddrMasters_0_b_payload_id, -input [1:0] io_ddrMasters_0_b_payload_resp, -output io_ddrMasters_0_ar_valid, -input io_ddrMasters_0_ar_ready, -output [31:0] io_ddrMasters_0_ar_payload_addr, -output [3:0] io_ddrMasters_0_ar_payload_id, -output [3:0] io_ddrMasters_0_ar_payload_region, -output [7:0] io_ddrMasters_0_ar_payload_len, -output [2:0] io_ddrMasters_0_ar_payload_size, -output [1:0] io_ddrMasters_0_ar_payload_burst, -output io_ddrMasters_0_ar_payload_lock, -output [3:0] io_ddrMasters_0_ar_payload_cache, -output [3:0] io_ddrMasters_0_ar_payload_qos, -output [2:0] io_ddrMasters_0_ar_payload_prot, -input io_ddrMasters_0_r_valid, -output io_ddrMasters_0_r_ready, -input [127:0] io_ddrMasters_0_r_payload_data, -input [3:0] io_ddrMasters_0_r_payload_id, -input [1:0] io_ddrMasters_0_r_payload_resp, -input io_ddrMasters_0_r_payload_last, -input io_ddrMasters_0_clk, -input io_ddrMasters_0_reset, -output userInterruptF, -output userInterruptG, -output userInterruptA, -output system_i2c_0_io_sda_writeEnable, -output system_i2c_0_io_sda_write, -input system_i2c_0_io_sda_read, -output system_i2c_0_io_scl_writeEnable, -output system_i2c_0_io_scl_write, -input system_i2c_0_io_scl_read, -input [3:0] system_gpio_0_io_read, -output [3:0] system_gpio_0_io_write, -output [3:0] system_gpio_0_io_writeEnable, -output system_watchdog_hardPanic_reset, -output userInterruptI, -input cpu3_customInstruction_cmd_valid, -output cpu3_customInstruction_cmd_ready, -input [9:0] cpu3_customInstruction_function_id, -input [31:0] cpu3_customInstruction_inputs_0, -input [31:0] cpu3_customInstruction_inputs_1, -output cpu3_customInstruction_rsp_valid, -input cpu3_customInstruction_rsp_ready, -output [31:0] cpu3_customInstruction_outputs_0, -output userInterruptD, -input [31:0] axiA_awaddr, -input [7:0] axiA_awlen, -input [2:0] axiA_awsize, -input [1:0] axiA_awburst, -input axiA_awlock, -input [3:0] axiA_awcache, -input [2:0] axiA_awprot, -input [3:0] axiA_awqos, -input [3:0] axiA_awregion, -input axiA_awvalid, -output axiA_awready, -input [31:0] axiA_wdata, -input [3:0] axiA_wstrb, -input axiA_wvalid, -input axiA_wlast, -output axiA_wready, -output [1:0] axiA_bresp, -output axiA_bvalid, -input axiA_bready, -input [31:0] axiA_araddr, -input [7:0] axiA_arlen, -input [2:0] axiA_arsize, -input [1:0] axiA_arburst, -input axiA_arlock, -input [3:0] axiA_arcache, -input [2:0] axiA_arprot, -input [3:0] axiA_arqos, -input [3:0] axiA_arregion, -input axiA_arvalid, -output axiA_arready, -output [31:0] axiA_rdata, -output [1:0] axiA_rresp, -output axiA_rlast, -output axiA_rvalid, -input axiA_rready, -output axiAInterrupt, -input cfg_done, -output cfg_start, -output cfg_sel, -output cfg_reset, -input io_peripheralClk, -input io_peripheralReset, -output io_asyncReset, -input io_gpio_sw_n, -input pll_peripheral_locked, -input pll_system_locked -); - -wire [15:0] io_apbSlave_0_PADDR; -wire io_apbSlave_0_PSEL; -wire io_apbSlave_0_PENABLE; -wire io_apbSlave_0_PREADY; -wire io_apbSlave_0_PWRITE; -wire [31:0] io_apbSlave_0_PWDATA; -wire [31:0] io_apbSlave_0_PRDATA; -wire io_apbSlave_0_PSLVERROR; - - -assign userInterruptG = 1'b0; //USER TO MODIFY -assign userInterruptH = 1'b0; //USER TO MODIFY -assign userInterruptI = 1'b0; //USER TO MODIFY - -/**/ -/* INFO: USER TO MODIFY CODES BELOW */ -/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ -/**/ -assign cpu3_customInstruction_cmd_ready = 1'b1; -assign cpu3_customInstruction_rsp_valid = 1'b0; -assign cpu3_customInstruction_outputs_0 = 32'd0; -//io_cfuClk -//io_cfyReset -//cpu3_customInstruction_rsp_ready -//cpu3_customInstruction_cmd_valid -//cpu3_customInstruction_function_id -//cpu3_customInstruction_inputs_0 -//cpu3_customInstruction_inputs_1 - -/**/ -/* INFO: USER TO MODIFY CODES BELOW */ -/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ -/**/ -assign cpu0_customInstruction_cmd_ready = 1'b1; -assign cpu0_customInstruction_rsp_valid = 1'b0; -assign cpu0_customInstruction_outputs_0 = 32'd0; -//io_cfuClk -//io_cfyReset -//cpu0_customInstruction_rsp_ready -//cpu0_customInstruction_cmd_valid -//cpu0_customInstruction_function_id -//cpu0_customInstruction_inputs_0 -//cpu0_customInstruction_inputs_1 - -/**/ -/* INFO: USER TO MODIFY CODES BELOW */ -/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ -/**/ -assign cpu1_customInstruction_cmd_ready = 1'b1; -assign cpu1_customInstruction_rsp_valid = 1'b0; -assign cpu1_customInstruction_outputs_0 = 32'd0; -//io_cfuClk -//io_cfyReset -//cpu1_customInstruction_rsp_ready -//cpu1_customInstruction_cmd_valid -//cpu1_customInstruction_function_id -//cpu1_customInstruction_inputs_0 -//cpu1_customInstruction_inputs_1 - -/**/ -/* INFO: USER TO MODIFY CODES BELOW */ -/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ -/**/ -assign io_apbSlave_0_PREADY = 1'b1; -assign io_apbSlave_0_PRDATA = 32'd0; -//io_apbSlave_0_PADDR; -//io_apbSlave_0_PSEL; -//io_apbSlave_0_PENABLE; -//io_apbSlave_0_PWRITE; -//io_apbSlave_0_PWDATA; -//io_apbSlave_0_PSLVERROR; -/**/ -/* INFO: USER TO MODIFY CODES BELOW */ -/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ -/**/ -assign cpu2_customInstruction_cmd_ready = 1'b1; -assign cpu2_customInstruction_rsp_valid = 1'b0; -assign cpu2_customInstruction_outputs_0 = 32'd0; -//io_cfuClk -//io_cfyReset -//cpu2_customInstruction_rsp_ready -//cpu2_customInstruction_cmd_valid -//cpu2_customInstruction_function_id -//cpu2_customInstruction_inputs_0 -//cpu2_customInstruction_inputs_1 - -/**/ -/* INFO: USER TO MODIFY CODES BELOW */ -/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ -/**/ -assign io_ddrMasters_0_aw_payload_addr = 32'd0; -assign io_ddrMasters_0_aw_payload_id = 4'd0; -assign io_ddrMasters_0_aw_payload_region = 4'd0; -assign io_ddrMasters_0_aw_payload_len = 8'd0; -assign io_ddrMasters_0_aw_payload_size = 3'd0; -assign io_ddrMasters_0_aw_payload_burst = 2'd0; -assign io_ddrMasters_0_aw_payload_lock = 1'b0; -assign io_ddrMasters_0_aw_payload_cache = 4'd0; -assign io_ddrMasters_0_aw_payload_qos = 4'd0; -assign io_ddrMasters_0_aw_payload_prot = 3'd0; -assign io_ddrMasters_0_aw_payload_allStrb = 1'b0; -assign io_ddrMasters_0_w_valid = 1'b0; -//io_ddrMasters_0_w_ready -assign io_ddrMasters_0_w_payload_data = 128'd0; -assign io_ddrMasters_0_w_payload_strb = 16'd0; -assign io_ddrMasters_0_w_payload_last = 1'b0; -//io_ddrMasters_0_b_valid -assign io_ddrMasters_0_b_ready = 1'b1; -//io_ddrMasters_0_b_payload_id -//io_ddrMasters_0_b_payload_resp -assign io_ddrMasters_0_ar_valid = 1'b0; -//io_ddrMasters_0_ar_ready -assign io_ddrMasters_0_ar_payload_addr = 32'd0; -assign io_ddrMasters_0_ar_payload_id = 4'd0; -assign io_ddrMasters_0_ar_payload_region = 4'd0; -assign io_ddrMasters_0_ar_payload_len = 8'd0; -assign io_ddrMasters_0_ar_payload_size = 3'd0; -assign io_ddrMasters_0_ar_payload_burst = 2'd0; -assign io_ddrMasters_0_ar_payload_lock = 1'b0; -assign io_ddrMasters_0_ar_payload_cache = 4'd0; -assign io_ddrMasters_0_ar_payload_qos = 4'd0; -assign io_ddrMasters_0_ar_payload_pro = 3'd0; -//io_ddrMasters_0_r_valid -assign io_ddrMasters_0_r_ready = 1'b1; -//io_ddrMasters_0_r_payload_data -//io_ddrMasters_0_r_payload_id -//io_ddrMasters_0_r_payload_resp -//io_ddrMasters_0_r_payload_last - - - -//axi4 bridge to various I/O -EfxSapphireHpSoc_slb u_top_peripherals( -.userInterruptD(userInterruptD), -.userInterruptA(userInterruptA), -.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset), -.system_uart_0_io_txd(system_uart_0_io_txd), -.system_uart_0_io_rxd(system_uart_0_io_rxd), -.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write), -.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable), -.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read), -.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write), -.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable), -.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read), -.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write), -.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable), -.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read), -.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write), -.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable), -.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read), -.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write), -.system_spi_0_io_ss(system_spi_0_io_ss), -.system_gpio_0_io_read(system_gpio_0_io_read), -.system_gpio_0_io_write(system_gpio_0_io_write), -.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable), -.userInterruptB(userInterruptB), -.userInterruptE(userInterruptE), -.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR), -.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL), -.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE), -.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY), -.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE), -.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA), -.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA), -.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR), -.system_i2c_0_io_sda_writeEnable(system_i2c_0_io_sda_writeEnable), -.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write), -.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read), -.system_i2c_0_io_scl_writeEnable(system_i2c_0_io_scl_writeEnable), -.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write), -.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read), -.userInterruptF(userInterruptF), -.jtagCtrl_tdi(jtagCtrl_tdi), -.jtagCtrl_tdo(jtagCtrl_tdo), -.jtagCtrl_enable(jtagCtrl_enable), -.jtagCtrl_capture(jtagCtrl_capture), -.jtagCtrl_shift(jtagCtrl_shift), -.jtagCtrl_update(jtagCtrl_update), -.jtagCtrl_reset(jtagCtrl_reset), -.ut_jtagCtrl_tdi(ut_jtagCtrl_tdi), -.ut_jtagCtrl_tdo(ut_jtagCtrl_tdo), -.ut_jtagCtrl_enable(ut_jtagCtrl_enable), -.ut_jtagCtrl_capture(ut_jtagCtrl_capture), -.ut_jtagCtrl_shift(ut_jtagCtrl_shift), -.ut_jtagCtrl_update(ut_jtagCtrl_update), -.ut_jtagCtrl_reset(ut_jtagCtrl_reset), -.userInterruptC(userInterruptC), -.axiA_awvalid(axiA_awvalid), -.axiA_awready(axiA_awready), -.axiA_awaddr(axiA_awaddr), -.axiA_awlen(axiA_awlen), -.axiA_awsize(axiA_awsize), -.axiA_awcache(axiA_awcache), -.axiA_awprot(axiA_awprot), -.axiA_wvalid(axiA_wvalid), -.axiA_wready(axiA_wready), -.axiA_wdata(axiA_wdata), -.axiA_wstrb(axiA_wstrb), -.axiA_wlast(axiA_wlast), -.axiA_bvalid(axiA_bvalid), -.axiA_bready(axiA_bready), -.axiA_bresp(axiA_bresp), -.axiA_arvalid(axiA_arvalid), -.axiA_arready(axiA_arready), -.axiA_araddr(axiA_araddr), -.axiA_arlen(axiA_arlen), -.axiA_arsize(axiA_arsize), -.axiA_arcache(axiA_arcache), -.axiA_arprot(axiA_arprot), -.axiA_rvalid(axiA_rvalid), -.axiA_rready(axiA_rready), -.axiA_rdata(axiA_rdata), -.axiA_rresp(axiA_rresp), -.axiA_rlast(axiA_rlast), -.axiAInterrupt(axiAInterrupt), -.cfg_done(cfg_done), -.cfg_start(cfg_start), -.cfg_sel(cfg_sel), -.cfg_reset(cfg_reset), -.io_peripheralClk(io_peripheralClk), -.io_peripheralReset(io_peripheralReset), -.io_asyncReset(io_asyncReset), -.io_gpio_sw_n(io_gpio_sw_n), -.pll_peripheral_locked(pll_peripheral_locked), -.pll_system_locked(pll_system_locked) -); - -endmodule diff --git a/fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini b/fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini deleted file mode 100644 index 5536035..0000000 --- a/fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini +++ /dev/null @@ -1,224 +0,0 @@ -[parameters] -pll_soc_sys_clk_name = soc_pll_sys_clk -hidden_min_freq = 0 -pll_soc_sys_clk_ref_freq_hidden = 100 -pll_soc_sys_clk_ref_freq = 100 -pll_soc_sys_clkout1_freq = 1000 -pll_soc_sys_clkout1_phase = 0 -pll_soc_sys_clkout2_freq = 250 -pll_soc_sys_clkout2_phase = 0 -pll_soc_mem_clk_name = soc_pll_peri_clk -pll_soc_mem_clk_ref_freq = 25 -pll_soc_mem_clkout1_freq = 250 -pll_soc_mem_clkout1_phase = 0 -pll_soc_mem_clkout2_freq = 250 -pll_soc_mem_clkout2_phase = 0 -pll_lpddr4_name = soc_ddr_pll -pll_lpddr4_ref_freq = 25 -pll_lpddr4_clkout0_freq = 100 -pll_lpddr4_clkout0_phase = 0 -pll_lpddr4_clkout3_freq = 533 -pll_lpddr4_clkout3_phase = 0 -ddr_data_width = 32 -ddr_memory_density = 8G -ddr_memory_type = LPDDR4x -ddr_physical_rank = 1 -ddr_pin_name = soc_ddr_inst1 -gpio_bus_name = system_gpio_0 -hard_jtag_inst_name = soc_jtag_inst1 -uart0_gpio_inst_name = system_uart_0 -spi0_gpio_inst_name = system_spi_0 -i2c0_gpio_inst_name = system_i2c_0 -jtag_gpio_inst_name = io_jtag -soc_pin_name = qcrv32_inst1 -intf_axim = 1 -intf_ci_0 = 1 -intf_ci_1 = 1 -intf_ci_2 = 1 -intf_ci_3 = 1 -co_debug = 0 -intf_jtag_type = 0 -intf_uintr = 9 -peri_spi_0 = 1 -peri_spi_1 = 0 -peri_spi_2 = 0 -peri_i2c_0 = 1 -peri_i2c_1 = 0 -peri_i2c_2 = 0 -peri_gpio_0 = 1 -peri_gpio_1 = 0 -peri_wdt_0 = 1 -peri_apb_0 = 1 -peri_apb_1 = 0 -peri_apb_2 = 0 -peri_apb_3 = 0 -peri_apb_4 = 0 -peri_gen = 1 -peri_uart_0 = 1 -peri_uart_1 = 0 -peri_uart_2 = 0 -peri_gpio_0_width = 4 -peri_gpio_1_width = 4 -peri_apb_0_size = 65536 -peri_apb_1_size = 4096 -peri_apb_2_size = 4096 -peri_apb_3_size = 4096 -peri_apb_4_size = 4096 -peri_freq = 200 -app_overwrite = 0 -app_overwrite_path = -peri_count = 6 -peri_tcount = 6 -intf_jtag_tap_sel = 8 -intf_axis = 1 -peri_pin_assign = 1 -pll_soc_mem_resource = PLL_TR0 -sys_freq = 1000 -sys_freq_hidden = 1000 -pll_soc_sys_clkout3_freq = 250 -pll_soc_sys_clkout3_phase = 0 -pll_soc_mem_clkout3_freq = 250 -pll_soc_mem_clkout3_phase = 0 -pll_soc_mem_clkout4_freq = 200 -pll_soc_mem_clkout4_phase = 0 -pll_soc_sys_resource = PLL_BL0 -pll_lpddr4_resource = PLL_BL2 -pll_res_assign = 0 -pll_soc_sys_clkout0_freq = 100 -pll_soc_sys_clkout0_phase = 0 -pll_soc_mem_clkout0_freq = 100 -pll_soc_mem_clkout0_phase = 0 -pll_lpddr4_clkout1_freq = 33 -pll_lpddr4_clkout1_phase = 0 -mem_freq = 250 -axim_freq = 250 -cfu_freq = 125 -ddr_freq = 800 -pll_res_assign_2 = 0 -ddr_res_assign = 0 -peri_res_assign = 0 -pll_soc_sys_ext_clk_src = 1 -pll_soc_mem_ext_clk_src = 0 -peri_sdhc = 0 -peri_tsemac = 0 -sw_ftdi_ch_num = 6011 -sw_app_size = 2044 -sw_app_size_custom = 0 -sw_stack_size = 8 -sw_stack_size_custom = 0 -sw_board = Ti375C529 Development Kit -sw_board_custom = -sw_ftdi_target_ch = 1 -sw_ftdi_ch_num_soft = 6011 -sw_ftdi_target_ch_soft = 0 -sw_frtos_app_size = 16380 -sw_frtos_app_size_custom = 0 -sw_frtos_stack_size = 4 -sw_frtos_stack_size_custom = 0 -package_type = 529 -family_type = TITANIUM -axi_pipeline = 0 -axi_write_buffer = 0 - -[ports] -io_peripheralclk = io_peripheralClk -io_peripheralreset = io_peripheralReset -io_asyncreset = io_asyncReset -io_gpio_sw_n = io_gpio_sw_n -pll_peripheral_locked = pll_peripheral_locked -pll_system_locked = pll_system_locked -jtagctrl_capture = jtagCtrl_capture -jtagctrl_enable = jtagCtrl_enable -jtagctrl_reset = jtagCtrl_reset -jtagctrl_shift = jtagCtrl_shift -jtagctrl_tdi = jtagCtrl_tdi -jtagctrl_tdo = jtagCtrl_tdo -jtagctrl_update = jtagCtrl_update -ut_jtagctrl_capture = ut_jtagCtrl_capture -ut_jtagctrl_enable = ut_jtagCtrl_enable -ut_jtagctrl_reset = ut_jtagCtrl_reset -ut_jtagctrl_shift = ut_jtagCtrl_shift -ut_jtagctrl_tdi = ut_jtagCtrl_tdi -ut_jtagctrl_tdo = ut_jtagCtrl_tdo -ut_jtagctrl_update = ut_jtagCtrl_update -system_spi_0_io_data_0_read = system_spi_0_io_data_0_read -system_spi_0_io_data_0_write = system_spi_0_io_data_0_write -system_spi_0_io_data_0_writeenable = system_spi_0_io_data_0_writeEnable -system_spi_0_io_data_1_read = system_spi_0_io_data_1_read -system_spi_0_io_data_1_write = system_spi_0_io_data_1_write -system_spi_0_io_data_1_writeenable = system_spi_0_io_data_1_writeEnable -system_spi_0_io_data_2_read = system_spi_0_io_data_2_read -system_spi_0_io_data_2_write = system_spi_0_io_data_2_write -system_spi_0_io_data_2_writeenable = system_spi_0_io_data_2_writeEnable -system_spi_0_io_data_3_read = system_spi_0_io_data_3_read -system_spi_0_io_data_3_write = system_spi_0_io_data_3_write -system_spi_0_io_data_3_writeenable = system_spi_0_io_data_3_writeEnable -system_spi_0_io_sclk_write = system_spi_0_io_sclk_write -system_spi_0_io_ss = system_spi_0_io_ss -system_uart_0_io_rxd = system_uart_0_io_rxd -system_uart_0_io_txd = system_uart_0_io_txd -system_i2c_0_io_scl_read = system_i2c_0_io_scl_read -system_i2c_0_io_scl_write = system_i2c_0_io_scl_write -system_i2c_0_io_sda_read = system_i2c_0_io_sda_read -system_gpio_0_io_read = system_gpio_0_io_read -system_gpio_0_io_write = system_gpio_0_io_write -system_gpio_0_io_writeenable = system_gpio_0_io_writeEnable -cfg_done = cfg_done -cfg_start = cfg_start -cfg_sel = cfg_sel -cfg_reset = cfg_reset -axiainterrupt = axiAInterrupt -axia_awaddr = axiA_awaddr -axia_awlen = axiA_awlen -axia_awsize = axiA_awsize -axia_awburst = axiA_awburst -axia_awlock = axiA_awlock -axia_awcache = axiA_awcache -axia_awprot = axiA_awprot -axia_awqos = axiA_awqos -axia_awregion = axiA_awregion -axia_awvalid = axiA_awvalid -axia_awready = axiA_awready -axia_wdata = axiA_wdata -axia_wstrb = axiA_wstrb -axia_wvalid = axiA_wvalid -axia_wlast = axiA_wlast -axia_wready = axiA_wready -axia_bresp = axiA_bresp -axia_bvalid = axiA_bvalid -axia_bready = axiA_bready -axia_araddr = axiA_araddr -axia_arlen = axiA_arlen -axia_arsize = axiA_arsize -axia_arburst = axiA_arburst -axia_arlock = axiA_arlock -axia_arcache = axiA_arcache -axia_arprot = axiA_arprot -axia_arqos = axiA_arqos -axia_arregion = axiA_arregion -axia_arvalid = axiA_arvalid -axia_arready = axiA_arready -axia_rdata = axiA_rdata -axia_rresp = axiA_rresp -axia_rlast = axiA_rlast -axia_rvalid = axiA_rvalid -axia_rready = axiA_rready -userinterrupta = userInterruptA -userinterruptb = userInterruptB -userinterruptc = userInterruptC -userinterruptd = userInterruptD -userinterrupte = userInterruptE -userinterruptf = userInterruptF -io_apbslave_0_paddr = io_apbSlave_0_PADDR -io_apbslave_0_penable = io_apbSlave_0_PENABLE -io_apbslave_0_prdata = io_apbSlave_0_PRDATA -io_apbslave_0_pready = io_apbSlave_0_PREADY -io_apbslave_0_psel = io_apbSlave_0_PSEL -io_apbslave_0_pslverror = io_apbSlave_0_PSLVERROR -io_apbslave_0_pwdata = io_apbSlave_0_PWDATA -io_apbslave_0_pwrite = io_apbSlave_0_PWRITE -system_i2c_0_io_sda_write = system_i2c_0_io_sda_write -system_i2c_0_io_sda_writeenable = system_i2c_0_io_sda_writeEnable -system_i2c_0_io_scl_writeenable = system_i2c_0_io_scl_writeEnable -system_watchdog_hardpanic_reset = system_watchdog_hardPanic_reset - diff --git a/fpga/ip/EfxSapphireHpSoc_slb/ipm/component.pickle b/fpga/ip/EfxSapphireHpSoc_slb/ipm/component.pickle deleted file mode 100644 index f8b5aad42d4be657ffc5bf4fd3b766b226db5239..0000000000000000000000000000000000000000 GIT binary patch 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3( zEFRTZ)EA3I1hXQBQ)DVwu5oH0PU}n-D>N2yVzGr_c9@)2YMdI0(_WLsD;kUQ#Nsf) zRO#%0UPgLmwZ^H5IMp#(tkGD+i$z1Ra9Rq&UruNJ3st`+r&XwqYv@NV4f2Cug=tTl zuA#lhuEqALX7|lx_gO}d&ov$`#3Pq*t`-;%Ax;kATH4%d-2HaV?k|wtml{2GXgpep z$K!;vSYSMaMsf(NXtUn9`<S>)6O zjX*1K3CIw*mS&2sJu*_dW1wC%N<>3390w+YJM=BDmX;6dMPo%Y55wodYVfYU<-erm z$9hqbh`z>fANUJY?;7mCn4J@lmUZ=_@gh1`M9ziaV$e>;!xDEvHG#!+O!JBC4uhf2h1a6~uuS zf|!GOyR>Yl7u_kME*NHl9571X@-AsPK`**nMAI;wq1Vn3?QFg1J`pX#aD`rbzi8L# zMGuN-3x+$uUhuoV<-^jlN{04~nkAxBMdX|VT7VRN%SWYUx?VI}M41>4(Q6+U?P$H| z2@y@iaGG8_U$pn>MGHhU2g5~r?bD)NsTVyXqV*VV0bhVU`j(5OpK zRa&moi(V7a77TZQJ>ZbOC?F|vt7Ln5cGzZE0mTyVR&U(>$5%tCJO1<_S z(T>uKHi&2fhEu@|@Tk7!`_giuUi5*8Uc&GVunBC_xBO6A?$(R8i0B}O6?@1zb22zf z5cAaex3rAci#`@n8w^uHFECi&@>6L!Trc`uM8z0R(QCJhcDi1)LqxMMT%gzP6zwv- z=qnMe#c(6o26pLNej_ap=tbX&sA5kUx0AqGps66{@a>kCt@WZGM3jnQPrY`pXfM}` zeiG3L42$*JpGA9b_%acv8&o|+m5JpL zgSeN7M;laqL^To1X$Enoi0?C~vP3lp%S8t901>Y=s0N8@J(gPx;=v-`X;57usvogD zY!D9-akbv^K^rqKt`gO0qH-D<#CamV(4ZPBs*ADgW)Ke(@c@HrgsAed9BU9eBEH_B z8ZD|juzbKE9wXv;2GuxGy@2Jb263T?HyBjKqWT2OuMOgBM7-ainjosbv8>TYpB|G$ ze5OHlov50K%1JbcCyThFK{Z8GJ+aI-h;I_{aD!^9sEViQ+yvAvOI9+YBXr{3kBo>nh z<`z&2=9qk2XnY5Y?_!h11saPh#9}4EtTQ>a(l`wfr>!Q7M2*E&VzHB8_JTh^)qcSo zFQ43zH*1$@eDlP&j>+Oujm1#0Xebs=OOsQo#%Y*1wKrL$X)H#FMK^-U0(oGJ$v0i& z>xl2QCX22bi_v0n8^M&CoH8^{W5j8$$)dZ)Vw_k!M=+~QPCYeFh2r#%$)dN$qF5|G zBA72tPJJ~_*ND?TlSMy`#RReVi(sl}$>+!E;9P;`OzW@log}`kOcnz*7T1ZzB?OaU za>~{?O%|ttCX3587E{DxD8Y;alffM^d?R0b8K&{QNqiqPS&YzFOcjfH1oOPf$Xa+A|58mD#Q z^rp#TwZ`IYvG|Z+wu2wQZzkV08sB%txALH1o|aF^NLR1bSiC0|r-+4fw#n&DjnhVP zYHqSvr?J>17AXYN+2r)L#%Z%SWtuGB)mUs5iyVR(Wpa8?DEUp856)>v#4i**FE+2piUN1k zk83RUiN);%bHB;y360Z!aeBgJF<)cx zt5`fwFt3=L7HFIfiqpF$i>Eafhs5Gzg83?jQ{>IibsDF`;`Fo0VzS2KPq8>cFeeQ5 zKQAM}Owl+U5vMau7B^`uDhvt!NV2h5I0+`FsT!w>;&iFW;ueiXWwGc%FoS%Y26oOW zdx2L~GksPOr(q_G>Kcn`Vo@X(fs)!eIb#Zn$B!)>H6bTIH-AJyPEM)%hW_zm#ttng zDlMrW-grU&=-i^Bf}#rw3&xEtEWT!B!FaW~S}!FVp#Ht|zS8q=3^uHiL(37>it~fla)uYHx0^M3 z2a40xe@C~7SGyiwm^*Gn>4-`t)pBx&Izvb17t=nFS5kfCn4F;n!wU-vLLN0U#&nkd zc9}R6mH&uJPVg-TacVEtX)Dvo7`4y+O%$!pO-XrXq%*hyoA>> 1'd1); - assign _zz_bridge_addressFilter_hits_1 = (bridge_addressFilter_byte0 >>> 1'd1); - assign _zz_bridge_masterLogic_start = 1'b1; - assign _zz_bridge_masterLogic_stop = 1'b1; - assign _zz_bridge_masterLogic_drop = 1'b1; - assign _zz_bridge_masterLogic_recover = 1'b1; - assign _zz_bridge_masterLogic_timer_value_1 = (! bridge_masterLogic_timer_done); - assign _zz_bridge_masterLogic_timer_value = {11'd0, _zz_bridge_masterLogic_timer_value_1}; - assign _zz_bridge_masterLogic_fsm_dropped_start = 1'b0; - assign _zz_bridge_masterLogic_fsm_dropped_stop = 1'b0; - assign _zz_bridge_masterLogic_fsm_dropped_recover = 1'b0; - assign _zz_io_bus_rsp_data = (3'b111 - bridge_dataCounter); - assign _zz_bridge_rxData_value = (3'b111 - bridge_dataCounter); - assign _zz_bridge_interruptCtrl_start_flag = 1'b0; - assign _zz_bridge_interruptCtrl_restart_flag = 1'b0; - assign _zz_bridge_interruptCtrl_end_flag = 1'b0; - assign _zz_bridge_interruptCtrl_drop_flag = 1'b0; - assign _zz_bridge_interruptCtrl_filterGen_flag = 1'b0; - assign _zz_bridge_interruptCtrl_clockGenExit_flag = 1'b0; - assign _zz_bridge_interruptCtrl_clockGenEnter_flag = 1'b0; - Axi4PeripheralI2cSlave i2cCtrl ( - .io_i2c_sda_write (i2cCtrl_io_i2c_sda_write ), //o - .io_i2c_sda_read (bridge_i2cBuffer_sda_read ), //i - .io_i2c_scl_write (i2cCtrl_io_i2c_scl_write ), //o - .io_i2c_scl_read (bridge_i2cBuffer_scl_read ), //i - .io_config_samplingClockDivider (_zz_io_config_samplingClockDivider[9:0]), //i - .io_config_timeout (_zz_io_config_timeout[19:0] ), //i - .io_config_tsuData (_zz_io_config_tsuData[5:0] ), //i - .io_config_timeoutClear (i2cCtrl_io_config_timeoutClear ), //i - .io_bus_cmd_kind (i2cCtrl_io_bus_cmd_kind[2:0] ), //o - .io_bus_cmd_data (i2cCtrl_io_bus_cmd_data ), //o - .io_bus_rsp_valid (i2cCtrl_io_bus_rsp_valid ), //i - .io_bus_rsp_enable (i2cCtrl_io_bus_rsp_enable ), //i - .io_bus_rsp_data (i2cCtrl_io_bus_rsp_data ), //i - .io_timeout (i2cCtrl_io_timeout ), //o - .io_internals_inFrame (i2cCtrl_io_internals_inFrame ), //o - .io_internals_sdaRead (i2cCtrl_io_internals_sdaRead ), //o - .io_internals_sclRead (i2cCtrl_io_internals_sclRead ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - initial begin - `ifndef SYNTHESIS - _zz_io_config_timeout = {$urandom}; - _zz_io_config_tsuData = {$urandom}; - `endif - end - - `ifndef SYNTHESIS - always @(*) begin - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateReg_string = "BOOT "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateReg_string = "IDLE "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateReg_string = "START1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateReg_string = "START2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateReg_string = "START3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateReg_string = "LOW "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateReg_string = "HIGH "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateReg_string = "RESTART"; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateReg_string = "STOP1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateReg_string = "STOP2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateReg_string = "STOP3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateReg_string = "TBUF "; - default : bridge_masterLogic_fsm_stateReg_string = "???????"; - endcase - end - always @(*) begin - case(bridge_masterLogic_fsm_stateNext) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateNext_string = "BOOT "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateNext_string = "IDLE "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateNext_string = "START1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateNext_string = "START2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateNext_string = "START3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateNext_string = "LOW "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateNext_string = "HIGH "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateNext_string = "RESTART"; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateNext_string = "STOP1 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateNext_string = "STOP2 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateNext_string = "STOP3 "; - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateNext_string = "TBUF "; - default : bridge_masterLogic_fsm_stateNext_string = "???????"; - endcase - end - `endif - - assign busCtrl_readErrorFlag = 1'b0; - assign busCtrl_writeErrorFlag = 1'b0; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); - always @(*) begin - _zz_busCtrl_rsp_ready_1 = io_ctrl_rsp_ready; - if(when_Stream_l375) begin - _zz_busCtrl_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); - assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign busCtrl_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - busCtrl_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h08 : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxData_valid; - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_rxData_value; - end - 8'h0c : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxAck_valid; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_rxAck_value; - end - 8'h0 : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txData_valid; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txData_enable; - end - 8'h04 : begin - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txAck_valid; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txAck_enable; - end - 8'h80 : begin - busCtrl_rsp_payload_fragment_data[1 : 0] = {bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}; - end - 8'h84 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_addressFilter_byte0[0]; - end - 8'h40 : begin - busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_masterLogic_start; - busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_masterLogic_stop; - busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_masterLogic_drop; - busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_masterLogic_recover; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_masterLogic_fsm_isBusy; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_masterLogic_fsm_dropped_start; - busCtrl_rsp_payload_fragment_data[10 : 10] = bridge_masterLogic_fsm_dropped_stop; - busCtrl_rsp_payload_fragment_data[11 : 11] = bridge_masterLogic_fsm_dropped_recover; - end - 8'h20 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_rxDataEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_rxAckEnable; - busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_interruptCtrl_txDataEnable; - busCtrl_rsp_payload_fragment_data[3 : 3] = bridge_interruptCtrl_txAckEnable; - busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_enable; - busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_enable; - busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_enable; - busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_enable; - busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_enable; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_enable; - busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_enable; - end - 8'h24 : begin - busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_flag; - busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_flag; - busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_flag; - busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_flag; - busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_flag; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_flag; - busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_flag; - end - 8'h44 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = i2cCtrl_io_internals_inFrame; - busCtrl_rsp_payload_fragment_data[1 : 1] = i2cCtrl_io_internals_sdaRead; - busCtrl_rsp_payload_fragment_data[2 : 2] = i2cCtrl_io_internals_sclRead; - end - 8'h48 : begin - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_slaveOverride_sda; - busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_slaveOverride_scl; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - assign bridge_busCtrlWithOffset_readErrorFlag = 1'b0; - assign bridge_busCtrlWithOffset_writeErrorFlag = 1'b0; - always @(*) begin - bridge_frameReset = 1'b0; - case(i2cCtrl_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_START : begin - bridge_frameReset = 1'b1; - end - Axi4PeripheralI2cSlaveCmdMode_RESTART : begin - bridge_frameReset = 1'b1; - end - Axi4PeripheralI2cSlaveCmdMode_STOP : begin - bridge_frameReset = 1'b1; - end - Axi4PeripheralI2cSlaveCmdMode_DROP : begin - bridge_frameReset = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - bridge_i2cBuffer_sda_write = i2cCtrl_io_i2c_sda_write; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - bridge_i2cBuffer_sda_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_I2cCtrl_l673) begin - bridge_i2cBuffer_sda_write = 1'b0; - end - end - - always @(*) begin - bridge_i2cBuffer_scl_write = i2cCtrl_io_i2c_scl_write; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - bridge_i2cBuffer_scl_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - if(bridge_masterLogic_timer_done) begin - if(when_I2cCtrl_l418) begin - bridge_i2cBuffer_scl_write = 1'b0; - end else begin - if(when_I2cCtrl_l422) begin - bridge_i2cBuffer_scl_write = 1'b0; - end - end - end else begin - bridge_i2cBuffer_scl_write = 1'b0; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - bridge_i2cBuffer_scl_write = 1'b0; - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_I2cCtrl_l674) begin - bridge_i2cBuffer_scl_write = 1'b0; - end - end - - always @(*) begin - when_I2cCtrl_l224 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h08 : begin - if(busCtrl_doRead) begin - when_I2cCtrl_l224 = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - when_I2cCtrl_l237 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h0c : begin - if(busCtrl_doRead) begin - when_I2cCtrl_l237 = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - bridge_txData_forceDisable = 1'b0; - if(when_I2cCtrl_l601) begin - bridge_txData_forceDisable = 1'b0; - end - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - if(bridge_masterLogic_timer_done) begin - if(when_I2cCtrl_l418) begin - bridge_txData_forceDisable = 1'b1; - end else begin - if(when_I2cCtrl_l422) begin - bridge_txData_forceDisable = 1'b1; - end - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - end - - always @(*) begin - bridge_txAck_forceAck = 1'b0; - if(when_I2cCtrl_l306) begin - bridge_txAck_forceAck = 1'b1; - end - end - - assign bridge_addressFilter_byte0Is10Bit = (bridge_addressFilter_byte0[7 : 3] == 5'h1e); - assign bridge_addressFilter_hits_0 = (bridge_addressFilter_addresses_0_enable && ((! bridge_addressFilter_addresses_0_is10Bit) ? ((_zz_bridge_addressFilter_hits_0 == bridge_addressFilter_addresses_0_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_0_value) && (bridge_addressFilter_state == 2'b10)))); - assign bridge_addressFilter_hits_1 = (bridge_addressFilter_addresses_1_enable && ((! bridge_addressFilter_addresses_1_is10Bit) ? ((_zz_bridge_addressFilter_hits_1 == bridge_addressFilter_addresses_1_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_1_value) && (bridge_addressFilter_state == 2'b10)))); - assign when_I2cCtrl_l306 = ((bridge_addressFilter_byte0Is10Bit && (bridge_addressFilter_state == 2'b01)) && (|{((bridge_addressFilter_addresses_1_enable && bridge_addressFilter_addresses_1_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_1_value[9 : 8])),((bridge_addressFilter_addresses_0_enable && bridge_addressFilter_addresses_0_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_0_value[9 : 8]))})); - assign _zz_when_I2cCtrl_l310 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); - assign when_I2cCtrl_l310 = (_zz_when_I2cCtrl_l310 && (! _zz_when_I2cCtrl_l310_1)); - always @(*) begin - when_BusSlaveFactory_l377 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379 = io_ctrl_cmd_payload_fragment_data[4]; - always @(*) begin - when_BusSlaveFactory_l377_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_1 = io_ctrl_cmd_payload_fragment_data[5]; - always @(*) begin - when_BusSlaveFactory_l377_2 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_2 = io_ctrl_cmd_payload_fragment_data[6]; - always @(*) begin - when_BusSlaveFactory_l377_3 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_3 = io_ctrl_cmd_payload_fragment_data[7]; - assign bridge_masterLogic_timer_done = (bridge_masterLogic_timer_value == 12'h0); - assign bridge_masterLogic_fsm_wantExit = 1'b0; - always @(*) begin - bridge_masterLogic_fsm_wantStart = 1'b0; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - bridge_masterLogic_fsm_wantStart = 1'b1; - end - endcase - end - - assign bridge_masterLogic_fsm_wantKill = 1'b0; - always @(*) begin - bridge_masterLogic_fsm_dropped_trigger = 1'b0; - if(when_I2cCtrl_l350) begin - bridge_masterLogic_fsm_dropped_trigger = 1'b1; - end - end - - assign when_I2cCtrl_l363 = (! i2cCtrl_io_internals_sclRead); - assign when_I2cCtrl_l363_1 = (! i2cCtrl_io_internals_inFrame); - assign bridge_masterLogic_fsm_outOfSync = ((! i2cCtrl_io_internals_inFrame) && ((! i2cCtrl_io_internals_sdaRead) || (! i2cCtrl_io_internals_sclRead))); - assign bridge_masterLogic_fsm_isBusy = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && (! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF))); - always @(*) begin - when_BusSlaveFactory_l341 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347 = io_ctrl_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l341_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_1 = io_ctrl_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l341_2 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h40 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_2 = io_ctrl_cmd_payload_fragment_data[11]; - assign bridge_masterLogic_txReady = (bridge_inAckState ? bridge_txAck_valid : bridge_txData_valid); - assign when_I2cCtrl_l523 = (! bridge_inAckState); - always @(*) begin - if(when_I2cCtrl_l523) begin - i2cCtrl_io_bus_rsp_valid = ((bridge_txData_valid && (! (bridge_rxData_valid && bridge_rxData_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); - if(bridge_txData_forceDisable) begin - i2cCtrl_io_bus_rsp_valid = 1'b1; - end - end else begin - i2cCtrl_io_bus_rsp_valid = ((bridge_txAck_valid && (! (bridge_rxAck_valid && bridge_rxAck_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); - if(bridge_txAck_forceAck) begin - i2cCtrl_io_bus_rsp_valid = 1'b1; - end - end - if(when_I2cCtrl_l546) begin - i2cCtrl_io_bus_rsp_valid = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE); - end - end - - always @(*) begin - if(when_I2cCtrl_l523) begin - i2cCtrl_io_bus_rsp_enable = bridge_txData_enable; - if(bridge_txData_forceDisable) begin - i2cCtrl_io_bus_rsp_enable = 1'b0; - end - end else begin - i2cCtrl_io_bus_rsp_enable = bridge_txAck_enable; - if(bridge_txAck_forceAck) begin - i2cCtrl_io_bus_rsp_enable = 1'b1; - end - end - if(when_I2cCtrl_l546) begin - i2cCtrl_io_bus_rsp_enable = 1'b0; - end - end - - always @(*) begin - if(when_I2cCtrl_l523) begin - i2cCtrl_io_bus_rsp_data = bridge_txData_value[_zz_io_bus_rsp_data]; - end else begin - i2cCtrl_io_bus_rsp_data = bridge_txAck_value; - if(bridge_txAck_forceAck) begin - i2cCtrl_io_bus_rsp_data = 1'b0; - end - end - end - - assign when_I2cCtrl_l546 = (bridge_wasntAck && (! bridge_masterLogic_fsm_isBusy)); - assign when_I2cCtrl_l566 = (! bridge_inAckState); - assign when_I2cCtrl_l570 = (i2cCtrl_io_bus_rsp_data != i2cCtrl_io_bus_cmd_data); - assign when_I2cCtrl_l574 = (bridge_dataCounter == 3'b111); - assign when_I2cCtrl_l578 = (bridge_txData_valid && (! bridge_txData_repeat)); - assign when_I2cCtrl_l588 = (bridge_txAck_valid && (! bridge_txAck_repeat)); - assign when_I2cCtrl_l601 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP) || (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP)); - always @(*) begin - bridge_interruptCtrl_interrupt = ((((bridge_interruptCtrl_rxDataEnable && bridge_rxData_valid) || (bridge_interruptCtrl_rxAckEnable && bridge_rxAck_valid)) || (bridge_interruptCtrl_txDataEnable && (! bridge_txData_valid))) || (bridge_interruptCtrl_txAckEnable && (! bridge_txAck_valid))); - if(bridge_interruptCtrl_start_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_restart_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_end_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_drop_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_filterGen_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_clockGenExit_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - if(bridge_interruptCtrl_clockGenEnter_flag) begin - bridge_interruptCtrl_interrupt = 1'b1; - end - end - - assign when_I2cCtrl_l634 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_START); - assign when_I2cCtrl_l634_1 = (! bridge_interruptCtrl_start_enable); - always @(*) begin - when_BusSlaveFactory_l341_3 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_3 = io_ctrl_cmd_payload_fragment_data[4]; - assign when_I2cCtrl_l634_2 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_RESTART); - assign when_I2cCtrl_l634_3 = (! bridge_interruptCtrl_restart_enable); - always @(*) begin - when_BusSlaveFactory_l341_4 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_4 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_4 = io_ctrl_cmd_payload_fragment_data[5]; - assign when_I2cCtrl_l634_4 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP); - assign when_I2cCtrl_l634_5 = (! bridge_interruptCtrl_end_enable); - always @(*) begin - when_BusSlaveFactory_l341_5 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_5 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_5 = io_ctrl_cmd_payload_fragment_data[6]; - assign when_I2cCtrl_l634_6 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || bridge_masterLogic_fsm_dropped_trigger); - assign when_I2cCtrl_l634_7 = (! bridge_interruptCtrl_drop_enable); - always @(*) begin - when_BusSlaveFactory_l341_6 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_6 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_6 = io_ctrl_cmd_payload_fragment_data[7]; - assign _zz_when_I2cCtrl_l634 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); - assign when_I2cCtrl_l634_8 = (_zz_when_I2cCtrl_l634 && (! _zz_when_I2cCtrl_l634_1)); - assign when_I2cCtrl_l634_9 = (! bridge_interruptCtrl_filterGen_enable); - always @(*) begin - when_BusSlaveFactory_l341_7 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_7 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_7 = io_ctrl_cmd_payload_fragment_data[17]; - assign when_I2cCtrl_l634_10 = ((! bridge_masterLogic_fsm_isBusy) && bridge_masterLogic_fsm_isBusy_regNext); - assign when_I2cCtrl_l634_11 = (! bridge_interruptCtrl_clockGenExit_enable); - always @(*) begin - when_BusSlaveFactory_l341_8 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_8 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_8 = io_ctrl_cmd_payload_fragment_data[15]; - assign when_I2cCtrl_l634_12 = (bridge_masterLogic_fsm_isBusy && (! bridge_masterLogic_fsm_isBusy_regNext_1)); - assign when_I2cCtrl_l634_13 = (! bridge_interruptCtrl_clockGenEnter_enable); - always @(*) begin - when_BusSlaveFactory_l341_9 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 8'h24 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_9 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_9 = io_ctrl_cmd_payload_fragment_data[16]; - always @(*) begin - i2cCtrl_io_config_timeoutClear = bridge_timeoutClear; - if(when_I2cCtrl_l659) begin - i2cCtrl_io_config_timeoutClear = 1'b1; - end - end - - assign when_I2cCtrl_l659 = ((! i2cCtrl_io_internals_inFrame) && (! bridge_masterLogic_fsm_isBusy)); - always @(*) begin - bridge_masterLogic_fsm_stateNext = bridge_masterLogic_fsm_stateReg; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - if(when_I2cCtrl_l367) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; - end else begin - if(when_I2cCtrl_l369) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; - end else begin - if(bridge_masterLogic_recover) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; - end - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - if(when_I2cCtrl_l380) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - if(when_I2cCtrl_l392) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - if(bridge_masterLogic_timer_done) begin - if(when_I2cCtrl_l418) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1; - end else begin - if(when_I2cCtrl_l422) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART; - end else begin - if(i2cCtrl_io_internals_sclRead) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH; - end - end - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - if(when_I2cCtrl_l442) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - if(!when_I2cCtrl_l450) begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - if(!when_I2cCtrl_l474) begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3; - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - if(i2cCtrl_io_internals_sdaRead) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; - end - end - default : begin - end - endcase - if(when_I2cCtrl_l350) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; - end - if(bridge_masterLogic_fsm_wantStart) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; - end - if(bridge_masterLogic_fsm_wantKill) begin - bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; - end - end - - assign when_I2cCtrl_l367 = ((! i2cCtrl_io_internals_inFrame) && i2cCtrl_io_internals_inFrame_regNext); - assign when_I2cCtrl_l369 = (bridge_masterLogic_start && (! bridge_masterLogic_fsm_inFrameLate)); - assign when_I2cCtrl_l380 = (! bridge_masterLogic_fsm_outOfSync); - assign when_I2cCtrl_l392 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); - assign when_I2cCtrl_l418 = ((bridge_masterLogic_stop && (! bridge_inAckState)) || (bridge_masterLogic_recover && i2cCtrl_io_internals_sdaRead)); - assign when_I2cCtrl_l422 = (bridge_masterLogic_start && (! bridge_inAckState)); - assign when_I2cCtrl_l442 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); - assign when_I2cCtrl_l450 = (! i2cCtrl_io_internals_sclRead); - assign when_I2cCtrl_l474 = (! i2cCtrl_io_internals_sclRead); - assign when_StateMachine_l253 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)); - assign when_StateMachine_l253_1 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)); - assign when_StateMachine_l253_2 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)); - assign when_StateMachine_l253_3 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)); - assign when_StateMachine_l253_4 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)); - assign when_StateMachine_l253_5 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)); - assign when_I2cCtrl_l350 = (bridge_masterLogic_drop || ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || i2cCtrl_io_timeout))); - assign when_I2cCtrl_l673 = (! bridge_slaveOverride_sda); - assign when_I2cCtrl_l674 = (! bridge_slaveOverride_scl); - assign io_i2c_scl_write = bridge_i2cBuffer_scl_write_regNext; - assign io_i2c_sda_write = bridge_i2cBuffer_sda_write_regNext; - assign bridge_i2cBuffer_scl_read = io_i2c_scl_read; - assign bridge_i2cBuffer_sda_read = io_i2c_sda_read; - assign system_i2c_0_io_interrupt_source = bridge_interruptCtrl_interrupt; - always @(posedge clk) begin - if(reset) begin - _zz_io_ctrl_rsp_valid_1 <= 1'b0; - bridge_rxData_event <= 1'b0; - bridge_rxData_listen <= 1'b0; - bridge_rxData_valid <= 1'b0; - bridge_rxAck_listen <= 1'b0; - bridge_rxAck_valid <= 1'b0; - bridge_txData_valid <= 1'b1; - bridge_txData_repeat <= 1'b1; - bridge_txData_enable <= 1'b0; - bridge_txAck_valid <= 1'b1; - bridge_txAck_repeat <= 1'b1; - bridge_txAck_enable <= 1'b0; - bridge_addressFilter_addresses_0_enable <= 1'b0; - bridge_addressFilter_addresses_1_enable <= 1'b0; - bridge_addressFilter_state <= 2'b00; - bridge_masterLogic_start <= 1'b0; - bridge_masterLogic_stop <= 1'b0; - bridge_masterLogic_drop <= 1'b0; - bridge_masterLogic_recover <= 1'b0; - bridge_masterLogic_fsm_dropped_start <= 1'b0; - bridge_masterLogic_fsm_dropped_stop <= 1'b0; - bridge_masterLogic_fsm_dropped_recover <= 1'b0; - bridge_dataCounter <= 3'b000; - bridge_inAckState <= 1'b0; - bridge_wasntAck <= 1'b0; - bridge_interruptCtrl_rxDataEnable <= 1'b0; - bridge_interruptCtrl_rxAckEnable <= 1'b0; - bridge_interruptCtrl_txDataEnable <= 1'b0; - bridge_interruptCtrl_txAckEnable <= 1'b0; - bridge_interruptCtrl_start_enable <= 1'b0; - bridge_interruptCtrl_start_flag <= 1'b0; - bridge_interruptCtrl_restart_enable <= 1'b0; - bridge_interruptCtrl_restart_flag <= 1'b0; - bridge_interruptCtrl_end_enable <= 1'b0; - bridge_interruptCtrl_end_flag <= 1'b0; - bridge_interruptCtrl_drop_enable <= 1'b0; - bridge_interruptCtrl_drop_flag <= 1'b0; - bridge_interruptCtrl_filterGen_enable <= 1'b0; - bridge_interruptCtrl_filterGen_flag <= 1'b0; - bridge_interruptCtrl_clockGenExit_enable <= 1'b0; - bridge_interruptCtrl_clockGenExit_flag <= 1'b0; - bridge_interruptCtrl_clockGenEnter_enable <= 1'b0; - bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; - _zz_io_config_samplingClockDivider <= 10'h0; - bridge_masterLogic_fsm_stateReg <= Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; - bridge_slaveOverride_sda <= 1'b1; - bridge_slaveOverride_scl <= 1'b1; - bridge_i2cBuffer_scl_write_regNext <= 1'b1; - bridge_i2cBuffer_sda_write_regNext <= 1'b1; - end else begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_ctrl_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); - end - bridge_rxData_event <= 1'b0; - if(when_I2cCtrl_l224) begin - bridge_rxData_valid <= 1'b0; - end - if(when_I2cCtrl_l237) begin - bridge_rxAck_valid <= 1'b0; - end - if(bridge_rxData_event) begin - case(bridge_addressFilter_state) - 2'b00 : begin - bridge_addressFilter_state <= 2'b01; - end - 2'b01 : begin - bridge_addressFilter_state <= 2'b10; - end - default : begin - end - endcase - end - if(bridge_frameReset) begin - bridge_addressFilter_state <= 2'b00; - end - if(when_I2cCtrl_l310) begin - bridge_txAck_valid <= 1'b0; - end - if(when_BusSlaveFactory_l377) begin - if(when_BusSlaveFactory_l379) begin - bridge_masterLogic_start <= _zz_bridge_masterLogic_start[0]; - end - end - if(when_BusSlaveFactory_l377_1) begin - if(when_BusSlaveFactory_l379_1) begin - bridge_masterLogic_stop <= _zz_bridge_masterLogic_stop[0]; - end - end - if(when_BusSlaveFactory_l377_2) begin - if(when_BusSlaveFactory_l379_2) begin - bridge_masterLogic_drop <= _zz_bridge_masterLogic_drop[0]; - end - end - if(when_BusSlaveFactory_l377_3) begin - if(when_BusSlaveFactory_l379_3) begin - bridge_masterLogic_recover <= _zz_bridge_masterLogic_recover[0]; - end - end - if(when_BusSlaveFactory_l341) begin - if(when_BusSlaveFactory_l347) begin - bridge_masterLogic_fsm_dropped_start <= _zz_bridge_masterLogic_fsm_dropped_start[0]; - end - end - if(when_BusSlaveFactory_l341_1) begin - if(when_BusSlaveFactory_l347_1) begin - bridge_masterLogic_fsm_dropped_stop <= _zz_bridge_masterLogic_fsm_dropped_stop[0]; - end - end - if(when_BusSlaveFactory_l341_2) begin - if(when_BusSlaveFactory_l347_2) begin - bridge_masterLogic_fsm_dropped_recover <= _zz_bridge_masterLogic_fsm_dropped_recover[0]; - end - end - case(i2cCtrl_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_READ : begin - if(when_I2cCtrl_l566) begin - bridge_dataCounter <= (bridge_dataCounter + 3'b001); - if(when_I2cCtrl_l570) begin - if(bridge_txData_disableOnDataConflict) begin - bridge_txData_enable <= 1'b0; - end - if(bridge_txAck_disableOnDataConflict) begin - bridge_txAck_enable <= 1'b0; - end - end - if(when_I2cCtrl_l574) begin - if(bridge_rxData_listen) begin - bridge_rxData_valid <= 1'b1; - end - bridge_rxData_event <= 1'b1; - bridge_inAckState <= 1'b1; - if(when_I2cCtrl_l578) begin - bridge_txData_valid <= 1'b0; - end - end - end else begin - if(bridge_rxAck_listen) begin - bridge_rxAck_valid <= 1'b1; - end - bridge_inAckState <= 1'b0; - bridge_wasntAck <= i2cCtrl_io_bus_cmd_data; - if(when_I2cCtrl_l588) begin - bridge_txAck_valid <= 1'b0; - end - end - end - default : begin - end - endcase - if(bridge_frameReset) begin - bridge_inAckState <= 1'b0; - bridge_dataCounter <= 3'b000; - bridge_wasntAck <= 1'b0; - end - if(when_I2cCtrl_l601) begin - bridge_txData_valid <= 1'b1; - bridge_txData_enable <= 1'b0; - bridge_txData_repeat <= 1'b1; - bridge_txAck_valid <= 1'b1; - bridge_txAck_enable <= 1'b0; - bridge_txAck_repeat <= 1'b1; - bridge_rxData_listen <= 1'b0; - bridge_rxAck_listen <= 1'b0; - end - if(when_I2cCtrl_l634) begin - bridge_interruptCtrl_start_flag <= 1'b1; - end - if(when_I2cCtrl_l634_1) begin - bridge_interruptCtrl_start_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_3) begin - if(when_BusSlaveFactory_l347_3) begin - bridge_interruptCtrl_start_flag <= _zz_bridge_interruptCtrl_start_flag[0]; - end - end - if(when_I2cCtrl_l634_2) begin - bridge_interruptCtrl_restart_flag <= 1'b1; - end - if(when_I2cCtrl_l634_3) begin - bridge_interruptCtrl_restart_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_4) begin - if(when_BusSlaveFactory_l347_4) begin - bridge_interruptCtrl_restart_flag <= _zz_bridge_interruptCtrl_restart_flag[0]; - end - end - if(when_I2cCtrl_l634_4) begin - bridge_interruptCtrl_end_flag <= 1'b1; - end - if(when_I2cCtrl_l634_5) begin - bridge_interruptCtrl_end_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_5) begin - if(when_BusSlaveFactory_l347_5) begin - bridge_interruptCtrl_end_flag <= _zz_bridge_interruptCtrl_end_flag[0]; - end - end - if(when_I2cCtrl_l634_6) begin - bridge_interruptCtrl_drop_flag <= 1'b1; - end - if(when_I2cCtrl_l634_7) begin - bridge_interruptCtrl_drop_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_6) begin - if(when_BusSlaveFactory_l347_6) begin - bridge_interruptCtrl_drop_flag <= _zz_bridge_interruptCtrl_drop_flag[0]; - end - end - if(when_I2cCtrl_l634_8) begin - bridge_interruptCtrl_filterGen_flag <= 1'b1; - end - if(when_I2cCtrl_l634_9) begin - bridge_interruptCtrl_filterGen_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_7) begin - if(when_BusSlaveFactory_l347_7) begin - bridge_interruptCtrl_filterGen_flag <= _zz_bridge_interruptCtrl_filterGen_flag[0]; - end - end - if(when_I2cCtrl_l634_10) begin - bridge_interruptCtrl_clockGenExit_flag <= 1'b1; - end - if(when_I2cCtrl_l634_11) begin - bridge_interruptCtrl_clockGenExit_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_8) begin - if(when_BusSlaveFactory_l347_8) begin - bridge_interruptCtrl_clockGenExit_flag <= _zz_bridge_interruptCtrl_clockGenExit_flag[0]; - end - end - if(when_I2cCtrl_l634_12) begin - bridge_interruptCtrl_clockGenEnter_flag <= 1'b1; - end - if(when_I2cCtrl_l634_13) begin - bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; - end - if(when_BusSlaveFactory_l341_9) begin - if(when_BusSlaveFactory_l347_9) begin - bridge_interruptCtrl_clockGenEnter_flag <= _zz_bridge_interruptCtrl_clockGenEnter_flag[0]; - end - end - bridge_masterLogic_fsm_stateReg <= bridge_masterLogic_fsm_stateNext; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - if(!when_I2cCtrl_l367) begin - if(when_I2cCtrl_l369) begin - bridge_txData_valid <= 1'b0; - end - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - if(bridge_masterLogic_timer_done) begin - bridge_masterLogic_start <= 1'b0; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - if(i2cCtrl_io_internals_sdaRead) begin - bridge_masterLogic_stop <= 1'b0; - bridge_masterLogic_recover <= 1'b0; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_I2cCtrl_l350) begin - bridge_masterLogic_start <= 1'b0; - bridge_masterLogic_stop <= 1'b0; - bridge_masterLogic_drop <= 1'b0; - bridge_masterLogic_recover <= 1'b0; - if(bridge_masterLogic_start) begin - bridge_masterLogic_fsm_dropped_start <= 1'b1; - end - if(bridge_masterLogic_stop) begin - bridge_masterLogic_fsm_dropped_stop <= 1'b1; - end - end - bridge_i2cBuffer_scl_write_regNext <= bridge_i2cBuffer_scl_write; - bridge_i2cBuffer_sda_write_regNext <= bridge_i2cBuffer_sda_write; - case(io_ctrl_cmd_payload_fragment_address) - 8'h08 : begin - if(busCtrl_doWrite) begin - bridge_rxData_listen <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h0c : begin - if(busCtrl_doWrite) begin - bridge_rxAck_listen <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h0 : begin - if(busCtrl_doWrite) begin - bridge_txData_repeat <= io_ctrl_cmd_payload_fragment_data[10]; - bridge_txData_valid <= io_ctrl_cmd_payload_fragment_data[8]; - bridge_txData_enable <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h04 : begin - if(busCtrl_doWrite) begin - bridge_txAck_repeat <= io_ctrl_cmd_payload_fragment_data[10]; - bridge_txAck_valid <= io_ctrl_cmd_payload_fragment_data[8]; - bridge_txAck_enable <= io_ctrl_cmd_payload_fragment_data[9]; - end - end - 8'h88 : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_0_enable <= io_ctrl_cmd_payload_fragment_data[15]; - end - end - 8'h8c : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_1_enable <= io_ctrl_cmd_payload_fragment_data[15]; - end - end - 8'h20 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_rxDataEnable <= io_ctrl_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_rxAckEnable <= io_ctrl_cmd_payload_fragment_data[1]; - bridge_interruptCtrl_txDataEnable <= io_ctrl_cmd_payload_fragment_data[2]; - bridge_interruptCtrl_txAckEnable <= io_ctrl_cmd_payload_fragment_data[3]; - bridge_interruptCtrl_start_enable <= io_ctrl_cmd_payload_fragment_data[4]; - bridge_interruptCtrl_restart_enable <= io_ctrl_cmd_payload_fragment_data[5]; - bridge_interruptCtrl_end_enable <= io_ctrl_cmd_payload_fragment_data[6]; - bridge_interruptCtrl_drop_enable <= io_ctrl_cmd_payload_fragment_data[7]; - bridge_interruptCtrl_filterGen_enable <= io_ctrl_cmd_payload_fragment_data[17]; - bridge_interruptCtrl_clockGenExit_enable <= io_ctrl_cmd_payload_fragment_data[15]; - bridge_interruptCtrl_clockGenEnter_enable <= io_ctrl_cmd_payload_fragment_data[16]; - end - end - 8'h28 : begin - if(busCtrl_doWrite) begin - _zz_io_config_samplingClockDivider <= io_ctrl_cmd_payload_fragment_data[9 : 0]; - end - end - 8'h48 : begin - if(busCtrl_doWrite) begin - bridge_slaveOverride_sda <= io_ctrl_cmd_payload_fragment_data[1]; - bridge_slaveOverride_scl <= io_ctrl_cmd_payload_fragment_data[2]; - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_ctrl_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - if(bridge_rxData_event) begin - case(bridge_addressFilter_state) - 2'b00 : begin - bridge_addressFilter_byte0 <= bridge_rxData_value; - end - 2'b01 : begin - bridge_addressFilter_byte1 <= bridge_rxData_value; - end - default : begin - end - endcase - end - _zz_when_I2cCtrl_l310_1 <= _zz_when_I2cCtrl_l310; - bridge_masterLogic_timer_value <= (bridge_masterLogic_timer_value - _zz_bridge_masterLogic_timer_value); - if(when_I2cCtrl_l363) begin - bridge_masterLogic_fsm_inFrameLate <= 1'b1; - end - if(when_I2cCtrl_l363_1) begin - bridge_masterLogic_fsm_inFrameLate <= 1'b0; - end - case(i2cCtrl_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_READ : begin - if(when_I2cCtrl_l566) begin - bridge_rxData_value[_zz_bridge_rxData_value] <= i2cCtrl_io_bus_cmd_data; - end else begin - bridge_rxAck_value <= i2cCtrl_io_bus_cmd_data; - end - end - default : begin - end - endcase - if(when_I2cCtrl_l601) begin - bridge_txData_disableOnDataConflict <= 1'b0; - bridge_txAck_disableOnDataConflict <= 1'b0; - end - _zz_when_I2cCtrl_l634_1 <= _zz_when_I2cCtrl_l634; - bridge_masterLogic_fsm_isBusy_regNext <= bridge_masterLogic_fsm_isBusy; - bridge_masterLogic_fsm_isBusy_regNext_1 <= bridge_masterLogic_fsm_isBusy; - bridge_timeoutClear <= 1'b0; - case(bridge_masterLogic_fsm_stateReg) - Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin - if(when_I2cCtrl_l450) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin - if(when_I2cCtrl_l474) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin - end - Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin - end - default : begin - end - endcase - if(when_StateMachine_l253) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - if(when_StateMachine_l253_1) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; - end - if(when_StateMachine_l253_2) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; - end - if(when_StateMachine_l253_3) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - if(when_StateMachine_l253_4) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; - end - if(when_StateMachine_l253_5) begin - bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tBuf; - end - case(io_ctrl_cmd_payload_fragment_address) - 8'h0 : begin - if(busCtrl_doWrite) begin - bridge_txData_value <= io_ctrl_cmd_payload_fragment_data[7 : 0]; - bridge_txData_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; - end - end - 8'h04 : begin - if(busCtrl_doWrite) begin - bridge_txAck_value <= io_ctrl_cmd_payload_fragment_data[0]; - bridge_txAck_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; - end - end - 8'h88 : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_0_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; - bridge_addressFilter_addresses_0_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; - end - end - 8'h8c : begin - if(busCtrl_doWrite) begin - bridge_addressFilter_addresses_1_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; - bridge_addressFilter_addresses_1_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; - end - end - 8'h50 : begin - if(busCtrl_doWrite) begin - bridge_masterLogic_timer_tLow <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 8'h54 : begin - if(busCtrl_doWrite) begin - bridge_masterLogic_timer_tHigh <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 8'h58 : begin - if(busCtrl_doWrite) begin - bridge_masterLogic_timer_tBuf <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 8'h2c : begin - if(busCtrl_doWrite) begin - _zz_io_config_timeout <= io_ctrl_cmd_payload_fragment_data[19 : 0]; - bridge_timeoutClear <= 1'b1; - end - end - 8'h30 : begin - if(busCtrl_doWrite) begin - _zz_io_config_tsuData <= io_ctrl_cmd_payload_fragment_data[5 : 0]; - end - end - default : begin - end - endcase - end - - always @(posedge clk) begin - if(reset) begin - i2cCtrl_io_internals_inFrame_regNext <= 1'b0; - end else begin - i2cCtrl_io_internals_inFrame_regNext <= i2cCtrl_io_internals_inFrame; - end - end - - -endmodule - -module Axi4PeripheralBmbSpiXdrMasterCtrl ( - input wire io_ctrl_cmd_valid, - output wire io_ctrl_cmd_ready, - input wire io_ctrl_cmd_payload_last, - input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, - input wire [11:0] io_ctrl_cmd_payload_fragment_address, - input wire [1:0] io_ctrl_cmd_payload_fragment_length, - input wire [31:0] io_ctrl_cmd_payload_fragment_data, - input wire [2:0] io_ctrl_cmd_payload_fragment_context, - output wire io_ctrl_rsp_valid, - input wire io_ctrl_rsp_ready, - output wire io_ctrl_rsp_payload_last, - output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, - output wire [31:0] io_ctrl_rsp_payload_fragment_data, - output wire [2:0] io_ctrl_rsp_payload_fragment_context, - output wire [0:0] io_spi_sclk_write, - output wire io_spi_data_0_writeEnable, - input wire [0:0] io_spi_data_0_read, - output wire [0:0] io_spi_data_0_write, - output wire io_spi_data_1_writeEnable, - input wire [0:0] io_spi_data_1_read, - output wire [0:0] io_spi_data_1_write, - output wire io_spi_data_2_writeEnable, - input wire [0:0] io_spi_data_2_read, - output wire [0:0] io_spi_data_2_write, - output wire io_spi_data_3_writeEnable, - input wire [0:0] io_spi_data_3_read, - output wire [0:0] io_spi_data_3_write, - output wire [3:0] io_spi_ss, - output wire system_spi_0_io_interrupt_source, - input wire clk, - input wire reset -); - - wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; - wire ctrl_io_cmd_ready; - wire ctrl_io_rsp_valid; - wire [7:0] ctrl_io_rsp_payload_data; - wire [0:0] ctrl_io_spi_sclk_write; - wire [3:0] ctrl_io_spi_ss; - wire [0:0] ctrl_io_spi_data_0_write; - wire ctrl_io_spi_data_0_writeEnable; - wire [0:0] ctrl_io_spi_data_1_write; - wire ctrl_io_spi_data_1_writeEnable; - wire [0:0] ctrl_io_spi_data_2_write; - wire ctrl_io_spi_data_2_writeEnable; - wire [0:0] ctrl_io_spi_data_3_write; - wire ctrl_io_spi_data_3_writeEnable; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; - wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; - wire factory_readErrorFlag; - wire factory_writeErrorFlag; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - reg [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [2:0] factory_rsp_payload_fragment_context; - wire _zz_factory_rsp_ready; - reg _zz_factory_rsp_ready_1; - wire _zz_io_ctrl_rsp_valid; - reg _zz_io_ctrl_rsp_valid_1; - reg _zz_io_ctrl_rsp_payload_last; - reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; - reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; - wire when_Stream_l375; - wire factory_askWrite; - wire factory_askRead; - wire io_ctrl_cmd_fire; - wire factory_doWrite; - wire factory_doRead; - wire when_BmbSlaveFactory_l33; - wire when_BmbSlaveFactory_l35; - wire [31:0] mapping_cmdLogic_writeData; - reg mapping_cmdLogic_doRegular; - reg mapping_cmdLogic_doWriteLarge; - reg mapping_cmdLogic_doReadWriteLarge; - wire mapping_cmdLogic_streamUnbuffered_valid; - wire mapping_cmdLogic_streamUnbuffered_ready; - wire mapping_cmdLogic_streamUnbuffered_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_payload_read; - wire mapping_cmdLogic_streamUnbuffered_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - wire when_Stream_l375_1; - wire ctrl_io_rsp_toStream_valid; - wire ctrl_io_rsp_toStream_ready; - wire [7:0] ctrl_io_rsp_toStream_payload_data; - reg _zz_io_pop_ready; - reg _zz_io_pop_ready_1; - reg mapping_interruptCtrl_cmdIntEnable; - reg mapping_interruptCtrl_rspIntEnable; - wire mapping_interruptCtrl_cmdInt; - wire mapping_interruptCtrl_rspInt; - wire mapping_interruptCtrl_interrupt; - reg _zz_io_config_kind_cpol; - reg _zz_io_config_kind_cpha; - reg [1:0] _zz_io_config_mod; - reg [11:0] _zz_io_config_sclkToggle; - reg [11:0] _zz_io_config_ss_setup; - reg [11:0] _zz_io_config_ss_hold; - reg [11:0] _zz_io_config_ss_disable; - reg [3:0] _zz_io_config_ss_activeHigh; - wire [1:0] _zz_io_config_kind_cpol_1; - - Axi4PeripheralTopLevel ctrl ( - .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i - .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i - .io_config_sclkToggle (_zz_io_config_sclkToggle[11:0] ), //i - .io_config_mod (_zz_io_config_mod[1:0] ), //i - .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh[3:0] ), //i - .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i - .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i - .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i - .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i - .io_cmd_ready (ctrl_io_cmd_ready ), //o - .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i - .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i - .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i - .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i - .io_rsp_valid (ctrl_io_rsp_valid ), //o - .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o - .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (io_spi_data_0_read ), //i - .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (io_spi_data_1_read ), //i - .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (io_spi_data_2_read ), //i - .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (io_spi_data_3_read ), //i - .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o - .io_spi_ss (ctrl_io_spi_ss[3:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo_2 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( - .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i - .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o - .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i - .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i - .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i - .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i - .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o - .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ), //i - .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o - .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o - .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o - .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o - .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo_3 ctrl_io_rsp_queueWithOccupancy ( - .io_push_valid (ctrl_io_rsp_toStream_valid ), //i - .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o - .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i - .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o - .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - assign factory_readErrorFlag = 1'b0; - assign factory_writeErrorFlag = 1'b0; - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_factory_rsp_ready = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready_1 && _zz_factory_rsp_ready); - always @(*) begin - _zz_factory_rsp_ready_1 = io_ctrl_rsp_ready; - if(when_Stream_l375) begin - _zz_factory_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); - assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (factory_doWrite && factory_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - factory_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - factory_rsp_payload_fragment_opcode = 1'b1; - end else begin - factory_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (factory_doRead && factory_readErrorFlag); - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - 12'h004 : begin - factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; - end - 12'h00c : begin - factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; - factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; - factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; - factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; - end - 12'h058 : begin - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - default : begin - end - endcase - end - - assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - always @(*) begin - mapping_cmdLogic_doRegular = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doRegular = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h050 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doReadWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h054 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doReadWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); - assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; - assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN)); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data); - always @(*) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - if(when_Stream_l375_1) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l375_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; - assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; - assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; - assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; - always @(*) begin - _zz_io_pop_ready = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doRead) begin - _zz_io_pop_ready = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - _zz_io_pop_ready_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h058 : begin - if(factory_doRead) begin - _zz_io_pop_ready_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); - assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); - assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); - assign io_spi_sclk_write = ctrl_io_spi_sclk_write; - assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; - assign io_spi_data_0_write = ctrl_io_spi_data_0_write; - assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; - assign io_spi_data_1_write = ctrl_io_spi_data_1_write; - assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; - assign io_spi_data_2_write = ctrl_io_spi_data_2_write; - assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; - assign io_spi_data_3_write = ctrl_io_spi_data_3_write; - assign io_spi_ss = ctrl_io_spi_ss; - assign system_spi_0_io_interrupt_source = mapping_interruptCtrl_interrupt; - assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; - assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; - always @(posedge clk) begin - if(reset) begin - _zz_io_ctrl_rsp_valid_1 <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; - mapping_interruptCtrl_cmdIntEnable <= 1'b0; - mapping_interruptCtrl_rspIntEnable <= 1'b0; - _zz_io_config_ss_activeHigh <= 4'b0000; - end else begin - if(_zz_factory_rsp_ready_1) begin - _zz_io_ctrl_rsp_valid_1 <= (factory_rsp_valid && _zz_factory_rsp_ready); - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b0; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h00c : begin - if(factory_doWrite) begin - mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; - mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; - end - end - 12'h030 : begin - if(factory_doWrite) begin - _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[3 : 0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(_zz_factory_rsp_ready_1) begin - _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h008 : begin - if(factory_doWrite) begin - _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; - _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; - _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; - end - end - 12'h020 : begin - if(factory_doWrite) begin - _zz_io_config_sclkToggle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h024 : begin - if(factory_doWrite) begin - _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h028 : begin - if(factory_doWrite) begin - _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h02c : begin - if(factory_doWrite) begin - _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - default : begin - end - endcase - end - - -endmodule - -module Axi4PeripheralBmbUartCtrl ( - input wire io_bus_cmd_valid, - output wire io_bus_cmd_ready, - input wire io_bus_cmd_payload_last, - input wire [0:0] io_bus_cmd_payload_fragment_opcode, - input wire [5:0] io_bus_cmd_payload_fragment_address, - input wire [1:0] io_bus_cmd_payload_fragment_length, - input wire [31:0] io_bus_cmd_payload_fragment_data, - input wire [2:0] io_bus_cmd_payload_fragment_context, - output wire io_bus_rsp_valid, - input wire io_bus_rsp_ready, - output wire io_bus_rsp_payload_last, - output wire [0:0] io_bus_rsp_payload_fragment_opcode, - output wire [31:0] io_bus_rsp_payload_fragment_data, - output wire [2:0] io_bus_rsp_payload_fragment_context, - output wire io_uart_txd, - input wire io_uart_rxd, - output wire system_uart_0_io_interrupt_source, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - - reg uartCtrl_io_read_queueWithOccupancy_io_pop_ready; - wire uartCtrl_io_write_ready; - wire uartCtrl_io_read_valid; - wire [7:0] uartCtrl_io_read_payload; - wire uartCtrl_io_uart_txd; - wire uartCtrl_io_readError; - wire uartCtrl_io_readBreak; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; - wire uartCtrl_io_read_queueWithOccupancy_io_push_ready; - wire uartCtrl_io_read_queueWithOccupancy_io_pop_valid; - wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_pop_payload; - wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_occupancy; - wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_availability; - wire [0:0] _zz_bridge_misc_readError; - wire [0:0] _zz_bridge_misc_readOverflowError; - wire [0:0] _zz_bridge_misc_breakDetected; - wire [0:0] _zz_bridge_misc_doBreak; - wire [0:0] _zz_bridge_misc_doBreak_1; - wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; - wire busCtrl_readErrorFlag; - wire busCtrl_writeErrorFlag; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - reg [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [2:0] busCtrl_rsp_payload_fragment_context; - wire _zz_busCtrl_rsp_ready; - reg _zz_busCtrl_rsp_ready_1; - wire _zz_io_bus_rsp_valid; - reg _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [2:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l375; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_bus_cmd_fire; - wire busCtrl_doWrite; - wire busCtrl_doRead; - wire when_BmbSlaveFactory_l33; - wire when_BmbSlaveFactory_l35; - wire bridge_busCtrlWrapped_readErrorFlag; - wire bridge_busCtrlWrapped_writeErrorFlag; - reg [2:0] bridge_uartConfigReg_frame_dataLength; - reg [0:0] bridge_uartConfigReg_frame_stop; - reg [1:0] bridge_uartConfigReg_frame_parity; - reg [19:0] bridge_uartConfigReg_clockDivider; - reg _zz_bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_ready; - wire [7:0] bridge_write_streamUnbuffered_payload; - reg bridge_read_streamBreaked_valid; - reg bridge_read_streamBreaked_ready; - wire [7:0] bridge_read_streamBreaked_payload; - reg bridge_interruptCtrl_writeIntEnable; - reg bridge_interruptCtrl_readIntEnable; - wire bridge_interruptCtrl_readInt; - wire bridge_interruptCtrl_writeInt; - wire bridge_interruptCtrl_interrupt; - reg bridge_misc_readError; - reg when_BusSlaveFactory_l341; - wire when_BusSlaveFactory_l347; - reg bridge_misc_readOverflowError; - reg when_BusSlaveFactory_l341_1; - wire when_BusSlaveFactory_l347_1; - wire uartCtrl_io_read_isStall; - reg bridge_misc_breakDetected; - reg uartCtrl_io_readBreak_regNext; - wire when_UartCtrl_l155; - reg when_BusSlaveFactory_l341_2; - wire when_BusSlaveFactory_l347_2; - reg bridge_misc_doBreak; - reg when_BusSlaveFactory_l377; - wire when_BusSlaveFactory_l379; - reg when_BusSlaveFactory_l341_3; - wire when_BusSlaveFactory_l347_3; - wire [1:0] _zz_bridge_uartConfigReg_frame_parity; - wire [0:0] _zz_bridge_uartConfigReg_frame_stop; - wire when_BmbSlaveFactory_l77; - `ifndef SYNTHESIS - reg [23:0] bridge_uartConfigReg_frame_stop_string; - reg [31:0] bridge_uartConfigReg_frame_parity_string; - reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; - reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; - `endif - - - assign _zz_bridge_misc_readError = 1'b0; - assign _zz_bridge_misc_readOverflowError = 1'b0; - assign _zz_bridge_misc_breakDetected = 1'b0; - assign _zz_bridge_misc_doBreak = 1'b1; - assign _zz_bridge_misc_doBreak_1 = 1'b0; - assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); - Axi4PeripheralUartCtrl uartCtrl ( - .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i - .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i - .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i - .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i - .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i - .io_write_ready (uartCtrl_io_write_ready ), //o - .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i - .io_read_valid (uartCtrl_io_read_valid ), //o - .io_read_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //i - .io_read_payload (uartCtrl_io_read_payload[7:0] ), //o - .io_uart_txd (uartCtrl_io_uart_txd ), //o - .io_uart_rxd (io_uart_rxd ), //i - .io_readError (uartCtrl_io_readError ), //o - .io_writeBreak (bridge_misc_doBreak ), //i - .io_readBreak (uartCtrl_io_readBreak ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( - .io_push_valid (bridge_write_streamUnbuffered_valid ), //i - .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i - .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_io_write_ready ), //i - .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralStreamFifo uartCtrl_io_read_queueWithOccupancy ( - .io_push_valid (uartCtrl_io_read_valid ), //i - .io_push_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (uartCtrl_io_read_payload[7:0] ), //i - .io_pop_valid (uartCtrl_io_read_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_io_read_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload (uartCtrl_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (uartCtrl_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (uartCtrl_io_read_queueWithOccupancy_io_availability[7:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(bridge_uartConfigReg_frame_stop) - Axi4PeripheralUartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; - default : bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(bridge_uartConfigReg_frame_parity) - Axi4PeripheralUartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; - default : bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_parity) - Axi4PeripheralUartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; - default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_stop) - Axi4PeripheralUartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; - default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - `endif - - assign io_uart_txd = uartCtrl_io_uart_txd; - assign busCtrl_readErrorFlag = 1'b0; - assign busCtrl_writeErrorFlag = 1'b0; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); - always @(*) begin - _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; - if(when_Stream_l375) begin - _zz_busCtrl_rsp_ready_1 = 1'b1; - end - end - - assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); - assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); - always @(*) begin - if(when_BmbSlaveFactory_l33) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - if(when_BmbSlaveFactory_l35) begin - busCtrl_rsp_payload_fragment_opcode = 1'b1; - end else begin - busCtrl_rsp_payload_fragment_opcode = 1'b0; - end - end - end - - assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; - end - 6'h04 : begin - busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_io_read_queueWithOccupancy_io_occupancy; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; - end - 6'h10 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; - busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_io_readBreak; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - assign bridge_busCtrlWrapped_readErrorFlag = 1'b0; - assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0; - always @(*) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doWrite) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; - assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; - assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - always @(*) begin - bridge_read_streamBreaked_valid = uartCtrl_io_read_queueWithOccupancy_io_pop_valid; - if(uartCtrl_io_readBreak) begin - bridge_read_streamBreaked_valid = 1'b0; - end - end - - always @(*) begin - uartCtrl_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; - if(uartCtrl_io_readBreak) begin - uartCtrl_io_read_queueWithOccupancy_io_pop_ready = 1'b1; - end - end - - assign bridge_read_streamBreaked_payload = uartCtrl_io_read_queueWithOccupancy_io_pop_payload; - always @(*) begin - bridge_read_streamBreaked_ready = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doRead) begin - bridge_read_streamBreaked_ready = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); - assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); - assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); - always @(*) begin - when_BusSlaveFactory_l341 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347 = io_bus_cmd_payload_fragment_data[0]; - always @(*) begin - when_BusSlaveFactory_l341_1 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_1 = io_bus_cmd_payload_fragment_data[1]; - assign uartCtrl_io_read_isStall = (uartCtrl_io_read_valid && (! uartCtrl_io_read_queueWithOccupancy_io_push_ready)); - assign when_UartCtrl_l155 = (uartCtrl_io_readBreak && (! uartCtrl_io_readBreak_regNext)); - always @(*) begin - when_BusSlaveFactory_l341_2 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_2 = io_bus_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l377 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l377 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379 = io_bus_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l341_3 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l341_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_3 = io_bus_cmd_payload_fragment_data[11]; - assign system_uart_0_io_interrupt_source = bridge_interruptCtrl_interrupt; - assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; - assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; - assign when_BmbSlaveFactory_l77 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); - always @(posedge clk) begin - if(reset) begin - _zz_io_bus_rsp_valid_1 <= 1'b0; - bridge_uartConfigReg_clockDivider <= 20'h0; - bridge_uartConfigReg_clockDivider <= 20'h000d8; - bridge_uartConfigReg_frame_dataLength <= 3'b111; - bridge_uartConfigReg_frame_parity <= Axi4PeripheralUartParityType_NONE; - bridge_uartConfigReg_frame_stop <= Axi4PeripheralUartStopType_ONE; - bridge_interruptCtrl_writeIntEnable <= 1'b0; - bridge_interruptCtrl_readIntEnable <= 1'b0; - bridge_misc_readError <= 1'b0; - bridge_misc_readOverflowError <= 1'b0; - bridge_misc_breakDetected <= 1'b0; - bridge_misc_doBreak <= 1'b0; - end else begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); - end - if(when_BusSlaveFactory_l341) begin - if(when_BusSlaveFactory_l347) begin - bridge_misc_readError <= _zz_bridge_misc_readError[0]; - end - end - if(uartCtrl_io_readError) begin - bridge_misc_readError <= 1'b1; - end - if(when_BusSlaveFactory_l341_1) begin - if(when_BusSlaveFactory_l347_1) begin - bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; - end - end - if(uartCtrl_io_read_isStall) begin - bridge_misc_readOverflowError <= 1'b1; - end - if(when_UartCtrl_l155) begin - bridge_misc_breakDetected <= 1'b1; - end - if(when_BusSlaveFactory_l341_2) begin - if(when_BusSlaveFactory_l347_2) begin - bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; - end - end - if(when_BusSlaveFactory_l377) begin - if(when_BusSlaveFactory_l379) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; - end - end - if(when_BusSlaveFactory_l341_3) begin - if(when_BusSlaveFactory_l347_3) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; - end - end - case(io_bus_cmd_payload_fragment_address) - 6'h0c : begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; - bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; - bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; - end - end - 6'h04 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; - end - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l77) begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_clockDivider[19 : 0] <= io_bus_cmd_payload_fragment_data[19 : 0]; - end - end - end - end - - always @(posedge clk) begin - if(_zz_busCtrl_rsp_ready_1) begin - _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - uartCtrl_io_readBreak_regNext <= uartCtrl_io_readBreak; - end - - -endmodule - -module Axi4PeripheralBmbDecoder_1 ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [23:0] io_input_cmd_payload_fragment_address, - input wire [1:0] io_input_cmd_payload_fragment_length, - input wire [31:0] io_input_cmd_payload_fragment_data, - input wire [3:0] io_input_cmd_payload_fragment_mask, - input wire [2:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input wire io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output wire [31:0] io_input_rsp_payload_fragment_data, - output reg [2:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input wire io_outputs_0_cmd_ready, - output wire io_outputs_0_cmd_payload_last, - output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_0_cmd_payload_fragment_address, - output wire [1:0] io_outputs_0_cmd_payload_fragment_length, - output wire [31:0] io_outputs_0_cmd_payload_fragment_data, - output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_0_cmd_payload_fragment_context, - input wire io_outputs_0_rsp_valid, - output wire io_outputs_0_rsp_ready, - input wire io_outputs_0_rsp_payload_last, - input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_0_rsp_payload_fragment_data, - input wire [2:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input wire io_outputs_1_cmd_ready, - output wire io_outputs_1_cmd_payload_last, - output wire [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_1_cmd_payload_fragment_address, - output wire [1:0] io_outputs_1_cmd_payload_fragment_length, - output wire [31:0] io_outputs_1_cmd_payload_fragment_data, - output wire [3:0] io_outputs_1_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_1_cmd_payload_fragment_context, - input wire io_outputs_1_rsp_valid, - output wire io_outputs_1_rsp_ready, - input wire io_outputs_1_rsp_payload_last, - input wire [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_1_rsp_payload_fragment_data, - input wire [2:0] io_outputs_1_rsp_payload_fragment_context, - output reg io_outputs_2_cmd_valid, - input wire io_outputs_2_cmd_ready, - output wire io_outputs_2_cmd_payload_last, - output wire [0:0] io_outputs_2_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_2_cmd_payload_fragment_address, - output wire [1:0] io_outputs_2_cmd_payload_fragment_length, - output wire [31:0] io_outputs_2_cmd_payload_fragment_data, - output wire [3:0] io_outputs_2_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_2_cmd_payload_fragment_context, - input wire io_outputs_2_rsp_valid, - output wire io_outputs_2_rsp_ready, - input wire io_outputs_2_rsp_payload_last, - input wire [0:0] io_outputs_2_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_2_rsp_payload_fragment_data, - input wire [2:0] io_outputs_2_rsp_payload_fragment_context, - output reg io_outputs_3_cmd_valid, - input wire io_outputs_3_cmd_ready, - output wire io_outputs_3_cmd_payload_last, - output wire [0:0] io_outputs_3_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_3_cmd_payload_fragment_address, - output wire [1:0] io_outputs_3_cmd_payload_fragment_length, - output wire [31:0] io_outputs_3_cmd_payload_fragment_data, - output wire [3:0] io_outputs_3_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_3_cmd_payload_fragment_context, - input wire io_outputs_3_rsp_valid, - output wire io_outputs_3_rsp_ready, - input wire io_outputs_3_rsp_payload_last, - input wire [0:0] io_outputs_3_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_3_rsp_payload_fragment_data, - input wire [2:0] io_outputs_3_rsp_payload_fragment_context, - output reg io_outputs_4_cmd_valid, - input wire io_outputs_4_cmd_ready, - output wire io_outputs_4_cmd_payload_last, - output wire [0:0] io_outputs_4_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_4_cmd_payload_fragment_address, - output wire [1:0] io_outputs_4_cmd_payload_fragment_length, - output wire [31:0] io_outputs_4_cmd_payload_fragment_data, - output wire [3:0] io_outputs_4_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_4_cmd_payload_fragment_context, - input wire io_outputs_4_rsp_valid, - output wire io_outputs_4_rsp_ready, - input wire io_outputs_4_rsp_payload_last, - input wire [0:0] io_outputs_4_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_4_rsp_payload_fragment_data, - input wire [2:0] io_outputs_4_rsp_payload_fragment_context, - output reg io_outputs_5_cmd_valid, - input wire io_outputs_5_cmd_ready, - output wire io_outputs_5_cmd_payload_last, - output wire [0:0] io_outputs_5_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_5_cmd_payload_fragment_address, - output wire [1:0] io_outputs_5_cmd_payload_fragment_length, - output wire [31:0] io_outputs_5_cmd_payload_fragment_data, - output wire [3:0] io_outputs_5_cmd_payload_fragment_mask, - output wire [2:0] io_outputs_5_cmd_payload_fragment_context, - input wire io_outputs_5_rsp_valid, - output wire io_outputs_5_rsp_ready, - input wire io_outputs_5_rsp_payload_last, - input wire [0:0] io_outputs_5_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_5_rsp_payload_fragment_data, - input wire [2:0] io_outputs_5_rsp_payload_fragment_context, - input wire clk, - input wire reset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_4; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [2:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [2:0] logic_input_payload_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_hitsS0_2; - wire logic_hitsS0_3; - wire logic_hitsS0_4; - wire logic_hitsS0_5; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - wire _zz_io_outputs_2_cmd_payload_last; - wire _zz_io_outputs_3_cmd_payload_last; - wire _zz_io_outputs_4_cmd_payload_last; - wire _zz_io_outputs_5_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - reg logic_rspHits_2; - reg logic_rspHits_3; - reg logic_rspHits_4; - reg logic_rspHits_5; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire when_BmbDecoder_l60; - wire when_BmbDecoder_l60_1; - reg logic_rspNoHit_singleBeatRsp; - reg [2:0] logic_rspNoHit_context; - wire _zz_io_input_rsp_payload_last; - wire _zz_io_input_rsp_payload_last_1; - wire _zz_io_input_rsp_payload_last_2; - wire [2:0] _zz_io_input_rsp_payload_last_3; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last_3) - 3'b000 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - 3'b001 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - 3'b010 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_2_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; - end - 3'b011 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_3_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; - end - 3'b100 : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_4_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_4 = io_outputs_5_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_5_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_5_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_5_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign logic_noHitS0 = (! (|{logic_hitsS0_5,{logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}}})); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h030000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h020000); - always @(*) begin - io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS0_2); - if(logic_cmdWait) begin - io_outputs_2_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; - assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; - assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h040000); - always @(*) begin - io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS0_3); - if(logic_cmdWait) begin - io_outputs_3_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; - assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; - assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h050000); - always @(*) begin - io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS0_4); - if(logic_cmdWait) begin - io_outputs_4_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; - assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; - assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_5 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); - always @(*) begin - io_outputs_5_cmd_valid = (logic_input_valid && logic_hitsS0_5); - if(logic_cmdWait) begin - io_outputs_5_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_5_cmd_payload_last = logic_input_payload_last; - assign io_outputs_5_cmd_payload_last = _zz_io_outputs_5_cmd_payload_last; - assign io_outputs_5_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_5_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_5_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_5_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_5_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_5_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = ((|{(logic_hitsS0_5 && io_outputs_5_cmd_ready),{(logic_hitsS0_4 && io_outputs_4_cmd_ready),{(logic_hitsS0_3 && io_outputs_3_cmd_ready),{(logic_hitsS0_2 && io_outputs_2_cmd_ready),{(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)}}}}}) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (|{logic_rspHits_5,{logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}}})); - assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); - always @(*) begin - io_input_rsp_valid = ((|{io_outputs_5_rsp_valid,{io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}}}) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = ((logic_rspHits_1 || logic_rspHits_3) || logic_rspHits_5); - assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_2 = (logic_rspHits_4 || logic_rspHits_5); - assign _zz_io_input_rsp_payload_last_3 = {_zz_io_input_rsp_payload_last_2,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_4; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign io_outputs_2_rsp_ready = io_input_rsp_ready; - assign io_outputs_3_rsp_ready = io_input_rsp_ready; - assign io_outputs_4_rsp_ready = io_input_rsp_ready; - assign io_outputs_5_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && (((((((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || (logic_hitsS0_2 != logic_rspHits_2)) || (logic_hitsS0_3 != logic_rspHits_3)) || (logic_hitsS0_4 != logic_rspHits_4)) || (logic_hitsS0_5 != logic_rspHits_5)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge clk) begin - if(reset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - logic_rspHits_1 <= logic_hitsS0_1; - logic_rspHits_2 <= logic_hitsS0_2; - logic_rspHits_3 <= logic_hitsS0_3; - logic_rspHits_4 <= logic_hitsS0_4; - logic_rspHits_5 <= logic_hitsS0_5; - end - if(logic_input_fire) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - end - - -endmodule - -module Axi4PeripheralBmbUnburstify ( - input wire io_input_cmd_valid, - output reg io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [23:0] io_input_cmd_payload_fragment_address, - input wire [9:0] io_input_cmd_payload_fragment_length, - input wire [31:0] io_input_cmd_payload_fragment_data, - input wire [3:0] io_input_cmd_payload_fragment_mask, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_source, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [31:0] io_input_rsp_payload_fragment_data, - output reg io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output reg [0:0] io_output_cmd_payload_fragment_opcode, - output reg [23:0] io_output_cmd_payload_fragment_address, - output reg [1:0] io_output_cmd_payload_fragment_length, - output wire [31:0] io_output_cmd_payload_fragment_data, - output wire [3:0] io_output_cmd_payload_fragment_mask, - output wire [2:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output reg io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [31:0] io_output_rsp_payload_fragment_data, - input wire [2:0] io_output_rsp_payload_fragment_context, - input wire clk, - input wire reset -); - - wire [7:0] _zz_buffer_last; - wire [0:0] _zz_buffer_last_1; - wire [11:0] _zz_buffer_addressIncr; - wire doResult; - reg buffer_valid; - reg [0:0] buffer_opcode; - reg [0:0] buffer_source; - reg [23:0] buffer_address; - reg [7:0] buffer_beat; - wire buffer_last; - wire [23:0] buffer_addressIncr; - wire buffer_isWrite; - wire io_output_cmd_fire; - wire [7:0] cmdTransferBeatCount; - wire requireBuffer; - reg cmdContext_drop; - reg cmdContext_last; - reg [0:0] cmdContext_source; - wire rspContext_drop; - wire rspContext_last; - wire [0:0] rspContext_source; - wire [2:0] _zz_rspContext_drop; - wire when_Stream_l445; - reg io_output_rsp_thrown_valid; - wire io_output_rsp_thrown_ready; - wire io_output_rsp_thrown_payload_last; - wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; - wire [31:0] io_output_rsp_thrown_payload_fragment_data; - wire [2:0] io_output_rsp_thrown_payload_fragment_context; - - assign _zz_buffer_last_1 = 1'b1; - assign _zz_buffer_last = {7'd0, _zz_buffer_last_1}; - assign _zz_buffer_addressIncr = (buffer_address[11 : 0] + 12'h004); - assign buffer_last = (buffer_beat == _zz_buffer_last); - assign buffer_addressIncr = {buffer_address[23 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; - assign buffer_isWrite = (buffer_opcode == 1'b1); - assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); - assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[9 : 2]; - assign requireBuffer = (cmdTransferBeatCount != 8'h0); - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_last = 1'b1; - assign io_output_cmd_payload_fragment_context = {cmdContext_source,{cmdContext_last,cmdContext_drop}}; - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_address = buffer_addressIncr; - end else begin - io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - if(requireBuffer) begin - io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; - end - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_opcode = buffer_opcode; - end else begin - io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - if(requireBuffer) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; - end - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_source = buffer_source; - end else begin - cmdContext_source = io_input_cmd_payload_fragment_source; - end - end - - always @(*) begin - io_input_cmd_ready = 1'b0; - if(buffer_valid) begin - io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); - end else begin - io_input_cmd_ready = io_output_cmd_ready; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); - end else begin - io_output_cmd_valid = io_input_cmd_valid; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_last = buffer_last; - end else begin - cmdContext_last = (! requireBuffer); - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_drop = buffer_isWrite; - end else begin - cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); - end - end - - assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; - assign rspContext_drop = _zz_rspContext_drop[0]; - assign rspContext_last = _zz_rspContext_drop[1]; - assign rspContext_source = _zz_rspContext_drop[2 : 2]; - assign when_Stream_l445 = (! (rspContext_last || (! rspContext_drop))); - always @(*) begin - io_output_rsp_thrown_valid = io_output_rsp_valid; - if(when_Stream_l445) begin - io_output_rsp_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_output_rsp_ready = io_output_rsp_thrown_ready; - if(when_Stream_l445) begin - io_output_rsp_ready = 1'b1; - end - end - - assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; - assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_input_rsp_valid = io_output_rsp_thrown_valid; - assign io_output_rsp_thrown_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = rspContext_last; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - always @(posedge clk) begin - if(reset) begin - buffer_valid <= 1'b0; - end else begin - if(io_output_cmd_fire) begin - if(buffer_last) begin - buffer_valid <= 1'b0; - end - end - if(!buffer_valid) begin - buffer_valid <= (requireBuffer && io_output_cmd_fire); - end - end - end - - always @(posedge clk) begin - if(io_output_cmd_fire) begin - buffer_beat <= (buffer_beat - 8'h01); - buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; - end - if(!buffer_valid) begin - buffer_opcode <= io_input_cmd_payload_fragment_opcode; - buffer_source <= io_input_cmd_payload_fragment_source; - buffer_address <= io_input_cmd_payload_fragment_address; - buffer_beat <= cmdTransferBeatCount; - end - end - - -endmodule - -module Axi4PeripheralBmbDecoder ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [23:0] io_input_cmd_payload_fragment_address, - input wire [9:0] io_input_cmd_payload_fragment_length, - input wire [31:0] io_input_cmd_payload_fragment_data, - input wire [3:0] io_input_cmd_payload_fragment_mask, - output reg io_input_rsp_valid, - input wire io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_source, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output wire [31:0] io_input_rsp_payload_fragment_data, - output reg io_outputs_0_cmd_valid, - input wire io_outputs_0_cmd_ready, - output wire io_outputs_0_cmd_payload_last, - output wire [0:0] io_outputs_0_cmd_payload_fragment_source, - output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output wire [23:0] io_outputs_0_cmd_payload_fragment_address, - output wire [9:0] io_outputs_0_cmd_payload_fragment_length, - output wire [31:0] io_outputs_0_cmd_payload_fragment_data, - output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, - input wire io_outputs_0_rsp_valid, - output wire io_outputs_0_rsp_ready, - input wire io_outputs_0_rsp_payload_last, - input wire [0:0] io_outputs_0_rsp_payload_fragment_source, - input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input wire [31:0] io_outputs_0_rsp_payload_fragment_data, - input wire clk, - input wire reset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_source; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [9:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire logic_hitsS0_0; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire when_BmbDecoder_l60; - wire when_BmbDecoder_l60_1; - reg logic_rspNoHit_singleBeatRsp; - reg [0:0] logic_rspNoHit_source; - reg [7:0] logic_rspNoHit_counter; - wire when_BmbDecoder_l81; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_noHitS0 = (! (|logic_hitsS0_0)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'hffffff)) == 24'h0); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - always @(*) begin - logic_input_ready = ((|(logic_hitsS0_0 && io_outputs_0_cmd_ready)) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (|logic_rspHits_0)); - assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); - always @(*) begin - io_input_rsp_valid = ((|io_outputs_0_rsp_valid) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b0; - if(when_BmbDecoder_l81) begin - io_input_rsp_payload_last = 1'b1; - end - if(logic_rspNoHit_singleBeatRsp) begin - io_input_rsp_payload_last = 1'b1; - end - end - end - - always @(*) begin - io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_source = logic_rspNoHit_source; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 8'h0); - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge clk) begin - if(reset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - end - if(logic_input_fire) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire) begin - logic_rspNoHit_source <= logic_input_payload_fragment_source; - end - if(logic_input_fire) begin - logic_rspNoHit_counter <= logic_input_payload_fragment_length[9 : 2]; - end - if(logic_rspNoHit_doIt) begin - if(io_input_rsp_fire) begin - logic_rspNoHit_counter <= (logic_rspNoHit_counter - 8'h01); - end - end - end - - -endmodule - -module Axi4PeripheralAxi4SharedToBmb ( - input wire io_axi_arw_valid, - output wire io_axi_arw_ready, - input wire [23:0] io_axi_arw_payload_addr, - input wire [7:0] io_axi_arw_payload_len, - input wire [2:0] io_axi_arw_payload_size, - input wire [3:0] io_axi_arw_payload_cache, - input wire [2:0] io_axi_arw_payload_prot, - input wire io_axi_arw_payload_write, - input wire io_axi_w_valid, - output wire io_axi_w_ready, - input wire [31:0] io_axi_w_payload_data, - input wire [3:0] io_axi_w_payload_strb, - input wire io_axi_w_payload_last, - output wire io_axi_b_valid, - input wire io_axi_b_ready, - output reg [1:0] io_axi_b_payload_resp, - output wire io_axi_r_valid, - input wire io_axi_r_ready, - output wire [31:0] io_axi_r_payload_data, - output reg [1:0] io_axi_r_payload_resp, - output wire io_axi_r_payload_last, - output wire io_bmb_cmd_valid, - input wire io_bmb_cmd_ready, - output wire io_bmb_cmd_payload_last, - output wire [0:0] io_bmb_cmd_payload_fragment_source, - output wire [0:0] io_bmb_cmd_payload_fragment_opcode, - output wire [23:0] io_bmb_cmd_payload_fragment_address, - output wire [9:0] io_bmb_cmd_payload_fragment_length, - output wire [31:0] io_bmb_cmd_payload_fragment_data, - output wire [3:0] io_bmb_cmd_payload_fragment_mask, - input wire io_bmb_rsp_valid, - output wire io_bmb_rsp_ready, - input wire io_bmb_rsp_payload_last, - input wire [0:0] io_bmb_rsp_payload_fragment_source, - input wire [0:0] io_bmb_rsp_payload_fragment_opcode, - input wire [31:0] io_bmb_rsp_payload_fragment_data -); - - wire [9:0] _zz_io_bmb_cmd_payload_fragment_length; - wire hazard; - wire io_bmb_cmd_fire; - wire rspIsWrite; - wire when_Axi4SharedToBmb_l42; - wire when_Axi4SharedToBmb_l49; - - assign _zz_io_bmb_cmd_payload_fragment_length = ({2'd0,io_axi_arw_payload_len} <<< 2'd2); - assign hazard = (io_axi_arw_payload_write && (! io_axi_w_valid)); - assign io_bmb_cmd_valid = (io_axi_arw_valid && (! hazard)); - assign io_bmb_cmd_payload_fragment_source = io_axi_arw_payload_write; - assign io_bmb_cmd_payload_fragment_opcode = io_axi_arw_payload_write; - assign io_bmb_cmd_payload_fragment_address = io_axi_arw_payload_addr; - assign io_bmb_cmd_payload_fragment_length = (_zz_io_bmb_cmd_payload_fragment_length | 10'h003); - assign io_bmb_cmd_payload_fragment_data = io_axi_w_payload_data; - assign io_bmb_cmd_payload_fragment_mask = io_axi_w_payload_strb; - assign io_bmb_cmd_payload_last = ((! io_axi_arw_payload_write) || io_axi_w_payload_last); - assign io_bmb_cmd_fire = (io_bmb_cmd_valid && io_bmb_cmd_ready); - assign io_axi_arw_ready = (io_bmb_cmd_fire && io_bmb_cmd_payload_last); - assign io_axi_w_ready = (io_bmb_cmd_fire && (io_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign rspIsWrite = io_bmb_rsp_payload_fragment_source[0]; - assign io_axi_b_valid = (io_bmb_rsp_valid && rspIsWrite); - always @(*) begin - io_axi_b_payload_resp = 2'b00; - if(when_Axi4SharedToBmb_l42) begin - io_axi_b_payload_resp = 2'b11; - end - end - - assign when_Axi4SharedToBmb_l42 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); - assign io_axi_r_valid = (io_bmb_rsp_valid && (! rspIsWrite)); - assign io_axi_r_payload_data = io_bmb_rsp_payload_fragment_data; - assign io_axi_r_payload_last = io_bmb_rsp_payload_last; - always @(*) begin - io_axi_r_payload_resp = 2'b00; - if(when_Axi4SharedToBmb_l49) begin - io_axi_r_payload_resp = 2'b11; - end - end - - assign when_Axi4SharedToBmb_l49 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); - assign io_bmb_rsp_ready = (rspIsWrite ? io_axi_b_ready : io_axi_r_ready); - -endmodule - -module Axi4PeripheralStreamArbiter ( - input wire io_inputs_0_valid, - output wire io_inputs_0_ready, - input wire [23:0] io_inputs_0_payload_addr, - input wire [7:0] io_inputs_0_payload_len, - input wire [2:0] io_inputs_0_payload_size, - input wire [3:0] io_inputs_0_payload_cache, - input wire [2:0] io_inputs_0_payload_prot, - input wire io_inputs_1_valid, - output wire io_inputs_1_ready, - input wire [23:0] io_inputs_1_payload_addr, - input wire [7:0] io_inputs_1_payload_len, - input wire [2:0] io_inputs_1_payload_size, - input wire [3:0] io_inputs_1_payload_cache, - input wire [2:0] io_inputs_1_payload_prot, - output wire io_output_valid, - input wire io_output_ready, - output wire [23:0] io_output_payload_addr, - output wire [7:0] io_output_payload_len, - output wire [2:0] io_output_payload_size, - output wire [3:0] io_output_payload_cache, - output wire [2:0] io_output_payload_prot, - output wire [0:0] io_chosen, - output wire [1:0] io_chosenOH, - input wire clk, - input wire reset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr); - assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len); - assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size); - assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache); - assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge clk) begin - if(reset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(io_output_fire) begin - locked <= 1'b0; - end - end - end - - -endmodule - -//Axi4PeripheralTimer_1 replaced by Axi4PeripheralTimer - -module Axi4PeripheralTimer ( - input wire io_tick, - input wire io_clear, - input wire [15:0] io_limit, - output wire io_full, - output wire [15:0] io_value, - input wire clk, - input wire reset -); - - wire [15:0] _zz_counter; - wire [0:0] _zz_counter_1; - reg [15:0] counter; - wire limitHit; - reg inhibitFull; - - assign _zz_counter_1 = (! limitHit); - assign _zz_counter = {15'd0, _zz_counter_1}; - assign limitHit = (counter == io_limit); - assign io_full = ((limitHit && io_tick) && (! inhibitFull)); - assign io_value = counter; - always @(posedge clk) begin - if(reset) begin - inhibitFull <= 1'b0; - end else begin - if(io_tick) begin - inhibitFull <= limitHit; - end - if(io_clear) begin - inhibitFull <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(io_tick) begin - counter <= (counter + _zz_counter); - end - if(io_clear) begin - counter <= 16'h0; - end - end - - -endmodule - -module Axi4PeripheralPrescaler ( - input wire io_clear, - input wire [23:0] io_limit, - output wire io_overflow, - input wire clk, - input wire reset -); - - reg [23:0] counter; - wire when_Prescaler_l17; - - assign when_Prescaler_l17 = (io_clear || io_overflow); - assign io_overflow = (counter == io_limit); - always @(posedge clk) begin - counter <= (counter + 24'h000001); - if(when_Prescaler_l17) begin - counter <= 24'h0; - end - end - - -endmodule - -module Axi4PeripheralI2cSlave ( - output wire io_i2c_sda_write, - input wire io_i2c_sda_read, - output wire io_i2c_scl_write, - input wire io_i2c_scl_read, - input wire [9:0] io_config_samplingClockDivider, - input wire [19:0] io_config_timeout, - input wire [5:0] io_config_tsuData, - input wire io_config_timeoutClear, - output reg [2:0] io_bus_cmd_kind, - output wire io_bus_cmd_data, - input wire io_bus_rsp_valid, - input wire io_bus_rsp_enable, - input wire io_bus_rsp_data, - output wire io_timeout, - output wire io_internals_inFrame, - output wire io_internals_sdaRead, - output wire io_internals_sclRead, - input wire clk, - input wire reset -); - localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; - localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; - localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; - localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; - localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; - localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; - localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; - - wire io_i2c_scl_read_buffercc_io_dataOut; - wire io_i2c_sda_read_buffercc_io_dataOut; - reg [9:0] filter_timer_counter; - wire filter_timer_tick; - wire filter_sampler_sclSync; - wire filter_sampler_sdaSync; - wire filter_sampler_sclSamples_0; - wire filter_sampler_sclSamples_1; - wire filter_sampler_sclSamples_2; - wire _zz_filter_sampler_sclSamples_0; - reg _zz_filter_sampler_sclSamples_1; - reg _zz_filter_sampler_sclSamples_2; - wire filter_sampler_sdaSamples_0; - wire filter_sampler_sdaSamples_1; - wire filter_sampler_sdaSamples_2; - wire _zz_filter_sampler_sdaSamples_0; - reg _zz_filter_sampler_sdaSamples_1; - reg _zz_filter_sampler_sdaSamples_2; - reg filter_sda; - reg filter_scl; - wire when_Misc_l82; - wire when_Misc_l85; - wire sclEdge_rise; - wire sclEdge_fall; - wire sclEdge_toggle; - reg filter_scl_regNext; - wire sdaEdge_rise; - wire sdaEdge_fall; - wire sdaEdge_toggle; - reg filter_sda_regNext; - wire detector_start; - wire detector_stop; - reg [5:0] tsuData_counter; - wire tsuData_done; - reg tsuData_reset; - wire when_I2CSlave_l191; - reg ctrl_inFrame; - reg ctrl_inFrameData; - reg ctrl_sdaWrite; - reg ctrl_sclWrite; - wire ctrl_rspBufferIn_valid; - reg ctrl_rspBufferIn_ready; - wire ctrl_rspBufferIn_payload_enable; - wire ctrl_rspBufferIn_payload_data; - wire ctrl_rspBuffer_valid; - reg ctrl_rspBuffer_ready; - wire ctrl_rspBuffer_payload_enable; - wire ctrl_rspBuffer_payload_data; - reg ctrl_rspBufferIn_rValid; - reg ctrl_rspBufferIn_rData_enable; - reg ctrl_rspBufferIn_rData_data; - wire when_Stream_l375; - wire ctrl_rspAhead_valid; - wire ctrl_rspAhead_payload_enable; - wire ctrl_rspAhead_payload_data; - wire when_I2CSlave_l241; - wire when_I2CSlave_l245; - wire when_I2CSlave_l251; - wire [2:0] _zz_io_bus_cmd_kind; - reg timeout_enabled; - reg [19:0] timeout_counter; - wire timeout_tick; - wire when_I2CSlave_l270; - wire when_I2CSlave_l276; - wire [2:0] _zz_io_bus_cmd_kind_1; - `ifndef SYNTHESIS - reg [55:0] io_bus_cmd_kind_string; - reg [55:0] _zz_io_bus_cmd_kind_string; - reg [55:0] _zz_io_bus_cmd_kind_1_string; - `endif - - - (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1 io_i2c_scl_read_buffercc ( - .io_dataIn (io_i2c_scl_read ), //i - .io_dataOut (io_i2c_scl_read_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1 io_i2c_sda_read_buffercc ( - .io_dataIn (io_i2c_sda_read ), //i - .io_dataOut (io_i2c_sda_read_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_NONE : io_bus_cmd_kind_string = "NONE "; - Axi4PeripheralI2cSlaveCmdMode_START : io_bus_cmd_kind_string = "START "; - Axi4PeripheralI2cSlaveCmdMode_RESTART : io_bus_cmd_kind_string = "RESTART"; - Axi4PeripheralI2cSlaveCmdMode_STOP : io_bus_cmd_kind_string = "STOP "; - Axi4PeripheralI2cSlaveCmdMode_DROP : io_bus_cmd_kind_string = "DROP "; - Axi4PeripheralI2cSlaveCmdMode_DRIVE : io_bus_cmd_kind_string = "DRIVE "; - Axi4PeripheralI2cSlaveCmdMode_READ : io_bus_cmd_kind_string = "READ "; - default : io_bus_cmd_kind_string = "???????"; - endcase - end - always @(*) begin - case(_zz_io_bus_cmd_kind) - Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_string = "NONE "; - Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_string = "START "; - Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_string = "RESTART"; - Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_string = "STOP "; - Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_string = "DROP "; - Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_string = "DRIVE "; - Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_string = "READ "; - default : _zz_io_bus_cmd_kind_string = "???????"; - endcase - end - always @(*) begin - case(_zz_io_bus_cmd_kind_1) - Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_1_string = "NONE "; - Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_1_string = "START "; - Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_1_string = "RESTART"; - Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_1_string = "STOP "; - Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_1_string = "DROP "; - Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_1_string = "DRIVE "; - Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_1_string = "READ "; - default : _zz_io_bus_cmd_kind_1_string = "???????"; - endcase - end - `endif - - assign filter_timer_tick = (filter_timer_counter == 10'h0); - assign filter_sampler_sclSync = io_i2c_scl_read_buffercc_io_dataOut; - assign filter_sampler_sdaSync = io_i2c_sda_read_buffercc_io_dataOut; - assign _zz_filter_sampler_sclSamples_0 = filter_sampler_sclSync; - assign filter_sampler_sclSamples_0 = _zz_filter_sampler_sclSamples_0; - assign filter_sampler_sclSamples_1 = _zz_filter_sampler_sclSamples_1; - assign filter_sampler_sclSamples_2 = _zz_filter_sampler_sclSamples_2; - assign _zz_filter_sampler_sdaSamples_0 = filter_sampler_sdaSync; - assign filter_sampler_sdaSamples_0 = _zz_filter_sampler_sdaSamples_0; - assign filter_sampler_sdaSamples_1 = _zz_filter_sampler_sdaSamples_1; - assign filter_sampler_sdaSamples_2 = _zz_filter_sampler_sdaSamples_2; - assign when_Misc_l82 = (&{(filter_sampler_sdaSamples_2 != filter_sda),{(filter_sampler_sdaSamples_1 != filter_sda),(filter_sampler_sdaSamples_0 != filter_sda)}}); - assign when_Misc_l85 = (&{(filter_sampler_sclSamples_2 != filter_scl),{(filter_sampler_sclSamples_1 != filter_scl),(filter_sampler_sclSamples_0 != filter_scl)}}); - assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl); - assign sclEdge_fall = (filter_scl_regNext && (! filter_scl)); - assign sclEdge_toggle = (filter_scl_regNext != filter_scl); - assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda); - assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda)); - assign sdaEdge_toggle = (filter_sda_regNext != filter_sda); - assign detector_start = (filter_scl && sdaEdge_fall); - assign detector_stop = (filter_scl && sdaEdge_rise); - assign tsuData_done = (tsuData_counter == 6'h0); - always @(*) begin - tsuData_reset = 1'b0; - if(ctrl_inFrameData) begin - tsuData_reset = (! ctrl_rspAhead_valid); - end - end - - assign when_I2CSlave_l191 = (! tsuData_done); - always @(*) begin - ctrl_sdaWrite = 1'b1; - if(ctrl_inFrameData) begin - if(when_I2CSlave_l251) begin - ctrl_sdaWrite = ctrl_rspAhead_payload_data; - end - end - end - - always @(*) begin - ctrl_sclWrite = 1'b1; - if(ctrl_inFrameData) begin - if(when_I2CSlave_l245) begin - ctrl_sclWrite = 1'b0; - end - end - end - - always @(*) begin - ctrl_rspBufferIn_ready = ctrl_rspBuffer_ready; - if(when_Stream_l375) begin - ctrl_rspBufferIn_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! ctrl_rspBuffer_valid); - assign ctrl_rspBuffer_valid = ctrl_rspBufferIn_rValid; - assign ctrl_rspBuffer_payload_enable = ctrl_rspBufferIn_rData_enable; - assign ctrl_rspBuffer_payload_data = ctrl_rspBufferIn_rData_data; - assign ctrl_rspAhead_valid = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_valid : ctrl_rspBufferIn_valid); - assign ctrl_rspAhead_payload_enable = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_enable : ctrl_rspBufferIn_payload_enable); - assign ctrl_rspAhead_payload_data = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_data : ctrl_rspBufferIn_payload_data); - assign ctrl_rspBufferIn_valid = io_bus_rsp_valid; - assign ctrl_rspBufferIn_payload_enable = io_bus_rsp_enable; - assign ctrl_rspBufferIn_payload_data = io_bus_rsp_data; - always @(*) begin - ctrl_rspBuffer_ready = 1'b0; - if(ctrl_inFrame) begin - if(sclEdge_fall) begin - ctrl_rspBuffer_ready = 1'b1; - end - end - end - - always @(*) begin - io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_NONE; - if(ctrl_inFrame) begin - if(sclEdge_rise) begin - io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_READ; - end - end - if(ctrl_inFrameData) begin - if(when_I2CSlave_l241) begin - io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_DRIVE; - end - end - if(detector_start) begin - io_bus_cmd_kind = _zz_io_bus_cmd_kind; - end - if(when_I2CSlave_l276) begin - if(ctrl_inFrame) begin - io_bus_cmd_kind = _zz_io_bus_cmd_kind_1; - end - end - end - - assign io_bus_cmd_data = filter_sda; - assign when_I2CSlave_l241 = ((! ctrl_rspBuffer_valid) || ctrl_rspBuffer_ready); - assign when_I2CSlave_l245 = ((! ctrl_rspAhead_valid) || (ctrl_rspAhead_payload_enable && (! tsuData_done))); - assign when_I2CSlave_l251 = (ctrl_rspAhead_valid && ctrl_rspAhead_payload_enable); - assign _zz_io_bus_cmd_kind = (ctrl_inFrame ? Axi4PeripheralI2cSlaveCmdMode_RESTART : Axi4PeripheralI2cSlaveCmdMode_START); - assign timeout_tick = (timeout_enabled && (timeout_counter == 20'h0)); - assign when_I2CSlave_l270 = (((timeout_tick || sclEdge_toggle) || (((! ctrl_inFrame) && filter_scl) && filter_sda)) || io_config_timeoutClear); - assign io_timeout = timeout_tick; - assign when_I2CSlave_l276 = (detector_stop || timeout_tick); - assign _zz_io_bus_cmd_kind_1 = (timeout_tick ? Axi4PeripheralI2cSlaveCmdMode_DROP : Axi4PeripheralI2cSlaveCmdMode_STOP); - assign io_internals_inFrame = ctrl_inFrame; - assign io_internals_sdaRead = filter_sda; - assign io_internals_sclRead = filter_scl; - assign io_i2c_scl_write = ctrl_sclWrite; - assign io_i2c_sda_write = ctrl_sdaWrite; - always @(posedge clk) begin - if(reset) begin - filter_timer_counter <= 10'h0; - _zz_filter_sampler_sclSamples_1 <= 1'b1; - _zz_filter_sampler_sclSamples_2 <= 1'b1; - _zz_filter_sampler_sdaSamples_1 <= 1'b1; - _zz_filter_sampler_sdaSamples_2 <= 1'b1; - filter_sda <= 1'b1; - filter_scl <= 1'b1; - filter_scl_regNext <= 1'b1; - filter_sda_regNext <= 1'b1; - tsuData_counter <= 6'h0; - ctrl_inFrame <= 1'b0; - ctrl_inFrameData <= 1'b0; - ctrl_rspBufferIn_rValid <= 1'b0; - timeout_counter <= 20'h0; - end else begin - filter_timer_counter <= (filter_timer_counter - 10'h001); - if(filter_timer_tick) begin - filter_timer_counter <= io_config_samplingClockDivider; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sclSamples_1 <= _zz_filter_sampler_sclSamples_0; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sclSamples_2 <= _zz_filter_sampler_sclSamples_1; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sdaSamples_1 <= _zz_filter_sampler_sdaSamples_0; - end - if(filter_timer_tick) begin - _zz_filter_sampler_sdaSamples_2 <= _zz_filter_sampler_sdaSamples_1; - end - if(filter_timer_tick) begin - if(when_Misc_l82) begin - filter_sda <= filter_sampler_sdaSamples_2; - end - if(when_Misc_l85) begin - filter_scl <= filter_sampler_sclSamples_2; - end - end - filter_scl_regNext <= filter_scl; - filter_sda_regNext <= filter_sda; - if(when_I2CSlave_l191) begin - tsuData_counter <= (tsuData_counter - 6'h01); - end - if(tsuData_reset) begin - tsuData_counter <= io_config_tsuData; - end - if(ctrl_rspBufferIn_ready) begin - ctrl_rspBufferIn_rValid <= ctrl_rspBufferIn_valid; - end - if(ctrl_inFrame) begin - if(sclEdge_fall) begin - ctrl_inFrameData <= 1'b1; - end - end - if(detector_start) begin - ctrl_inFrame <= 1'b1; - ctrl_inFrameData <= 1'b0; - end - timeout_counter <= (timeout_counter - 20'h00001); - if(when_I2CSlave_l270) begin - timeout_counter <= io_config_timeout; - end - if(when_I2CSlave_l276) begin - ctrl_inFrame <= 1'b0; - ctrl_inFrameData <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(ctrl_rspBufferIn_ready) begin - ctrl_rspBufferIn_rData_enable <= ctrl_rspBufferIn_payload_enable; - ctrl_rspBufferIn_rData_data <= ctrl_rspBufferIn_payload_data; - end - timeout_enabled <= (io_config_timeout != 20'h0); - end - - -endmodule - -module Axi4PeripheralStreamFifo_3 ( - input wire io_push_valid, - output wire io_push_ready, - input wire [7:0] io_push_payload_data, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [7:0] io_pop_payload_data, - input wire io_flush, - output wire [8:0] io_occupancy, - output wire [8:0] io_availability, - input wire clk, - input wire reset -); - - reg [7:0] logic_ram_spinal_port1; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [8:0] logic_ptr_push; - reg [8:0] logic_ptr_pop; - wire [8:0] logic_ptr_occupancy; - wire [8:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire io_push_fire; - wire logic_push_onRam_write_valid; - wire [7:0] logic_push_onRam_write_payload_address; - wire [7:0] logic_push_onRam_write_payload_data_data; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [7:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [7:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [7:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [7:0] logic_pop_sync_readPort_cmd_payload; - wire [7:0] logic_pop_sync_readPort_rsp_data; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; - wire logic_pop_sync_readArbitation_fire; - reg [8:0] logic_pop_sync_popReg; - reg [7:0] logic_ram [0:255]; - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_data; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); - assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); - assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); - assign io_push_ready = (! logic_ptr_full); - assign io_push_fire = (io_push_valid && io_push_ready); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; - assign logic_push_onRam_write_payload_data_data = io_push_payload_data; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp_data = logic_ram_spinal_port1[7 : 0]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (9'h100 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - logic_ptr_wentUp <= 1'b0; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 9'h0; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 9'h001); - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 9'h001); - end - if(io_flush) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 9'h0; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module Axi4PeripheralStreamFifo_2 ( - input wire io_push_valid, - output wire io_push_ready, - input wire io_push_payload_kind, - input wire io_push_payload_read, - input wire io_push_payload_write, - input wire [7:0] io_push_payload_data, - output wire io_pop_valid, - input wire io_pop_ready, - output wire io_pop_payload_kind, - output wire io_pop_payload_read, - output wire io_pop_payload_write, - output wire [7:0] io_pop_payload_data, - input wire io_flush, - output wire [8:0] io_occupancy, - output wire [8:0] io_availability, - input wire clk, - input wire reset -); - - reg [10:0] logic_ram_spinal_port1; - wire [10:0] _zz_logic_ram_port; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [8:0] logic_ptr_push; - reg [8:0] logic_ptr_pop; - wire [8:0] logic_ptr_occupancy; - wire [8:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire io_push_fire; - wire logic_push_onRam_write_valid; - wire [7:0] logic_push_onRam_write_payload_address; - wire logic_push_onRam_write_payload_data_kind; - wire logic_push_onRam_write_payload_data_read; - wire logic_push_onRam_write_payload_data_write; - wire [7:0] logic_push_onRam_write_payload_data_data; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [7:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [7:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [7:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [7:0] logic_pop_sync_readPort_cmd_payload; - wire logic_pop_sync_readPort_rsp_kind; - wire logic_pop_sync_readPort_rsp_read; - wire logic_pop_sync_readPort_rsp_write; - wire [7:0] logic_pop_sync_readPort_rsp_data; - wire [10:0] _zz_logic_pop_sync_readPort_rsp_kind; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire logic_pop_sync_readArbitation_translated_payload_kind; - wire logic_pop_sync_readArbitation_translated_payload_read; - wire logic_pop_sync_readArbitation_translated_payload_write; - wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; - wire logic_pop_sync_readArbitation_fire; - reg [8:0] logic_pop_sync_popReg; - reg [10:0] logic_ram [0:255]; - - assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_data,{logic_push_onRam_write_payload_data_write,{logic_push_onRam_write_payload_data_read,logic_push_onRam_write_payload_data_kind}}}; - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); - assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); - assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); - assign io_push_ready = (! logic_ptr_full); - assign io_push_fire = (io_push_valid && io_push_ready); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; - assign logic_push_onRam_write_payload_data_kind = io_push_payload_kind; - assign logic_push_onRam_write_payload_data_read = io_push_payload_read; - assign logic_push_onRam_write_payload_data_write = io_push_payload_write; - assign logic_push_onRam_write_payload_data_data = io_push_payload_data; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign _zz_logic_pop_sync_readPort_rsp_kind = logic_ram_spinal_port1; - assign logic_pop_sync_readPort_rsp_kind = _zz_logic_pop_sync_readPort_rsp_kind[0]; - assign logic_pop_sync_readPort_rsp_read = _zz_logic_pop_sync_readPort_rsp_kind[1]; - assign logic_pop_sync_readPort_rsp_write = _zz_logic_pop_sync_readPort_rsp_kind[2]; - assign logic_pop_sync_readPort_rsp_data = _zz_logic_pop_sync_readPort_rsp_kind[10 : 3]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_kind = logic_pop_sync_readPort_rsp_kind; - assign logic_pop_sync_readArbitation_translated_payload_read = logic_pop_sync_readPort_rsp_read; - assign logic_pop_sync_readArbitation_translated_payload_write = logic_pop_sync_readPort_rsp_write; - assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_kind = logic_pop_sync_readArbitation_translated_payload_kind; - assign io_pop_payload_read = logic_pop_sync_readArbitation_translated_payload_read; - assign io_pop_payload_write = logic_pop_sync_readArbitation_translated_payload_write; - assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (9'h100 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - logic_ptr_wentUp <= 1'b0; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 9'h0; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 9'h001); - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 9'h001); - end - if(io_flush) begin - logic_ptr_push <= 9'h0; - logic_ptr_pop <= 9'h0; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 9'h0; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module Axi4PeripheralTopLevel ( - input wire io_config_kind_cpol, - input wire io_config_kind_cpha, - input wire [11:0] io_config_sclkToggle, - input wire [1:0] io_config_mod, - input wire [3:0] io_config_ss_activeHigh, - input wire [11:0] io_config_ss_setup, - input wire [11:0] io_config_ss_hold, - input wire [11:0] io_config_ss_disable, - input wire io_cmd_valid, - output reg io_cmd_ready, - input wire io_cmd_payload_kind, - input wire io_cmd_payload_read, - input wire io_cmd_payload_write, - input wire [7:0] io_cmd_payload_data, - output wire io_rsp_valid, - output wire [7:0] io_rsp_payload_data, - output wire [0:0] io_spi_sclk_write, - output reg io_spi_data_0_writeEnable, - input wire [0:0] io_spi_data_0_read, - output reg [0:0] io_spi_data_0_write, - output reg io_spi_data_1_writeEnable, - input wire [0:0] io_spi_data_1_read, - output reg [0:0] io_spi_data_1_write, - output reg io_spi_data_2_writeEnable, - input wire [0:0] io_spi_data_2_read, - output reg [0:0] io_spi_data_2_write, - output reg io_spi_data_3_writeEnable, - input wire [0:0] io_spi_data_3_read, - output reg [0:0] io_spi_data_3_write, - output wire [3:0] io_spi_ss, - input wire clk, - input wire reset -); - - reg [0:0] _zz_outputPhy_dataWrite_3; - wire [2:0] _zz_outputPhy_dataWrite_4; - reg [1:0] _zz_outputPhy_dataWrite_5; - wire [1:0] _zz_outputPhy_dataWrite_6; - wire [2:0] _zz_outputPhy_dataWrite_7; - reg [3:0] _zz_outputPhy_dataWrite_8; - wire [0:0] _zz_outputPhy_dataWrite_9; - wire [2:0] _zz_outputPhy_dataWrite_10; - wire [3:0] _zz_inputPhy_dataRead; - wire [3:0] _zz_inputPhy_dataRead_1; - wire [3:0] _zz_inputPhy_dataRead_2; - wire [3:0] _zz_inputPhy_dataRead_3; - wire [3:0] _zz_inputPhy_dataRead_4; - wire [3:0] _zz_inputPhy_dataRead_5; - wire [3:0] _zz_inputPhy_dataRead_6; - wire [8:0] _zz_inputPhy_bufferNext; - wire [10:0] _zz_inputPhy_bufferNext_1; - reg [11:0] timer_counter; - reg timer_reset; - wire timer_ss_setupHit; - wire timer_ss_holdHit; - wire timer_ss_disableHit; - wire timer_sclkToggleHit; - reg fsm_state; - reg [2:0] fsm_counter; - reg [2:0] _zz_fsm_counterPlus; - wire [2:0] fsm_counterPlus; - reg fsm_fastRate; - reg fsm_isDdr; - reg [2:0] fsm_counterMax; - reg fsm_lateSampling; - reg fsm_readFill; - reg fsm_readDone; - reg [3:0] fsm_ss; - wire when_SpiXdrMasterCtrl_l741; - wire when_SpiXdrMasterCtrl_l744; - wire when_SpiXdrMasterCtrl_l751; - wire when_SpiXdrMasterCtrl_l753; - wire when_SpiXdrMasterCtrl_l760; - wire when_SpiXdrMasterCtrl_l766; - wire when_SpiXdrMasterCtrl_l783; - reg [0:0] outputPhy_sclkWrite; - wire [0:0] _zz_io_spi_sclk_write; - wire when_SpiXdrMasterCtrl_l798; - reg [3:0] outputPhy_dataWrite; - reg [2:0] outputPhy_widthSel; - reg [2:0] outputPhy_offset; - wire [7:0] _zz_outputPhy_dataWrite; - wire [7:0] _zz_outputPhy_dataWrite_1; - wire [7:0] _zz_outputPhy_dataWrite_2; - wire when_SpiXdrMasterCtrl_l841; - wire when_SpiXdrMasterCtrl_l841_1; - reg [1:0] io_config_mod_delay_1; - reg [1:0] inputPhy_mod; - reg fsm_readFill_delay_1; - reg inputPhy_readFill; - reg fsm_readDone_delay_1; - reg inputPhy_readDone; - reg [6:0] inputPhy_buffer; - reg [7:0] inputPhy_bufferNext; - reg [2:0] inputPhy_widthSel; - wire [3:0] inputPhy_dataWrite; - reg [3:0] inputPhy_dataRead; - reg fsm_state_delay_1; - reg fsm_state_delay_2; - wire when_SpiXdrMasterCtrl_l863; - reg [3:0] inputPhy_dataReadBuffer; - - assign _zz_outputPhy_dataWrite_4 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_6 = (_zz_outputPhy_dataWrite_7 >>> 1'd1); - assign _zz_outputPhy_dataWrite_7 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_9 = (_zz_outputPhy_dataWrite_10 >>> 2'd2); - assign _zz_outputPhy_dataWrite_10 = (outputPhy_offset - fsm_counter); - assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; - assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; - always @(*) begin - case(_zz_outputPhy_dataWrite_4) - 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; - 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; - 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; - 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; - 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; - 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; - 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; - default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_6) - 2'b00 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[1 : 0]; - 2'b01 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[3 : 2]; - 2'b10 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[5 : 4]; - default : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[7 : 6]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_9) - 1'b0 : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[3 : 0]; - default : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[7 : 4]; - endcase - end - - always @(*) begin - timer_reset = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - timer_reset = timer_sclkToggleHit; - end else begin - if(!when_SpiXdrMasterCtrl_l760) begin - if(when_SpiXdrMasterCtrl_l766) begin - if(timer_ss_holdHit) begin - timer_reset = 1'b1; - end - end - end - end - end - if(when_SpiXdrMasterCtrl_l783) begin - timer_reset = 1'b1; - end - end - - assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); - assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); - assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); - assign timer_sclkToggleHit = (timer_counter == io_config_sclkToggle); - always @(*) begin - _zz_fsm_counterPlus = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - _zz_fsm_counterPlus = 3'b001; - end - 2'b01 : begin - _zz_fsm_counterPlus = 3'b010; - end - 2'b10 : begin - _zz_fsm_counterPlus = 3'b100; - end - default : begin - end - endcase - end - - assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); - always @(*) begin - fsm_fastRate = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_fastRate = 1'b0; - end - 2'b01 : begin - fsm_fastRate = 1'b0; - end - 2'b10 : begin - fsm_fastRate = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_isDdr = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_isDdr = 1'b0; - end - 2'b01 : begin - fsm_isDdr = 1'b0; - end - 2'b10 : begin - fsm_isDdr = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_counterMax = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - fsm_counterMax = 3'b111; - end - 2'b01 : begin - fsm_counterMax = 3'b110; - end - 2'b10 : begin - fsm_counterMax = 3'b100; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_lateSampling = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_lateSampling = 1'b1; - end - 2'b01 : begin - fsm_lateSampling = 1'b1; - end - 2'b10 : begin - fsm_lateSampling = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_readFill = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(when_SpiXdrMasterCtrl_l744) begin - fsm_readFill = 1'b1; - end - end - end - end - - always @(*) begin - fsm_readDone = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(when_SpiXdrMasterCtrl_l744) begin - fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); - end - end - end - end - - assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); - always @(*) begin - io_cmd_ready = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(when_SpiXdrMasterCtrl_l751) begin - if(when_SpiXdrMasterCtrl_l753) begin - io_cmd_ready = 1'b1; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l760) begin - if(timer_ss_setupHit) begin - io_cmd_ready = 1'b1; - end - end else begin - if(!when_SpiXdrMasterCtrl_l766) begin - if(timer_ss_disableHit) begin - io_cmd_ready = 1'b1; - end - end - end - end - end - end - - assign when_SpiXdrMasterCtrl_l741 = (! io_cmd_payload_kind); - assign when_SpiXdrMasterCtrl_l744 = ((timer_sclkToggleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l751 = ((timer_sclkToggleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l753 = (fsm_counter == fsm_counterMax); - assign when_SpiXdrMasterCtrl_l760 = io_cmd_payload_data[7]; - assign when_SpiXdrMasterCtrl_l766 = (! fsm_state); - assign when_SpiXdrMasterCtrl_l783 = ((! io_cmd_valid) || io_cmd_ready); - always @(*) begin - outputPhy_sclkWrite = 1'b0; - if(when_SpiXdrMasterCtrl_l798) begin - case(io_config_mod) - 2'b00 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b01 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b10 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - default : begin - end - endcase - end - end - - assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; - assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); - assign when_SpiXdrMasterCtrl_l798 = (io_cmd_valid && (! io_cmd_payload_kind)); - always @(*) begin - outputPhy_widthSel = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_widthSel = 3'b000; - end - 2'b01 : begin - outputPhy_widthSel = 3'b001; - end - 2'b10 : begin - outputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_offset = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_offset = 3'b111; - end - 2'b01 : begin - outputPhy_offset = 3'b111; - end - 2'b10 : begin - outputPhy_offset = 3'b111; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_dataWrite = 4'bxxxx; - case(outputPhy_widthSel) - 3'b000 : begin - outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; - end - 3'b001 : begin - outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_5; - end - 3'b010 : begin - outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_8; - end - default : begin - end - endcase - end - - assign _zz_outputPhy_dataWrite = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; - always @(*) begin - io_spi_data_0_writeEnable = 1'b0; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_writeEnable = 1'b1; - end - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l841) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_writeEnable = 1'b0; - case(io_config_mod) - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l841) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_2_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l841_1) begin - io_spi_data_3_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_0_write = 1'bx; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); - end - 2'b01 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - 2'b10 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_write = 1'bx; - case(io_config_mod) - 2'b01 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - 2'b10 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_2_write[0] = outputPhy_dataWrite[2]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_3_write[0] = outputPhy_dataWrite[3]; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l841 = (io_cmd_valid && io_cmd_payload_write); - assign when_SpiXdrMasterCtrl_l841_1 = (io_cmd_valid && io_cmd_payload_write); - always @(*) begin - inputPhy_bufferNext = 8'bxxxxxxxx; - case(inputPhy_widthSel) - 3'b000 : begin - inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; - end - 3'b001 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; - end - 3'b010 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; - end - default : begin - end - endcase - end - - always @(*) begin - inputPhy_widthSel = 3'bxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_widthSel = 3'b000; - end - 2'b01 : begin - inputPhy_widthSel = 3'b001; - end - 2'b10 : begin - inputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l863 = (! fsm_state_delay_2); - always @(*) begin - inputPhy_dataRead = 4'bxxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; - end - 2'b01 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; - end - 2'b10 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; - inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; - inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; - end - default : begin - end - endcase - end - - assign io_rsp_valid = inputPhy_readDone; - assign io_rsp_payload_data = inputPhy_bufferNext; - always @(posedge clk) begin - timer_counter <= (timer_counter + 12'h001); - if(timer_reset) begin - timer_counter <= 12'h0; - end - io_config_mod_delay_1 <= io_config_mod; - inputPhy_mod <= io_config_mod_delay_1; - fsm_state_delay_1 <= fsm_state; - fsm_state_delay_2 <= fsm_state_delay_1; - if(when_SpiXdrMasterCtrl_l863) begin - inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - end - case(inputPhy_widthSel) - 3'b000 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b001 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b010 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - default : begin - end - endcase - end - - always @(posedge clk) begin - if(reset) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - fsm_ss <= 4'b0000; - fsm_readFill_delay_1 <= 1'b0; - inputPhy_readFill <= 1'b0; - fsm_readDone_delay_1 <= 1'b0; - inputPhy_readDone <= 1'b0; - end else begin - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l741) begin - if(timer_sclkToggleHit) begin - fsm_state <= (! fsm_state); - end - if(when_SpiXdrMasterCtrl_l751) begin - fsm_counter <= fsm_counterPlus; - if(when_SpiXdrMasterCtrl_l753) begin - fsm_state <= 1'b0; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l760) begin - fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b1; - end else begin - if(when_SpiXdrMasterCtrl_l766) begin - if(timer_ss_holdHit) begin - fsm_state <= 1'b1; - end - end else begin - fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b0; - end - end - end - end - if(when_SpiXdrMasterCtrl_l783) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - end - fsm_readFill_delay_1 <= fsm_readFill; - inputPhy_readFill <= fsm_readFill_delay_1; - fsm_readDone_delay_1 <= fsm_readDone; - inputPhy_readDone <= fsm_readDone_delay_1; - end - end - - -endmodule - -//Axi4PeripheralStreamFifo_1 replaced by Axi4PeripheralStreamFifo - -module Axi4PeripheralStreamFifo ( - input wire io_push_valid, - output wire io_push_ready, - input wire [7:0] io_push_payload, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [7:0] io_pop_payload, - input wire io_flush, - output wire [7:0] io_occupancy, - output wire [7:0] io_availability, - input wire clk, - input wire reset -); - - reg [7:0] logic_ram_spinal_port1; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [7:0] logic_ptr_push; - reg [7:0] logic_ptr_pop; - wire [7:0] logic_ptr_occupancy; - wire [7:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire io_push_fire; - wire logic_push_onRam_write_valid; - wire [6:0] logic_push_onRam_write_payload_address; - wire [7:0] logic_push_onRam_write_payload_data; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [6:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [6:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [6:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [6:0] logic_pop_sync_readPort_cmd_payload; - wire [7:0] logic_pop_sync_readPort_rsp; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [7:0] logic_pop_sync_readArbitation_translated_payload; - wire logic_pop_sync_readArbitation_fire; - reg [7:0] logic_pop_sync_popReg; - reg [7:0] logic_ram [0:127]; - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 8'h80) == 8'h0); - assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); - assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); - assign io_push_ready = (! logic_ptr_full); - assign io_push_fire = (io_push_valid && io_push_ready); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push[6:0]; - assign logic_push_onRam_write_payload_data = io_push_payload; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop[6:0]; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (8'h80 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 8'h0; - logic_ptr_pop <= 8'h0; - logic_ptr_wentUp <= 1'b0; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 8'h0; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 8'h01); - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 8'h01); - end - if(io_flush) begin - logic_ptr_push <= 8'h0; - logic_ptr_pop <= 8'h0; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 8'h0; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module Axi4PeripheralUartCtrl ( - input wire [2:0] io_config_frame_dataLength, - input wire [0:0] io_config_frame_stop, - input wire [1:0] io_config_frame_parity, - input wire [19:0] io_config_clockDivider, - input wire io_write_valid, - output reg io_write_ready, - input wire [7:0] io_write_payload, - output wire io_read_valid, - input wire io_read_ready, - output wire [7:0] io_read_payload, - output wire io_uart_txd, - input wire io_uart_rxd, - output wire io_readError, - input wire io_writeBreak, - output wire io_readBreak, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - - wire tx_io_write_ready; - wire tx_io_txd; - wire rx_io_read_valid; - wire [7:0] rx_io_read_payload; - wire rx_io_rts; - wire rx_io_error; - wire rx_io_break; - reg [19:0] clockDivider_counter; - wire clockDivider_tick; - reg clockDivider_tickReg; - reg io_write_thrown_valid; - wire io_write_thrown_ready; - wire [7:0] io_write_thrown_payload; - `ifndef SYNTHESIS - reg [23:0] io_config_frame_stop_string; - reg [31:0] io_config_frame_parity_string; - `endif - - - Axi4PeripheralUartCtrlTx tx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_write_valid (io_write_thrown_valid ), //i - .io_write_ready (tx_io_write_ready ), //o - .io_write_payload (io_write_thrown_payload[7:0] ), //i - .io_cts (1'b0 ), //i - .io_txd (tx_io_txd ), //o - .io_break (io_writeBreak ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Axi4PeripheralUartCtrlRx rx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_read_valid (rx_io_read_valid ), //o - .io_read_ready (io_read_ready ), //i - .io_read_payload (rx_io_read_payload[7:0] ), //o - .io_rxd (io_uart_rxd ), //i - .io_rts (rx_io_rts ), //o - .io_error (rx_io_error ), //o - .io_break (rx_io_break ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_config_frame_stop) - Axi4PeripheralUartStopType_ONE : io_config_frame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : io_config_frame_stop_string = "TWO"; - default : io_config_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_config_frame_parity) - Axi4PeripheralUartParityType_NONE : io_config_frame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : io_config_frame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : io_config_frame_parity_string = "ODD "; - default : io_config_frame_parity_string = "????"; - endcase - end - `endif - - assign clockDivider_tick = (clockDivider_counter == 20'h0); - always @(*) begin - io_write_thrown_valid = io_write_valid; - if(rx_io_break) begin - io_write_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_write_ready = io_write_thrown_ready; - if(rx_io_break) begin - io_write_ready = 1'b1; - end - end - - assign io_write_thrown_payload = io_write_payload; - assign io_write_thrown_ready = tx_io_write_ready; - assign io_read_valid = rx_io_read_valid; - assign io_read_payload = rx_io_read_payload; - assign io_uart_txd = tx_io_txd; - assign io_readError = rx_io_error; - assign io_readBreak = rx_io_break; - always @(posedge clk) begin - if(reset) begin - clockDivider_counter <= 20'h0; - clockDivider_tickReg <= 1'b0; - end else begin - clockDivider_tickReg <= clockDivider_tick; - clockDivider_counter <= (clockDivider_counter - 20'h00001); - if(clockDivider_tick) begin - clockDivider_counter <= io_config_clockDivider; - end - end - end - - -endmodule - -//Axi4PeripheralBufferCC_2 replaced by Axi4PeripheralBufferCC_1 - -module Axi4PeripheralBufferCC_1 ( - input wire io_dataIn, - output wire io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module Axi4PeripheralUartCtrlRx ( - input wire [2:0] io_configFrame_dataLength, - input wire [0:0] io_configFrame_stop, - input wire [1:0] io_configFrame_parity, - input wire io_samplingTick, - output wire io_read_valid, - input wire io_read_ready, - output wire [7:0] io_read_payload, - input wire io_rxd, - output wire io_rts, - output reg io_error, - output wire io_break, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - localparam Axi4PeripheralUartCtrlRxState_IDLE = 3'd0; - localparam Axi4PeripheralUartCtrlRxState_START = 3'd1; - localparam Axi4PeripheralUartCtrlRxState_DATA = 3'd2; - localparam Axi4PeripheralUartCtrlRxState_PARITY = 3'd3; - localparam Axi4PeripheralUartCtrlRxState_STOP = 3'd4; - - wire io_rxd_buffercc_io_dataOut; - wire _zz_sampler_value; - wire _zz_sampler_value_1; - wire _zz_sampler_value_2; - wire _zz_sampler_value_3; - wire _zz_sampler_value_4; - wire _zz_sampler_value_5; - wire _zz_sampler_value_6; - wire [2:0] _zz_when_UartCtrlRx_l139; - wire [0:0] _zz_when_UartCtrlRx_l139_1; - reg _zz_io_rts; - wire sampler_synchroniser; - wire sampler_samples_0; - reg sampler_samples_1; - reg sampler_samples_2; - reg sampler_samples_3; - reg sampler_samples_4; - reg sampler_value; - reg sampler_tick; - reg [2:0] bitTimer_counter; - reg bitTimer_tick; - wire when_UartCtrlRx_l43; - reg [2:0] bitCounter_value; - reg [6:0] break_counter; - wire break_valid; - wire when_UartCtrlRx_l69; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg [7:0] stateMachine_shifter; - reg stateMachine_validReg; - wire when_UartCtrlRx_l93; - wire when_UartCtrlRx_l103; - wire when_UartCtrlRx_l111; - wire when_UartCtrlRx_l113; - wire when_UartCtrlRx_l125; - wire when_UartCtrlRx_l136; - wire when_UartCtrlRx_l139; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; - assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); - assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); - assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); - assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); - assign _zz_sampler_value_6 = 1'b1; - assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); - assign _zz_sampler_value_2 = 1'b1; - (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC io_rxd_buffercc ( - .io_dataIn (io_rxd ), //i - .io_dataOut (io_rxd_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; - Axi4PeripheralUartCtrlRxState_START : stateMachine_state_string = "START "; - Axi4PeripheralUartCtrlRxState_DATA : stateMachine_state_string = "DATA "; - Axi4PeripheralUartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; - Axi4PeripheralUartCtrlRxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - io_error = 1'b0; - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : begin - end - Axi4PeripheralUartCtrlRxState_START : begin - end - Axi4PeripheralUartCtrlRxState_DATA : begin - end - Axi4PeripheralUartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(!when_UartCtrlRx_l125) begin - io_error = 1'b1; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - io_error = 1'b1; - end - end - end - endcase - end - - assign io_rts = _zz_io_rts; - assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; - assign sampler_samples_0 = sampler_synchroniser; - always @(*) begin - bitTimer_tick = 1'b0; - if(sampler_tick) begin - if(when_UartCtrlRx_l43) begin - bitTimer_tick = 1'b1; - end - end - end - - assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); - assign break_valid = (break_counter == 7'h68); - assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); - assign io_break = break_valid; - assign io_read_valid = stateMachine_validReg; - assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); - assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); - assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); - assign when_UartCtrlRx_l113 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); - assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); - assign when_UartCtrlRx_l136 = (! sampler_value); - assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); - assign io_read_payload = stateMachine_shifter; - always @(posedge clk) begin - if(reset) begin - _zz_io_rts <= 1'b0; - sampler_samples_1 <= 1'b1; - sampler_samples_2 <= 1'b1; - sampler_samples_3 <= 1'b1; - sampler_samples_4 <= 1'b1; - sampler_value <= 1'b1; - sampler_tick <= 1'b0; - break_counter <= 7'h0; - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - stateMachine_validReg <= 1'b0; - end else begin - _zz_io_rts <= (! io_read_ready); - if(io_samplingTick) begin - sampler_samples_1 <= sampler_samples_0; - end - if(io_samplingTick) begin - sampler_samples_2 <= sampler_samples_1; - end - if(io_samplingTick) begin - sampler_samples_3 <= sampler_samples_2; - end - if(io_samplingTick) begin - sampler_samples_4 <= sampler_samples_3; - end - sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); - sampler_tick <= io_samplingTick; - if(sampler_value) begin - break_counter <= 7'h0; - end else begin - if(when_UartCtrlRx_l69) begin - break_counter <= (break_counter + 7'h01); - end - end - stateMachine_validReg <= 1'b0; - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_START; - end - end - Axi4PeripheralUartCtrlRxState_START : begin - if(bitTimer_tick) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_DATA; - if(when_UartCtrlRx_l103) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end - end - end - Axi4PeripheralUartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l111) begin - if(when_UartCtrlRx_l113) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_PARITY; - end - end - end - end - Axi4PeripheralUartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l125) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end else begin - if(when_UartCtrlRx_l139) begin - stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; - end - end - end - end - endcase - end - end - - always @(posedge clk) begin - if(sampler_tick) begin - bitTimer_counter <= (bitTimer_counter - 3'b001); - end - if(bitTimer_tick) begin - bitCounter_value <= (bitCounter_value + 3'b001); - end - if(bitTimer_tick) begin - stateMachine_parity <= (stateMachine_parity ^ sampler_value); - end - case(stateMachine_state) - Axi4PeripheralUartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - bitTimer_counter <= 3'b010; - end - end - Axi4PeripheralUartCtrlRxState_START : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); - end - end - Axi4PeripheralUartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - stateMachine_shifter[bitCounter_value] <= sampler_value; - if(when_UartCtrlRx_l111) begin - bitCounter_value <= 3'b000; - end - end - end - Axi4PeripheralUartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module Axi4PeripheralUartCtrlTx ( - input wire [2:0] io_configFrame_dataLength, - input wire [0:0] io_configFrame_stop, - input wire [1:0] io_configFrame_parity, - input wire io_samplingTick, - input wire io_write_valid, - output reg io_write_ready, - input wire [7:0] io_write_payload, - input wire io_cts, - output wire io_txd, - input wire io_break, - input wire clk, - input wire reset -); - localparam Axi4PeripheralUartStopType_ONE = 1'd0; - localparam Axi4PeripheralUartStopType_TWO = 1'd1; - localparam Axi4PeripheralUartParityType_NONE = 2'd0; - localparam Axi4PeripheralUartParityType_EVEN = 2'd1; - localparam Axi4PeripheralUartParityType_ODD = 2'd2; - localparam Axi4PeripheralUartCtrlTxState_IDLE = 3'd0; - localparam Axi4PeripheralUartCtrlTxState_START = 3'd1; - localparam Axi4PeripheralUartCtrlTxState_DATA = 3'd2; - localparam Axi4PeripheralUartCtrlTxState_PARITY = 3'd3; - localparam Axi4PeripheralUartCtrlTxState_STOP = 3'd4; - - wire [2:0] _zz_clockDivider_counter_valueNext; - wire [0:0] _zz_clockDivider_counter_valueNext_1; - wire [2:0] _zz_when_UartCtrlTx_l93; - wire [0:0] _zz_when_UartCtrlTx_l93_1; - reg clockDivider_counter_willIncrement; - wire clockDivider_counter_willClear; - reg [2:0] clockDivider_counter_valueNext; - reg [2:0] clockDivider_counter_value; - wire clockDivider_counter_willOverflowIfInc; - wire clockDivider_counter_willOverflow; - reg [2:0] tickCounter_value; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg stateMachine_txd; - wire when_UartCtrlTx_l58; - wire when_UartCtrlTx_l73; - wire when_UartCtrlTx_l76; - wire when_UartCtrlTx_l93; - wire [2:0] _zz_stateMachine_state; - reg _zz_io_txd; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - reg [47:0] _zz_stateMachine_state_string; - `endif - - - assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; - assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; - assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; - Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; - Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; - Axi4PeripheralUartCtrlTxState_START : stateMachine_state_string = "START "; - Axi4PeripheralUartCtrlTxState_DATA : stateMachine_state_string = "DATA "; - Axi4PeripheralUartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; - Axi4PeripheralUartCtrlTxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - always @(*) begin - case(_zz_stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE "; - Axi4PeripheralUartCtrlTxState_START : _zz_stateMachine_state_string = "START "; - Axi4PeripheralUartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA "; - Axi4PeripheralUartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY"; - Axi4PeripheralUartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP "; - default : _zz_stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - clockDivider_counter_willIncrement = 1'b0; - if(io_samplingTick) begin - clockDivider_counter_willIncrement = 1'b1; - end - end - - assign clockDivider_counter_willClear = 1'b0; - assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); - assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); - always @(*) begin - clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); - if(clockDivider_counter_willClear) begin - clockDivider_counter_valueNext = 3'b000; - end - end - - always @(*) begin - stateMachine_txd = 1'b1; - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - end - Axi4PeripheralUartCtrlTxState_START : begin - stateMachine_txd = 1'b0; - end - Axi4PeripheralUartCtrlTxState_DATA : begin - stateMachine_txd = io_write_payload[tickCounter_value]; - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - stateMachine_txd = stateMachine_parity; - end - default : begin - end - endcase - end - - always @(*) begin - io_write_ready = io_break; - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - end - Axi4PeripheralUartCtrlTxState_START : begin - end - Axi4PeripheralUartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - io_write_ready = 1'b1; - end - end - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - end - default : begin - end - endcase - end - - assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); - assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); - assign when_UartCtrlTx_l76 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); - assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); - assign _zz_stateMachine_state = (io_write_valid ? Axi4PeripheralUartCtrlTxState_START : Axi4PeripheralUartCtrlTxState_IDLE); - assign io_txd = _zz_io_txd; - always @(posedge clk) begin - if(reset) begin - clockDivider_counter_value <= 3'b000; - stateMachine_state <= Axi4PeripheralUartCtrlTxState_IDLE; - _zz_io_txd <= 1'b1; - end else begin - clockDivider_counter_value <= clockDivider_counter_valueNext; - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - if(when_UartCtrlTx_l58) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_START; - end - end - Axi4PeripheralUartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_DATA; - end - end - Axi4PeripheralUartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - if(when_UartCtrlTx_l76) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; - end else begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_PARITY; - end - end - end - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; - end - end - default : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l93) begin - stateMachine_state <= _zz_stateMachine_state; - end - end - end - endcase - _zz_io_txd <= (stateMachine_txd && (! io_break)); - end - end - - always @(posedge clk) begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= (tickCounter_value + 3'b001); - end - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); - end - case(stateMachine_state) - Axi4PeripheralUartCtrlTxState_IDLE : begin - end - Axi4PeripheralUartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); - tickCounter_value <= 3'b000; - end - end - Axi4PeripheralUartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - tickCounter_value <= 3'b000; - end - end - end - Axi4PeripheralUartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module Axi4PeripheralBufferCC ( - input wire io_dataIn, - output wire io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule diff --git a/fpga/ip/EfxSapphireHpSoc_slb/source/peri_config b/fpga/ip/EfxSapphireHpSoc_slb/source/peri_config deleted file mode 100644 index c0743d8..0000000 --- a/fpga/ip/EfxSapphireHpSoc_slb/source/peri_config +++ /dev/null @@ -1,8 +0,0 @@ ---peripheralFrequency 200000000 ---PeripheralClock true ---uart name=system_uart_0_io,address=0x10000,interruptId=0 ---apbSlave name=io_apbSlave_0,address=0x100000,size=65536 ---watchdog name=system_watchdog,address=0x50000,interruptId=13,prescalerWidth=24,counters=2,countersWidth=16 ---gpio name=system_gpio_0_io,address=0x40000,width=4,interrupts="0->9;1->10" ---i2c name=system_i2c_0_io,address=0x20000,interruptId=6 ---spi name=system_spi_0_io,address=0x30000,interruptId=3,width=8,ssCount=4 diff --git a/fpga/ip/gAXIM_2to1_switch/.gitignore b/fpga/ip/gAXIM_2to1_switch/.gitignore new file mode 100644 index 0000000..4e31dc3 --- /dev/null +++ b/fpga/ip/gAXIM_2to1_switch/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!settings.json \ No newline at end of file diff --git a/fpga/ip/gAXIM_2to1_switch/axi_interconnect.vh b/fpga/ip/gAXIM_2to1_switch/axi_interconnect.vh deleted file mode 100644 index cf9993c..0000000 --- a/fpga/ip/gAXIM_2to1_switch/axi_interconnect.vh +++ /dev/null @@ -1,2 +0,0 @@ -localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h10000000,32'h0}; -localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd24,32'd32}; \ No newline at end of file diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v deleted file mode 100644 index e89ce24..0000000 --- a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v +++ /dev/null @@ -1,1349 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _f860ac11fa8043be8fa45e244a8a89a5 -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gAXIM_2to1_switch -( - input rst_n, - input clk, - input [1:0] s_axi_awvalid, - input [63:0] s_axi_awaddr, - input [3:0] s_axi_awlock, - output [1:0] s_axi_awready, - input [1:0] s_axi_arvalid, - input [63:0] s_axi_araddr, - input [3:0] s_axi_arlock, - output [1:0] s_axi_arready, - input [1:0] s_axi_wvalid, - input [1:0] s_axi_wlast, - input [15:0] s_axi_wid, - input [1:0] s_axi_bready, - output [3:0] s_axi_bresp, - input [1:0] s_axi_rready, - output [15:0] s_axi_bid, - output [15:0] s_axi_rid, - input [255:0] s_axi_wdata, - output [255:0] s_axi_rdata, - output [3:0] s_axi_rresp, - output [1:0] s_axi_bvalid, - output [1:0] s_axi_rvalid, - output [1:0] s_axi_rlast, - input [31:0] s_axi_wstrb, - output [0:0] m_axi_awvalid, - output [31:0] m_axi_awaddr, - output [1:0] m_axi_awlock, - input [0:0] m_axi_awready, - output [0:0] m_axi_arvalid, - output [31:0] m_axi_araddr, - output [1:0] m_axi_arlock, - input [0:0] m_axi_arready, - output [0:0] m_axi_wvalid, - output [0:0] m_axi_wlast, - output [0:0] m_axi_bready, - input [1:0] m_axi_bresp, - output [0:0] m_axi_rready, - input [7:0] m_axi_bid, - input [7:0] m_axi_rid, - output [127:0] m_axi_wdata, - input [127:0] m_axi_rdata, - input [1:0] m_axi_rresp, - input [0:0] m_axi_bvalid, - input [0:0] m_axi_rvalid, - input [0:0] m_axi_rlast, - output [15:0] m_axi_wstrb, - input [0:0] m_axi_wready, - output [1:0] s_axi_wready, - input [7:0] s_axi_awprot, - input [7:0] s_axi_awcache, - input [7:0] s_axi_awqos, - input [5:0] s_axi_awuser, - input [7:0] s_axi_arqos, - input [7:0] s_axi_arcache, - output [3:0] m_axi_awprot, - input [15:0] s_axi_arid, - input [5:0] s_axi_arsize, - input [15:0] s_axi_arlen, - input [3:0] s_axi_arburst, - input [7:0] s_axi_arprot, - input [15:0] s_axi_awid, - input [3:0] s_axi_awburst, - input [15:0] s_axi_awlen, - input [5:0] s_axi_awsize, - output [7:0] m_axi_awid, - output [1:0] m_axi_awburst, - output [7:0] m_axi_awlen, - output [2:0] m_axi_awsize, - output [3:0] m_axi_awcache, - output [3:0] m_axi_awqos, - output [2:0] m_axi_awuser, - output [3:0] m_axi_arprot, - output [1:0] m_axi_arburst, - output [7:0] m_axi_arlen, - output [2:0] m_axi_arsize, - output [3:0] m_axi_arcache, - output [3:0] m_axi_arqos, - output [2:0] m_axi_aruser, - output [3:0] m_axi_awregion, - output [3:0] m_axi_arregion, - output [7:0] m_axi_arid, - output [2:0] m_axi_wuser, - input [2:0] m_axi_ruser, - input [2:0] m_axi_buser, - input [5:0] s_axi_aruser, - input [5:0] s_axi_wuser, - output [5:0] s_axi_buser, - output [5:0] s_axi_ruser -); -`IP_MODULE_NAME(efx_axi_interconnect) -#( - .ARB_MODE ("ROUND_ROBIN_1"), - .S_PORTS (2), - .DATA_WIDTH (128), - .ADDR_WIDTH (32), - .M_PORTS (1), - .ID_WIDTH (8), - .USER_WIDTH (3), - .PROTOCOL ("AXI4") -) -u_efx_axi_interconnect -( - .rst_n ( rst_n ), - .clk ( clk ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awlock ( s_axi_awlock ), - .s_axi_awready ( s_axi_awready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arlock ( s_axi_arlock ), - .s_axi_arready ( s_axi_arready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_wlast ( s_axi_wlast ), - .s_axi_wid ( s_axi_wid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_rready ( s_axi_rready ), - .s_axi_bid ( s_axi_bid ), - .s_axi_rid ( s_axi_rid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rlast ( s_axi_rlast ), - .s_axi_wstrb ( s_axi_wstrb ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awready ( m_axi_awready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arready ( m_axi_arready ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_bready ( m_axi_bready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_rready ( m_axi_rready ), - .m_axi_bid ( m_axi_bid ), - .m_axi_rid ( m_axi_rid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wready ( m_axi_wready ), - .s_axi_wready ( s_axi_wready ), - .s_axi_awprot ( s_axi_awprot ), - .s_axi_awcache ( s_axi_awcache ), - .s_axi_awqos ( s_axi_awqos ), - .s_axi_awuser ( s_axi_awuser ), - .s_axi_arqos ( s_axi_arqos ), - .s_axi_arcache ( s_axi_arcache ), - .m_axi_awprot ( m_axi_awprot ), - .s_axi_arid ( s_axi_arid ), - .s_axi_arsize ( s_axi_arsize ), - .s_axi_arlen ( s_axi_arlen ), - .s_axi_arburst ( s_axi_arburst ), - .s_axi_arprot ( s_axi_arprot ), - .s_axi_awid ( s_axi_awid ), - .s_axi_awburst ( s_axi_awburst ), - .s_axi_awlen ( s_axi_awlen ), - .s_axi_awsize ( s_axi_awsize ), - .m_axi_awid ( m_axi_awid ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awqos ( m_axi_awqos ), - .m_axi_awuser ( m_axi_awuser ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arqos ( m_axi_arqos ), - .m_axi_aruser ( m_axi_aruser ), - .m_axi_awregion ( m_axi_awregion ), - .m_axi_arregion ( m_axi_arregion ), - .m_axi_arid ( m_axi_arid ), - .m_axi_wuser ( m_axi_wuser ), - .m_axi_ruser ( m_axi_ruser ), - .m_axi_buser ( m_axi_buser ), - .s_axi_aruser ( s_axi_aruser ), - .s_axi_wuser ( s_axi_wuser ), - .s_axi_buser ( s_axi_buser ), - .s_axi_ruser ( s_axi_ruser ) -); -endmodule - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -k0MNGAL+siJuDYrFA58rRJscMTUE6hiuNEylu7uA+mdVk/vCPJpUprjqZIgJ75i6 -csRX146zVh4AUQABC09rbvto0kqPbqsZwZGmdOm1W8NmGZIXLCsG4MZs984TiToI -QMOSc+XFr9GVx1rFODfIQCsRVOla6WZCpHrBZzFjmFwY4t9fXFQCs5fSkNbGyG6v -8YDvdegFPMYp5Qu9ccfxeosyrpdCBompAmWscbYmzMrmyFiInvb8Y5dyqCuve1NW -jirl6fz1954ypdomnZDn+X9k8zTCJAxovyf9Qxk6Q+/Pf6e6yRqEYBxT7dtZhWRG -tEQdKP3bt5KBf+EuwdVLuQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding 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-OAu6M+ioz+nfZk6rwKkJjrU28weaeNKuNtCQOwbaS39NwTHRNDybrXbAXbso3Izx -hHULq89G/WE7fXIJJ0uNZj/cmIVk3lVF6/9zsx2+nHv/XUIhJZx9EG5LfBBVc6qr -CfMjv+9oxgyUl/uPWDBsm26tkTV3DbbHeU//M/nf4KYRWNdwUirBLfeGqxXgdZFH -9mDPUQ4z6WmHHr3T8a0VqhMnAY9JZPZWtcaMhdhuEyEt5JTTJAmmO/m7cGRh+U9j -Oylxf2Mb1LOHffkW1XhJrQ3bDYFPbrrvddxJb7fYr43RlXkG/NtCA0CR7fzBlhtw -oML9Tv6EfavyLW/lnsOYIqZT3EexL37fh5q/U6iFfb2Fi4yP0ihSU9TcISR8bkn0 -`pragma protect end_protected - -//pragma protect end - - -module `IP_MODULE_NAME(efx_axi_interconnect) #( - parameter PROTOCOL = "AXI4", - parameter ARB_MODE = "PRIORITY", - parameter S_PORTS = 1, - parameter M_PORTS = 8, - parameter ID_WIDTH = 8, - parameter DATA_WIDTH = 32, - parameter USER_WIDTH = 3, - parameter ADDR_WIDTH = 32, - parameter M_REGIONS = 1, - parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, - parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, - parameter STRB_WIDTH = DATA_WIDTH/8 -) ( - input wire clk, - input wire rst_n, - input wire [S_PORTS-1:0] s_axi_awvalid, - input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [S_PORTS*3-1:0] s_axi_awprot, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, - input wire [S_PORTS*2-1:0] s_axi_awburst, - input wire [S_PORTS*8-1:0] s_axi_awlen, - input wire [S_PORTS*3-1:0] s_axi_awsize, - input wire [S_PORTS*4-1:0] s_axi_awcache, - input wire [S_PORTS*4-1:0] s_axi_awqos, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, - input wire [S_PORTS*2-1:0] s_axi_awlock, - output reg [S_PORTS-1:0] s_axi_awready, - input wire [S_PORTS-1:0] s_axi_wvalid, - input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, - input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, - input wire [S_PORTS-1:0] s_axi_wlast, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, - output wire [S_PORTS-1:0] s_axi_wready, - input wire [S_PORTS-1:0] s_axi_bready, - output wire [S_PORTS*2-1:0] s_axi_bresp, - output reg [S_PORTS-1:0] s_axi_bvalid, - output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, - output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, - input wire [S_PORTS-1:0] s_axi_arvalid, - input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, - input wire [S_PORTS*3-1:0] s_axi_arprot, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, - input wire [S_PORTS*2-1:0] s_axi_arburst, - input wire [S_PORTS*8-1:0] s_axi_arlen, - input wire [S_PORTS*3-1:0] s_axi_arsize, - input wire [S_PORTS*4-1:0] s_axi_arcache, - input wire [S_PORTS*4-1:0] s_axi_arqos, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, - input wire [S_PORTS*2-1:0] s_axi_arlock, - output reg [S_PORTS-1:0] s_axi_arready, - input wire [S_PORTS-1:0] s_axi_rready, - output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, - output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, - output wire [S_PORTS*2-1:0] s_axi_rresp, - output wire [S_PORTS-1:0] s_axi_rvalid, - output wire [S_PORTS-1:0] s_axi_rlast, - output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, - output reg [M_PORTS-1:0] m_axi_awvalid, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, - output wire [M_PORTS*2-1:0] m_axi_awburst, - output wire [M_PORTS*8-1:0] m_axi_awlen, - output wire [M_PORTS*3-1:0] m_axi_awsize, - output wire [M_PORTS*4-1:0] m_axi_awcache, - output wire [M_PORTS*4-1:0] m_axi_awqos, - output wire [M_PORTS*4-1:0] m_axi_awregion, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, - output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [M_PORTS*3-1:0] m_axi_awprot, - output wire [M_PORTS*2-1:0] m_axi_awlock, - input wire [M_PORTS-1:0] m_axi_awready, - output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, - output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, - output wire [M_PORTS-1:0] m_axi_wvalid, - output wire [M_PORTS-1:0] m_axi_wlast, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, - input wire [M_PORTS-1:0] m_axi_wready, - input wire [M_PORTS*2-1:0] m_axi_bresp, - input wire [M_PORTS-1:0] m_axi_bvalid, - input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, - input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, - output reg [M_PORTS-1:0] m_axi_bready, - output reg [M_PORTS-1:0] m_axi_arvalid, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, - output wire [M_PORTS*2-1:0] m_axi_arburst, - output wire [M_PORTS*8-1:0] m_axi_arlen, - output wire [M_PORTS*3-1:0] m_axi_arsize, - output wire [M_PORTS*4-1:0] m_axi_arcache, - output wire [M_PORTS*4-1:0] m_axi_arqos, - output wire [M_PORTS*4-1:0] m_axi_arregion, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, - output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, - output wire [M_PORTS*3-1:0] m_axi_arprot, - output wire [M_PORTS*2-1:0] m_axi_arlock, - input wire [M_PORTS-1:0] m_axi_arready, - input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, - input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, - input wire [M_PORTS*2-1:0] m_axi_rresp, - input wire [M_PORTS-1:0] m_axi_rvalid, - input wire [M_PORTS-1:0] m_axi_rlast, - input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, - output wire [M_PORTS-1:0] m_axi_rready -); -`include "axi_interconnect.vh" -parameter S_PORTS_WIDTH = clog2(S_PORTS); -parameter M_PORTS_WIDTH = clog2(M_PORTS); -parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); -parameter IDLE = 0, - PORT_GRANT = 1, - ADDR_DECODE = 2, - WR_FORWARD = 3, - WR_RESPONSE = 4, - RD_REQUEST = 5, - RD_RETURN = 6, - DRP_REQUEST = 7, - DRP_WAIT = 8, - END_WAIT = 9; -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -f0DVmU/kdU862C3ryhjQlDsM4c/0bG91GM/Tt0YfOziNIhVBbdZsoYW2RTSSEC81 -yNXUBt7tFmZq4YDopiOye7MWsFmf8WWRQEL3slo6DkYqzPlqCgnjys82AVws5Cco -WGW89TXAcQAYHJy7oG8Ae9oSMdLa3PIQNp7mSA6rz4RhAKHQyvxQU3wr0zXDmYKl -CeyI1ZIu155HAUZL2bXguauGtJWtwaTXIrQO4i5/hXied5l3pm8lCdXsKbM1Enxx -V3E/sk/RBAVETx2fmYxracwCdN363LHRvYHyP4b2qkmUndhj47mK2s4d6wc/G0IJ -HQRhooSUf5bQscVy4yyOxw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 24464 ) -`pragma protect data_block -VTq/qeL5rbYMXcLz0pVnq2QU7OySLW7WR1ySFBochA6uqctGyUZMjS/Pnq7DeDQA -s5ClOKMV4s33FMhzgVOQol94f7qpRytPtHwO4wJfN4F2g5QpANsEk5OSaLDZaL+T -9JNTHQOahODVVMjsEwLu3Hf3nxQqnUpY1Jq2hY3IPT9HQw+jYUbU1mwaaPtk3z/B -wfByi6gTuDXLRhTsDy9zF2v2hyVz2yDuu+x9TSJkxCf5Ivowir1LIvj5/3PTq70h -N6f3RfvSBCkVywuTW3T7/OhSi8wnLfdctcCOumE1svbUYFgxg4J2eKZs7MjC0kx9 -BSZcpQPmbuAEPr0X4s1LPhIA3vVVwZzzfsgimy/Xg5Jay4omrboBZMNf9zoz/upT -CWeKBGZMPg7uyDy+H3GpdRNVVeOleOFSVrU/4KbsSuM7/fgKqbwL1vbL3FoZihPh -ldxqCnYv2m//sJpbeK3FtM5xLVdzq8u7WgS2RNd0wbzqdcIbA5ahg4/wV5r22Zo3 -pDP2uVlZvB4LOCQM7VnNmxqVSUNOdZrdkfxscccugLwsZ/LRvxbuw3GVqzFEQGGl -FBnm83T00BwwWMh3yKaRmz9mYY8xXcUOaZ9cgJpRVvfKPq/yHCtnHgXpEEkbHFoC -p3eSX44fIQ/EIHBkJ6jvFyA61OKdjC0gsAj02XudRxsxq76JhRuRBETksNXiKo1k -txGlub+1WwXw3GYTDyjs23iROrf853eo1PTW2BocqDzdb6AFB8CkhQIM8lKkRJFe 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-r5ExI1pGNSH9//Y/MGfi0YdGasyURchybzAFBqBPQncYoJJd59EuuFvDKe61vqnz -UwmT6hBjVltw3wo5ZO/zy2s7IrMTq0ZNJYlNgN8B8ZA1j7HuSq4/bthQuhm8gEZS -cEBEpVMB8POKzvB68i4w1+1P2TLDbdJsTG3HWvqKBmmgGhmAHGLDymLKh8UTu5ke -X3aA+skwxfifnzgVnv+xKdc9DEWimIE1fNU4LVR/4iiMSYDpQeQEEaHY/JbPxt9o -5ACEZkytoNFw9QqC2NrKI3kQ2q/kz2JsVFR/sPuBBCN5+JI6121bUy1O95B1JWjr -dbt6UQMAbXHqycQ86oOXPaqUJzqPRAcEGaK68OlhfxqUo1bgtLoiPkHNxAPQqKLi -W2Olki0g7Z9zVzaR5/cublzSgvh7JWA622Fj6WP5h9hj31H2rp+mkLwBBxDIWW6V -AUnm+fOWA/rYPabXn7kvoEj3h+tt4f6whrN3b+rLNBAgZN+YX+cGTJPTbfEo5RWv -DQvhAYU1uIOTF5KDtDjR/jOrRqV+eXmsgkhq5E4J93wKRY2XuMjSZPbLB0GeycY3 -bLh66SPgSabSAkWmBAGAZN1F7dY4MO9dw1pD0S6p9gGzYeoUpExc9r7mMDan26qm -LbNSMaUY0hoSQ961AiGdxsFbVyiBmdOBLBgcPnv6XknWUz0fKOs9wILctT0BX2k/ -kZf/9Rf1daeB/KsyaCiPYOPkX02a61xXAshEi42jlyaSAsul/47oYYso7HVVoqmw -mKmOBdbMjiJk40oj6GzQWrfPsnssygo9rIEMMRP2452xqWYBfEpaxxNlswnT/K/a -EUEnCk3Jhrifsq+nNy+5QfgAA8SY4uCoKAs29r71o4fEdsbemsnHMFcPvxx4SW7y -uTRODq+RN6LasiF4kuEaoVY3dpY2GZ66nLzfw4Qwil40dyiTymb//VVEVGmk05xo -Uk8NgeWE79/gaC/o8Qa/qu1KcTuCpe1hQoLWt2ynxTNqFr877AF8+r0teqM6dQKU -sMnZJyhRDWAK8UodSoddJO5EXv/lVPyA488s0BhIYieS/RsRjTg2PDCM3kFpWRiY -6Sgu3ZFqj8duLmBMTqJzlToqEpG7fEWwM7Fny6qnum/kpbgTTO/chlDhxrPC2zlm -JTIkg9TGQu9O0qUTDRoUnPzaeJDdeqDaoZyZBAw4k2BRxbFUaZo3tA7UQhfNuo2b -f3cV5sXXuzNfnp0ze9jMkbd/QlqcBoNB7hzLkHwhfYHIftcRCkBpb9QKJpZhEEdl -QT3oZFQTdOjruzXBgyP67mEfeyuQUgFkSn0w8KrtG9NRL6MbTGZPeNQQHQ+4jfCV -5+t9kr6D2ghD35b31kEGYayjMyb79CwVAlWly2D/RkLydSbvGuJ7/S2tUe+wbAA8 -48ZzwvsoEYAShvffELPQyQWUrej1Fbv9bApqnYdWhOwixsolF7sOQoW1SO/EzBdt -dbXRDBkjVAm5GvXvON5lPWYvSkdmaYfIPAQXRfuarloErf7TIklFTVEmKJovkiOg -mxBvBVgrAJZMATPlMz1Xdvf5CwIfPFm/PboaWS1Q7/mzlUSjBSIdPJQVZQ7S2BQw -qLGw9gKVLlwEiokuNvSL6AXYDlxd6nCSyOM+nb1QHyfmt7dMrFWor67PDTC0lwjU -9zcMAWrVQOFDeKWV3aa5LOzOvZBWml74NUoj3NLyWEarA0phv3WMltXyYBjNGB3f -TB1SgPqc6sfTPeiI9a1B4cve2J8zRA3KPoKO3KaXIrwOmDpgsC+2TJ2eEpmL032d -Yg6UJzltMqJ51MjVLlXXbr75yiwtL5CZ4o9OPMRCOdB4JERkq6rNpCcNHg6Qrmae -WxLl6ObOV53td0Axcqu7/1d/ywnObMzZwQueTEcDK+IoWkvyCFspoGQGJSTdrCln -9U/fwZ1Aw573Y8yV23mCoVz+46CizX1R0tt8RsiUUuJRedZuXpdgmloXHSwHqVir -4TeoeKbJ5TabI9wAUk5DudmB5BBA5WQUXbk863Vmp6ZrYuTLfrMjZIX9wugW7G99 -XjupmycimgGdDcwkPXsuhcn+y+kypAeSBT8BmORPoMB3GBQcBFCpksISgnzfj9Df -f88VaFEwPw6WYPsr5zD3qmYV2Wcsa1+AXMyVWEud3OibijB/ydovxfhoylxzubgq -c5dWawXZrm5RAj6OLUtonq8ExeCxZUVesAT41fPbsmxPMODfaNW5FbLVC3kqoKSR -/vBOG3e/0w29HIfCe3INg/hQVqRtqNawZuPB3U4eg6mkDZO0y9woSZUx+4YHiEnU -NTXJ5dCxVSwAc1bY/Ip6OLqp0SL7pbJLVLOZcdpgE5tqhkRt2TK3t44YBFUW+niA -+7vUO6hk9FiP9bQI/e7mVqrPotPqBtZ/BYUCVLnHL1JkdNsfhSH93PbRBOL30thr -a/CDhbsHwqYjqkrPHUZbNL6xs3s1Ebn/iXs+MoUC0UijkUhThusSGW3zplPE0G54 -0jWIUjvdB/4anXrEkP0+JFchB+2p29bDA6M6GqPIVL5rQWDi/hZj7Jo0GIXXkCmh -pvHuQ5Figaz8huMCbW3V2iIeCWQtEZCIlkqcyGu/srkMp8Qy6LofUqNL4sudqhPx -f4uyi9jp8NVnv5ItQ16FzQScH1btWx693lWnmb0+Z2LTNY3edWuP30Cn2zr10hQO -93mjE8j8xiqRmhLimsfa03ja3y1M5RFuYdaN/LBTd4fTOYAzlN0jlO+qU0fuEZpk -uQWrVWtrciib0QKfC1g20lTslFmwF9dosu8yjarIqZXr+RJVRJ+dXzaC9RXCMNZb -65UcvJNvzjdQOIPUdQcFIuSQwWUnMe5P8kikQsxEZuT+BErj9Pt17T+HPstvcsd4 -mLxzNtdOSZuENCu1k9eImFqEVVl2odtXcLBE6f8fS1rDtjNUupb+m5h+WR63QHid -eDln4z8ShnayiKhW6xp0jj2dUvWnOyhQwZWRP8m/EmfeFO7gYiIw1SxDD/ZqH364 -PzVEZruTbQ4jUKjpfHxf9WBgIVrEYTPTBjPjxaZbhfA= -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -gQ+VauIuH+g40FNOpVzoPSXPaSSXzZWh6rE+e4zt/Higof5lTVqndEO2y+vyS/HT -Uz3/xsHmLa5/hfJOzrQ2WAbWJcFOc0pzmbDqYnUgEw1W4IUS1qcjifpXTLdxvwfy -rSWd00QRecQN7v+pyLFb6xf5TELzzsB2PAr6/xlRVs03sGcC8jpFMP1gppLRrh+C -xnDjMIBVdGmu01tJ1gcEY/913addbws7HLgMcMDLft0U/4zTbjE/rrDoC7+eO+3k -z9ZPUNkRvEPxurfsVZfIuglJuZJSqyaB+Khmc5Q1nMDb9IswcttQUM3RtjEksR13 -Y4OcKLh/ejWsVorB6JLJeA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) -`pragma protect data_block -fo0JdXfIQsWgrENhFGo0RRW9s/IV4eGBK5upzSxFjRkxTj+wCit1QKkd15jJgDu4 -P06Rnw+P2/Cu/tkXRjH7RGfSCa1EZ08cwLiSykEmyb+qQo8wTkOBh8KIag5m0P1t -XTuNeK4lZP50EUwL/4wSSMPuRtdpIAF+0PAXjdoge2gwhduxtVQZpgPO12dwk0Wo -Qyfuxrm/7iyjiETt18QCBk/PXC9JLX6a9hmtr8ujb+7IKQJFj1S7F9WxCZ1yamDs -e1D+l34aYZ5r3sBbAysWrg65oN3fAAd6bhptfeU2+BDBA8oKIcTClBK2f3pBUPul -8YV5xUU0+FGat/Rjkm2ZmKKpm9JD+w7ufesbJ2fqRCCex08yynx+EuV6lNupQQk3 -UbxIK2+04eVmLtY7V87103cxyVnLFXqAQY3XaG0AWBpO2Ew1NwH6CU4yFpyUAC84 -Bjztc1mHKONeueopzONq61tRDqarI0ex6IhDy04D9/zAOhMyBrEHzeR0UozXtK6Y -TB/qqFBgJmagIMQWcL03s2FYWQgGUU3PRQ4JiB57ubJG6H64M9UJUMXI7VXW245F -S0oLuBSWchTwY4/6zvioNieoCZgdkxOTUqHNuV4Zf7Epcgh3IQIZRzjBSpah3skn -kQwLdkHYbh3EzBAN0L4lF8u4LE/8SqwLPpsl91D8Qck2jzgNTYnbsG+t2tsum6n8 -wYvw9H2G6SCXAimDrg2Qy66lpdDA8XQf+1Pu8sYKlEd3GH9lQyGX+l4gx3OLuOtR -fAlYbOhHnFRDXMNE9ZG/I8VKDFToJD1/SjoKUnrz4TdMcQZn3Asrj6LyXsw5CHgd -zhf60BREHK5nXIJRGkqTlV0OyCbaEe0yTgmpWapYbnUcpX4UNu07ijUdSbUBReil -f2PULQwchd1Nh+nj49FyRm0SU4twHeYIMoSC2sMtPiJkuqAZPugzpBpKZUPnKzDd -VmHxPV5Fl4haVbGLfQj4rfl6Mqpqk2DLOiPmwiXnf7CTAjpnwNQ07KsBw6SKxLAe -YS+1RZFe1JQTA73Dv+hAjOEby2uC1tz9V61abAakI4omdhXK1WBGS7AW7VIkOhsa -U2d43C1vqygKdJzTQVB3SVqswMzruIiClRGEypfl8F1L7BIegRA7y6KJYY2lQ69u -7eDX8XmDYmXDiWgXqtWRALbhHrDi8EwOCp5Tts6KK1q+HZNB6UjiGUrGZ2/EhU4H -rNhfbS8YD9wTQtEs/QCi40wIeLIYjIf429BBIRU8k3na6ZwzGLdfxJnqsRLJ6E7X -aCiJk8iag4Wfv0HsAb9J8vDUKzzLHS5OYlHmEss6CTswBAYs7u8/UF9rlfvXy8Mb -z5tfh7xCXqOQpY1gF85w0agvdFKLhhUzfB2Y/XiH+P9zw8608Q4B2irkUuj0fbhU -/VGCOg52ghhNNkaio6JDtzCj/4nMf3QJwdYnJNTiSWLmN/D4rgU8FE7RObm2foEA -5qemSiCt9nYnRGtaRQ0jFh1zieourorN3TI49Lfh/b++M/Hq8OUZh7Uxs5ni4scB -RqEGxATE+29gCCCJ1S3HVi7fcit9xh2mupZnT+m3qHM+Jt01sv59AUJ/UFx/cNYz -qo1oB/NkzOstxVDMlcp8bOO+elF1X4n4wKeC0g/eMM8C+ffQiVT7Rqh2mYLgXQA7 -BhBS+E0RB6UhkxYPnRFEgtk0VLL54VPEVDTINYlLs+L3ZsWwYJs39Gen6vvvepYy -bujDTnnouQqtvD9ok3pkbA== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TpRHXtmr81JyoWaAtQOsoLu44jF5UvFDPdO5/CllOd3kdY7PwU2fkKx7bS6RlGe6 -282Wvc58pPBGh6uImNRfZkaAKTaspN+giuR1GHAo4nfIKi92dgY2DTW5JbEU67ml -1IGNiK4su606fm7n90PZ69MZadoZPNpUxZxzYbSs+I39eZWsgU+rtoUE2d35qjdW -UyorSD+O2F5Wv51CWlcWJyscNK886BFGFi72CtEY8IdYcolZ7hcONOhQT5jbhGWK -UFFTqjnMO6iVrEodujVvUgcUtFQSTl5/oHSkmacP7CSADA82+06uIHf+rByqHGTp -JNgtSAVN844IRP39n4T5EA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) -`pragma protect data_block -dW2N/rFxim9wkWiMqoV2KfFOb7ryaosiEjsKQ5d9XAY99bfh9dHXfxBwbIc/m/4e -C1jjMt+51lGF8ncrYuentPA6MwNEfk27Jwvqv9/Trdq+kOdiWuYmhbZxfJC2L3WJ -BzjhoC/o2ZNSFpgmDKLxln0/pf6iM8sUIldzujq1RDEv/fZvcQ9IXZ0c0cgbXEWf -SfOaD5E2qBGsljqkzqzIKjaiTPnGPsKJ6cZ41jLGbcm+AcbSk6th9Vdeim0hCA9t -HjX+E+Tq77j/ivdd5OuzAehdPAg3IiMJTQxdTNsI3km5GzvomnmxK+pG8L9aCaAh -o+hCsSXZD2QyVCRFZjVT4s0ltvRto5PgSDzzqm1N69eUDE/spFnroMx1TQCLbjBT -zS0w4mCeLkzFlxc0DJduqQlnRMlA8AnBFujD/Q2OAdVMSHQC7YscXbPzF31GPlqx -Eg2t/VyotaMLOGG0wG7ax43UokgdGbSuphzh14sCh3ZSbPueJQLw2MQwK5M2gcvg -/OCrpP6ZQDt10hFz8i/uLrgNIWA93ZzqujdUnYXBBCwUzRJEyHSLnlXX6Ko3rzE5 -ct8FuQPGV8vF+t6COL2nQ0qaq+23R5E5PuFtEMyRrDT+p8iXZasw8RECO0NyVnEE -YuX0T1i6imJS88oOkLq+ywGLgMFC+4O26DIlpPh4+UJ/fnt/pVOADhugk3UeF+QA -ZDR1sgxihCZe9rP7QzVpjm2tDiaPt+fklsKWPprWH2eAiuNaia9mSSHNYGF2x2lD -9h3FKeV/2LSUG5mOvvl3sgKhV2fY0MuldurIH+utuZSPbknY3sebf3BKCntClVOm -6zvNgcnFtvD2+A79A8sltui4gm5GYPS2b0YDfju51vT0iTsCH30p3LWNEG/zEtf2 -48bHsr15Z/CgHdw169NsY8B3V8RHxaJP+T6zbPLBjVmRFbuTftozxf/dv+m7Rgl2 -3kmwmDxauFLyklSGjQ352H678ASYS37eMG1wvn3akQjYEAsrQTdi1sxmk6SACmSb -Ko7v8gOZpn886AO3O4V3iIggxtfGIfRMtOXcoEIX6dRl5GdFkcASHigHwoV56yRO -tlfJEHrrKLKbmqhjLMjDz5jTptQZfwCjZGzki/PYImxPv0ay8+PTa/qXEaJEMsWZ -vWEGZGSO9zphfmPXEJI+qF22X0dYlKGn/U8rzBEsdcxIXyGWQwBJvbo+GhnPURiQ -i1MJHwfOEDztC3XemmsQeaMuSDWZFrnOKXuYkOBj7tD8ir7vJOor8isvwQUz9LGK -g5Vx+0HdaBgE32QEZ/NjYA1V6bM0iUHz9e9qzEVqN/kRww8HFXA6SnpD5lz6hyxy -jFVRtphwYQWmSzwLvFWa2AYQuI4xjU7tJKOCZRqxjD4hiIkjDK6/K/01Gk5QL/3K -12xoSmqSIZRHwxFGBoHiuBmy+wBhSdqqIOdJ/OsoBT+1OwzQ24l0CRjfAk+zBdVi -7A89GoA5JGSeX8OCJopZvuJ/kEWBUL+l+AU3S9Z4l0uVYybFXE7WXuTNCWRjCQFQ -DmofPA/+XPmyr1MT/3DpFQgnMN00C/jJ1eRmmSntrjCcYaPS0vX117igGa1YWfcD -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TBCX5/gAT5S6xdVBuY05hYDsXmHLnm/0Yl4d4ayUlKrDe3IUWB3JcRtZJEwtIwhQ -wqO6qIYs21XvVt74eCxdt1SZXHRXXJiT196fD9q5vFrJxAQqeTDvH51bmshhKW+i -DwXpMTwZlLgBsT2BEP5C0RiiICy9chJTycHB7vHEh6lTXT6S/2H7bweTMlFCh6s6 -n5aHgBbfjk9BYIUSTuEvOxw9Yki0T44zjqGmjZ3qxkhk5Rae8iPLqCnjRTjNfqOE -zQtaoVQW+8NbATVUmZC4WlgxF/J03hq0TLeqLYfcuWR0uH9vLAWsUzHqlGMZvUSV -23zwmB8p0BqUeaj1cllyzw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) -`pragma protect data_block -2OvJlNYOCu/okutbEvWbuQI4X9C4wmVA84hW5XRuqc+R7lDXEYZ89g58fT3Wyd8M -ecpTY/f/5J++NaepFO9rZ71cRzxgXD7ZQypxrBwT8eXz6kwhomKLL8xgQuGMrD2h -002LEC5h770bZFbr2QDl94Kd8oWweGDIcwbbPgGtsgfsrwnZq107rvdgRLsvDJ6H -A9T68XpAsV83OJOA8hk5S1ytXOtMoD1vxUA9NgZ2d9BBiwxnfNC6r2DYa/TpgT+F -8Dlnu2u3Ch2T50E1FvIsU2NsOkKdsN8k6Nmhr7J+mWrK8q1RSElNbQt02yIshAzD -fz1m7maxuzNvKiofs7xTJYH5Zl3jsRgP4i3jUPcFIYQTdju0XGFuzz4tT0y3o98B -wJPQRdZzLdAIRwwOeqCGe94DNj6v4B0lCOW+L2I2xO/Zd85RIWk0KQ11TMBxIioX -lElgvMwoYdOobLmpseg4vchu9jvsSwd1ET14HpSefqoM8cHFSvGA3j0KpwHUHD6N -cAg2z8pkpvWyZBxPOnKrjjHml3gwE3q+X2mtD1ayi41L4xn6E8czI/znMUiRwwcz -u/UG8I65XcONtBswjX1cTAad9X9cP37rq7ly/mnCVaQ1fwdx50rBY6tOiF0jiVR5 -JjSBl4FkBYJu7kHqA7DcluE9ATZ1+D+BIfESxs4o+MIGiPbk2VMeafwTD7GkJFOt -pp85p5WDA/qQLIA+aQsaHfBRLInMjsajsBU1Nnr1Z2FuT4dNgRDU1JiEJoiGBh4S -RZzlhgVKqLQdDiC5KHU60BMuW3u1CxkP6BLofYO1/DTsIOzKRlb9s3+Bx2RBLO+X -LpI1kmPdmyjjLOe9xPxUuWAlk4Ona2bF7SOrCRKslzRwj5WK3kdfynnrqi6fyg/g -6RtRb5T19kv8xkX8Q0Nu2f6aIj9NFg8R8LJhXh6X45cptFvZzqgrDrKouB2qeqzv -r/ARvwCCrLhqU1Rwol3o14E8rmlZcjNTDxMVbtGHIC6f+FQD8Ge6dA7TLtOmbzhg -ADyiBfAGChDV8d6/1Hzt1ZCbp6C5hSA43mtpTQYEjZcGds4olsLWRMFlvn6SaE8U -/yc4f8I5aqNLijlkaO5yVtVndDXvrhyJK63yxQ2hv4wjwsq4K2PDQ4XYvUcmKPD/ -XlPlsS9Ze38WOmF18BNsWhFg/X1ZEsnJQZqQFknQ9z/lHiYTcq+HtWHD6JfZzOaM -E3UA8T88Db5hkBxdi+VdfTfF/tcJB9TVv94cA8SuyNnP6Q6AMPtj4AcaMmUbLwpN -6fOz+eRjs375gUjeGtSoPhbJZ6VvJjLK6xs1mDGS9ROACnxpeDCou3/Z35w98hvB -+vycfefBU/3Oz/FibzGZfGGRZxR88DoezSovO8xS1UTztbTV/E3Hf50BgcR927BL -NJGAapWYDd8JtV0BHG5wpaes7/XmU1ypZarztFE+5fUtgzp4AKZ9d8fLPqu7uHyy -VFSlknUG3lKAvV+aTv5kwTm6T24a0lpxxYWzaadSBxuqeJtU7FNijzCia9l+KD/j -MuWIX01bTZapbrnUlFm4fAAgbW5f3nA4jSdhRz4mKzYdZ4aMWDM8hBS+zHKdAxt+ -r3IOTmKOM53qQd6/AzPhoA0A+KC7CNCPEgYxWjHD9LvdybgmZ3XenDSbtLwQbD6Q -UwWAn1xKUS+VTfDL9VkVXP1CneqLQxZtc1Sc/vBPwSJ6+7jAYG5QfCsFKpYk6KVg -WWBjX/iaBk51jQZ/ISopM3fO5XEr5/3lYtazRsrg0f+S3e4Zzo8nxEOq9P5xVhSQ -O7JVUzPKxB+mq8b8+Trp0jpdlwATuoCmknWv7M7xGQxIxgYlBegfgpZNrb4ocJt1 -C2A5oMK874OASkTuFy/CZtTCSKDyyC2WSUJy/ybgFlZWnTyWBNaSIgYpaI2Gq/5N -W2sAGdn2IzwgLXJcE2TeXPkUP8I6D0EvyGS8UJ8WVt4jXlr/F3VEInfxr2Y6siXk -AHHFHgrTgDIGLtO8E808PqkxvLBmGkuPh75G6ryBOPonCZ0aT1e/GX3dbFPpEaEW -llXDZSgbk2fjRwniN+3OtnrHeVbQUlTC3iaVcpJd1hL8XMqXbPIDInH7Hno0Rp0/ -Voc9LaQvrTj/kEwf26rJMPkHP3A/gue3fawMlgP2mdiTeVrBYqtURRsKaMlxgKT3 -3O7Gyd/yxwB05GETZ6zA/3Z0q4ztIi5TZ5m+C2wW+NIXwkcYJdqHOodrO1fkRlTs -npvFlNq1Br3v3gImbnvFaouFkT+542lb5sOY50i4uwrifKPntqOl0n9+dE1pyipU -QURHoCbkL2QR65H1hYcDoLRvhJAfS/oEFf4DSf8HgiZITq5pSvnYcJn76jC0mNiX -9LRJqxBuOkHcdFIbmkvDuwIN0asrQmGQCAsYOOxVA6EpX0XWcJ8dVmRyWbGVZXNq -45wAMvGDj0F6Jm7b2sQ3quJFDXDWvD7hPWp8nLqRDN+P/s9tHqK5LMXPHFdcqMn4 -hKSmCVgEtnsVfWUGyjVJ0Yvh+jxdg3vECIO38UuFBuTGroD0egvsyd7iuwT3aOmn -5YaYW0vHuHERbtLy6AkO1sVVmg18jSH32tE036uQS+LCrj+G0cg6Mf5sU2CHJZA0 -9Jse9KsUSQdI7bnqvPdYIQ== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -eiP/26NloMbfJbEe1aU/cN+AkTVidxKZaNv824TVZXkpjf5L1zEVLf4buBzXwSr1 -MiO1FaB1qgL+ZgKHLwNzc4IiIP0d7qYOaGR46jDr8/k9N2BVxXC3V0wJJ6yhDom9 -O7B9d2Lcm+b0UifdEaFcX3luTwZzXAQW83Bggnm4eVP275Vqog3REHo5wgsstEU3 -AG6o+oVDnNjZTPDPyJ4uHq9bjFFyvY3ga+lOo2iVymecnhCiRtjy3AFtvWBJW0ek -uhj8QvNYf04TXkRXdhdRfq/HDLr3M6Qa7/Xn6vGE+drFyRTL1nmH9wkjBBbD3swn -58tiwvvx3ajgMOCJeXfrXQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) -`pragma protect data_block -z83CFN/6+XAqqlsaR10y0/0TRdqihm7Mln1SErDagYzHq/tf3472iVn71ufDnRwX -XjpfuAMiYkGYL+YySToA+S247ZqaWHze8oceixrYgRvhox5tY82fxq9Fl8kghDLv -SjC2MS3eD6cYQeQLFqzD1Mn0WKOQZFVCku3VAWFB2lduR5mhayfY/Fa3R/W72ABn -Z0d6Zn4ZBsgSyb/M70GpfeksPL4x3rnLEOyMOaWSU6+bpfwlHv6gwzh9HPzLZxVy -08g2U6/uxm0PBfE3o/LncY5k29GaWHkcOHv6VhXh/m8K01MJZqFeBphDIArYoxxq -PWDxAO8AUxxtI14Tgpa2V285dFMvK+4KnQioTwi0kMw0x+o+AprykzkXPkE/VVzK -KXd3WO23uskN1uRWHMVa+YBeVjuyFSDLn3GxfHH9tkFDow1kssYW0TqHWs0aqHah -qnNS7hoeJjqPZiowmyQrmDxNCJSTzH8quhzu6sXOHqjuy3hV/M2EY8gngXNAKKsb -WbOvs5QeFheEcLGYrod/Zfv9aZk0e3y0m11vKOyZVQVGFJQzc1uQ0fLjWrpSt7yG -qya4/JgJ8aoha2vBdN7gKSQ0jQBRSMhhOkv1iunq1iT+1ZETzOdrs32w7jLu65tq -rkZk2Z9PlyyFm4XlIu3ljYIH3Z1F+BdPGXiUKHiLhEHanApDED/zljh7BDGApCKl -t1zRJJjZMckJfWQclrLgdXSejbEhZFqHfgYNQe4ywo4o/SbWaqGvPgahhDBBVxZV -rvCFFNip8ka1YAIM4x0DqYw1pSFzn0sUmEm44Jl+Eo4D5chLPEJnYyAjsKm0nIFa -We3J6DKurh1q/PmPYqN51Vno2A5tlFLR8v6SH4m4qu3V3skZsRF0vR6BGx84VdVj -bN8BlLOwDEGmTO8UZpg5knVPN5bAfvf/kXvbSbr8KPR5NBZRqz3SXFeMxZYBPfbj -GI8S5ZZZeq5AvybyDwwt8BHWypNkKlsr+UxyAt+phMEA8F/U9gAt5r50llYjO4qu -5tLeotWmT7oFHBktGytHHC+gKwtWEMsJLm7+744JbDfnMvdHRr+AQgpYts9jdNY6 -guxuay2WoNBpjmE51Kq8M1xXeO6beJN3h1JAlESUfz7eFKkE8Vkr5Jg6ccn0KUsS -ZZmNyAaAta//k2mRELcX5bJmUCCHy7lAgQBjtv7XZBfyULC/eXy3RUO/ar8/VQKj -wwOLkv6PJN1DfDlpZ+oswIslScrN1ijU4t2buGKO8zI+cQCpYuC9FBN8V8chHOZw -//0ODvW7AEl6D/OUt8ZC6gUirNCSFRQjXz5x+MOrJPH54wUb0gmtQRPSsbnbcm8g -r+J90t6Fz+FSggPmyNbgv8Z+eWprb5Z3QuqJaQlTYxXGJYLXXwcTjZP3Sf58Vd4Q -9PV9zVG1BxTwV5hFTLJrTkIFGs6wyF+96e+3TnhJKuzZ4Qgf0XJPp9crAdiNtxfx -`pragma protect end_protected - -//pragma protect end - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh deleted file mode 100644 index f49727e..0000000 --- a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh +++ /dev/null @@ -1,53 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -localparam ARB_MODE = "ROUND_ROBIN_1"; -localparam S_PORTS = 2; -localparam DATA_WIDTH = 128; -localparam ADDR_WIDTH = 32; -localparam M_PORTS = 1; -localparam ID_WIDTH = 8; -localparam USER_WIDTH = 3; -localparam PROTOCOL = "AXI4"; diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v deleted file mode 100644 index 7c70e62..0000000 --- a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v +++ /dev/null @@ -1,137 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -gAXIM_2to1_switch u_gAXIM_2to1_switch -( - .rst_n ( rst_n ), - .clk ( clk ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awlock ( s_axi_awlock ), - .s_axi_awready ( s_axi_awready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arlock ( s_axi_arlock ), - .s_axi_arready ( s_axi_arready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_wlast ( s_axi_wlast ), - .s_axi_wid ( s_axi_wid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_rready ( s_axi_rready ), - .s_axi_bid ( s_axi_bid ), - .s_axi_rid ( s_axi_rid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rlast ( s_axi_rlast ), - .s_axi_wstrb ( s_axi_wstrb ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awready ( m_axi_awready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arready ( m_axi_arready ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_bready ( m_axi_bready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_rready ( m_axi_rready ), - .m_axi_bid ( m_axi_bid ), - .m_axi_rid ( m_axi_rid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wready ( m_axi_wready ), - .s_axi_wready ( s_axi_wready ), - .s_axi_awprot ( s_axi_awprot ), - .s_axi_awcache ( s_axi_awcache ), - .s_axi_awqos ( s_axi_awqos ), - .s_axi_awuser ( s_axi_awuser ), - .s_axi_arqos ( s_axi_arqos ), - .s_axi_arcache ( s_axi_arcache ), - .m_axi_awprot ( m_axi_awprot ), - .s_axi_arid ( s_axi_arid ), - .s_axi_arsize ( s_axi_arsize ), - .s_axi_arlen ( s_axi_arlen ), - .s_axi_arburst ( s_axi_arburst ), - .s_axi_arprot ( s_axi_arprot ), - .s_axi_awid ( s_axi_awid ), - .s_axi_awburst ( s_axi_awburst ), - .s_axi_awlen ( s_axi_awlen ), - .s_axi_awsize ( s_axi_awsize ), - .m_axi_awid ( m_axi_awid ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awqos ( m_axi_awqos ), - .m_axi_awuser ( m_axi_awuser ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arqos ( m_axi_arqos ), - .m_axi_aruser ( m_axi_aruser ), - .m_axi_awregion ( m_axi_awregion ), - .m_axi_arregion ( m_axi_arregion ), - .m_axi_arid ( m_axi_arid ), - .m_axi_wuser ( m_axi_wuser ), - .m_axi_ruser ( m_axi_ruser ), - .m_axi_buser ( m_axi_buser ), - .s_axi_aruser ( s_axi_aruser ), - .s_axi_wuser ( s_axi_wuser ), - .s_axi_buser ( s_axi_buser ), - .s_axi_ruser ( s_axi_ruser ) -); diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd deleted file mode 100644 index 9adec60..0000000 --- a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd +++ /dev/null @@ -1,229 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component gAXIM_2to1_switch is -port ( - rst_n : in std_logic; - clk : in std_logic; - s_axi_awvalid : in std_logic_vector(1 downto 0); - s_axi_awaddr : in std_logic_vector(63 downto 0); - s_axi_awlock : in std_logic_vector(3 downto 0); - s_axi_awready : out std_logic_vector(1 downto 0); - s_axi_arvalid : in std_logic_vector(1 downto 0); - s_axi_araddr : in std_logic_vector(63 downto 0); - s_axi_arlock : in std_logic_vector(3 downto 0); - s_axi_arready : out std_logic_vector(1 downto 0); - s_axi_wvalid : in std_logic_vector(1 downto 0); - s_axi_wlast : in std_logic_vector(1 downto 0); - s_axi_wid : in std_logic_vector(15 downto 0); - s_axi_bready : in std_logic_vector(1 downto 0); - s_axi_bresp : out std_logic_vector(3 downto 0); - s_axi_rready : in std_logic_vector(1 downto 0); - s_axi_bid : out std_logic_vector(15 downto 0); - s_axi_rid : out std_logic_vector(15 downto 0); - s_axi_wdata : in std_logic_vector(255 downto 0); - s_axi_rdata : out std_logic_vector(255 downto 0); - s_axi_rresp : out std_logic_vector(3 downto 0); - s_axi_bvalid : out std_logic_vector(1 downto 0); - s_axi_rvalid : out std_logic_vector(1 downto 0); - s_axi_rlast : out std_logic_vector(1 downto 0); - s_axi_wstrb : in std_logic_vector(31 downto 0); - m_axi_awvalid : out std_logic_vector(0 to 0); - m_axi_awaddr : out std_logic_vector(31 downto 0); - m_axi_awlock : out std_logic_vector(1 downto 0); - m_axi_awready : in std_logic_vector(0 to 0); - m_axi_arvalid : out std_logic_vector(0 to 0); - m_axi_araddr : out std_logic_vector(31 downto 0); - m_axi_arlock : out std_logic_vector(1 downto 0); - m_axi_arready : in std_logic_vector(0 to 0); - m_axi_wvalid : out std_logic_vector(0 to 0); - m_axi_wlast : out std_logic_vector(0 to 0); - m_axi_bready : out std_logic_vector(0 to 0); - m_axi_bresp : in std_logic_vector(1 downto 0); - m_axi_rready : out std_logic_vector(0 to 0); - m_axi_bid : in std_logic_vector(7 downto 0); - m_axi_rid : in std_logic_vector(7 downto 0); - m_axi_wdata : out std_logic_vector(127 downto 0); - m_axi_rdata : in std_logic_vector(127 downto 0); - m_axi_rresp : in std_logic_vector(1 downto 0); - m_axi_bvalid : in std_logic_vector(0 to 0); - m_axi_rvalid : in std_logic_vector(0 to 0); - m_axi_rlast : in std_logic_vector(0 to 0); - m_axi_wstrb : out std_logic_vector(15 downto 0); - m_axi_wready : in std_logic_vector(0 to 0); - s_axi_wready : out std_logic_vector(1 downto 0); - s_axi_awprot : in std_logic_vector(7 downto 0); - s_axi_awcache : in std_logic_vector(7 downto 0); - s_axi_awqos : in std_logic_vector(7 downto 0); - s_axi_awuser : in std_logic_vector(5 downto 0); - s_axi_arqos : in std_logic_vector(7 downto 0); - s_axi_arcache : in std_logic_vector(7 downto 0); - m_axi_awprot : out std_logic_vector(3 downto 0); - s_axi_arid : in std_logic_vector(15 downto 0); - s_axi_arsize : in std_logic_vector(5 downto 0); - s_axi_arlen : in std_logic_vector(15 downto 0); - s_axi_arburst : in std_logic_vector(3 downto 0); - s_axi_arprot : in std_logic_vector(7 downto 0); - s_axi_awid : in std_logic_vector(15 downto 0); - s_axi_awburst : in std_logic_vector(3 downto 0); - s_axi_awlen : in std_logic_vector(15 downto 0); - s_axi_awsize : in std_logic_vector(5 downto 0); - m_axi_awid : out std_logic_vector(7 downto 0); - m_axi_awburst : out std_logic_vector(1 downto 0); - m_axi_awlen : out std_logic_vector(7 downto 0); - m_axi_awsize : out std_logic_vector(2 downto 0); - m_axi_awcache : out std_logic_vector(3 downto 0); - m_axi_awqos : out std_logic_vector(3 downto 0); - m_axi_awuser : out std_logic_vector(2 downto 0); - m_axi_arprot : out std_logic_vector(3 downto 0); - m_axi_arburst : out std_logic_vector(1 downto 0); - m_axi_arlen : out std_logic_vector(7 downto 0); - m_axi_arsize : out std_logic_vector(2 downto 0); - m_axi_arcache : out std_logic_vector(3 downto 0); - m_axi_arqos : out std_logic_vector(3 downto 0); - m_axi_aruser : out std_logic_vector(2 downto 0); - m_axi_awregion : out std_logic_vector(3 downto 0); - m_axi_arregion : out std_logic_vector(3 downto 0); - m_axi_arid : out std_logic_vector(7 downto 0); - m_axi_wuser : out std_logic_vector(2 downto 0); - m_axi_ruser : in std_logic_vector(2 downto 0); - m_axi_buser : in std_logic_vector(2 downto 0); - s_axi_aruser : in std_logic_vector(5 downto 0); - s_axi_wuser : in std_logic_vector(5 downto 0); - s_axi_buser : out std_logic_vector(5 downto 0); - s_axi_ruser : out std_logic_vector(5 downto 0) -); -end component gAXIM_2to1_switch; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_gAXIM_2to1_switch : gAXIM_2to1_switch -port map ( - rst_n => rst_n, - clk => clk, - s_axi_awvalid => s_axi_awvalid, - s_axi_awaddr => s_axi_awaddr, - s_axi_awlock => s_axi_awlock, - s_axi_awready => s_axi_awready, - s_axi_arvalid => s_axi_arvalid, - s_axi_araddr => s_axi_araddr, - s_axi_arlock => s_axi_arlock, - s_axi_arready => s_axi_arready, - s_axi_wvalid => s_axi_wvalid, - s_axi_wlast => s_axi_wlast, - s_axi_wid => s_axi_wid, - s_axi_bready => s_axi_bready, - s_axi_bresp => s_axi_bresp, - s_axi_rready => s_axi_rready, - s_axi_bid => s_axi_bid, - s_axi_rid => s_axi_rid, - s_axi_wdata => s_axi_wdata, - s_axi_rdata => s_axi_rdata, - s_axi_rresp => s_axi_rresp, - s_axi_bvalid => s_axi_bvalid, - s_axi_rvalid => s_axi_rvalid, - s_axi_rlast => s_axi_rlast, - s_axi_wstrb => s_axi_wstrb, - m_axi_awvalid => m_axi_awvalid, - m_axi_awaddr => m_axi_awaddr, - m_axi_awlock => m_axi_awlock, - m_axi_awready => m_axi_awready, - m_axi_arvalid => m_axi_arvalid, - m_axi_araddr => m_axi_araddr, - m_axi_arlock => m_axi_arlock, - m_axi_arready => m_axi_arready, - m_axi_wvalid => m_axi_wvalid, - m_axi_wlast => m_axi_wlast, - m_axi_bready => m_axi_bready, - m_axi_bresp => m_axi_bresp, - m_axi_rready => m_axi_rready, - m_axi_bid => m_axi_bid, - m_axi_rid => m_axi_rid, - m_axi_wdata => m_axi_wdata, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_rvalid => m_axi_rvalid, - m_axi_rlast => m_axi_rlast, - m_axi_wstrb => m_axi_wstrb, - m_axi_wready => m_axi_wready, - s_axi_wready => s_axi_wready, - s_axi_awprot => s_axi_awprot, - s_axi_awcache => s_axi_awcache, - s_axi_awqos => s_axi_awqos, - s_axi_awuser => s_axi_awuser, - s_axi_arqos => s_axi_arqos, - s_axi_arcache => s_axi_arcache, - m_axi_awprot => m_axi_awprot, - s_axi_arid => s_axi_arid, - s_axi_arsize => s_axi_arsize, - s_axi_arlen => s_axi_arlen, - s_axi_arburst => s_axi_arburst, - s_axi_arprot => s_axi_arprot, - s_axi_awid => s_axi_awid, - s_axi_awburst => s_axi_awburst, - s_axi_awlen => s_axi_awlen, - s_axi_awsize => s_axi_awsize, - m_axi_awid => m_axi_awid, - m_axi_awburst => m_axi_awburst, - m_axi_awlen => m_axi_awlen, - m_axi_awsize => m_axi_awsize, - m_axi_awcache => m_axi_awcache, - m_axi_awqos => m_axi_awqos, - m_axi_awuser => m_axi_awuser, - m_axi_arprot => m_axi_arprot, - m_axi_arburst => m_axi_arburst, - m_axi_arlen => m_axi_arlen, - m_axi_arsize => m_axi_arsize, - m_axi_arcache => m_axi_arcache, - m_axi_arqos => m_axi_arqos, - m_axi_aruser => m_axi_aruser, - m_axi_awregion => m_axi_awregion, - m_axi_arregion => m_axi_arregion, - m_axi_arid => m_axi_arid, - m_axi_wuser => m_axi_wuser, - m_axi_ruser => m_axi_ruser, - m_axi_buser => m_axi_buser, - s_axi_aruser => s_axi_aruser, - s_axi_wuser => s_axi_wuser, - s_axi_buser => s_axi_buser, - s_axi_ruser => s_axi_ruser -); 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-localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd16,32'd16,32'd24}; \ No newline at end of file diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v deleted file mode 100644 index 0040aec..0000000 --- a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v +++ /dev/null @@ -1,1349 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _2bba7642b6c647e08f6a49c8c42e531c -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gAXIS_1to3_switch -( - input rst_n, - input clk, - input [0:0] s_axi_awvalid, - input [31:0] s_axi_awaddr, - input [1:0] s_axi_awlock, - output [0:0] s_axi_awready, - input [0:0] s_axi_arvalid, - input [31:0] s_axi_araddr, - input [1:0] s_axi_arlock, - output [0:0] s_axi_arready, - input [0:0] s_axi_wvalid, - input [0:0] s_axi_wlast, - input [7:0] s_axi_wid, - input [0:0] s_axi_bready, - output [1:0] s_axi_bresp, - input [0:0] s_axi_rready, - output [7:0] s_axi_bid, - output [7:0] s_axi_rid, - input [31:0] s_axi_wdata, - output [31:0] s_axi_rdata, - output [1:0] s_axi_rresp, - output [0:0] s_axi_bvalid, - output [0:0] s_axi_rvalid, - output [0:0] s_axi_rlast, - input [3:0] s_axi_wstrb, - output [2:0] m_axi_awvalid, - output [95:0] m_axi_awaddr, - output [5:0] m_axi_awlock, - input [2:0] m_axi_awready, - output [2:0] m_axi_arvalid, - output [95:0] m_axi_araddr, - output [5:0] m_axi_arlock, - input [2:0] m_axi_arready, - output [2:0] m_axi_wvalid, - output [2:0] m_axi_wlast, - output [2:0] m_axi_bready, - input [5:0] m_axi_bresp, - output [2:0] m_axi_rready, - input [23:0] m_axi_bid, - input [23:0] m_axi_rid, - output [95:0] m_axi_wdata, - input [95:0] m_axi_rdata, - input [5:0] m_axi_rresp, - input [2:0] m_axi_bvalid, - input [2:0] m_axi_rvalid, - input [2:0] m_axi_rlast, - output [11:0] m_axi_wstrb, - input [2:0] m_axi_wready, - output [0:0] s_axi_wready, - input [3:0] s_axi_awprot, - input [3:0] s_axi_awcache, - input [3:0] s_axi_awqos, - input [2:0] s_axi_awuser, - input [3:0] s_axi_arqos, - input [3:0] s_axi_arcache, - output [11:0] m_axi_awprot, - input [7:0] s_axi_arid, - input [2:0] s_axi_arsize, - input [7:0] s_axi_arlen, - input [1:0] s_axi_arburst, - input [3:0] s_axi_arprot, - input [7:0] s_axi_awid, - input [1:0] s_axi_awburst, - input [7:0] s_axi_awlen, - input [2:0] s_axi_awsize, - output [23:0] m_axi_awid, - output [5:0] m_axi_awburst, - output [23:0] m_axi_awlen, - output [8:0] m_axi_awsize, - output [11:0] m_axi_awcache, - output [11:0] m_axi_awqos, - output [8:0] m_axi_awuser, - output [11:0] m_axi_arprot, - output [5:0] m_axi_arburst, - output [23:0] m_axi_arlen, - output [8:0] m_axi_arsize, - output [11:0] m_axi_arcache, - output [11:0] m_axi_arqos, - output [8:0] m_axi_aruser, - output [11:0] m_axi_awregion, - output [11:0] m_axi_arregion, - output [23:0] m_axi_arid, - output [8:0] m_axi_wuser, - input [8:0] m_axi_ruser, - input [8:0] m_axi_buser, - input [2:0] s_axi_aruser, - input [2:0] s_axi_wuser, - output [2:0] s_axi_buser, - output [2:0] s_axi_ruser -); -`IP_MODULE_NAME(efx_axi_interconnect) -#( - .ARB_MODE ("ROUND_ROBIN_1"), - .S_PORTS (1), - .DATA_WIDTH (32), - .ADDR_WIDTH (32), - .M_PORTS (3), - .ID_WIDTH (8), - .USER_WIDTH (3), - .PROTOCOL ("AXI4") -) -u_efx_axi_interconnect -( - .rst_n ( rst_n ), - .clk ( clk ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awlock ( s_axi_awlock ), - .s_axi_awready ( s_axi_awready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arlock ( s_axi_arlock ), - .s_axi_arready ( s_axi_arready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_wlast ( s_axi_wlast ), - .s_axi_wid ( s_axi_wid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_rready ( s_axi_rready ), - .s_axi_bid ( s_axi_bid ), - .s_axi_rid ( s_axi_rid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rlast ( s_axi_rlast ), - .s_axi_wstrb ( s_axi_wstrb ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awready ( m_axi_awready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arready ( m_axi_arready ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_bready ( m_axi_bready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_rready ( m_axi_rready ), - .m_axi_bid ( m_axi_bid ), - .m_axi_rid ( m_axi_rid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wready ( m_axi_wready ), - .s_axi_wready ( s_axi_wready ), - .s_axi_awprot ( s_axi_awprot ), - .s_axi_awcache ( s_axi_awcache ), - .s_axi_awqos ( s_axi_awqos ), - .s_axi_awuser ( s_axi_awuser ), - .s_axi_arqos ( s_axi_arqos ), - .s_axi_arcache ( s_axi_arcache ), - .m_axi_awprot ( m_axi_awprot ), - .s_axi_arid ( s_axi_arid ), - .s_axi_arsize ( s_axi_arsize ), - .s_axi_arlen ( s_axi_arlen ), - .s_axi_arburst ( s_axi_arburst ), - .s_axi_arprot ( s_axi_arprot ), - .s_axi_awid ( s_axi_awid ), - .s_axi_awburst ( s_axi_awburst ), - .s_axi_awlen ( s_axi_awlen ), - .s_axi_awsize ( s_axi_awsize ), - .m_axi_awid ( m_axi_awid ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awqos ( m_axi_awqos ), - .m_axi_awuser ( m_axi_awuser ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arqos ( m_axi_arqos ), - .m_axi_aruser ( m_axi_aruser ), - .m_axi_awregion ( m_axi_awregion ), - .m_axi_arregion ( m_axi_arregion ), - .m_axi_arid ( m_axi_arid ), - .m_axi_wuser ( m_axi_wuser ), - .m_axi_ruser ( m_axi_ruser ), - .m_axi_buser ( m_axi_buser ), - .s_axi_aruser ( s_axi_aruser ), - .s_axi_wuser ( s_axi_wuser ), - .s_axi_buser ( s_axi_buser ), - .s_axi_ruser ( s_axi_ruser ) -); -endmodule - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -k0MNGAL+siJuDYrFA58rRJscMTUE6hiuNEylu7uA+mdVk/vCPJpUprjqZIgJ75i6 -csRX146zVh4AUQABC09rbvto0kqPbqsZwZGmdOm1W8NmGZIXLCsG4MZs984TiToI -QMOSc+XFr9GVx1rFODfIQCsRVOla6WZCpHrBZzFjmFwY4t9fXFQCs5fSkNbGyG6v -8YDvdegFPMYp5Qu9ccfxeosyrpdCBompAmWscbYmzMrmyFiInvb8Y5dyqCuve1NW -jirl6fz1954ypdomnZDn+X9k8zTCJAxovyf9Qxk6Q+/Pf6e6yRqEYBxT7dtZhWRG -tEQdKP3bt5KBf+EuwdVLuQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) -`pragma protect data_block -CosGYIkH0xBRxN95EJWx839RlT4VAi4LCJZ1mt3NitRA5g2pDgJLsvVh2D1y5BVA -pdFnLxJlKeO8VGxcbjdy9+FeBPs3Bo0hcGMo8L+LaJ0bVkv+6b77n30HN7W4KS8h -FD1Ep9sROiwLtXRFHJO89i05/tAaQLM8i1caOwWOyxnOkkN9uNWnXu8Q0YVHwDSo -6edwH6pDm7sUFDB7MkilS2mpOjdUBdlO7TGkRl9TuEENWQoMfIDEVtwj5ArywPyR -ABP441amQzUHEwhfDKcPN2iMoBL+T+S1wuWnJHqvzHEb6nVPARgwM2LxvxR9dJld -dNlxyS3zC6MHchUMEAThn6/mNnJEIrcrJfsvf1vvLfpUlQ5d+C8Gj2KcQl4cX+1i -y70cPd03g1gHtWhRfChJ+8u0hcEyphEmEnx9SLi2I4xYi+fTWMgPPM9PNN1YXNHq -otMqtc2ceQLlyCdlKJplKqKXkqQdhPcZ9wt1WckUoSV+ZeiA4t7bGUWN3kexbKDy -o/js6xWIxX0ryxN/pbXUzhaj+FMP84LHEs7BoUU3zxlGsUspgAysZAO14S2sGjNI -BGpe6bm0ONuesSHUY7+4NUAWlwtPlG6ulaAEIClApiB8gBOvDsTAQbDKVkunI6rz -9cfhmqP/A1djz1i+Lw6iytrG/0VEU8wOePUdJupVohofGQa/4y+YwGciqdf8bscN -y2H+LIZnDVF8FwQqxUMjnTJGvd0s9fHCJfhYvXMWorLOGLe2wW1l63PmZQoaNVXY -K/JSkYpZKe+1jeyKioBw1ecvAOFXmnHjUXoGGiAbTSgVf2c5qN+UOXty8BIpzXsg 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-OAu6M+ioz+nfZk6rwKkJjrU28weaeNKuNtCQOwbaS39NwTHRNDybrXbAXbso3Izx -hHULq89G/WE7fXIJJ0uNZj/cmIVk3lVF6/9zsx2+nHv/XUIhJZx9EG5LfBBVc6qr -CfMjv+9oxgyUl/uPWDBsm26tkTV3DbbHeU//M/nf4KYRWNdwUirBLfeGqxXgdZFH -9mDPUQ4z6WmHHr3T8a0VqhMnAY9JZPZWtcaMhdhuEyEt5JTTJAmmO/m7cGRh+U9j -Oylxf2Mb1LOHffkW1XhJrQ3bDYFPbrrvddxJb7fYr43RlXkG/NtCA0CR7fzBlhtw -oML9Tv6EfavyLW/lnsOYIqZT3EexL37fh5q/U6iFfb2Fi4yP0ihSU9TcISR8bkn0 -`pragma protect end_protected - -//pragma protect end - - -module `IP_MODULE_NAME(efx_axi_interconnect) #( - parameter PROTOCOL = "AXI4", - parameter ARB_MODE = "PRIORITY", - parameter S_PORTS = 1, - parameter M_PORTS = 8, - parameter ID_WIDTH = 8, - parameter DATA_WIDTH = 32, - parameter USER_WIDTH = 3, - parameter ADDR_WIDTH = 32, - parameter M_REGIONS = 1, - parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, - parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, - parameter STRB_WIDTH = DATA_WIDTH/8 -) ( - input wire clk, - input wire rst_n, - input wire [S_PORTS-1:0] s_axi_awvalid, - input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [S_PORTS*3-1:0] s_axi_awprot, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, - input wire [S_PORTS*2-1:0] s_axi_awburst, - input wire [S_PORTS*8-1:0] s_axi_awlen, - input wire [S_PORTS*3-1:0] s_axi_awsize, - input wire [S_PORTS*4-1:0] s_axi_awcache, - input wire [S_PORTS*4-1:0] s_axi_awqos, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, - input wire [S_PORTS*2-1:0] s_axi_awlock, - output reg [S_PORTS-1:0] s_axi_awready, - input wire [S_PORTS-1:0] s_axi_wvalid, - input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, - input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, - input wire [S_PORTS-1:0] s_axi_wlast, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, - output wire [S_PORTS-1:0] s_axi_wready, - input wire [S_PORTS-1:0] s_axi_bready, - output wire [S_PORTS*2-1:0] s_axi_bresp, - output reg [S_PORTS-1:0] s_axi_bvalid, - output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, - output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, - input wire [S_PORTS-1:0] s_axi_arvalid, - input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, - input wire [S_PORTS*3-1:0] s_axi_arprot, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, - input wire [S_PORTS*2-1:0] s_axi_arburst, - input wire [S_PORTS*8-1:0] s_axi_arlen, - input wire [S_PORTS*3-1:0] s_axi_arsize, - input wire [S_PORTS*4-1:0] s_axi_arcache, - input wire [S_PORTS*4-1:0] s_axi_arqos, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, - input wire [S_PORTS*2-1:0] s_axi_arlock, - output reg [S_PORTS-1:0] s_axi_arready, - input wire [S_PORTS-1:0] s_axi_rready, - output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, - output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, - output wire [S_PORTS*2-1:0] s_axi_rresp, - output wire [S_PORTS-1:0] s_axi_rvalid, - output wire [S_PORTS-1:0] s_axi_rlast, - output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, - output reg [M_PORTS-1:0] m_axi_awvalid, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, - output wire [M_PORTS*2-1:0] m_axi_awburst, - output wire [M_PORTS*8-1:0] m_axi_awlen, - output wire [M_PORTS*3-1:0] m_axi_awsize, - output wire [M_PORTS*4-1:0] m_axi_awcache, - output wire [M_PORTS*4-1:0] m_axi_awqos, - output wire [M_PORTS*4-1:0] m_axi_awregion, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, - output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [M_PORTS*3-1:0] m_axi_awprot, - output wire [M_PORTS*2-1:0] m_axi_awlock, - input wire [M_PORTS-1:0] m_axi_awready, - output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, - output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, - output wire [M_PORTS-1:0] m_axi_wvalid, - output wire [M_PORTS-1:0] m_axi_wlast, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, - input wire [M_PORTS-1:0] m_axi_wready, - input wire [M_PORTS*2-1:0] m_axi_bresp, - input wire [M_PORTS-1:0] m_axi_bvalid, - input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, - input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, - output reg [M_PORTS-1:0] m_axi_bready, - output reg [M_PORTS-1:0] m_axi_arvalid, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, - output wire [M_PORTS*2-1:0] m_axi_arburst, - output wire [M_PORTS*8-1:0] m_axi_arlen, - output wire [M_PORTS*3-1:0] m_axi_arsize, - output wire [M_PORTS*4-1:0] m_axi_arcache, - output wire [M_PORTS*4-1:0] m_axi_arqos, - output wire [M_PORTS*4-1:0] m_axi_arregion, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, - output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, - output wire [M_PORTS*3-1:0] m_axi_arprot, - output wire [M_PORTS*2-1:0] m_axi_arlock, - input wire [M_PORTS-1:0] m_axi_arready, - input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, - input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, - input wire [M_PORTS*2-1:0] m_axi_rresp, - input wire [M_PORTS-1:0] m_axi_rvalid, - input wire [M_PORTS-1:0] m_axi_rlast, - input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, - output wire [M_PORTS-1:0] m_axi_rready -); -`include "axi_interconnect.vh" -parameter S_PORTS_WIDTH = clog2(S_PORTS); -parameter M_PORTS_WIDTH = clog2(M_PORTS); -parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); -parameter IDLE = 0, - PORT_GRANT = 1, - ADDR_DECODE = 2, - WR_FORWARD = 3, - WR_RESPONSE = 4, - RD_REQUEST = 5, - RD_RETURN = 6, - DRP_REQUEST = 7, - DRP_WAIT = 8, - END_WAIT = 9; -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -f0DVmU/kdU862C3ryhjQlDsM4c/0bG91GM/Tt0YfOziNIhVBbdZsoYW2RTSSEC81 -yNXUBt7tFmZq4YDopiOye7MWsFmf8WWRQEL3slo6DkYqzPlqCgnjys82AVws5Cco -WGW89TXAcQAYHJy7oG8Ae9oSMdLa3PIQNp7mSA6rz4RhAKHQyvxQU3wr0zXDmYKl -CeyI1ZIu155HAUZL2bXguauGtJWtwaTXIrQO4i5/hXied5l3pm8lCdXsKbM1Enxx -V3E/sk/RBAVETx2fmYxracwCdN363LHRvYHyP4b2qkmUndhj47mK2s4d6wc/G0IJ -HQRhooSUf5bQscVy4yyOxw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 24464 ) -`pragma protect data_block -VTq/qeL5rbYMXcLz0pVnq2QU7OySLW7WR1ySFBochA6uqctGyUZMjS/Pnq7DeDQA -s5ClOKMV4s33FMhzgVOQol94f7qpRytPtHwO4wJfN4F2g5QpANsEk5OSaLDZaL+T -9JNTHQOahODVVMjsEwLu3Hf3nxQqnUpY1Jq2hY3IPT9HQw+jYUbU1mwaaPtk3z/B -wfByi6gTuDXLRhTsDy9zF2v2hyVz2yDuu+x9TSJkxCf5Ivowir1LIvj5/3PTq70h -N6f3RfvSBCkVywuTW3T7/OhSi8wnLfdctcCOumE1svbUYFgxg4J2eKZs7MjC0kx9 -BSZcpQPmbuAEPr0X4s1LPhIA3vVVwZzzfsgimy/Xg5Jay4omrboBZMNf9zoz/upT -CWeKBGZMPg7uyDy+H3GpdRNVVeOleOFSVrU/4KbsSuM7/fgKqbwL1vbL3FoZihPh -ldxqCnYv2m//sJpbeK3FtM5xLVdzq8u7WgS2RNd0wbzqdcIbA5ahg4/wV5r22Zo3 -pDP2uVlZvB4LOCQM7VnNmxqVSUNOdZrdkfxscccugLwsZ/LRvxbuw3GVqzFEQGGl -FBnm83T00BwwWMh3yKaRmz9mYY8xXcUOaZ9cgJpRVvfKPq/yHCtnHgXpEEkbHFoC -p3eSX44fIQ/EIHBkJ6jvFyA61OKdjC0gsAj02XudRxsxq76JhRuRBETksNXiKo1k -txGlub+1WwXw3GYTDyjs23iROrf853eo1PTW2BocqDzdb6AFB8CkhQIM8lKkRJFe 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-mLxzNtdOSZuENCu1k9eImFqEVVl2odtXcLBE6f8fS1rDtjNUupb+m5h+WR63QHid -eDln4z8ShnayiKhW6xp0jj2dUvWnOyhQwZWRP8m/EmfeFO7gYiIw1SxDD/ZqH364 -PzVEZruTbQ4jUKjpfHxf9WBgIVrEYTPTBjPjxaZbhfA= -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -gQ+VauIuH+g40FNOpVzoPSXPaSSXzZWh6rE+e4zt/Higof5lTVqndEO2y+vyS/HT -Uz3/xsHmLa5/hfJOzrQ2WAbWJcFOc0pzmbDqYnUgEw1W4IUS1qcjifpXTLdxvwfy -rSWd00QRecQN7v+pyLFb6xf5TELzzsB2PAr6/xlRVs03sGcC8jpFMP1gppLRrh+C -xnDjMIBVdGmu01tJ1gcEY/913addbws7HLgMcMDLft0U/4zTbjE/rrDoC7+eO+3k -z9ZPUNkRvEPxurfsVZfIuglJuZJSqyaB+Khmc5Q1nMDb9IswcttQUM3RtjEksR13 -Y4OcKLh/ejWsVorB6JLJeA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) -`pragma protect data_block -fo0JdXfIQsWgrENhFGo0RRW9s/IV4eGBK5upzSxFjRkxTj+wCit1QKkd15jJgDu4 -P06Rnw+P2/Cu/tkXRjH7RGfSCa1EZ08cwLiSykEmyb+qQo8wTkOBh8KIag5m0P1t -XTuNeK4lZP50EUwL/4wSSMPuRtdpIAF+0PAXjdoge2gwhduxtVQZpgPO12dwk0Wo -Qyfuxrm/7iyjiETt18QCBk/PXC9JLX6a9hmtr8ujb+7IKQJFj1S7F9WxCZ1yamDs -e1D+l34aYZ5r3sBbAysWrg65oN3fAAd6bhptfeU2+BDBA8oKIcTClBK2f3pBUPul -8YV5xUU0+FGat/Rjkm2ZmKKpm9JD+w7ufesbJ2fqRCCex08yynx+EuV6lNupQQk3 -UbxIK2+04eVmLtY7V87103cxyVnLFXqAQY3XaG0AWBpO2Ew1NwH6CU4yFpyUAC84 -Bjztc1mHKONeueopzONq61tRDqarI0ex6IhDy04D9/zAOhMyBrEHzeR0UozXtK6Y -TB/qqFBgJmagIMQWcL03s2FYWQgGUU3PRQ4JiB57ubJG6H64M9UJUMXI7VXW245F -S0oLuBSWchTwY4/6zvioNieoCZgdkxOTUqHNuV4Zf7Epcgh3IQIZRzjBSpah3skn -kQwLdkHYbh3EzBAN0L4lF8u4LE/8SqwLPpsl91D8Qck2jzgNTYnbsG+t2tsum6n8 -wYvw9H2G6SCXAimDrg2Qy66lpdDA8XQf+1Pu8sYKlEd3GH9lQyGX+l4gx3OLuOtR -fAlYbOhHnFRDXMNE9ZG/I8VKDFToJD1/SjoKUnrz4TdMcQZn3Asrj6LyXsw5CHgd -zhf60BREHK5nXIJRGkqTlV0OyCbaEe0yTgmpWapYbnUcpX4UNu07ijUdSbUBReil -f2PULQwchd1Nh+nj49FyRm0SU4twHeYIMoSC2sMtPiJkuqAZPugzpBpKZUPnKzDd -VmHxPV5Fl4haVbGLfQj4rfl6Mqpqk2DLOiPmwiXnf7CTAjpnwNQ07KsBw6SKxLAe -YS+1RZFe1JQTA73Dv+hAjOEby2uC1tz9V61abAakI4omdhXK1WBGS7AW7VIkOhsa -U2d43C1vqygKdJzTQVB3SVqswMzruIiClRGEypfl8F1L7BIegRA7y6KJYY2lQ69u -7eDX8XmDYmXDiWgXqtWRALbhHrDi8EwOCp5Tts6KK1q+HZNB6UjiGUrGZ2/EhU4H -rNhfbS8YD9wTQtEs/QCi40wIeLIYjIf429BBIRU8k3na6ZwzGLdfxJnqsRLJ6E7X -aCiJk8iag4Wfv0HsAb9J8vDUKzzLHS5OYlHmEss6CTswBAYs7u8/UF9rlfvXy8Mb -z5tfh7xCXqOQpY1gF85w0agvdFKLhhUzfB2Y/XiH+P9zw8608Q4B2irkUuj0fbhU -/VGCOg52ghhNNkaio6JDtzCj/4nMf3QJwdYnJNTiSWLmN/D4rgU8FE7RObm2foEA -5qemSiCt9nYnRGtaRQ0jFh1zieourorN3TI49Lfh/b++M/Hq8OUZh7Uxs5ni4scB -RqEGxATE+29gCCCJ1S3HVi7fcit9xh2mupZnT+m3qHM+Jt01sv59AUJ/UFx/cNYz -qo1oB/NkzOstxVDMlcp8bOO+elF1X4n4wKeC0g/eMM8C+ffQiVT7Rqh2mYLgXQA7 -BhBS+E0RB6UhkxYPnRFEgtk0VLL54VPEVDTINYlLs+L3ZsWwYJs39Gen6vvvepYy -bujDTnnouQqtvD9ok3pkbA== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TpRHXtmr81JyoWaAtQOsoLu44jF5UvFDPdO5/CllOd3kdY7PwU2fkKx7bS6RlGe6 -282Wvc58pPBGh6uImNRfZkaAKTaspN+giuR1GHAo4nfIKi92dgY2DTW5JbEU67ml -1IGNiK4su606fm7n90PZ69MZadoZPNpUxZxzYbSs+I39eZWsgU+rtoUE2d35qjdW -UyorSD+O2F5Wv51CWlcWJyscNK886BFGFi72CtEY8IdYcolZ7hcONOhQT5jbhGWK -UFFTqjnMO6iVrEodujVvUgcUtFQSTl5/oHSkmacP7CSADA82+06uIHf+rByqHGTp -JNgtSAVN844IRP39n4T5EA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) -`pragma protect data_block -dW2N/rFxim9wkWiMqoV2KfFOb7ryaosiEjsKQ5d9XAY99bfh9dHXfxBwbIc/m/4e -C1jjMt+51lGF8ncrYuentPA6MwNEfk27Jwvqv9/Trdq+kOdiWuYmhbZxfJC2L3WJ -BzjhoC/o2ZNSFpgmDKLxln0/pf6iM8sUIldzujq1RDEv/fZvcQ9IXZ0c0cgbXEWf -SfOaD5E2qBGsljqkzqzIKjaiTPnGPsKJ6cZ41jLGbcm+AcbSk6th9Vdeim0hCA9t -HjX+E+Tq77j/ivdd5OuzAehdPAg3IiMJTQxdTNsI3km5GzvomnmxK+pG8L9aCaAh -o+hCsSXZD2QyVCRFZjVT4s0ltvRto5PgSDzzqm1N69eUDE/spFnroMx1TQCLbjBT -zS0w4mCeLkzFlxc0DJduqQlnRMlA8AnBFujD/Q2OAdVMSHQC7YscXbPzF31GPlqx -Eg2t/VyotaMLOGG0wG7ax43UokgdGbSuphzh14sCh3ZSbPueJQLw2MQwK5M2gcvg -/OCrpP6ZQDt10hFz8i/uLrgNIWA93ZzqujdUnYXBBCwUzRJEyHSLnlXX6Ko3rzE5 -ct8FuQPGV8vF+t6COL2nQ0qaq+23R5E5PuFtEMyRrDT+p8iXZasw8RECO0NyVnEE -YuX0T1i6imJS88oOkLq+ywGLgMFC+4O26DIlpPh4+UJ/fnt/pVOADhugk3UeF+QA -ZDR1sgxihCZe9rP7QzVpjm2tDiaPt+fklsKWPprWH2eAiuNaia9mSSHNYGF2x2lD -9h3FKeV/2LSUG5mOvvl3sgKhV2fY0MuldurIH+utuZSPbknY3sebf3BKCntClVOm -6zvNgcnFtvD2+A79A8sltui4gm5GYPS2b0YDfju51vT0iTsCH30p3LWNEG/zEtf2 -48bHsr15Z/CgHdw169NsY8B3V8RHxaJP+T6zbPLBjVmRFbuTftozxf/dv+m7Rgl2 -3kmwmDxauFLyklSGjQ352H678ASYS37eMG1wvn3akQjYEAsrQTdi1sxmk6SACmSb -Ko7v8gOZpn886AO3O4V3iIggxtfGIfRMtOXcoEIX6dRl5GdFkcASHigHwoV56yRO -tlfJEHrrKLKbmqhjLMjDz5jTptQZfwCjZGzki/PYImxPv0ay8+PTa/qXEaJEMsWZ -vWEGZGSO9zphfmPXEJI+qF22X0dYlKGn/U8rzBEsdcxIXyGWQwBJvbo+GhnPURiQ -i1MJHwfOEDztC3XemmsQeaMuSDWZFrnOKXuYkOBj7tD8ir7vJOor8isvwQUz9LGK -g5Vx+0HdaBgE32QEZ/NjYA1V6bM0iUHz9e9qzEVqN/kRww8HFXA6SnpD5lz6hyxy -jFVRtphwYQWmSzwLvFWa2AYQuI4xjU7tJKOCZRqxjD4hiIkjDK6/K/01Gk5QL/3K -12xoSmqSIZRHwxFGBoHiuBmy+wBhSdqqIOdJ/OsoBT+1OwzQ24l0CRjfAk+zBdVi -7A89GoA5JGSeX8OCJopZvuJ/kEWBUL+l+AU3S9Z4l0uVYybFXE7WXuTNCWRjCQFQ -DmofPA/+XPmyr1MT/3DpFQgnMN00C/jJ1eRmmSntrjCcYaPS0vX117igGa1YWfcD -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TBCX5/gAT5S6xdVBuY05hYDsXmHLnm/0Yl4d4ayUlKrDe3IUWB3JcRtZJEwtIwhQ -wqO6qIYs21XvVt74eCxdt1SZXHRXXJiT196fD9q5vFrJxAQqeTDvH51bmshhKW+i -DwXpMTwZlLgBsT2BEP5C0RiiICy9chJTycHB7vHEh6lTXT6S/2H7bweTMlFCh6s6 -n5aHgBbfjk9BYIUSTuEvOxw9Yki0T44zjqGmjZ3qxkhk5Rae8iPLqCnjRTjNfqOE -zQtaoVQW+8NbATVUmZC4WlgxF/J03hq0TLeqLYfcuWR0uH9vLAWsUzHqlGMZvUSV -23zwmB8p0BqUeaj1cllyzw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) -`pragma protect data_block -2OvJlNYOCu/okutbEvWbuQI4X9C4wmVA84hW5XRuqc+R7lDXEYZ89g58fT3Wyd8M -ecpTY/f/5J++NaepFO9rZ71cRzxgXD7ZQypxrBwT8eXz6kwhomKLL8xgQuGMrD2h -002LEC5h770bZFbr2QDl94Kd8oWweGDIcwbbPgGtsgfsrwnZq107rvdgRLsvDJ6H -A9T68XpAsV83OJOA8hk5S1ytXOtMoD1vxUA9NgZ2d9BBiwxnfNC6r2DYa/TpgT+F -8Dlnu2u3Ch2T50E1FvIsU2NsOkKdsN8k6Nmhr7J+mWrK8q1RSElNbQt02yIshAzD -fz1m7maxuzNvKiofs7xTJYH5Zl3jsRgP4i3jUPcFIYQTdju0XGFuzz4tT0y3o98B -wJPQRdZzLdAIRwwOeqCGe94DNj6v4B0lCOW+L2I2xO/Zd85RIWk0KQ11TMBxIioX -lElgvMwoYdOobLmpseg4vchu9jvsSwd1ET14HpSefqoM8cHFSvGA3j0KpwHUHD6N -cAg2z8pkpvWyZBxPOnKrjjHml3gwE3q+X2mtD1ayi41L4xn6E8czI/znMUiRwwcz -u/UG8I65XcONtBswjX1cTAad9X9cP37rq7ly/mnCVaQ1fwdx50rBY6tOiF0jiVR5 -JjSBl4FkBYJu7kHqA7DcluE9ATZ1+D+BIfESxs4o+MIGiPbk2VMeafwTD7GkJFOt -pp85p5WDA/qQLIA+aQsaHfBRLInMjsajsBU1Nnr1Z2FuT4dNgRDU1JiEJoiGBh4S -RZzlhgVKqLQdDiC5KHU60BMuW3u1CxkP6BLofYO1/DTsIOzKRlb9s3+Bx2RBLO+X -LpI1kmPdmyjjLOe9xPxUuWAlk4Ona2bF7SOrCRKslzRwj5WK3kdfynnrqi6fyg/g -6RtRb5T19kv8xkX8Q0Nu2f6aIj9NFg8R8LJhXh6X45cptFvZzqgrDrKouB2qeqzv -r/ARvwCCrLhqU1Rwol3o14E8rmlZcjNTDxMVbtGHIC6f+FQD8Ge6dA7TLtOmbzhg -ADyiBfAGChDV8d6/1Hzt1ZCbp6C5hSA43mtpTQYEjZcGds4olsLWRMFlvn6SaE8U -/yc4f8I5aqNLijlkaO5yVtVndDXvrhyJK63yxQ2hv4wjwsq4K2PDQ4XYvUcmKPD/ -XlPlsS9Ze38WOmF18BNsWhFg/X1ZEsnJQZqQFknQ9z/lHiYTcq+HtWHD6JfZzOaM -E3UA8T88Db5hkBxdi+VdfTfF/tcJB9TVv94cA8SuyNnP6Q6AMPtj4AcaMmUbLwpN -6fOz+eRjs375gUjeGtSoPhbJZ6VvJjLK6xs1mDGS9ROACnxpeDCou3/Z35w98hvB -+vycfefBU/3Oz/FibzGZfGGRZxR88DoezSovO8xS1UTztbTV/E3Hf50BgcR927BL -NJGAapWYDd8JtV0BHG5wpaes7/XmU1ypZarztFE+5fUtgzp4AKZ9d8fLPqu7uHyy -VFSlknUG3lKAvV+aTv5kwTm6T24a0lpxxYWzaadSBxuqeJtU7FNijzCia9l+KD/j -MuWIX01bTZapbrnUlFm4fAAgbW5f3nA4jSdhRz4mKzYdZ4aMWDM8hBS+zHKdAxt+ -r3IOTmKOM53qQd6/AzPhoA0A+KC7CNCPEgYxWjHD9LvdybgmZ3XenDSbtLwQbD6Q -UwWAn1xKUS+VTfDL9VkVXP1CneqLQxZtc1Sc/vBPwSJ6+7jAYG5QfCsFKpYk6KVg -WWBjX/iaBk51jQZ/ISopM3fO5XEr5/3lYtazRsrg0f+S3e4Zzo8nxEOq9P5xVhSQ -O7JVUzPKxB+mq8b8+Trp0jpdlwATuoCmknWv7M7xGQxIxgYlBegfgpZNrb4ocJt1 -C2A5oMK874OASkTuFy/CZtTCSKDyyC2WSUJy/ybgFlZWnTyWBNaSIgYpaI2Gq/5N -W2sAGdn2IzwgLXJcE2TeXPkUP8I6D0EvyGS8UJ8WVt4jXlr/F3VEInfxr2Y6siXk -AHHFHgrTgDIGLtO8E808PqkxvLBmGkuPh75G6ryBOPonCZ0aT1e/GX3dbFPpEaEW -llXDZSgbk2fjRwniN+3OtnrHeVbQUlTC3iaVcpJd1hL8XMqXbPIDInH7Hno0Rp0/ -Voc9LaQvrTj/kEwf26rJMPkHP3A/gue3fawMlgP2mdiTeVrBYqtURRsKaMlxgKT3 -3O7Gyd/yxwB05GETZ6zA/3Z0q4ztIi5TZ5m+C2wW+NIXwkcYJdqHOodrO1fkRlTs -npvFlNq1Br3v3gImbnvFaouFkT+542lb5sOY50i4uwrifKPntqOl0n9+dE1pyipU -QURHoCbkL2QR65H1hYcDoLRvhJAfS/oEFf4DSf8HgiZITq5pSvnYcJn76jC0mNiX -9LRJqxBuOkHcdFIbmkvDuwIN0asrQmGQCAsYOOxVA6EpX0XWcJ8dVmRyWbGVZXNq -45wAMvGDj0F6Jm7b2sQ3quJFDXDWvD7hPWp8nLqRDN+P/s9tHqK5LMXPHFdcqMn4 -hKSmCVgEtnsVfWUGyjVJ0Yvh+jxdg3vECIO38UuFBuTGroD0egvsyd7iuwT3aOmn -5YaYW0vHuHERbtLy6AkO1sVVmg18jSH32tE036uQS+LCrj+G0cg6Mf5sU2CHJZA0 -9Jse9KsUSQdI7bnqvPdYIQ== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -eiP/26NloMbfJbEe1aU/cN+AkTVidxKZaNv824TVZXkpjf5L1zEVLf4buBzXwSr1 -MiO1FaB1qgL+ZgKHLwNzc4IiIP0d7qYOaGR46jDr8/k9N2BVxXC3V0wJJ6yhDom9 -O7B9d2Lcm+b0UifdEaFcX3luTwZzXAQW83Bggnm4eVP275Vqog3REHo5wgsstEU3 -AG6o+oVDnNjZTPDPyJ4uHq9bjFFyvY3ga+lOo2iVymecnhCiRtjy3AFtvWBJW0ek -uhj8QvNYf04TXkRXdhdRfq/HDLr3M6Qa7/Xn6vGE+drFyRTL1nmH9wkjBBbD3swn -58tiwvvx3ajgMOCJeXfrXQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) -`pragma protect data_block -z83CFN/6+XAqqlsaR10y0/0TRdqihm7Mln1SErDagYzHq/tf3472iVn71ufDnRwX -XjpfuAMiYkGYL+YySToA+S247ZqaWHze8oceixrYgRvhox5tY82fxq9Fl8kghDLv -SjC2MS3eD6cYQeQLFqzD1Mn0WKOQZFVCku3VAWFB2lduR5mhayfY/Fa3R/W72ABn -Z0d6Zn4ZBsgSyb/M70GpfeksPL4x3rnLEOyMOaWSU6+bpfwlHv6gwzh9HPzLZxVy -08g2U6/uxm0PBfE3o/LncY5k29GaWHkcOHv6VhXh/m8K01MJZqFeBphDIArYoxxq -PWDxAO8AUxxtI14Tgpa2V285dFMvK+4KnQioTwi0kMw0x+o+AprykzkXPkE/VVzK -KXd3WO23uskN1uRWHMVa+YBeVjuyFSDLn3GxfHH9tkFDow1kssYW0TqHWs0aqHah -qnNS7hoeJjqPZiowmyQrmDxNCJSTzH8quhzu6sXOHqjuy3hV/M2EY8gngXNAKKsb -WbOvs5QeFheEcLGYrod/Zfv9aZk0e3y0m11vKOyZVQVGFJQzc1uQ0fLjWrpSt7yG -qya4/JgJ8aoha2vBdN7gKSQ0jQBRSMhhOkv1iunq1iT+1ZETzOdrs32w7jLu65tq -rkZk2Z9PlyyFm4XlIu3ljYIH3Z1F+BdPGXiUKHiLhEHanApDED/zljh7BDGApCKl -t1zRJJjZMckJfWQclrLgdXSejbEhZFqHfgYNQe4ywo4o/SbWaqGvPgahhDBBVxZV -rvCFFNip8ka1YAIM4x0DqYw1pSFzn0sUmEm44Jl+Eo4D5chLPEJnYyAjsKm0nIFa -We3J6DKurh1q/PmPYqN51Vno2A5tlFLR8v6SH4m4qu3V3skZsRF0vR6BGx84VdVj -bN8BlLOwDEGmTO8UZpg5knVPN5bAfvf/kXvbSbr8KPR5NBZRqz3SXFeMxZYBPfbj -GI8S5ZZZeq5AvybyDwwt8BHWypNkKlsr+UxyAt+phMEA8F/U9gAt5r50llYjO4qu -5tLeotWmT7oFHBktGytHHC+gKwtWEMsJLm7+744JbDfnMvdHRr+AQgpYts9jdNY6 -guxuay2WoNBpjmE51Kq8M1xXeO6beJN3h1JAlESUfz7eFKkE8Vkr5Jg6ccn0KUsS -ZZmNyAaAta//k2mRELcX5bJmUCCHy7lAgQBjtv7XZBfyULC/eXy3RUO/ar8/VQKj -wwOLkv6PJN1DfDlpZ+oswIslScrN1ijU4t2buGKO8zI+cQCpYuC9FBN8V8chHOZw -//0ODvW7AEl6D/OUt8ZC6gUirNCSFRQjXz5x+MOrJPH54wUb0gmtQRPSsbnbcm8g -r+J90t6Fz+FSggPmyNbgv8Z+eWprb5Z3QuqJaQlTYxXGJYLXXwcTjZP3Sf58Vd4Q -9PV9zVG1BxTwV5hFTLJrTkIFGs6wyF+96e+3TnhJKuzZ4Qgf0XJPp9crAdiNtxfx -`pragma protect end_protected - -//pragma protect end - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh deleted file mode 100644 index 26709b4..0000000 --- a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh +++ /dev/null @@ -1,53 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -localparam ARB_MODE = "ROUND_ROBIN_1"; -localparam S_PORTS = 1; -localparam DATA_WIDTH = 32; -localparam ADDR_WIDTH = 32; -localparam M_PORTS = 3; -localparam ID_WIDTH = 8; -localparam USER_WIDTH = 3; -localparam PROTOCOL = "AXI4"; diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v deleted file mode 100644 index 00aa64f..0000000 --- a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v +++ /dev/null @@ -1,137 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -gAXIS_1to3_switch u_gAXIS_1to3_switch -( - .rst_n ( rst_n ), - .clk ( clk ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awlock ( s_axi_awlock ), - .s_axi_awready ( s_axi_awready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arlock ( s_axi_arlock ), - .s_axi_arready ( s_axi_arready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_wlast ( s_axi_wlast ), - .s_axi_wid ( s_axi_wid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_rready ( s_axi_rready ), - .s_axi_bid ( s_axi_bid ), - .s_axi_rid ( s_axi_rid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rlast ( s_axi_rlast ), - .s_axi_wstrb ( s_axi_wstrb ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awready ( m_axi_awready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arready ( m_axi_arready ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_bready ( m_axi_bready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_rready ( m_axi_rready ), - .m_axi_bid ( m_axi_bid ), - .m_axi_rid ( m_axi_rid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wready ( m_axi_wready ), - .s_axi_wready ( s_axi_wready ), - .s_axi_awprot ( s_axi_awprot ), - .s_axi_awcache ( s_axi_awcache ), - .s_axi_awqos ( s_axi_awqos ), - .s_axi_awuser ( s_axi_awuser ), - .s_axi_arqos ( s_axi_arqos ), - .s_axi_arcache ( s_axi_arcache ), - .m_axi_awprot ( m_axi_awprot ), - .s_axi_arid ( s_axi_arid ), - .s_axi_arsize ( s_axi_arsize ), - .s_axi_arlen ( s_axi_arlen ), - .s_axi_arburst ( s_axi_arburst ), - .s_axi_arprot ( s_axi_arprot ), - .s_axi_awid ( s_axi_awid ), - .s_axi_awburst ( s_axi_awburst ), - .s_axi_awlen ( s_axi_awlen ), - .s_axi_awsize ( s_axi_awsize ), - .m_axi_awid ( m_axi_awid ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awqos ( m_axi_awqos ), - .m_axi_awuser ( m_axi_awuser ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arqos ( m_axi_arqos ), - .m_axi_aruser ( m_axi_aruser ), - .m_axi_awregion ( m_axi_awregion ), - .m_axi_arregion ( m_axi_arregion ), - .m_axi_arid ( m_axi_arid ), - .m_axi_wuser ( m_axi_wuser ), - .m_axi_ruser ( m_axi_ruser ), - .m_axi_buser ( m_axi_buser ), - .s_axi_aruser ( s_axi_aruser ), - .s_axi_wuser ( s_axi_wuser ), - .s_axi_buser ( s_axi_buser ), - .s_axi_ruser ( s_axi_ruser ) -); diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd deleted file mode 100644 index 9f59356..0000000 --- a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd +++ /dev/null @@ -1,229 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component gAXIS_1to3_switch is -port ( - rst_n : in std_logic; - clk : in std_logic; - s_axi_awvalid : in std_logic_vector(0 to 0); - s_axi_awaddr : in std_logic_vector(31 downto 0); - s_axi_awlock : in std_logic_vector(1 downto 0); - s_axi_awready : out std_logic_vector(0 to 0); - s_axi_arvalid : in std_logic_vector(0 to 0); - s_axi_araddr : in std_logic_vector(31 downto 0); - s_axi_arlock : in std_logic_vector(1 downto 0); - s_axi_arready : out std_logic_vector(0 to 0); - s_axi_wvalid : in std_logic_vector(0 to 0); - s_axi_wlast : in std_logic_vector(0 to 0); - s_axi_wid : in std_logic_vector(7 downto 0); - s_axi_bready : in std_logic_vector(0 to 0); - s_axi_bresp : out std_logic_vector(1 downto 0); - s_axi_rready : in std_logic_vector(0 to 0); - s_axi_bid : out std_logic_vector(7 downto 0); - s_axi_rid : out std_logic_vector(7 downto 0); - s_axi_wdata : in std_logic_vector(31 downto 0); - s_axi_rdata : out std_logic_vector(31 downto 0); - s_axi_rresp : out std_logic_vector(1 downto 0); - s_axi_bvalid : out std_logic_vector(0 to 0); - s_axi_rvalid : out std_logic_vector(0 to 0); - s_axi_rlast : out std_logic_vector(0 to 0); - s_axi_wstrb : in std_logic_vector(3 downto 0); - m_axi_awvalid : out std_logic_vector(2 downto 0); - m_axi_awaddr : out std_logic_vector(95 downto 0); - m_axi_awlock : out std_logic_vector(5 downto 0); - m_axi_awready : in std_logic_vector(2 downto 0); - m_axi_arvalid : out std_logic_vector(2 downto 0); - m_axi_araddr : out std_logic_vector(95 downto 0); - m_axi_arlock : out std_logic_vector(5 downto 0); - m_axi_arready : in std_logic_vector(2 downto 0); - m_axi_wvalid : out std_logic_vector(2 downto 0); - m_axi_wlast : out std_logic_vector(2 downto 0); - m_axi_bready : out std_logic_vector(2 downto 0); - m_axi_bresp : in std_logic_vector(5 downto 0); - m_axi_rready : out std_logic_vector(2 downto 0); - m_axi_bid : in std_logic_vector(23 downto 0); - m_axi_rid : in std_logic_vector(23 downto 0); - m_axi_wdata : out std_logic_vector(95 downto 0); - m_axi_rdata : in std_logic_vector(95 downto 0); - m_axi_rresp : in std_logic_vector(5 downto 0); - m_axi_bvalid : in std_logic_vector(2 downto 0); - m_axi_rvalid : in std_logic_vector(2 downto 0); - m_axi_rlast : in std_logic_vector(2 downto 0); - m_axi_wstrb : out std_logic_vector(11 downto 0); - m_axi_wready : in std_logic_vector(2 downto 0); - s_axi_wready : out std_logic_vector(0 to 0); - s_axi_awprot : in std_logic_vector(3 downto 0); - s_axi_awcache : in std_logic_vector(3 downto 0); - s_axi_awqos : in std_logic_vector(3 downto 0); - s_axi_awuser : in std_logic_vector(2 downto 0); - s_axi_arqos : in std_logic_vector(3 downto 0); - s_axi_arcache : in std_logic_vector(3 downto 0); - m_axi_awprot : out std_logic_vector(11 downto 0); - s_axi_arid : in std_logic_vector(7 downto 0); - s_axi_arsize : in std_logic_vector(2 downto 0); - s_axi_arlen : in std_logic_vector(7 downto 0); - s_axi_arburst : in std_logic_vector(1 downto 0); - s_axi_arprot : in std_logic_vector(3 downto 0); - s_axi_awid : in std_logic_vector(7 downto 0); - s_axi_awburst : in std_logic_vector(1 downto 0); - s_axi_awlen : in std_logic_vector(7 downto 0); - s_axi_awsize : in std_logic_vector(2 downto 0); - m_axi_awid : out std_logic_vector(23 downto 0); - m_axi_awburst : out std_logic_vector(5 downto 0); - m_axi_awlen : out std_logic_vector(23 downto 0); - m_axi_awsize : out std_logic_vector(8 downto 0); - m_axi_awcache : out std_logic_vector(11 downto 0); - m_axi_awqos : out std_logic_vector(11 downto 0); - m_axi_awuser : out std_logic_vector(8 downto 0); - m_axi_arprot : out std_logic_vector(11 downto 0); - m_axi_arburst : out std_logic_vector(5 downto 0); - m_axi_arlen : out std_logic_vector(23 downto 0); - m_axi_arsize : out std_logic_vector(8 downto 0); - m_axi_arcache : out std_logic_vector(11 downto 0); - m_axi_arqos : out std_logic_vector(11 downto 0); - m_axi_aruser : out std_logic_vector(8 downto 0); - m_axi_awregion : out std_logic_vector(11 downto 0); - m_axi_arregion : out std_logic_vector(11 downto 0); - m_axi_arid : out std_logic_vector(23 downto 0); - m_axi_wuser : out std_logic_vector(8 downto 0); - m_axi_ruser : in std_logic_vector(8 downto 0); - m_axi_buser : in std_logic_vector(8 downto 0); - s_axi_aruser : in std_logic_vector(2 downto 0); - s_axi_wuser : in std_logic_vector(2 downto 0); - s_axi_buser : out std_logic_vector(2 downto 0); - s_axi_ruser : out std_logic_vector(2 downto 0) -); -end component gAXIS_1to3_switch; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_gAXIS_1to3_switch : gAXIS_1to3_switch -port map ( - rst_n => rst_n, - clk => clk, - s_axi_awvalid => s_axi_awvalid, - s_axi_awaddr => s_axi_awaddr, - s_axi_awlock => s_axi_awlock, - s_axi_awready => s_axi_awready, - s_axi_arvalid => s_axi_arvalid, - s_axi_araddr => s_axi_araddr, - s_axi_arlock => s_axi_arlock, - s_axi_arready => s_axi_arready, - s_axi_wvalid => s_axi_wvalid, - s_axi_wlast => s_axi_wlast, - s_axi_wid => s_axi_wid, - s_axi_bready => s_axi_bready, - s_axi_bresp => s_axi_bresp, - s_axi_rready => s_axi_rready, - s_axi_bid => s_axi_bid, - s_axi_rid => s_axi_rid, - s_axi_wdata => s_axi_wdata, - s_axi_rdata => s_axi_rdata, - s_axi_rresp => s_axi_rresp, - s_axi_bvalid => s_axi_bvalid, - s_axi_rvalid => s_axi_rvalid, - s_axi_rlast => s_axi_rlast, - s_axi_wstrb => s_axi_wstrb, - m_axi_awvalid => m_axi_awvalid, - m_axi_awaddr => m_axi_awaddr, - m_axi_awlock => m_axi_awlock, - m_axi_awready => m_axi_awready, - m_axi_arvalid => m_axi_arvalid, - m_axi_araddr => m_axi_araddr, - m_axi_arlock => m_axi_arlock, - m_axi_arready => m_axi_arready, - m_axi_wvalid => m_axi_wvalid, - m_axi_wlast => m_axi_wlast, - m_axi_bready => m_axi_bready, - m_axi_bresp => m_axi_bresp, - m_axi_rready => m_axi_rready, - m_axi_bid => m_axi_bid, - m_axi_rid => m_axi_rid, - m_axi_wdata => m_axi_wdata, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_rvalid => m_axi_rvalid, - m_axi_rlast => m_axi_rlast, - m_axi_wstrb => m_axi_wstrb, - m_axi_wready => m_axi_wready, - s_axi_wready => s_axi_wready, - s_axi_awprot => s_axi_awprot, - s_axi_awcache => s_axi_awcache, - s_axi_awqos => s_axi_awqos, - s_axi_awuser => s_axi_awuser, - s_axi_arqos => s_axi_arqos, - s_axi_arcache => s_axi_arcache, - m_axi_awprot => m_axi_awprot, - s_axi_arid => s_axi_arid, - s_axi_arsize => s_axi_arsize, - s_axi_arlen => s_axi_arlen, - s_axi_arburst => s_axi_arburst, - s_axi_arprot => s_axi_arprot, - s_axi_awid => s_axi_awid, - s_axi_awburst => s_axi_awburst, - s_axi_awlen => s_axi_awlen, - s_axi_awsize => s_axi_awsize, - m_axi_awid => m_axi_awid, - m_axi_awburst => m_axi_awburst, - m_axi_awlen => m_axi_awlen, - m_axi_awsize => m_axi_awsize, - m_axi_awcache => m_axi_awcache, - m_axi_awqos => m_axi_awqos, - m_axi_awuser => m_axi_awuser, - m_axi_arprot => m_axi_arprot, - m_axi_arburst => m_axi_arburst, - m_axi_arlen => m_axi_arlen, - m_axi_arsize => m_axi_arsize, - m_axi_arcache => m_axi_arcache, - m_axi_arqos => m_axi_arqos, - m_axi_aruser => m_axi_aruser, - m_axi_awregion => m_axi_awregion, - m_axi_arregion => m_axi_arregion, - m_axi_arid => m_axi_arid, - m_axi_wuser => m_axi_wuser, - m_axi_ruser => m_axi_ruser, - m_axi_buser => m_axi_buser, - s_axi_aruser => s_axi_aruser, - s_axi_wuser => s_axi_wuser, - s_axi_buser => s_axi_buser, - s_axi_ruser => s_axi_ruser -); - ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/gAXIS_1to3_switch/ipm/component.pickle b/fpga/ip/gAXIS_1to3_switch/ipm/component.pickle deleted file mode 100644 index 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z9I6wY84q_#5JQSPl~EZUd;P4Q%zYR^~cET!w#=;WAJ)FdJR>_4zK@HdYw>_96+^kV5=mydacWqk=GLruW@7W z`lqGWP^9ee`bX01gaYOOijxCd;jz_gUEPel&N{rtjlt^|Nw1-%+2Qq%rPm4d&H>ai z2evw8tJk_18hJhA@ESJ;ukVvyLkYCQ>z_!k6Uw6lD18oWWzANvb?r3r`n=2Kdb#vEp;kM9I_$t!V{P?X7jh%7A9r|-8-v%6 zNw1-N+u`*}>2*SBcK~JEfvqIl>b0)>Mqa1$%XF?1BUN7Gza`b3w>QHG2o1(=a$inH52Qd zc&d3Y^n%n_ICCqxv6zJClN*bA5Y7Ubdi&M=}(YPA?Pk3M< zNPifiqjqh)B6N9^{Dv2EO%}uPr#2KT;XYDBu?kL0k!(*w=o>lF^YW_l=qsW}IT#e> zRN_gBW*?K-l*!EGEAz9Z`_5+M>#Q=F@I6<{XJ&Kx@LSbobRrnnSx#Cm>`d24w ztBW(@TS!io@_A)r-O$W{{2dtyeqPuwEDaXzTC_+$Iua}n|FtCi-;2dZ@HolJ%zVCh zs!&-NsZLfWckkcVoA27Ux3e#|_dst?Pqw$Ov$Hq9zc)M8o88wZKHaysck1N6ece+h zC#Ukgx!$f^Z_niZY*#+Jue&#Ya&O<>$*!KRzMj7PWVWy8fau@dm(O>dJkZy@f3h!| k>(1x>> 1'b1); - assign _zz_ram_port = pushCC_pushPtr[3:0]; - assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); - assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; - always @(posedge clk) begin - if(_zz_1) begin - ram[_zz_ram_port] <= _zz_ram_port_1; - end - end - - always @(posedge dat1_o_clk) begin - if(popCC_readPort_cmd_valid) begin - ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; - end - end - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef popToPushGray_buffercc ( - .io_dataIn (popToPushGray[4:0] ), //i - .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_5_a048ca8f51874147a1cd65d43e6523ef pushToPopGray_buffercc ( - .io_dataIn (pushToPopGray[4:0] ), //i - .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o - .dat1_o_clk (dat1_o_clk ), //i - .dat1_o_reset (dat1_o_reset ) //i - ); - always @(*) begin - _zz_1 = 1'b0; - if(io_push_fire) begin - _zz_1 = 1'b1; - end - end - - assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); - assign io_push_fire = (io_push_valid && io_push_ready); - assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; - assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); - assign io_push_ready = (! pushCC_full); - assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); - assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); - assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); - assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; - assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); - assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); - assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); - assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; - assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); - assign popCC_addressGen_valid = (! popCC_empty); - assign popCC_addressGen_payload = popCC_popPtr[3:0]; - assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); - always @(*) begin - popCC_addressGen_ready = popCC_readArbitation_ready; - if(when_Stream_l375) begin - popCC_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCC_readArbitation_valid); - assign popCC_readArbitation_valid = popCC_addressGen_rValid; - assign popCC_readArbitation_payload = popCC_addressGen_rData; - assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; - assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; - assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; - assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; - assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; - assign popCC_readPort_cmd_valid = popCC_addressGen_fire; - assign popCC_readPort_cmd_payload = popCC_addressGen_payload; - assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; - assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; - assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; - assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; - assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; - assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; - assign io_pop_valid = popCC_readArbitation_translated_valid; - assign popCC_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; - assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; - assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; - assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; - assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); - assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); - assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); - assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); - assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; - assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); - assign pushToPopGray = pushCC_pushPtrGray; - assign popToPushGray = popCC_ptrToPush; - always @(posedge clk) begin - if(reset) begin - pushCC_pushPtr <= 5'h0; - pushCC_pushPtrGray <= 5'h0; - end else begin - if(io_push_fire) begin - pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); - end - if(io_push_fire) begin - pushCC_pushPtr <= pushCC_pushPtrPlus; - end - end - end - - always @(posedge dat1_o_clk) begin - if(dat1_o_reset) begin - popCC_popPtr <= 5'h0; - popCC_addressGen_rValid <= 1'b0; - popCC_ptrToPush <= 5'h0; - popCC_ptrToOccupancy <= 5'h0; - end else begin - if(popCC_addressGen_fire) begin - popCC_popPtr <= popCC_popPtrPlus; - end - if(popCC_addressGen_ready) begin - popCC_addressGen_rValid <= popCC_addressGen_valid; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToPush <= popCC_popPtrGray; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToOccupancy <= popCC_popPtr; - end - end - end - - always @(posedge dat1_o_clk) begin - if(popCC_addressGen_ready) begin - popCC_addressGen_rData <= popCC_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_StreamFifoCC_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_push_valid, - output wire io_push_ready, - input wire [63:0] io_push_payload_data, - input wire [7:0] io_push_payload_mask, - input wire [3:0] io_push_payload_sink, - input wire io_push_payload_last, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [63:0] io_pop_payload_data, - output wire [7:0] io_pop_payload_mask, - output wire [3:0] io_pop_payload_sink, - output wire io_pop_payload_last, - output wire [4:0] io_pushOccupancy, - output wire [4:0] io_popOccupancy, - input wire dat0_i_clk, - input wire dat0_i_reset, - input wire clk, - input wire reset -); - - reg [76:0] ram_spinal_port1; - wire [4:0] popToPushGray_buffercc_io_dataOut; - wire [4:0] pushToPopGray_buffercc_io_dataOut; - wire [4:0] _zz_pushCC_pushPtrGray; - wire [3:0] _zz_ram_port; - wire [76:0] _zz_ram_port_1; - wire [4:0] _zz_popCC_popPtrGray; - reg _zz_1; - wire [4:0] popToPushGray; - wire [4:0] pushToPopGray; - reg [4:0] pushCC_pushPtr; - wire [4:0] pushCC_pushPtrPlus; - wire io_push_fire; - reg [4:0] pushCC_pushPtrGray; - wire [4:0] pushCC_popPtrGray; - wire pushCC_full; - wire _zz_io_pushOccupancy; - wire _zz_io_pushOccupancy_1; - wire _zz_io_pushOccupancy_2; - wire _zz_io_pushOccupancy_3; - reg [4:0] popCC_popPtr; - (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; - wire [4:0] popCC_popPtrGray; - wire [4:0] popCC_pushPtrGray; - wire popCC_addressGen_valid; - reg popCC_addressGen_ready; - wire [3:0] popCC_addressGen_payload; - wire popCC_empty; - wire popCC_addressGen_fire; - wire popCC_readArbitation_valid; - wire popCC_readArbitation_ready; - wire [3:0] popCC_readArbitation_payload; - reg popCC_addressGen_rValid; - reg [3:0] popCC_addressGen_rData; - wire when_Stream_l375; - wire popCC_readPort_cmd_valid; - wire [3:0] popCC_readPort_cmd_payload; - wire [63:0] popCC_readPort_rsp_data; - wire [7:0] popCC_readPort_rsp_mask; - wire [3:0] popCC_readPort_rsp_sink; - wire popCC_readPort_rsp_last; - wire [76:0] _zz_popCC_readPort_rsp_data; - wire popCC_readArbitation_translated_valid; - wire popCC_readArbitation_translated_ready; - wire [63:0] popCC_readArbitation_translated_payload_data; - wire [7:0] popCC_readArbitation_translated_payload_mask; - wire [3:0] popCC_readArbitation_translated_payload_sink; - wire popCC_readArbitation_translated_payload_last; - wire popCC_readArbitation_fire; - reg [4:0] popCC_ptrToPush; - reg [4:0] popCC_ptrToOccupancy; - wire _zz_io_popOccupancy; - wire _zz_io_popOccupancy_1; - wire _zz_io_popOccupancy_2; - wire _zz_io_popOccupancy_3; - reg [76:0] ram [0:15]; - - assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); - assign _zz_ram_port = pushCC_pushPtr[3:0]; - assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); - assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; - always @(posedge dat0_i_clk) begin - if(_zz_1) begin - ram[_zz_ram_port] <= _zz_ram_port_1; - end - end - - always @(posedge clk) begin - if(popCC_readPort_cmd_valid) begin - ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; - end - end - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_2_a048ca8f51874147a1cd65d43e6523ef popToPushGray_buffercc ( - .io_dataIn (popToPushGray[4:0] ), //i - .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o - .dat0_i_clk (dat0_i_clk ), //i - .dat0_i_reset (dat0_i_reset ) //i - ); - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef pushToPopGray_buffercc ( - .io_dataIn (pushToPopGray[4:0] ), //i - .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - _zz_1 = 1'b0; - if(io_push_fire) begin - _zz_1 = 1'b1; - end - end - - assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); - assign io_push_fire = (io_push_valid && io_push_ready); - assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; - assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); - assign io_push_ready = (! pushCC_full); - assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); - assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); - assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); - assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; - assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); - assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); - assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); - assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; - assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); - assign popCC_addressGen_valid = (! popCC_empty); - assign popCC_addressGen_payload = popCC_popPtr[3:0]; - assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); - always @(*) begin - popCC_addressGen_ready = popCC_readArbitation_ready; - if(when_Stream_l375) begin - popCC_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCC_readArbitation_valid); - assign popCC_readArbitation_valid = popCC_addressGen_rValid; - assign popCC_readArbitation_payload = popCC_addressGen_rData; - assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; - assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; - assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; - assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; - assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; - assign popCC_readPort_cmd_valid = popCC_addressGen_fire; - assign popCC_readPort_cmd_payload = popCC_addressGen_payload; - assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; - assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; - assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; - assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; - assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; - assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; - assign io_pop_valid = popCC_readArbitation_translated_valid; - assign popCC_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; - assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; - assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; - assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; - assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); - assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); - assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); - assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); - assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; - assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); - assign pushToPopGray = pushCC_pushPtrGray; - assign popToPushGray = popCC_ptrToPush; - always @(posedge dat0_i_clk) begin - if(dat0_i_reset) begin - pushCC_pushPtr <= 5'h0; - pushCC_pushPtrGray <= 5'h0; - end else begin - if(io_push_fire) begin - pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); - end - if(io_push_fire) begin - pushCC_pushPtr <= pushCC_pushPtrPlus; - end - end - end - - always @(posedge clk) begin - if(reset) begin - popCC_popPtr <= 5'h0; - popCC_addressGen_rValid <= 1'b0; - popCC_ptrToPush <= 5'h0; - popCC_ptrToOccupancy <= 5'h0; - end else begin - if(popCC_addressGen_fire) begin - popCC_popPtr <= popCC_popPtrPlus; - end - if(popCC_addressGen_ready) begin - popCC_addressGen_rValid <= popCC_addressGen_valid; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToPush <= popCC_popPtrGray; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToOccupancy <= popCC_popPtr; - end - end - end - - always @(posedge clk) begin - if(popCC_addressGen_ready) begin - popCC_addressGen_rData <= popCC_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_BsbUpSizerDense_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_valid, - output wire io_input_ready, - input wire [7:0] io_input_payload_data, - input wire [0:0] io_input_payload_mask, - input wire [3:0] io_input_payload_sink, - input wire io_input_payload_last, - output wire io_output_valid, - input wire io_output_ready, - output wire [63:0] io_output_payload_data, - output wire [7:0] io_output_payload_mask, - output wire [3:0] io_output_payload_sink, - output wire io_output_payload_last, - input wire dat0_i_clk, - input wire dat0_i_reset -); - - reg valid; - reg [2:0] counter; - reg [63:0] buffer_data; - reg [7:0] buffer_mask; - reg [3:0] buffer_sink; - reg buffer_last; - wire full; - wire canAggregate; - wire onOutput; - wire [2:0] counterSample; - wire io_output_fire; - wire io_input_fire; - wire [7:0] _zz_1; - wire [7:0] _zz_2; - - assign full = ((counter == 3'b000) || buffer_last); - assign canAggregate = ((((valid && (! buffer_last)) && (! full)) && 1'b1) && (buffer_sink == io_input_payload_sink)); - assign counterSample = (canAggregate ? counter : 3'b000); - assign io_output_fire = (io_output_valid && io_output_ready); - assign io_input_fire = (io_input_valid && io_input_ready); - assign _zz_1 = ({7'd0,1'b1} <<< counterSample); - assign _zz_2 = ({7'd0,1'b1} <<< counterSample); - assign io_output_valid = (valid && ((valid && full) || (io_input_valid && (! canAggregate)))); - assign io_output_payload_data = buffer_data; - assign io_output_payload_mask = buffer_mask; - assign io_output_payload_sink = buffer_sink; - assign io_output_payload_last = buffer_last; - assign io_input_ready = (((! valid) || canAggregate) || io_output_ready); - always @(posedge dat0_i_clk) begin - if(dat0_i_reset) begin - valid <= 1'b0; - counter <= 3'b000; - buffer_last <= 1'b0; - buffer_mask <= 8'h0; - end else begin - if(io_output_fire) begin - valid <= 1'b0; - buffer_mask <= 8'h0; - end - if(io_input_fire) begin - valid <= 1'b1; - if(_zz_2[0]) begin - buffer_mask[0 : 0] <= io_input_payload_mask; - end - if(_zz_2[1]) begin - buffer_mask[1 : 1] <= io_input_payload_mask; - end - if(_zz_2[2]) begin - buffer_mask[2 : 2] <= io_input_payload_mask; - end - if(_zz_2[3]) begin - buffer_mask[3 : 3] <= io_input_payload_mask; - end - if(_zz_2[4]) begin - buffer_mask[4 : 4] <= io_input_payload_mask; - end - if(_zz_2[5]) begin - buffer_mask[5 : 5] <= io_input_payload_mask; - end - if(_zz_2[6]) begin - buffer_mask[6 : 6] <= io_input_payload_mask; - end - if(_zz_2[7]) begin - buffer_mask[7 : 7] <= io_input_payload_mask; - end - buffer_last <= io_input_payload_last; - counter <= (counterSample + 3'b001); - end - end - end - - always @(posedge dat0_i_clk) begin - if(io_input_fire) begin - buffer_sink <= io_input_payload_sink; - if(_zz_1[0]) begin - buffer_data[7 : 0] <= io_input_payload_data; - end - if(_zz_1[1]) begin - buffer_data[15 : 8] <= io_input_payload_data; - end - if(_zz_1[2]) begin - buffer_data[23 : 16] <= io_input_payload_data; - end - if(_zz_1[3]) begin - buffer_data[31 : 24] <= io_input_payload_data; - end - if(_zz_1[4]) begin - buffer_data[39 : 32] <= io_input_payload_data; - end - if(_zz_1[5]) begin - buffer_data[47 : 40] <= io_input_payload_data; - end - if(_zz_1[6]) begin - buffer_data[55 : 48] <= io_input_payload_data; - end - if(_zz_1[7]) begin - buffer_data[63 : 56] <= io_input_payload_data; - end - end - end - - -endmodule - -module EfxDMA_BmbToAxi4WriteOnlyBridge_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [127:0] io_input_cmd_payload_fragment_data, - input wire [15:0] io_input_cmd_payload_fragment_mask, - input wire [13:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [13:0] io_input_rsp_payload_fragment_context, - output wire io_output_aw_valid, - input wire io_output_aw_ready, - output wire [31:0] io_output_aw_payload_addr, - output wire [7:0] io_output_aw_payload_len, - output wire [2:0] io_output_aw_payload_size, - output wire [3:0] io_output_aw_payload_cache, - output wire [2:0] io_output_aw_payload_prot, - output wire io_output_w_valid, - input wire io_output_w_ready, - output wire [127:0] io_output_w_payload_data, - output wire [15:0] io_output_w_payload_strb, - output wire io_output_w_payload_last, - input wire io_output_b_valid, - output wire io_output_b_ready, - input wire [1:0] io_output_b_payload_resp, - input wire clk, - input wire reset -); - - reg contextRemover_io_output_cmd_ready; - reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; - wire contextRemover_io_input_cmd_ready; - wire contextRemover_io_input_rsp_valid; - wire contextRemover_io_input_rsp_payload_last; - wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; - wire [13:0] contextRemover_io_input_rsp_payload_fragment_context; - wire contextRemover_io_output_cmd_valid; - wire contextRemover_io_output_cmd_payload_last; - wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; - wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; - wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; - wire [127:0] contextRemover_io_output_cmd_payload_fragment_data; - wire [15:0] contextRemover_io_output_cmd_payload_fragment_mask; - wire contextRemover_io_output_rsp_ready; - wire [8:0] _zz_io_output_aw_payload_len; - wire [12:0] _zz_io_output_aw_payload_len_1; - wire [12:0] _zz_io_output_aw_payload_len_2; - wire [3:0] _zz_io_output_aw_payload_len_3; - wire cmdFork_valid; - reg cmdFork_ready; - wire cmdFork_payload_last; - wire [0:0] cmdFork_payload_fragment_opcode; - wire [31:0] cmdFork_payload_fragment_address; - wire [11:0] cmdFork_payload_fragment_length; - wire [127:0] cmdFork_payload_fragment_data; - wire [15:0] cmdFork_payload_fragment_mask; - wire dataFork_valid; - wire dataFork_ready; - wire dataFork_payload_last; - wire [0:0] dataFork_payload_fragment_opcode; - wire [31:0] dataFork_payload_fragment_address; - wire [11:0] dataFork_payload_fragment_length; - wire [127:0] dataFork_payload_fragment_data; - wire [15:0] dataFork_payload_fragment_mask; - reg contextRemover_io_output_cmd_fork2_logic_linkEnable_0; - reg contextRemover_io_output_cmd_fork2_logic_linkEnable_1; - wire when_Stream_l1063; - wire when_Stream_l1063_1; - wire cmdFork_fire; - wire dataFork_fire; - wire contextRemover_io_output_cmd_fire; - reg contextRemover_io_output_cmd_payload_first; - wire when_Stream_l445; - reg cmdStage_valid; - wire cmdStage_ready; - wire cmdStage_payload_last; - wire [0:0] cmdStage_payload_fragment_opcode; - wire [31:0] cmdStage_payload_fragment_address; - wire [11:0] cmdStage_payload_fragment_length; - wire [127:0] cmdStage_payload_fragment_data; - wire [15:0] cmdStage_payload_fragment_mask; - wire when_BmbToAxi4Bridge_l297; - - assign _zz_io_output_aw_payload_len = _zz_io_output_aw_payload_len_1[12 : 4]; - assign _zz_io_output_aw_payload_len_1 = ({1'b0,cmdStage_payload_fragment_length} + _zz_io_output_aw_payload_len_2); - assign _zz_io_output_aw_payload_len_3 = cmdStage_payload_fragment_address[3 : 0]; - assign _zz_io_output_aw_payload_len_2 = {9'd0, _zz_io_output_aw_payload_len_3}; - EfxDMA_BmbContextRemover_1_a048ca8f51874147a1cd65d43e6523ef contextRemover ( - .io_input_cmd_valid (io_input_cmd_valid ), //i - .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_data (io_input_cmd_payload_fragment_data[127:0] ), //i - .io_input_cmd_payload_fragment_mask (io_input_cmd_payload_fragment_mask[15:0] ), //i - .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[13:0] ), //i - .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_input_rsp_ready ), //i - .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[13:0] ), //o - .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o - .io_output_cmd_ready (contextRemover_io_output_cmd_ready ), //i - .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o - .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_cmd_payload_fragment_data (contextRemover_io_output_cmd_payload_fragment_data[127:0] ), //o - .io_output_cmd_payload_fragment_mask (contextRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o - .io_output_rsp_valid (io_output_b_valid ), //i - .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (1'b1 ), //i - .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; - assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; - assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; - always @(*) begin - contextRemover_io_output_cmd_ready = 1'b1; - if(when_Stream_l1063) begin - contextRemover_io_output_cmd_ready = 1'b0; - end - if(when_Stream_l1063_1) begin - contextRemover_io_output_cmd_ready = 1'b0; - end - end - - assign when_Stream_l1063 = ((! cmdFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); - assign when_Stream_l1063_1 = ((! dataFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); - assign cmdFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); - assign cmdFork_payload_last = contextRemover_io_output_cmd_payload_last; - assign cmdFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; - assign cmdFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; - assign cmdFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; - assign cmdFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; - assign cmdFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; - assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); - assign dataFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); - assign dataFork_payload_last = contextRemover_io_output_cmd_payload_last; - assign dataFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; - assign dataFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; - assign dataFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; - assign dataFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; - assign dataFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; - assign dataFork_fire = (dataFork_valid && dataFork_ready); - assign contextRemover_io_output_cmd_fire = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_ready); - assign when_Stream_l445 = (! contextRemover_io_output_cmd_payload_first); - always @(*) begin - cmdStage_valid = cmdFork_valid; - if(when_Stream_l445) begin - cmdStage_valid = 1'b0; - end - end - - always @(*) begin - cmdFork_ready = cmdStage_ready; - if(when_Stream_l445) begin - cmdFork_ready = 1'b1; - end - end - - assign cmdStage_payload_last = cmdFork_payload_last; - assign cmdStage_payload_fragment_opcode = cmdFork_payload_fragment_opcode; - assign cmdStage_payload_fragment_address = cmdFork_payload_fragment_address; - assign cmdStage_payload_fragment_length = cmdFork_payload_fragment_length; - assign cmdStage_payload_fragment_data = cmdFork_payload_fragment_data; - assign cmdStage_payload_fragment_mask = cmdFork_payload_fragment_mask; - assign io_output_aw_valid = cmdStage_valid; - assign cmdStage_ready = io_output_aw_ready; - assign io_output_aw_payload_addr = cmdStage_payload_fragment_address; - assign io_output_aw_payload_len = _zz_io_output_aw_payload_len[7:0]; - assign io_output_aw_payload_size = 3'b100; - assign io_output_aw_payload_prot = 3'b010; - assign io_output_aw_payload_cache = 4'b1111; - assign io_output_w_valid = dataFork_valid; - assign dataFork_ready = io_output_w_ready; - assign io_output_w_payload_data = dataFork_payload_fragment_data; - assign io_output_w_payload_strb = dataFork_payload_fragment_mask; - assign io_output_w_payload_last = dataFork_payload_last; - assign io_output_b_ready = contextRemover_io_output_rsp_ready; - assign when_BmbToAxi4Bridge_l297 = (io_output_b_payload_resp == 2'b00); - always @(*) begin - if(when_BmbToAxi4Bridge_l297) begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; - end else begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; - end - end - - always @(posedge clk) begin - if(reset) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; - contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; - contextRemover_io_output_cmd_payload_first <= 1'b1; - end else begin - if(cmdFork_fire) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b0; - end - if(dataFork_fire) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b0; - end - if(contextRemover_io_output_cmd_ready) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; - contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; - end - if(contextRemover_io_output_cmd_fire) begin - contextRemover_io_output_cmd_payload_first <= contextRemover_io_output_cmd_payload_last; - end - end - end - - -endmodule - -module EfxDMA_BmbSourceRemover_1_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [127:0] io_input_cmd_payload_fragment_data, - input wire [15:0] io_input_cmd_payload_fragment_mask, - input wire [12:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_source, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [12:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [127:0] io_output_cmd_payload_fragment_data, - output wire [15:0] io_output_cmd_payload_fragment_mask, - output wire [13:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [13:0] io_output_rsp_payload_fragment_context -); - - wire [0:0] cmdContext_source; - wire [12:0] cmdContext_context; - wire [0:0] rspContext_source; - wire [12:0] rspContext_context; - wire [13:0] _zz_rspContext_source; - - assign cmdContext_source = io_input_cmd_payload_fragment_source; - assign cmdContext_context = io_input_cmd_payload_fragment_context; - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; - assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; - assign rspContext_source = _zz_rspContext_source[0 : 0]; - assign rspContext_context = _zz_rspContext_source[13 : 1]; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_context = rspContext_context; - -endmodule - -module EfxDMA_BmbToAxi4ReadOnlyBridge_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [21:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [127:0] io_input_rsp_payload_fragment_data, - output wire [21:0] io_input_rsp_payload_fragment_context, - output wire io_output_ar_valid, - input wire io_output_ar_ready, - output wire [31:0] io_output_ar_payload_addr, - output wire [7:0] io_output_ar_payload_len, - output wire [2:0] io_output_ar_payload_size, - output wire [3:0] io_output_ar_payload_cache, - output wire [2:0] io_output_ar_payload_prot, - input wire io_output_r_valid, - output wire io_output_r_ready, - input wire [127:0] io_output_r_payload_data, - input wire [1:0] io_output_r_payload_resp, - input wire io_output_r_payload_last, - input wire clk, - input wire reset -); - - reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; - wire contextRemover_io_input_cmd_ready; - wire contextRemover_io_input_rsp_valid; - wire contextRemover_io_input_rsp_payload_last; - wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; - wire [127:0] contextRemover_io_input_rsp_payload_fragment_data; - wire [21:0] contextRemover_io_input_rsp_payload_fragment_context; - wire contextRemover_io_output_cmd_valid; - wire contextRemover_io_output_cmd_payload_last; - wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; - wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; - wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; - wire contextRemover_io_output_rsp_ready; - wire [8:0] _zz_io_output_ar_payload_len; - wire [12:0] _zz_io_output_ar_payload_len_1; - wire [12:0] _zz_io_output_ar_payload_len_2; - wire [3:0] _zz_io_output_ar_payload_len_3; - wire when_BmbToAxi4Bridge_l243; - - assign _zz_io_output_ar_payload_len = _zz_io_output_ar_payload_len_1[12 : 4]; - assign _zz_io_output_ar_payload_len_1 = ({1'b0,contextRemover_io_output_cmd_payload_fragment_length} + _zz_io_output_ar_payload_len_2); - assign _zz_io_output_ar_payload_len_3 = contextRemover_io_output_cmd_payload_fragment_address[3 : 0]; - assign _zz_io_output_ar_payload_len_2 = {9'd0, _zz_io_output_ar_payload_len_3}; - EfxDMA_BmbContextRemover_a048ca8f51874147a1cd65d43e6523ef contextRemover ( - .io_input_cmd_valid (io_input_cmd_valid ), //i - .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[21:0] ), //i - .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_input_rsp_ready ), //i - .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (contextRemover_io_input_rsp_payload_fragment_data[127:0] ), //o - .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[21:0] ), //o - .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o - .io_output_cmd_ready (io_output_ar_ready ), //i - .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o - .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_rsp_valid (io_output_r_valid ), //i - .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (io_output_r_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (io_output_r_payload_data[127:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; - assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; - assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = contextRemover_io_input_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; - assign io_output_ar_valid = contextRemover_io_output_cmd_valid; - assign io_output_ar_payload_addr = contextRemover_io_output_cmd_payload_fragment_address; - assign io_output_ar_payload_len = _zz_io_output_ar_payload_len[7:0]; - assign io_output_ar_payload_size = 3'b100; - assign io_output_ar_payload_prot = 3'b010; - assign io_output_ar_payload_cache = 4'b1111; - assign io_output_r_ready = contextRemover_io_output_rsp_ready; - assign when_BmbToAxi4Bridge_l243 = (io_output_r_payload_resp == 2'b00); - always @(*) begin - if(when_BmbToAxi4Bridge_l243) begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; - end else begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; - end - end - - -endmodule - -module EfxDMA_BmbSourceRemover_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [20:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_source, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [127:0] io_input_rsp_payload_fragment_data, - output wire [20:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [21:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [127:0] io_output_rsp_payload_fragment_data, - input wire [21:0] io_output_rsp_payload_fragment_context -); - - wire [0:0] cmdContext_source; - wire [20:0] cmdContext_context; - wire [0:0] rspContext_source; - wire [20:0] rspContext_context; - wire [21:0] _zz_rspContext_source; - - assign cmdContext_source = io_input_cmd_payload_fragment_source; - assign cmdContext_context = io_input_cmd_payload_fragment_context; - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; - assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; - assign rspContext_source = _zz_rspContext_source[0 : 0]; - assign rspContext_context = _zz_rspContext_source[21 : 1]; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_context = rspContext_context; - -endmodule - -module EfxDMA_BufferCC_6_a048ca8f51874147a1cd65d43e6523ef ( - input wire [1:0] io_dataIn, - output wire [1:0] io_dataOut, - input wire ctrl_clk, - input wire ctrl_reset -); - - (* async_reg = "true" *) reg [1:0] buffers_0; - (* async_reg = "true" *) reg [1:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge ctrl_clk) begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - - -endmodule - -module EfxDMA_Apb3CC_a048ca8f51874147a1cd65d43e6523ef ( - input wire [13:0] io_input_PADDR, - input wire [0:0] io_input_PSEL, - input wire io_input_PENABLE, - output wire io_input_PREADY, - input wire io_input_PWRITE, - input wire [31:0] io_input_PWDATA, - output wire [31:0] io_input_PRDATA, - output wire io_input_PSLVERROR, - output wire [13:0] io_output_PADDR, - output reg [0:0] io_output_PSEL, - output reg io_output_PENABLE, - input wire io_output_PREADY, - output wire io_output_PWRITE, - output wire [31:0] io_output_PWDATA, - input wire [31:0] io_output_PRDATA, - input wire io_output_PSLVERROR, - input wire ctrl_clk, - input wire ctrl_reset, - input wire clk, - input wire reset -); - - wire flowCCUnsafeByToggle_io_output_valid; - wire [13:0] flowCCUnsafeByToggle_io_output_payload_PADDR; - wire flowCCUnsafeByToggle_io_output_payload_PWRITE; - wire [31:0] flowCCUnsafeByToggle_io_output_payload_PWDATA; - wire flowCCUnsafeByToggle_1_io_output_valid; - wire [31:0] flowCCUnsafeByToggle_1_io_output_payload_PRDATA; - wire flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; - wire inputLogic_inputCmd_valid; - wire [13:0] inputLogic_inputCmd_payload_PADDR; - wire inputLogic_inputCmd_payload_PWRITE; - wire [31:0] inputLogic_inputCmd_payload_PWDATA; - wire inputLogic_inputRsp_valid; - wire [31:0] inputLogic_inputRsp_payload_PRDATA; - wire inputLogic_inputRsp_payload_PSLVERROR; - reg inputLogic_state; - wire flowCCUnsafeByToggle_io_output_toStream_valid; - reg flowCCUnsafeByToggle_io_output_toStream_ready; - wire [13:0] flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; - wire flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; - wire [31:0] flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; - wire outputLogic_outputCmd_valid; - reg outputLogic_outputCmd_ready; - wire [13:0] outputLogic_outputCmd_payload_PADDR; - wire outputLogic_outputCmd_payload_PWRITE; - wire [31:0] outputLogic_outputCmd_payload_PWDATA; - reg flowCCUnsafeByToggle_io_output_toStream_rValid; - wire flowCCUnsafeByToggle_io_output_toStream_fire; - (* async_reg = "true" *) reg [13:0] flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; - (* async_reg = "true" *) reg flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; - (* async_reg = "true" *) reg [31:0] flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; - wire when_Stream_l375; - reg outputLogic_state; - wire when_Apb3CCToggle_l81; - wire outputLogic_outputRsp_valid; - wire [31:0] outputLogic_outputRsp_payload_PRDATA; - wire outputLogic_outputRsp_payload_PSLVERROR; - wire outputLogic_outputCmd_fire; - - EfxDMA_FlowCCUnsafeByToggle_a048ca8f51874147a1cd65d43e6523ef flowCCUnsafeByToggle ( - .io_input_valid (inputLogic_inputCmd_valid ), //i - .io_input_payload_PADDR (inputLogic_inputCmd_payload_PADDR[13:0] ), //i - .io_input_payload_PWRITE (inputLogic_inputCmd_payload_PWRITE ), //i - .io_input_payload_PWDATA (inputLogic_inputCmd_payload_PWDATA[31:0] ), //i - .io_output_valid (flowCCUnsafeByToggle_io_output_valid ), //o - .io_output_payload_PADDR (flowCCUnsafeByToggle_io_output_payload_PADDR[13:0] ), //o - .io_output_payload_PWRITE (flowCCUnsafeByToggle_io_output_payload_PWRITE ), //o - .io_output_payload_PWDATA (flowCCUnsafeByToggle_io_output_payload_PWDATA[31:0]), //o - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_FlowCCUnsafeByToggle_1_a048ca8f51874147a1cd65d43e6523ef flowCCUnsafeByToggle_1 ( - .io_input_valid (outputLogic_outputRsp_valid ), //i - .io_input_payload_PRDATA (outputLogic_outputRsp_payload_PRDATA[31:0] ), //i - .io_input_payload_PSLVERROR (outputLogic_outputRsp_payload_PSLVERROR ), //i - .io_output_valid (flowCCUnsafeByToggle_1_io_output_valid ), //o - .io_output_payload_PRDATA (flowCCUnsafeByToggle_1_io_output_payload_PRDATA[31:0]), //o - .io_output_payload_PSLVERROR (flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR ), //o - .clk (clk ), //i - .reset (reset ), //i - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ) //i - ); - assign inputLogic_inputCmd_valid = ((io_input_PSEL[0] && io_input_PENABLE) && (! inputLogic_state)); - assign inputLogic_inputCmd_payload_PADDR = io_input_PADDR; - assign inputLogic_inputCmd_payload_PWRITE = io_input_PWRITE; - assign inputLogic_inputCmd_payload_PWDATA = io_input_PWDATA; - assign io_input_PREADY = inputLogic_inputRsp_valid; - assign io_input_PRDATA = inputLogic_inputRsp_payload_PRDATA; - assign io_input_PSLVERROR = inputLogic_inputRsp_payload_PSLVERROR; - assign flowCCUnsafeByToggle_io_output_toStream_valid = flowCCUnsafeByToggle_io_output_valid; - assign flowCCUnsafeByToggle_io_output_toStream_payload_PADDR = flowCCUnsafeByToggle_io_output_payload_PADDR; - assign flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE = flowCCUnsafeByToggle_io_output_payload_PWRITE; - assign flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA = flowCCUnsafeByToggle_io_output_payload_PWDATA; - assign flowCCUnsafeByToggle_io_output_toStream_fire = (flowCCUnsafeByToggle_io_output_toStream_valid && flowCCUnsafeByToggle_io_output_toStream_ready); - always @(*) begin - flowCCUnsafeByToggle_io_output_toStream_ready = outputLogic_outputCmd_ready; - if(when_Stream_l375) begin - flowCCUnsafeByToggle_io_output_toStream_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! outputLogic_outputCmd_valid); - assign outputLogic_outputCmd_valid = flowCCUnsafeByToggle_io_output_toStream_rValid; - assign outputLogic_outputCmd_payload_PADDR = flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; - assign outputLogic_outputCmd_payload_PWRITE = flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; - assign outputLogic_outputCmd_payload_PWDATA = flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; - always @(*) begin - io_output_PENABLE = 1'b0; - if(outputLogic_outputCmd_valid) begin - if(when_Apb3CCToggle_l81) begin - io_output_PENABLE = 1'b0; - end else begin - io_output_PENABLE = 1'b1; - end - end - end - - always @(*) begin - io_output_PSEL = 1'b0; - if(outputLogic_outputCmd_valid) begin - io_output_PSEL = 1'b1; - end - end - - assign io_output_PADDR = outputLogic_outputCmd_payload_PADDR; - assign io_output_PWDATA = outputLogic_outputCmd_payload_PWDATA; - assign io_output_PWRITE = outputLogic_outputCmd_payload_PWRITE; - always @(*) begin - outputLogic_outputCmd_ready = 1'b0; - if(outputLogic_outputCmd_valid) begin - if(!when_Apb3CCToggle_l81) begin - if(io_output_PREADY) begin - outputLogic_outputCmd_ready = 1'b1; - end - end - end - end - - assign when_Apb3CCToggle_l81 = (! outputLogic_state); - assign outputLogic_outputCmd_fire = (outputLogic_outputCmd_valid && outputLogic_outputCmd_ready); - assign outputLogic_outputRsp_valid = outputLogic_outputCmd_fire; - assign outputLogic_outputRsp_payload_PRDATA = io_output_PRDATA; - assign outputLogic_outputRsp_payload_PSLVERROR = io_output_PSLVERROR; - assign inputLogic_inputRsp_valid = flowCCUnsafeByToggle_1_io_output_valid; - assign inputLogic_inputRsp_payload_PRDATA = flowCCUnsafeByToggle_1_io_output_payload_PRDATA; - assign inputLogic_inputRsp_payload_PSLVERROR = flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - inputLogic_state <= 1'b0; - end else begin - if(inputLogic_inputCmd_valid) begin - inputLogic_state <= 1'b1; - end - if(inputLogic_inputRsp_valid) begin - inputLogic_state <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(reset) begin - flowCCUnsafeByToggle_io_output_toStream_rValid <= 1'b0; - outputLogic_state <= 1'b0; - end else begin - if(flowCCUnsafeByToggle_io_output_toStream_ready) begin - flowCCUnsafeByToggle_io_output_toStream_rValid <= flowCCUnsafeByToggle_io_output_toStream_valid; - end - if(outputLogic_outputCmd_valid) begin - if(when_Apb3CCToggle_l81) begin - outputLogic_state <= 1'b1; - end else begin - if(io_output_PREADY) begin - outputLogic_state <= 1'b0; - end - end - end - end - end - - always @(posedge clk) begin - if(flowCCUnsafeByToggle_io_output_toStream_fire) begin - flowCCUnsafeByToggle_io_output_toStream_rData_PADDR <= flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; - flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE <= flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; - flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA <= flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; - end - end - - -endmodule - -module EfxDMA_Core_a048ca8f51874147a1cd65d43e6523ef ( - output wire io_sgRead_cmd_valid, - input wire io_sgRead_cmd_ready, - output wire io_sgRead_cmd_payload_last, - output wire [0:0] io_sgRead_cmd_payload_fragment_opcode, - output wire [31:0] io_sgRead_cmd_payload_fragment_address, - output wire [4:0] io_sgRead_cmd_payload_fragment_length, - output wire [0:0] io_sgRead_cmd_payload_fragment_context, - input wire io_sgRead_rsp_valid, - output wire io_sgRead_rsp_ready, - input wire io_sgRead_rsp_payload_last, - input wire [0:0] io_sgRead_rsp_payload_fragment_opcode, - input wire [127:0] io_sgRead_rsp_payload_fragment_data, - input wire [0:0] io_sgRead_rsp_payload_fragment_context, - output wire io_sgWrite_cmd_valid, - input wire io_sgWrite_cmd_ready, - output wire io_sgWrite_cmd_payload_last, - output wire [0:0] io_sgWrite_cmd_payload_fragment_opcode, - output wire [31:0] io_sgWrite_cmd_payload_fragment_address, - output wire [1:0] io_sgWrite_cmd_payload_fragment_length, - output reg [127:0] io_sgWrite_cmd_payload_fragment_data, - output reg [15:0] io_sgWrite_cmd_payload_fragment_mask, - output wire [0:0] io_sgWrite_cmd_payload_fragment_context, - input wire io_sgWrite_rsp_valid, - output wire io_sgWrite_rsp_ready, - input wire io_sgWrite_rsp_payload_last, - input wire [0:0] io_sgWrite_rsp_payload_fragment_opcode, - input wire [0:0] io_sgWrite_rsp_payload_fragment_context, - output reg io_read_cmd_valid, - input wire io_read_cmd_ready, - output wire io_read_cmd_payload_last, - output wire [0:0] io_read_cmd_payload_fragment_opcode, - output wire [31:0] io_read_cmd_payload_fragment_address, - output wire [11:0] io_read_cmd_payload_fragment_length, - output wire [20:0] io_read_cmd_payload_fragment_context, - input wire io_read_rsp_valid, - output wire io_read_rsp_ready, - input wire io_read_rsp_payload_last, - input wire [0:0] io_read_rsp_payload_fragment_opcode, - input wire [127:0] io_read_rsp_payload_fragment_data, - input wire [20:0] io_read_rsp_payload_fragment_context, - output wire io_write_cmd_valid, - input wire io_write_cmd_ready, - output wire io_write_cmd_payload_last, - output wire [0:0] io_write_cmd_payload_fragment_opcode, - output wire [31:0] io_write_cmd_payload_fragment_address, - output wire [11:0] io_write_cmd_payload_fragment_length, - output wire [127:0] io_write_cmd_payload_fragment_data, - output wire [15:0] io_write_cmd_payload_fragment_mask, - output wire [12:0] io_write_cmd_payload_fragment_context, - input wire io_write_rsp_valid, - output wire io_write_rsp_ready, - input wire io_write_rsp_payload_last, - input wire [0:0] io_write_rsp_payload_fragment_opcode, - input wire [12:0] io_write_rsp_payload_fragment_context, - output wire io_outputs_0_valid, - input wire io_outputs_0_ready, - output wire [63:0] io_outputs_0_payload_data, - output wire [7:0] io_outputs_0_payload_mask, - output wire [3:0] io_outputs_0_payload_sink, - output wire io_outputs_0_payload_last, - input wire io_inputs_0_valid, - output reg io_inputs_0_ready, - input wire [63:0] io_inputs_0_payload_data, - input wire [7:0] io_inputs_0_payload_mask, - input wire [3:0] io_inputs_0_payload_sink, - input wire io_inputs_0_payload_last, - output reg [1:0] io_interrupts, - input wire [13:0] io_ctrl_PADDR, - input wire [0:0] io_ctrl_PSEL, - input wire io_ctrl_PENABLE, - output wire io_ctrl_PREADY, - input wire io_ctrl_PWRITE, - input wire [31:0] io_ctrl_PWDATA, - output reg [31:0] io_ctrl_PRDATA, - output wire io_ctrl_PSLVERROR, - output wire ll_0_descriptorUpdate, - output wire ll_1_descriptorUpdate, - input wire clk, - input wire reset -); - - wire [9:0] memory_core_io_writes_0_cmd_payload_address; - wire [6:0] memory_core_io_writes_0_cmd_payload_context; - wire [9:0] memory_core_io_writes_1_cmd_payload_address; - reg [15:0] memory_core_io_writes_1_cmd_payload_mask; - wire [6:0] memory_core_io_writes_1_cmd_payload_context; - wire memory_core_io_reads_0_cmd_valid; - wire [9:0] memory_core_io_reads_0_cmd_payload_address; - wire [2:0] memory_core_io_reads_0_cmd_payload_context; - wire [9:0] memory_core_io_reads_1_cmd_payload_address; - wire [11:0] memory_core_io_reads_1_cmd_payload_context; - wire [15:0] b2m_fsm_aggregate_engine_io_input_payload_mask; - wire b2m_fsm_aggregate_engine_io_flush; - wire [3:0] b2m_fsm_aggregate_engine_io_offset; - wire memory_core_io_writes_0_cmd_ready; - wire memory_core_io_writes_0_rsp_valid; - wire [6:0] memory_core_io_writes_0_rsp_payload_context; - wire memory_core_io_writes_1_cmd_ready; - wire memory_core_io_writes_1_rsp_valid; - wire [6:0] memory_core_io_writes_1_rsp_payload_context; - wire memory_core_io_reads_0_cmd_ready; - wire memory_core_io_reads_0_rsp_valid; - wire [63:0] memory_core_io_reads_0_rsp_payload_data; - wire [7:0] memory_core_io_reads_0_rsp_payload_mask; - wire [2:0] memory_core_io_reads_0_rsp_payload_context; - wire memory_core_io_reads_1_cmd_ready; - wire memory_core_io_reads_1_rsp_valid; - wire [127:0] memory_core_io_reads_1_rsp_payload_data; - wire [15:0] memory_core_io_reads_1_rsp_payload_mask; - wire [11:0] memory_core_io_reads_1_rsp_payload_context; - wire b2m_fsm_aggregate_engine_io_input_ready; - wire [127:0] b2m_fsm_aggregate_engine_io_output_data; - wire [15:0] b2m_fsm_aggregate_engine_io_output_mask; - wire b2m_fsm_aggregate_engine_io_output_consumed; - wire [3:0] b2m_fsm_aggregate_engine_io_output_usedUntil; - wire [26:0] _zz_channels_0_bytesProbe_value; - wire [26:0] _zz_channels_0_bytesProbe_value_1; - wire [13:0] _zz_channels_0_fifo_pop_withOverride_backupNext; - wire [13:0] _zz_channels_0_fifo_pop_withOverride_exposed; - wire [26:0] _zz_channels_0_pop_b2m_selfFlush; - wire [13:0] _zz_channels_0_pop_b2m_request; - wire [10:0] _zz_channels_0_pop_b2m_request_1; - wire [9:0] _zz_channels_0_pop_b2m_request_2; - wire [3:0] _zz_channels_0_pop_b2m_memPending; - wire [3:0] _zz_channels_0_pop_b2m_memPending_1; - wire [0:0] _zz_channels_0_pop_b2m_memPending_2; - wire [3:0] _zz_channels_0_pop_b2m_memPending_3; - wire [0:0] _zz_channels_0_pop_b2m_memPending_4; - wire [10:0] _zz_channels_0_fifo_push_available; - wire [26:0] _zz_channels_1_bytesProbe_value; - wire [26:0] _zz_channels_1_bytesProbe_value_1; - wire [13:0] _zz_channels_1_fifo_pop_withoutOverride_exposed; - wire [3:0] _zz_channels_1_push_m2b_memPending; - wire [3:0] _zz_channels_1_push_m2b_memPending_1; - wire [0:0] _zz_channels_1_push_m2b_memPending_2; - wire [3:0] _zz_channels_1_push_m2b_memPending_3; - wire [0:0] _zz_channels_1_push_m2b_memPending_4; - wire [10:0] _zz_channels_1_push_m2b_loadRequest; - wire [8:0] _zz_channels_1_push_m2b_loadRequest_1; - wire [25:0] _zz_when_DmaSg_l486; - wire [10:0] _zz_channels_1_fifo_push_available; - wire [0:0] _zz_s2b_0_cmd_firsts; - wire [4:0] _zz_s2b_0_cmd_firsts_1; - wire [3:0] _zz_s2b_0_cmd_byteCount_8; - reg [3:0] _zz_s2b_0_cmd_byteCount_9; - wire [2:0] _zz_s2b_0_cmd_byteCount_10; - reg [3:0] _zz_s2b_0_cmd_byteCount_11; - wire [2:0] _zz_s2b_0_cmd_byteCount_12; - reg [3:0] _zz_s2b_0_cmd_byteCount_13; - wire [2:0] _zz_s2b_0_cmd_byteCount_14; - wire [1:0] _zz_s2b_0_cmd_byteCount_15; - wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2; - wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1; - wire [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2; - reg [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; - wire [25:0] _zz_m2b_cmd_s0_length; - wire [25:0] _zz_m2b_cmd_s0_length_1; - wire [25:0] _zz_m2b_cmd_s0_length_2; - wire [25:0] _zz_m2b_cmd_s0_lastBurst; - wire [31:0] _zz_m2b_cmd_s1_context_stop; - wire [31:0] _zz_m2b_cmd_s1_context_stop_1; - wire [31:0] _zz_m2b_cmd_s1_addressNext; - wire [31:0] _zz_m2b_cmd_s1_addressNext_1; - wire [25:0] _zz_m2b_cmd_s1_byteLeftNext; - wire [25:0] _zz_m2b_cmd_s1_byteLeftNext_1; - wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr; - wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_1; - wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_2; - wire [3:0] _zz_m2b_cmd_s1_fifoPushDecr_3; - wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr_4; - wire [1:0] _zz_m2b_cmd_s1_fifoPushDecr_5; - wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; - wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1; - wire [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2; - reg [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; - wire [0:0] _zz_when; - wire [12:0] _zz_b2m_fsm_bytesInBurstP1; - wire [1:0] _zz_b2m_fsm_bytesInBurstP1_1; - wire [31:0] _zz_b2m_fsm_addressNext; - wire [26:0] _zz_b2m_fsm_bytesLeftNext; - wire [13:0] _zz_b2m_fsm_bytesLeftNext_1; - wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1; - wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1_1; - wire [11:0] _zz__zz_b2m_fsm_sel_bytesInBurst_2; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_3; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_4; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_5; - wire [13:0] _zz_b2m_fsm_fifoCompletion; - wire [13:0] _zz_b2m_fsm_fifoCompletion_1; - wire [11:0] _zz_b2m_fsm_beatCounter; - wire [11:0] _zz_b2m_fsm_beatCounter_1; - wire [3:0] _zz_b2m_fsm_beatCounter_2; - wire [10:0] _zz_b2m_fsm_sel_ptr; - wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_1; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_2; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_3; - wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_4; - wire [9:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_5; - wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_6; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_7; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_8; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_9; - wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_10; - wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_11; - wire [3:0] _zz_b2m_fsm_cmd_maskLastTriggerComb; - wire [3:0] _zz_b2m_fsm_cmd_maskLast; - wire _zz_b2m_fsm_cmd_maskLast_1; - wire [0:0] _zz_b2m_fsm_cmd_maskLast_2; - wire [7:0] _zz_b2m_fsm_cmd_maskLast_3; - wire [3:0] _zz_b2m_fsm_cmd_maskLast_4; - wire [3:0] _zz_b2m_fsm_cmd_maskLast_5; - wire [3:0] _zz_b2m_fsm_cmd_maskFirst; - wire _zz_b2m_fsm_cmd_maskFirst_1; - wire [0:0] _zz_b2m_fsm_cmd_maskFirst_2; - wire [7:0] _zz_b2m_fsm_cmd_maskFirst_3; - wire [3:0] _zz_b2m_fsm_cmd_maskFirst_4; - wire [3:0] _zz_b2m_fsm_cmd_maskFirst_5; - wire [0:0] _zz_when_1; - wire [0:0] _zz_when_2; - wire [1:0] _zz__zz_ll_arbiter_head_1; - wire [1:0] _zz__zz_ll_arbiter_head_1_1; - wire [1:0] _zz_ll_arbiter_head_2; - wire [1:0] _zz_ll_arbiter_isJustASink; - wire [1:0] _zz_ll_arbiter_doDescriptorStall; - wire [1:0] _zz_ll_arbiter_onSgStream; - wire [1:0] _zz_ll_cmd_ptr; - wire [1:0] _zz_ll_cmd_ptrNext; - wire [1:0] _zz_ll_cmd_endOfPacket; - wire [0:0] _zz_channels_0_channelStart; - wire [0:0] _zz_channels_0_ctrl_kick; - wire [0:0] _zz_channels_0_channelStart_1; - wire [0:0] _zz_channels_0_ll_sgStart; - wire [0:0] _zz_channels_0_interrupts_completion_valid; - wire [0:0] _zz_channels_0_interrupts_onChannelCompletion_valid; - wire [0:0] _zz_channels_0_interrupts_onLinkedListUpdate_valid; - wire [0:0] _zz_channels_0_interrupts_s2mPacket_valid; - wire [0:0] _zz_channels_1_channelStart; - wire [0:0] _zz_channels_1_ctrl_kick; - wire [0:0] _zz_channels_1_channelStart_1; - wire [0:0] _zz_channels_1_ll_sgStart; - wire [0:0] _zz_channels_1_interrupts_completion_valid; - wire [0:0] _zz_channels_1_interrupts_onChannelCompletion_valid; - wire [0:0] _zz_channels_1_interrupts_onLinkedListUpdate_valid; - wire [31:0] _zz_io_ctrl_PRDATA; - wire [31:0] _zz_io_ctrl_PRDATA_1; - wire [10:0] _zz_channels_0_fifo_push_ptrIncr_value; - wire [0:0] _zz_channels_0_fifo_push_ptrIncr_value_1; - wire [13:0] _zz_channels_0_fifo_pop_bytesIncr_value_1; - wire [3:0] _zz_channels_0_fifo_pop_bytesIncr_value_2; - wire [10:0] _zz_channels_0_fifo_pop_ptrIncr_value; - wire [1:0] _zz_channels_0_fifo_pop_ptrIncr_value_1; - wire [10:0] _zz_channels_1_fifo_push_ptrIncr_value_1; - wire [1:0] _zz_channels_1_fifo_push_ptrIncr_value_2; - wire [13:0] _zz_channels_1_fifo_pop_bytesIncr_value_1; - wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_2; - wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_3; - wire [10:0] _zz_channels_1_fifo_pop_ptrIncr_value; - wire [0:0] _zz_channels_1_fifo_pop_ptrIncr_value_1; - wire ctrl_readErrorFlag; - wire ctrl_writeErrorFlag; - wire ctrl_askWrite; - wire ctrl_askRead; - wire ctrl_doWrite; - wire ctrl_doRead; - reg channels_0_channelStart; - reg channels_0_channelStop; - reg channels_0_channelCompletion; - reg channels_0_channelValid; - reg channels_0_descriptorStart; - reg channels_0_descriptorCompletion; - reg channels_0_descriptorValid; - reg [25:0] channels_0_bytes; - reg [1:0] channels_0_priority; - reg [1:0] channels_0_weight; - reg channels_0_readyToStop; - reg [26:0] channels_0_bytesProbe_value; - reg channels_0_bytesProbe_incr_valid; - reg [11:0] channels_0_bytesProbe_incr_payload; - reg channels_0_ctrl_kick; - reg channels_0_ll_sgStart; - reg channels_0_ll_valid; - reg channels_0_ll_onSgStream; - reg channels_0_ll_head; - reg channels_0_ll_justASync; - reg channels_0_ll_waitDone; - reg channels_0_ll_readDone; - reg channels_0_ll_writeDone; - reg channels_0_ll_gotDescriptorStall; - reg channels_0_ll_controlNoCompletion; - reg channels_0_ll_packet; - reg channels_0_ll_requireSync; - reg [31:0] channels_0_ll_ptr; - reg [31:0] channels_0_ll_ptrNext; - wire channels_0_ll_requestLl; - reg channels_0_ll_descriptorUpdated; - wire when_DmaSg_l318; - wire when_DmaSg_l320; - wire when_DmaSg_l322; - wire when_DmaSg_l328; - wire [10:0] channels_0_fifo_base; - wire [10:0] channels_0_fifo_words; - reg [10:0] channels_0_fifo_push_available; - wire [10:0] channels_0_fifo_push_availableDecr; - reg [10:0] channels_0_fifo_push_ptr; - wire [10:0] channels_0_fifo_push_ptrWithBase; - wire [10:0] channels_0_fifo_push_ptrIncr_value; - reg [10:0] channels_0_fifo_pop_ptr; - wire [13:0] channels_0_fifo_pop_bytes; - wire [10:0] channels_0_fifo_pop_ptrWithBase; - wire [13:0] channels_0_fifo_pop_bytesIncr_value; - wire [13:0] channels_0_fifo_pop_bytesDecr_value; - wire channels_0_fifo_pop_empty; - wire [10:0] channels_0_fifo_pop_ptrIncr_value; - reg [13:0] channels_0_fifo_pop_withOverride_backup; - wire [13:0] channels_0_fifo_pop_withOverride_backupNext; - reg channels_0_fifo_pop_withOverride_load; - reg channels_0_fifo_pop_withOverride_unload; - reg [13:0] channels_0_fifo_pop_withOverride_exposed; - reg channels_0_fifo_pop_withOverride_valid; - wire when_DmaSg_l409; - wire channels_0_fifo_empty; - reg channels_0_push_memory; - reg channels_0_push_s2b_completionOnLast; - reg channels_0_push_s2b_packetEvent; - reg channels_0_push_s2b_packetLock; - reg channels_0_push_s2b_waitFirst; - wire when_DmaSg_l457; - reg channels_0_pop_memory; - wire [11:0] channels_0_pop_b2m_bytePerBurst; - reg channels_0_pop_b2m_fire; - reg channels_0_pop_b2m_waitFinalRsp; - reg channels_0_pop_b2m_flush; - reg channels_0_pop_b2m_packetSync; - reg channels_0_pop_b2m_packet; - wire when_DmaSg_l505; - reg channels_0_pop_b2m_memRsp; - reg [3:0] channels_0_pop_b2m_memPending; - reg [31:0] channels_0_pop_b2m_address; - reg [26:0] channels_0_pop_b2m_bytesLeft; - wire channels_0_pop_b2m_selfFlush; - wire channels_0_pop_b2m_request; - reg [3:0] channels_0_pop_b2m_bytesToSkip; - reg [13:0] channels_0_pop_b2m_decrBytes; - reg channels_0_pop_b2m_memPendingInc; - wire when_DmaSg_l523; - wire when_DmaSg_l532; - wire when_DmaSg_l536; - wire when_DmaSg_l547; - wire when_DmaSg_l563; - wire channels_0_readyForChannelCompletion; - wire when_DmaSg_l575; - reg _zz_when_DmaSg_l593; - wire when_DmaSg_l593; - wire channels_0_s2b_full; - reg [10:0] channels_0_fifo_pop_ptrIncr_value_regNext; - wire when_DmaSg_l255; - reg channels_0_interrupts_completion_enable; - reg channels_0_interrupts_completion_valid; - wire when_DmaSg_l255_1; - wire when_DmaSg_l255_2; - reg channels_0_interrupts_onChannelCompletion_enable; - reg channels_0_interrupts_onChannelCompletion_valid; - wire when_DmaSg_l255_3; - reg channels_0_interrupts_onLinkedListUpdate_enable; - reg channels_0_interrupts_onLinkedListUpdate_valid; - wire when_DmaSg_l255_4; - reg channels_0_interrupts_s2mPacket_enable; - reg channels_0_interrupts_s2mPacket_valid; - wire when_DmaSg_l255_5; - wire when_DmaSg_l625; - reg channels_1_channelStart; - reg channels_1_channelStop; - reg channels_1_channelCompletion; - reg channels_1_channelValid; - reg channels_1_descriptorStart; - reg channels_1_descriptorCompletion; - reg channels_1_descriptorValid; - reg [25:0] channels_1_bytes; - reg [1:0] channels_1_priority; - reg [1:0] channels_1_weight; - reg channels_1_readyToStop; - reg [26:0] channels_1_bytesProbe_value; - reg channels_1_bytesProbe_incr_valid; - reg [11:0] channels_1_bytesProbe_incr_payload; - reg channels_1_ctrl_kick; - reg channels_1_ll_sgStart; - reg channels_1_ll_valid; - reg channels_1_ll_onSgStream; - reg channels_1_ll_head; - reg channels_1_ll_justASync; - reg channels_1_ll_waitDone; - reg channels_1_ll_readDone; - reg channels_1_ll_writeDone; - reg channels_1_ll_gotDescriptorStall; - reg channels_1_ll_controlNoCompletion; - reg channels_1_ll_packet; - reg channels_1_ll_requireSync; - reg [31:0] channels_1_ll_ptr; - reg [31:0] channels_1_ll_ptrNext; - wire channels_1_ll_requestLl; - reg channels_1_ll_descriptorUpdated; - wire when_DmaSg_l318_1; - wire when_DmaSg_l320_1; - wire when_DmaSg_l322_1; - wire when_DmaSg_l328_1; - wire [10:0] channels_1_fifo_base; - wire [10:0] channels_1_fifo_words; - reg [10:0] channels_1_fifo_push_available; - reg [10:0] channels_1_fifo_push_availableDecr; - reg [10:0] channels_1_fifo_push_ptr; - wire [10:0] channels_1_fifo_push_ptrWithBase; - wire [10:0] channels_1_fifo_push_ptrIncr_value; - reg [10:0] channels_1_fifo_pop_ptr; - wire [13:0] channels_1_fifo_pop_bytes; - wire [10:0] channels_1_fifo_pop_ptrWithBase; - wire [13:0] channels_1_fifo_pop_bytesIncr_value; - wire [13:0] channels_1_fifo_pop_bytesDecr_value; - wire channels_1_fifo_pop_empty; - wire [10:0] channels_1_fifo_pop_ptrIncr_value; - reg [13:0] channels_1_fifo_pop_withoutOverride_exposed; - wire channels_1_fifo_empty; - reg channels_1_push_memory; - reg [31:0] channels_1_push_m2b_address; - wire [11:0] channels_1_push_m2b_bytePerBurst; - reg channels_1_push_m2b_loadDone; - reg [25:0] channels_1_push_m2b_bytesLeft; - reg [3:0] channels_1_push_m2b_memPending; - reg channels_1_push_m2b_memPendingIncr; - reg channels_1_push_m2b_memPendingDecr; - reg channels_1_push_m2b_loadRequest; - reg channels_1_pop_memory; - reg channels_1_pop_b2s_last; - reg [3:0] channels_1_pop_b2s_sinkId; - reg channels_1_pop_b2s_veryLastTrigger; - reg channels_1_pop_b2s_veryLastValid; - wire when_DmaSg_l474; - reg [10:0] channels_1_pop_b2s_veryLastPtr; - reg channels_1_pop_b2s_veryLastEndPacket; - wire when_DmaSg_l483; - wire when_DmaSg_l486; - wire when_DmaSg_l562; - reg channels_1_readyForChannelCompletion; - wire when_DmaSg_l566; - wire when_DmaSg_l575_1; - reg _zz_when_DmaSg_l593_1; - wire when_DmaSg_l593_1; - wire channels_1_s2b_full; - reg [10:0] channels_1_fifo_pop_ptrIncr_value_regNext; - wire when_DmaSg_l255_6; - reg channels_1_interrupts_completion_enable; - reg channels_1_interrupts_completion_valid; - wire when_DmaSg_l255_7; - wire when_DmaSg_l255_8; - reg channels_1_interrupts_onChannelCompletion_enable; - reg channels_1_interrupts_onChannelCompletion_valid; - wire when_DmaSg_l255_9; - reg channels_1_interrupts_onLinkedListUpdate_enable; - reg channels_1_interrupts_onLinkedListUpdate_valid; - wire when_DmaSg_l255_10; - wire when_DmaSg_l625_1; - wire io_inputs_0_fire; - wire when_package_l12; - reg io_inputs_0_payload_last_regNextWhen; - wire when_package_l12_1; - reg io_inputs_0_payload_last_regNextWhen_1; - wire when_package_l12_2; - reg io_inputs_0_payload_last_regNextWhen_2; - wire when_package_l12_3; - reg io_inputs_0_payload_last_regNextWhen_3; - wire when_package_l12_4; - reg io_inputs_0_payload_last_regNextWhen_4; - wire when_package_l12_5; - reg io_inputs_0_payload_last_regNextWhen_5; - wire when_package_l12_6; - reg io_inputs_0_payload_last_regNextWhen_6; - wire when_package_l12_7; - reg io_inputs_0_payload_last_regNextWhen_7; - wire when_package_l12_8; - reg io_inputs_0_payload_last_regNextWhen_8; - wire when_package_l12_9; - reg io_inputs_0_payload_last_regNextWhen_9; - wire when_package_l12_10; - reg io_inputs_0_payload_last_regNextWhen_10; - wire when_package_l12_11; - reg io_inputs_0_payload_last_regNextWhen_11; - wire when_package_l12_12; - reg io_inputs_0_payload_last_regNextWhen_12; - wire when_package_l12_13; - reg io_inputs_0_payload_last_regNextWhen_13; - wire when_package_l12_14; - reg io_inputs_0_payload_last_regNextWhen_14; - wire when_package_l12_15; - reg io_inputs_0_payload_last_regNextWhen_15; - wire [15:0] s2b_0_cmd_firsts; - wire s2b_0_cmd_first; - wire [0:0] s2b_0_cmd_channelsOh; - wire s2b_0_cmd_noHit; - wire [0:0] s2b_0_cmd_channelsFull; - reg io_inputs_0_thrown_valid; - wire io_inputs_0_thrown_ready; - wire [63:0] io_inputs_0_thrown_payload_data; - wire [7:0] io_inputs_0_thrown_payload_mask; - wire [3:0] io_inputs_0_thrown_payload_sink; - wire io_inputs_0_thrown_payload_last; - wire _zz_io_inputs_0_thrown_ready; - wire s2b_0_cmd_sinkHalted_valid; - wire s2b_0_cmd_sinkHalted_ready; - wire [63:0] s2b_0_cmd_sinkHalted_payload_data; - wire [7:0] s2b_0_cmd_sinkHalted_payload_mask; - wire [3:0] s2b_0_cmd_sinkHalted_payload_sink; - wire s2b_0_cmd_sinkHalted_payload_last; - wire [3:0] _zz_s2b_0_cmd_byteCount; - wire [3:0] _zz_s2b_0_cmd_byteCount_1; - wire [3:0] _zz_s2b_0_cmd_byteCount_2; - wire [3:0] _zz_s2b_0_cmd_byteCount_3; - wire [3:0] _zz_s2b_0_cmd_byteCount_4; - wire [3:0] _zz_s2b_0_cmd_byteCount_5; - wire [3:0] _zz_s2b_0_cmd_byteCount_6; - wire [3:0] _zz_s2b_0_cmd_byteCount_7; - wire [3:0] s2b_0_cmd_byteCount; - wire [0:0] s2b_0_cmd_context_channel; - wire [3:0] s2b_0_cmd_context_bytes; - wire s2b_0_cmd_context_flush; - wire s2b_0_cmd_context_packet; - wire memory_core_io_writes_0_cmd_fire; - wire when_DmaSg_l665; - wire [0:0] s2b_0_rsp_context_channel; - wire [3:0] s2b_0_rsp_context_bytes; - wire s2b_0_rsp_context_flush; - wire s2b_0_rsp_context_packet; - wire [6:0] _zz_s2b_0_rsp_context_channel; - wire _zz_channels_0_fifo_pop_bytesIncr_value; - wire when_DmaSg_l679; - wire when_DmaSg_l681; - wire when_DmaSg_l682; - wire [0:0] b2s_0_cmd_channelsOh; - wire [0:0] b2s_0_cmd_context_channel; - wire b2s_0_cmd_context_veryLast; - wire b2s_0_cmd_context_endPacket; - wire [10:0] b2s_0_cmd_veryLastPtr; - wire [10:0] b2s_0_cmd_address; - wire [0:0] b2s_0_rsp_context_channel; - wire b2s_0_rsp_context_veryLast; - wire b2s_0_rsp_context_endPacket; - wire [2:0] _zz_b2s_0_rsp_context_channel; - wire io_outputs_0_fire; - wire when_DmaSg_l725; - wire when_DmaSg_l726; - reg m2b_cmd_s0_valid; - wire [1:0] _zz_m2b_cmd_s0_priority_masked; - wire [0:0] m2b_cmd_s0_priority_masked; - reg [0:0] m2b_cmd_s0_priority_roundRobins_0; - reg [0:0] m2b_cmd_s0_priority_roundRobins_1; - reg [0:0] m2b_cmd_s0_priority_roundRobins_2; - reg [0:0] m2b_cmd_s0_priority_roundRobins_3; - reg [1:0] m2b_cmd_s0_priority_counter; - wire [0:0] _zz_m2b_cmd_s0_priority_chosenOh; - wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_1; - wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_2; - wire [0:0] m2b_cmd_s0_priority_chosenOh; - wire m2b_cmd_s0_priority_weightLast; - wire [0:0] m2b_cmd_s0_priority_contextNext; - wire when_DmaSg_l758; - wire when_DmaSg_l760; - wire when_DmaSg_l763; - wire when_DmaSg_l763_1; - wire when_DmaSg_l763_2; - wire when_DmaSg_l763_3; - wire when_DmaSg_l773; - wire [31:0] m2b_cmd_s0_address; - wire [25:0] m2b_cmd_s0_bytesLeft; - wire [11:0] m2b_cmd_s0_readAddressBurstRange; - wire [11:0] m2b_cmd_s0_lengthHead; - wire [11:0] m2b_cmd_s0_length; - wire m2b_cmd_s0_lastBurst; - reg m2b_cmd_s1_valid; - reg [31:0] m2b_cmd_s1_address; - reg [11:0] m2b_cmd_s1_length; - reg m2b_cmd_s1_lastBurst; - reg [25:0] m2b_cmd_s1_bytesLeft; - wire [3:0] m2b_cmd_s1_context_start; - wire [3:0] m2b_cmd_s1_context_stop; - wire [11:0] m2b_cmd_s1_context_length; - wire m2b_cmd_s1_context_last; - wire [31:0] m2b_cmd_s1_addressNext; - wire [25:0] m2b_cmd_s1_byteLeftNext; - wire [9:0] m2b_cmd_s1_fifoPushDecr; - wire when_DmaSg_l828; - wire [3:0] m2b_rsp_context_start; - wire [3:0] m2b_rsp_context_stop; - wire [11:0] m2b_rsp_context_length; - wire m2b_rsp_context_last; - wire [20:0] _zz_m2b_rsp_context_start; - wire m2b_rsp_veryLast; - wire io_read_rsp_fire; - wire when_DmaSg_l847; - wire when_DmaSg_l848; - reg m2b_rsp_first; - wire m2b_rsp_writeContext_last; - wire m2b_rsp_writeContext_lastOfBurst; - wire [4:0] m2b_rsp_writeContext_loadByteInNextBeat; - wire memory_core_io_writes_1_cmd_fire; - wire _zz_channels_1_fifo_push_ptrIncr_value; - wire when_DmaSg_l874; - wire m2b_writeRsp_context_last; - wire m2b_writeRsp_context_lastOfBurst; - wire [4:0] m2b_writeRsp_context_loadByteInNextBeat; - wire [6:0] _zz_m2b_writeRsp_context_last; - wire _zz_channels_1_fifo_pop_bytesIncr_value; - wire when_DmaSg_l893; - reg b2m_fsm_sel_valid; - reg b2m_fsm_sel_ready; - reg [11:0] b2m_fsm_sel_bytePerBurst; - reg [11:0] b2m_fsm_sel_bytesInBurst; - reg [13:0] b2m_fsm_sel_bytesInFifo; - reg [31:0] b2m_fsm_sel_address; - reg [10:0] b2m_fsm_sel_ptr; - reg [10:0] b2m_fsm_sel_ptrMask; - reg b2m_fsm_sel_flush; - reg b2m_fsm_sel_packet; - reg [25:0] b2m_fsm_sel_bytesLeft; - reg b2m_fsm_arbiter_logic_valid; - wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_masked; - wire [0:0] b2m_fsm_arbiter_logic_priority_masked; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_0; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_1; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_2; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_3; - reg [1:0] b2m_fsm_arbiter_logic_priority_counter; - wire [0:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh; - wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1; - wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; - wire [0:0] b2m_fsm_arbiter_logic_priority_chosenOh; - wire b2m_fsm_arbiter_logic_priority_weightLast; - wire [0:0] b2m_fsm_arbiter_logic_priority_contextNext; - wire when_DmaSg_l758_1; - wire when_DmaSg_l760_1; - wire when_DmaSg_l763_4; - wire when_DmaSg_l763_5; - wire when_DmaSg_l763_6; - wire when_DmaSg_l763_7; - wire when_DmaSg_l773_1; - wire when_DmaSg_l935; - wire [12:0] b2m_fsm_bytesInBurstP1; - wire [31:0] b2m_fsm_addressNext; - wire [26:0] b2m_fsm_bytesLeftNext; - wire b2m_fsm_isFinalCmd; - reg [7:0] b2m_fsm_beatCounter; - reg b2m_fsm_sel_valid_regNext; - wire b2m_fsm_s0; - reg b2m_fsm_s1; - reg b2m_fsm_s2; - wire when_DmaSg_l986; - wire [13:0] _zz_b2m_fsm_sel_bytesInBurst; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_1; - wire [11:0] _zz_b2m_fsm_sel_bytesInBurst_2; - wire b2m_fsm_fifoCompletion; - wire when_DmaSg_l996; - wire when_DmaSg_l1001; - reg b2m_fsm_toggle; - wire when_DmaSg_l1013; - wire [10:0] b2m_fsm_fetch_context_ptr; - wire b2m_fsm_fetch_context_toggle; - wire when_DmaSg_l1033; - wire [10:0] b2m_fsm_aggregate_context_ptr; - wire b2m_fsm_aggregate_context_toggle; - wire [11:0] _zz_b2m_fsm_aggregate_context_ptr; - wire memory_core_io_reads_1_rsp_s2mPipe_valid; - reg memory_core_io_reads_1_rsp_s2mPipe_ready; - wire [127:0] memory_core_io_reads_1_rsp_s2mPipe_payload_data; - wire [15:0] memory_core_io_reads_1_rsp_s2mPipe_payload_mask; - wire [11:0] memory_core_io_reads_1_rsp_s2mPipe_payload_context; - reg memory_core_io_reads_1_rsp_rValidN; - reg [127:0] memory_core_io_reads_1_rsp_rData_data; - reg [15:0] memory_core_io_reads_1_rsp_rData_mask; - reg [11:0] memory_core_io_reads_1_rsp_rData_context; - wire when_Stream_l445; - reg b2m_fsm_aggregate_memoryPort_valid; - wire b2m_fsm_aggregate_memoryPort_ready; - wire [127:0] b2m_fsm_aggregate_memoryPort_payload_data; - wire [15:0] b2m_fsm_aggregate_memoryPort_payload_mask; - wire [11:0] b2m_fsm_aggregate_memoryPort_payload_context; - reg b2m_fsm_aggregate_first; - wire b2m_fsm_aggregate_memoryPort_fire; - wire when_DmaSg_l1050; - wire [3:0] b2m_fsm_aggregate_bytesToSkip; - wire [15:0] b2m_fsm_aggregate_bytesToSkipMask; - reg _zz_io_flush; - wire [3:0] b2m_fsm_cmd_maskFirstTrigger; - wire [3:0] b2m_fsm_cmd_maskLastTriggerComb; - reg [3:0] b2m_fsm_cmd_maskLastTriggerReg; - reg [15:0] b2m_fsm_cmd_maskLast; - wire [15:0] b2m_fsm_cmd_maskFirst; - wire b2m_fsm_cmd_enoughAggregation; - wire io_write_cmd_fire; - reg io_write_cmd_payload_first; - wire b2m_fsm_cmd_doPtrIncr; - wire [11:0] b2m_fsm_cmd_context_length; - wire b2m_fsm_cmd_context_doPacketSync; - wire when_DmaSg_l1102; - wire [11:0] b2m_rsp_context_length; - wire b2m_rsp_context_doPacketSync; - wire [12:0] _zz_b2m_rsp_context_length; - wire io_write_rsp_fire; - wire when_DmaSg_l1116; - wire [1:0] _zz_ll_arbiter_head; - wire _zz_ll_arbiter_head_1; - wire ll_arbiter_head; - wire ll_arbiter_isJustASink; - wire ll_arbiter_doDescriptorStall; - wire ll_arbiter_onSgStream; - reg ll_cmd_valid; - wire when_DmaSg_l1149; - reg ll_cmd_oh_0; - reg ll_cmd_oh_1; - wire when_DmaSg_l1148; - reg [31:0] ll_cmd_ptr; - wire when_DmaSg_l1148_1; - reg [31:0] ll_cmd_ptrNext; - wire when_DmaSg_l1148_2; - reg [26:0] ll_cmd_bytesDone; - wire when_DmaSg_l1148_3; - reg ll_cmd_endOfPacket; - wire when_DmaSg_l1154; - reg ll_cmd_isJustASink; - wire when_DmaSg_l1155; - reg ll_cmd_doDescriptorStall; - wire when_DmaSg_l1156; - reg ll_cmd_onSgStream; - reg ll_cmd_readFired; - reg ll_cmd_writeFired; - wire when_DmaSg_l1160; - wire when_DmaSg_l1161; - wire when_DmaSg_l1169; - wire when_DmaSg_l1169_1; - wire when_DmaSg_l1177; - wire [0:0] ll_cmd_context_channel; - wire [3:0] ll_cmd_writeMaskSplit_0; - wire [3:0] ll_cmd_writeMaskSplit_1; - wire [3:0] ll_cmd_writeMaskSplit_2; - wire [3:0] ll_cmd_writeMaskSplit_3; - wire [31:0] ll_cmd_writeDataSplit_0; - wire [31:0] ll_cmd_writeDataSplit_1; - wire [31:0] ll_cmd_writeDataSplit_2; - wire [31:0] ll_cmd_writeDataSplit_3; - wire io_sgRead_cmd_fire; - wire io_sgWrite_cmd_fire; - wire [0:0] ll_readRsp_context_channel; - wire [1:0] _zz_ll_readRsp_oh_0; - wire ll_readRsp_oh_0; - wire ll_readRsp_oh_1; - reg [0:0] ll_readRsp_beatCounter; - reg ll_readRsp_completed; - wire io_sgRead_rsp_fire; - wire when_DmaSg_l1248; - wire when_DmaSg_l1248_1; - wire when_DmaSg_l1248_2; - wire when_DmaSg_l1248_3; - wire when_DmaSg_l1248_4; - wire when_DmaSg_l1248_5; - wire when_DmaSg_l1248_6; - wire when_DmaSg_l1271; - wire [0:0] ll_writeRsp_context_channel; - wire [1:0] _zz_ll_writeRsp_oh_0; - wire ll_writeRsp_oh_0; - wire ll_writeRsp_oh_1; - wire io_sgWrite_rsp_fire; - reg when_BusSlaveFactory_l377; - wire when_BusSlaveFactory_l379; - reg when_BusSlaveFactory_l377_1; - wire when_BusSlaveFactory_l379_1; - reg when_BusSlaveFactory_l377_2; - wire when_BusSlaveFactory_l379_2; - reg when_BusSlaveFactory_l377_3; - wire when_BusSlaveFactory_l379_3; - reg when_BusSlaveFactory_l341; - wire when_BusSlaveFactory_l347; - reg when_BusSlaveFactory_l341_1; - wire when_BusSlaveFactory_l347_1; - reg when_BusSlaveFactory_l341_2; - wire when_BusSlaveFactory_l347_2; - reg when_BusSlaveFactory_l341_3; - wire when_BusSlaveFactory_l347_3; - reg when_BusSlaveFactory_l377_4; - wire when_BusSlaveFactory_l379_4; - reg when_BusSlaveFactory_l377_5; - wire when_BusSlaveFactory_l379_5; - reg when_BusSlaveFactory_l377_6; - wire when_BusSlaveFactory_l379_6; - reg when_BusSlaveFactory_l377_7; - wire when_BusSlaveFactory_l379_7; - reg when_BusSlaveFactory_l341_4; - wire when_BusSlaveFactory_l347_4; - reg when_BusSlaveFactory_l341_5; - wire when_BusSlaveFactory_l347_5; - reg when_BusSlaveFactory_l341_6; - wire when_BusSlaveFactory_l347_6; - wire when_Apb3SlaveFactory_l81; - wire when_Apb3SlaveFactory_l81_1; - wire when_Apb3SlaveFactory_l81_2; - wire when_Apb3SlaveFactory_l81_3; - function [15:0] zz_io_sgWrite_cmd_payload_fragment_mask(input dummy); - begin - zz_io_sgWrite_cmd_payload_fragment_mask[7 : 4] = 4'b0000; - zz_io_sgWrite_cmd_payload_fragment_mask[11 : 8] = 4'b0000; - zz_io_sgWrite_cmd_payload_fragment_mask[15 : 12] = 4'b0000; - zz_io_sgWrite_cmd_payload_fragment_mask[3 : 0] = 4'b1111; - end - endfunction - wire [15:0] _zz_1; - - assign _zz_channels_0_bytesProbe_value = (channels_0_bytesProbe_value + _zz_channels_0_bytesProbe_value_1); - assign _zz_channels_0_bytesProbe_value_1 = {15'd0, channels_0_bytesProbe_incr_payload}; - assign _zz_channels_0_fifo_pop_withOverride_backupNext = (channels_0_fifo_pop_withOverride_backup + channels_0_fifo_pop_bytesIncr_value); - assign _zz_channels_0_fifo_pop_withOverride_exposed = (channels_0_fifo_pop_withOverride_exposed - channels_0_fifo_pop_bytesDecr_value); - assign _zz_channels_0_pop_b2m_selfFlush = {13'd0, channels_0_fifo_pop_bytes}; - assign _zz_channels_0_pop_b2m_request = {2'd0, channels_0_pop_b2m_bytePerBurst}; - assign _zz_channels_0_pop_b2m_request_2 = (channels_0_fifo_words >>> 1'd1); - assign _zz_channels_0_pop_b2m_request_1 = {1'd0, _zz_channels_0_pop_b2m_request_2}; - assign _zz_channels_0_pop_b2m_memPending = (channels_0_pop_b2m_memPending + _zz_channels_0_pop_b2m_memPending_1); - assign _zz_channels_0_pop_b2m_memPending_2 = channels_0_pop_b2m_memPendingInc; - assign _zz_channels_0_pop_b2m_memPending_1 = {3'd0, _zz_channels_0_pop_b2m_memPending_2}; - assign _zz_channels_0_pop_b2m_memPending_4 = channels_0_pop_b2m_memRsp; - assign _zz_channels_0_pop_b2m_memPending_3 = {3'd0, _zz_channels_0_pop_b2m_memPending_4}; - assign _zz_channels_0_fifo_push_available = (channels_0_fifo_push_available + channels_0_fifo_pop_ptrIncr_value_regNext); - assign _zz_channels_1_bytesProbe_value = (channels_1_bytesProbe_value + _zz_channels_1_bytesProbe_value_1); - assign _zz_channels_1_bytesProbe_value_1 = {15'd0, channels_1_bytesProbe_incr_payload}; - assign _zz_channels_1_fifo_pop_withoutOverride_exposed = (channels_1_fifo_pop_withoutOverride_exposed + channels_1_fifo_pop_bytesIncr_value); - assign _zz_channels_1_push_m2b_memPending = (channels_1_push_m2b_memPending + _zz_channels_1_push_m2b_memPending_1); - assign _zz_channels_1_push_m2b_memPending_2 = channels_1_push_m2b_memPendingIncr; - assign _zz_channels_1_push_m2b_memPending_1 = {3'd0, _zz_channels_1_push_m2b_memPending_2}; - assign _zz_channels_1_push_m2b_memPending_4 = channels_1_push_m2b_memPendingDecr; - assign _zz_channels_1_push_m2b_memPending_3 = {3'd0, _zz_channels_1_push_m2b_memPending_4}; - assign _zz_channels_1_push_m2b_loadRequest_1 = (channels_1_push_m2b_bytePerBurst >>> 2'd3); - assign _zz_channels_1_push_m2b_loadRequest = {2'd0, _zz_channels_1_push_m2b_loadRequest_1}; - assign _zz_when_DmaSg_l486 = {14'd0, channels_1_push_m2b_bytePerBurst}; - assign _zz_channels_1_fifo_push_available = (channels_1_fifo_push_available + channels_1_fifo_pop_ptrIncr_value_regNext); - assign _zz_s2b_0_cmd_byteCount_8 = (_zz_s2b_0_cmd_byteCount_9 + _zz_s2b_0_cmd_byteCount_11); - assign _zz_s2b_0_cmd_byteCount_15 = {s2b_0_cmd_sinkHalted_payload_mask[7],s2b_0_cmd_sinkHalted_payload_mask[6]}; - assign _zz_s2b_0_cmd_byteCount_14 = {1'd0, _zz_s2b_0_cmd_byteCount_15}; - assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 - _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1); - assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2 = _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; - assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1 = {1'd0, _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2}; - assign _zz_m2b_cmd_s0_length = ((_zz_m2b_cmd_s0_length_1 < m2b_cmd_s0_bytesLeft) ? _zz_m2b_cmd_s0_length_2 : m2b_cmd_s0_bytesLeft); - assign _zz_m2b_cmd_s0_length_1 = {14'd0, m2b_cmd_s0_lengthHead}; - assign _zz_m2b_cmd_s0_length_2 = {14'd0, m2b_cmd_s0_lengthHead}; - assign _zz_m2b_cmd_s0_lastBurst = {14'd0, m2b_cmd_s0_length}; - assign _zz_m2b_cmd_s1_context_stop = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_context_stop_1); - assign _zz_m2b_cmd_s1_context_stop_1 = {20'd0, m2b_cmd_s1_length}; - assign _zz_m2b_cmd_s1_addressNext = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_addressNext_1); - assign _zz_m2b_cmd_s1_addressNext_1 = {20'd0, m2b_cmd_s1_length}; - assign _zz_m2b_cmd_s1_byteLeftNext = (m2b_cmd_s1_bytesLeft - _zz_m2b_cmd_s1_byteLeftNext_1); - assign _zz_m2b_cmd_s1_byteLeftNext_1 = {14'd0, m2b_cmd_s1_length}; - assign _zz_m2b_cmd_s1_fifoPushDecr = ({1'b0,(_zz_m2b_cmd_s1_fifoPushDecr_1 | 12'h00f)} + _zz_m2b_cmd_s1_fifoPushDecr_4); - assign _zz_m2b_cmd_s1_fifoPushDecr_1 = (_zz_m2b_cmd_s1_fifoPushDecr_2 + io_read_cmd_payload_fragment_length); - assign _zz_m2b_cmd_s1_fifoPushDecr_3 = m2b_cmd_s1_address[3 : 0]; - assign _zz_m2b_cmd_s1_fifoPushDecr_2 = {8'd0, _zz_m2b_cmd_s1_fifoPushDecr_3}; - assign _zz_m2b_cmd_s1_fifoPushDecr_5 = {1'b0,1'b1}; - assign _zz_m2b_cmd_s1_fifoPushDecr_4 = {11'd0, _zz_m2b_cmd_s1_fifoPushDecr_5}; - assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 - _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1); - assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2 = _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; - assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1 = {1'd0, _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2}; - assign _zz_when = 1'b1; - assign _zz_b2m_fsm_bytesInBurstP1_1 = {1'b0,1'b1}; - assign _zz_b2m_fsm_bytesInBurstP1 = {11'd0, _zz_b2m_fsm_bytesInBurstP1_1}; - assign _zz_b2m_fsm_addressNext = {19'd0, b2m_fsm_bytesInBurstP1}; - assign _zz_b2m_fsm_bytesLeftNext_1 = {1'b0,b2m_fsm_bytesInBurstP1}; - assign _zz_b2m_fsm_bytesLeftNext = {13'd0, _zz_b2m_fsm_bytesLeftNext_1}; - assign _zz__zz_b2m_fsm_sel_bytesInBurst_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; - assign _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; - assign _zz__zz_b2m_fsm_sel_bytesInBurst_2 = b2m_fsm_sel_address[11:0]; - assign _zz_b2m_fsm_sel_bytesInBurst_3 = ((_zz_b2m_fsm_sel_bytesInBurst_1 < _zz_b2m_fsm_sel_bytesInBurst_4) ? _zz_b2m_fsm_sel_bytesInBurst_1 : _zz_b2m_fsm_sel_bytesInBurst_5); - assign _zz_b2m_fsm_sel_bytesInBurst_4 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; - assign _zz_b2m_fsm_sel_bytesInBurst_5 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; - assign _zz_b2m_fsm_fifoCompletion = {2'd0, b2m_fsm_sel_bytesInBurst}; - assign _zz_b2m_fsm_fifoCompletion_1 = (b2m_fsm_sel_bytesInFifo - 14'h0001); - assign _zz_b2m_fsm_beatCounter = (_zz_b2m_fsm_beatCounter_1 + b2m_fsm_sel_bytesInBurst); - assign _zz_b2m_fsm_beatCounter_2 = b2m_fsm_sel_address[3 : 0]; - assign _zz_b2m_fsm_beatCounter_1 = {8'd0, _zz_b2m_fsm_beatCounter_2}; - assign _zz_b2m_fsm_sel_ptr = (b2m_fsm_sel_ptr + 11'h002); - assign _zz_b2m_fsm_cmd_maskLastTriggerComb = b2m_fsm_sel_bytesInBurst[3:0]; - assign _zz_when_1 = 1'b1; - assign _zz_when_2 = 1'b1; - assign _zz__zz_ll_arbiter_head_1 = (_zz_ll_arbiter_head & (~ _zz__zz_ll_arbiter_head_1_1)); - assign _zz__zz_ll_arbiter_head_1_1 = (_zz_ll_arbiter_head - 2'b01); - assign _zz_ll_arbiter_head_2 = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_isJustASink = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_doDescriptorStall = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_onSgStream = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_cmd_ptr = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_cmd_ptrNext = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_cmd_endOfPacket = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_channels_0_channelStart = 1'b1; - assign _zz_channels_0_ctrl_kick = 1'b1; - assign _zz_channels_0_channelStart_1 = 1'b1; - assign _zz_channels_0_ll_sgStart = 1'b1; - assign _zz_channels_0_interrupts_completion_valid = 1'b0; - assign _zz_channels_0_interrupts_onChannelCompletion_valid = 1'b0; - assign _zz_channels_0_interrupts_onLinkedListUpdate_valid = 1'b0; - assign _zz_channels_0_interrupts_s2mPacket_valid = 1'b0; - assign _zz_channels_1_channelStart = 1'b1; - assign _zz_channels_1_ctrl_kick = 1'b1; - assign _zz_channels_1_channelStart_1 = 1'b1; - assign _zz_channels_1_ll_sgStart = 1'b1; - assign _zz_channels_1_interrupts_completion_valid = 1'b0; - assign _zz_channels_1_interrupts_onChannelCompletion_valid = 1'b0; - assign _zz_channels_1_interrupts_onLinkedListUpdate_valid = 1'b0; - assign _zz_io_ctrl_PRDATA = channels_0_ll_ptr; - assign _zz_io_ctrl_PRDATA_1 = channels_1_ll_ptr; - assign _zz_channels_0_fifo_push_ptrIncr_value_1 = ((when_DmaSg_l665 && (|s2b_0_cmd_sinkHalted_payload_mask)) ? 1'b1 : 1'b0); - assign _zz_channels_0_fifo_push_ptrIncr_value = {10'd0, _zz_channels_0_fifo_push_ptrIncr_value_1}; - assign _zz_channels_0_fifo_pop_bytesIncr_value_2 = (_zz_channels_0_fifo_pop_bytesIncr_value ? s2b_0_rsp_context_bytes : 4'b0000); - assign _zz_channels_0_fifo_pop_bytesIncr_value_1 = {10'd0, _zz_channels_0_fifo_pop_bytesIncr_value_2}; - assign _zz_channels_0_fifo_pop_ptrIncr_value_1 = ((b2m_fsm_cmd_doPtrIncr && 1'b1) ? 2'b10 : 2'b00); - assign _zz_channels_0_fifo_pop_ptrIncr_value = {9'd0, _zz_channels_0_fifo_pop_ptrIncr_value_1}; - assign _zz_channels_1_fifo_push_ptrIncr_value_2 = (_zz_channels_1_fifo_push_ptrIncr_value ? 2'b10 : 2'b00); - assign _zz_channels_1_fifo_push_ptrIncr_value_1 = {9'd0, _zz_channels_1_fifo_push_ptrIncr_value_2}; - assign _zz_channels_1_fifo_pop_bytesIncr_value_2 = (_zz_channels_1_fifo_pop_bytesIncr_value ? _zz_channels_1_fifo_pop_bytesIncr_value_3 : 5'h0); - assign _zz_channels_1_fifo_pop_bytesIncr_value_1 = {9'd0, _zz_channels_1_fifo_pop_bytesIncr_value_2}; - assign _zz_channels_1_fifo_pop_bytesIncr_value_3 = (m2b_writeRsp_context_loadByteInNextBeat + 5'h01); - assign _zz_channels_1_fifo_pop_ptrIncr_value_1 = ((b2s_0_cmd_channelsOh[0] && memory_core_io_reads_0_cmd_ready) ? 1'b1 : 1'b0); - assign _zz_channels_1_fifo_pop_ptrIncr_value = {10'd0, _zz_channels_1_fifo_pop_ptrIncr_value_1}; - assign _zz_s2b_0_cmd_byteCount_10 = {s2b_0_cmd_sinkHalted_payload_mask[2],{s2b_0_cmd_sinkHalted_payload_mask[1],s2b_0_cmd_sinkHalted_payload_mask[0]}}; - assign _zz_s2b_0_cmd_byteCount_12 = {s2b_0_cmd_sinkHalted_payload_mask[5],{s2b_0_cmd_sinkHalted_payload_mask[4],s2b_0_cmd_sinkHalted_payload_mask[3]}}; - assign _zz_s2b_0_cmd_firsts = io_inputs_0_payload_last_regNextWhen_5; - assign _zz_s2b_0_cmd_firsts_1 = {io_inputs_0_payload_last_regNextWhen_4,{io_inputs_0_payload_last_regNextWhen_3,{io_inputs_0_payload_last_regNextWhen_2,{io_inputs_0_payload_last_regNextWhen_1,io_inputs_0_payload_last_regNextWhen}}}}; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask = 4'b1101; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_1 = (! b2m_fsm_aggregate_first); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_2 = (b2m_fsm_aggregate_bytesToSkip <= 4'b1100); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_3 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1011)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_4 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1010)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_5 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1001)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1000)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask_6)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_7 || _zz_b2m_fsm_aggregate_bytesToSkipMask_8),{_zz_b2m_fsm_aggregate_bytesToSkipMask_9,{_zz_b2m_fsm_aggregate_bytesToSkipMask_10,_zz_b2m_fsm_aggregate_bytesToSkipMask_11}}}}}}; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_6 = 4'b0111; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_7 = (! b2m_fsm_aggregate_first); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_8 = (b2m_fsm_aggregate_bytesToSkip <= 4'b0110); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_9 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0101)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_10 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0100)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_11 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0011)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0010)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0001)),((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0000))}}}; - assign _zz_b2m_fsm_cmd_maskLast = 4'b1010; - assign _zz_b2m_fsm_cmd_maskLast_1 = (4'b1001 <= b2m_fsm_cmd_maskLastTriggerComb); - assign _zz_b2m_fsm_cmd_maskLast_2 = (4'b1000 <= b2m_fsm_cmd_maskLastTriggerComb); - assign _zz_b2m_fsm_cmd_maskLast_3 = {(4'b0111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0011 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0010 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast_4 <= b2m_fsm_cmd_maskLastTriggerComb),(_zz_b2m_fsm_cmd_maskLast_5 <= b2m_fsm_cmd_maskLastTriggerComb)}}}}}}}; - assign _zz_b2m_fsm_cmd_maskLast_4 = 4'b0001; - assign _zz_b2m_fsm_cmd_maskLast_5 = 4'b0000; - assign _zz_b2m_fsm_cmd_maskFirst = 4'b1010; - assign _zz_b2m_fsm_cmd_maskFirst_1 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1001); - assign _zz_b2m_fsm_cmd_maskFirst_2 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1000); - assign _zz_b2m_fsm_cmd_maskFirst_3 = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b0111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0011),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0010),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_4),(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_5)}}}}}}}; - assign _zz_b2m_fsm_cmd_maskFirst_4 = 4'b0001; - assign _zz_b2m_fsm_cmd_maskFirst_5 = 4'b0000; - EfxDMA_DmaMemoryCore_a048ca8f51874147a1cd65d43e6523ef memory_core ( - .io_writes_0_cmd_valid (s2b_0_cmd_sinkHalted_valid ), //i - .io_writes_0_cmd_ready (memory_core_io_writes_0_cmd_ready ), //o - .io_writes_0_cmd_payload_address (memory_core_io_writes_0_cmd_payload_address[9:0]), //i - .io_writes_0_cmd_payload_data (s2b_0_cmd_sinkHalted_payload_data[63:0] ), //i - .io_writes_0_cmd_payload_mask (s2b_0_cmd_sinkHalted_payload_mask[7:0] ), //i - .io_writes_0_cmd_payload_priority (channels_0_priority[1:0] ), //i - .io_writes_0_cmd_payload_context (memory_core_io_writes_0_cmd_payload_context[6:0]), //i - .io_writes_0_rsp_valid (memory_core_io_writes_0_rsp_valid ), //o - .io_writes_0_rsp_payload_context (memory_core_io_writes_0_rsp_payload_context[6:0]), //o - .io_writes_1_cmd_valid (io_read_rsp_valid ), //i - .io_writes_1_cmd_ready (memory_core_io_writes_1_cmd_ready ), //o - .io_writes_1_cmd_payload_address (memory_core_io_writes_1_cmd_payload_address[9:0]), //i - .io_writes_1_cmd_payload_data (io_read_rsp_payload_fragment_data[127:0] ), //i - .io_writes_1_cmd_payload_mask (memory_core_io_writes_1_cmd_payload_mask[15:0] ), //i - .io_writes_1_cmd_payload_context (memory_core_io_writes_1_cmd_payload_context[6:0]), //i - .io_writes_1_rsp_valid (memory_core_io_writes_1_rsp_valid ), //o - .io_writes_1_rsp_payload_context (memory_core_io_writes_1_rsp_payload_context[6:0]), //o - .io_reads_0_cmd_valid (memory_core_io_reads_0_cmd_valid ), //i - .io_reads_0_cmd_ready (memory_core_io_reads_0_cmd_ready ), //o - .io_reads_0_cmd_payload_address (memory_core_io_reads_0_cmd_payload_address[9:0] ), //i - .io_reads_0_cmd_payload_priority (channels_1_priority[1:0] ), //i - .io_reads_0_cmd_payload_context (memory_core_io_reads_0_cmd_payload_context[2:0] ), //i - .io_reads_0_rsp_valid (memory_core_io_reads_0_rsp_valid ), //o - .io_reads_0_rsp_ready (io_outputs_0_ready ), //i - .io_reads_0_rsp_payload_data (memory_core_io_reads_0_rsp_payload_data[63:0] ), //o - .io_reads_0_rsp_payload_mask (memory_core_io_reads_0_rsp_payload_mask[7:0] ), //o - .io_reads_0_rsp_payload_context (memory_core_io_reads_0_rsp_payload_context[2:0] ), //o - .io_reads_1_cmd_valid (b2m_fsm_sel_valid ), //i - .io_reads_1_cmd_ready (memory_core_io_reads_1_cmd_ready ), //o - .io_reads_1_cmd_payload_address (memory_core_io_reads_1_cmd_payload_address[9:0] ), //i - .io_reads_1_cmd_payload_context (memory_core_io_reads_1_cmd_payload_context[11:0]), //i - .io_reads_1_rsp_valid (memory_core_io_reads_1_rsp_valid ), //o - .io_reads_1_rsp_ready (memory_core_io_reads_1_rsp_rValidN ), //i - .io_reads_1_rsp_payload_data (memory_core_io_reads_1_rsp_payload_data[127:0] ), //o - .io_reads_1_rsp_payload_mask (memory_core_io_reads_1_rsp_payload_mask[15:0] ), //o - .io_reads_1_rsp_payload_context (memory_core_io_reads_1_rsp_payload_context[11:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_Aggregator_a048ca8f51874147a1cd65d43e6523ef b2m_fsm_aggregate_engine ( - .io_input_valid (b2m_fsm_aggregate_memoryPort_valid ), //i - .io_input_ready (b2m_fsm_aggregate_engine_io_input_ready ), //o - .io_input_payload_data (b2m_fsm_aggregate_memoryPort_payload_data[127:0] ), //i - .io_input_payload_mask (b2m_fsm_aggregate_engine_io_input_payload_mask[15:0]), //i - .io_output_data (b2m_fsm_aggregate_engine_io_output_data[127:0] ), //o - .io_output_mask (b2m_fsm_aggregate_engine_io_output_mask[15:0] ), //o - .io_output_enough (b2m_fsm_cmd_enoughAggregation ), //i - .io_output_consume (io_write_cmd_fire ), //i - .io_output_consumed (b2m_fsm_aggregate_engine_io_output_consumed ), //o - .io_output_lastByteUsed (b2m_fsm_cmd_maskLastTriggerReg[3:0] ), //i - .io_output_usedUntil (b2m_fsm_aggregate_engine_io_output_usedUntil[3:0] ), //o - .io_flush (b2m_fsm_aggregate_engine_io_flush ), //i - .io_offset (b2m_fsm_aggregate_engine_io_offset[3:0] ), //i - .io_burstLength (b2m_fsm_sel_bytesInBurst[11:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(_zz_s2b_0_cmd_byteCount_10) - 3'b000 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount; - 3'b001 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_1; - 3'b010 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_2; - 3'b011 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_3; - 3'b100 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_4; - 3'b101 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_5; - 3'b110 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_6; - default : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_7; - endcase - end - - always @(*) begin - case(_zz_s2b_0_cmd_byteCount_12) - 3'b000 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount; - 3'b001 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_1; - 3'b010 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_2; - 3'b011 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_3; - 3'b100 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_4; - 3'b101 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_5; - 3'b110 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_6; - default : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_7; - endcase - end - - always @(*) begin - case(_zz_s2b_0_cmd_byteCount_14) - 3'b000 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount; - 3'b001 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_1; - 3'b010 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_2; - 3'b011 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_3; - 3'b100 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_4; - 3'b101 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_5; - 3'b110 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_6; - default : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_7; - endcase - end - - always @(*) begin - case(_zz_m2b_cmd_s0_priority_masked) - 2'b00 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_0; - 2'b01 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_1; - 2'b10 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_2; - default : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_3; - endcase - end - - always @(*) begin - case(_zz_b2m_fsm_arbiter_logic_priority_masked) - 2'b00 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_0; - 2'b01 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_1; - 2'b10 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_2; - default : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_3; - endcase - end - - assign ctrl_readErrorFlag = 1'b0; - assign ctrl_writeErrorFlag = 1'b0; - assign io_ctrl_PREADY = 1'b1; - always @(*) begin - io_ctrl_PRDATA = 32'h0; - case(io_ctrl_PADDR) - 14'h002c : begin - io_ctrl_PRDATA[0 : 0] = channels_0_channelValid; - end - 14'h0054 : begin - io_ctrl_PRDATA[0 : 0] = channels_0_interrupts_completion_valid; - io_ctrl_PRDATA[2 : 2] = channels_0_interrupts_onChannelCompletion_valid; - io_ctrl_PRDATA[3 : 3] = channels_0_interrupts_onLinkedListUpdate_valid; - io_ctrl_PRDATA[4 : 4] = channels_0_interrupts_s2mPacket_valid; - end - 14'h0060 : begin - io_ctrl_PRDATA[26 : 0] = channels_0_bytesProbe_value; - end - 14'h00ac : begin - io_ctrl_PRDATA[0 : 0] = channels_1_channelValid; - end - 14'h00d4 : begin - io_ctrl_PRDATA[0 : 0] = channels_1_interrupts_completion_valid; - io_ctrl_PRDATA[2 : 2] = channels_1_interrupts_onChannelCompletion_valid; - io_ctrl_PRDATA[3 : 3] = channels_1_interrupts_onLinkedListUpdate_valid; - end - 14'h00e0 : begin - io_ctrl_PRDATA[26 : 0] = channels_1_bytesProbe_value; - end - default : begin - end - endcase - if(when_Apb3SlaveFactory_l81_1) begin - io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA[31 : 0]; - end - if(when_Apb3SlaveFactory_l81_3) begin - io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA_1[31 : 0]; - end - end - - assign ctrl_askWrite = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PWRITE); - assign ctrl_askRead = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && (! io_ctrl_PWRITE)); - assign ctrl_doWrite = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && io_ctrl_PWRITE); - assign ctrl_doRead = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && (! io_ctrl_PWRITE)); - assign io_ctrl_PSLVERROR = ((ctrl_doWrite && ctrl_writeErrorFlag) || (ctrl_doRead && ctrl_readErrorFlag)); - always @(*) begin - channels_0_channelStart = 1'b0; - if(when_BusSlaveFactory_l377) begin - if(when_BusSlaveFactory_l379) begin - channels_0_channelStart = _zz_channels_0_channelStart[0]; - end - end - if(when_BusSlaveFactory_l377_2) begin - if(when_BusSlaveFactory_l379_2) begin - channels_0_channelStart = _zz_channels_0_channelStart_1[0]; - end - end - end - - always @(*) begin - channels_0_channelCompletion = 1'b0; - if(channels_0_channelValid) begin - if(channels_0_channelStop) begin - if(channels_0_readyToStop) begin - channels_0_channelCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_0_descriptorStart = 1'b0; - if(channels_0_ctrl_kick) begin - channels_0_descriptorStart = 1'b1; - end - if(when_DmaSg_l318) begin - if(when_DmaSg_l320) begin - if(when_DmaSg_l322) begin - channels_0_descriptorStart = 1'b1; - end - end - end - end - - always @(*) begin - channels_0_descriptorCompletion = 1'b0; - if(channels_0_pop_b2m_packetSync) begin - if(when_DmaSg_l532) begin - if(channels_0_push_s2b_completionOnLast) begin - channels_0_descriptorCompletion = 1'b1; - end - end - end - if(when_DmaSg_l547) begin - channels_0_descriptorCompletion = 1'b1; - end - if(channels_0_channelValid) begin - if(channels_0_channelStop) begin - if(channels_0_readyToStop) begin - channels_0_descriptorCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_0_readyToStop = 1'b1; - if(channels_0_ll_waitDone) begin - channels_0_readyToStop = 1'b0; - end - if(when_DmaSg_l563) begin - channels_0_readyToStop = 1'b0; - end - end - - always @(*) begin - channels_0_bytesProbe_incr_valid = 1'b0; - if(io_write_rsp_fire) begin - if(when_DmaSg_l1116) begin - channels_0_bytesProbe_incr_valid = 1'b1; - end - end - end - - always @(*) begin - channels_0_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; - if(io_write_rsp_fire) begin - if(when_DmaSg_l1116) begin - channels_0_bytesProbe_incr_payload = b2m_rsp_context_length; - end - end - end - - always @(*) begin - channels_0_ll_sgStart = 1'b0; - if(when_BusSlaveFactory_l377_3) begin - if(when_BusSlaveFactory_l379_3) begin - channels_0_ll_sgStart = _zz_channels_0_ll_sgStart[0]; - end - end - end - - assign channels_0_ll_requestLl = ((((channels_0_channelValid && channels_0_ll_valid) && (! channels_0_channelStop)) && (! channels_0_ll_waitDone)) && ((! channels_0_descriptorValid) || channels_0_ll_requireSync)); - always @(*) begin - channels_0_ll_descriptorUpdated = 1'b0; - if(when_DmaSg_l318) begin - if(when_DmaSg_l328) begin - channels_0_ll_descriptorUpdated = 1'b1; - end - end - end - - assign when_DmaSg_l318 = (((channels_0_ll_valid && channels_0_ll_waitDone) && channels_0_ll_writeDone) && channels_0_ll_readDone); - assign when_DmaSg_l320 = (! channels_0_ll_justASync); - assign when_DmaSg_l322 = (! channels_0_ll_gotDescriptorStall); - assign when_DmaSg_l328 = (! channels_0_ll_head); - assign channels_0_fifo_base = 11'h0; - assign channels_0_fifo_words = 11'h1ff; - assign channels_0_fifo_push_availableDecr = 11'h0; - assign channels_0_fifo_push_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_push_ptr & channels_0_fifo_words)); - assign channels_0_fifo_pop_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_pop_ptr & channels_0_fifo_words)); - assign channels_0_fifo_pop_empty = (channels_0_fifo_pop_ptr == channels_0_fifo_push_ptr); - assign channels_0_fifo_pop_withOverride_backupNext = (_zz_channels_0_fifo_pop_withOverride_backupNext - channels_0_fifo_pop_bytesDecr_value); - always @(*) begin - channels_0_fifo_pop_withOverride_load = 1'b0; - if(when_DmaSg_l457) begin - channels_0_fifo_pop_withOverride_load = 1'b1; - end - end - - always @(*) begin - channels_0_fifo_pop_withOverride_unload = 1'b0; - if(channels_0_pop_b2m_packetSync) begin - channels_0_fifo_pop_withOverride_unload = 1'b1; - end - end - - assign when_DmaSg_l409 = (channels_0_channelStart || channels_0_fifo_pop_withOverride_unload); - assign channels_0_fifo_pop_bytes = channels_0_fifo_pop_withOverride_exposed; - assign channels_0_fifo_empty = (channels_0_fifo_push_ptr == channels_0_fifo_pop_ptr); - always @(*) begin - channels_0_push_s2b_packetEvent = 1'b0; - if(when_DmaSg_l679) begin - channels_0_push_s2b_packetEvent = 1'b1; - end - end - - assign when_DmaSg_l457 = (channels_0_push_s2b_packetEvent && channels_0_push_s2b_completionOnLast); - assign channels_0_pop_b2m_bytePerBurst = 12'h3ff; - always @(*) begin - channels_0_pop_b2m_fire = 1'b0; - if(when_DmaSg_l935) begin - if(_zz_when[0]) begin - channels_0_pop_b2m_fire = 1'b1; - end - end - end - - always @(*) begin - channels_0_pop_b2m_packetSync = 1'b0; - if(when_DmaSg_l523) begin - if(channels_0_pop_b2m_packet) begin - channels_0_pop_b2m_packetSync = 1'b1; - end - end - if(io_write_rsp_fire) begin - if(when_DmaSg_l1116) begin - if(b2m_rsp_context_doPacketSync) begin - channels_0_pop_b2m_packetSync = 1'b1; - end - end - end - end - - assign when_DmaSg_l505 = (channels_0_channelStart || channels_0_pop_b2m_fire); - always @(*) begin - channels_0_pop_b2m_memRsp = 1'b0; - if(io_write_rsp_fire) begin - if(_zz_when_2[0]) begin - channels_0_pop_b2m_memRsp = 1'b1; - end - end - end - - assign channels_0_pop_b2m_selfFlush = (channels_0_pop_b2m_bytesLeft < _zz_channels_0_pop_b2m_selfFlush); - assign channels_0_pop_b2m_request = ((((((channels_0_descriptorValid && (! channels_0_channelStop)) && (! channels_0_pop_b2m_waitFinalRsp)) && channels_0_pop_memory) && ((_zz_channels_0_pop_b2m_request < channels_0_fifo_pop_bytes) || (((channels_0_fifo_push_available < _zz_channels_0_pop_b2m_request_1) || channels_0_pop_b2m_flush) || channels_0_pop_b2m_selfFlush))) && (channels_0_fifo_pop_bytes != 14'h0)) && (channels_0_pop_b2m_memPending != 4'b1111)); - always @(*) begin - channels_0_pop_b2m_memPendingInc = 1'b0; - if(when_DmaSg_l758_1) begin - if(when_DmaSg_l773_1) begin - channels_0_pop_b2m_memPendingInc = 1'b1; - end - end - end - - always @(*) begin - channels_0_pop_b2m_decrBytes = 14'h0; - if(b2m_fsm_s1) begin - if(when_DmaSg_l996) begin - channels_0_pop_b2m_decrBytes = {1'd0, b2m_fsm_bytesInBurstP1}; - end - end - end - - assign when_DmaSg_l523 = ((channels_0_pop_b2m_memPending == 4'b0000) && (channels_0_fifo_pop_bytes == 14'h0)); - assign when_DmaSg_l532 = (channels_0_descriptorValid && (! channels_0_push_memory)); - assign when_DmaSg_l536 = (! channels_0_pop_b2m_waitFinalRsp); - assign when_DmaSg_l547 = ((channels_0_descriptorValid && (channels_0_pop_b2m_memPending == 4'b0000)) && channels_0_pop_b2m_waitFinalRsp); - assign when_DmaSg_l563 = (channels_0_pop_b2m_memPending != 4'b0000); - assign channels_0_readyForChannelCompletion = 1'b1; - assign when_DmaSg_l575 = (! channels_0_descriptorValid); - always @(*) begin - _zz_when_DmaSg_l593 = 1'b1; - if(channels_0_ctrl_kick) begin - _zz_when_DmaSg_l593 = 1'b0; - end - if(channels_0_ll_valid) begin - _zz_when_DmaSg_l593 = 1'b0; - end - end - - assign when_DmaSg_l593 = (_zz_when_DmaSg_l593 && channels_0_readyForChannelCompletion); - assign channels_0_s2b_full = (channels_0_fifo_push_available < 11'h002); - assign when_DmaSg_l255 = (channels_0_descriptorValid && channels_0_descriptorCompletion); - assign when_DmaSg_l255_1 = (! channels_0_interrupts_completion_enable); - assign when_DmaSg_l255_2 = (channels_0_channelValid && channels_0_channelCompletion); - assign when_DmaSg_l255_3 = (! channels_0_interrupts_onChannelCompletion_enable); - assign when_DmaSg_l255_4 = (! channels_0_interrupts_onLinkedListUpdate_enable); - assign when_DmaSg_l255_5 = (! channels_0_interrupts_s2mPacket_enable); - assign when_DmaSg_l625 = (channels_0_channelStart || channels_0_descriptorStart); - always @(*) begin - channels_1_channelStart = 1'b0; - if(when_BusSlaveFactory_l377_4) begin - if(when_BusSlaveFactory_l379_4) begin - channels_1_channelStart = _zz_channels_1_channelStart[0]; - end - end - if(when_BusSlaveFactory_l377_6) begin - if(when_BusSlaveFactory_l379_6) begin - channels_1_channelStart = _zz_channels_1_channelStart_1[0]; - end - end - end - - always @(*) begin - channels_1_channelCompletion = 1'b0; - if(channels_1_channelValid) begin - if(channels_1_channelStop) begin - if(channels_1_readyToStop) begin - channels_1_channelCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_1_descriptorStart = 1'b0; - if(channels_1_ctrl_kick) begin - channels_1_descriptorStart = 1'b1; - end - if(when_DmaSg_l318_1) begin - if(when_DmaSg_l320_1) begin - if(when_DmaSg_l322_1) begin - channels_1_descriptorStart = 1'b1; - end - end - end - end - - always @(*) begin - channels_1_descriptorCompletion = 1'b0; - if(when_DmaSg_l483) begin - channels_1_descriptorCompletion = 1'b1; - end - if(channels_1_channelValid) begin - if(channels_1_channelStop) begin - if(channels_1_readyToStop) begin - channels_1_descriptorCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_1_readyToStop = 1'b1; - if(channels_1_ll_waitDone) begin - channels_1_readyToStop = 1'b0; - end - if(when_DmaSg_l562) begin - channels_1_readyToStop = 1'b0; - end - end - - always @(*) begin - channels_1_bytesProbe_incr_valid = 1'b0; - if(when_DmaSg_l874) begin - channels_1_bytesProbe_incr_valid = 1'b1; - end - end - - always @(*) begin - channels_1_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; - if(when_DmaSg_l874) begin - channels_1_bytesProbe_incr_payload = m2b_rsp_context_length; - end - end - - always @(*) begin - channels_1_ll_sgStart = 1'b0; - if(when_BusSlaveFactory_l377_7) begin - if(when_BusSlaveFactory_l379_7) begin - channels_1_ll_sgStart = _zz_channels_1_ll_sgStart[0]; - end - end - end - - assign channels_1_ll_requestLl = ((((channels_1_channelValid && channels_1_ll_valid) && (! channels_1_channelStop)) && (! channels_1_ll_waitDone)) && ((! channels_1_descriptorValid) || channels_1_ll_requireSync)); - always @(*) begin - channels_1_ll_descriptorUpdated = 1'b0; - if(when_DmaSg_l318_1) begin - if(when_DmaSg_l328_1) begin - channels_1_ll_descriptorUpdated = 1'b1; - end - end - end - - assign when_DmaSg_l318_1 = (((channels_1_ll_valid && channels_1_ll_waitDone) && channels_1_ll_writeDone) && channels_1_ll_readDone); - assign when_DmaSg_l320_1 = (! channels_1_ll_justASync); - assign when_DmaSg_l322_1 = (! channels_1_ll_gotDescriptorStall); - assign when_DmaSg_l328_1 = (! channels_1_ll_head); - assign channels_1_fifo_base = 11'h200; - assign channels_1_fifo_words = 11'h1ff; - always @(*) begin - channels_1_fifo_push_availableDecr = 11'h0; - if(m2b_cmd_s1_valid) begin - if(io_read_cmd_ready) begin - if(when_DmaSg_l828) begin - channels_1_fifo_push_availableDecr = {1'd0, m2b_cmd_s1_fifoPushDecr}; - end - end - end - end - - assign channels_1_fifo_push_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_push_ptr & channels_1_fifo_words)); - assign channels_1_fifo_pop_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_pop_ptr & channels_1_fifo_words)); - assign channels_1_fifo_pop_empty = (channels_1_fifo_pop_ptr == channels_1_fifo_push_ptr); - assign channels_1_fifo_pop_bytes = channels_1_fifo_pop_withoutOverride_exposed; - assign channels_1_fifo_empty = (channels_1_fifo_push_ptr == channels_1_fifo_pop_ptr); - assign channels_1_push_m2b_bytePerBurst = 12'h3ff; - always @(*) begin - channels_1_push_m2b_memPendingIncr = 1'b0; - if(when_DmaSg_l758) begin - if(when_DmaSg_l773) begin - channels_1_push_m2b_memPendingIncr = 1'b1; - end - end - end - - always @(*) begin - channels_1_push_m2b_memPendingDecr = 1'b0; - if(when_DmaSg_l893) begin - channels_1_push_m2b_memPendingDecr = 1'b1; - end - end - - always @(*) begin - channels_1_push_m2b_loadRequest = (((((channels_1_descriptorValid && (! channels_1_channelStop)) && (! channels_1_push_m2b_loadDone)) && channels_1_push_memory) && (_zz_channels_1_push_m2b_loadRequest < channels_1_fifo_push_available)) && (channels_1_push_m2b_memPending != 4'b1111)); - if(when_DmaSg_l486) begin - channels_1_push_m2b_loadRequest = 1'b0; - end - end - - always @(*) begin - channels_1_pop_b2s_veryLastTrigger = 1'b0; - if(when_DmaSg_l847) begin - if(when_DmaSg_l848) begin - channels_1_pop_b2s_veryLastTrigger = 1'b1; - end - end - end - - assign when_DmaSg_l474 = (channels_1_pop_b2s_veryLastTrigger && channels_1_pop_b2s_last); - assign when_DmaSg_l483 = ((((channels_1_descriptorValid && (! channels_1_pop_memory)) && channels_1_push_memory) && channels_1_push_m2b_loadDone) && (channels_1_push_m2b_memPending == 4'b0000)); - assign when_DmaSg_l486 = (((! channels_1_pop_memory) && channels_1_pop_b2s_veryLastValid) && (channels_1_push_m2b_bytesLeft <= _zz_when_DmaSg_l486)); - assign when_DmaSg_l562 = (channels_1_push_m2b_memPending != 4'b0000); - always @(*) begin - channels_1_readyForChannelCompletion = 1'b1; - if(when_DmaSg_l566) begin - channels_1_readyForChannelCompletion = 1'b0; - end - end - - assign when_DmaSg_l566 = ((! channels_1_pop_memory) && (! channels_1_fifo_pop_empty)); - assign when_DmaSg_l575_1 = (! channels_1_descriptorValid); - always @(*) begin - _zz_when_DmaSg_l593_1 = 1'b1; - if(channels_1_ctrl_kick) begin - _zz_when_DmaSg_l593_1 = 1'b0; - end - if(channels_1_ll_valid) begin - _zz_when_DmaSg_l593_1 = 1'b0; - end - end - - assign when_DmaSg_l593_1 = (_zz_when_DmaSg_l593_1 && channels_1_readyForChannelCompletion); - assign channels_1_s2b_full = (channels_1_fifo_push_available < 11'h002); - assign when_DmaSg_l255_6 = (channels_1_descriptorValid && channels_1_descriptorCompletion); - assign when_DmaSg_l255_7 = (! channels_1_interrupts_completion_enable); - assign when_DmaSg_l255_8 = (channels_1_channelValid && channels_1_channelCompletion); - assign when_DmaSg_l255_9 = (! channels_1_interrupts_onChannelCompletion_enable); - assign when_DmaSg_l255_10 = (! channels_1_interrupts_onLinkedListUpdate_enable); - assign when_DmaSg_l625_1 = (channels_1_channelStart || channels_1_descriptorStart); - assign io_inputs_0_fire = (io_inputs_0_valid && io_inputs_0_ready); - assign when_package_l12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0000)); - assign when_package_l12_1 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0001)); - assign when_package_l12_2 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0010)); - assign when_package_l12_3 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0011)); - assign when_package_l12_4 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0100)); - assign when_package_l12_5 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0101)); - assign when_package_l12_6 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0110)); - assign when_package_l12_7 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0111)); - assign when_package_l12_8 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1000)); - assign when_package_l12_9 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1001)); - assign when_package_l12_10 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1010)); - assign when_package_l12_11 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1011)); - assign when_package_l12_12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1100)); - assign when_package_l12_13 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1101)); - assign when_package_l12_14 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1110)); - assign when_package_l12_15 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1111)); - assign s2b_0_cmd_firsts = {io_inputs_0_payload_last_regNextWhen_15,{io_inputs_0_payload_last_regNextWhen_14,{io_inputs_0_payload_last_regNextWhen_13,{io_inputs_0_payload_last_regNextWhen_12,{io_inputs_0_payload_last_regNextWhen_11,{io_inputs_0_payload_last_regNextWhen_10,{io_inputs_0_payload_last_regNextWhen_9,{io_inputs_0_payload_last_regNextWhen_8,{io_inputs_0_payload_last_regNextWhen_7,{io_inputs_0_payload_last_regNextWhen_6,{_zz_s2b_0_cmd_firsts,_zz_s2b_0_cmd_firsts_1}}}}}}}}}}}; - assign s2b_0_cmd_first = s2b_0_cmd_firsts[io_inputs_0_payload_sink]; - assign s2b_0_cmd_channelsOh = ((((channels_0_channelValid && (s2b_0_cmd_first || (! channels_0_push_s2b_waitFirst))) && (! channels_0_push_memory)) && 1'b1) && (io_inputs_0_payload_sink == 4'b0000)); - assign s2b_0_cmd_noHit = (! (|s2b_0_cmd_channelsOh)); - assign s2b_0_cmd_channelsFull = (channels_0_s2b_full || (channels_0_push_s2b_packetLock && io_inputs_0_payload_last)); - always @(*) begin - io_inputs_0_thrown_valid = io_inputs_0_valid; - if(s2b_0_cmd_noHit) begin - io_inputs_0_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_inputs_0_ready = io_inputs_0_thrown_ready; - if(s2b_0_cmd_noHit) begin - io_inputs_0_ready = 1'b1; - end - end - - assign io_inputs_0_thrown_payload_data = io_inputs_0_payload_data; - assign io_inputs_0_thrown_payload_mask = io_inputs_0_payload_mask; - assign io_inputs_0_thrown_payload_sink = io_inputs_0_payload_sink; - assign io_inputs_0_thrown_payload_last = io_inputs_0_payload_last; - assign _zz_io_inputs_0_thrown_ready = (! (|(s2b_0_cmd_channelsOh & s2b_0_cmd_channelsFull))); - assign s2b_0_cmd_sinkHalted_valid = (io_inputs_0_thrown_valid && _zz_io_inputs_0_thrown_ready); - assign io_inputs_0_thrown_ready = (s2b_0_cmd_sinkHalted_ready && _zz_io_inputs_0_thrown_ready); - assign s2b_0_cmd_sinkHalted_payload_data = io_inputs_0_thrown_payload_data; - assign s2b_0_cmd_sinkHalted_payload_mask = io_inputs_0_thrown_payload_mask; - assign s2b_0_cmd_sinkHalted_payload_sink = io_inputs_0_thrown_payload_sink; - assign s2b_0_cmd_sinkHalted_payload_last = io_inputs_0_thrown_payload_last; - assign _zz_s2b_0_cmd_byteCount = 4'b0000; - assign _zz_s2b_0_cmd_byteCount_1 = 4'b0001; - assign _zz_s2b_0_cmd_byteCount_2 = 4'b0001; - assign _zz_s2b_0_cmd_byteCount_3 = 4'b0010; - assign _zz_s2b_0_cmd_byteCount_4 = 4'b0001; - assign _zz_s2b_0_cmd_byteCount_5 = 4'b0010; - assign _zz_s2b_0_cmd_byteCount_6 = 4'b0010; - assign _zz_s2b_0_cmd_byteCount_7 = 4'b0011; - assign s2b_0_cmd_byteCount = (_zz_s2b_0_cmd_byteCount_8 + _zz_s2b_0_cmd_byteCount_13); - assign s2b_0_cmd_context_channel = s2b_0_cmd_channelsOh; - assign s2b_0_cmd_context_bytes = s2b_0_cmd_byteCount; - assign s2b_0_cmd_context_flush = io_inputs_0_payload_last; - assign s2b_0_cmd_context_packet = io_inputs_0_payload_last; - assign s2b_0_cmd_sinkHalted_ready = memory_core_io_writes_0_cmd_ready; - assign memory_core_io_writes_0_cmd_payload_address = channels_0_fifo_push_ptrWithBase[9:0]; - assign memory_core_io_writes_0_cmd_payload_context = {s2b_0_cmd_context_packet,{s2b_0_cmd_context_flush,{s2b_0_cmd_context_bytes,s2b_0_cmd_context_channel}}}; - assign memory_core_io_writes_0_cmd_fire = (s2b_0_cmd_sinkHalted_valid && memory_core_io_writes_0_cmd_ready); - assign when_DmaSg_l665 = (s2b_0_cmd_channelsOh[0] && memory_core_io_writes_0_cmd_fire); - assign _zz_s2b_0_rsp_context_channel = memory_core_io_writes_0_rsp_payload_context; - assign s2b_0_rsp_context_channel = _zz_s2b_0_rsp_context_channel[0 : 0]; - assign s2b_0_rsp_context_bytes = _zz_s2b_0_rsp_context_channel[4 : 1]; - assign s2b_0_rsp_context_flush = _zz_s2b_0_rsp_context_channel[5]; - assign s2b_0_rsp_context_packet = _zz_s2b_0_rsp_context_channel[6]; - assign _zz_channels_0_fifo_pop_bytesIncr_value = (memory_core_io_writes_0_rsp_valid && s2b_0_rsp_context_channel[0]); - assign when_DmaSg_l679 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); - assign when_DmaSg_l681 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_flush); - assign when_DmaSg_l682 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); - assign b2s_0_cmd_channelsOh = (((channels_1_channelValid && (! channels_1_pop_memory)) && 1'b1) && (! channels_1_fifo_pop_empty)); - assign b2s_0_cmd_veryLastPtr = channels_1_pop_b2s_veryLastPtr; - assign b2s_0_cmd_address = channels_1_fifo_pop_ptrWithBase; - assign b2s_0_cmd_context_channel = b2s_0_cmd_channelsOh; - assign b2s_0_cmd_context_veryLast = ((channels_1_pop_b2s_veryLastValid && (b2s_0_cmd_address[10 : 1] == b2s_0_cmd_veryLastPtr[10 : 1])) && (b2s_0_cmd_address[0 : 0] == 1'b1)); - assign b2s_0_cmd_context_endPacket = channels_1_pop_b2s_veryLastEndPacket; - assign memory_core_io_reads_0_cmd_valid = (|b2s_0_cmd_channelsOh); - assign memory_core_io_reads_0_cmd_payload_address = b2s_0_cmd_address[9:0]; - assign memory_core_io_reads_0_cmd_payload_context = {b2s_0_cmd_context_endPacket,{b2s_0_cmd_context_veryLast,b2s_0_cmd_context_channel}}; - assign _zz_b2s_0_rsp_context_channel = memory_core_io_reads_0_rsp_payload_context; - assign b2s_0_rsp_context_channel = _zz_b2s_0_rsp_context_channel[0 : 0]; - assign b2s_0_rsp_context_veryLast = _zz_b2s_0_rsp_context_channel[1]; - assign b2s_0_rsp_context_endPacket = _zz_b2s_0_rsp_context_channel[2]; - assign io_outputs_0_valid = memory_core_io_reads_0_rsp_valid; - assign io_outputs_0_payload_data = memory_core_io_reads_0_rsp_payload_data; - assign io_outputs_0_payload_mask = memory_core_io_reads_0_rsp_payload_mask; - assign io_outputs_0_payload_sink = channels_1_pop_b2s_sinkId; - assign io_outputs_0_payload_last = (b2s_0_rsp_context_veryLast && b2s_0_rsp_context_endPacket); - assign io_outputs_0_fire = (io_outputs_0_valid && io_outputs_0_ready); - assign when_DmaSg_l725 = (io_outputs_0_fire && b2s_0_rsp_context_veryLast); - assign when_DmaSg_l726 = b2s_0_rsp_context_channel[0]; - assign _zz_m2b_cmd_s0_priority_masked = channels_1_priority; - assign m2b_cmd_s0_priority_masked = (channels_1_push_m2b_loadRequest && (channels_1_priority == _zz_m2b_cmd_s0_priority_masked)); - assign _zz_m2b_cmd_s0_priority_chosenOh = m2b_cmd_s0_priority_masked; - assign _zz_m2b_cmd_s0_priority_chosenOh_1 = {_zz_m2b_cmd_s0_priority_chosenOh,_zz_m2b_cmd_s0_priority_chosenOh}; - assign _zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 & (~ _zz__zz_m2b_cmd_s0_priority_chosenOh_2)); - assign m2b_cmd_s0_priority_chosenOh = (_zz_m2b_cmd_s0_priority_chosenOh_2[1 : 1] | _zz_m2b_cmd_s0_priority_chosenOh_2[0 : 0]); - assign m2b_cmd_s0_priority_weightLast = (channels_1_weight == m2b_cmd_s0_priority_counter); - assign m2b_cmd_s0_priority_contextNext = (m2b_cmd_s0_priority_weightLast ? m2b_cmd_s0_priority_chosenOh[0 : 0] : m2b_cmd_s0_priority_chosenOh); - assign when_DmaSg_l758 = (! m2b_cmd_s0_valid); - assign when_DmaSg_l760 = (|channels_1_push_m2b_loadRequest); - assign when_DmaSg_l763 = (2'b00 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l763_1 = (2'b01 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l763_2 = (2'b10 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l763_3 = (2'b11 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l773 = (channels_1_push_m2b_loadRequest && m2b_cmd_s0_priority_chosenOh[0]); - assign m2b_cmd_s0_address = channels_1_push_m2b_address; - assign m2b_cmd_s0_bytesLeft = channels_1_push_m2b_bytesLeft; - assign m2b_cmd_s0_readAddressBurstRange = m2b_cmd_s0_address[11 : 0]; - assign m2b_cmd_s0_lengthHead = ((~ m2b_cmd_s0_readAddressBurstRange) & channels_1_push_m2b_bytePerBurst); - assign m2b_cmd_s0_length = _zz_m2b_cmd_s0_length[11:0]; - assign m2b_cmd_s0_lastBurst = (m2b_cmd_s0_bytesLeft == _zz_m2b_cmd_s0_lastBurst); - assign m2b_cmd_s1_context_start = m2b_cmd_s1_address[3:0]; - assign m2b_cmd_s1_context_stop = _zz_m2b_cmd_s1_context_stop[3:0]; - assign m2b_cmd_s1_context_last = m2b_cmd_s1_lastBurst; - assign m2b_cmd_s1_context_length = m2b_cmd_s1_length; - always @(*) begin - io_read_cmd_valid = 1'b0; - if(m2b_cmd_s1_valid) begin - io_read_cmd_valid = 1'b1; - end - end - - assign io_read_cmd_payload_last = 1'b1; - assign io_read_cmd_payload_fragment_opcode = 1'b0; - assign io_read_cmd_payload_fragment_address = m2b_cmd_s1_address; - assign io_read_cmd_payload_fragment_length = m2b_cmd_s1_length; - assign io_read_cmd_payload_fragment_context = {m2b_cmd_s1_context_last,{m2b_cmd_s1_context_length,{m2b_cmd_s1_context_stop,m2b_cmd_s1_context_start}}}; - assign m2b_cmd_s1_addressNext = (_zz_m2b_cmd_s1_addressNext + 32'h00000001); - assign m2b_cmd_s1_byteLeftNext = (_zz_m2b_cmd_s1_byteLeftNext - 26'h0000001); - assign m2b_cmd_s1_fifoPushDecr = (_zz_m2b_cmd_s1_fifoPushDecr >>> 2'd3); - assign when_DmaSg_l828 = 1'b1; - assign _zz_m2b_rsp_context_start = io_read_rsp_payload_fragment_context; - assign m2b_rsp_context_start = _zz_m2b_rsp_context_start[3 : 0]; - assign m2b_rsp_context_stop = _zz_m2b_rsp_context_start[7 : 4]; - assign m2b_rsp_context_length = _zz_m2b_rsp_context_start[19 : 8]; - assign m2b_rsp_context_last = _zz_m2b_rsp_context_start[20]; - assign m2b_rsp_veryLast = (m2b_rsp_context_last && io_read_rsp_payload_last); - assign io_read_rsp_fire = (io_read_rsp_valid && io_read_rsp_ready); - assign when_DmaSg_l847 = (io_read_rsp_fire && m2b_rsp_veryLast); - assign when_DmaSg_l848 = 1'b1; - always @(*) begin - memory_core_io_writes_1_cmd_payload_mask[0] = ((! (m2b_rsp_first && (4'b0000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0000)))); - memory_core_io_writes_1_cmd_payload_mask[1] = ((! (m2b_rsp_first && (4'b0001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0001)))); - memory_core_io_writes_1_cmd_payload_mask[2] = ((! (m2b_rsp_first && (4'b0010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0010)))); - memory_core_io_writes_1_cmd_payload_mask[3] = ((! (m2b_rsp_first && (4'b0011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0011)))); - memory_core_io_writes_1_cmd_payload_mask[4] = ((! (m2b_rsp_first && (4'b0100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0100)))); - memory_core_io_writes_1_cmd_payload_mask[5] = ((! (m2b_rsp_first && (4'b0101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0101)))); - memory_core_io_writes_1_cmd_payload_mask[6] = ((! (m2b_rsp_first && (4'b0110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0110)))); - memory_core_io_writes_1_cmd_payload_mask[7] = ((! (m2b_rsp_first && (4'b0111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0111)))); - memory_core_io_writes_1_cmd_payload_mask[8] = ((! (m2b_rsp_first && (4'b1000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1000)))); - memory_core_io_writes_1_cmd_payload_mask[9] = ((! (m2b_rsp_first && (4'b1001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1001)))); - memory_core_io_writes_1_cmd_payload_mask[10] = ((! (m2b_rsp_first && (4'b1010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1010)))); - memory_core_io_writes_1_cmd_payload_mask[11] = ((! (m2b_rsp_first && (4'b1011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1011)))); - memory_core_io_writes_1_cmd_payload_mask[12] = ((! (m2b_rsp_first && (4'b1100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1100)))); - memory_core_io_writes_1_cmd_payload_mask[13] = ((! (m2b_rsp_first && (4'b1101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1101)))); - memory_core_io_writes_1_cmd_payload_mask[14] = ((! (m2b_rsp_first && (4'b1110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1110)))); - memory_core_io_writes_1_cmd_payload_mask[15] = ((! (m2b_rsp_first && (4'b1111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1111)))); - end - - assign m2b_rsp_writeContext_last = m2b_rsp_veryLast; - assign m2b_rsp_writeContext_lastOfBurst = io_read_rsp_payload_last; - assign m2b_rsp_writeContext_loadByteInNextBeat = ({1'b0,(io_read_rsp_payload_last ? m2b_rsp_context_stop : 4'b1111)} - {1'b0,(m2b_rsp_first ? m2b_rsp_context_start : 4'b0000)}); - assign memory_core_io_writes_1_cmd_payload_address = channels_1_fifo_push_ptrWithBase[9:0]; - assign io_read_rsp_ready = memory_core_io_writes_1_cmd_ready; - assign memory_core_io_writes_1_cmd_payload_context = {m2b_rsp_writeContext_loadByteInNextBeat,{m2b_rsp_writeContext_lastOfBurst,m2b_rsp_writeContext_last}}; - assign memory_core_io_writes_1_cmd_fire = (io_read_rsp_valid && memory_core_io_writes_1_cmd_ready); - assign _zz_channels_1_fifo_push_ptrIncr_value = (memory_core_io_writes_1_cmd_fire && 1'b1); - assign when_DmaSg_l874 = (_zz_channels_1_fifo_push_ptrIncr_value && io_read_rsp_payload_last); - assign _zz_m2b_writeRsp_context_last = memory_core_io_writes_1_rsp_payload_context; - assign m2b_writeRsp_context_last = _zz_m2b_writeRsp_context_last[0]; - assign m2b_writeRsp_context_lastOfBurst = _zz_m2b_writeRsp_context_last[1]; - assign m2b_writeRsp_context_loadByteInNextBeat = _zz_m2b_writeRsp_context_last[6 : 2]; - assign _zz_channels_1_fifo_pop_bytesIncr_value = (memory_core_io_writes_1_rsp_valid && 1'b1); - assign when_DmaSg_l893 = (_zz_channels_1_fifo_pop_bytesIncr_value && m2b_writeRsp_context_lastOfBurst); - assign _zz_b2m_fsm_arbiter_logic_priority_masked = channels_0_priority; - assign b2m_fsm_arbiter_logic_priority_masked = (channels_0_pop_b2m_request && (channels_0_priority == _zz_b2m_fsm_arbiter_logic_priority_masked)); - assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh = b2m_fsm_arbiter_logic_priority_masked; - assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 = {_zz_b2m_fsm_arbiter_logic_priority_chosenOh,_zz_b2m_fsm_arbiter_logic_priority_chosenOh}; - assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 & (~ _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2)); - assign b2m_fsm_arbiter_logic_priority_chosenOh = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[1 : 1] | _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[0 : 0]); - assign b2m_fsm_arbiter_logic_priority_weightLast = (channels_0_weight == b2m_fsm_arbiter_logic_priority_counter); - assign b2m_fsm_arbiter_logic_priority_contextNext = (b2m_fsm_arbiter_logic_priority_weightLast ? b2m_fsm_arbiter_logic_priority_chosenOh[0 : 0] : b2m_fsm_arbiter_logic_priority_chosenOh); - assign when_DmaSg_l758_1 = (! b2m_fsm_arbiter_logic_valid); - assign when_DmaSg_l760_1 = (|channels_0_pop_b2m_request); - assign when_DmaSg_l763_4 = (2'b00 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l763_5 = (2'b01 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l763_6 = (2'b10 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l763_7 = (2'b11 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l773_1 = (channels_0_pop_b2m_request && b2m_fsm_arbiter_logic_priority_chosenOh[0]); - assign when_DmaSg_l935 = ((! b2m_fsm_sel_valid) && b2m_fsm_arbiter_logic_valid); - assign b2m_fsm_bytesInBurstP1 = ({1'b0,b2m_fsm_sel_bytesInBurst} + _zz_b2m_fsm_bytesInBurstP1); - assign b2m_fsm_addressNext = (b2m_fsm_sel_address + _zz_b2m_fsm_addressNext); - assign b2m_fsm_bytesLeftNext = ({1'b0,b2m_fsm_sel_bytesLeft} - _zz_b2m_fsm_bytesLeftNext); - assign b2m_fsm_isFinalCmd = b2m_fsm_bytesLeftNext[26]; - assign b2m_fsm_s0 = (b2m_fsm_sel_valid && (! b2m_fsm_sel_valid_regNext)); - assign when_DmaSg_l986 = (! b2m_fsm_sel_valid); - assign _zz_b2m_fsm_sel_bytesInBurst = (b2m_fsm_sel_bytesInFifo - 14'h0001); - assign _zz_b2m_fsm_sel_bytesInBurst_1 = ((_zz__zz_b2m_fsm_sel_bytesInBurst_1 < b2m_fsm_sel_bytesLeft) ? _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 : b2m_fsm_sel_bytesLeft); - assign _zz_b2m_fsm_sel_bytesInBurst_2 = (b2m_fsm_sel_bytePerBurst - (_zz__zz_b2m_fsm_sel_bytesInBurst_2 & b2m_fsm_sel_bytePerBurst)); - assign b2m_fsm_fifoCompletion = (_zz_b2m_fsm_fifoCompletion == _zz_b2m_fsm_fifoCompletion_1); - assign when_DmaSg_l996 = 1'b1; - assign when_DmaSg_l1001 = (! b2m_fsm_fifoCompletion); - assign when_DmaSg_l1013 = (b2m_fsm_sel_valid && b2m_fsm_sel_ready); - always @(*) begin - b2m_fsm_sel_ready = 1'b0; - if(when_DmaSg_l1102) begin - b2m_fsm_sel_ready = 1'b1; - end - end - - assign b2m_fsm_fetch_context_ptr = channels_0_fifo_pop_ptr; - assign b2m_fsm_fetch_context_toggle = b2m_fsm_toggle; - assign memory_core_io_reads_1_cmd_payload_address = b2m_fsm_sel_ptr[9:0]; - assign memory_core_io_reads_1_cmd_payload_context = {b2m_fsm_fetch_context_toggle,b2m_fsm_fetch_context_ptr}; - assign when_DmaSg_l1033 = (b2m_fsm_sel_valid && memory_core_io_reads_1_cmd_ready); - assign _zz_b2m_fsm_aggregate_context_ptr = memory_core_io_reads_1_rsp_payload_context; - assign b2m_fsm_aggregate_context_ptr = _zz_b2m_fsm_aggregate_context_ptr[10 : 0]; - assign b2m_fsm_aggregate_context_toggle = _zz_b2m_fsm_aggregate_context_ptr[11]; - assign memory_core_io_reads_1_rsp_s2mPipe_valid = (memory_core_io_reads_1_rsp_valid || (! memory_core_io_reads_1_rsp_rValidN)); - assign memory_core_io_reads_1_rsp_s2mPipe_payload_data = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_data : memory_core_io_reads_1_rsp_rData_data); - assign memory_core_io_reads_1_rsp_s2mPipe_payload_mask = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_mask : memory_core_io_reads_1_rsp_rData_mask); - assign memory_core_io_reads_1_rsp_s2mPipe_payload_context = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_context : memory_core_io_reads_1_rsp_rData_context); - assign when_Stream_l445 = (b2m_fsm_aggregate_context_toggle != b2m_fsm_toggle); - always @(*) begin - b2m_fsm_aggregate_memoryPort_valid = memory_core_io_reads_1_rsp_s2mPipe_valid; - if(when_Stream_l445) begin - b2m_fsm_aggregate_memoryPort_valid = 1'b0; - end - end - - always @(*) begin - memory_core_io_reads_1_rsp_s2mPipe_ready = b2m_fsm_aggregate_memoryPort_ready; - if(when_Stream_l445) begin - memory_core_io_reads_1_rsp_s2mPipe_ready = 1'b1; - end - end - - assign b2m_fsm_aggregate_memoryPort_payload_data = memory_core_io_reads_1_rsp_s2mPipe_payload_data; - assign b2m_fsm_aggregate_memoryPort_payload_mask = memory_core_io_reads_1_rsp_s2mPipe_payload_mask; - assign b2m_fsm_aggregate_memoryPort_payload_context = memory_core_io_reads_1_rsp_s2mPipe_payload_context; - assign b2m_fsm_aggregate_memoryPort_fire = (b2m_fsm_aggregate_memoryPort_valid && b2m_fsm_aggregate_memoryPort_ready); - assign when_DmaSg_l1050 = (! (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready))); - assign b2m_fsm_aggregate_bytesToSkip = channels_0_pop_b2m_bytesToSkip; - assign b2m_fsm_aggregate_bytesToSkipMask = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1111)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1110)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_1 || _zz_b2m_fsm_aggregate_bytesToSkipMask_2),{_zz_b2m_fsm_aggregate_bytesToSkipMask_3,{_zz_b2m_fsm_aggregate_bytesToSkipMask_4,_zz_b2m_fsm_aggregate_bytesToSkipMask_5}}}}}}; - assign b2m_fsm_aggregate_memoryPort_ready = b2m_fsm_aggregate_engine_io_input_ready; - assign b2m_fsm_aggregate_engine_io_input_payload_mask = (b2m_fsm_aggregate_memoryPort_payload_mask & b2m_fsm_aggregate_bytesToSkipMask); - assign b2m_fsm_aggregate_engine_io_offset = b2m_fsm_sel_address[3:0]; - assign b2m_fsm_aggregate_engine_io_flush = (! _zz_io_flush); - assign b2m_fsm_cmd_maskFirstTrigger = b2m_fsm_sel_address[3:0]; - assign b2m_fsm_cmd_maskLastTriggerComb = (b2m_fsm_cmd_maskFirstTrigger + _zz_b2m_fsm_cmd_maskLastTriggerComb); - assign b2m_fsm_cmd_maskFirst = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b1111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1011),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst),{_zz_b2m_fsm_cmd_maskFirst_1,{_zz_b2m_fsm_cmd_maskFirst_2,_zz_b2m_fsm_cmd_maskFirst_3}}}}}}}}; - assign b2m_fsm_cmd_enoughAggregation = (((b2m_fsm_s2 && b2m_fsm_sel_valid) && (! b2m_fsm_aggregate_engine_io_flush)) && (io_write_cmd_payload_last ? ((b2m_fsm_aggregate_engine_io_output_mask & b2m_fsm_cmd_maskLast) == b2m_fsm_cmd_maskLast) : (&b2m_fsm_aggregate_engine_io_output_mask))); - assign io_write_cmd_fire = (io_write_cmd_valid && io_write_cmd_ready); - assign io_write_cmd_valid = b2m_fsm_cmd_enoughAggregation; - assign io_write_cmd_payload_last = (b2m_fsm_beatCounter == 8'h0); - assign io_write_cmd_payload_fragment_address = b2m_fsm_sel_address; - assign io_write_cmd_payload_fragment_opcode = 1'b1; - assign io_write_cmd_payload_fragment_data = b2m_fsm_aggregate_engine_io_output_data; - assign io_write_cmd_payload_fragment_mask = (~ ((io_write_cmd_payload_first ? (~ b2m_fsm_cmd_maskFirst) : 16'h0) | (io_write_cmd_payload_last ? (~ b2m_fsm_cmd_maskLast) : 16'h0))); - assign io_write_cmd_payload_fragment_length = b2m_fsm_sel_bytesInBurst; - assign b2m_fsm_cmd_doPtrIncr = (b2m_fsm_sel_valid && (b2m_fsm_aggregate_engine_io_output_consumed || ((io_write_cmd_fire && io_write_cmd_payload_last) && (b2m_fsm_aggregate_engine_io_output_usedUntil == 4'b1111)))); - assign b2m_fsm_cmd_context_length = b2m_fsm_sel_bytesInBurst; - assign b2m_fsm_cmd_context_doPacketSync = (b2m_fsm_sel_packet && b2m_fsm_fifoCompletion); - assign io_write_cmd_payload_fragment_context = {b2m_fsm_cmd_context_doPacketSync,b2m_fsm_cmd_context_length}; - assign when_DmaSg_l1102 = (io_write_cmd_fire && io_write_cmd_payload_last); - assign io_write_rsp_ready = 1'b1; - assign _zz_b2m_rsp_context_length = io_write_rsp_payload_fragment_context; - assign b2m_rsp_context_length = _zz_b2m_rsp_context_length[11 : 0]; - assign b2m_rsp_context_doPacketSync = _zz_b2m_rsp_context_length[12]; - assign io_write_rsp_fire = (io_write_rsp_valid && io_write_rsp_ready); - assign when_DmaSg_l1116 = 1'b1; - assign _zz_ll_arbiter_head = {channels_1_ll_requestLl,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_head_1 = _zz__zz_ll_arbiter_head_1[1]; - assign ll_arbiter_head = (_zz_ll_arbiter_head_2[0] ? channels_0_ll_head : channels_1_ll_head); - assign ll_arbiter_isJustASink = (_zz_ll_arbiter_isJustASink[0] ? channels_0_descriptorValid : channels_1_descriptorValid); - assign ll_arbiter_doDescriptorStall = (_zz_ll_arbiter_doDescriptorStall[0] ? ((! channels_0_ll_controlNoCompletion) || channels_0_ll_gotDescriptorStall) : ((! channels_1_ll_controlNoCompletion) || channels_1_ll_gotDescriptorStall)); - assign ll_arbiter_onSgStream = (_zz_ll_arbiter_onSgStream[0] ? channels_0_ll_onSgStream : channels_1_ll_onSgStream); - assign when_DmaSg_l1149 = (! ll_cmd_valid); - assign when_DmaSg_l1148 = (! ll_cmd_valid); - assign when_DmaSg_l1148_1 = (! ll_cmd_valid); - assign when_DmaSg_l1148_2 = (! ll_cmd_valid); - assign when_DmaSg_l1148_3 = (! ll_cmd_valid); - assign when_DmaSg_l1154 = (! ll_cmd_valid); - assign when_DmaSg_l1155 = (! ll_cmd_valid); - assign when_DmaSg_l1156 = (! ll_cmd_valid); - assign when_DmaSg_l1160 = (! ll_cmd_valid); - assign when_DmaSg_l1161 = (|{_zz_ll_arbiter_head_1,channels_0_ll_requestLl}); - assign when_DmaSg_l1169 = (! ll_arbiter_isJustASink); - assign when_DmaSg_l1169_1 = (! ll_arbiter_isJustASink); - assign when_DmaSg_l1177 = (ll_cmd_writeFired && ll_cmd_readFired); - assign ll_cmd_context_channel = ll_cmd_oh_1; - assign io_sgRead_cmd_valid = ((ll_cmd_valid && (! ll_cmd_readFired)) && (! ll_cmd_onSgStream)); - assign io_sgRead_cmd_payload_last = 1'b1; - assign io_sgRead_cmd_payload_fragment_address = {ll_cmd_ptrNext[31 : 5],5'h0}; - assign io_sgRead_cmd_payload_fragment_length = 5'h1f; - assign io_sgRead_cmd_payload_fragment_opcode = 1'b0; - assign io_sgRead_cmd_payload_fragment_context = ll_cmd_context_channel; - assign io_sgWrite_cmd_valid = ((ll_cmd_valid && (! ll_cmd_writeFired)) && (! ll_cmd_onSgStream)); - assign io_sgWrite_cmd_payload_last = 1'b1; - assign io_sgWrite_cmd_payload_fragment_address = {ll_cmd_ptr[31 : 5],5'h0}; - assign io_sgWrite_cmd_payload_fragment_length = 2'b11; - assign io_sgWrite_cmd_payload_fragment_opcode = 1'b1; - assign io_sgWrite_cmd_payload_fragment_context = ll_cmd_context_channel; - assign ll_cmd_writeMaskSplit_0 = io_sgWrite_cmd_payload_fragment_mask[3 : 0]; - assign ll_cmd_writeMaskSplit_1 = io_sgWrite_cmd_payload_fragment_mask[7 : 4]; - assign ll_cmd_writeMaskSplit_2 = io_sgWrite_cmd_payload_fragment_mask[11 : 8]; - assign ll_cmd_writeMaskSplit_3 = io_sgWrite_cmd_payload_fragment_mask[15 : 12]; - assign ll_cmd_writeDataSplit_0 = io_sgWrite_cmd_payload_fragment_data[31 : 0]; - assign ll_cmd_writeDataSplit_1 = io_sgWrite_cmd_payload_fragment_data[63 : 32]; - assign ll_cmd_writeDataSplit_2 = io_sgWrite_cmd_payload_fragment_data[95 : 64]; - assign ll_cmd_writeDataSplit_3 = io_sgWrite_cmd_payload_fragment_data[127 : 96]; - assign _zz_1 = zz_io_sgWrite_cmd_payload_fragment_mask(1'b0); - always @(*) io_sgWrite_cmd_payload_fragment_mask = _zz_1; - always @(*) begin - io_sgWrite_cmd_payload_fragment_data[63 : 32] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - io_sgWrite_cmd_payload_fragment_data[95 : 64] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - io_sgWrite_cmd_payload_fragment_data[127 : 96] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - io_sgWrite_cmd_payload_fragment_data[31 : 0] = 32'h0; - io_sgWrite_cmd_payload_fragment_data[26 : 0] = ll_cmd_bytesDone; - io_sgWrite_cmd_payload_fragment_data[30] = ll_cmd_endOfPacket; - io_sgWrite_cmd_payload_fragment_data[31] = ((! ll_cmd_isJustASink) && ll_cmd_doDescriptorStall); - end - - assign io_sgRead_cmd_fire = (io_sgRead_cmd_valid && io_sgRead_cmd_ready); - assign io_sgWrite_cmd_fire = (io_sgWrite_cmd_valid && io_sgWrite_cmd_ready); - assign ll_readRsp_context_channel = io_sgRead_rsp_payload_fragment_context[0 : 0]; - assign _zz_ll_readRsp_oh_0 = (2'b01 <<< ll_readRsp_context_channel); - assign ll_readRsp_oh_0 = _zz_ll_readRsp_oh_0[0]; - assign ll_readRsp_oh_1 = _zz_ll_readRsp_oh_0[1]; - assign io_sgRead_rsp_ready = 1'b1; - assign io_sgRead_rsp_fire = (io_sgRead_rsp_valid && io_sgRead_rsp_ready); - assign when_DmaSg_l1248 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_1 = (1'b1 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_2 = (1'b1 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_3 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_4 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_5 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_6 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1271 = (io_sgRead_rsp_fire && io_sgRead_rsp_payload_last); - assign ll_writeRsp_context_channel = io_sgWrite_rsp_payload_fragment_context[0 : 0]; - assign _zz_ll_writeRsp_oh_0 = (2'b01 <<< ll_writeRsp_context_channel); - assign ll_writeRsp_oh_0 = _zz_ll_writeRsp_oh_0[0]; - assign ll_writeRsp_oh_1 = _zz_ll_writeRsp_oh_0[1]; - assign io_sgWrite_rsp_ready = 1'b1; - assign io_sgWrite_rsp_fire = (io_sgWrite_rsp_valid && io_sgWrite_rsp_ready); - always @(*) begin - io_interrupts = 2'b00; - if(channels_0_interrupts_completion_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_0_interrupts_onChannelCompletion_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_0_interrupts_onLinkedListUpdate_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_0_interrupts_s2mPacket_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_1_interrupts_completion_valid) begin - io_interrupts[1] = 1'b1; - end - if(channels_1_interrupts_onChannelCompletion_valid) begin - io_interrupts[1] = 1'b1; - end - if(channels_1_interrupts_onLinkedListUpdate_valid) begin - io_interrupts[1] = 1'b1; - end - end - - always @(*) begin - when_BusSlaveFactory_l377 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_1 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_1 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_2 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_2 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l377_3 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_3 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l341 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l341_1 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_1 = io_ctrl_PWDATA[2]; - always @(*) begin - when_BusSlaveFactory_l341_2 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_2 = io_ctrl_PWDATA[3]; - always @(*) begin - when_BusSlaveFactory_l341_3 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_3 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l377_4 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_4 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_4 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_5 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_5 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_5 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_6 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_6 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_6 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l377_7 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_7 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_7 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l341_4 = 1'b0; - case(io_ctrl_PADDR) - 14'h00d4 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_4 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_4 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l341_5 = 1'b0; - case(io_ctrl_PADDR) - 14'h00d4 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_5 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_5 = io_ctrl_PWDATA[2]; - always @(*) begin - when_BusSlaveFactory_l341_6 = 1'b0; - case(io_ctrl_PADDR) - 14'h00d4 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_6 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_6 = io_ctrl_PWDATA[3]; - assign when_Apb3SlaveFactory_l81 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0010); - assign when_Apb3SlaveFactory_l81_1 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0070); - assign when_Apb3SlaveFactory_l81_2 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0080); - assign when_Apb3SlaveFactory_l81_3 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h00f0); - assign channels_0_fifo_push_ptrIncr_value = _zz_channels_0_fifo_push_ptrIncr_value; - assign channels_0_fifo_pop_bytesIncr_value = _zz_channels_0_fifo_pop_bytesIncr_value_1; - assign channels_0_fifo_pop_bytesDecr_value = channels_0_pop_b2m_decrBytes; - assign channels_0_fifo_pop_ptrIncr_value = _zz_channels_0_fifo_pop_ptrIncr_value; - assign channels_1_fifo_push_ptrIncr_value = _zz_channels_1_fifo_push_ptrIncr_value_1; - assign channels_1_fifo_pop_bytesIncr_value = _zz_channels_1_fifo_pop_bytesIncr_value_1; - assign channels_1_fifo_pop_bytesDecr_value = 14'h0; - assign channels_1_fifo_pop_ptrIncr_value = _zz_channels_1_fifo_pop_ptrIncr_value; - assign ll_0_descriptorUpdate = (channels_0_ll_descriptorUpdated && (! channels_0_ll_gotDescriptorStall)); - assign ll_1_descriptorUpdate = (channels_1_ll_descriptorUpdated && (! channels_1_ll_gotDescriptorStall)); - always @(posedge clk) begin - if(reset) begin - channels_0_channelValid <= 1'b0; - channels_0_descriptorValid <= 1'b0; - channels_0_priority <= 2'b00; - channels_0_weight <= 2'b00; - channels_0_ctrl_kick <= 1'b0; - channels_0_ll_valid <= 1'b0; - channels_0_ll_onSgStream <= 1'b0; - channels_0_pop_b2m_memPending <= 4'b0000; - channels_0_interrupts_completion_enable <= 1'b0; - channels_0_interrupts_completion_valid <= 1'b0; - channels_0_interrupts_onChannelCompletion_enable <= 1'b0; - channels_0_interrupts_onChannelCompletion_valid <= 1'b0; - channels_0_interrupts_onLinkedListUpdate_enable <= 1'b0; - channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; - channels_0_interrupts_s2mPacket_enable <= 1'b0; - channels_0_interrupts_s2mPacket_valid <= 1'b0; - channels_1_channelValid <= 1'b0; - channels_1_descriptorValid <= 1'b0; - channels_1_priority <= 2'b00; - channels_1_weight <= 2'b00; - channels_1_ctrl_kick <= 1'b0; - channels_1_ll_valid <= 1'b0; - channels_1_ll_onSgStream <= 1'b0; - channels_1_push_m2b_loadDone <= 1'b1; - channels_1_push_m2b_memPending <= 4'b0000; - channels_1_interrupts_completion_enable <= 1'b0; - channels_1_interrupts_completion_valid <= 1'b0; - channels_1_interrupts_onChannelCompletion_enable <= 1'b0; - channels_1_interrupts_onChannelCompletion_valid <= 1'b0; - channels_1_interrupts_onLinkedListUpdate_enable <= 1'b0; - channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; - io_inputs_0_payload_last_regNextWhen <= 1'b1; - io_inputs_0_payload_last_regNextWhen_1 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_2 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_3 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_4 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_5 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_6 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_7 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_8 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_9 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_10 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_11 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_12 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_13 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_14 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_15 <= 1'b1; - m2b_cmd_s0_valid <= 1'b0; - m2b_cmd_s0_priority_roundRobins_0 <= 1'b1; - m2b_cmd_s0_priority_roundRobins_1 <= 1'b1; - m2b_cmd_s0_priority_roundRobins_2 <= 1'b1; - m2b_cmd_s0_priority_roundRobins_3 <= 1'b1; - m2b_cmd_s0_priority_counter <= 2'b00; - m2b_cmd_s1_valid <= 1'b0; - m2b_rsp_first <= 1'b1; - b2m_fsm_sel_valid <= 1'b0; - b2m_fsm_arbiter_logic_valid <= 1'b0; - b2m_fsm_arbiter_logic_priority_roundRobins_0 <= 1'b1; - b2m_fsm_arbiter_logic_priority_roundRobins_1 <= 1'b1; - b2m_fsm_arbiter_logic_priority_roundRobins_2 <= 1'b1; - b2m_fsm_arbiter_logic_priority_roundRobins_3 <= 1'b1; - b2m_fsm_arbiter_logic_priority_counter <= 2'b00; - b2m_fsm_sel_valid_regNext <= 1'b0; - b2m_fsm_s1 <= 1'b0; - b2m_fsm_s2 <= 1'b0; - b2m_fsm_toggle <= 1'b0; - memory_core_io_reads_1_rsp_rValidN <= 1'b1; - _zz_io_flush <= 1'b0; - io_write_cmd_payload_first <= 1'b1; - ll_cmd_valid <= 1'b0; - ll_readRsp_beatCounter <= 1'b0; - end else begin - if(channels_0_channelStart) begin - channels_0_channelValid <= 1'b1; - end - if(channels_0_channelCompletion) begin - channels_0_channelValid <= 1'b0; - end - if(channels_0_descriptorStart) begin - channels_0_descriptorValid <= 1'b1; - end - if(channels_0_descriptorCompletion) begin - channels_0_descriptorValid <= 1'b0; - end - channels_0_ctrl_kick <= 1'b0; - if(channels_0_channelCompletion) begin - channels_0_ctrl_kick <= 1'b0; - end - if(when_DmaSg_l318) begin - if(when_DmaSg_l320) begin - if(!when_DmaSg_l322) begin - channels_0_ll_valid <= 1'b0; - end - end - end - if(channels_0_ll_sgStart) begin - channels_0_ll_valid <= 1'b1; - end - if(channels_0_channelCompletion) begin - channels_0_ll_valid <= 1'b0; - end - channels_0_pop_b2m_memPending <= (_zz_channels_0_pop_b2m_memPending - _zz_channels_0_pop_b2m_memPending_3); - if(when_DmaSg_l255) begin - channels_0_interrupts_completion_valid <= 1'b1; - end - if(when_DmaSg_l255_1) begin - channels_0_interrupts_completion_valid <= 1'b0; - end - if(when_DmaSg_l255_2) begin - channels_0_interrupts_onChannelCompletion_valid <= 1'b1; - end - if(when_DmaSg_l255_3) begin - channels_0_interrupts_onChannelCompletion_valid <= 1'b0; - end - if(channels_0_ll_descriptorUpdated) begin - channels_0_interrupts_onLinkedListUpdate_valid <= 1'b1; - end - if(when_DmaSg_l255_4) begin - channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; - end - if(channels_0_pop_b2m_packetSync) begin - channels_0_interrupts_s2mPacket_valid <= 1'b1; - end - if(when_DmaSg_l255_5) begin - channels_0_interrupts_s2mPacket_valid <= 1'b0; - end - if(channels_1_channelStart) begin - channels_1_channelValid <= 1'b1; - end - if(channels_1_channelCompletion) begin - channels_1_channelValid <= 1'b0; - end - if(channels_1_descriptorStart) begin - channels_1_descriptorValid <= 1'b1; - end - if(channels_1_descriptorCompletion) begin - channels_1_descriptorValid <= 1'b0; - end - channels_1_ctrl_kick <= 1'b0; - if(channels_1_channelCompletion) begin - channels_1_ctrl_kick <= 1'b0; - end - if(when_DmaSg_l318_1) begin - if(when_DmaSg_l320_1) begin - if(!when_DmaSg_l322_1) begin - channels_1_ll_valid <= 1'b0; - end - end - end - if(channels_1_ll_sgStart) begin - channels_1_ll_valid <= 1'b1; - end - if(channels_1_channelCompletion) begin - channels_1_ll_valid <= 1'b0; - end - channels_1_push_m2b_memPending <= (_zz_channels_1_push_m2b_memPending - _zz_channels_1_push_m2b_memPending_3); - if(channels_1_descriptorStart) begin - channels_1_push_m2b_loadDone <= 1'b0; - end - if(when_DmaSg_l255_6) begin - channels_1_interrupts_completion_valid <= 1'b1; - end - if(when_DmaSg_l255_7) begin - channels_1_interrupts_completion_valid <= 1'b0; - end - if(when_DmaSg_l255_8) begin - channels_1_interrupts_onChannelCompletion_valid <= 1'b1; - end - if(when_DmaSg_l255_9) begin - channels_1_interrupts_onChannelCompletion_valid <= 1'b0; - end - if(channels_1_ll_descriptorUpdated) begin - channels_1_interrupts_onLinkedListUpdate_valid <= 1'b1; - end - if(when_DmaSg_l255_10) begin - channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; - end - if(when_package_l12) begin - io_inputs_0_payload_last_regNextWhen <= io_inputs_0_payload_last; - end - if(when_package_l12_1) begin - io_inputs_0_payload_last_regNextWhen_1 <= io_inputs_0_payload_last; - end - if(when_package_l12_2) begin - io_inputs_0_payload_last_regNextWhen_2 <= io_inputs_0_payload_last; - end - if(when_package_l12_3) begin - io_inputs_0_payload_last_regNextWhen_3 <= io_inputs_0_payload_last; - end - if(when_package_l12_4) begin - io_inputs_0_payload_last_regNextWhen_4 <= io_inputs_0_payload_last; - end - if(when_package_l12_5) begin - io_inputs_0_payload_last_regNextWhen_5 <= io_inputs_0_payload_last; - end - if(when_package_l12_6) begin - io_inputs_0_payload_last_regNextWhen_6 <= io_inputs_0_payload_last; - end - if(when_package_l12_7) begin - io_inputs_0_payload_last_regNextWhen_7 <= io_inputs_0_payload_last; - end - if(when_package_l12_8) begin - io_inputs_0_payload_last_regNextWhen_8 <= io_inputs_0_payload_last; - end - if(when_package_l12_9) begin - io_inputs_0_payload_last_regNextWhen_9 <= io_inputs_0_payload_last; - end - if(when_package_l12_10) begin - io_inputs_0_payload_last_regNextWhen_10 <= io_inputs_0_payload_last; - end - if(when_package_l12_11) begin - io_inputs_0_payload_last_regNextWhen_11 <= io_inputs_0_payload_last; - end - if(when_package_l12_12) begin - io_inputs_0_payload_last_regNextWhen_12 <= io_inputs_0_payload_last; - end - if(when_package_l12_13) begin - io_inputs_0_payload_last_regNextWhen_13 <= io_inputs_0_payload_last; - end - if(when_package_l12_14) begin - io_inputs_0_payload_last_regNextWhen_14 <= io_inputs_0_payload_last; - end - if(when_package_l12_15) begin - io_inputs_0_payload_last_regNextWhen_15 <= io_inputs_0_payload_last; - end - if(when_DmaSg_l758) begin - if(when_DmaSg_l760) begin - m2b_cmd_s0_valid <= 1'b1; - if(when_DmaSg_l763) begin - m2b_cmd_s0_priority_roundRobins_0 <= m2b_cmd_s0_priority_contextNext; - end - if(when_DmaSg_l763_1) begin - m2b_cmd_s0_priority_roundRobins_1 <= m2b_cmd_s0_priority_contextNext; - end - if(when_DmaSg_l763_2) begin - m2b_cmd_s0_priority_roundRobins_2 <= m2b_cmd_s0_priority_contextNext; - end - if(when_DmaSg_l763_3) begin - m2b_cmd_s0_priority_roundRobins_3 <= m2b_cmd_s0_priority_contextNext; - end - m2b_cmd_s0_priority_counter <= (m2b_cmd_s0_priority_counter + 2'b01); - if(m2b_cmd_s0_priority_weightLast) begin - m2b_cmd_s0_priority_counter <= 2'b00; - end - end - end - if(m2b_cmd_s0_valid) begin - m2b_cmd_s1_valid <= 1'b1; - end - if(m2b_cmd_s1_valid) begin - if(io_read_cmd_ready) begin - m2b_cmd_s0_valid <= 1'b0; - m2b_cmd_s1_valid <= 1'b0; - if(when_DmaSg_l828) begin - if(m2b_cmd_s1_lastBurst) begin - channels_1_push_m2b_loadDone <= 1'b1; - end - end - end - end - if(io_read_rsp_fire) begin - m2b_rsp_first <= io_read_rsp_payload_last; - end - if(when_DmaSg_l758_1) begin - if(when_DmaSg_l760_1) begin - b2m_fsm_arbiter_logic_valid <= 1'b1; - if(when_DmaSg_l763_4) begin - b2m_fsm_arbiter_logic_priority_roundRobins_0 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - if(when_DmaSg_l763_5) begin - b2m_fsm_arbiter_logic_priority_roundRobins_1 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - if(when_DmaSg_l763_6) begin - b2m_fsm_arbiter_logic_priority_roundRobins_2 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - if(when_DmaSg_l763_7) begin - b2m_fsm_arbiter_logic_priority_roundRobins_3 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - b2m_fsm_arbiter_logic_priority_counter <= (b2m_fsm_arbiter_logic_priority_counter + 2'b01); - if(b2m_fsm_arbiter_logic_priority_weightLast) begin - b2m_fsm_arbiter_logic_priority_counter <= 2'b00; - end - end - end - if(b2m_fsm_sel_ready) begin - b2m_fsm_sel_valid <= 1'b0; - if(b2m_fsm_sel_valid) begin - b2m_fsm_arbiter_logic_valid <= 1'b0; - end - end - if(when_DmaSg_l935) begin - b2m_fsm_sel_valid <= 1'b1; - end - b2m_fsm_sel_valid_regNext <= b2m_fsm_sel_valid; - b2m_fsm_s1 <= b2m_fsm_s0; - if(b2m_fsm_s1) begin - b2m_fsm_s2 <= 1'b1; - end - if(when_DmaSg_l986) begin - b2m_fsm_s2 <= 1'b0; - end - if(when_DmaSg_l1013) begin - b2m_fsm_toggle <= (! b2m_fsm_toggle); - end - if(memory_core_io_reads_1_rsp_valid) begin - memory_core_io_reads_1_rsp_rValidN <= 1'b0; - end - if(memory_core_io_reads_1_rsp_s2mPipe_ready) begin - memory_core_io_reads_1_rsp_rValidN <= 1'b1; - end - _zz_io_flush <= (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready)); - if(io_write_cmd_fire) begin - io_write_cmd_payload_first <= io_write_cmd_payload_last; - end - if(when_DmaSg_l1160) begin - if(when_DmaSg_l1161) begin - ll_cmd_valid <= 1'b1; - end - end else begin - if(when_DmaSg_l1177) begin - ll_cmd_valid <= 1'b0; - end - end - if(io_sgRead_rsp_fire) begin - ll_readRsp_beatCounter <= (ll_readRsp_beatCounter + 1'b1); - end - if(when_BusSlaveFactory_l377_1) begin - if(when_BusSlaveFactory_l379_1) begin - channels_0_ctrl_kick <= _zz_channels_0_ctrl_kick[0]; - end - end - if(when_BusSlaveFactory_l341) begin - if(when_BusSlaveFactory_l347) begin - channels_0_interrupts_completion_valid <= _zz_channels_0_interrupts_completion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_1) begin - if(when_BusSlaveFactory_l347_1) begin - channels_0_interrupts_onChannelCompletion_valid <= _zz_channels_0_interrupts_onChannelCompletion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_2) begin - if(when_BusSlaveFactory_l347_2) begin - channels_0_interrupts_onLinkedListUpdate_valid <= _zz_channels_0_interrupts_onLinkedListUpdate_valid[0]; - end - end - if(when_BusSlaveFactory_l341_3) begin - if(when_BusSlaveFactory_l347_3) begin - channels_0_interrupts_s2mPacket_valid <= _zz_channels_0_interrupts_s2mPacket_valid[0]; - end - end - if(when_BusSlaveFactory_l377_5) begin - if(when_BusSlaveFactory_l379_5) begin - channels_1_ctrl_kick <= _zz_channels_1_ctrl_kick[0]; - end - end - if(when_BusSlaveFactory_l341_4) begin - if(when_BusSlaveFactory_l347_4) begin - channels_1_interrupts_completion_valid <= _zz_channels_1_interrupts_completion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_5) begin - if(when_BusSlaveFactory_l347_5) begin - channels_1_interrupts_onChannelCompletion_valid <= _zz_channels_1_interrupts_onChannelCompletion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_6) begin - if(when_BusSlaveFactory_l347_6) begin - channels_1_interrupts_onLinkedListUpdate_valid <= _zz_channels_1_interrupts_onLinkedListUpdate_valid[0]; - end - end - case(io_ctrl_PADDR) - 14'h0078 : begin - if(ctrl_doWrite) begin - channels_0_ll_onSgStream <= io_ctrl_PWDATA[0]; - end - end - 14'h0044 : begin - if(ctrl_doWrite) begin - channels_0_priority <= io_ctrl_PWDATA[1 : 0]; - channels_0_weight <= io_ctrl_PWDATA[9 : 8]; - end - end - 14'h0050 : begin - if(ctrl_doWrite) begin - channels_0_interrupts_completion_enable <= io_ctrl_PWDATA[0]; - channels_0_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; - channels_0_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; - channels_0_interrupts_s2mPacket_enable <= io_ctrl_PWDATA[4]; - end - end - 14'h00f8 : begin - if(ctrl_doWrite) begin - channels_1_ll_onSgStream <= io_ctrl_PWDATA[0]; - end - end - 14'h00c4 : begin - if(ctrl_doWrite) begin - channels_1_priority <= io_ctrl_PWDATA[1 : 0]; - channels_1_weight <= io_ctrl_PWDATA[9 : 8]; - end - end - 14'h00d0 : begin - if(ctrl_doWrite) begin - channels_1_interrupts_completion_enable <= io_ctrl_PWDATA[0]; - channels_1_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; - channels_1_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(channels_0_bytesProbe_incr_valid) begin - channels_0_bytesProbe_value <= (_zz_channels_0_bytesProbe_value + 27'h0000001); - end - if(channels_0_descriptorStart) begin - channels_0_ll_packet <= 1'b0; - end - if(channels_0_descriptorStart) begin - channels_0_ll_requireSync <= 1'b0; - end - if(when_DmaSg_l318) begin - channels_0_ll_waitDone <= 1'b0; - if(when_DmaSg_l320) begin - channels_0_ll_head <= 1'b0; - end - end - if(channels_0_channelStart) begin - channels_0_ll_waitDone <= 1'b0; - channels_0_ll_head <= 1'b1; - end - channels_0_fifo_push_ptr <= (channels_0_fifo_push_ptr + channels_0_fifo_push_ptrIncr_value); - if(channels_0_channelStart) begin - channels_0_fifo_push_ptr <= 11'h0; - end - channels_0_fifo_pop_ptr <= (channels_0_fifo_pop_ptr + channels_0_fifo_pop_ptrIncr_value); - channels_0_fifo_pop_withOverride_backup <= channels_0_fifo_pop_withOverride_backupNext; - if(when_DmaSg_l409) begin - channels_0_fifo_pop_withOverride_valid <= 1'b0; - end - if(channels_0_fifo_pop_withOverride_load) begin - channels_0_fifo_pop_withOverride_valid <= 1'b1; - end - channels_0_fifo_pop_withOverride_exposed <= ((! channels_0_fifo_pop_withOverride_valid) ? channels_0_fifo_pop_withOverride_backupNext : _zz_channels_0_fifo_pop_withOverride_exposed); - if(channels_0_channelStart) begin - channels_0_fifo_pop_withOverride_backup <= 14'h0; - channels_0_fifo_pop_withOverride_valid <= 1'b0; - end - if(channels_0_channelStart) begin - channels_0_push_s2b_packetLock <= 1'b0; - end - if(channels_0_pop_b2m_fire) begin - channels_0_pop_b2m_flush <= 1'b0; - end - if(when_DmaSg_l505) begin - channels_0_pop_b2m_packet <= 1'b0; - end - if(when_DmaSg_l523) begin - channels_0_pop_b2m_flush <= 1'b0; - channels_0_pop_b2m_packet <= 1'b0; - end - if(channels_0_pop_b2m_packetSync) begin - channels_0_push_s2b_packetLock <= 1'b0; - if(when_DmaSg_l532) begin - if(!channels_0_push_s2b_completionOnLast) begin - if(when_DmaSg_l536) begin - channels_0_ll_requireSync <= 1'b1; - end - end - channels_0_ll_packet <= 1'b1; - end - end - if(channels_0_channelStart) begin - channels_0_pop_b2m_bytesToSkip <= 4'b0000; - channels_0_pop_b2m_flush <= 1'b0; - end - if(channels_0_descriptorStart) begin - channels_0_pop_b2m_bytesLeft <= {1'd0, channels_0_bytes}; - channels_0_pop_b2m_waitFinalRsp <= 1'b0; - end - if(channels_0_channelValid) begin - if(!channels_0_channelStop) begin - if(when_DmaSg_l575) begin - if(when_DmaSg_l593) begin - channels_0_channelStop <= 1'b1; - end - end - end - end - channels_0_fifo_pop_ptrIncr_value_regNext <= channels_0_fifo_pop_ptrIncr_value; - channels_0_fifo_push_available <= (_zz_channels_0_fifo_push_available - (channels_0_push_memory ? channels_0_fifo_push_availableDecr : channels_0_fifo_push_ptrIncr_value)); - if(channels_0_channelStart) begin - channels_0_fifo_push_ptr <= 11'h0; - channels_0_fifo_push_available <= (channels_0_fifo_words + 11'h001); - channels_0_fifo_pop_ptr <= 11'h0; - end - if(when_DmaSg_l625) begin - channels_0_bytesProbe_value <= 27'h0; - end - if(channels_1_bytesProbe_incr_valid) begin - channels_1_bytesProbe_value <= (_zz_channels_1_bytesProbe_value + 27'h0000001); - end - if(channels_1_descriptorStart) begin - channels_1_ll_packet <= 1'b0; - end - if(channels_1_descriptorStart) begin - channels_1_ll_requireSync <= 1'b0; - end - if(when_DmaSg_l318_1) begin - channels_1_ll_waitDone <= 1'b0; - if(when_DmaSg_l320_1) begin - channels_1_ll_head <= 1'b0; - end - end - if(channels_1_channelStart) begin - channels_1_ll_waitDone <= 1'b0; - channels_1_ll_head <= 1'b1; - end - channels_1_fifo_push_ptr <= (channels_1_fifo_push_ptr + channels_1_fifo_push_ptrIncr_value); - if(channels_1_channelStart) begin - channels_1_fifo_push_ptr <= 11'h0; - end - channels_1_fifo_pop_ptr <= (channels_1_fifo_pop_ptr + channels_1_fifo_pop_ptrIncr_value); - channels_1_fifo_pop_withoutOverride_exposed <= (_zz_channels_1_fifo_pop_withoutOverride_exposed - channels_1_fifo_pop_bytesDecr_value); - if(channels_1_channelStart) begin - channels_1_fifo_pop_withoutOverride_exposed <= 14'h0; - end - if(channels_1_descriptorStart) begin - channels_1_push_m2b_bytesLeft <= channels_1_bytes; - end - if(when_DmaSg_l474) begin - channels_1_pop_b2s_veryLastValid <= 1'b1; - end - if(channels_1_pop_b2s_veryLastTrigger) begin - channels_1_pop_b2s_veryLastPtr <= channels_1_fifo_push_ptrWithBase; - channels_1_pop_b2s_veryLastEndPacket <= channels_1_pop_b2s_last; - end - if(channels_1_channelStart) begin - channels_1_pop_b2s_veryLastValid <= 1'b0; - end - if(channels_1_channelValid) begin - if(!channels_1_channelStop) begin - if(when_DmaSg_l575_1) begin - if(when_DmaSg_l593_1) begin - channels_1_channelStop <= 1'b1; - end - end - end - end - channels_1_fifo_pop_ptrIncr_value_regNext <= channels_1_fifo_pop_ptrIncr_value; - channels_1_fifo_push_available <= (_zz_channels_1_fifo_push_available - (channels_1_push_memory ? channels_1_fifo_push_availableDecr : channels_1_fifo_push_ptrIncr_value)); - if(channels_1_channelStart) begin - channels_1_fifo_push_ptr <= 11'h0; - channels_1_fifo_push_available <= (channels_1_fifo_words + 11'h001); - channels_1_fifo_pop_ptr <= 11'h0; - end - if(when_DmaSg_l625_1) begin - channels_1_bytesProbe_value <= 27'h0; - end - if(when_DmaSg_l665) begin - channels_0_push_s2b_waitFirst <= 1'b0; - if(io_inputs_0_payload_last) begin - channels_0_push_s2b_packetLock <= 1'b1; - end - end - if(when_DmaSg_l681) begin - channels_0_pop_b2m_flush <= 1'b1; - end - if(when_DmaSg_l682) begin - channels_0_pop_b2m_packet <= 1'b1; - end - if(when_DmaSg_l725) begin - if(when_DmaSg_l726) begin - channels_1_pop_b2s_veryLastValid <= 1'b0; - end - end - m2b_cmd_s1_address <= m2b_cmd_s0_address; - m2b_cmd_s1_length <= m2b_cmd_s0_length; - m2b_cmd_s1_lastBurst <= m2b_cmd_s0_lastBurst; - m2b_cmd_s1_bytesLeft <= m2b_cmd_s0_bytesLeft; - if(m2b_cmd_s1_valid) begin - if(io_read_cmd_ready) begin - if(when_DmaSg_l828) begin - channels_1_push_m2b_address <= m2b_cmd_s1_addressNext; - channels_1_push_m2b_bytesLeft <= m2b_cmd_s1_byteLeftNext; - end - end - end - if(when_DmaSg_l935) begin - b2m_fsm_sel_address <= channels_0_pop_b2m_address; - b2m_fsm_sel_ptr <= channels_0_fifo_pop_ptrWithBase; - b2m_fsm_sel_ptrMask <= channels_0_fifo_words; - b2m_fsm_sel_bytePerBurst <= channels_0_pop_b2m_bytePerBurst; - b2m_fsm_sel_bytesInFifo <= channels_0_fifo_pop_bytes; - b2m_fsm_sel_flush <= channels_0_pop_b2m_flush; - b2m_fsm_sel_packet <= channels_0_pop_b2m_packet; - b2m_fsm_sel_bytesLeft <= channels_0_pop_b2m_bytesLeft[25:0]; - end - if(b2m_fsm_s0) begin - b2m_fsm_sel_bytesInBurst <= _zz_b2m_fsm_sel_bytesInBurst_3[11:0]; - end - if(b2m_fsm_s1) begin - b2m_fsm_beatCounter <= (_zz_b2m_fsm_beatCounter >>> 3'd4); - if(when_DmaSg_l996) begin - channels_0_pop_b2m_address <= b2m_fsm_addressNext; - channels_0_pop_b2m_bytesLeft <= b2m_fsm_bytesLeftNext; - if(b2m_fsm_isFinalCmd) begin - channels_0_pop_b2m_waitFinalRsp <= 1'b1; - end - if(when_DmaSg_l1001) begin - if(b2m_fsm_sel_flush) begin - channels_0_pop_b2m_flush <= 1'b1; - end - if(b2m_fsm_sel_packet) begin - channels_0_pop_b2m_packet <= 1'b1; - end - end - end - end - if(when_DmaSg_l1033) begin - b2m_fsm_sel_ptr <= ((b2m_fsm_sel_ptr & (~ b2m_fsm_sel_ptrMask)) | (_zz_b2m_fsm_sel_ptr & b2m_fsm_sel_ptrMask)); - end - if(memory_core_io_reads_1_rsp_rValidN) begin - memory_core_io_reads_1_rsp_rData_data <= memory_core_io_reads_1_rsp_payload_data; - memory_core_io_reads_1_rsp_rData_mask <= memory_core_io_reads_1_rsp_payload_mask; - memory_core_io_reads_1_rsp_rData_context <= memory_core_io_reads_1_rsp_payload_context; - end - if(b2m_fsm_aggregate_memoryPort_fire) begin - b2m_fsm_aggregate_first <= 1'b0; - end - if(when_DmaSg_l1050) begin - b2m_fsm_aggregate_first <= 1'b1; - end - b2m_fsm_cmd_maskLastTriggerReg <= b2m_fsm_cmd_maskLastTriggerComb; - b2m_fsm_cmd_maskLast <= {(4'b1111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1011 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast <= b2m_fsm_cmd_maskLastTriggerComb),{_zz_b2m_fsm_cmd_maskLast_1,{_zz_b2m_fsm_cmd_maskLast_2,_zz_b2m_fsm_cmd_maskLast_3}}}}}}}}; - if(io_write_cmd_fire) begin - b2m_fsm_beatCounter <= (b2m_fsm_beatCounter - 8'h01); - end - if(when_DmaSg_l1102) begin - if(_zz_when_1[0]) begin - channels_0_pop_b2m_bytesToSkip <= (b2m_fsm_aggregate_engine_io_output_usedUntil + 4'b0001); - end - end - if(when_DmaSg_l1149) begin - ll_cmd_oh_0 <= channels_0_ll_requestLl; - ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; - end - if(when_DmaSg_l1148) begin - ll_cmd_ptr <= (_zz_ll_cmd_ptr[0] ? channels_0_ll_ptr : channels_1_ll_ptr); - end - if(when_DmaSg_l1148_1) begin - ll_cmd_ptrNext <= (_zz_ll_cmd_ptrNext[0] ? channels_0_ll_ptrNext : channels_1_ll_ptrNext); - end - if(when_DmaSg_l1148_2) begin - ll_cmd_bytesDone <= channels_0_bytesProbe_value; - end - if(when_DmaSg_l1148_3) begin - ll_cmd_endOfPacket <= (_zz_ll_cmd_endOfPacket[0] ? channels_0_ll_packet : channels_1_ll_packet); - end - if(when_DmaSg_l1154) begin - ll_cmd_isJustASink <= ll_arbiter_isJustASink; - end - if(when_DmaSg_l1155) begin - ll_cmd_doDescriptorStall <= ll_arbiter_doDescriptorStall; - end - if(when_DmaSg_l1156) begin - ll_cmd_onSgStream <= ll_arbiter_onSgStream; - end - if(when_DmaSg_l1160) begin - ll_cmd_oh_0 <= channels_0_ll_requestLl; - ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; - if(channels_0_ll_requestLl) begin - channels_0_ll_waitDone <= 1'b1; - channels_0_ll_writeDone <= ll_arbiter_head; - channels_0_ll_justASync <= ll_arbiter_isJustASink; - channels_0_ll_packet <= 1'b0; - channels_0_ll_requireSync <= 1'b0; - if(when_DmaSg_l1169) begin - channels_0_ll_ptr <= channels_0_ll_ptrNext; - end - channels_0_ll_readDone <= ll_arbiter_isJustASink; - end - if(_zz_ll_arbiter_head_1) begin - channels_1_ll_waitDone <= 1'b1; - channels_1_ll_writeDone <= ll_arbiter_head; - channels_1_ll_justASync <= ll_arbiter_isJustASink; - channels_1_ll_packet <= 1'b0; - channels_1_ll_requireSync <= 1'b0; - if(when_DmaSg_l1169_1) begin - channels_1_ll_ptr <= channels_1_ll_ptrNext; - end - channels_1_ll_readDone <= ll_arbiter_isJustASink; - end - ll_cmd_readFired <= ll_arbiter_isJustASink; - ll_cmd_writeFired <= ll_arbiter_head; - end - if(io_sgRead_cmd_fire) begin - ll_cmd_readFired <= 1'b1; - end - if(io_sgWrite_cmd_fire) begin - ll_cmd_writeFired <= 1'b1; - end - if(io_sgRead_rsp_fire) begin - if(when_DmaSg_l1248) begin - if(ll_readRsp_oh_1) begin - channels_1_push_m2b_address <= io_sgRead_rsp_payload_fragment_data[95 : 64]; - end - end - if(when_DmaSg_l1248_1) begin - if(ll_readRsp_oh_0) begin - channels_0_pop_b2m_address <= io_sgRead_rsp_payload_fragment_data[31 : 0]; - end - end - if(when_DmaSg_l1248_2) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; - end - end - if(when_DmaSg_l1248_3) begin - if(ll_readRsp_oh_0) begin - channels_0_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; - end - if(ll_readRsp_oh_1) begin - channels_1_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; - end - end - if(when_DmaSg_l1248_4) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; - end - end - if(when_DmaSg_l1248_5) begin - if(ll_readRsp_oh_1) begin - channels_1_pop_b2s_last <= io_sgRead_rsp_payload_fragment_data[62]; - end - end - if(when_DmaSg_l1248_6) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; - end - end - if(when_DmaSg_l1271) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_readDone <= 1'b1; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_readDone <= 1'b1; - end - end - end - if(io_sgWrite_rsp_fire) begin - if(ll_writeRsp_oh_0) begin - channels_0_ll_writeDone <= 1'b1; - end - if(ll_writeRsp_oh_1) begin - channels_1_ll_writeDone <= 1'b1; - end - end - case(io_ctrl_PADDR) - 14'h000c : begin - if(ctrl_doWrite) begin - channels_0_push_memory <= io_ctrl_PWDATA[12]; - channels_0_push_s2b_completionOnLast <= io_ctrl_PWDATA[13]; - channels_0_push_s2b_waitFirst <= io_ctrl_PWDATA[14]; - end - end - 14'h001c : begin - if(ctrl_doWrite) begin - channels_0_pop_memory <= io_ctrl_PWDATA[12]; - end - end - 14'h002c : begin - if(ctrl_doWrite) begin - channels_0_channelStop <= io_ctrl_PWDATA[2]; - end - end - 14'h0020 : begin - if(ctrl_doWrite) begin - channels_0_bytes <= io_ctrl_PWDATA[25 : 0]; - end - end - 14'h008c : begin - if(ctrl_doWrite) begin - channels_1_push_memory <= io_ctrl_PWDATA[12]; - end - end - 14'h0098 : begin - if(ctrl_doWrite) begin - channels_1_pop_b2s_sinkId <= io_ctrl_PWDATA[19 : 16]; - end - end - 14'h009c : begin - if(ctrl_doWrite) begin - channels_1_pop_memory <= io_ctrl_PWDATA[12]; - channels_1_pop_b2s_last <= io_ctrl_PWDATA[13]; - end - end - 14'h00ac : begin - if(ctrl_doWrite) begin - channels_1_channelStop <= io_ctrl_PWDATA[2]; - end - end - 14'h00a0 : begin - if(ctrl_doWrite) begin - channels_1_bytes <= io_ctrl_PWDATA[25 : 0]; - end - end - default : begin - end - endcase - if(when_Apb3SlaveFactory_l81) begin - if(ctrl_doWrite) begin - channels_0_pop_b2m_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - if(when_Apb3SlaveFactory_l81_1) begin - if(ctrl_doWrite) begin - channels_0_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - if(when_Apb3SlaveFactory_l81_2) begin - if(ctrl_doWrite) begin - channels_1_push_m2b_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - if(when_Apb3SlaveFactory_l81_3) begin - if(ctrl_doWrite) begin - channels_1_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - end - - -endmodule - -module EfxDMA_StreamArbiter_1_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_inputs_0_valid, - output wire io_inputs_0_ready, - input wire io_inputs_0_payload_last, - input wire [0:0] io_inputs_0_payload_fragment_source, - input wire [0:0] io_inputs_0_payload_fragment_opcode, - input wire [31:0] io_inputs_0_payload_fragment_address, - input wire [11:0] io_inputs_0_payload_fragment_length, - input wire [127:0] io_inputs_0_payload_fragment_data, - input wire [15:0] io_inputs_0_payload_fragment_mask, - input wire [12:0] io_inputs_0_payload_fragment_context, - input wire io_inputs_1_valid, - output wire io_inputs_1_ready, - input wire io_inputs_1_payload_last, - input wire [0:0] io_inputs_1_payload_fragment_source, - input wire [0:0] io_inputs_1_payload_fragment_opcode, - input wire [31:0] io_inputs_1_payload_fragment_address, - input wire [11:0] io_inputs_1_payload_fragment_length, - input wire [127:0] io_inputs_1_payload_fragment_data, - input wire [15:0] io_inputs_1_payload_fragment_mask, - input wire [12:0] io_inputs_1_payload_fragment_context, - output wire io_output_valid, - input wire io_output_ready, - output wire io_output_payload_last, - output wire [0:0] io_output_payload_fragment_source, - output wire [0:0] io_output_payload_fragment_opcode, - output wire [31:0] io_output_payload_fragment_address, - output wire [11:0] io_output_payload_fragment_length, - output wire [127:0] io_output_payload_fragment_data, - output wire [15:0] io_output_payload_fragment_mask, - output wire [12:0] io_output_payload_fragment_context, - output wire [0:0] io_chosen, - output wire [1:0] io_chosenOH, - input wire clk, - input wire reset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l683; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l683 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); - assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge clk) begin - if(reset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l683) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module EfxDMA_StreamArbiter_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_inputs_0_valid, - output wire io_inputs_0_ready, - input wire io_inputs_0_payload_last, - input wire [0:0] io_inputs_0_payload_fragment_source, - input wire [0:0] io_inputs_0_payload_fragment_opcode, - input wire [31:0] io_inputs_0_payload_fragment_address, - input wire [11:0] io_inputs_0_payload_fragment_length, - input wire [20:0] io_inputs_0_payload_fragment_context, - input wire io_inputs_1_valid, - output wire io_inputs_1_ready, - input wire io_inputs_1_payload_last, - input wire [0:0] io_inputs_1_payload_fragment_source, - input wire [0:0] io_inputs_1_payload_fragment_opcode, - input wire [31:0] io_inputs_1_payload_fragment_address, - input wire [11:0] io_inputs_1_payload_fragment_length, - input wire [20:0] io_inputs_1_payload_fragment_context, - output wire io_output_valid, - input wire io_output_ready, - output wire io_output_payload_last, - output wire [0:0] io_output_payload_fragment_source, - output wire [0:0] io_output_payload_fragment_opcode, - output wire [31:0] io_output_payload_fragment_address, - output wire [11:0] io_output_payload_fragment_length, - output wire [20:0] io_output_payload_fragment_context, - output wire [0:0] io_chosen, - output wire [1:0] io_chosenOH, - input wire clk, - input wire reset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l683; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l683 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge clk) begin - if(reset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l683) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module EfxDMA_BufferCC_5_a048ca8f51874147a1cd65d43e6523ef ( - input wire [4:0] io_dataIn, - output wire [4:0] io_dataOut, - input wire dat1_o_clk, - input wire dat1_o_reset -); - - (* async_reg = "true" *) reg [4:0] buffers_0; - (* async_reg = "true" *) reg [4:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge dat1_o_clk) begin - if(dat1_o_reset) begin - buffers_0 <= 5'h0; - buffers_1 <= 5'h0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -//EfxDMA_BufferCC_4 replaced by EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef - -module EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef ( - input wire [4:0] io_dataIn, - output wire [4:0] io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg [4:0] buffers_0; - (* async_reg = "true" *) reg [4:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 5'h0; - buffers_1 <= 5'h0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module EfxDMA_BufferCC_2_a048ca8f51874147a1cd65d43e6523ef ( - input wire [4:0] io_dataIn, - output wire [4:0] io_dataOut, - input wire dat0_i_clk, - input wire dat0_i_reset -); - - (* async_reg = "true" *) reg [4:0] buffers_0; - (* async_reg = "true" *) reg [4:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge dat0_i_clk) begin - if(dat0_i_reset) begin - buffers_0 <= 5'h0; - buffers_1 <= 5'h0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module EfxDMA_BmbContextRemover_1_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_cmd_valid, - output reg io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [127:0] io_input_cmd_payload_fragment_data, - input wire [15:0] io_input_cmd_payload_fragment_mask, - input wire [13:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [13:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [127:0] io_output_cmd_payload_fragment_data, - output wire [15:0] io_output_cmd_payload_fragment_mask, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire clk, - input wire reset -); - - reg fifoFork_thrown_translated_fifo_io_pop_ready; - wire fifoFork_thrown_translated_fifo_io_push_ready; - wire fifoFork_thrown_translated_fifo_io_pop_valid; - wire [13:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; - wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; - wire [2:0] fifoFork_thrown_translated_fifo_io_availability; - wire fifoFork_valid; - reg fifoFork_ready; - wire fifoFork_payload_last; - wire [0:0] fifoFork_payload_fragment_opcode; - wire [31:0] fifoFork_payload_fragment_address; - wire [11:0] fifoFork_payload_fragment_length; - wire [127:0] fifoFork_payload_fragment_data; - wire [15:0] fifoFork_payload_fragment_mask; - wire [13:0] fifoFork_payload_fragment_context; - wire cmdFork_valid; - wire cmdFork_ready; - wire cmdFork_payload_last; - wire [0:0] cmdFork_payload_fragment_opcode; - wire [31:0] cmdFork_payload_fragment_address; - wire [11:0] cmdFork_payload_fragment_length; - wire [127:0] cmdFork_payload_fragment_data; - wire [15:0] cmdFork_payload_fragment_mask; - wire [13:0] cmdFork_payload_fragment_context; - reg io_input_cmd_fork2_logic_linkEnable_0; - reg io_input_cmd_fork2_logic_linkEnable_1; - wire when_Stream_l1063; - wire when_Stream_l1063_1; - wire fifoFork_fire; - wire cmdFork_fire; - wire [13:0] pushCtx_context; - reg fifoFork_payload_first; - wire when_Stream_l445; - reg fifoFork_thrown_valid; - wire fifoFork_thrown_ready; - wire fifoFork_thrown_payload_last; - wire [0:0] fifoFork_thrown_payload_fragment_opcode; - wire [31:0] fifoFork_thrown_payload_fragment_address; - wire [11:0] fifoFork_thrown_payload_fragment_length; - wire [127:0] fifoFork_thrown_payload_fragment_data; - wire [15:0] fifoFork_thrown_payload_fragment_mask; - wire [13:0] fifoFork_thrown_payload_fragment_context; - wire fifoFork_thrown_translated_valid; - wire fifoFork_thrown_translated_ready; - wire [13:0] fifoFork_thrown_translated_payload_context; - wire popCtx_valid; - wire popCtx_ready; - wire [13:0] popCtx_payload_context; - reg fifoFork_thrown_translated_fifo_io_pop_rValid; - reg [13:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; - wire when_Stream_l375; - wire _zz_io_input_rsp_valid; - - EfxDMA_StreamFifo_1_a048ca8f51874147a1cd65d43e6523ef fifoFork_thrown_translated_fifo ( - .io_push_valid (fifoFork_thrown_translated_valid ), //i - .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o - .io_push_payload_context (fifoFork_thrown_translated_payload_context[13:0] ), //i - .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o - .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i - .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[13:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o - .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - io_input_cmd_ready = 1'b1; - if(when_Stream_l1063) begin - io_input_cmd_ready = 1'b0; - end - if(when_Stream_l1063_1) begin - io_input_cmd_ready = 1'b0; - end - end - - assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); - assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); - assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); - assign fifoFork_payload_last = io_input_cmd_payload_last; - assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign fifoFork_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign fifoFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); - assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); - assign cmdFork_payload_last = io_input_cmd_payload_last; - assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign cmdFork_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign cmdFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); - assign io_output_cmd_valid = cmdFork_valid; - assign cmdFork_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = cmdFork_payload_last; - assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = cmdFork_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = cmdFork_payload_fragment_mask; - assign pushCtx_context = fifoFork_payload_fragment_context; - assign when_Stream_l445 = (! fifoFork_payload_first); - always @(*) begin - fifoFork_thrown_valid = fifoFork_valid; - if(when_Stream_l445) begin - fifoFork_thrown_valid = 1'b0; - end - end - - always @(*) begin - fifoFork_ready = fifoFork_thrown_ready; - if(when_Stream_l445) begin - fifoFork_ready = 1'b1; - end - end - - assign fifoFork_thrown_payload_last = fifoFork_payload_last; - assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; - assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; - assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; - assign fifoFork_thrown_payload_fragment_data = fifoFork_payload_fragment_data; - assign fifoFork_thrown_payload_fragment_mask = fifoFork_payload_fragment_mask; - assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; - assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; - assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; - assign fifoFork_thrown_translated_payload_context = pushCtx_context; - assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; - always @(*) begin - fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; - if(when_Stream_l375) begin - fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCtx_valid); - assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; - assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; - assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); - assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); - assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); - assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_context = popCtx_payload_context; - always @(posedge clk) begin - if(reset) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - fifoFork_payload_first <= 1'b1; - fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; - end else begin - if(fifoFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_cmd_ready) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - end - if(fifoFork_fire) begin - fifoFork_payload_first <= fifoFork_payload_last; - end - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; - end - end - end - - always @(posedge clk) begin - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; - end - end - - -endmodule - -module EfxDMA_BmbContextRemover_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_cmd_valid, - output reg io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [21:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [127:0] io_input_rsp_payload_fragment_data, - output wire [21:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [127:0] io_output_rsp_payload_fragment_data, - input wire clk, - input wire reset -); - - reg fifoFork_thrown_translated_fifo_io_pop_ready; - wire fifoFork_thrown_translated_fifo_io_push_ready; - wire fifoFork_thrown_translated_fifo_io_pop_valid; - wire [21:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; - wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; - wire [2:0] fifoFork_thrown_translated_fifo_io_availability; - wire fifoFork_valid; - reg fifoFork_ready; - wire fifoFork_payload_last; - wire [0:0] fifoFork_payload_fragment_opcode; - wire [31:0] fifoFork_payload_fragment_address; - wire [11:0] fifoFork_payload_fragment_length; - wire [21:0] fifoFork_payload_fragment_context; - wire cmdFork_valid; - wire cmdFork_ready; - wire cmdFork_payload_last; - wire [0:0] cmdFork_payload_fragment_opcode; - wire [31:0] cmdFork_payload_fragment_address; - wire [11:0] cmdFork_payload_fragment_length; - wire [21:0] cmdFork_payload_fragment_context; - reg io_input_cmd_fork2_logic_linkEnable_0; - reg io_input_cmd_fork2_logic_linkEnable_1; - wire when_Stream_l1063; - wire when_Stream_l1063_1; - wire fifoFork_fire; - wire cmdFork_fire; - wire [21:0] pushCtx_context; - reg fifoFork_payload_first; - wire when_Stream_l445; - reg fifoFork_thrown_valid; - wire fifoFork_thrown_ready; - wire fifoFork_thrown_payload_last; - wire [0:0] fifoFork_thrown_payload_fragment_opcode; - wire [31:0] fifoFork_thrown_payload_fragment_address; - wire [11:0] fifoFork_thrown_payload_fragment_length; - wire [21:0] fifoFork_thrown_payload_fragment_context; - wire fifoFork_thrown_translated_valid; - wire fifoFork_thrown_translated_ready; - wire [21:0] fifoFork_thrown_translated_payload_context; - wire popCtx_valid; - wire popCtx_ready; - wire [21:0] popCtx_payload_context; - reg fifoFork_thrown_translated_fifo_io_pop_rValid; - reg [21:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; - wire when_Stream_l375; - wire _zz_io_input_rsp_valid; - - EfxDMA_StreamFifo_a048ca8f51874147a1cd65d43e6523ef fifoFork_thrown_translated_fifo ( - .io_push_valid (fifoFork_thrown_translated_valid ), //i - .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o - .io_push_payload_context (fifoFork_thrown_translated_payload_context[21:0] ), //i - .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o - .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i - .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[21:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o - .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - io_input_cmd_ready = 1'b1; - if(when_Stream_l1063) begin - io_input_cmd_ready = 1'b0; - end - if(when_Stream_l1063_1) begin - io_input_cmd_ready = 1'b0; - end - end - - assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); - assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); - assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); - assign fifoFork_payload_last = io_input_cmd_payload_last; - assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); - assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); - assign cmdFork_payload_last = io_input_cmd_payload_last; - assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); - assign io_output_cmd_valid = cmdFork_valid; - assign cmdFork_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = cmdFork_payload_last; - assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; - assign pushCtx_context = fifoFork_payload_fragment_context; - assign when_Stream_l445 = (! fifoFork_payload_first); - always @(*) begin - fifoFork_thrown_valid = fifoFork_valid; - if(when_Stream_l445) begin - fifoFork_thrown_valid = 1'b0; - end - end - - always @(*) begin - fifoFork_ready = fifoFork_thrown_ready; - if(when_Stream_l445) begin - fifoFork_ready = 1'b1; - end - end - - assign fifoFork_thrown_payload_last = fifoFork_payload_last; - assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; - assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; - assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; - assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; - assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; - assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; - assign fifoFork_thrown_translated_payload_context = pushCtx_context; - assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; - always @(*) begin - fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; - if(when_Stream_l375) begin - fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCtx_valid); - assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; - assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; - assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); - assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); - assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); - assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = popCtx_payload_context; - always @(posedge clk) begin - if(reset) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - fifoFork_payload_first <= 1'b1; - fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; - end else begin - if(fifoFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_cmd_ready) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - end - if(fifoFork_fire) begin - fifoFork_payload_first <= fifoFork_payload_last; - end - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; - end - end - end - - always @(posedge clk) begin - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; - end - end - - -endmodule - -module EfxDMA_FlowCCUnsafeByToggle_1_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_valid, - input wire [31:0] io_input_payload_PRDATA, - input wire io_input_payload_PSLVERROR, - output wire io_output_valid, - output wire [31:0] io_output_payload_PRDATA, - output wire io_output_payload_PSLVERROR, - input wire clk, - input wire reset, - input wire ctrl_clk, - input wire ctrl_reset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg [31:0] inputArea_data_PRDATA; - reg inputArea_data_PSLVERROR; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire [31:0] outputArea_flow_payload_PRDATA; - wire outputArea_flow_payload_PSLVERROR; - reg outputArea_flow_m2sPipe_valid; - (* async_reg = "true" *) reg [31:0] outputArea_flow_m2sPipe_payload_PRDATA; - (* async_reg = "true" *) reg outputArea_flow_m2sPipe_payload_PSLVERROR; - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_1_a048ca8f51874147a1cd65d43e6523ef inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ) //i - ); - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_PRDATA = inputArea_data_PRDATA; - assign outputArea_flow_payload_PSLVERROR = inputArea_data_PSLVERROR; - assign io_output_valid = outputArea_flow_m2sPipe_valid; - assign io_output_payload_PRDATA = outputArea_flow_m2sPipe_payload_PRDATA; - assign io_output_payload_PSLVERROR = outputArea_flow_m2sPipe_payload_PSLVERROR; - always @(posedge clk) begin - if(reset) begin - inputArea_target <= 1'b0; - end else begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - end - end - end - - always @(posedge clk) begin - if(io_input_valid) begin - inputArea_data_PRDATA <= io_input_payload_PRDATA; - inputArea_data_PSLVERROR <= io_input_payload_PSLVERROR; - end - end - - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - outputArea_flow_m2sPipe_valid <= 1'b0; - outputArea_hit <= 1'b0; - end else begin - outputArea_hit <= outputArea_target; - outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; - end - end - - always @(posedge ctrl_clk) begin - if(outputArea_flow_valid) begin - outputArea_flow_m2sPipe_payload_PRDATA <= outputArea_flow_payload_PRDATA; - outputArea_flow_m2sPipe_payload_PSLVERROR <= outputArea_flow_payload_PSLVERROR; - end - end - - -endmodule - -module EfxDMA_FlowCCUnsafeByToggle_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_valid, - input wire [13:0] io_input_payload_PADDR, - input wire io_input_payload_PWRITE, - input wire [31:0] io_input_payload_PWDATA, - output wire io_output_valid, - output wire [13:0] io_output_payload_PADDR, - output wire io_output_payload_PWRITE, - output wire [31:0] io_output_payload_PWDATA, - input wire ctrl_clk, - input wire ctrl_reset, - input wire clk, - input wire reset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg [13:0] inputArea_data_PADDR; - reg inputArea_data_PWRITE; - reg [31:0] inputArea_data_PWDATA; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire [13:0] outputArea_flow_payload_PADDR; - wire outputArea_flow_payload_PWRITE; - wire [31:0] outputArea_flow_payload_PWDATA; - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_a048ca8f51874147a1cd65d43e6523ef inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_PADDR = inputArea_data_PADDR; - assign outputArea_flow_payload_PWRITE = inputArea_data_PWRITE; - assign outputArea_flow_payload_PWDATA = inputArea_data_PWDATA; - assign io_output_valid = outputArea_flow_valid; - assign io_output_payload_PADDR = outputArea_flow_payload_PADDR; - assign io_output_payload_PWRITE = outputArea_flow_payload_PWRITE; - assign io_output_payload_PWDATA = outputArea_flow_payload_PWDATA; - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - inputArea_target <= 1'b0; - end else begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - end - end - end - - always @(posedge ctrl_clk) begin - if(io_input_valid) begin - inputArea_data_PADDR <= io_input_payload_PADDR; - inputArea_data_PWRITE <= io_input_payload_PWRITE; - inputArea_data_PWDATA <= io_input_payload_PWDATA; - end - end - - always @(posedge clk) begin - if(reset) begin - outputArea_hit <= 1'b0; - end else begin - outputArea_hit <= outputArea_target; - end - end - - -endmodule - -module EfxDMA_Aggregator_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_input_valid, - output reg io_input_ready, - input wire [127:0] io_input_payload_data, - input wire [15:0] io_input_payload_mask, - output reg [127:0] io_output_data, - output reg [15:0] io_output_mask, - input wire io_output_enough, - input wire io_output_consume, - output wire io_output_consumed, - input wire [3:0] io_output_lastByteUsed, - output wire [3:0] io_output_usedUntil, - input wire io_flush, - input wire [3:0] io_offset, - input wire [11:0] io_burstLength, - input wire clk, - input wire reset -); - - reg [0:0] _zz_s0_countOnesLogic_0_1; - wire [0:0] _zz_s0_countOnesLogic_0_2; - reg [1:0] _zz_s0_countOnesLogic_1_1; - wire [1:0] _zz_s0_countOnesLogic_1_2; - reg [1:0] _zz_s0_countOnesLogic_2_1; - wire [2:0] _zz_s0_countOnesLogic_2_2; - reg [2:0] _zz_s0_countOnesLogic_3_9; - wire [2:0] _zz_s0_countOnesLogic_3_10; - reg [2:0] _zz_s0_countOnesLogic_3_11; - wire [2:0] _zz_s0_countOnesLogic_3_12; - wire [0:0] _zz_s0_countOnesLogic_3_13; - reg [2:0] _zz_s0_countOnesLogic_4_9; - wire [2:0] _zz_s0_countOnesLogic_4_10; - reg [2:0] _zz_s0_countOnesLogic_4_11; - wire [2:0] _zz_s0_countOnesLogic_4_12; - wire [1:0] _zz_s0_countOnesLogic_4_13; - reg [2:0] _zz_s0_countOnesLogic_5_9; - wire [2:0] _zz_s0_countOnesLogic_5_10; - reg [2:0] _zz_s0_countOnesLogic_5_11; - wire [2:0] _zz_s0_countOnesLogic_5_12; - wire [2:0] _zz_s0_countOnesLogic_6_9; - reg [2:0] _zz_s0_countOnesLogic_6_10; - wire [2:0] _zz_s0_countOnesLogic_6_11; - reg [2:0] _zz_s0_countOnesLogic_6_12; - wire [2:0] _zz_s0_countOnesLogic_6_13; - reg [2:0] _zz_s0_countOnesLogic_6_14; - wire [2:0] _zz_s0_countOnesLogic_6_15; - wire [0:0] _zz_s0_countOnesLogic_6_16; - wire [3:0] _zz_s0_countOnesLogic_7_9; - reg [3:0] _zz_s0_countOnesLogic_7_10; - wire [2:0] _zz_s0_countOnesLogic_7_11; - reg [3:0] _zz_s0_countOnesLogic_7_12; - wire [2:0] _zz_s0_countOnesLogic_7_13; - reg [3:0] _zz_s0_countOnesLogic_7_14; - wire [2:0] _zz_s0_countOnesLogic_7_15; - wire [1:0] _zz_s0_countOnesLogic_7_16; - wire [3:0] _zz_s0_countOnesLogic_8_9; - reg [3:0] _zz_s0_countOnesLogic_8_10; - wire [2:0] _zz_s0_countOnesLogic_8_11; - reg [3:0] _zz_s0_countOnesLogic_8_12; - wire [2:0] _zz_s0_countOnesLogic_8_13; - reg [3:0] _zz_s0_countOnesLogic_8_14; - wire [2:0] _zz_s0_countOnesLogic_8_15; - wire [3:0] _zz_s0_countOnesLogic_9_9; - reg [3:0] _zz_s0_countOnesLogic_9_10; - wire [2:0] _zz_s0_countOnesLogic_9_11; - reg [3:0] _zz_s0_countOnesLogic_9_12; - wire [2:0] _zz_s0_countOnesLogic_9_13; - wire [3:0] _zz_s0_countOnesLogic_9_14; - reg [3:0] _zz_s0_countOnesLogic_9_15; - wire [2:0] _zz_s0_countOnesLogic_9_16; - reg [3:0] _zz_s0_countOnesLogic_9_17; - wire [2:0] _zz_s0_countOnesLogic_9_18; - wire [0:0] _zz_s0_countOnesLogic_9_19; - wire [3:0] _zz_s0_countOnesLogic_10_9; - reg [3:0] _zz_s0_countOnesLogic_10_10; - wire [2:0] _zz_s0_countOnesLogic_10_11; - reg [3:0] _zz_s0_countOnesLogic_10_12; - wire [2:0] _zz_s0_countOnesLogic_10_13; - wire [3:0] _zz_s0_countOnesLogic_10_14; - reg [3:0] _zz_s0_countOnesLogic_10_15; - wire [2:0] _zz_s0_countOnesLogic_10_16; - reg [3:0] _zz_s0_countOnesLogic_10_17; - wire [2:0] _zz_s0_countOnesLogic_10_18; - wire [1:0] _zz_s0_countOnesLogic_10_19; - wire [3:0] _zz_s0_countOnesLogic_11_9; - reg [3:0] _zz_s0_countOnesLogic_11_10; - wire [2:0] _zz_s0_countOnesLogic_11_11; - reg [3:0] _zz_s0_countOnesLogic_11_12; - wire [2:0] _zz_s0_countOnesLogic_11_13; - wire [3:0] _zz_s0_countOnesLogic_11_14; - reg [3:0] _zz_s0_countOnesLogic_11_15; - wire [2:0] _zz_s0_countOnesLogic_11_16; - reg [3:0] _zz_s0_countOnesLogic_11_17; - wire [2:0] _zz_s0_countOnesLogic_11_18; - wire [3:0] _zz_s0_countOnesLogic_12_9; - wire [3:0] _zz_s0_countOnesLogic_12_10; - reg [3:0] _zz_s0_countOnesLogic_12_11; - wire [2:0] _zz_s0_countOnesLogic_12_12; - reg [3:0] _zz_s0_countOnesLogic_12_13; - wire [2:0] _zz_s0_countOnesLogic_12_14; - wire [3:0] _zz_s0_countOnesLogic_12_15; - reg [3:0] _zz_s0_countOnesLogic_12_16; - wire [2:0] _zz_s0_countOnesLogic_12_17; - reg [3:0] _zz_s0_countOnesLogic_12_18; - wire [2:0] _zz_s0_countOnesLogic_12_19; - reg [3:0] _zz_s0_countOnesLogic_12_20; - wire [2:0] _zz_s0_countOnesLogic_12_21; - wire [0:0] _zz_s0_countOnesLogic_12_22; - wire [3:0] _zz_s0_countOnesLogic_13_9; - wire [3:0] _zz_s0_countOnesLogic_13_10; - reg [3:0] _zz_s0_countOnesLogic_13_11; - wire [2:0] _zz_s0_countOnesLogic_13_12; - reg [3:0] _zz_s0_countOnesLogic_13_13; - wire [2:0] _zz_s0_countOnesLogic_13_14; - wire [3:0] _zz_s0_countOnesLogic_13_15; - reg [3:0] _zz_s0_countOnesLogic_13_16; - wire [2:0] _zz_s0_countOnesLogic_13_17; - reg [3:0] _zz_s0_countOnesLogic_13_18; - wire [2:0] _zz_s0_countOnesLogic_13_19; - reg [3:0] _zz_s0_countOnesLogic_13_20; - wire [2:0] _zz_s0_countOnesLogic_13_21; - wire [1:0] _zz_s0_countOnesLogic_13_22; - wire [3:0] _zz_s0_countOnesLogic_14_9; - wire [3:0] _zz_s0_countOnesLogic_14_10; - reg [3:0] _zz_s0_countOnesLogic_14_11; - wire [2:0] _zz_s0_countOnesLogic_14_12; - reg [3:0] _zz_s0_countOnesLogic_14_13; - wire [2:0] _zz_s0_countOnesLogic_14_14; - wire [3:0] _zz_s0_countOnesLogic_14_15; - reg [3:0] _zz_s0_countOnesLogic_14_16; - wire [2:0] _zz_s0_countOnesLogic_14_17; - reg [3:0] _zz_s0_countOnesLogic_14_18; - wire [2:0] _zz_s0_countOnesLogic_14_19; - reg [3:0] _zz_s0_countOnesLogic_14_20; - wire [2:0] _zz_s0_countOnesLogic_14_21; - wire [4:0] _zz_s0_countOnesLogic_15_8; - wire [4:0] _zz_s0_countOnesLogic_15_9; - reg [4:0] _zz_s0_countOnesLogic_15_10; - wire [2:0] _zz_s0_countOnesLogic_15_11; - reg [4:0] _zz_s0_countOnesLogic_15_12; - wire [2:0] _zz_s0_countOnesLogic_15_13; - wire [4:0] _zz_s0_countOnesLogic_15_14; - reg [4:0] _zz_s0_countOnesLogic_15_15; - wire [2:0] _zz_s0_countOnesLogic_15_16; - reg [4:0] _zz_s0_countOnesLogic_15_17; - wire [2:0] _zz_s0_countOnesLogic_15_18; - wire [4:0] _zz_s0_countOnesLogic_15_19; - reg [4:0] _zz_s0_countOnesLogic_15_20; - wire [2:0] _zz_s0_countOnesLogic_15_21; - reg [4:0] _zz_s0_countOnesLogic_15_22; - wire [2:0] _zz_s0_countOnesLogic_15_23; - wire [0:0] _zz_s0_countOnesLogic_15_24; - wire [4:0] _zz_s1_offsetNext; - wire [12:0] _zz_s1_byteCounter; - wire [3:0] _zz_s1_inputIndexes_1; - wire [3:0] _zz_s1_inputIndexes_2; - wire [3:0] _zz_s1_inputIndexes_3; - wire [3:0] _zz_s1_inputIndexes_4; - wire [3:0] _zz_s1_inputIndexes_5; - wire [3:0] _zz_s1_inputIndexes_6; - wire [3:0] _zz_s1_inputIndexes_7; - wire [0:0] _zz_s1_outputPayload_selValid_240; - wire [6:0] _zz_s1_outputPayload_selValid_241; - wire [0:0] _zz_s1_outputPayload_selValid_242; - wire [6:0] _zz_s1_outputPayload_selValid_243; - wire [0:0] _zz_s1_outputPayload_selValid_244; - wire [6:0] _zz_s1_outputPayload_selValid_245; - wire [0:0] _zz_s1_outputPayload_selValid_246; - wire [6:0] _zz_s1_outputPayload_selValid_247; - wire [0:0] _zz_s1_outputPayload_selValid_248; - wire [6:0] _zz_s1_outputPayload_selValid_249; - wire [0:0] _zz_s1_outputPayload_selValid_250; - wire [6:0] _zz_s1_outputPayload_selValid_251; - wire [0:0] _zz_s1_outputPayload_selValid_252; - wire [6:0] _zz_s1_outputPayload_selValid_253; - wire [0:0] _zz_s1_outputPayload_selValid_254; - wire [6:0] _zz_s1_outputPayload_selValid_255; - wire [0:0] _zz_s1_outputPayload_selValid_256; - wire [6:0] _zz_s1_outputPayload_selValid_257; - wire [0:0] _zz_s1_outputPayload_selValid_258; - wire [6:0] _zz_s1_outputPayload_selValid_259; - wire [0:0] _zz_s1_outputPayload_selValid_260; - wire [6:0] _zz_s1_outputPayload_selValid_261; - wire [0:0] _zz_s1_outputPayload_selValid_262; - wire [6:0] _zz_s1_outputPayload_selValid_263; - wire [0:0] _zz_s1_outputPayload_selValid_264; - wire [6:0] _zz_s1_outputPayload_selValid_265; - wire [0:0] _zz_s1_outputPayload_selValid_266; - wire [6:0] _zz_s1_outputPayload_selValid_267; - wire [0:0] _zz_s1_outputPayload_selValid_268; - wire [6:0] _zz_s1_outputPayload_selValid_269; - wire [0:0] _zz_s1_outputPayload_selValid_270; - wire [6:0] _zz_s1_outputPayload_selValid_271; - wire [12:0] _zz_when_DmaSg_l1464; - reg [7:0] _zz_s2_byteLogic_0_inputData; - reg [7:0] _zz_s2_byteLogic_1_inputData; - reg [7:0] _zz_s2_byteLogic_2_inputData; - reg [7:0] _zz_s2_byteLogic_3_inputData; - reg [7:0] _zz_s2_byteLogic_4_inputData; - reg [7:0] _zz_s2_byteLogic_5_inputData; - reg [7:0] _zz_s2_byteLogic_6_inputData; - reg [7:0] _zz_s2_byteLogic_7_inputData; - reg [7:0] _zz_s2_byteLogic_8_inputData; - reg [7:0] _zz_s2_byteLogic_9_inputData; - reg [7:0] _zz_s2_byteLogic_10_inputData; - reg [7:0] _zz_s2_byteLogic_11_inputData; - reg [7:0] _zz_s2_byteLogic_12_inputData; - reg [7:0] _zz_s2_byteLogic_13_inputData; - reg [7:0] _zz_s2_byteLogic_14_inputData; - reg [7:0] _zz_s2_byteLogic_15_inputData; - reg [3:0] _zz_io_output_usedUntil_4; - wire [3:0] _zz_io_output_usedUntil_5; - wire s0_input_valid; - wire s0_input_ready; - wire [127:0] s0_input_payload_data; - wire [15:0] s0_input_payload_mask; - reg io_input_rValid; - reg [127:0] io_input_rData_data; - reg [15:0] io_input_rData_mask; - wire when_Stream_l375; - wire _zz_s0_countOnesLogic_0; - wire _zz_s0_countOnesLogic_1; - wire _zz_s0_countOnesLogic_2; - wire _zz_s0_countOnesLogic_3; - wire _zz_s0_countOnesLogic_4; - wire _zz_s0_countOnesLogic_5; - wire _zz_s0_countOnesLogic_6; - wire _zz_s0_countOnesLogic_7; - wire _zz_s0_countOnesLogic_8; - wire _zz_s0_countOnesLogic_9; - wire _zz_s0_countOnesLogic_10; - wire _zz_s0_countOnesLogic_11; - wire _zz_s0_countOnesLogic_12; - wire _zz_s0_countOnesLogic_13; - wire _zz_s0_countOnesLogic_14; - wire [0:0] s0_countOnesLogic_0; - wire [1:0] s0_countOnesLogic_1; - wire [1:0] s0_countOnesLogic_2; - wire [2:0] _zz_s0_countOnesLogic_3_1; - wire [2:0] _zz_s0_countOnesLogic_3_2; - wire [2:0] _zz_s0_countOnesLogic_3_3; - wire [2:0] _zz_s0_countOnesLogic_3_4; - wire [2:0] _zz_s0_countOnesLogic_3_5; - wire [2:0] _zz_s0_countOnesLogic_3_6; - wire [2:0] _zz_s0_countOnesLogic_3_7; - wire [2:0] _zz_s0_countOnesLogic_3_8; - wire [2:0] s0_countOnesLogic_3; - wire [2:0] _zz_s0_countOnesLogic_4_1; - wire [2:0] _zz_s0_countOnesLogic_4_2; - wire [2:0] _zz_s0_countOnesLogic_4_3; - wire [2:0] _zz_s0_countOnesLogic_4_4; - wire [2:0] _zz_s0_countOnesLogic_4_5; - wire [2:0] _zz_s0_countOnesLogic_4_6; - wire [2:0] _zz_s0_countOnesLogic_4_7; - wire [2:0] _zz_s0_countOnesLogic_4_8; - wire [2:0] s0_countOnesLogic_4; - wire [2:0] _zz_s0_countOnesLogic_5_1; - wire [2:0] _zz_s0_countOnesLogic_5_2; - wire [2:0] _zz_s0_countOnesLogic_5_3; - wire [2:0] _zz_s0_countOnesLogic_5_4; - wire [2:0] _zz_s0_countOnesLogic_5_5; - wire [2:0] _zz_s0_countOnesLogic_5_6; - wire [2:0] _zz_s0_countOnesLogic_5_7; - wire [2:0] _zz_s0_countOnesLogic_5_8; - wire [2:0] s0_countOnesLogic_5; - wire [2:0] _zz_s0_countOnesLogic_6_1; - wire [2:0] _zz_s0_countOnesLogic_6_2; - wire [2:0] _zz_s0_countOnesLogic_6_3; - wire [2:0] _zz_s0_countOnesLogic_6_4; - wire [2:0] _zz_s0_countOnesLogic_6_5; - wire [2:0] _zz_s0_countOnesLogic_6_6; - wire [2:0] _zz_s0_countOnesLogic_6_7; - wire [2:0] _zz_s0_countOnesLogic_6_8; - wire [2:0] s0_countOnesLogic_6; - wire [3:0] _zz_s0_countOnesLogic_7_1; - wire [3:0] _zz_s0_countOnesLogic_7_2; - wire [3:0] _zz_s0_countOnesLogic_7_3; - wire [3:0] _zz_s0_countOnesLogic_7_4; - wire [3:0] _zz_s0_countOnesLogic_7_5; - wire [3:0] _zz_s0_countOnesLogic_7_6; - wire [3:0] _zz_s0_countOnesLogic_7_7; - wire [3:0] _zz_s0_countOnesLogic_7_8; - wire [3:0] s0_countOnesLogic_7; - wire [3:0] _zz_s0_countOnesLogic_8_1; - wire [3:0] _zz_s0_countOnesLogic_8_2; - wire [3:0] _zz_s0_countOnesLogic_8_3; - wire [3:0] _zz_s0_countOnesLogic_8_4; - wire [3:0] _zz_s0_countOnesLogic_8_5; - wire [3:0] _zz_s0_countOnesLogic_8_6; - wire [3:0] _zz_s0_countOnesLogic_8_7; - wire [3:0] _zz_s0_countOnesLogic_8_8; - wire [3:0] s0_countOnesLogic_8; - wire [3:0] _zz_s0_countOnesLogic_9_1; - wire [3:0] _zz_s0_countOnesLogic_9_2; - wire [3:0] _zz_s0_countOnesLogic_9_3; - wire [3:0] _zz_s0_countOnesLogic_9_4; - wire [3:0] _zz_s0_countOnesLogic_9_5; - wire [3:0] _zz_s0_countOnesLogic_9_6; - wire [3:0] _zz_s0_countOnesLogic_9_7; - wire [3:0] _zz_s0_countOnesLogic_9_8; - wire [3:0] s0_countOnesLogic_9; - wire [3:0] _zz_s0_countOnesLogic_10_1; - wire [3:0] _zz_s0_countOnesLogic_10_2; - wire [3:0] _zz_s0_countOnesLogic_10_3; - wire [3:0] _zz_s0_countOnesLogic_10_4; - wire [3:0] _zz_s0_countOnesLogic_10_5; - wire [3:0] _zz_s0_countOnesLogic_10_6; - wire [3:0] _zz_s0_countOnesLogic_10_7; - wire [3:0] _zz_s0_countOnesLogic_10_8; - wire [3:0] s0_countOnesLogic_10; - wire [3:0] _zz_s0_countOnesLogic_11_1; - wire [3:0] _zz_s0_countOnesLogic_11_2; - wire [3:0] _zz_s0_countOnesLogic_11_3; - wire [3:0] _zz_s0_countOnesLogic_11_4; - wire [3:0] _zz_s0_countOnesLogic_11_5; - wire [3:0] _zz_s0_countOnesLogic_11_6; - wire [3:0] _zz_s0_countOnesLogic_11_7; - wire [3:0] _zz_s0_countOnesLogic_11_8; - wire [3:0] s0_countOnesLogic_11; - wire [3:0] _zz_s0_countOnesLogic_12_1; - wire [3:0] _zz_s0_countOnesLogic_12_2; - wire [3:0] _zz_s0_countOnesLogic_12_3; - wire [3:0] _zz_s0_countOnesLogic_12_4; - wire [3:0] _zz_s0_countOnesLogic_12_5; - wire [3:0] _zz_s0_countOnesLogic_12_6; - wire [3:0] _zz_s0_countOnesLogic_12_7; - wire [3:0] _zz_s0_countOnesLogic_12_8; - wire [3:0] s0_countOnesLogic_12; - wire [3:0] _zz_s0_countOnesLogic_13_1; - wire [3:0] _zz_s0_countOnesLogic_13_2; - wire [3:0] _zz_s0_countOnesLogic_13_3; - wire [3:0] _zz_s0_countOnesLogic_13_4; - wire [3:0] _zz_s0_countOnesLogic_13_5; - wire [3:0] _zz_s0_countOnesLogic_13_6; - wire [3:0] _zz_s0_countOnesLogic_13_7; - wire [3:0] _zz_s0_countOnesLogic_13_8; - wire [3:0] s0_countOnesLogic_13; - wire [3:0] _zz_s0_countOnesLogic_14_1; - wire [3:0] _zz_s0_countOnesLogic_14_2; - wire [3:0] _zz_s0_countOnesLogic_14_3; - wire [3:0] _zz_s0_countOnesLogic_14_4; - wire [3:0] _zz_s0_countOnesLogic_14_5; - wire [3:0] _zz_s0_countOnesLogic_14_6; - wire [3:0] _zz_s0_countOnesLogic_14_7; - wire [3:0] _zz_s0_countOnesLogic_14_8; - wire [3:0] s0_countOnesLogic_14; - wire [4:0] _zz_s0_countOnesLogic_15; - wire [4:0] _zz_s0_countOnesLogic_15_1; - wire [4:0] _zz_s0_countOnesLogic_15_2; - wire [4:0] _zz_s0_countOnesLogic_15_3; - wire [4:0] _zz_s0_countOnesLogic_15_4; - wire [4:0] _zz_s0_countOnesLogic_15_5; - wire [4:0] _zz_s0_countOnesLogic_15_6; - wire [4:0] _zz_s0_countOnesLogic_15_7; - wire [4:0] s0_countOnesLogic_15; - wire [127:0] s0_outputPayload_cmd_data; - wire [15:0] s0_outputPayload_cmd_mask; - wire [0:0] s0_outputPayload_countOnes_0; - wire [1:0] s0_outputPayload_countOnes_1; - wire [1:0] s0_outputPayload_countOnes_2; - wire [2:0] s0_outputPayload_countOnes_3; - wire [2:0] s0_outputPayload_countOnes_4; - wire [2:0] s0_outputPayload_countOnes_5; - wire [2:0] s0_outputPayload_countOnes_6; - wire [3:0] s0_outputPayload_countOnes_7; - wire [3:0] s0_outputPayload_countOnes_8; - wire [3:0] s0_outputPayload_countOnes_9; - wire [3:0] s0_outputPayload_countOnes_10; - wire [3:0] s0_outputPayload_countOnes_11; - wire [3:0] s0_outputPayload_countOnes_12; - wire [3:0] s0_outputPayload_countOnes_13; - wire [3:0] s0_outputPayload_countOnes_14; - wire [4:0] s0_outputPayload_countOnes_15; - wire s0_output_valid; - reg s0_output_ready; - wire [127:0] s0_output_payload_cmd_data; - wire [15:0] s0_output_payload_cmd_mask; - wire [0:0] s0_output_payload_countOnes_0; - wire [1:0] s0_output_payload_countOnes_1; - wire [1:0] s0_output_payload_countOnes_2; - wire [2:0] s0_output_payload_countOnes_3; - wire [2:0] s0_output_payload_countOnes_4; - wire [2:0] s0_output_payload_countOnes_5; - wire [2:0] s0_output_payload_countOnes_6; - wire [3:0] s0_output_payload_countOnes_7; - wire [3:0] s0_output_payload_countOnes_8; - wire [3:0] s0_output_payload_countOnes_9; - wire [3:0] s0_output_payload_countOnes_10; - wire [3:0] s0_output_payload_countOnes_11; - wire [3:0] s0_output_payload_countOnes_12; - wire [3:0] s0_output_payload_countOnes_13; - wire [3:0] s0_output_payload_countOnes_14; - wire [4:0] s0_output_payload_countOnes_15; - wire s1_input_valid; - wire s1_input_ready; - wire [127:0] s1_input_payload_cmd_data; - wire [15:0] s1_input_payload_cmd_mask; - wire [0:0] s1_input_payload_countOnes_0; - wire [1:0] s1_input_payload_countOnes_1; - wire [1:0] s1_input_payload_countOnes_2; - wire [2:0] s1_input_payload_countOnes_3; - wire [2:0] s1_input_payload_countOnes_4; - wire [2:0] s1_input_payload_countOnes_5; - wire [2:0] s1_input_payload_countOnes_6; - wire [3:0] s1_input_payload_countOnes_7; - wire [3:0] s1_input_payload_countOnes_8; - wire [3:0] s1_input_payload_countOnes_9; - wire [3:0] s1_input_payload_countOnes_10; - wire [3:0] s1_input_payload_countOnes_11; - wire [3:0] s1_input_payload_countOnes_12; - wire [3:0] s1_input_payload_countOnes_13; - wire [3:0] s1_input_payload_countOnes_14; - wire [4:0] s1_input_payload_countOnes_15; - reg s0_output_rValid; - reg [127:0] s0_output_rData_cmd_data; - reg [15:0] s0_output_rData_cmd_mask; - reg [0:0] s0_output_rData_countOnes_0; - reg [1:0] s0_output_rData_countOnes_1; - reg [1:0] s0_output_rData_countOnes_2; - reg [2:0] s0_output_rData_countOnes_3; - reg [2:0] s0_output_rData_countOnes_4; - reg [2:0] s0_output_rData_countOnes_5; - reg [2:0] s0_output_rData_countOnes_6; - reg [3:0] s0_output_rData_countOnes_7; - reg [3:0] s0_output_rData_countOnes_8; - reg [3:0] s0_output_rData_countOnes_9; - reg [3:0] s0_output_rData_countOnes_10; - reg [3:0] s0_output_rData_countOnes_11; - reg [3:0] s0_output_rData_countOnes_12; - reg [3:0] s0_output_rData_countOnes_13; - reg [3:0] s0_output_rData_countOnes_14; - reg [4:0] s0_output_rData_countOnes_15; - wire when_Stream_l375_1; - reg [3:0] s1_offset; - wire [4:0] s1_offsetNext; - wire s1_input_fire; - reg [12:0] s1_byteCounter; - wire [3:0] s1_inputIndexes_0; - wire [3:0] s1_inputIndexes_1; - wire [3:0] s1_inputIndexes_2; - wire [3:0] s1_inputIndexes_3; - wire [3:0] s1_inputIndexes_4; - wire [3:0] s1_inputIndexes_5; - wire [3:0] s1_inputIndexes_6; - wire [3:0] s1_inputIndexes_7; - wire [3:0] s1_inputIndexes_8; - wire [3:0] s1_inputIndexes_9; - wire [3:0] s1_inputIndexes_10; - wire [3:0] s1_inputIndexes_11; - wire [3:0] s1_inputIndexes_12; - wire [3:0] s1_inputIndexes_13; - wire [3:0] s1_inputIndexes_14; - wire [3:0] s1_inputIndexes_15; - wire [127:0] s1_outputPayload_cmd_data; - wire [15:0] s1_outputPayload_cmd_mask; - wire [3:0] s1_outputPayload_index_0; - wire [3:0] s1_outputPayload_index_1; - wire [3:0] s1_outputPayload_index_2; - wire [3:0] s1_outputPayload_index_3; - wire [3:0] s1_outputPayload_index_4; - wire [3:0] s1_outputPayload_index_5; - wire [3:0] s1_outputPayload_index_6; - wire [3:0] s1_outputPayload_index_7; - wire [3:0] s1_outputPayload_index_8; - wire [3:0] s1_outputPayload_index_9; - wire [3:0] s1_outputPayload_index_10; - wire [3:0] s1_outputPayload_index_11; - wire [3:0] s1_outputPayload_index_12; - wire [3:0] s1_outputPayload_index_13; - wire [3:0] s1_outputPayload_index_14; - wire [3:0] s1_outputPayload_index_15; - wire s1_outputPayload_last; - wire [3:0] s1_outputPayload_sel_0; - wire [3:0] s1_outputPayload_sel_1; - wire [3:0] s1_outputPayload_sel_2; - wire [3:0] s1_outputPayload_sel_3; - wire [3:0] s1_outputPayload_sel_4; - wire [3:0] s1_outputPayload_sel_5; - wire [3:0] s1_outputPayload_sel_6; - wire [3:0] s1_outputPayload_sel_7; - wire [3:0] s1_outputPayload_sel_8; - wire [3:0] s1_outputPayload_sel_9; - wire [3:0] s1_outputPayload_sel_10; - wire [3:0] s1_outputPayload_sel_11; - wire [3:0] s1_outputPayload_sel_12; - wire [3:0] s1_outputPayload_sel_13; - wire [3:0] s1_outputPayload_sel_14; - wire [3:0] s1_outputPayload_sel_15; - reg [15:0] s1_outputPayload_selValid; - wire _zz_s1_outputPayload_selValid; - wire _zz_s1_outputPayload_selValid_1; - wire _zz_s1_outputPayload_selValid_2; - wire _zz_s1_outputPayload_selValid_3; - wire _zz_s1_outputPayload_selValid_4; - wire _zz_s1_outputPayload_selValid_5; - wire _zz_s1_outputPayload_selValid_6; - wire _zz_s1_outputPayload_selValid_7; - wire _zz_s1_outputPayload_selValid_8; - wire _zz_s1_outputPayload_selValid_9; - wire _zz_s1_outputPayload_selValid_10; - wire _zz_s1_outputPayload_selValid_11; - wire _zz_s1_outputPayload_selValid_12; - wire _zz_s1_outputPayload_selValid_13; - wire _zz_s1_outputPayload_selValid_14; - wire _zz_s1_outputPayload_sel_0; - wire _zz_s1_outputPayload_sel_0_1; - wire _zz_s1_outputPayload_sel_0_2; - wire _zz_s1_outputPayload_sel_0_3; - wire _zz_s1_outputPayload_selValid_15; - wire _zz_s1_outputPayload_selValid_16; - wire _zz_s1_outputPayload_selValid_17; - wire _zz_s1_outputPayload_selValid_18; - wire _zz_s1_outputPayload_selValid_19; - wire _zz_s1_outputPayload_selValid_20; - wire _zz_s1_outputPayload_selValid_21; - wire _zz_s1_outputPayload_selValid_22; - wire _zz_s1_outputPayload_selValid_23; - wire _zz_s1_outputPayload_selValid_24; - wire _zz_s1_outputPayload_selValid_25; - wire _zz_s1_outputPayload_selValid_26; - wire _zz_s1_outputPayload_selValid_27; - wire _zz_s1_outputPayload_selValid_28; - wire _zz_s1_outputPayload_selValid_29; - wire _zz_s1_outputPayload_sel_1; - wire _zz_s1_outputPayload_sel_1_1; - wire _zz_s1_outputPayload_sel_1_2; - wire _zz_s1_outputPayload_sel_1_3; - wire _zz_s1_outputPayload_selValid_30; - wire _zz_s1_outputPayload_selValid_31; - wire _zz_s1_outputPayload_selValid_32; - wire _zz_s1_outputPayload_selValid_33; - wire _zz_s1_outputPayload_selValid_34; - wire _zz_s1_outputPayload_selValid_35; - wire _zz_s1_outputPayload_selValid_36; - wire _zz_s1_outputPayload_selValid_37; - wire _zz_s1_outputPayload_selValid_38; - wire _zz_s1_outputPayload_selValid_39; - wire _zz_s1_outputPayload_selValid_40; - wire _zz_s1_outputPayload_selValid_41; - wire _zz_s1_outputPayload_selValid_42; - wire _zz_s1_outputPayload_selValid_43; - wire _zz_s1_outputPayload_selValid_44; - wire _zz_s1_outputPayload_sel_2; - wire _zz_s1_outputPayload_sel_2_1; - wire _zz_s1_outputPayload_sel_2_2; - wire _zz_s1_outputPayload_sel_2_3; - wire _zz_s1_outputPayload_selValid_45; - wire _zz_s1_outputPayload_selValid_46; - wire _zz_s1_outputPayload_selValid_47; - wire _zz_s1_outputPayload_selValid_48; - wire _zz_s1_outputPayload_selValid_49; - wire _zz_s1_outputPayload_selValid_50; - wire _zz_s1_outputPayload_selValid_51; - wire _zz_s1_outputPayload_selValid_52; - wire _zz_s1_outputPayload_selValid_53; - wire _zz_s1_outputPayload_selValid_54; - wire _zz_s1_outputPayload_selValid_55; - wire _zz_s1_outputPayload_selValid_56; - wire _zz_s1_outputPayload_selValid_57; - wire _zz_s1_outputPayload_selValid_58; - wire _zz_s1_outputPayload_selValid_59; - wire _zz_s1_outputPayload_sel_3; - wire _zz_s1_outputPayload_sel_3_1; - wire _zz_s1_outputPayload_sel_3_2; - wire _zz_s1_outputPayload_sel_3_3; - wire _zz_s1_outputPayload_selValid_60; - wire _zz_s1_outputPayload_selValid_61; - wire _zz_s1_outputPayload_selValid_62; - wire _zz_s1_outputPayload_selValid_63; - wire _zz_s1_outputPayload_selValid_64; - wire _zz_s1_outputPayload_selValid_65; - wire _zz_s1_outputPayload_selValid_66; - wire _zz_s1_outputPayload_selValid_67; - wire _zz_s1_outputPayload_selValid_68; - wire _zz_s1_outputPayload_selValid_69; - wire _zz_s1_outputPayload_selValid_70; - wire _zz_s1_outputPayload_selValid_71; - wire _zz_s1_outputPayload_selValid_72; - wire _zz_s1_outputPayload_selValid_73; - wire _zz_s1_outputPayload_selValid_74; - wire _zz_s1_outputPayload_sel_4; - wire _zz_s1_outputPayload_sel_4_1; - wire _zz_s1_outputPayload_sel_4_2; - wire _zz_s1_outputPayload_sel_4_3; - wire _zz_s1_outputPayload_selValid_75; - wire _zz_s1_outputPayload_selValid_76; - wire _zz_s1_outputPayload_selValid_77; - wire _zz_s1_outputPayload_selValid_78; - wire _zz_s1_outputPayload_selValid_79; - wire _zz_s1_outputPayload_selValid_80; - wire _zz_s1_outputPayload_selValid_81; - wire _zz_s1_outputPayload_selValid_82; - wire _zz_s1_outputPayload_selValid_83; - wire _zz_s1_outputPayload_selValid_84; - wire _zz_s1_outputPayload_selValid_85; - wire _zz_s1_outputPayload_selValid_86; - wire _zz_s1_outputPayload_selValid_87; - wire _zz_s1_outputPayload_selValid_88; - wire _zz_s1_outputPayload_selValid_89; - wire _zz_s1_outputPayload_sel_5; - wire _zz_s1_outputPayload_sel_5_1; - wire _zz_s1_outputPayload_sel_5_2; - wire _zz_s1_outputPayload_sel_5_3; - wire _zz_s1_outputPayload_selValid_90; - wire _zz_s1_outputPayload_selValid_91; - wire _zz_s1_outputPayload_selValid_92; - wire _zz_s1_outputPayload_selValid_93; - wire _zz_s1_outputPayload_selValid_94; - wire _zz_s1_outputPayload_selValid_95; - wire _zz_s1_outputPayload_selValid_96; - wire _zz_s1_outputPayload_selValid_97; - wire _zz_s1_outputPayload_selValid_98; - wire _zz_s1_outputPayload_selValid_99; - wire _zz_s1_outputPayload_selValid_100; - wire _zz_s1_outputPayload_selValid_101; - wire _zz_s1_outputPayload_selValid_102; - wire _zz_s1_outputPayload_selValid_103; - wire _zz_s1_outputPayload_selValid_104; - wire _zz_s1_outputPayload_sel_6; - wire _zz_s1_outputPayload_sel_6_1; - wire _zz_s1_outputPayload_sel_6_2; - wire _zz_s1_outputPayload_sel_6_3; - wire _zz_s1_outputPayload_selValid_105; - wire _zz_s1_outputPayload_selValid_106; - wire _zz_s1_outputPayload_selValid_107; - wire _zz_s1_outputPayload_selValid_108; - wire _zz_s1_outputPayload_selValid_109; - wire _zz_s1_outputPayload_selValid_110; - wire _zz_s1_outputPayload_selValid_111; - wire _zz_s1_outputPayload_selValid_112; - wire _zz_s1_outputPayload_selValid_113; - wire _zz_s1_outputPayload_selValid_114; - wire _zz_s1_outputPayload_selValid_115; - wire _zz_s1_outputPayload_selValid_116; - wire _zz_s1_outputPayload_selValid_117; - wire _zz_s1_outputPayload_selValid_118; - wire _zz_s1_outputPayload_selValid_119; - wire _zz_s1_outputPayload_sel_7; - wire _zz_s1_outputPayload_sel_7_1; - wire _zz_s1_outputPayload_sel_7_2; - wire _zz_s1_outputPayload_sel_7_3; - wire _zz_s1_outputPayload_selValid_120; - wire _zz_s1_outputPayload_selValid_121; - wire _zz_s1_outputPayload_selValid_122; - wire _zz_s1_outputPayload_selValid_123; - wire _zz_s1_outputPayload_selValid_124; - wire _zz_s1_outputPayload_selValid_125; - wire _zz_s1_outputPayload_selValid_126; - wire _zz_s1_outputPayload_selValid_127; - wire _zz_s1_outputPayload_selValid_128; - wire _zz_s1_outputPayload_selValid_129; - wire _zz_s1_outputPayload_selValid_130; - wire _zz_s1_outputPayload_selValid_131; - wire _zz_s1_outputPayload_selValid_132; - wire _zz_s1_outputPayload_selValid_133; - wire _zz_s1_outputPayload_selValid_134; - wire _zz_s1_outputPayload_sel_8; - wire _zz_s1_outputPayload_sel_8_1; - wire _zz_s1_outputPayload_sel_8_2; - wire _zz_s1_outputPayload_sel_8_3; - wire _zz_s1_outputPayload_selValid_135; - wire _zz_s1_outputPayload_selValid_136; - wire _zz_s1_outputPayload_selValid_137; - wire _zz_s1_outputPayload_selValid_138; - wire _zz_s1_outputPayload_selValid_139; - wire _zz_s1_outputPayload_selValid_140; - wire _zz_s1_outputPayload_selValid_141; - wire _zz_s1_outputPayload_selValid_142; - wire _zz_s1_outputPayload_selValid_143; - wire _zz_s1_outputPayload_selValid_144; - wire _zz_s1_outputPayload_selValid_145; - wire _zz_s1_outputPayload_selValid_146; - wire _zz_s1_outputPayload_selValid_147; - wire _zz_s1_outputPayload_selValid_148; - wire _zz_s1_outputPayload_selValid_149; - wire _zz_s1_outputPayload_sel_9; - wire _zz_s1_outputPayload_sel_9_1; - wire _zz_s1_outputPayload_sel_9_2; - wire _zz_s1_outputPayload_sel_9_3; - wire _zz_s1_outputPayload_selValid_150; - wire _zz_s1_outputPayload_selValid_151; - wire _zz_s1_outputPayload_selValid_152; - wire _zz_s1_outputPayload_selValid_153; - wire _zz_s1_outputPayload_selValid_154; - wire _zz_s1_outputPayload_selValid_155; - wire _zz_s1_outputPayload_selValid_156; - wire _zz_s1_outputPayload_selValid_157; - wire _zz_s1_outputPayload_selValid_158; - wire _zz_s1_outputPayload_selValid_159; - wire _zz_s1_outputPayload_selValid_160; - wire _zz_s1_outputPayload_selValid_161; - wire _zz_s1_outputPayload_selValid_162; - wire _zz_s1_outputPayload_selValid_163; - wire _zz_s1_outputPayload_selValid_164; - wire _zz_s1_outputPayload_sel_10; - wire _zz_s1_outputPayload_sel_10_1; - wire _zz_s1_outputPayload_sel_10_2; - wire _zz_s1_outputPayload_sel_10_3; - wire _zz_s1_outputPayload_selValid_165; - wire _zz_s1_outputPayload_selValid_166; - wire _zz_s1_outputPayload_selValid_167; - wire _zz_s1_outputPayload_selValid_168; - wire _zz_s1_outputPayload_selValid_169; - wire _zz_s1_outputPayload_selValid_170; - wire _zz_s1_outputPayload_selValid_171; - wire _zz_s1_outputPayload_selValid_172; - wire _zz_s1_outputPayload_selValid_173; - wire _zz_s1_outputPayload_selValid_174; - wire _zz_s1_outputPayload_selValid_175; - wire _zz_s1_outputPayload_selValid_176; - wire _zz_s1_outputPayload_selValid_177; - wire _zz_s1_outputPayload_selValid_178; - wire _zz_s1_outputPayload_selValid_179; - wire _zz_s1_outputPayload_sel_11; - wire _zz_s1_outputPayload_sel_11_1; - wire _zz_s1_outputPayload_sel_11_2; - wire _zz_s1_outputPayload_sel_11_3; - wire _zz_s1_outputPayload_selValid_180; - wire _zz_s1_outputPayload_selValid_181; - wire _zz_s1_outputPayload_selValid_182; - wire _zz_s1_outputPayload_selValid_183; - wire _zz_s1_outputPayload_selValid_184; - wire _zz_s1_outputPayload_selValid_185; - wire _zz_s1_outputPayload_selValid_186; - wire _zz_s1_outputPayload_selValid_187; - wire _zz_s1_outputPayload_selValid_188; - wire _zz_s1_outputPayload_selValid_189; - wire _zz_s1_outputPayload_selValid_190; - wire _zz_s1_outputPayload_selValid_191; - wire _zz_s1_outputPayload_selValid_192; - wire _zz_s1_outputPayload_selValid_193; - wire _zz_s1_outputPayload_selValid_194; - wire _zz_s1_outputPayload_sel_12; - wire _zz_s1_outputPayload_sel_12_1; - wire _zz_s1_outputPayload_sel_12_2; - wire _zz_s1_outputPayload_sel_12_3; - wire _zz_s1_outputPayload_selValid_195; - wire _zz_s1_outputPayload_selValid_196; - wire _zz_s1_outputPayload_selValid_197; - wire _zz_s1_outputPayload_selValid_198; - wire _zz_s1_outputPayload_selValid_199; - wire _zz_s1_outputPayload_selValid_200; - wire _zz_s1_outputPayload_selValid_201; - wire _zz_s1_outputPayload_selValid_202; - wire _zz_s1_outputPayload_selValid_203; - wire _zz_s1_outputPayload_selValid_204; - wire _zz_s1_outputPayload_selValid_205; - wire _zz_s1_outputPayload_selValid_206; - wire _zz_s1_outputPayload_selValid_207; - wire _zz_s1_outputPayload_selValid_208; - wire _zz_s1_outputPayload_selValid_209; - wire _zz_s1_outputPayload_sel_13; - wire _zz_s1_outputPayload_sel_13_1; - wire _zz_s1_outputPayload_sel_13_2; - wire _zz_s1_outputPayload_sel_13_3; - wire _zz_s1_outputPayload_selValid_210; - wire _zz_s1_outputPayload_selValid_211; - wire _zz_s1_outputPayload_selValid_212; - wire _zz_s1_outputPayload_selValid_213; - wire _zz_s1_outputPayload_selValid_214; - wire _zz_s1_outputPayload_selValid_215; - wire _zz_s1_outputPayload_selValid_216; - wire _zz_s1_outputPayload_selValid_217; - wire _zz_s1_outputPayload_selValid_218; - wire _zz_s1_outputPayload_selValid_219; - wire _zz_s1_outputPayload_selValid_220; - wire _zz_s1_outputPayload_selValid_221; - wire _zz_s1_outputPayload_selValid_222; - wire _zz_s1_outputPayload_selValid_223; - wire _zz_s1_outputPayload_selValid_224; - wire _zz_s1_outputPayload_sel_14; - wire _zz_s1_outputPayload_sel_14_1; - wire _zz_s1_outputPayload_sel_14_2; - wire _zz_s1_outputPayload_sel_14_3; - wire _zz_s1_outputPayload_selValid_225; - wire _zz_s1_outputPayload_selValid_226; - wire _zz_s1_outputPayload_selValid_227; - wire _zz_s1_outputPayload_selValid_228; - wire _zz_s1_outputPayload_selValid_229; - wire _zz_s1_outputPayload_selValid_230; - wire _zz_s1_outputPayload_selValid_231; - wire _zz_s1_outputPayload_selValid_232; - wire _zz_s1_outputPayload_selValid_233; - wire _zz_s1_outputPayload_selValid_234; - wire _zz_s1_outputPayload_selValid_235; - wire _zz_s1_outputPayload_selValid_236; - wire _zz_s1_outputPayload_selValid_237; - wire _zz_s1_outputPayload_selValid_238; - wire _zz_s1_outputPayload_selValid_239; - wire _zz_s1_outputPayload_sel_15; - wire _zz_s1_outputPayload_sel_15_1; - wire _zz_s1_outputPayload_sel_15_2; - wire _zz_s1_outputPayload_sel_15_3; - wire s1_output_valid; - reg s1_output_ready; - wire [127:0] s1_output_payload_cmd_data; - wire [15:0] s1_output_payload_cmd_mask; - wire [3:0] s1_output_payload_index_0; - wire [3:0] s1_output_payload_index_1; - wire [3:0] s1_output_payload_index_2; - wire [3:0] s1_output_payload_index_3; - wire [3:0] s1_output_payload_index_4; - wire [3:0] s1_output_payload_index_5; - wire [3:0] s1_output_payload_index_6; - wire [3:0] s1_output_payload_index_7; - wire [3:0] s1_output_payload_index_8; - wire [3:0] s1_output_payload_index_9; - wire [3:0] s1_output_payload_index_10; - wire [3:0] s1_output_payload_index_11; - wire [3:0] s1_output_payload_index_12; - wire [3:0] s1_output_payload_index_13; - wire [3:0] s1_output_payload_index_14; - wire [3:0] s1_output_payload_index_15; - wire s1_output_payload_last; - wire [3:0] s1_output_payload_sel_0; - wire [3:0] s1_output_payload_sel_1; - wire [3:0] s1_output_payload_sel_2; - wire [3:0] s1_output_payload_sel_3; - wire [3:0] s1_output_payload_sel_4; - wire [3:0] s1_output_payload_sel_5; - wire [3:0] s1_output_payload_sel_6; - wire [3:0] s1_output_payload_sel_7; - wire [3:0] s1_output_payload_sel_8; - wire [3:0] s1_output_payload_sel_9; - wire [3:0] s1_output_payload_sel_10; - wire [3:0] s1_output_payload_sel_11; - wire [3:0] s1_output_payload_sel_12; - wire [3:0] s1_output_payload_sel_13; - wire [3:0] s1_output_payload_sel_14; - wire [3:0] s1_output_payload_sel_15; - wire [15:0] s1_output_payload_selValid; - wire s2_input_valid; - reg s2_input_ready; - wire [127:0] s2_input_payload_cmd_data; - wire [15:0] s2_input_payload_cmd_mask; - wire [3:0] s2_input_payload_index_0; - wire [3:0] s2_input_payload_index_1; - wire [3:0] s2_input_payload_index_2; - wire [3:0] s2_input_payload_index_3; - wire [3:0] s2_input_payload_index_4; - wire [3:0] s2_input_payload_index_5; - wire [3:0] s2_input_payload_index_6; - wire [3:0] s2_input_payload_index_7; - wire [3:0] s2_input_payload_index_8; - wire [3:0] s2_input_payload_index_9; - wire [3:0] s2_input_payload_index_10; - wire [3:0] s2_input_payload_index_11; - wire [3:0] s2_input_payload_index_12; - wire [3:0] s2_input_payload_index_13; - wire [3:0] s2_input_payload_index_14; - wire [3:0] s2_input_payload_index_15; - wire s2_input_payload_last; - wire [3:0] s2_input_payload_sel_0; - wire [3:0] s2_input_payload_sel_1; - wire [3:0] s2_input_payload_sel_2; - wire [3:0] s2_input_payload_sel_3; - wire [3:0] s2_input_payload_sel_4; - wire [3:0] s2_input_payload_sel_5; - wire [3:0] s2_input_payload_sel_6; - wire [3:0] s2_input_payload_sel_7; - wire [3:0] s2_input_payload_sel_8; - wire [3:0] s2_input_payload_sel_9; - wire [3:0] s2_input_payload_sel_10; - wire [3:0] s2_input_payload_sel_11; - wire [3:0] s2_input_payload_sel_12; - wire [3:0] s2_input_payload_sel_13; - wire [3:0] s2_input_payload_sel_14; - wire [3:0] s2_input_payload_sel_15; - wire [15:0] s2_input_payload_selValid; - reg s1_output_rValid; - reg [127:0] s1_output_rData_cmd_data; - reg [15:0] s1_output_rData_cmd_mask; - reg [3:0] s1_output_rData_index_0; - reg [3:0] s1_output_rData_index_1; - reg [3:0] s1_output_rData_index_2; - reg [3:0] s1_output_rData_index_3; - reg [3:0] s1_output_rData_index_4; - reg [3:0] s1_output_rData_index_5; - reg [3:0] s1_output_rData_index_6; - reg [3:0] s1_output_rData_index_7; - reg [3:0] s1_output_rData_index_8; - reg [3:0] s1_output_rData_index_9; - reg [3:0] s1_output_rData_index_10; - reg [3:0] s1_output_rData_index_11; - reg [3:0] s1_output_rData_index_12; - reg [3:0] s1_output_rData_index_13; - reg [3:0] s1_output_rData_index_14; - reg [3:0] s1_output_rData_index_15; - reg s1_output_rData_last; - reg [3:0] s1_output_rData_sel_0; - reg [3:0] s1_output_rData_sel_1; - reg [3:0] s1_output_rData_sel_2; - reg [3:0] s1_output_rData_sel_3; - reg [3:0] s1_output_rData_sel_4; - reg [3:0] s1_output_rData_sel_5; - reg [3:0] s1_output_rData_sel_6; - reg [3:0] s1_output_rData_sel_7; - reg [3:0] s1_output_rData_sel_8; - reg [3:0] s1_output_rData_sel_9; - reg [3:0] s1_output_rData_sel_10; - reg [3:0] s1_output_rData_sel_11; - reg [3:0] s1_output_rData_sel_12; - reg [3:0] s1_output_rData_sel_13; - reg [3:0] s1_output_rData_sel_14; - reg [3:0] s1_output_rData_sel_15; - reg [15:0] s1_output_rData_selValid; - wire when_Stream_l375_2; - wire when_DmaSg_l1464; - wire s2_input_fire; - wire [7:0] s2_inputDataBytes_0; - wire [7:0] s2_inputDataBytes_1; - wire [7:0] s2_inputDataBytes_2; - wire [7:0] s2_inputDataBytes_3; - wire [7:0] s2_inputDataBytes_4; - wire [7:0] s2_inputDataBytes_5; - wire [7:0] s2_inputDataBytes_6; - wire [7:0] s2_inputDataBytes_7; - wire [7:0] s2_inputDataBytes_8; - wire [7:0] s2_inputDataBytes_9; - wire [7:0] s2_inputDataBytes_10; - wire [7:0] s2_inputDataBytes_11; - wire [7:0] s2_inputDataBytes_12; - wire [7:0] s2_inputDataBytes_13; - wire [7:0] s2_inputDataBytes_14; - wire [7:0] s2_inputDataBytes_15; - reg s2_byteLogic_0_buffer_valid; - reg [7:0] s2_byteLogic_0_buffer_data; - wire s2_byteLogic_0_lastUsed; - wire s2_byteLogic_0_inputMask; - wire [7:0] s2_byteLogic_0_inputData; - wire s2_byteLogic_0_outputMask; - wire [7:0] s2_byteLogic_0_outputData; - wire when_DmaSg_l1493; - reg s2_byteLogic_1_buffer_valid; - reg [7:0] s2_byteLogic_1_buffer_data; - wire s2_byteLogic_1_lastUsed; - wire s2_byteLogic_1_inputMask; - wire [7:0] s2_byteLogic_1_inputData; - wire s2_byteLogic_1_outputMask; - wire [7:0] s2_byteLogic_1_outputData; - wire when_DmaSg_l1493_1; - reg s2_byteLogic_2_buffer_valid; - reg [7:0] s2_byteLogic_2_buffer_data; - wire s2_byteLogic_2_lastUsed; - wire s2_byteLogic_2_inputMask; - wire [7:0] s2_byteLogic_2_inputData; - wire s2_byteLogic_2_outputMask; - wire [7:0] s2_byteLogic_2_outputData; - wire when_DmaSg_l1493_2; - reg s2_byteLogic_3_buffer_valid; - reg [7:0] s2_byteLogic_3_buffer_data; - wire s2_byteLogic_3_lastUsed; - wire s2_byteLogic_3_inputMask; - wire [7:0] s2_byteLogic_3_inputData; - wire s2_byteLogic_3_outputMask; - wire [7:0] s2_byteLogic_3_outputData; - wire when_DmaSg_l1493_3; - reg s2_byteLogic_4_buffer_valid; - reg [7:0] s2_byteLogic_4_buffer_data; - wire s2_byteLogic_4_lastUsed; - wire s2_byteLogic_4_inputMask; - wire [7:0] s2_byteLogic_4_inputData; - wire s2_byteLogic_4_outputMask; - wire [7:0] s2_byteLogic_4_outputData; - wire when_DmaSg_l1493_4; - reg s2_byteLogic_5_buffer_valid; - reg [7:0] s2_byteLogic_5_buffer_data; - wire s2_byteLogic_5_lastUsed; - wire s2_byteLogic_5_inputMask; - wire [7:0] s2_byteLogic_5_inputData; - wire s2_byteLogic_5_outputMask; - wire [7:0] s2_byteLogic_5_outputData; - wire when_DmaSg_l1493_5; - reg s2_byteLogic_6_buffer_valid; - reg [7:0] s2_byteLogic_6_buffer_data; - wire s2_byteLogic_6_lastUsed; - wire s2_byteLogic_6_inputMask; - wire [7:0] s2_byteLogic_6_inputData; - wire s2_byteLogic_6_outputMask; - wire [7:0] s2_byteLogic_6_outputData; - wire when_DmaSg_l1493_6; - reg s2_byteLogic_7_buffer_valid; - reg [7:0] s2_byteLogic_7_buffer_data; - wire s2_byteLogic_7_lastUsed; - wire s2_byteLogic_7_inputMask; - wire [7:0] s2_byteLogic_7_inputData; - wire s2_byteLogic_7_outputMask; - wire [7:0] s2_byteLogic_7_outputData; - wire when_DmaSg_l1493_7; - reg s2_byteLogic_8_buffer_valid; - reg [7:0] s2_byteLogic_8_buffer_data; - wire s2_byteLogic_8_lastUsed; - wire s2_byteLogic_8_inputMask; - wire [7:0] s2_byteLogic_8_inputData; - wire s2_byteLogic_8_outputMask; - wire [7:0] s2_byteLogic_8_outputData; - wire when_DmaSg_l1493_8; - reg s2_byteLogic_9_buffer_valid; - reg [7:0] s2_byteLogic_9_buffer_data; - wire s2_byteLogic_9_lastUsed; - wire s2_byteLogic_9_inputMask; - wire [7:0] s2_byteLogic_9_inputData; - wire s2_byteLogic_9_outputMask; - wire [7:0] s2_byteLogic_9_outputData; - wire when_DmaSg_l1493_9; - reg s2_byteLogic_10_buffer_valid; - reg [7:0] s2_byteLogic_10_buffer_data; - wire s2_byteLogic_10_lastUsed; - wire s2_byteLogic_10_inputMask; - wire [7:0] s2_byteLogic_10_inputData; - wire s2_byteLogic_10_outputMask; - wire [7:0] s2_byteLogic_10_outputData; - wire when_DmaSg_l1493_10; - reg s2_byteLogic_11_buffer_valid; - reg [7:0] s2_byteLogic_11_buffer_data; - wire s2_byteLogic_11_lastUsed; - wire s2_byteLogic_11_inputMask; - wire [7:0] s2_byteLogic_11_inputData; - wire s2_byteLogic_11_outputMask; - wire [7:0] s2_byteLogic_11_outputData; - wire when_DmaSg_l1493_11; - reg s2_byteLogic_12_buffer_valid; - reg [7:0] s2_byteLogic_12_buffer_data; - wire s2_byteLogic_12_lastUsed; - wire s2_byteLogic_12_inputMask; - wire [7:0] s2_byteLogic_12_inputData; - wire s2_byteLogic_12_outputMask; - wire [7:0] s2_byteLogic_12_outputData; - wire when_DmaSg_l1493_12; - reg s2_byteLogic_13_buffer_valid; - reg [7:0] s2_byteLogic_13_buffer_data; - wire s2_byteLogic_13_lastUsed; - wire s2_byteLogic_13_inputMask; - wire [7:0] s2_byteLogic_13_inputData; - wire s2_byteLogic_13_outputMask; - wire [7:0] s2_byteLogic_13_outputData; - wire when_DmaSg_l1493_13; - reg s2_byteLogic_14_buffer_valid; - reg [7:0] s2_byteLogic_14_buffer_data; - wire s2_byteLogic_14_lastUsed; - wire s2_byteLogic_14_inputMask; - wire [7:0] s2_byteLogic_14_inputData; - wire s2_byteLogic_14_outputMask; - wire [7:0] s2_byteLogic_14_outputData; - wire when_DmaSg_l1493_14; - reg s2_byteLogic_15_buffer_valid; - reg [7:0] s2_byteLogic_15_buffer_data; - wire s2_byteLogic_15_lastUsed; - wire s2_byteLogic_15_inputMask; - wire [7:0] s2_byteLogic_15_inputData; - wire s2_byteLogic_15_outputMask; - wire [7:0] s2_byteLogic_15_outputData; - wire when_DmaSg_l1493_15; - wire _zz_io_output_usedUntil; - wire _zz_io_output_usedUntil_1; - wire _zz_io_output_usedUntil_2; - wire _zz_io_output_usedUntil_3; - - assign _zz_s0_countOnesLogic_3_13 = _zz_s0_countOnesLogic_3; - assign _zz_s0_countOnesLogic_3_12 = {2'd0, _zz_s0_countOnesLogic_3_13}; - assign _zz_s0_countOnesLogic_4_13 = {_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}; - assign _zz_s0_countOnesLogic_4_12 = {1'd0, _zz_s0_countOnesLogic_4_13}; - assign _zz_s0_countOnesLogic_6_9 = (_zz_s0_countOnesLogic_6_10 + _zz_s0_countOnesLogic_6_12); - assign _zz_s0_countOnesLogic_6_16 = _zz_s0_countOnesLogic_6; - assign _zz_s0_countOnesLogic_6_15 = {2'd0, _zz_s0_countOnesLogic_6_16}; - assign _zz_s0_countOnesLogic_7_9 = (_zz_s0_countOnesLogic_7_10 + _zz_s0_countOnesLogic_7_12); - assign _zz_s0_countOnesLogic_7_16 = {_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}; - assign _zz_s0_countOnesLogic_7_15 = {1'd0, _zz_s0_countOnesLogic_7_16}; - assign _zz_s0_countOnesLogic_8_9 = (_zz_s0_countOnesLogic_8_10 + _zz_s0_countOnesLogic_8_12); - assign _zz_s0_countOnesLogic_9_9 = (_zz_s0_countOnesLogic_9_10 + _zz_s0_countOnesLogic_9_12); - assign _zz_s0_countOnesLogic_9_14 = (_zz_s0_countOnesLogic_9_15 + _zz_s0_countOnesLogic_9_17); - assign _zz_s0_countOnesLogic_9_19 = _zz_s0_countOnesLogic_9; - assign _zz_s0_countOnesLogic_9_18 = {2'd0, _zz_s0_countOnesLogic_9_19}; - assign _zz_s0_countOnesLogic_10_9 = (_zz_s0_countOnesLogic_10_10 + _zz_s0_countOnesLogic_10_12); - assign _zz_s0_countOnesLogic_10_14 = (_zz_s0_countOnesLogic_10_15 + _zz_s0_countOnesLogic_10_17); - assign _zz_s0_countOnesLogic_10_19 = {_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}; - assign _zz_s0_countOnesLogic_10_18 = {1'd0, _zz_s0_countOnesLogic_10_19}; - assign _zz_s0_countOnesLogic_11_9 = (_zz_s0_countOnesLogic_11_10 + _zz_s0_countOnesLogic_11_12); - assign _zz_s0_countOnesLogic_11_14 = (_zz_s0_countOnesLogic_11_15 + _zz_s0_countOnesLogic_11_17); - assign _zz_s0_countOnesLogic_12_9 = (_zz_s0_countOnesLogic_12_10 + _zz_s0_countOnesLogic_12_15); - assign _zz_s0_countOnesLogic_12_10 = (_zz_s0_countOnesLogic_12_11 + _zz_s0_countOnesLogic_12_13); - assign _zz_s0_countOnesLogic_12_15 = (_zz_s0_countOnesLogic_12_16 + _zz_s0_countOnesLogic_12_18); - assign _zz_s0_countOnesLogic_12_22 = _zz_s0_countOnesLogic_12; - assign _zz_s0_countOnesLogic_12_21 = {2'd0, _zz_s0_countOnesLogic_12_22}; - assign _zz_s0_countOnesLogic_13_9 = (_zz_s0_countOnesLogic_13_10 + _zz_s0_countOnesLogic_13_15); - assign _zz_s0_countOnesLogic_13_10 = (_zz_s0_countOnesLogic_13_11 + _zz_s0_countOnesLogic_13_13); - assign _zz_s0_countOnesLogic_13_15 = (_zz_s0_countOnesLogic_13_16 + _zz_s0_countOnesLogic_13_18); - assign _zz_s0_countOnesLogic_13_22 = {_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}; - assign _zz_s0_countOnesLogic_13_21 = {1'd0, _zz_s0_countOnesLogic_13_22}; - assign _zz_s0_countOnesLogic_14_9 = (_zz_s0_countOnesLogic_14_10 + _zz_s0_countOnesLogic_14_15); - assign _zz_s0_countOnesLogic_14_10 = (_zz_s0_countOnesLogic_14_11 + _zz_s0_countOnesLogic_14_13); - assign _zz_s0_countOnesLogic_14_15 = (_zz_s0_countOnesLogic_14_16 + _zz_s0_countOnesLogic_14_18); - assign _zz_s0_countOnesLogic_15_8 = (_zz_s0_countOnesLogic_15_9 + _zz_s0_countOnesLogic_15_14); - assign _zz_s0_countOnesLogic_15_9 = (_zz_s0_countOnesLogic_15_10 + _zz_s0_countOnesLogic_15_12); - assign _zz_s0_countOnesLogic_15_14 = (_zz_s0_countOnesLogic_15_15 + _zz_s0_countOnesLogic_15_17); - assign _zz_s0_countOnesLogic_15_19 = (_zz_s0_countOnesLogic_15_20 + _zz_s0_countOnesLogic_15_22); - assign _zz_s0_countOnesLogic_15_24 = s0_input_payload_mask[15]; - assign _zz_s0_countOnesLogic_15_23 = {2'd0, _zz_s0_countOnesLogic_15_24}; - assign _zz_s1_offsetNext = {1'd0, s1_offset}; - assign _zz_s1_byteCounter = {8'd0, s1_input_payload_countOnes_15}; - assign _zz_s1_inputIndexes_1 = {3'd0, s1_input_payload_countOnes_0}; - assign _zz_s1_inputIndexes_2 = {2'd0, s1_input_payload_countOnes_1}; - assign _zz_s1_inputIndexes_3 = {2'd0, s1_input_payload_countOnes_2}; - assign _zz_s1_inputIndexes_4 = {1'd0, s1_input_payload_countOnes_3}; - assign _zz_s1_inputIndexes_5 = {1'd0, s1_input_payload_countOnes_4}; - assign _zz_s1_inputIndexes_6 = {1'd0, s1_input_payload_countOnes_5}; - assign _zz_s1_inputIndexes_7 = {1'd0, s1_input_payload_countOnes_6}; - assign _zz_when_DmaSg_l1464 = {1'd0, io_burstLength}; - assign _zz_s0_countOnesLogic_0_2 = _zz_s0_countOnesLogic_0; - assign _zz_s0_countOnesLogic_1_2 = {_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}; - assign _zz_s0_countOnesLogic_2_2 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_3_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_4_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_5_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_5_12 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_6_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_6_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_7_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_7_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_8_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_8_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_8_15 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_9_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_9_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_9_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_10_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_10_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_10_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_11_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_11_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_11_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_11_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_12_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_12_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_12_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_12_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_13_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_13_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_13_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_13_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_14_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_14_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_14_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_14_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_14_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; - assign _zz_s0_countOnesLogic_15_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_15_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_15_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_15_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_15_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; - assign _zz_io_output_usedUntil_5 = {_zz_io_output_usedUntil_3,{_zz_io_output_usedUntil_2,{_zz_io_output_usedUntil_1,_zz_io_output_usedUntil}}}; - assign _zz_s1_outputPayload_selValid_240 = _zz_s1_outputPayload_selValid_6; - assign _zz_s1_outputPayload_selValid_241 = {_zz_s1_outputPayload_selValid_5,{_zz_s1_outputPayload_selValid_4,{_zz_s1_outputPayload_selValid_3,{_zz_s1_outputPayload_selValid_2,{_zz_s1_outputPayload_selValid_1,{_zz_s1_outputPayload_selValid,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0000))}}}}}}; - assign _zz_s1_outputPayload_selValid_242 = _zz_s1_outputPayload_selValid_21; - assign _zz_s1_outputPayload_selValid_243 = {_zz_s1_outputPayload_selValid_20,{_zz_s1_outputPayload_selValid_19,{_zz_s1_outputPayload_selValid_18,{_zz_s1_outputPayload_selValid_17,{_zz_s1_outputPayload_selValid_16,{_zz_s1_outputPayload_selValid_15,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0001))}}}}}}; - assign _zz_s1_outputPayload_selValid_244 = _zz_s1_outputPayload_selValid_36; - assign _zz_s1_outputPayload_selValid_245 = {_zz_s1_outputPayload_selValid_35,{_zz_s1_outputPayload_selValid_34,{_zz_s1_outputPayload_selValid_33,{_zz_s1_outputPayload_selValid_32,{_zz_s1_outputPayload_selValid_31,{_zz_s1_outputPayload_selValid_30,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0010))}}}}}}; - assign _zz_s1_outputPayload_selValid_246 = _zz_s1_outputPayload_selValid_51; - assign _zz_s1_outputPayload_selValid_247 = {_zz_s1_outputPayload_selValid_50,{_zz_s1_outputPayload_selValid_49,{_zz_s1_outputPayload_selValid_48,{_zz_s1_outputPayload_selValid_47,{_zz_s1_outputPayload_selValid_46,{_zz_s1_outputPayload_selValid_45,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0011))}}}}}}; - assign _zz_s1_outputPayload_selValid_248 = _zz_s1_outputPayload_selValid_66; - assign _zz_s1_outputPayload_selValid_249 = {_zz_s1_outputPayload_selValid_65,{_zz_s1_outputPayload_selValid_64,{_zz_s1_outputPayload_selValid_63,{_zz_s1_outputPayload_selValid_62,{_zz_s1_outputPayload_selValid_61,{_zz_s1_outputPayload_selValid_60,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0100))}}}}}}; - assign _zz_s1_outputPayload_selValid_250 = _zz_s1_outputPayload_selValid_81; - assign _zz_s1_outputPayload_selValid_251 = {_zz_s1_outputPayload_selValid_80,{_zz_s1_outputPayload_selValid_79,{_zz_s1_outputPayload_selValid_78,{_zz_s1_outputPayload_selValid_77,{_zz_s1_outputPayload_selValid_76,{_zz_s1_outputPayload_selValid_75,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0101))}}}}}}; - assign _zz_s1_outputPayload_selValid_252 = _zz_s1_outputPayload_selValid_96; - assign _zz_s1_outputPayload_selValid_253 = {_zz_s1_outputPayload_selValid_95,{_zz_s1_outputPayload_selValid_94,{_zz_s1_outputPayload_selValid_93,{_zz_s1_outputPayload_selValid_92,{_zz_s1_outputPayload_selValid_91,{_zz_s1_outputPayload_selValid_90,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0110))}}}}}}; - assign _zz_s1_outputPayload_selValid_254 = _zz_s1_outputPayload_selValid_111; - assign _zz_s1_outputPayload_selValid_255 = {_zz_s1_outputPayload_selValid_110,{_zz_s1_outputPayload_selValid_109,{_zz_s1_outputPayload_selValid_108,{_zz_s1_outputPayload_selValid_107,{_zz_s1_outputPayload_selValid_106,{_zz_s1_outputPayload_selValid_105,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0111))}}}}}}; - assign _zz_s1_outputPayload_selValid_256 = _zz_s1_outputPayload_selValid_126; - assign _zz_s1_outputPayload_selValid_257 = {_zz_s1_outputPayload_selValid_125,{_zz_s1_outputPayload_selValid_124,{_zz_s1_outputPayload_selValid_123,{_zz_s1_outputPayload_selValid_122,{_zz_s1_outputPayload_selValid_121,{_zz_s1_outputPayload_selValid_120,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1000))}}}}}}; - assign _zz_s1_outputPayload_selValid_258 = _zz_s1_outputPayload_selValid_141; - assign _zz_s1_outputPayload_selValid_259 = {_zz_s1_outputPayload_selValid_140,{_zz_s1_outputPayload_selValid_139,{_zz_s1_outputPayload_selValid_138,{_zz_s1_outputPayload_selValid_137,{_zz_s1_outputPayload_selValid_136,{_zz_s1_outputPayload_selValid_135,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1001))}}}}}}; - assign _zz_s1_outputPayload_selValid_260 = _zz_s1_outputPayload_selValid_156; - assign _zz_s1_outputPayload_selValid_261 = {_zz_s1_outputPayload_selValid_155,{_zz_s1_outputPayload_selValid_154,{_zz_s1_outputPayload_selValid_153,{_zz_s1_outputPayload_selValid_152,{_zz_s1_outputPayload_selValid_151,{_zz_s1_outputPayload_selValid_150,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1010))}}}}}}; - assign _zz_s1_outputPayload_selValid_262 = _zz_s1_outputPayload_selValid_171; - assign _zz_s1_outputPayload_selValid_263 = {_zz_s1_outputPayload_selValid_170,{_zz_s1_outputPayload_selValid_169,{_zz_s1_outputPayload_selValid_168,{_zz_s1_outputPayload_selValid_167,{_zz_s1_outputPayload_selValid_166,{_zz_s1_outputPayload_selValid_165,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1011))}}}}}}; - assign _zz_s1_outputPayload_selValid_264 = _zz_s1_outputPayload_selValid_186; - assign _zz_s1_outputPayload_selValid_265 = {_zz_s1_outputPayload_selValid_185,{_zz_s1_outputPayload_selValid_184,{_zz_s1_outputPayload_selValid_183,{_zz_s1_outputPayload_selValid_182,{_zz_s1_outputPayload_selValid_181,{_zz_s1_outputPayload_selValid_180,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1100))}}}}}}; - assign _zz_s1_outputPayload_selValid_266 = _zz_s1_outputPayload_selValid_201; - assign _zz_s1_outputPayload_selValid_267 = {_zz_s1_outputPayload_selValid_200,{_zz_s1_outputPayload_selValid_199,{_zz_s1_outputPayload_selValid_198,{_zz_s1_outputPayload_selValid_197,{_zz_s1_outputPayload_selValid_196,{_zz_s1_outputPayload_selValid_195,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1101))}}}}}}; - assign _zz_s1_outputPayload_selValid_268 = _zz_s1_outputPayload_selValid_216; - assign _zz_s1_outputPayload_selValid_269 = {_zz_s1_outputPayload_selValid_215,{_zz_s1_outputPayload_selValid_214,{_zz_s1_outputPayload_selValid_213,{_zz_s1_outputPayload_selValid_212,{_zz_s1_outputPayload_selValid_211,{_zz_s1_outputPayload_selValid_210,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1110))}}}}}}; - assign _zz_s1_outputPayload_selValid_270 = _zz_s1_outputPayload_selValid_231; - assign _zz_s1_outputPayload_selValid_271 = {_zz_s1_outputPayload_selValid_230,{_zz_s1_outputPayload_selValid_229,{_zz_s1_outputPayload_selValid_228,{_zz_s1_outputPayload_selValid_227,{_zz_s1_outputPayload_selValid_226,{_zz_s1_outputPayload_selValid_225,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1111))}}}}}}; - always @(*) begin - case(_zz_s0_countOnesLogic_0_2) - 1'b0 : _zz_s0_countOnesLogic_0_1 = 1'b0; - default : _zz_s0_countOnesLogic_0_1 = 1'b1; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_1_2) - 2'b00 : _zz_s0_countOnesLogic_1_1 = 2'b00; - 2'b01 : _zz_s0_countOnesLogic_1_1 = 2'b01; - 2'b10 : _zz_s0_countOnesLogic_1_1 = 2'b01; - default : _zz_s0_countOnesLogic_1_1 = 2'b10; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_2_2) - 3'b000 : _zz_s0_countOnesLogic_2_1 = 2'b00; - 3'b001 : _zz_s0_countOnesLogic_2_1 = 2'b01; - 3'b010 : _zz_s0_countOnesLogic_2_1 = 2'b01; - 3'b011 : _zz_s0_countOnesLogic_2_1 = 2'b10; - 3'b100 : _zz_s0_countOnesLogic_2_1 = 2'b01; - 3'b101 : _zz_s0_countOnesLogic_2_1 = 2'b10; - 3'b110 : _zz_s0_countOnesLogic_2_1 = 2'b10; - default : _zz_s0_countOnesLogic_2_1 = 2'b11; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_3_10) - 3'b000 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_1; - 3'b001 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_2; - 3'b010 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_3; - 3'b011 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_4; - 3'b100 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_5; - 3'b101 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_6; - 3'b110 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_7; - default : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_3_12) - 3'b000 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_1; - 3'b001 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_2; - 3'b010 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_3; - 3'b011 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_4; - 3'b100 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_5; - 3'b101 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_6; - 3'b110 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_7; - default : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_4_10) - 3'b000 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_1; - 3'b001 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_2; - 3'b010 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_3; - 3'b011 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_4; - 3'b100 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_5; - 3'b101 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_6; - 3'b110 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_7; - default : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_4_12) - 3'b000 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_1; - 3'b001 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_2; - 3'b010 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_3; - 3'b011 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_4; - 3'b100 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_5; - 3'b101 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_6; - 3'b110 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_7; - default : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_5_10) - 3'b000 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_1; - 3'b001 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_2; - 3'b010 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_3; - 3'b011 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_4; - 3'b100 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_5; - 3'b101 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_6; - 3'b110 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_7; - default : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_5_12) - 3'b000 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_1; - 3'b001 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_2; - 3'b010 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_3; - 3'b011 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_4; - 3'b100 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_5; - 3'b101 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_6; - 3'b110 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_7; - default : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_6_11) - 3'b000 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_1; - 3'b001 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_2; - 3'b010 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_3; - 3'b011 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_4; - 3'b100 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_5; - 3'b101 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_6; - 3'b110 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_7; - default : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_6_13) - 3'b000 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_1; - 3'b001 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_2; - 3'b010 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_3; - 3'b011 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_4; - 3'b100 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_5; - 3'b101 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_6; - 3'b110 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_7; - default : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_6_15) - 3'b000 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_1; - 3'b001 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_2; - 3'b010 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_3; - 3'b011 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_4; - 3'b100 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_5; - 3'b101 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_6; - 3'b110 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_7; - default : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_7_11) - 3'b000 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_1; - 3'b001 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_2; - 3'b010 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_3; - 3'b011 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_4; - 3'b100 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_5; - 3'b101 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_6; - 3'b110 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_7; - default : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_7_13) - 3'b000 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_1; - 3'b001 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_2; - 3'b010 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_3; - 3'b011 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_4; - 3'b100 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_5; - 3'b101 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_6; - 3'b110 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_7; - default : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_7_15) - 3'b000 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_1; - 3'b001 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_2; - 3'b010 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_3; - 3'b011 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_4; - 3'b100 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_5; - 3'b101 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_6; - 3'b110 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_7; - default : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_8_11) - 3'b000 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_1; - 3'b001 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_2; - 3'b010 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_3; - 3'b011 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_4; - 3'b100 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_5; - 3'b101 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_6; - 3'b110 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_7; - default : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_8_13) - 3'b000 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_1; - 3'b001 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_2; - 3'b010 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_3; - 3'b011 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_4; - 3'b100 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_5; - 3'b101 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_6; - 3'b110 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_7; - default : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_8_15) - 3'b000 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_1; - 3'b001 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_2; - 3'b010 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_3; - 3'b011 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_4; - 3'b100 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_5; - 3'b101 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_6; - 3'b110 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_7; - default : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_11) - 3'b000 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_13) - 3'b000 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_16) - 3'b000 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_18) - 3'b000 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_11) - 3'b000 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_13) - 3'b000 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_16) - 3'b000 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_18) - 3'b000 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_11) - 3'b000 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_13) - 3'b000 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_16) - 3'b000 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_18) - 3'b000 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_12) - 3'b000 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_14) - 3'b000 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_17) - 3'b000 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_19) - 3'b000 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_21) - 3'b000 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_12) - 3'b000 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_14) - 3'b000 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_17) - 3'b000 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_19) - 3'b000 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_21) - 3'b000 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_12) - 3'b000 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_14) - 3'b000 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_17) - 3'b000 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_19) - 3'b000 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_21) - 3'b000 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_11) - 3'b000 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_13) - 3'b000 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_16) - 3'b000 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_18) - 3'b000 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_21) - 3'b000 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_23) - 3'b000 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_0) - 4'b0000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_1) - 4'b0000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_2) - 4'b0000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_3) - 4'b0000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_4) - 4'b0000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_5) - 4'b0000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_6) - 4'b0000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_7) - 4'b0000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_8) - 4'b0000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_9) - 4'b0000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_10) - 4'b0000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_11) - 4'b0000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_12) - 4'b0000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_13) - 4'b0000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_14) - 4'b0000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_15) - 4'b0000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(_zz_io_output_usedUntil_5) - 4'b0000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_0; - 4'b0001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_1; - 4'b0010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_2; - 4'b0011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_3; - 4'b0100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_4; - 4'b0101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_5; - 4'b0110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_6; - 4'b0111 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_7; - 4'b1000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_8; - 4'b1001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_9; - 4'b1010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_10; - 4'b1011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_11; - 4'b1100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_12; - 4'b1101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_13; - 4'b1110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_14; - default : _zz_io_output_usedUntil_4 = s2_input_payload_sel_15; - endcase - end - - always @(*) begin - io_input_ready = s0_input_ready; - if(when_Stream_l375) begin - io_input_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! s0_input_valid); - assign s0_input_valid = io_input_rValid; - assign s0_input_payload_data = io_input_rData_data; - assign s0_input_payload_mask = io_input_rData_mask; - assign _zz_s0_countOnesLogic_0 = s0_input_payload_mask[0]; - assign _zz_s0_countOnesLogic_1 = s0_input_payload_mask[1]; - assign _zz_s0_countOnesLogic_2 = s0_input_payload_mask[2]; - assign _zz_s0_countOnesLogic_3 = s0_input_payload_mask[3]; - assign _zz_s0_countOnesLogic_4 = s0_input_payload_mask[4]; - assign _zz_s0_countOnesLogic_5 = s0_input_payload_mask[5]; - assign _zz_s0_countOnesLogic_6 = s0_input_payload_mask[6]; - assign _zz_s0_countOnesLogic_7 = s0_input_payload_mask[7]; - assign _zz_s0_countOnesLogic_8 = s0_input_payload_mask[8]; - assign _zz_s0_countOnesLogic_9 = s0_input_payload_mask[9]; - assign _zz_s0_countOnesLogic_10 = s0_input_payload_mask[10]; - assign _zz_s0_countOnesLogic_11 = s0_input_payload_mask[11]; - assign _zz_s0_countOnesLogic_12 = s0_input_payload_mask[12]; - assign _zz_s0_countOnesLogic_13 = s0_input_payload_mask[13]; - assign _zz_s0_countOnesLogic_14 = s0_input_payload_mask[14]; - assign s0_countOnesLogic_0 = _zz_s0_countOnesLogic_0_1; - assign s0_countOnesLogic_1 = _zz_s0_countOnesLogic_1_1; - assign s0_countOnesLogic_2 = _zz_s0_countOnesLogic_2_1; - assign _zz_s0_countOnesLogic_3_1 = 3'b000; - assign _zz_s0_countOnesLogic_3_2 = 3'b001; - assign _zz_s0_countOnesLogic_3_3 = 3'b001; - assign _zz_s0_countOnesLogic_3_4 = 3'b010; - assign _zz_s0_countOnesLogic_3_5 = 3'b001; - assign _zz_s0_countOnesLogic_3_6 = 3'b010; - assign _zz_s0_countOnesLogic_3_7 = 3'b010; - assign _zz_s0_countOnesLogic_3_8 = 3'b011; - assign s0_countOnesLogic_3 = (_zz_s0_countOnesLogic_3_9 + _zz_s0_countOnesLogic_3_11); - assign _zz_s0_countOnesLogic_4_1 = 3'b000; - assign _zz_s0_countOnesLogic_4_2 = 3'b001; - assign _zz_s0_countOnesLogic_4_3 = 3'b001; - assign _zz_s0_countOnesLogic_4_4 = 3'b010; - assign _zz_s0_countOnesLogic_4_5 = 3'b001; - assign _zz_s0_countOnesLogic_4_6 = 3'b010; - assign _zz_s0_countOnesLogic_4_7 = 3'b010; - assign _zz_s0_countOnesLogic_4_8 = 3'b011; - assign s0_countOnesLogic_4 = (_zz_s0_countOnesLogic_4_9 + _zz_s0_countOnesLogic_4_11); - assign _zz_s0_countOnesLogic_5_1 = 3'b000; - assign _zz_s0_countOnesLogic_5_2 = 3'b001; - assign _zz_s0_countOnesLogic_5_3 = 3'b001; - assign _zz_s0_countOnesLogic_5_4 = 3'b010; - assign _zz_s0_countOnesLogic_5_5 = 3'b001; - assign _zz_s0_countOnesLogic_5_6 = 3'b010; - assign _zz_s0_countOnesLogic_5_7 = 3'b010; - assign _zz_s0_countOnesLogic_5_8 = 3'b011; - assign s0_countOnesLogic_5 = (_zz_s0_countOnesLogic_5_9 + _zz_s0_countOnesLogic_5_11); - assign _zz_s0_countOnesLogic_6_1 = 3'b000; - assign _zz_s0_countOnesLogic_6_2 = 3'b001; - assign _zz_s0_countOnesLogic_6_3 = 3'b001; - assign _zz_s0_countOnesLogic_6_4 = 3'b010; - assign _zz_s0_countOnesLogic_6_5 = 3'b001; - assign _zz_s0_countOnesLogic_6_6 = 3'b010; - assign _zz_s0_countOnesLogic_6_7 = 3'b010; - assign _zz_s0_countOnesLogic_6_8 = 3'b011; - assign s0_countOnesLogic_6 = (_zz_s0_countOnesLogic_6_9 + _zz_s0_countOnesLogic_6_14); - assign _zz_s0_countOnesLogic_7_1 = 4'b0000; - assign _zz_s0_countOnesLogic_7_2 = 4'b0001; - assign _zz_s0_countOnesLogic_7_3 = 4'b0001; - assign _zz_s0_countOnesLogic_7_4 = 4'b0010; - assign _zz_s0_countOnesLogic_7_5 = 4'b0001; - assign _zz_s0_countOnesLogic_7_6 = 4'b0010; - assign _zz_s0_countOnesLogic_7_7 = 4'b0010; - assign _zz_s0_countOnesLogic_7_8 = 4'b0011; - assign s0_countOnesLogic_7 = (_zz_s0_countOnesLogic_7_9 + _zz_s0_countOnesLogic_7_14); - assign _zz_s0_countOnesLogic_8_1 = 4'b0000; - assign _zz_s0_countOnesLogic_8_2 = 4'b0001; - assign _zz_s0_countOnesLogic_8_3 = 4'b0001; - assign _zz_s0_countOnesLogic_8_4 = 4'b0010; - assign _zz_s0_countOnesLogic_8_5 = 4'b0001; - assign _zz_s0_countOnesLogic_8_6 = 4'b0010; - assign _zz_s0_countOnesLogic_8_7 = 4'b0010; - assign _zz_s0_countOnesLogic_8_8 = 4'b0011; - assign s0_countOnesLogic_8 = (_zz_s0_countOnesLogic_8_9 + _zz_s0_countOnesLogic_8_14); - assign _zz_s0_countOnesLogic_9_1 = 4'b0000; - assign _zz_s0_countOnesLogic_9_2 = 4'b0001; - assign _zz_s0_countOnesLogic_9_3 = 4'b0001; - assign _zz_s0_countOnesLogic_9_4 = 4'b0010; - assign _zz_s0_countOnesLogic_9_5 = 4'b0001; - assign _zz_s0_countOnesLogic_9_6 = 4'b0010; - assign _zz_s0_countOnesLogic_9_7 = 4'b0010; - assign _zz_s0_countOnesLogic_9_8 = 4'b0011; - assign s0_countOnesLogic_9 = (_zz_s0_countOnesLogic_9_9 + _zz_s0_countOnesLogic_9_14); - assign _zz_s0_countOnesLogic_10_1 = 4'b0000; - assign _zz_s0_countOnesLogic_10_2 = 4'b0001; - assign _zz_s0_countOnesLogic_10_3 = 4'b0001; - assign _zz_s0_countOnesLogic_10_4 = 4'b0010; - assign _zz_s0_countOnesLogic_10_5 = 4'b0001; - assign _zz_s0_countOnesLogic_10_6 = 4'b0010; - assign _zz_s0_countOnesLogic_10_7 = 4'b0010; - assign _zz_s0_countOnesLogic_10_8 = 4'b0011; - assign s0_countOnesLogic_10 = (_zz_s0_countOnesLogic_10_9 + _zz_s0_countOnesLogic_10_14); - assign _zz_s0_countOnesLogic_11_1 = 4'b0000; - assign _zz_s0_countOnesLogic_11_2 = 4'b0001; - assign _zz_s0_countOnesLogic_11_3 = 4'b0001; - assign _zz_s0_countOnesLogic_11_4 = 4'b0010; - assign _zz_s0_countOnesLogic_11_5 = 4'b0001; - assign _zz_s0_countOnesLogic_11_6 = 4'b0010; - assign _zz_s0_countOnesLogic_11_7 = 4'b0010; - assign _zz_s0_countOnesLogic_11_8 = 4'b0011; - assign s0_countOnesLogic_11 = (_zz_s0_countOnesLogic_11_9 + _zz_s0_countOnesLogic_11_14); - assign _zz_s0_countOnesLogic_12_1 = 4'b0000; - assign _zz_s0_countOnesLogic_12_2 = 4'b0001; - assign _zz_s0_countOnesLogic_12_3 = 4'b0001; - assign _zz_s0_countOnesLogic_12_4 = 4'b0010; - assign _zz_s0_countOnesLogic_12_5 = 4'b0001; - assign _zz_s0_countOnesLogic_12_6 = 4'b0010; - assign _zz_s0_countOnesLogic_12_7 = 4'b0010; - assign _zz_s0_countOnesLogic_12_8 = 4'b0011; - assign s0_countOnesLogic_12 = (_zz_s0_countOnesLogic_12_9 + _zz_s0_countOnesLogic_12_20); - assign _zz_s0_countOnesLogic_13_1 = 4'b0000; - assign _zz_s0_countOnesLogic_13_2 = 4'b0001; - assign _zz_s0_countOnesLogic_13_3 = 4'b0001; - assign _zz_s0_countOnesLogic_13_4 = 4'b0010; - assign _zz_s0_countOnesLogic_13_5 = 4'b0001; - assign _zz_s0_countOnesLogic_13_6 = 4'b0010; - assign _zz_s0_countOnesLogic_13_7 = 4'b0010; - assign _zz_s0_countOnesLogic_13_8 = 4'b0011; - assign s0_countOnesLogic_13 = (_zz_s0_countOnesLogic_13_9 + _zz_s0_countOnesLogic_13_20); - assign _zz_s0_countOnesLogic_14_1 = 4'b0000; - assign _zz_s0_countOnesLogic_14_2 = 4'b0001; - assign _zz_s0_countOnesLogic_14_3 = 4'b0001; - assign _zz_s0_countOnesLogic_14_4 = 4'b0010; - assign _zz_s0_countOnesLogic_14_5 = 4'b0001; - assign _zz_s0_countOnesLogic_14_6 = 4'b0010; - assign _zz_s0_countOnesLogic_14_7 = 4'b0010; - assign _zz_s0_countOnesLogic_14_8 = 4'b0011; - assign s0_countOnesLogic_14 = (_zz_s0_countOnesLogic_14_9 + _zz_s0_countOnesLogic_14_20); - assign _zz_s0_countOnesLogic_15 = 5'h0; - assign _zz_s0_countOnesLogic_15_1 = 5'h01; - assign _zz_s0_countOnesLogic_15_2 = 5'h01; - assign _zz_s0_countOnesLogic_15_3 = 5'h02; - assign _zz_s0_countOnesLogic_15_4 = 5'h01; - assign _zz_s0_countOnesLogic_15_5 = 5'h02; - assign _zz_s0_countOnesLogic_15_6 = 5'h02; - assign _zz_s0_countOnesLogic_15_7 = 5'h03; - assign s0_countOnesLogic_15 = (_zz_s0_countOnesLogic_15_8 + _zz_s0_countOnesLogic_15_19); - assign s0_outputPayload_cmd_data = s0_input_payload_data; - assign s0_outputPayload_cmd_mask = s0_input_payload_mask; - assign s0_outputPayload_countOnes_0 = s0_countOnesLogic_0; - assign s0_outputPayload_countOnes_1 = s0_countOnesLogic_1; - assign s0_outputPayload_countOnes_2 = s0_countOnesLogic_2; - assign s0_outputPayload_countOnes_3 = s0_countOnesLogic_3; - assign s0_outputPayload_countOnes_4 = s0_countOnesLogic_4; - assign s0_outputPayload_countOnes_5 = s0_countOnesLogic_5; - assign s0_outputPayload_countOnes_6 = s0_countOnesLogic_6; - assign s0_outputPayload_countOnes_7 = s0_countOnesLogic_7; - assign s0_outputPayload_countOnes_8 = s0_countOnesLogic_8; - assign s0_outputPayload_countOnes_9 = s0_countOnesLogic_9; - assign s0_outputPayload_countOnes_10 = s0_countOnesLogic_10; - assign s0_outputPayload_countOnes_11 = s0_countOnesLogic_11; - assign s0_outputPayload_countOnes_12 = s0_countOnesLogic_12; - assign s0_outputPayload_countOnes_13 = s0_countOnesLogic_13; - assign s0_outputPayload_countOnes_14 = s0_countOnesLogic_14; - assign s0_outputPayload_countOnes_15 = s0_countOnesLogic_15; - assign s0_output_valid = s0_input_valid; - assign s0_input_ready = s0_output_ready; - assign s0_output_payload_cmd_data = s0_outputPayload_cmd_data; - assign s0_output_payload_cmd_mask = s0_outputPayload_cmd_mask; - assign s0_output_payload_countOnes_0 = s0_outputPayload_countOnes_0; - assign s0_output_payload_countOnes_1 = s0_outputPayload_countOnes_1; - assign s0_output_payload_countOnes_2 = s0_outputPayload_countOnes_2; - assign s0_output_payload_countOnes_3 = s0_outputPayload_countOnes_3; - assign s0_output_payload_countOnes_4 = s0_outputPayload_countOnes_4; - assign s0_output_payload_countOnes_5 = s0_outputPayload_countOnes_5; - assign s0_output_payload_countOnes_6 = s0_outputPayload_countOnes_6; - assign s0_output_payload_countOnes_7 = s0_outputPayload_countOnes_7; - assign s0_output_payload_countOnes_8 = s0_outputPayload_countOnes_8; - assign s0_output_payload_countOnes_9 = s0_outputPayload_countOnes_9; - assign s0_output_payload_countOnes_10 = s0_outputPayload_countOnes_10; - assign s0_output_payload_countOnes_11 = s0_outputPayload_countOnes_11; - assign s0_output_payload_countOnes_12 = s0_outputPayload_countOnes_12; - assign s0_output_payload_countOnes_13 = s0_outputPayload_countOnes_13; - assign s0_output_payload_countOnes_14 = s0_outputPayload_countOnes_14; - assign s0_output_payload_countOnes_15 = s0_outputPayload_countOnes_15; - always @(*) begin - s0_output_ready = s1_input_ready; - if(when_Stream_l375_1) begin - s0_output_ready = 1'b1; - end - end - - assign when_Stream_l375_1 = (! s1_input_valid); - assign s1_input_valid = s0_output_rValid; - assign s1_input_payload_cmd_data = s0_output_rData_cmd_data; - assign s1_input_payload_cmd_mask = s0_output_rData_cmd_mask; - assign s1_input_payload_countOnes_0 = s0_output_rData_countOnes_0; - assign s1_input_payload_countOnes_1 = s0_output_rData_countOnes_1; - assign s1_input_payload_countOnes_2 = s0_output_rData_countOnes_2; - assign s1_input_payload_countOnes_3 = s0_output_rData_countOnes_3; - assign s1_input_payload_countOnes_4 = s0_output_rData_countOnes_4; - assign s1_input_payload_countOnes_5 = s0_output_rData_countOnes_5; - assign s1_input_payload_countOnes_6 = s0_output_rData_countOnes_6; - assign s1_input_payload_countOnes_7 = s0_output_rData_countOnes_7; - assign s1_input_payload_countOnes_8 = s0_output_rData_countOnes_8; - assign s1_input_payload_countOnes_9 = s0_output_rData_countOnes_9; - assign s1_input_payload_countOnes_10 = s0_output_rData_countOnes_10; - assign s1_input_payload_countOnes_11 = s0_output_rData_countOnes_11; - assign s1_input_payload_countOnes_12 = s0_output_rData_countOnes_12; - assign s1_input_payload_countOnes_13 = s0_output_rData_countOnes_13; - assign s1_input_payload_countOnes_14 = s0_output_rData_countOnes_14; - assign s1_input_payload_countOnes_15 = s0_output_rData_countOnes_15; - assign s1_offsetNext = (_zz_s1_offsetNext + s1_input_payload_countOnes_15); - assign s1_input_fire = (s1_input_valid && s1_input_ready); - assign s1_inputIndexes_0 = (4'b0000 + s1_offset); - assign s1_inputIndexes_1 = (_zz_s1_inputIndexes_1 + s1_offset); - assign s1_inputIndexes_2 = (_zz_s1_inputIndexes_2 + s1_offset); - assign s1_inputIndexes_3 = (_zz_s1_inputIndexes_3 + s1_offset); - assign s1_inputIndexes_4 = (_zz_s1_inputIndexes_4 + s1_offset); - assign s1_inputIndexes_5 = (_zz_s1_inputIndexes_5 + s1_offset); - assign s1_inputIndexes_6 = (_zz_s1_inputIndexes_6 + s1_offset); - assign s1_inputIndexes_7 = (_zz_s1_inputIndexes_7 + s1_offset); - assign s1_inputIndexes_8 = (s1_input_payload_countOnes_7 + s1_offset); - assign s1_inputIndexes_9 = (s1_input_payload_countOnes_8 + s1_offset); - assign s1_inputIndexes_10 = (s1_input_payload_countOnes_9 + s1_offset); - assign s1_inputIndexes_11 = (s1_input_payload_countOnes_10 + s1_offset); - assign s1_inputIndexes_12 = (s1_input_payload_countOnes_11 + s1_offset); - assign s1_inputIndexes_13 = (s1_input_payload_countOnes_12 + s1_offset); - assign s1_inputIndexes_14 = (s1_input_payload_countOnes_13 + s1_offset); - assign s1_inputIndexes_15 = (s1_input_payload_countOnes_14 + s1_offset); - assign s1_outputPayload_cmd_data = s1_input_payload_cmd_data; - assign s1_outputPayload_cmd_mask = s1_input_payload_cmd_mask; - assign s1_outputPayload_index_0 = s1_inputIndexes_0; - assign s1_outputPayload_index_1 = s1_inputIndexes_1; - assign s1_outputPayload_index_2 = s1_inputIndexes_2; - assign s1_outputPayload_index_3 = s1_inputIndexes_3; - assign s1_outputPayload_index_4 = s1_inputIndexes_4; - assign s1_outputPayload_index_5 = s1_inputIndexes_5; - assign s1_outputPayload_index_6 = s1_inputIndexes_6; - assign s1_outputPayload_index_7 = s1_inputIndexes_7; - assign s1_outputPayload_index_8 = s1_inputIndexes_8; - assign s1_outputPayload_index_9 = s1_inputIndexes_9; - assign s1_outputPayload_index_10 = s1_inputIndexes_10; - assign s1_outputPayload_index_11 = s1_inputIndexes_11; - assign s1_outputPayload_index_12 = s1_inputIndexes_12; - assign s1_outputPayload_index_13 = s1_inputIndexes_13; - assign s1_outputPayload_index_14 = s1_inputIndexes_14; - assign s1_outputPayload_index_15 = s1_inputIndexes_15; - assign s1_outputPayload_last = s1_offsetNext[4]; - assign _zz_s1_outputPayload_selValid = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_1 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_2 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_3 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_4 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_5 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_6 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_7 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_8 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_9 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_10 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_11 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_12 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_13 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_14 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0000)); - assign _zz_s1_outputPayload_sel_0 = (((((((_zz_s1_outputPayload_selValid || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_14); - assign _zz_s1_outputPayload_sel_0_1 = (((((((_zz_s1_outputPayload_selValid_1 || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); - assign _zz_s1_outputPayload_sel_0_2 = (((((((_zz_s1_outputPayload_selValid_3 || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); - assign _zz_s1_outputPayload_sel_0_3 = (((((((_zz_s1_outputPayload_selValid_7 || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); - assign s1_outputPayload_sel_0 = {_zz_s1_outputPayload_sel_0_3,{_zz_s1_outputPayload_sel_0_2,{_zz_s1_outputPayload_sel_0_1,_zz_s1_outputPayload_sel_0}}}; - always @(*) begin - s1_outputPayload_selValid[0] = ((|{_zz_s1_outputPayload_selValid_14,{_zz_s1_outputPayload_selValid_13,{_zz_s1_outputPayload_selValid_12,{_zz_s1_outputPayload_selValid_11,{_zz_s1_outputPayload_selValid_10,{_zz_s1_outputPayload_selValid_9,{_zz_s1_outputPayload_selValid_8,{_zz_s1_outputPayload_selValid_7,{_zz_s1_outputPayload_selValid_240,_zz_s1_outputPayload_selValid_241}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_0]); - s1_outputPayload_selValid[1] = ((|{_zz_s1_outputPayload_selValid_29,{_zz_s1_outputPayload_selValid_28,{_zz_s1_outputPayload_selValid_27,{_zz_s1_outputPayload_selValid_26,{_zz_s1_outputPayload_selValid_25,{_zz_s1_outputPayload_selValid_24,{_zz_s1_outputPayload_selValid_23,{_zz_s1_outputPayload_selValid_22,{_zz_s1_outputPayload_selValid_242,_zz_s1_outputPayload_selValid_243}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_1]); - s1_outputPayload_selValid[2] = ((|{_zz_s1_outputPayload_selValid_44,{_zz_s1_outputPayload_selValid_43,{_zz_s1_outputPayload_selValid_42,{_zz_s1_outputPayload_selValid_41,{_zz_s1_outputPayload_selValid_40,{_zz_s1_outputPayload_selValid_39,{_zz_s1_outputPayload_selValid_38,{_zz_s1_outputPayload_selValid_37,{_zz_s1_outputPayload_selValid_244,_zz_s1_outputPayload_selValid_245}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_2]); - s1_outputPayload_selValid[3] = ((|{_zz_s1_outputPayload_selValid_59,{_zz_s1_outputPayload_selValid_58,{_zz_s1_outputPayload_selValid_57,{_zz_s1_outputPayload_selValid_56,{_zz_s1_outputPayload_selValid_55,{_zz_s1_outputPayload_selValid_54,{_zz_s1_outputPayload_selValid_53,{_zz_s1_outputPayload_selValid_52,{_zz_s1_outputPayload_selValid_246,_zz_s1_outputPayload_selValid_247}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_3]); - s1_outputPayload_selValid[4] = ((|{_zz_s1_outputPayload_selValid_74,{_zz_s1_outputPayload_selValid_73,{_zz_s1_outputPayload_selValid_72,{_zz_s1_outputPayload_selValid_71,{_zz_s1_outputPayload_selValid_70,{_zz_s1_outputPayload_selValid_69,{_zz_s1_outputPayload_selValid_68,{_zz_s1_outputPayload_selValid_67,{_zz_s1_outputPayload_selValid_248,_zz_s1_outputPayload_selValid_249}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_4]); - s1_outputPayload_selValid[5] = ((|{_zz_s1_outputPayload_selValid_89,{_zz_s1_outputPayload_selValid_88,{_zz_s1_outputPayload_selValid_87,{_zz_s1_outputPayload_selValid_86,{_zz_s1_outputPayload_selValid_85,{_zz_s1_outputPayload_selValid_84,{_zz_s1_outputPayload_selValid_83,{_zz_s1_outputPayload_selValid_82,{_zz_s1_outputPayload_selValid_250,_zz_s1_outputPayload_selValid_251}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_5]); - s1_outputPayload_selValid[6] = ((|{_zz_s1_outputPayload_selValid_104,{_zz_s1_outputPayload_selValid_103,{_zz_s1_outputPayload_selValid_102,{_zz_s1_outputPayload_selValid_101,{_zz_s1_outputPayload_selValid_100,{_zz_s1_outputPayload_selValid_99,{_zz_s1_outputPayload_selValid_98,{_zz_s1_outputPayload_selValid_97,{_zz_s1_outputPayload_selValid_252,_zz_s1_outputPayload_selValid_253}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_6]); - s1_outputPayload_selValid[7] = ((|{_zz_s1_outputPayload_selValid_119,{_zz_s1_outputPayload_selValid_118,{_zz_s1_outputPayload_selValid_117,{_zz_s1_outputPayload_selValid_116,{_zz_s1_outputPayload_selValid_115,{_zz_s1_outputPayload_selValid_114,{_zz_s1_outputPayload_selValid_113,{_zz_s1_outputPayload_selValid_112,{_zz_s1_outputPayload_selValid_254,_zz_s1_outputPayload_selValid_255}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_7]); - s1_outputPayload_selValid[8] = ((|{_zz_s1_outputPayload_selValid_134,{_zz_s1_outputPayload_selValid_133,{_zz_s1_outputPayload_selValid_132,{_zz_s1_outputPayload_selValid_131,{_zz_s1_outputPayload_selValid_130,{_zz_s1_outputPayload_selValid_129,{_zz_s1_outputPayload_selValid_128,{_zz_s1_outputPayload_selValid_127,{_zz_s1_outputPayload_selValid_256,_zz_s1_outputPayload_selValid_257}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_8]); - s1_outputPayload_selValid[9] = ((|{_zz_s1_outputPayload_selValid_149,{_zz_s1_outputPayload_selValid_148,{_zz_s1_outputPayload_selValid_147,{_zz_s1_outputPayload_selValid_146,{_zz_s1_outputPayload_selValid_145,{_zz_s1_outputPayload_selValid_144,{_zz_s1_outputPayload_selValid_143,{_zz_s1_outputPayload_selValid_142,{_zz_s1_outputPayload_selValid_258,_zz_s1_outputPayload_selValid_259}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_9]); - s1_outputPayload_selValid[10] = ((|{_zz_s1_outputPayload_selValid_164,{_zz_s1_outputPayload_selValid_163,{_zz_s1_outputPayload_selValid_162,{_zz_s1_outputPayload_selValid_161,{_zz_s1_outputPayload_selValid_160,{_zz_s1_outputPayload_selValid_159,{_zz_s1_outputPayload_selValid_158,{_zz_s1_outputPayload_selValid_157,{_zz_s1_outputPayload_selValid_260,_zz_s1_outputPayload_selValid_261}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_10]); - s1_outputPayload_selValid[11] = ((|{_zz_s1_outputPayload_selValid_179,{_zz_s1_outputPayload_selValid_178,{_zz_s1_outputPayload_selValid_177,{_zz_s1_outputPayload_selValid_176,{_zz_s1_outputPayload_selValid_175,{_zz_s1_outputPayload_selValid_174,{_zz_s1_outputPayload_selValid_173,{_zz_s1_outputPayload_selValid_172,{_zz_s1_outputPayload_selValid_262,_zz_s1_outputPayload_selValid_263}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_11]); - s1_outputPayload_selValid[12] = ((|{_zz_s1_outputPayload_selValid_194,{_zz_s1_outputPayload_selValid_193,{_zz_s1_outputPayload_selValid_192,{_zz_s1_outputPayload_selValid_191,{_zz_s1_outputPayload_selValid_190,{_zz_s1_outputPayload_selValid_189,{_zz_s1_outputPayload_selValid_188,{_zz_s1_outputPayload_selValid_187,{_zz_s1_outputPayload_selValid_264,_zz_s1_outputPayload_selValid_265}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_12]); - s1_outputPayload_selValid[13] = ((|{_zz_s1_outputPayload_selValid_209,{_zz_s1_outputPayload_selValid_208,{_zz_s1_outputPayload_selValid_207,{_zz_s1_outputPayload_selValid_206,{_zz_s1_outputPayload_selValid_205,{_zz_s1_outputPayload_selValid_204,{_zz_s1_outputPayload_selValid_203,{_zz_s1_outputPayload_selValid_202,{_zz_s1_outputPayload_selValid_266,_zz_s1_outputPayload_selValid_267}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_13]); - s1_outputPayload_selValid[14] = ((|{_zz_s1_outputPayload_selValid_224,{_zz_s1_outputPayload_selValid_223,{_zz_s1_outputPayload_selValid_222,{_zz_s1_outputPayload_selValid_221,{_zz_s1_outputPayload_selValid_220,{_zz_s1_outputPayload_selValid_219,{_zz_s1_outputPayload_selValid_218,{_zz_s1_outputPayload_selValid_217,{_zz_s1_outputPayload_selValid_268,_zz_s1_outputPayload_selValid_269}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_14]); - s1_outputPayload_selValid[15] = ((|{_zz_s1_outputPayload_selValid_239,{_zz_s1_outputPayload_selValid_238,{_zz_s1_outputPayload_selValid_237,{_zz_s1_outputPayload_selValid_236,{_zz_s1_outputPayload_selValid_235,{_zz_s1_outputPayload_selValid_234,{_zz_s1_outputPayload_selValid_233,{_zz_s1_outputPayload_selValid_232,{_zz_s1_outputPayload_selValid_270,_zz_s1_outputPayload_selValid_271}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_15]); - end - - assign _zz_s1_outputPayload_selValid_15 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_16 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_17 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_18 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_19 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_20 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_21 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_22 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_23 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_24 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_25 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_26 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_27 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_28 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_29 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0001)); - assign _zz_s1_outputPayload_sel_1 = (((((((_zz_s1_outputPayload_selValid_15 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_29); - assign _zz_s1_outputPayload_sel_1_1 = (((((((_zz_s1_outputPayload_selValid_16 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); - assign _zz_s1_outputPayload_sel_1_2 = (((((((_zz_s1_outputPayload_selValid_18 || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); - assign _zz_s1_outputPayload_sel_1_3 = (((((((_zz_s1_outputPayload_selValid_22 || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); - assign s1_outputPayload_sel_1 = {_zz_s1_outputPayload_sel_1_3,{_zz_s1_outputPayload_sel_1_2,{_zz_s1_outputPayload_sel_1_1,_zz_s1_outputPayload_sel_1}}}; - assign _zz_s1_outputPayload_selValid_30 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_31 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_32 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_33 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_34 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_35 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_36 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_37 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_38 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_39 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_40 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_41 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_42 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_43 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_44 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0010)); - assign _zz_s1_outputPayload_sel_2 = (((((((_zz_s1_outputPayload_selValid_30 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_44); - assign _zz_s1_outputPayload_sel_2_1 = (((((((_zz_s1_outputPayload_selValid_31 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); - assign _zz_s1_outputPayload_sel_2_2 = (((((((_zz_s1_outputPayload_selValid_33 || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); - assign _zz_s1_outputPayload_sel_2_3 = (((((((_zz_s1_outputPayload_selValid_37 || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); - assign s1_outputPayload_sel_2 = {_zz_s1_outputPayload_sel_2_3,{_zz_s1_outputPayload_sel_2_2,{_zz_s1_outputPayload_sel_2_1,_zz_s1_outputPayload_sel_2}}}; - assign _zz_s1_outputPayload_selValid_45 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_46 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_47 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_48 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_49 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_50 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_51 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_52 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_53 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_54 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_55 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_56 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_57 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_58 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_59 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0011)); - assign _zz_s1_outputPayload_sel_3 = (((((((_zz_s1_outputPayload_selValid_45 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_59); - assign _zz_s1_outputPayload_sel_3_1 = (((((((_zz_s1_outputPayload_selValid_46 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); - assign _zz_s1_outputPayload_sel_3_2 = (((((((_zz_s1_outputPayload_selValid_48 || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); - assign _zz_s1_outputPayload_sel_3_3 = (((((((_zz_s1_outputPayload_selValid_52 || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); - assign s1_outputPayload_sel_3 = {_zz_s1_outputPayload_sel_3_3,{_zz_s1_outputPayload_sel_3_2,{_zz_s1_outputPayload_sel_3_1,_zz_s1_outputPayload_sel_3}}}; - assign _zz_s1_outputPayload_selValid_60 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_61 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_62 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_63 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_64 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_65 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_66 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_67 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_68 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_69 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_70 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_71 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_72 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_73 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_74 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0100)); - assign _zz_s1_outputPayload_sel_4 = (((((((_zz_s1_outputPayload_selValid_60 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_74); - assign _zz_s1_outputPayload_sel_4_1 = (((((((_zz_s1_outputPayload_selValid_61 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); - assign _zz_s1_outputPayload_sel_4_2 = (((((((_zz_s1_outputPayload_selValid_63 || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); - assign _zz_s1_outputPayload_sel_4_3 = (((((((_zz_s1_outputPayload_selValid_67 || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); - assign s1_outputPayload_sel_4 = {_zz_s1_outputPayload_sel_4_3,{_zz_s1_outputPayload_sel_4_2,{_zz_s1_outputPayload_sel_4_1,_zz_s1_outputPayload_sel_4}}}; - assign _zz_s1_outputPayload_selValid_75 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_76 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_77 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_78 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_79 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_80 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_81 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_82 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_83 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_84 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_85 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_86 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_87 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_88 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_89 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0101)); - assign _zz_s1_outputPayload_sel_5 = (((((((_zz_s1_outputPayload_selValid_75 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_89); - assign _zz_s1_outputPayload_sel_5_1 = (((((((_zz_s1_outputPayload_selValid_76 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); - assign _zz_s1_outputPayload_sel_5_2 = (((((((_zz_s1_outputPayload_selValid_78 || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); - assign _zz_s1_outputPayload_sel_5_3 = (((((((_zz_s1_outputPayload_selValid_82 || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); - assign s1_outputPayload_sel_5 = {_zz_s1_outputPayload_sel_5_3,{_zz_s1_outputPayload_sel_5_2,{_zz_s1_outputPayload_sel_5_1,_zz_s1_outputPayload_sel_5}}}; - assign _zz_s1_outputPayload_selValid_90 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_91 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_92 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_93 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_94 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_95 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_96 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_97 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_98 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_99 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_100 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_101 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_102 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_103 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_104 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0110)); - assign _zz_s1_outputPayload_sel_6 = (((((((_zz_s1_outputPayload_selValid_90 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_104); - assign _zz_s1_outputPayload_sel_6_1 = (((((((_zz_s1_outputPayload_selValid_91 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); - assign _zz_s1_outputPayload_sel_6_2 = (((((((_zz_s1_outputPayload_selValid_93 || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); - assign _zz_s1_outputPayload_sel_6_3 = (((((((_zz_s1_outputPayload_selValid_97 || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); - assign s1_outputPayload_sel_6 = {_zz_s1_outputPayload_sel_6_3,{_zz_s1_outputPayload_sel_6_2,{_zz_s1_outputPayload_sel_6_1,_zz_s1_outputPayload_sel_6}}}; - assign _zz_s1_outputPayload_selValid_105 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_106 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_107 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_108 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_109 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_110 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_111 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_112 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_113 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_114 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_115 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_116 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_117 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_118 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_119 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0111)); - assign _zz_s1_outputPayload_sel_7 = (((((((_zz_s1_outputPayload_selValid_105 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_119); - assign _zz_s1_outputPayload_sel_7_1 = (((((((_zz_s1_outputPayload_selValid_106 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); - assign _zz_s1_outputPayload_sel_7_2 = (((((((_zz_s1_outputPayload_selValid_108 || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); - assign _zz_s1_outputPayload_sel_7_3 = (((((((_zz_s1_outputPayload_selValid_112 || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); - assign s1_outputPayload_sel_7 = {_zz_s1_outputPayload_sel_7_3,{_zz_s1_outputPayload_sel_7_2,{_zz_s1_outputPayload_sel_7_1,_zz_s1_outputPayload_sel_7}}}; - assign _zz_s1_outputPayload_selValid_120 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_121 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_122 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_123 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_124 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_125 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_126 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_127 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_128 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_129 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_130 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_131 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_132 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_133 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_134 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1000)); - assign _zz_s1_outputPayload_sel_8 = (((((((_zz_s1_outputPayload_selValid_120 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_134); - assign _zz_s1_outputPayload_sel_8_1 = (((((((_zz_s1_outputPayload_selValid_121 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); - assign _zz_s1_outputPayload_sel_8_2 = (((((((_zz_s1_outputPayload_selValid_123 || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); - assign _zz_s1_outputPayload_sel_8_3 = (((((((_zz_s1_outputPayload_selValid_127 || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); - assign s1_outputPayload_sel_8 = {_zz_s1_outputPayload_sel_8_3,{_zz_s1_outputPayload_sel_8_2,{_zz_s1_outputPayload_sel_8_1,_zz_s1_outputPayload_sel_8}}}; - assign _zz_s1_outputPayload_selValid_135 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_136 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_137 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_138 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_139 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_140 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_141 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_142 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_143 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_144 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_145 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_146 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_147 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_148 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_149 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1001)); - assign _zz_s1_outputPayload_sel_9 = (((((((_zz_s1_outputPayload_selValid_135 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_149); - assign _zz_s1_outputPayload_sel_9_1 = (((((((_zz_s1_outputPayload_selValid_136 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); - assign _zz_s1_outputPayload_sel_9_2 = (((((((_zz_s1_outputPayload_selValid_138 || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); - assign _zz_s1_outputPayload_sel_9_3 = (((((((_zz_s1_outputPayload_selValid_142 || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); - assign s1_outputPayload_sel_9 = {_zz_s1_outputPayload_sel_9_3,{_zz_s1_outputPayload_sel_9_2,{_zz_s1_outputPayload_sel_9_1,_zz_s1_outputPayload_sel_9}}}; - assign _zz_s1_outputPayload_selValid_150 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_151 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_152 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_153 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_154 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_155 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_156 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_157 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_158 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_159 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_160 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_161 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_162 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_163 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_164 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1010)); - assign _zz_s1_outputPayload_sel_10 = (((((((_zz_s1_outputPayload_selValid_150 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_164); - assign _zz_s1_outputPayload_sel_10_1 = (((((((_zz_s1_outputPayload_selValid_151 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); - assign _zz_s1_outputPayload_sel_10_2 = (((((((_zz_s1_outputPayload_selValid_153 || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); - assign _zz_s1_outputPayload_sel_10_3 = (((((((_zz_s1_outputPayload_selValid_157 || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); - assign s1_outputPayload_sel_10 = {_zz_s1_outputPayload_sel_10_3,{_zz_s1_outputPayload_sel_10_2,{_zz_s1_outputPayload_sel_10_1,_zz_s1_outputPayload_sel_10}}}; - assign _zz_s1_outputPayload_selValid_165 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_166 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_167 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_168 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_169 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_170 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_171 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_172 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_173 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_174 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_175 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_176 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_177 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_178 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_179 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1011)); - assign _zz_s1_outputPayload_sel_11 = (((((((_zz_s1_outputPayload_selValid_165 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_179); - assign _zz_s1_outputPayload_sel_11_1 = (((((((_zz_s1_outputPayload_selValid_166 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); - assign _zz_s1_outputPayload_sel_11_2 = (((((((_zz_s1_outputPayload_selValid_168 || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); - assign _zz_s1_outputPayload_sel_11_3 = (((((((_zz_s1_outputPayload_selValid_172 || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); - assign s1_outputPayload_sel_11 = {_zz_s1_outputPayload_sel_11_3,{_zz_s1_outputPayload_sel_11_2,{_zz_s1_outputPayload_sel_11_1,_zz_s1_outputPayload_sel_11}}}; - assign _zz_s1_outputPayload_selValid_180 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_181 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_182 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_183 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_184 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_185 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_186 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_187 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_188 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_189 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_190 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_191 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_192 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_193 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_194 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1100)); - assign _zz_s1_outputPayload_sel_12 = (((((((_zz_s1_outputPayload_selValid_180 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_194); - assign _zz_s1_outputPayload_sel_12_1 = (((((((_zz_s1_outputPayload_selValid_181 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); - assign _zz_s1_outputPayload_sel_12_2 = (((((((_zz_s1_outputPayload_selValid_183 || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); - assign _zz_s1_outputPayload_sel_12_3 = (((((((_zz_s1_outputPayload_selValid_187 || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); - assign s1_outputPayload_sel_12 = {_zz_s1_outputPayload_sel_12_3,{_zz_s1_outputPayload_sel_12_2,{_zz_s1_outputPayload_sel_12_1,_zz_s1_outputPayload_sel_12}}}; - assign _zz_s1_outputPayload_selValid_195 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_196 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_197 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_198 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_199 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_200 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_201 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_202 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_203 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_204 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_205 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_206 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_207 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_208 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_209 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1101)); - assign _zz_s1_outputPayload_sel_13 = (((((((_zz_s1_outputPayload_selValid_195 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_209); - assign _zz_s1_outputPayload_sel_13_1 = (((((((_zz_s1_outputPayload_selValid_196 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); - assign _zz_s1_outputPayload_sel_13_2 = (((((((_zz_s1_outputPayload_selValid_198 || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); - assign _zz_s1_outputPayload_sel_13_3 = (((((((_zz_s1_outputPayload_selValid_202 || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); - assign s1_outputPayload_sel_13 = {_zz_s1_outputPayload_sel_13_3,{_zz_s1_outputPayload_sel_13_2,{_zz_s1_outputPayload_sel_13_1,_zz_s1_outputPayload_sel_13}}}; - assign _zz_s1_outputPayload_selValid_210 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_211 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_212 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_213 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_214 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_215 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_216 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_217 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_218 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_219 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_220 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_221 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_222 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_223 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_224 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1110)); - assign _zz_s1_outputPayload_sel_14 = (((((((_zz_s1_outputPayload_selValid_210 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_224); - assign _zz_s1_outputPayload_sel_14_1 = (((((((_zz_s1_outputPayload_selValid_211 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); - assign _zz_s1_outputPayload_sel_14_2 = (((((((_zz_s1_outputPayload_selValid_213 || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); - assign _zz_s1_outputPayload_sel_14_3 = (((((((_zz_s1_outputPayload_selValid_217 || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); - assign s1_outputPayload_sel_14 = {_zz_s1_outputPayload_sel_14_3,{_zz_s1_outputPayload_sel_14_2,{_zz_s1_outputPayload_sel_14_1,_zz_s1_outputPayload_sel_14}}}; - assign _zz_s1_outputPayload_selValid_225 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_226 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_227 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_228 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_229 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_230 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_231 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_232 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_233 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_234 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_235 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_236 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_237 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_238 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_239 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1111)); - assign _zz_s1_outputPayload_sel_15 = (((((((_zz_s1_outputPayload_selValid_225 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_239); - assign _zz_s1_outputPayload_sel_15_1 = (((((((_zz_s1_outputPayload_selValid_226 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); - assign _zz_s1_outputPayload_sel_15_2 = (((((((_zz_s1_outputPayload_selValid_228 || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); - assign _zz_s1_outputPayload_sel_15_3 = (((((((_zz_s1_outputPayload_selValid_232 || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); - assign s1_outputPayload_sel_15 = {_zz_s1_outputPayload_sel_15_3,{_zz_s1_outputPayload_sel_15_2,{_zz_s1_outputPayload_sel_15_1,_zz_s1_outputPayload_sel_15}}}; - assign s1_output_valid = s1_input_valid; - assign s1_input_ready = s1_output_ready; - assign s1_output_payload_cmd_data = s1_outputPayload_cmd_data; - assign s1_output_payload_cmd_mask = s1_outputPayload_cmd_mask; - assign s1_output_payload_index_0 = s1_outputPayload_index_0; - assign s1_output_payload_index_1 = s1_outputPayload_index_1; - assign s1_output_payload_index_2 = s1_outputPayload_index_2; - assign s1_output_payload_index_3 = s1_outputPayload_index_3; - assign s1_output_payload_index_4 = s1_outputPayload_index_4; - assign s1_output_payload_index_5 = s1_outputPayload_index_5; - assign s1_output_payload_index_6 = s1_outputPayload_index_6; - assign s1_output_payload_index_7 = s1_outputPayload_index_7; - assign s1_output_payload_index_8 = s1_outputPayload_index_8; - assign s1_output_payload_index_9 = s1_outputPayload_index_9; - assign s1_output_payload_index_10 = s1_outputPayload_index_10; - assign s1_output_payload_index_11 = s1_outputPayload_index_11; - assign s1_output_payload_index_12 = s1_outputPayload_index_12; - assign s1_output_payload_index_13 = s1_outputPayload_index_13; - assign s1_output_payload_index_14 = s1_outputPayload_index_14; - assign s1_output_payload_index_15 = s1_outputPayload_index_15; - assign s1_output_payload_last = s1_outputPayload_last; - assign s1_output_payload_sel_0 = s1_outputPayload_sel_0; - assign s1_output_payload_sel_1 = s1_outputPayload_sel_1; - assign s1_output_payload_sel_2 = s1_outputPayload_sel_2; - assign s1_output_payload_sel_3 = s1_outputPayload_sel_3; - assign s1_output_payload_sel_4 = s1_outputPayload_sel_4; - assign s1_output_payload_sel_5 = s1_outputPayload_sel_5; - assign s1_output_payload_sel_6 = s1_outputPayload_sel_6; - assign s1_output_payload_sel_7 = s1_outputPayload_sel_7; - assign s1_output_payload_sel_8 = s1_outputPayload_sel_8; - assign s1_output_payload_sel_9 = s1_outputPayload_sel_9; - assign s1_output_payload_sel_10 = s1_outputPayload_sel_10; - assign s1_output_payload_sel_11 = s1_outputPayload_sel_11; - assign s1_output_payload_sel_12 = s1_outputPayload_sel_12; - assign s1_output_payload_sel_13 = s1_outputPayload_sel_13; - assign s1_output_payload_sel_14 = s1_outputPayload_sel_14; - assign s1_output_payload_sel_15 = s1_outputPayload_sel_15; - assign s1_output_payload_selValid = s1_outputPayload_selValid; - always @(*) begin - s1_output_ready = s2_input_ready; - if(when_Stream_l375_2) begin - s1_output_ready = 1'b1; - end - end - - assign when_Stream_l375_2 = (! s2_input_valid); - assign s2_input_valid = s1_output_rValid; - assign s2_input_payload_cmd_data = s1_output_rData_cmd_data; - assign s2_input_payload_cmd_mask = s1_output_rData_cmd_mask; - assign s2_input_payload_index_0 = s1_output_rData_index_0; - assign s2_input_payload_index_1 = s1_output_rData_index_1; - assign s2_input_payload_index_2 = s1_output_rData_index_2; - assign s2_input_payload_index_3 = s1_output_rData_index_3; - assign s2_input_payload_index_4 = s1_output_rData_index_4; - assign s2_input_payload_index_5 = s1_output_rData_index_5; - assign s2_input_payload_index_6 = s1_output_rData_index_6; - assign s2_input_payload_index_7 = s1_output_rData_index_7; - assign s2_input_payload_index_8 = s1_output_rData_index_8; - assign s2_input_payload_index_9 = s1_output_rData_index_9; - assign s2_input_payload_index_10 = s1_output_rData_index_10; - assign s2_input_payload_index_11 = s1_output_rData_index_11; - assign s2_input_payload_index_12 = s1_output_rData_index_12; - assign s2_input_payload_index_13 = s1_output_rData_index_13; - assign s2_input_payload_index_14 = s1_output_rData_index_14; - assign s2_input_payload_index_15 = s1_output_rData_index_15; - assign s2_input_payload_last = s1_output_rData_last; - assign s2_input_payload_sel_0 = s1_output_rData_sel_0; - assign s2_input_payload_sel_1 = s1_output_rData_sel_1; - assign s2_input_payload_sel_2 = s1_output_rData_sel_2; - assign s2_input_payload_sel_3 = s1_output_rData_sel_3; - assign s2_input_payload_sel_4 = s1_output_rData_sel_4; - assign s2_input_payload_sel_5 = s1_output_rData_sel_5; - assign s2_input_payload_sel_6 = s1_output_rData_sel_6; - assign s2_input_payload_sel_7 = s1_output_rData_sel_7; - assign s2_input_payload_sel_8 = s1_output_rData_sel_8; - assign s2_input_payload_sel_9 = s1_output_rData_sel_9; - assign s2_input_payload_sel_10 = s1_output_rData_sel_10; - assign s2_input_payload_sel_11 = s1_output_rData_sel_11; - assign s2_input_payload_sel_12 = s1_output_rData_sel_12; - assign s2_input_payload_sel_13 = s1_output_rData_sel_13; - assign s2_input_payload_sel_14 = s1_output_rData_sel_14; - assign s2_input_payload_sel_15 = s1_output_rData_sel_15; - assign s2_input_payload_selValid = s1_output_rData_selValid; - always @(*) begin - s2_input_ready = ((! io_output_enough) || io_output_consume); - if(when_DmaSg_l1464) begin - s2_input_ready = 1'b0; - end - end - - assign when_DmaSg_l1464 = (_zz_when_DmaSg_l1464 < s1_byteCounter); - assign s2_input_fire = (s2_input_valid && s2_input_ready); - assign io_output_consumed = s2_input_fire; - assign s2_inputDataBytes_0 = s2_input_payload_cmd_data[7 : 0]; - assign s2_inputDataBytes_1 = s2_input_payload_cmd_data[15 : 8]; - assign s2_inputDataBytes_2 = s2_input_payload_cmd_data[23 : 16]; - assign s2_inputDataBytes_3 = s2_input_payload_cmd_data[31 : 24]; - assign s2_inputDataBytes_4 = s2_input_payload_cmd_data[39 : 32]; - assign s2_inputDataBytes_5 = s2_input_payload_cmd_data[47 : 40]; - assign s2_inputDataBytes_6 = s2_input_payload_cmd_data[55 : 48]; - assign s2_inputDataBytes_7 = s2_input_payload_cmd_data[63 : 56]; - assign s2_inputDataBytes_8 = s2_input_payload_cmd_data[71 : 64]; - assign s2_inputDataBytes_9 = s2_input_payload_cmd_data[79 : 72]; - assign s2_inputDataBytes_10 = s2_input_payload_cmd_data[87 : 80]; - assign s2_inputDataBytes_11 = s2_input_payload_cmd_data[95 : 88]; - assign s2_inputDataBytes_12 = s2_input_payload_cmd_data[103 : 96]; - assign s2_inputDataBytes_13 = s2_input_payload_cmd_data[111 : 104]; - assign s2_inputDataBytes_14 = s2_input_payload_cmd_data[119 : 112]; - assign s2_inputDataBytes_15 = s2_input_payload_cmd_data[127 : 120]; - assign s2_byteLogic_0_lastUsed = (4'b0000 == io_output_lastByteUsed); - assign s2_byteLogic_0_inputMask = s2_input_payload_selValid[0]; - assign s2_byteLogic_0_inputData = _zz_s2_byteLogic_0_inputData; - assign s2_byteLogic_0_outputMask = (s2_byteLogic_0_buffer_valid || (s2_input_valid && s2_byteLogic_0_inputMask)); - assign s2_byteLogic_0_outputData = (s2_byteLogic_0_buffer_valid ? s2_byteLogic_0_buffer_data : s2_byteLogic_0_inputData); - always @(*) begin - io_output_mask[0] = s2_byteLogic_0_outputMask; - io_output_mask[1] = s2_byteLogic_1_outputMask; - io_output_mask[2] = s2_byteLogic_2_outputMask; - io_output_mask[3] = s2_byteLogic_3_outputMask; - io_output_mask[4] = s2_byteLogic_4_outputMask; - io_output_mask[5] = s2_byteLogic_5_outputMask; - io_output_mask[6] = s2_byteLogic_6_outputMask; - io_output_mask[7] = s2_byteLogic_7_outputMask; - io_output_mask[8] = s2_byteLogic_8_outputMask; - io_output_mask[9] = s2_byteLogic_9_outputMask; - io_output_mask[10] = s2_byteLogic_10_outputMask; - io_output_mask[11] = s2_byteLogic_11_outputMask; - io_output_mask[12] = s2_byteLogic_12_outputMask; - io_output_mask[13] = s2_byteLogic_13_outputMask; - io_output_mask[14] = s2_byteLogic_14_outputMask; - io_output_mask[15] = s2_byteLogic_15_outputMask; - end - - always @(*) begin - io_output_data[7 : 0] = s2_byteLogic_0_outputData; - io_output_data[15 : 8] = s2_byteLogic_1_outputData; - io_output_data[23 : 16] = s2_byteLogic_2_outputData; - io_output_data[31 : 24] = s2_byteLogic_3_outputData; - io_output_data[39 : 32] = s2_byteLogic_4_outputData; - io_output_data[47 : 40] = s2_byteLogic_5_outputData; - io_output_data[55 : 48] = s2_byteLogic_6_outputData; - io_output_data[63 : 56] = s2_byteLogic_7_outputData; - io_output_data[71 : 64] = s2_byteLogic_8_outputData; - io_output_data[79 : 72] = s2_byteLogic_9_outputData; - io_output_data[87 : 80] = s2_byteLogic_10_outputData; - io_output_data[95 : 88] = s2_byteLogic_11_outputData; - io_output_data[103 : 96] = s2_byteLogic_12_outputData; - io_output_data[111 : 104] = s2_byteLogic_13_outputData; - io_output_data[119 : 112] = s2_byteLogic_14_outputData; - io_output_data[127 : 120] = s2_byteLogic_15_outputData; - end - - assign when_DmaSg_l1493 = (s2_byteLogic_0_inputMask && ((! io_output_consume) || s2_byteLogic_0_buffer_valid)); - assign s2_byteLogic_1_lastUsed = (4'b0001 == io_output_lastByteUsed); - assign s2_byteLogic_1_inputMask = s2_input_payload_selValid[1]; - assign s2_byteLogic_1_inputData = _zz_s2_byteLogic_1_inputData; - assign s2_byteLogic_1_outputMask = (s2_byteLogic_1_buffer_valid || (s2_input_valid && s2_byteLogic_1_inputMask)); - assign s2_byteLogic_1_outputData = (s2_byteLogic_1_buffer_valid ? s2_byteLogic_1_buffer_data : s2_byteLogic_1_inputData); - assign when_DmaSg_l1493_1 = (s2_byteLogic_1_inputMask && ((! io_output_consume) || s2_byteLogic_1_buffer_valid)); - assign s2_byteLogic_2_lastUsed = (4'b0010 == io_output_lastByteUsed); - assign s2_byteLogic_2_inputMask = s2_input_payload_selValid[2]; - assign s2_byteLogic_2_inputData = _zz_s2_byteLogic_2_inputData; - assign s2_byteLogic_2_outputMask = (s2_byteLogic_2_buffer_valid || (s2_input_valid && s2_byteLogic_2_inputMask)); - assign s2_byteLogic_2_outputData = (s2_byteLogic_2_buffer_valid ? s2_byteLogic_2_buffer_data : s2_byteLogic_2_inputData); - assign when_DmaSg_l1493_2 = (s2_byteLogic_2_inputMask && ((! io_output_consume) || s2_byteLogic_2_buffer_valid)); - assign s2_byteLogic_3_lastUsed = (4'b0011 == io_output_lastByteUsed); - assign s2_byteLogic_3_inputMask = s2_input_payload_selValid[3]; - assign s2_byteLogic_3_inputData = _zz_s2_byteLogic_3_inputData; - assign s2_byteLogic_3_outputMask = (s2_byteLogic_3_buffer_valid || (s2_input_valid && s2_byteLogic_3_inputMask)); - assign s2_byteLogic_3_outputData = (s2_byteLogic_3_buffer_valid ? s2_byteLogic_3_buffer_data : s2_byteLogic_3_inputData); - assign when_DmaSg_l1493_3 = (s2_byteLogic_3_inputMask && ((! io_output_consume) || s2_byteLogic_3_buffer_valid)); - assign s2_byteLogic_4_lastUsed = (4'b0100 == io_output_lastByteUsed); - assign s2_byteLogic_4_inputMask = s2_input_payload_selValid[4]; - assign s2_byteLogic_4_inputData = _zz_s2_byteLogic_4_inputData; - assign s2_byteLogic_4_outputMask = (s2_byteLogic_4_buffer_valid || (s2_input_valid && s2_byteLogic_4_inputMask)); - assign s2_byteLogic_4_outputData = (s2_byteLogic_4_buffer_valid ? s2_byteLogic_4_buffer_data : s2_byteLogic_4_inputData); - assign when_DmaSg_l1493_4 = (s2_byteLogic_4_inputMask && ((! io_output_consume) || s2_byteLogic_4_buffer_valid)); - assign s2_byteLogic_5_lastUsed = (4'b0101 == io_output_lastByteUsed); - assign s2_byteLogic_5_inputMask = s2_input_payload_selValid[5]; - assign s2_byteLogic_5_inputData = _zz_s2_byteLogic_5_inputData; - assign s2_byteLogic_5_outputMask = (s2_byteLogic_5_buffer_valid || (s2_input_valid && s2_byteLogic_5_inputMask)); - assign s2_byteLogic_5_outputData = (s2_byteLogic_5_buffer_valid ? s2_byteLogic_5_buffer_data : s2_byteLogic_5_inputData); - assign when_DmaSg_l1493_5 = (s2_byteLogic_5_inputMask && ((! io_output_consume) || s2_byteLogic_5_buffer_valid)); - assign s2_byteLogic_6_lastUsed = (4'b0110 == io_output_lastByteUsed); - assign s2_byteLogic_6_inputMask = s2_input_payload_selValid[6]; - assign s2_byteLogic_6_inputData = _zz_s2_byteLogic_6_inputData; - assign s2_byteLogic_6_outputMask = (s2_byteLogic_6_buffer_valid || (s2_input_valid && s2_byteLogic_6_inputMask)); - assign s2_byteLogic_6_outputData = (s2_byteLogic_6_buffer_valid ? s2_byteLogic_6_buffer_data : s2_byteLogic_6_inputData); - assign when_DmaSg_l1493_6 = (s2_byteLogic_6_inputMask && ((! io_output_consume) || s2_byteLogic_6_buffer_valid)); - assign s2_byteLogic_7_lastUsed = (4'b0111 == io_output_lastByteUsed); - assign s2_byteLogic_7_inputMask = s2_input_payload_selValid[7]; - assign s2_byteLogic_7_inputData = _zz_s2_byteLogic_7_inputData; - assign s2_byteLogic_7_outputMask = (s2_byteLogic_7_buffer_valid || (s2_input_valid && s2_byteLogic_7_inputMask)); - assign s2_byteLogic_7_outputData = (s2_byteLogic_7_buffer_valid ? s2_byteLogic_7_buffer_data : s2_byteLogic_7_inputData); - assign when_DmaSg_l1493_7 = (s2_byteLogic_7_inputMask && ((! io_output_consume) || s2_byteLogic_7_buffer_valid)); - assign s2_byteLogic_8_lastUsed = (4'b1000 == io_output_lastByteUsed); - assign s2_byteLogic_8_inputMask = s2_input_payload_selValid[8]; - assign s2_byteLogic_8_inputData = _zz_s2_byteLogic_8_inputData; - assign s2_byteLogic_8_outputMask = (s2_byteLogic_8_buffer_valid || (s2_input_valid && s2_byteLogic_8_inputMask)); - assign s2_byteLogic_8_outputData = (s2_byteLogic_8_buffer_valid ? s2_byteLogic_8_buffer_data : s2_byteLogic_8_inputData); - assign when_DmaSg_l1493_8 = (s2_byteLogic_8_inputMask && ((! io_output_consume) || s2_byteLogic_8_buffer_valid)); - assign s2_byteLogic_9_lastUsed = (4'b1001 == io_output_lastByteUsed); - assign s2_byteLogic_9_inputMask = s2_input_payload_selValid[9]; - assign s2_byteLogic_9_inputData = _zz_s2_byteLogic_9_inputData; - assign s2_byteLogic_9_outputMask = (s2_byteLogic_9_buffer_valid || (s2_input_valid && s2_byteLogic_9_inputMask)); - assign s2_byteLogic_9_outputData = (s2_byteLogic_9_buffer_valid ? s2_byteLogic_9_buffer_data : s2_byteLogic_9_inputData); - assign when_DmaSg_l1493_9 = (s2_byteLogic_9_inputMask && ((! io_output_consume) || s2_byteLogic_9_buffer_valid)); - assign s2_byteLogic_10_lastUsed = (4'b1010 == io_output_lastByteUsed); - assign s2_byteLogic_10_inputMask = s2_input_payload_selValid[10]; - assign s2_byteLogic_10_inputData = _zz_s2_byteLogic_10_inputData; - assign s2_byteLogic_10_outputMask = (s2_byteLogic_10_buffer_valid || (s2_input_valid && s2_byteLogic_10_inputMask)); - assign s2_byteLogic_10_outputData = (s2_byteLogic_10_buffer_valid ? s2_byteLogic_10_buffer_data : s2_byteLogic_10_inputData); - assign when_DmaSg_l1493_10 = (s2_byteLogic_10_inputMask && ((! io_output_consume) || s2_byteLogic_10_buffer_valid)); - assign s2_byteLogic_11_lastUsed = (4'b1011 == io_output_lastByteUsed); - assign s2_byteLogic_11_inputMask = s2_input_payload_selValid[11]; - assign s2_byteLogic_11_inputData = _zz_s2_byteLogic_11_inputData; - assign s2_byteLogic_11_outputMask = (s2_byteLogic_11_buffer_valid || (s2_input_valid && s2_byteLogic_11_inputMask)); - assign s2_byteLogic_11_outputData = (s2_byteLogic_11_buffer_valid ? s2_byteLogic_11_buffer_data : s2_byteLogic_11_inputData); - assign when_DmaSg_l1493_11 = (s2_byteLogic_11_inputMask && ((! io_output_consume) || s2_byteLogic_11_buffer_valid)); - assign s2_byteLogic_12_lastUsed = (4'b1100 == io_output_lastByteUsed); - assign s2_byteLogic_12_inputMask = s2_input_payload_selValid[12]; - assign s2_byteLogic_12_inputData = _zz_s2_byteLogic_12_inputData; - assign s2_byteLogic_12_outputMask = (s2_byteLogic_12_buffer_valid || (s2_input_valid && s2_byteLogic_12_inputMask)); - assign s2_byteLogic_12_outputData = (s2_byteLogic_12_buffer_valid ? s2_byteLogic_12_buffer_data : s2_byteLogic_12_inputData); - assign when_DmaSg_l1493_12 = (s2_byteLogic_12_inputMask && ((! io_output_consume) || s2_byteLogic_12_buffer_valid)); - assign s2_byteLogic_13_lastUsed = (4'b1101 == io_output_lastByteUsed); - assign s2_byteLogic_13_inputMask = s2_input_payload_selValid[13]; - assign s2_byteLogic_13_inputData = _zz_s2_byteLogic_13_inputData; - assign s2_byteLogic_13_outputMask = (s2_byteLogic_13_buffer_valid || (s2_input_valid && s2_byteLogic_13_inputMask)); - assign s2_byteLogic_13_outputData = (s2_byteLogic_13_buffer_valid ? s2_byteLogic_13_buffer_data : s2_byteLogic_13_inputData); - assign when_DmaSg_l1493_13 = (s2_byteLogic_13_inputMask && ((! io_output_consume) || s2_byteLogic_13_buffer_valid)); - assign s2_byteLogic_14_lastUsed = (4'b1110 == io_output_lastByteUsed); - assign s2_byteLogic_14_inputMask = s2_input_payload_selValid[14]; - assign s2_byteLogic_14_inputData = _zz_s2_byteLogic_14_inputData; - assign s2_byteLogic_14_outputMask = (s2_byteLogic_14_buffer_valid || (s2_input_valid && s2_byteLogic_14_inputMask)); - assign s2_byteLogic_14_outputData = (s2_byteLogic_14_buffer_valid ? s2_byteLogic_14_buffer_data : s2_byteLogic_14_inputData); - assign when_DmaSg_l1493_14 = (s2_byteLogic_14_inputMask && ((! io_output_consume) || s2_byteLogic_14_buffer_valid)); - assign s2_byteLogic_15_lastUsed = (4'b1111 == io_output_lastByteUsed); - assign s2_byteLogic_15_inputMask = s2_input_payload_selValid[15]; - assign s2_byteLogic_15_inputData = _zz_s2_byteLogic_15_inputData; - assign s2_byteLogic_15_outputMask = (s2_byteLogic_15_buffer_valid || (s2_input_valid && s2_byteLogic_15_inputMask)); - assign s2_byteLogic_15_outputData = (s2_byteLogic_15_buffer_valid ? s2_byteLogic_15_buffer_data : s2_byteLogic_15_inputData); - assign when_DmaSg_l1493_15 = (s2_byteLogic_15_inputMask && ((! io_output_consume) || s2_byteLogic_15_buffer_valid)); - assign _zz_io_output_usedUntil = (((((((s2_byteLogic_1_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_5_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_9_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_15_lastUsed); - assign _zz_io_output_usedUntil_1 = (((((((s2_byteLogic_2_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); - assign _zz_io_output_usedUntil_2 = (((((((s2_byteLogic_4_lastUsed || s2_byteLogic_5_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); - assign _zz_io_output_usedUntil_3 = (((((((s2_byteLogic_8_lastUsed || s2_byteLogic_9_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); - assign io_output_usedUntil = _zz_io_output_usedUntil_4; - always @(posedge clk) begin - if(reset) begin - io_input_rValid <= 1'b0; - s0_output_rValid <= 1'b0; - s1_output_rValid <= 1'b0; - end else begin - if(io_input_ready) begin - io_input_rValid <= io_input_valid; - end - if(io_flush) begin - io_input_rValid <= 1'b0; - end - if(s0_output_ready) begin - s0_output_rValid <= s0_output_valid; - end - if(io_flush) begin - s0_output_rValid <= 1'b0; - end - if(s1_output_ready) begin - s1_output_rValid <= s1_output_valid; - end - if(io_flush) begin - s1_output_rValid <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(io_input_ready) begin - io_input_rData_data <= io_input_payload_data; - io_input_rData_mask <= io_input_payload_mask; - end - if(s0_output_ready) begin - s0_output_rData_cmd_data <= s0_output_payload_cmd_data; - s0_output_rData_cmd_mask <= s0_output_payload_cmd_mask; - s0_output_rData_countOnes_0 <= s0_output_payload_countOnes_0; - s0_output_rData_countOnes_1 <= s0_output_payload_countOnes_1; - s0_output_rData_countOnes_2 <= s0_output_payload_countOnes_2; - s0_output_rData_countOnes_3 <= s0_output_payload_countOnes_3; - s0_output_rData_countOnes_4 <= s0_output_payload_countOnes_4; - s0_output_rData_countOnes_5 <= s0_output_payload_countOnes_5; - s0_output_rData_countOnes_6 <= s0_output_payload_countOnes_6; - s0_output_rData_countOnes_7 <= s0_output_payload_countOnes_7; - s0_output_rData_countOnes_8 <= s0_output_payload_countOnes_8; - s0_output_rData_countOnes_9 <= s0_output_payload_countOnes_9; - s0_output_rData_countOnes_10 <= s0_output_payload_countOnes_10; - s0_output_rData_countOnes_11 <= s0_output_payload_countOnes_11; - s0_output_rData_countOnes_12 <= s0_output_payload_countOnes_12; - s0_output_rData_countOnes_13 <= s0_output_payload_countOnes_13; - s0_output_rData_countOnes_14 <= s0_output_payload_countOnes_14; - s0_output_rData_countOnes_15 <= s0_output_payload_countOnes_15; - end - if(s1_input_fire) begin - s1_offset <= s1_offsetNext[3:0]; - end - if(io_flush) begin - s1_offset <= io_offset; - end - if(s1_input_fire) begin - s1_byteCounter <= (s1_byteCounter + _zz_s1_byteCounter); - end - if(io_flush) begin - s1_byteCounter <= 13'h0; - end - if(s1_output_ready) begin - s1_output_rData_cmd_data <= s1_output_payload_cmd_data; - s1_output_rData_cmd_mask <= s1_output_payload_cmd_mask; - s1_output_rData_index_0 <= s1_output_payload_index_0; - s1_output_rData_index_1 <= s1_output_payload_index_1; - s1_output_rData_index_2 <= s1_output_payload_index_2; - s1_output_rData_index_3 <= s1_output_payload_index_3; - s1_output_rData_index_4 <= s1_output_payload_index_4; - s1_output_rData_index_5 <= s1_output_payload_index_5; - s1_output_rData_index_6 <= s1_output_payload_index_6; - s1_output_rData_index_7 <= s1_output_payload_index_7; - s1_output_rData_index_8 <= s1_output_payload_index_8; - s1_output_rData_index_9 <= s1_output_payload_index_9; - s1_output_rData_index_10 <= s1_output_payload_index_10; - s1_output_rData_index_11 <= s1_output_payload_index_11; - s1_output_rData_index_12 <= s1_output_payload_index_12; - s1_output_rData_index_13 <= s1_output_payload_index_13; - s1_output_rData_index_14 <= s1_output_payload_index_14; - s1_output_rData_index_15 <= s1_output_payload_index_15; - s1_output_rData_last <= s1_output_payload_last; - s1_output_rData_sel_0 <= s1_output_payload_sel_0; - s1_output_rData_sel_1 <= s1_output_payload_sel_1; - s1_output_rData_sel_2 <= s1_output_payload_sel_2; - s1_output_rData_sel_3 <= s1_output_payload_sel_3; - s1_output_rData_sel_4 <= s1_output_payload_sel_4; - s1_output_rData_sel_5 <= s1_output_payload_sel_5; - s1_output_rData_sel_6 <= s1_output_payload_sel_6; - s1_output_rData_sel_7 <= s1_output_payload_sel_7; - s1_output_rData_sel_8 <= s1_output_payload_sel_8; - s1_output_rData_sel_9 <= s1_output_payload_sel_9; - s1_output_rData_sel_10 <= s1_output_payload_sel_10; - s1_output_rData_sel_11 <= s1_output_payload_sel_11; - s1_output_rData_sel_12 <= s1_output_payload_sel_12; - s1_output_rData_sel_13 <= s1_output_payload_sel_13; - s1_output_rData_sel_14 <= s1_output_payload_sel_14; - s1_output_rData_sel_15 <= s1_output_payload_sel_15; - s1_output_rData_selValid <= s1_output_payload_selValid; - end - if(io_output_consume) begin - s2_byteLogic_0_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_0_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493) begin - s2_byteLogic_0_buffer_valid <= 1'b1; - s2_byteLogic_0_buffer_data <= s2_byteLogic_0_inputData; - end - end - if(io_flush) begin - s2_byteLogic_0_buffer_valid <= (4'b0000 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_1_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_1_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_1) begin - s2_byteLogic_1_buffer_valid <= 1'b1; - s2_byteLogic_1_buffer_data <= s2_byteLogic_1_inputData; - end - end - if(io_flush) begin - s2_byteLogic_1_buffer_valid <= (4'b0001 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_2_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_2_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_2) begin - s2_byteLogic_2_buffer_valid <= 1'b1; - s2_byteLogic_2_buffer_data <= s2_byteLogic_2_inputData; - end - end - if(io_flush) begin - s2_byteLogic_2_buffer_valid <= (4'b0010 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_3_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_3_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_3) begin - s2_byteLogic_3_buffer_valid <= 1'b1; - s2_byteLogic_3_buffer_data <= s2_byteLogic_3_inputData; - end - end - if(io_flush) begin - s2_byteLogic_3_buffer_valid <= (4'b0011 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_4_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_4_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_4) begin - s2_byteLogic_4_buffer_valid <= 1'b1; - s2_byteLogic_4_buffer_data <= s2_byteLogic_4_inputData; - end - end - if(io_flush) begin - s2_byteLogic_4_buffer_valid <= (4'b0100 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_5_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_5_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_5) begin - s2_byteLogic_5_buffer_valid <= 1'b1; - s2_byteLogic_5_buffer_data <= s2_byteLogic_5_inputData; - end - end - if(io_flush) begin - s2_byteLogic_5_buffer_valid <= (4'b0101 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_6_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_6_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_6) begin - s2_byteLogic_6_buffer_valid <= 1'b1; - s2_byteLogic_6_buffer_data <= s2_byteLogic_6_inputData; - end - end - if(io_flush) begin - s2_byteLogic_6_buffer_valid <= (4'b0110 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_7_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_7_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_7) begin - s2_byteLogic_7_buffer_valid <= 1'b1; - s2_byteLogic_7_buffer_data <= s2_byteLogic_7_inputData; - end - end - if(io_flush) begin - s2_byteLogic_7_buffer_valid <= (4'b0111 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_8_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_8_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_8) begin - s2_byteLogic_8_buffer_valid <= 1'b1; - s2_byteLogic_8_buffer_data <= s2_byteLogic_8_inputData; - end - end - if(io_flush) begin - s2_byteLogic_8_buffer_valid <= (4'b1000 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_9_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_9_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_9) begin - s2_byteLogic_9_buffer_valid <= 1'b1; - s2_byteLogic_9_buffer_data <= s2_byteLogic_9_inputData; - end - end - if(io_flush) begin - s2_byteLogic_9_buffer_valid <= (4'b1001 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_10_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_10_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_10) begin - s2_byteLogic_10_buffer_valid <= 1'b1; - s2_byteLogic_10_buffer_data <= s2_byteLogic_10_inputData; - end - end - if(io_flush) begin - s2_byteLogic_10_buffer_valid <= (4'b1010 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_11_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_11_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_11) begin - s2_byteLogic_11_buffer_valid <= 1'b1; - s2_byteLogic_11_buffer_data <= s2_byteLogic_11_inputData; - end - end - if(io_flush) begin - s2_byteLogic_11_buffer_valid <= (4'b1011 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_12_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_12_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_12) begin - s2_byteLogic_12_buffer_valid <= 1'b1; - s2_byteLogic_12_buffer_data <= s2_byteLogic_12_inputData; - end - end - if(io_flush) begin - s2_byteLogic_12_buffer_valid <= (4'b1100 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_13_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_13_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_13) begin - s2_byteLogic_13_buffer_valid <= 1'b1; - s2_byteLogic_13_buffer_data <= s2_byteLogic_13_inputData; - end - end - if(io_flush) begin - s2_byteLogic_13_buffer_valid <= (4'b1101 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_14_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_14_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_14) begin - s2_byteLogic_14_buffer_valid <= 1'b1; - s2_byteLogic_14_buffer_data <= s2_byteLogic_14_inputData; - end - end - if(io_flush) begin - s2_byteLogic_14_buffer_valid <= (4'b1110 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_15_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_15_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_15) begin - s2_byteLogic_15_buffer_valid <= 1'b1; - s2_byteLogic_15_buffer_data <= s2_byteLogic_15_inputData; - end - end - if(io_flush) begin - s2_byteLogic_15_buffer_valid <= (4'b1111 < io_offset); - end - end - - -endmodule - -module EfxDMA_DmaMemoryCore_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_writes_0_cmd_valid, - output wire io_writes_0_cmd_ready, - input wire [9:0] io_writes_0_cmd_payload_address, - input wire [63:0] io_writes_0_cmd_payload_data, - input wire [7:0] io_writes_0_cmd_payload_mask, - input wire [1:0] io_writes_0_cmd_payload_priority, - input wire [6:0] io_writes_0_cmd_payload_context, - output wire io_writes_0_rsp_valid, - output wire [6:0] io_writes_0_rsp_payload_context, - input wire io_writes_1_cmd_valid, - output wire io_writes_1_cmd_ready, - input wire [9:0] io_writes_1_cmd_payload_address, - input wire [127:0] io_writes_1_cmd_payload_data, - input wire [15:0] io_writes_1_cmd_payload_mask, - input wire [6:0] io_writes_1_cmd_payload_context, - output wire io_writes_1_rsp_valid, - output wire [6:0] io_writes_1_rsp_payload_context, - input wire io_reads_0_cmd_valid, - output wire io_reads_0_cmd_ready, - input wire [9:0] io_reads_0_cmd_payload_address, - input wire [1:0] io_reads_0_cmd_payload_priority, - input wire [2:0] io_reads_0_cmd_payload_context, - output wire io_reads_0_rsp_valid, - input wire io_reads_0_rsp_ready, - output wire [63:0] io_reads_0_rsp_payload_data, - output wire [7:0] io_reads_0_rsp_payload_mask, - output wire [2:0] io_reads_0_rsp_payload_context, - input wire io_reads_1_cmd_valid, - output wire io_reads_1_cmd_ready, - input wire [9:0] io_reads_1_cmd_payload_address, - input wire [11:0] io_reads_1_cmd_payload_context, - output wire io_reads_1_rsp_valid, - input wire io_reads_1_rsp_ready, - output wire [127:0] io_reads_1_rsp_payload_data, - output wire [15:0] io_reads_1_rsp_payload_mask, - output wire [11:0] io_reads_1_rsp_payload_context, - input wire clk, - input wire reset -); - - reg [71:0] banks_0_ram_spinal_port1; - reg [71:0] banks_1_ram_spinal_port1; - wire [71:0] _zz_banks_0_ram_port; - wire [71:0] _zz_banks_1_ram_port; - wire [3:0] _zz_write_ports_0_priority_value; - wire [9:0] _zz_when_MemoryCore_l136; - wire [9:0] _zz_when_MemoryCore_l136_1; - reg [63:0] _zz_read_ports_0_buffer_bufferIn_payload_data; - reg [7:0] _zz_read_ports_0_buffer_bufferIn_payload_mask; - wire [3:0] _zz_read_ports_0_priority_value; - wire [9:0] _zz_when_MemoryCore_l221; - wire [9:0] _zz_when_MemoryCore_l221_1; - reg _zz_1; - reg _zz_2; - reg banks_0_write_valid; - reg [8:0] banks_0_write_payload_address; - reg [63:0] banks_0_write_payload_data_data; - reg [7:0] banks_0_write_payload_data_mask; - wire banks_0_read_cmd_valid; - wire [8:0] banks_0_read_cmd_payload; - wire [63:0] banks_0_read_rsp_data; - wire [7:0] banks_0_read_rsp_mask; - wire [71:0] _zz_banks_0_read_rsp_data; - wire banks_0_writeOr_value_valid; - wire [8:0] banks_0_writeOr_value_payload_address; - wire [63:0] banks_0_writeOr_value_payload_data_data; - wire [7:0] banks_0_writeOr_value_payload_data_mask; - wire banks_0_readOr_value_valid; - wire [8:0] banks_0_readOr_value_payload; - reg banks_1_write_valid; - reg [8:0] banks_1_write_payload_address; - reg [63:0] banks_1_write_payload_data_data; - reg [7:0] banks_1_write_payload_data_mask; - wire banks_1_read_cmd_valid; - wire [8:0] banks_1_read_cmd_payload; - wire [63:0] banks_1_read_rsp_data; - wire [7:0] banks_1_read_rsp_mask; - wire [71:0] _zz_banks_1_read_rsp_data; - wire banks_1_writeOr_value_valid; - wire [8:0] banks_1_writeOr_value_payload_address; - wire [63:0] banks_1_writeOr_value_payload_data_data; - wire [7:0] banks_1_writeOr_value_payload_data_mask; - wire banks_1_readOr_value_valid; - wire [8:0] banks_1_readOr_value_payload; - reg [3:0] write_ports_0_priority_value; - wire write_nodes_0_0_priority; - wire write_nodes_0_0_conflict; - wire write_nodes_0_1_priority; - wire write_nodes_0_1_conflict; - wire write_nodes_1_0_priority; - wire write_nodes_1_0_conflict; - wire write_nodes_1_1_priority; - wire write_nodes_1_1_conflict; - wire [0:0] write_arbiter_0_losedAgainst; - reg write_arbiter_0_doIt; - reg _zz_banks_0_writeOr_value_valid; - reg [8:0] _zz_banks_0_writeOr_value_valid_1; - reg [63:0] _zz_banks_0_writeOr_value_valid_2; - reg [7:0] _zz_banks_0_writeOr_value_valid_3; - wire when_MemoryCore_l136; - reg _zz_banks_1_writeOr_value_valid; - reg [8:0] _zz_banks_1_writeOr_value_valid_1; - reg [63:0] _zz_banks_1_writeOr_value_valid_2; - reg [7:0] _zz_banks_1_writeOr_value_valid_3; - wire when_MemoryCore_l136_1; - reg write_arbiter_0_doIt_regNext; - reg [6:0] io_writes_0_cmd_payload_context_regNext; - wire [0:0] write_arbiter_1_losedAgainst; - reg write_arbiter_1_doIt; - reg _zz_banks_0_writeOr_value_valid_4; - reg [8:0] _zz_banks_0_writeOr_value_valid_5; - reg [63:0] _zz_banks_0_writeOr_value_valid_6; - reg [7:0] _zz_banks_0_writeOr_value_valid_7; - wire when_MemoryCore_l136_2; - reg _zz_banks_1_writeOr_value_valid_4; - reg [8:0] _zz_banks_1_writeOr_value_valid_5; - reg [63:0] _zz_banks_1_writeOr_value_valid_6; - reg [7:0] _zz_banks_1_writeOr_value_valid_7; - wire when_MemoryCore_l136_3; - reg write_arbiter_1_doIt_regNext; - reg [6:0] io_writes_1_cmd_payload_context_regNext; - wire read_ports_0_buffer_s0_valid; - wire [2:0] read_ports_0_buffer_s0_payload_context; - wire [9:0] read_ports_0_buffer_s0_payload_address; - reg read_ports_0_buffer_s1_valid; - reg [2:0] read_ports_0_buffer_s1_payload_context; - reg [9:0] read_ports_0_buffer_s1_payload_address; - wire [0:0] read_ports_0_buffer_groupSel; - wire read_ports_0_buffer_bufferIn_valid; - wire read_ports_0_buffer_bufferIn_ready; - wire [63:0] read_ports_0_buffer_bufferIn_payload_data; - wire [7:0] read_ports_0_buffer_bufferIn_payload_mask; - wire [2:0] read_ports_0_buffer_bufferIn_payload_context; - wire read_ports_0_buffer_bufferOut_valid; - wire read_ports_0_buffer_bufferOut_ready; - wire [63:0] read_ports_0_buffer_bufferOut_payload_data; - wire [7:0] read_ports_0_buffer_bufferOut_payload_mask; - wire [2:0] read_ports_0_buffer_bufferOut_payload_context; - reg read_ports_0_buffer_bufferIn_rValidN; - reg [63:0] read_ports_0_buffer_bufferIn_rData_data; - reg [7:0] read_ports_0_buffer_bufferIn_rData_mask; - reg [2:0] read_ports_0_buffer_bufferIn_rData_context; - wire read_ports_0_buffer_full; - wire _zz_io_reads_0_cmd_ready; - wire read_ports_0_cmd_valid; - wire read_ports_0_cmd_ready; - wire [9:0] read_ports_0_cmd_payload_address; - wire [1:0] read_ports_0_cmd_payload_priority; - wire [2:0] read_ports_0_cmd_payload_context; - reg [3:0] read_ports_0_priority_value; - wire read_ports_1_buffer_s0_valid; - wire [11:0] read_ports_1_buffer_s0_payload_context; - wire [9:0] read_ports_1_buffer_s0_payload_address; - reg read_ports_1_buffer_s1_valid; - reg [11:0] read_ports_1_buffer_s1_payload_context; - reg [9:0] read_ports_1_buffer_s1_payload_address; - wire read_ports_1_buffer_bufferIn_valid; - wire read_ports_1_buffer_bufferIn_ready; - wire [127:0] read_ports_1_buffer_bufferIn_payload_data; - wire [15:0] read_ports_1_buffer_bufferIn_payload_mask; - wire [11:0] read_ports_1_buffer_bufferIn_payload_context; - wire read_ports_1_buffer_bufferOut_valid; - wire read_ports_1_buffer_bufferOut_ready; - wire [127:0] read_ports_1_buffer_bufferOut_payload_data; - wire [15:0] read_ports_1_buffer_bufferOut_payload_mask; - wire [11:0] read_ports_1_buffer_bufferOut_payload_context; - reg read_ports_1_buffer_bufferIn_rValidN; - reg [127:0] read_ports_1_buffer_bufferIn_rData_data; - reg [15:0] read_ports_1_buffer_bufferIn_rData_mask; - reg [11:0] read_ports_1_buffer_bufferIn_rData_context; - wire read_ports_1_buffer_full; - wire _zz_io_reads_1_cmd_ready; - wire read_ports_1_cmd_valid; - wire read_ports_1_cmd_ready; - wire [9:0] read_ports_1_cmd_payload_address; - wire [11:0] read_ports_1_cmd_payload_context; - wire read_nodes_0_0_priority; - wire read_nodes_0_0_conflict; - wire read_nodes_0_1_priority; - wire read_nodes_0_1_conflict; - wire read_nodes_1_0_priority; - wire read_nodes_1_0_conflict; - wire read_nodes_1_1_priority; - wire read_nodes_1_1_conflict; - wire [0:0] read_arbiter_0_losedAgainst; - wire read_arbiter_0_doIt; - reg _zz_banks_0_readOr_value_valid; - reg [8:0] _zz_banks_0_readOr_value_valid_1; - wire when_MemoryCore_l221; - reg _zz_banks_1_readOr_value_valid; - reg [8:0] _zz_banks_1_readOr_value_valid_1; - wire when_MemoryCore_l221_1; - wire [0:0] read_arbiter_1_losedAgainst; - wire read_arbiter_1_doIt; - reg _zz_banks_0_readOr_value_valid_2; - reg [8:0] _zz_banks_0_readOr_value_valid_3; - wire when_MemoryCore_l221_2; - reg _zz_banks_1_readOr_value_valid_2; - reg [8:0] _zz_banks_1_readOr_value_valid_3; - wire when_MemoryCore_l221_3; - reg [9:0] initialiser_counter; - wire initialiser_done; - wire when_MemoryCore_l239; - wire [71:0] _zz_banks_0_write_payload_data_data; - wire [71:0] _zz_banks_1_write_payload_data_data; - wire [81:0] _zz_banks_0_writeOr_value_valid_8; - wire [80:0] _zz_banks_0_writeOr_value_payload_address; - wire [71:0] _zz_banks_0_writeOr_value_payload_data_data; - wire [9:0] _zz_banks_0_readOr_value_valid_4; - wire [81:0] _zz_banks_1_writeOr_value_valid_8; - wire [80:0] _zz_banks_1_writeOr_value_payload_address; - wire [71:0] _zz_banks_1_writeOr_value_payload_data_data; - wire [9:0] _zz_banks_1_readOr_value_valid_4; - (* ram_style = "block" *) reg [71:0] banks_0_ram [0:511]; - (* ram_style = "block" *) reg [71:0] banks_1_ram [0:511]; - - assign _zz_write_ports_0_priority_value = {2'd0, io_writes_0_cmd_payload_priority}; - assign _zz_when_MemoryCore_l136 = (io_writes_0_cmd_payload_address ^ 10'h0); - assign _zz_when_MemoryCore_l136_1 = (io_writes_0_cmd_payload_address ^ 10'h001); - assign _zz_read_ports_0_priority_value = {2'd0, read_ports_0_cmd_payload_priority}; - assign _zz_when_MemoryCore_l221 = (read_ports_0_cmd_payload_address ^ 10'h0); - assign _zz_when_MemoryCore_l221_1 = (read_ports_0_cmd_payload_address ^ 10'h001); - assign _zz_banks_0_ram_port = {banks_0_write_payload_data_mask,banks_0_write_payload_data_data}; - assign _zz_banks_1_ram_port = {banks_1_write_payload_data_mask,banks_1_write_payload_data_data}; - always @(posedge clk) begin - if(_zz_2) begin - banks_0_ram[banks_0_write_payload_address] <= _zz_banks_0_ram_port; - end - end - - always @(posedge clk) begin - if(banks_0_read_cmd_valid) begin - banks_0_ram_spinal_port1 <= banks_0_ram[banks_0_read_cmd_payload]; - end - end - - always @(posedge clk) begin - if(_zz_1) begin - banks_1_ram[banks_1_write_payload_address] <= _zz_banks_1_ram_port; - end - end - - always @(posedge clk) begin - if(banks_1_read_cmd_valid) begin - banks_1_ram_spinal_port1 <= banks_1_ram[banks_1_read_cmd_payload]; - end - end - - initial begin - `ifndef SYNTHESIS - write_ports_0_priority_value = {$urandom}; - read_ports_0_priority_value = {$urandom}; - `endif - end - - always @(*) begin - case(read_ports_0_buffer_groupSel) - 1'b0 : begin - _zz_read_ports_0_buffer_bufferIn_payload_data = banks_0_read_rsp_data; - _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_0_read_rsp_mask; - end - default : begin - _zz_read_ports_0_buffer_bufferIn_payload_data = banks_1_read_rsp_data; - _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_1_read_rsp_mask; - end - endcase - end - - always @(*) begin - _zz_1 = 1'b0; - if(banks_1_write_valid) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(banks_0_write_valid) begin - _zz_2 = 1'b1; - end - end - - assign _zz_banks_0_read_rsp_data = banks_0_ram_spinal_port1; - assign banks_0_read_rsp_data = _zz_banks_0_read_rsp_data[63 : 0]; - assign banks_0_read_rsp_mask = _zz_banks_0_read_rsp_data[71 : 64]; - always @(*) begin - banks_0_write_valid = banks_0_writeOr_value_valid; - if(when_MemoryCore_l239) begin - banks_0_write_valid = 1'b1; - end - end - - always @(*) begin - banks_0_write_payload_address = banks_0_writeOr_value_payload_address; - if(when_MemoryCore_l239) begin - banks_0_write_payload_address = initialiser_counter[8:0]; - end - end - - always @(*) begin - banks_0_write_payload_data_data = banks_0_writeOr_value_payload_data_data; - if(when_MemoryCore_l239) begin - banks_0_write_payload_data_data = _zz_banks_0_write_payload_data_data[63 : 0]; - end - end - - always @(*) begin - banks_0_write_payload_data_mask = banks_0_writeOr_value_payload_data_mask; - if(when_MemoryCore_l239) begin - banks_0_write_payload_data_mask = _zz_banks_0_write_payload_data_data[71 : 64]; - end - end - - assign banks_0_read_cmd_valid = banks_0_readOr_value_valid; - assign banks_0_read_cmd_payload = banks_0_readOr_value_payload; - assign _zz_banks_1_read_rsp_data = banks_1_ram_spinal_port1; - assign banks_1_read_rsp_data = _zz_banks_1_read_rsp_data[63 : 0]; - assign banks_1_read_rsp_mask = _zz_banks_1_read_rsp_data[71 : 64]; - always @(*) begin - banks_1_write_valid = banks_1_writeOr_value_valid; - if(when_MemoryCore_l239) begin - banks_1_write_valid = 1'b1; - end - end - - always @(*) begin - banks_1_write_payload_address = banks_1_writeOr_value_payload_address; - if(when_MemoryCore_l239) begin - banks_1_write_payload_address = initialiser_counter[8:0]; - end - end - - always @(*) begin - banks_1_write_payload_data_data = banks_1_writeOr_value_payload_data_data; - if(when_MemoryCore_l239) begin - banks_1_write_payload_data_data = _zz_banks_1_write_payload_data_data[63 : 0]; - end - end - - always @(*) begin - banks_1_write_payload_data_mask = banks_1_writeOr_value_payload_data_mask; - if(when_MemoryCore_l239) begin - banks_1_write_payload_data_mask = _zz_banks_1_write_payload_data_data[71 : 64]; - end - end - - assign banks_1_read_cmd_valid = banks_1_readOr_value_valid; - assign banks_1_read_cmd_payload = banks_1_readOr_value_payload; - assign write_nodes_0_1_priority = 1'b0; - assign write_nodes_1_0_priority = 1'b1; - assign write_nodes_0_1_conflict = ((io_writes_0_cmd_valid && io_writes_1_cmd_valid) && (((io_writes_0_cmd_payload_address ^ io_writes_1_cmd_payload_address) & 10'h0) == 10'h0)); - assign write_nodes_1_0_conflict = write_nodes_0_1_conflict; - assign write_arbiter_0_losedAgainst = (write_nodes_0_1_conflict && (! write_nodes_0_1_priority)); - always @(*) begin - write_arbiter_0_doIt = (io_writes_0_cmd_valid && (write_arbiter_0_losedAgainst == 1'b0)); - if(when_MemoryCore_l239) begin - write_arbiter_0_doIt = 1'b0; - end - end - - assign when_MemoryCore_l136 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid = 1'b1; - end else begin - _zz_banks_0_writeOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_writeOr_value_valid_1 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_2 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_3 = 8'h0; - end - end - - assign when_MemoryCore_l136_1 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136_1[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid = 1'b1; - end else begin - _zz_banks_1_writeOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_writeOr_value_valid_1 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; - end else begin - _zz_banks_1_writeOr_value_valid_2 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; - end else begin - _zz_banks_1_writeOr_value_valid_3 = 8'h0; - end - end - - assign io_writes_0_cmd_ready = write_arbiter_0_doIt; - assign io_writes_0_rsp_valid = write_arbiter_0_doIt_regNext; - assign io_writes_0_rsp_payload_context = io_writes_0_cmd_payload_context_regNext; - assign write_arbiter_1_losedAgainst = (write_nodes_1_0_conflict && (! write_nodes_1_0_priority)); - always @(*) begin - write_arbiter_1_doIt = (io_writes_1_cmd_valid && (write_arbiter_1_losedAgainst == 1'b0)); - if(when_MemoryCore_l239) begin - write_arbiter_1_doIt = 1'b0; - end - end - - assign when_MemoryCore_l136_2 = (write_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_4 = 1'b1; - end else begin - _zz_banks_0_writeOr_value_valid_4 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_writeOr_value_valid_5 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[63 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_6 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[7 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_7 = 8'h0; - end - end - - assign when_MemoryCore_l136_3 = (write_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_4 = 1'b1; - end else begin - _zz_banks_1_writeOr_value_valid_4 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_writeOr_value_valid_5 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[127 : 64]; - end else begin - _zz_banks_1_writeOr_value_valid_6 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[15 : 8]; - end else begin - _zz_banks_1_writeOr_value_valid_7 = 8'h0; - end - end - - assign io_writes_1_cmd_ready = write_arbiter_1_doIt; - assign io_writes_1_rsp_valid = write_arbiter_1_doIt_regNext; - assign io_writes_1_rsp_payload_context = io_writes_1_cmd_payload_context_regNext; - assign read_ports_0_buffer_groupSel = read_ports_0_buffer_s1_payload_address[0 : 0]; - assign read_ports_0_buffer_bufferIn_valid = read_ports_0_buffer_s1_valid; - assign read_ports_0_buffer_bufferIn_payload_context = read_ports_0_buffer_s1_payload_context; - assign read_ports_0_buffer_bufferIn_payload_data = _zz_read_ports_0_buffer_bufferIn_payload_data; - assign read_ports_0_buffer_bufferIn_payload_mask = _zz_read_ports_0_buffer_bufferIn_payload_mask; - assign read_ports_0_buffer_bufferIn_ready = read_ports_0_buffer_bufferIn_rValidN; - assign read_ports_0_buffer_bufferOut_valid = (read_ports_0_buffer_bufferIn_valid || (! read_ports_0_buffer_bufferIn_rValidN)); - assign read_ports_0_buffer_bufferOut_payload_data = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_data : read_ports_0_buffer_bufferIn_rData_data); - assign read_ports_0_buffer_bufferOut_payload_mask = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_mask : read_ports_0_buffer_bufferIn_rData_mask); - assign read_ports_0_buffer_bufferOut_payload_context = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_context : read_ports_0_buffer_bufferIn_rData_context); - assign io_reads_0_rsp_valid = read_ports_0_buffer_bufferOut_valid; - assign read_ports_0_buffer_bufferOut_ready = io_reads_0_rsp_ready; - assign io_reads_0_rsp_payload_data = read_ports_0_buffer_bufferOut_payload_data; - assign io_reads_0_rsp_payload_mask = read_ports_0_buffer_bufferOut_payload_mask; - assign io_reads_0_rsp_payload_context = read_ports_0_buffer_bufferOut_payload_context; - assign read_ports_0_buffer_full = (read_ports_0_buffer_bufferOut_valid && (! read_ports_0_buffer_bufferOut_ready)); - assign _zz_io_reads_0_cmd_ready = (! read_ports_0_buffer_full); - assign read_ports_0_cmd_valid = (io_reads_0_cmd_valid && _zz_io_reads_0_cmd_ready); - assign io_reads_0_cmd_ready = (read_ports_0_cmd_ready && _zz_io_reads_0_cmd_ready); - assign read_ports_0_cmd_payload_address = io_reads_0_cmd_payload_address; - assign read_ports_0_cmd_payload_priority = io_reads_0_cmd_payload_priority; - assign read_ports_0_cmd_payload_context = io_reads_0_cmd_payload_context; - assign read_ports_1_buffer_bufferIn_valid = read_ports_1_buffer_s1_valid; - assign read_ports_1_buffer_bufferIn_payload_context = read_ports_1_buffer_s1_payload_context; - assign read_ports_1_buffer_bufferIn_payload_data = {banks_1_read_rsp_data,banks_0_read_rsp_data}; - assign read_ports_1_buffer_bufferIn_payload_mask = {banks_1_read_rsp_mask,banks_0_read_rsp_mask}; - assign read_ports_1_buffer_bufferIn_ready = read_ports_1_buffer_bufferIn_rValidN; - assign read_ports_1_buffer_bufferOut_valid = (read_ports_1_buffer_bufferIn_valid || (! read_ports_1_buffer_bufferIn_rValidN)); - assign read_ports_1_buffer_bufferOut_payload_data = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_data : read_ports_1_buffer_bufferIn_rData_data); - assign read_ports_1_buffer_bufferOut_payload_mask = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_mask : read_ports_1_buffer_bufferIn_rData_mask); - assign read_ports_1_buffer_bufferOut_payload_context = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_context : read_ports_1_buffer_bufferIn_rData_context); - assign io_reads_1_rsp_valid = read_ports_1_buffer_bufferOut_valid; - assign read_ports_1_buffer_bufferOut_ready = io_reads_1_rsp_ready; - assign io_reads_1_rsp_payload_data = read_ports_1_buffer_bufferOut_payload_data; - assign io_reads_1_rsp_payload_mask = read_ports_1_buffer_bufferOut_payload_mask; - assign io_reads_1_rsp_payload_context = read_ports_1_buffer_bufferOut_payload_context; - assign read_ports_1_buffer_full = (read_ports_1_buffer_bufferOut_valid && (! read_ports_1_buffer_bufferOut_ready)); - assign _zz_io_reads_1_cmd_ready = (! read_ports_1_buffer_full); - assign read_ports_1_cmd_valid = (io_reads_1_cmd_valid && _zz_io_reads_1_cmd_ready); - assign io_reads_1_cmd_ready = (read_ports_1_cmd_ready && _zz_io_reads_1_cmd_ready); - assign read_ports_1_cmd_payload_address = io_reads_1_cmd_payload_address; - assign read_ports_1_cmd_payload_context = io_reads_1_cmd_payload_context; - assign read_nodes_0_1_priority = 1'b0; - assign read_nodes_1_0_priority = 1'b1; - assign read_nodes_0_1_conflict = ((read_ports_0_cmd_valid && read_ports_1_cmd_valid) && (((read_ports_0_cmd_payload_address ^ io_reads_1_cmd_payload_address) & 10'h0) == 10'h0)); - assign read_nodes_1_0_conflict = read_nodes_0_1_conflict; - assign read_arbiter_0_losedAgainst = (read_nodes_0_1_conflict && (! read_nodes_0_1_priority)); - assign read_arbiter_0_doIt = (read_ports_0_cmd_valid && (read_arbiter_0_losedAgainst == 1'b0)); - assign when_MemoryCore_l221 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l221) begin - _zz_banks_0_readOr_value_valid = 1'b1; - end else begin - _zz_banks_0_readOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221) begin - _zz_banks_0_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_readOr_value_valid_1 = 9'h0; - end - end - - assign when_MemoryCore_l221_1 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221_1[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l221_1) begin - _zz_banks_1_readOr_value_valid = 1'b1; - end else begin - _zz_banks_1_readOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221_1) begin - _zz_banks_1_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_readOr_value_valid_1 = 9'h0; - end - end - - assign read_ports_0_cmd_ready = read_arbiter_0_doIt; - assign read_ports_0_buffer_s0_valid = read_arbiter_0_doIt; - assign read_ports_0_buffer_s0_payload_context = read_ports_0_cmd_payload_context; - assign read_ports_0_buffer_s0_payload_address = read_ports_0_cmd_payload_address; - assign read_arbiter_1_losedAgainst = (read_nodes_1_0_conflict && (! read_nodes_1_0_priority)); - assign read_arbiter_1_doIt = (read_ports_1_cmd_valid && (read_arbiter_1_losedAgainst == 1'b0)); - assign when_MemoryCore_l221_2 = (read_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l221_2) begin - _zz_banks_0_readOr_value_valid_2 = 1'b1; - end else begin - _zz_banks_0_readOr_value_valid_2 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221_2) begin - _zz_banks_0_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_readOr_value_valid_3 = 9'h0; - end - end - - assign when_MemoryCore_l221_3 = (read_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l221_3) begin - _zz_banks_1_readOr_value_valid_2 = 1'b1; - end else begin - _zz_banks_1_readOr_value_valid_2 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221_3) begin - _zz_banks_1_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_readOr_value_valid_3 = 9'h0; - end - end - - assign read_ports_1_cmd_ready = read_arbiter_1_doIt; - assign read_ports_1_buffer_s0_valid = read_arbiter_1_doIt; - assign read_ports_1_buffer_s0_payload_context = read_ports_1_cmd_payload_context; - assign read_ports_1_buffer_s0_payload_address = read_ports_1_cmd_payload_address; - assign initialiser_done = initialiser_counter[9]; - assign when_MemoryCore_l239 = (! initialiser_done); - assign _zz_banks_0_write_payload_data_data = 72'h0; - assign _zz_banks_1_write_payload_data_data = 72'h0; - assign _zz_banks_0_writeOr_value_valid_8 = ({{{_zz_banks_0_writeOr_value_valid_3,_zz_banks_0_writeOr_value_valid_2},_zz_banks_0_writeOr_value_valid_1},_zz_banks_0_writeOr_value_valid} | {{{_zz_banks_0_writeOr_value_valid_7,_zz_banks_0_writeOr_value_valid_6},_zz_banks_0_writeOr_value_valid_5},_zz_banks_0_writeOr_value_valid_4}); - assign banks_0_writeOr_value_valid = _zz_banks_0_writeOr_value_valid_8[0]; - assign _zz_banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_valid_8[81 : 1]; - assign banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_payload_address[8 : 0]; - assign _zz_banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_address[80 : 9]; - assign banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_data_data[63 : 0]; - assign banks_0_writeOr_value_payload_data_mask = _zz_banks_0_writeOr_value_payload_data_data[71 : 64]; - assign _zz_banks_0_readOr_value_valid_4 = ({_zz_banks_0_readOr_value_valid_1,_zz_banks_0_readOr_value_valid} | {_zz_banks_0_readOr_value_valid_3,_zz_banks_0_readOr_value_valid_2}); - assign banks_0_readOr_value_valid = _zz_banks_0_readOr_value_valid_4[0]; - assign banks_0_readOr_value_payload = _zz_banks_0_readOr_value_valid_4[9 : 1]; - assign _zz_banks_1_writeOr_value_valid_8 = ({{{_zz_banks_1_writeOr_value_valid_3,_zz_banks_1_writeOr_value_valid_2},_zz_banks_1_writeOr_value_valid_1},_zz_banks_1_writeOr_value_valid} | {{{_zz_banks_1_writeOr_value_valid_7,_zz_banks_1_writeOr_value_valid_6},_zz_banks_1_writeOr_value_valid_5},_zz_banks_1_writeOr_value_valid_4}); - assign banks_1_writeOr_value_valid = _zz_banks_1_writeOr_value_valid_8[0]; - assign _zz_banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_valid_8[81 : 1]; - assign banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_payload_address[8 : 0]; - assign _zz_banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_address[80 : 9]; - assign banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_data_data[63 : 0]; - assign banks_1_writeOr_value_payload_data_mask = _zz_banks_1_writeOr_value_payload_data_data[71 : 64]; - assign _zz_banks_1_readOr_value_valid_4 = ({_zz_banks_1_readOr_value_valid_1,_zz_banks_1_readOr_value_valid} | {_zz_banks_1_readOr_value_valid_3,_zz_banks_1_readOr_value_valid_2}); - assign banks_1_readOr_value_valid = _zz_banks_1_readOr_value_valid_4[0]; - assign banks_1_readOr_value_payload = _zz_banks_1_readOr_value_valid_4[9 : 1]; - always @(posedge clk) begin - if(io_writes_0_cmd_valid) begin - write_ports_0_priority_value <= (write_ports_0_priority_value + _zz_write_ports_0_priority_value); - if(io_writes_0_cmd_ready) begin - write_ports_0_priority_value <= 4'b0000; - end - end - io_writes_0_cmd_payload_context_regNext <= io_writes_0_cmd_payload_context; - io_writes_1_cmd_payload_context_regNext <= io_writes_1_cmd_payload_context; - read_ports_0_buffer_s1_payload_context <= read_ports_0_buffer_s0_payload_context; - read_ports_0_buffer_s1_payload_address <= read_ports_0_buffer_s0_payload_address; - if(read_ports_0_buffer_bufferIn_ready) begin - read_ports_0_buffer_bufferIn_rData_data <= read_ports_0_buffer_bufferIn_payload_data; - read_ports_0_buffer_bufferIn_rData_mask <= read_ports_0_buffer_bufferIn_payload_mask; - read_ports_0_buffer_bufferIn_rData_context <= read_ports_0_buffer_bufferIn_payload_context; - end - if(read_ports_0_cmd_valid) begin - read_ports_0_priority_value <= (read_ports_0_priority_value + _zz_read_ports_0_priority_value); - if(read_ports_0_cmd_ready) begin - read_ports_0_priority_value <= 4'b0000; - end - end - read_ports_1_buffer_s1_payload_context <= read_ports_1_buffer_s0_payload_context; - read_ports_1_buffer_s1_payload_address <= read_ports_1_buffer_s0_payload_address; - if(read_ports_1_buffer_bufferIn_ready) begin - read_ports_1_buffer_bufferIn_rData_data <= read_ports_1_buffer_bufferIn_payload_data; - read_ports_1_buffer_bufferIn_rData_mask <= read_ports_1_buffer_bufferIn_payload_mask; - read_ports_1_buffer_bufferIn_rData_context <= read_ports_1_buffer_bufferIn_payload_context; - end - end - - always @(posedge clk) begin - if(reset) begin - write_arbiter_0_doIt_regNext <= 1'b0; - write_arbiter_1_doIt_regNext <= 1'b0; - read_ports_0_buffer_s1_valid <= 1'b0; - read_ports_0_buffer_bufferIn_rValidN <= 1'b1; - read_ports_1_buffer_s1_valid <= 1'b0; - read_ports_1_buffer_bufferIn_rValidN <= 1'b1; - initialiser_counter <= 10'h0; - end else begin - write_arbiter_0_doIt_regNext <= write_arbiter_0_doIt; - write_arbiter_1_doIt_regNext <= write_arbiter_1_doIt; - read_ports_0_buffer_s1_valid <= read_ports_0_buffer_s0_valid; - if(read_ports_0_buffer_bufferIn_valid) begin - read_ports_0_buffer_bufferIn_rValidN <= 1'b0; - end - if(read_ports_0_buffer_bufferOut_ready) begin - read_ports_0_buffer_bufferIn_rValidN <= 1'b1; - end - read_ports_1_buffer_s1_valid <= read_ports_1_buffer_s0_valid; - if(read_ports_1_buffer_bufferIn_valid) begin - read_ports_1_buffer_bufferIn_rValidN <= 1'b0; - end - if(read_ports_1_buffer_bufferOut_ready) begin - read_ports_1_buffer_bufferIn_rValidN <= 1'b1; - end - if(when_MemoryCore_l239) begin - initialiser_counter <= (initialiser_counter + 10'h001); - end - end - end - - -endmodule - -module EfxDMA_StreamFifo_1_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_push_valid, - output wire io_push_ready, - input wire [13:0] io_push_payload_context, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [13:0] io_pop_payload_context, - input wire io_flush, - output wire [2:0] io_occupancy, - output wire [2:0] io_availability, - input wire clk, - input wire reset -); - - reg [13:0] logic_ram_spinal_port1; - wire [2:0] _zz_logic_ptr_notPow2_counter; - wire [2:0] _zz_logic_ptr_notPow2_counter_1; - wire [0:0] _zz_logic_ptr_notPow2_counter_2; - wire [2:0] _zz_logic_ptr_notPow2_counter_3; - wire [0:0] _zz_logic_ptr_notPow2_counter_4; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [2:0] logic_ptr_push; - reg [2:0] logic_ptr_pop; - wire [2:0] logic_ptr_occupancy; - wire [2:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire when_Stream_l1283; - wire when_Stream_l1287; - reg [2:0] logic_ptr_notPow2_counter; - wire io_push_fire; - wire io_pop_fire; - wire logic_push_onRam_write_valid; - wire [2:0] logic_push_onRam_write_payload_address; - wire [13:0] logic_push_onRam_write_payload_data_context; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [2:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [2:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [2:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [2:0] logic_pop_sync_readPort_cmd_payload; - wire [13:0] logic_pop_sync_readPort_rsp_context; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [13:0] logic_pop_sync_readArbitation_translated_payload_context; - wire logic_pop_sync_readArbitation_fire; - reg [2:0] logic_pop_sync_popReg; - reg [13:0] logic_ram [0:6]; - - assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); - assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; - assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; - assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; - assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); - assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); - assign when_Stream_l1283 = (logic_ptr_push == 3'b110); - assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); - assign io_push_fire = (io_push_valid && io_push_ready); - assign io_pop_fire = (io_pop_valid && io_pop_ready); - assign logic_ptr_occupancy = logic_ptr_notPow2_counter; - assign io_push_ready = (! logic_ptr_full); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push; - assign logic_push_onRam_write_payload_data_context = io_push_payload_context; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[13 : 0]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (3'b111 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - logic_ptr_wentUp <= 1'b0; - logic_ptr_notPow2_counter <= 3'b000; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 3'b000; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 3'b001); - if(when_Stream_l1283) begin - logic_ptr_push <= 3'b000; - end - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 3'b001); - if(when_Stream_l1287) begin - logic_ptr_pop <= 3'b000; - end - end - if(io_flush) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - end - logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); - if(io_flush) begin - logic_ptr_notPow2_counter <= 3'b000; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 3'b000; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_StreamFifo_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_push_valid, - output wire io_push_ready, - input wire [21:0] io_push_payload_context, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [21:0] io_pop_payload_context, - input wire io_flush, - output wire [2:0] io_occupancy, - output wire [2:0] io_availability, - input wire clk, - input wire reset -); - - reg [21:0] logic_ram_spinal_port1; - wire [2:0] _zz_logic_ptr_notPow2_counter; - wire [2:0] _zz_logic_ptr_notPow2_counter_1; - wire [0:0] _zz_logic_ptr_notPow2_counter_2; - wire [2:0] _zz_logic_ptr_notPow2_counter_3; - wire [0:0] _zz_logic_ptr_notPow2_counter_4; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [2:0] logic_ptr_push; - reg [2:0] logic_ptr_pop; - wire [2:0] logic_ptr_occupancy; - wire [2:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire when_Stream_l1283; - wire when_Stream_l1287; - reg [2:0] logic_ptr_notPow2_counter; - wire io_push_fire; - wire io_pop_fire; - wire logic_push_onRam_write_valid; - wire [2:0] logic_push_onRam_write_payload_address; - wire [21:0] logic_push_onRam_write_payload_data_context; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [2:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [2:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [2:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [2:0] logic_pop_sync_readPort_cmd_payload; - wire [21:0] logic_pop_sync_readPort_rsp_context; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [21:0] logic_pop_sync_readArbitation_translated_payload_context; - wire logic_pop_sync_readArbitation_fire; - reg [2:0] logic_pop_sync_popReg; - reg [21:0] logic_ram [0:6]; - - assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); - assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; - assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; - assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; - assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); - assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); - assign when_Stream_l1283 = (logic_ptr_push == 3'b110); - assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); - assign io_push_fire = (io_push_valid && io_push_ready); - assign io_pop_fire = (io_pop_valid && io_pop_ready); - assign logic_ptr_occupancy = logic_ptr_notPow2_counter; - assign io_push_ready = (! logic_ptr_full); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push; - assign logic_push_onRam_write_payload_data_context = io_push_payload_context; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[21 : 0]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (3'b111 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - logic_ptr_wentUp <= 1'b0; - logic_ptr_notPow2_counter <= 3'b000; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 3'b000; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 3'b001); - if(when_Stream_l1283) begin - logic_ptr_push <= 3'b000; - end - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 3'b001); - if(when_Stream_l1287) begin - logic_ptr_pop <= 3'b000; - end - end - if(io_flush) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - end - logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); - if(io_flush) begin - logic_ptr_notPow2_counter <= 3'b000; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 3'b000; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_BufferCC_1_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_dataIn, - output wire io_dataOut, - input wire ctrl_clk, - input wire ctrl_reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module EfxDMA_BufferCC_a048ca8f51874147a1cd65d43e6523ef ( - input wire io_dataIn, - output wire io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/gDMA/gDMA_define.vh b/fpga/ip/gDMA/gDMA_define.vh deleted file mode 100644 index 9ddbd8e..0000000 --- a/fpga/ip/gDMA/gDMA_define.vh +++ /dev/null @@ -1,45 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 6.4.2 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - diff --git a/fpga/ip/gDMA/gDMA_tmpl.v b/fpga/ip/gDMA/gDMA_tmpl.v deleted file mode 100644 index a24f50a..0000000 --- a/fpga/ip/gDMA/gDMA_tmpl.v +++ /dev/null @@ -1,114 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 6.4.2 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -gDMA u_gDMA -( - .clk ( clk ), - .ctrl_reset ( ctrl_reset ), - .reset ( reset ), - .ctrl_clk ( ctrl_clk ), - .ctrl_PADDR ( ctrl_PADDR ), - .ctrl_PREADY ( ctrl_PREADY ), - .ctrl_PENABLE ( ctrl_PENABLE ), - .ctrl_PSEL ( ctrl_PSEL ), - .ctrl_PWRITE ( ctrl_PWRITE ), - .ctrl_PWDATA ( ctrl_PWDATA ), - .ctrl_PRDATA ( ctrl_PRDATA ), - .ctrl_PSLVERROR ( ctrl_PSLVERROR ), - .ctrl_interrupts ( ctrl_interrupts ), - .read_arvalid ( read_arvalid ), - .read_araddr ( read_araddr ), - .read_arready ( read_arready ), - .read_arregion ( read_arregion ), - .read_arlen ( read_arlen ), - .read_arsize ( read_arsize ), - .read_arburst ( read_arburst ), - .read_arlock ( read_arlock ), - .read_arcache ( read_arcache ), - .read_arqos ( read_arqos ), - .read_arprot ( read_arprot ), - .read_rready ( read_rready ), - .read_rvalid ( read_rvalid ), - .read_rdata ( read_rdata ), - .read_rlast ( read_rlast ), - .write_awvalid ( write_awvalid ), - .write_awready ( write_awready ), - .write_awaddr ( write_awaddr ), - .write_awregion ( write_awregion ), - .write_awlen ( write_awlen ), - .write_awsize ( write_awsize ), - .write_awburst ( write_awburst ), - .write_awlock ( write_awlock ), - .write_awcache ( write_awcache ), - .write_awqos ( write_awqos ), - .write_awprot ( write_awprot ), - .write_wvalid ( write_wvalid ), - .write_wready ( write_wready ), - .write_wdata ( write_wdata ), - .write_wstrb ( write_wstrb ), - .write_wlast ( write_wlast ), - .write_bvalid ( write_bvalid ), - .write_bready ( write_bready ), - .write_bresp ( write_bresp ), - .dat1_o_tvalid ( dat1_o_tvalid ), - .dat1_o_tready ( dat1_o_tready ), - .dat1_o_tdata ( dat1_o_tdata ), - .dat1_o_tkeep ( dat1_o_tkeep ), - .dat1_o_tdest ( dat1_o_tdest ), - .dat1_o_tlast ( dat1_o_tlast ), - .io_0_descriptorUpdate ( io_0_descriptorUpdate ), - .dat1_o_clk ( dat1_o_clk ), - .dat1_o_reset ( dat1_o_reset ), - .dat0_i_clk ( dat0_i_clk ), - .dat0_i_reset ( dat0_i_reset ), - .dat0_i_tvalid ( dat0_i_tvalid ), - .dat0_i_tready ( dat0_i_tready ), - .dat0_i_tdata ( dat0_i_tdata ), - .dat0_i_tkeep ( dat0_i_tkeep ), - .dat0_i_tdest ( dat0_i_tdest ), - .dat0_i_tlast ( dat0_i_tlast ), - .read_rresp ( read_rresp ), - .io_1_descriptorUpdate ( io_1_descriptorUpdate ) -); diff --git a/fpga/ip/gDMA/gDMA_tmpl.vhd b/fpga/ip/gDMA/gDMA_tmpl.vhd deleted file mode 100644 index 3f0c81e..0000000 --- a/fpga/ip/gDMA/gDMA_tmpl.vhd +++ /dev/null @@ -1,183 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component gDMA is -port ( - clk : in std_logic; - ctrl_reset : in std_logic; - reset : in std_logic; - ctrl_clk : in std_logic; - ctrl_PADDR : in std_logic_vector(13 downto 0); - ctrl_PREADY : out std_logic; - ctrl_PENABLE : in std_logic; - ctrl_PSEL : in std_logic; - ctrl_PWRITE : in std_logic; - ctrl_PWDATA : in std_logic_vector(31 downto 0); - ctrl_PRDATA : out std_logic_vector(31 downto 0); - ctrl_PSLVERROR : out std_logic; - ctrl_interrupts : out std_logic_vector(1 downto 0); - read_arvalid : out std_logic; - read_araddr : out std_logic_vector(31 downto 0); - read_arready : in std_logic; - read_arregion : out std_logic_vector(3 downto 0); - read_arlen : out std_logic_vector(7 downto 0); - read_arsize : out std_logic_vector(2 downto 0); - read_arburst : out std_logic_vector(1 downto 0); - read_arlock : out std_logic; - read_arcache : out std_logic_vector(3 downto 0); - read_arqos : out std_logic_vector(3 downto 0); - read_arprot : out std_logic_vector(2 downto 0); - read_rready : out std_logic; - read_rvalid : in std_logic; - read_rdata : in std_logic_vector(127 downto 0); - read_rlast : in std_logic; - write_awvalid : out std_logic; - write_awready : in std_logic; - write_awaddr : out std_logic_vector(31 downto 0); - write_awregion : out std_logic_vector(3 downto 0); - write_awlen : out std_logic_vector(7 downto 0); - write_awsize : out std_logic_vector(2 downto 0); - write_awburst : out std_logic_vector(1 downto 0); - write_awlock : out std_logic; - write_awcache : out std_logic_vector(3 downto 0); - write_awqos : out std_logic_vector(3 downto 0); - write_awprot : out std_logic_vector(2 downto 0); - write_wvalid : out std_logic; - write_wready : in std_logic; - write_wdata : out std_logic_vector(127 downto 0); - write_wstrb : out std_logic_vector(15 downto 0); - write_wlast : out std_logic; - write_bvalid : in std_logic; - write_bready : out std_logic; - write_bresp : in std_logic_vector(1 downto 0); - dat1_o_tvalid : out std_logic; - dat1_o_tready : in std_logic; - dat1_o_tdata : out std_logic_vector(7 downto 0); - dat1_o_tkeep : out std_logic_vector(0 to 0); - dat1_o_tdest : out std_logic_vector(3 downto 0); - dat1_o_tlast : out std_logic; - io_0_descriptorUpdate : out std_logic; - dat1_o_clk : in std_logic; - dat1_o_reset : in std_logic; - dat0_i_clk : in std_logic; - dat0_i_reset : in std_logic; - dat0_i_tvalid : in std_logic; - dat0_i_tready : out std_logic; - dat0_i_tdata : in std_logic_vector(7 downto 0); - dat0_i_tkeep : in std_logic_vector(0 to 0); - dat0_i_tdest : in std_logic_vector(3 downto 0); - dat0_i_tlast : in std_logic; - read_rresp : in std_logic_vector(1 downto 0); - io_1_descriptorUpdate : out std_logic -); -end component gDMA; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_gDMA : gDMA -port map ( - clk => clk, - ctrl_reset => ctrl_reset, - reset => reset, - ctrl_clk => ctrl_clk, - ctrl_PADDR => ctrl_PADDR, - ctrl_PREADY => ctrl_PREADY, - ctrl_PENABLE => ctrl_PENABLE, - ctrl_PSEL => ctrl_PSEL, - ctrl_PWRITE => ctrl_PWRITE, - ctrl_PWDATA => ctrl_PWDATA, - ctrl_PRDATA => ctrl_PRDATA, - ctrl_PSLVERROR => ctrl_PSLVERROR, - ctrl_interrupts => ctrl_interrupts, - read_arvalid => read_arvalid, - read_araddr => read_araddr, - read_arready => read_arready, - read_arregion => read_arregion, - read_arlen => read_arlen, - read_arsize => read_arsize, - read_arburst => read_arburst, - read_arlock => read_arlock, - read_arcache => read_arcache, - read_arqos => read_arqos, - read_arprot => read_arprot, - read_rready => read_rready, - read_rvalid => read_rvalid, - read_rdata => read_rdata, - read_rlast => read_rlast, - write_awvalid => write_awvalid, - write_awready => write_awready, - write_awaddr => write_awaddr, - write_awregion => write_awregion, - write_awlen => write_awlen, - write_awsize => write_awsize, - write_awburst => write_awburst, - write_awlock => write_awlock, - write_awcache => write_awcache, - write_awqos => write_awqos, - write_awprot => write_awprot, - write_wvalid => write_wvalid, - write_wready => write_wready, - write_wdata => write_wdata, - write_wstrb => write_wstrb, - write_wlast => write_wlast, - write_bvalid => write_bvalid, - write_bready => write_bready, - write_bresp => write_bresp, - dat1_o_tvalid => dat1_o_tvalid, - dat1_o_tready => dat1_o_tready, - dat1_o_tdata => dat1_o_tdata, - dat1_o_tkeep => dat1_o_tkeep, - dat1_o_tdest => dat1_o_tdest, - dat1_o_tlast => dat1_o_tlast, - io_0_descriptorUpdate => io_0_descriptorUpdate, - dat1_o_clk => dat1_o_clk, - dat1_o_reset => dat1_o_reset, - dat0_i_clk => dat0_i_clk, - dat0_i_reset => dat0_i_reset, - dat0_i_tvalid => dat0_i_tvalid, - dat0_i_tready => dat0_i_tready, - dat0_i_tdata => dat0_i_tdata, - dat0_i_tkeep => dat0_i_tkeep, - dat0_i_tdest => dat0_i_tdest, - dat0_i_tlast => dat0_i_tlast, - read_rresp => read_rresp, - io_1_descriptorUpdate => io_1_descriptorUpdate -); - ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/gDMA/ipm/component.pickle b/fpga/ip/gDMA/ipm/component.pickle deleted file mode 100644 index d3113f81e63c70060e10cdf846efec1c10b7380c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 156601 zcmeHw3y@q_nci3rYcwOtviuM>Hng#9k8CvR?wRS4Y|GYYX7sQ$dd!S08Sr*`y6>oO ztEao^hb&p1wOvb=rS|f4<2CF;NWckDyEqkIfz6UFD3*}y60#L2QoFFJR9HeKkfgRk zxkzAh9{1dP&+FcEA1!tFTvvfTea|`fp8xwF-}%q$g$*BGH*muM{Kwd%Enm*+wUrC? z(OSJ)Xyu!FwUW)%^wFB0zgX5r8(Lk@mGx(H@Il+SdAhn%t5&p1b5UEVm2*w4{Zf1P zi|y6+h_RuPThZFaCfHuqDJwyan5%X%e0ny;>a zI%R#So~vJJ8@Ddi^}+?MkK*<2x4YgX$GP~ehQZ=f&Om>C@(O}CA~a;|crmAe4n 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b/fpga/ip/gDMA/source/EfxDMA.v deleted file mode 100644 index c77644c..0000000 --- a/fpga/ip/gDMA/source/EfxDMA.v +++ /dev/null @@ -1,11449 +0,0 @@ -// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 -// Component : EfxDMA - -`timescale 1ns/1ps - -module EfxDMA ( - input wire [13:0] ctrl_PADDR, - input wire [0:0] ctrl_PSEL, - input wire ctrl_PENABLE, - output wire ctrl_PREADY, - input wire ctrl_PWRITE, - input wire [31:0] ctrl_PWDATA, - output wire [31:0] ctrl_PRDATA, - output wire ctrl_PSLVERROR, - output wire [1:0] ctrl_interrupts, - output wire read_arvalid, - input wire read_arready, - output wire [31:0] read_araddr, - output wire [3:0] read_arregion, - output wire [7:0] read_arlen, - output wire [2:0] read_arsize, - output wire [1:0] read_arburst, - output wire [0:0] read_arlock, - output wire [3:0] read_arcache, - output wire [3:0] read_arqos, - output wire [2:0] read_arprot, - input wire read_rvalid, - output wire read_rready, - input wire [127:0] read_rdata, - input wire [1:0] read_rresp, - input wire read_rlast, - output wire write_awvalid, - input wire write_awready, - output wire [31:0] write_awaddr, - output wire [3:0] write_awregion, - output wire [7:0] write_awlen, - output wire [2:0] write_awsize, - output wire [1:0] write_awburst, - output wire [0:0] write_awlock, - output wire [3:0] write_awcache, - output wire [3:0] write_awqos, - output wire [2:0] write_awprot, - output wire write_wvalid, - input wire write_wready, - output wire [127:0] write_wdata, - output wire [15:0] write_wstrb, - output wire write_wlast, - input wire write_bvalid, - output wire write_bready, - input wire [1:0] write_bresp, - input wire dat0_i_tvalid, - output wire dat0_i_tready, - input wire [7:0] dat0_i_tdata, - input wire [0:0] dat0_i_tkeep, - input wire [3:0] dat0_i_tdest, - input wire dat0_i_tlast, - output wire dat1_o_tvalid, - input wire dat1_o_tready, - output wire [7:0] dat1_o_tdata, - output wire [0:0] dat1_o_tkeep, - output wire [3:0] dat1_o_tdest, - output wire dat1_o_tlast, - output wire io_0_descriptorUpdate, - output wire io_1_descriptorUpdate, - input wire clk, - input wire reset, - input wire ctrl_clk, - input wire ctrl_reset, - input wire dat0_i_clk, - input wire dat0_i_reset, - input wire dat1_o_clk, - input wire dat1_o_reset -); - - wire core_io_sgRead_cmd_valid; - wire core_io_sgRead_cmd_payload_last; - wire [0:0] core_io_sgRead_cmd_payload_fragment_opcode; - wire [31:0] core_io_sgRead_cmd_payload_fragment_address; - wire [4:0] core_io_sgRead_cmd_payload_fragment_length; - wire [0:0] core_io_sgRead_cmd_payload_fragment_context; - wire core_io_sgRead_rsp_ready; - wire core_io_sgWrite_cmd_valid; - wire core_io_sgWrite_cmd_payload_last; - wire [0:0] core_io_sgWrite_cmd_payload_fragment_opcode; - wire [31:0] core_io_sgWrite_cmd_payload_fragment_address; - wire [1:0] core_io_sgWrite_cmd_payload_fragment_length; - wire [127:0] core_io_sgWrite_cmd_payload_fragment_data; - wire [15:0] core_io_sgWrite_cmd_payload_fragment_mask; - wire [0:0] core_io_sgWrite_cmd_payload_fragment_context; - wire core_io_sgWrite_rsp_ready; - wire core_io_read_cmd_valid; - wire core_io_read_cmd_payload_last; - wire [0:0] core_io_read_cmd_payload_fragment_opcode; - wire [31:0] core_io_read_cmd_payload_fragment_address; - wire [11:0] core_io_read_cmd_payload_fragment_length; - wire [20:0] core_io_read_cmd_payload_fragment_context; - wire core_io_read_rsp_ready; - wire core_io_write_cmd_valid; - wire core_io_write_cmd_payload_last; - wire [0:0] core_io_write_cmd_payload_fragment_opcode; - wire [31:0] core_io_write_cmd_payload_fragment_address; - wire [11:0] core_io_write_cmd_payload_fragment_length; - wire [127:0] core_io_write_cmd_payload_fragment_data; - wire [15:0] core_io_write_cmd_payload_fragment_mask; - wire [12:0] core_io_write_cmd_payload_fragment_context; - wire core_io_write_rsp_ready; - wire core_io_outputs_0_valid; - wire [63:0] core_io_outputs_0_payload_data; - wire [7:0] core_io_outputs_0_payload_mask; - wire [3:0] core_io_outputs_0_payload_sink; - wire core_io_outputs_0_payload_last; - wire core_io_inputs_0_ready; - wire [1:0] core_io_interrupts; - wire core_io_ctrl_PREADY; - wire [31:0] core_io_ctrl_PRDATA; - wire core_io_ctrl_PSLVERROR; - wire core_ll_0_descriptorUpdate; - wire core_ll_1_descriptorUpdate; - wire withCtrlCc_apbCc_io_input_PREADY; - wire [31:0] withCtrlCc_apbCc_io_input_PRDATA; - wire withCtrlCc_apbCc_io_input_PSLVERROR; - wire [13:0] withCtrlCc_apbCc_io_output_PADDR; - wire [0:0] withCtrlCc_apbCc_io_output_PSEL; - wire withCtrlCc_apbCc_io_output_PENABLE; - wire withCtrlCc_apbCc_io_output_PWRITE; - wire [31:0] withCtrlCc_apbCc_io_output_PWDATA; - wire [1:0] io_interrupts_buffercc_io_dataOut; - wire readLogic_sourceRemover_io_input_cmd_ready; - wire readLogic_sourceRemover_io_input_rsp_valid; - wire readLogic_sourceRemover_io_input_rsp_payload_last; - wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_source; - wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; - wire [127:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_data; - wire [20:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_context; - wire readLogic_sourceRemover_io_output_cmd_valid; - wire readLogic_sourceRemover_io_output_cmd_payload_last; - wire [0:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; - wire [31:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_address; - wire [11:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_length; - wire [21:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_context; - wire readLogic_sourceRemover_io_output_rsp_ready; - wire readLogic_bridge_io_input_cmd_ready; - wire readLogic_bridge_io_input_rsp_valid; - wire readLogic_bridge_io_input_rsp_payload_last; - wire [0:0] readLogic_bridge_io_input_rsp_payload_fragment_opcode; - wire [127:0] readLogic_bridge_io_input_rsp_payload_fragment_data; - wire [21:0] readLogic_bridge_io_input_rsp_payload_fragment_context; - wire readLogic_bridge_io_output_ar_valid; - wire [31:0] readLogic_bridge_io_output_ar_payload_addr; - wire [7:0] readLogic_bridge_io_output_ar_payload_len; - wire [2:0] readLogic_bridge_io_output_ar_payload_size; - wire [3:0] readLogic_bridge_io_output_ar_payload_cache; - wire [2:0] readLogic_bridge_io_output_ar_payload_prot; - wire readLogic_bridge_io_output_r_ready; - wire writeLogic_sourceRemover_io_input_cmd_ready; - wire writeLogic_sourceRemover_io_input_rsp_valid; - wire writeLogic_sourceRemover_io_input_rsp_payload_last; - wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; - wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; - wire [12:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; - wire writeLogic_sourceRemover_io_output_cmd_valid; - wire writeLogic_sourceRemover_io_output_cmd_payload_last; - wire [0:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; - wire [31:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_address; - wire [11:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_length; - wire [127:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_data; - wire [15:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask; - wire [13:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_context; - wire writeLogic_sourceRemover_io_output_rsp_ready; - wire writeLogic_bridge_io_input_cmd_ready; - wire writeLogic_bridge_io_input_rsp_valid; - wire writeLogic_bridge_io_input_rsp_payload_last; - wire [0:0] writeLogic_bridge_io_input_rsp_payload_fragment_opcode; - wire [13:0] writeLogic_bridge_io_input_rsp_payload_fragment_context; - wire writeLogic_bridge_io_output_aw_valid; - wire [31:0] writeLogic_bridge_io_output_aw_payload_addr; - wire [7:0] writeLogic_bridge_io_output_aw_payload_len; - wire [2:0] writeLogic_bridge_io_output_aw_payload_size; - wire [3:0] writeLogic_bridge_io_output_aw_payload_cache; - wire [2:0] writeLogic_bridge_io_output_aw_payload_prot; - wire writeLogic_bridge_io_output_w_valid; - wire [127:0] writeLogic_bridge_io_output_w_payload_data; - wire [15:0] writeLogic_bridge_io_output_w_payload_strb; - wire writeLogic_bridge_io_output_w_payload_last; - wire writeLogic_bridge_io_output_b_ready; - wire inputsAdapter_0_upsizer_logic_io_input_ready; - wire inputsAdapter_0_upsizer_logic_io_output_valid; - wire [63:0] inputsAdapter_0_upsizer_logic_io_output_payload_data; - wire [7:0] inputsAdapter_0_upsizer_logic_io_output_payload_mask; - wire [3:0] inputsAdapter_0_upsizer_logic_io_output_payload_sink; - wire inputsAdapter_0_upsizer_logic_io_output_payload_last; - wire inputsAdapter_0_crossclock_fifo_io_push_ready; - wire inputsAdapter_0_crossclock_fifo_io_pop_valid; - wire [63:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_data; - wire [7:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; - wire [3:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; - wire inputsAdapter_0_crossclock_fifo_io_pop_payload_last; - wire [4:0] inputsAdapter_0_crossclock_fifo_io_pushOccupancy; - wire [4:0] inputsAdapter_0_crossclock_fifo_io_popOccupancy; - wire outputsAdapter_0_crossclock_fifo_io_push_ready; - wire outputsAdapter_0_crossclock_fifo_io_pop_valid; - wire [63:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_data; - wire [7:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_mask; - wire [3:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_sink; - wire outputsAdapter_0_crossclock_fifo_io_pop_payload_last; - wire [4:0] outputsAdapter_0_crossclock_fifo_io_pushOccupancy; - wire [4:0] outputsAdapter_0_crossclock_fifo_io_popOccupancy; - wire outputsAdapter_0_sparseDownsizer_logic_io_input_ready; - wire outputsAdapter_0_sparseDownsizer_logic_io_output_valid; - wire [7:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; - wire [0:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; - wire [3:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; - wire outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; - wire interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; - wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; - wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; - wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; - wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; - wire interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; - wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; - wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; - wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; - wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; - wire [20:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; - wire interconnect_read_aggregated_arbiter_io_output_cmd_valid; - wire interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; - wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; - wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; - wire [31:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; - wire [11:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; - wire [20:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; - wire interconnect_read_aggregated_arbiter_io_output_rsp_ready; - wire interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; - wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; - wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; - wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; - wire interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; - wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; - wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; - wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; - wire [12:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; - wire interconnect_write_aggregated_arbiter_io_output_cmd_valid; - wire interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; - wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; - wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; - wire [31:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; - wire [11:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; - wire [127:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; - wire [15:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; - wire [12:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; - wire interconnect_write_aggregated_arbiter_io_output_rsp_ready; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; - wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; - wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; - wire [11:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; - wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; - wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; - wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data; - wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; - wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; - wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; - wire [4:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; - wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; - wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; - wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; - wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; - wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; - wire [11:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; - wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data; - wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask; - wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; - wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; - wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; - wire io_write_cmd_s2mPipe_valid; - reg io_write_cmd_s2mPipe_ready; - wire io_write_cmd_s2mPipe_payload_last; - wire [0:0] io_write_cmd_s2mPipe_payload_fragment_opcode; - wire [31:0] io_write_cmd_s2mPipe_payload_fragment_address; - wire [11:0] io_write_cmd_s2mPipe_payload_fragment_length; - wire [127:0] io_write_cmd_s2mPipe_payload_fragment_data; - wire [15:0] io_write_cmd_s2mPipe_payload_fragment_mask; - wire [12:0] io_write_cmd_s2mPipe_payload_fragment_context; - reg io_write_cmd_rValidN; - reg io_write_cmd_rData_last; - reg [0:0] io_write_cmd_rData_fragment_opcode; - reg [31:0] io_write_cmd_rData_fragment_address; - reg [11:0] io_write_cmd_rData_fragment_length; - reg [127:0] io_write_cmd_rData_fragment_data; - reg [15:0] io_write_cmd_rData_fragment_mask; - reg [12:0] io_write_cmd_rData_fragment_context; - wire io_write_cmd_s2mPipe_m2sPipe_valid; - wire io_write_cmd_s2mPipe_m2sPipe_ready; - wire io_write_cmd_s2mPipe_m2sPipe_payload_last; - wire [0:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; - wire [31:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; - wire [11:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; - wire [127:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; - wire [15:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; - wire [12:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; - reg io_write_cmd_s2mPipe_rValid; - reg io_write_cmd_s2mPipe_rData_last; - reg [0:0] io_write_cmd_s2mPipe_rData_fragment_opcode; - reg [31:0] io_write_cmd_s2mPipe_rData_fragment_address; - reg [11:0] io_write_cmd_s2mPipe_rData_fragment_length; - reg [127:0] io_write_cmd_s2mPipe_rData_fragment_data; - reg [15:0] io_write_cmd_s2mPipe_rData_fragment_mask; - reg [12:0] io_write_cmd_s2mPipe_rData_fragment_context; - wire when_Stream_l375; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; - wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; - wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; - wire [1:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; - wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; - wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; - wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; - wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - wire interconnect_read_aggregated_cmd_valid; - wire interconnect_read_aggregated_cmd_ready; - wire interconnect_read_aggregated_cmd_payload_last; - wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_source; - wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_opcode; - wire [31:0] interconnect_read_aggregated_cmd_payload_fragment_address; - wire [11:0] interconnect_read_aggregated_cmd_payload_fragment_length; - wire [20:0] interconnect_read_aggregated_cmd_payload_fragment_context; - wire interconnect_read_aggregated_rsp_valid; - wire interconnect_read_aggregated_rsp_ready; - wire interconnect_read_aggregated_rsp_payload_last; - wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_source; - wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_opcode; - wire [127:0] interconnect_read_aggregated_rsp_payload_fragment_data; - wire [20:0] interconnect_read_aggregated_rsp_payload_fragment_context; - wire interconnect_write_aggregated_cmd_valid; - reg interconnect_write_aggregated_cmd_ready; - wire interconnect_write_aggregated_cmd_payload_last; - wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_source; - wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_opcode; - wire [31:0] interconnect_write_aggregated_cmd_payload_fragment_address; - wire [11:0] interconnect_write_aggregated_cmd_payload_fragment_length; - wire [127:0] interconnect_write_aggregated_cmd_payload_fragment_data; - wire [15:0] interconnect_write_aggregated_cmd_payload_fragment_mask; - wire [12:0] interconnect_write_aggregated_cmd_payload_fragment_context; - wire interconnect_write_aggregated_rsp_valid; - wire interconnect_write_aggregated_rsp_ready; - wire interconnect_write_aggregated_rsp_payload_last; - wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_source; - wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_opcode; - wire [12:0] interconnect_write_aggregated_rsp_payload_fragment_context; - wire readLogic_resized_cmd_valid; - wire readLogic_resized_cmd_ready; - wire readLogic_resized_cmd_payload_last; - wire [0:0] readLogic_resized_cmd_payload_fragment_source; - wire [0:0] readLogic_resized_cmd_payload_fragment_opcode; - wire [31:0] readLogic_resized_cmd_payload_fragment_address; - wire [11:0] readLogic_resized_cmd_payload_fragment_length; - wire [20:0] readLogic_resized_cmd_payload_fragment_context; - wire readLogic_resized_rsp_valid; - wire readLogic_resized_rsp_ready; - wire readLogic_resized_rsp_payload_last; - wire [0:0] readLogic_resized_rsp_payload_fragment_source; - wire [0:0] readLogic_resized_rsp_payload_fragment_opcode; - wire [127:0] readLogic_resized_rsp_payload_fragment_data; - wire [20:0] readLogic_resized_rsp_payload_fragment_context; - wire interconnect_read_aggregated_cmd_halfPipe_valid; - wire interconnect_read_aggregated_cmd_halfPipe_ready; - wire interconnect_read_aggregated_cmd_halfPipe_payload_last; - wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; - wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; - wire [31:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; - wire [11:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; - wire [20:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; - reg interconnect_read_aggregated_cmd_rValid; - wire interconnect_read_aggregated_cmd_halfPipe_fire; - reg interconnect_read_aggregated_cmd_rData_last; - reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_source; - reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_opcode; - reg [31:0] interconnect_read_aggregated_cmd_rData_fragment_address; - reg [11:0] interconnect_read_aggregated_cmd_rData_fragment_length; - reg [20:0] interconnect_read_aggregated_cmd_rData_fragment_context; - wire readLogic_resized_rsp_combStage_valid; - wire readLogic_resized_rsp_combStage_ready; - wire readLogic_resized_rsp_combStage_payload_last; - wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_source; - wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_opcode; - wire [127:0] readLogic_resized_rsp_combStage_payload_fragment_data; - wire [20:0] readLogic_resized_rsp_combStage_payload_fragment_context; - wire readLogic_adapter_ar_valid; - wire readLogic_adapter_ar_ready; - wire [31:0] readLogic_adapter_ar_payload_addr; - wire [3:0] readLogic_adapter_ar_payload_region; - wire [7:0] readLogic_adapter_ar_payload_len; - wire [2:0] readLogic_adapter_ar_payload_size; - wire [1:0] readLogic_adapter_ar_payload_burst; - wire [0:0] readLogic_adapter_ar_payload_lock; - wire [3:0] readLogic_adapter_ar_payload_cache; - wire [3:0] readLogic_adapter_ar_payload_qos; - wire [2:0] readLogic_adapter_ar_payload_prot; - wire readLogic_adapter_r_valid; - wire readLogic_adapter_r_ready; - wire [127:0] readLogic_adapter_r_payload_data; - wire [1:0] readLogic_adapter_r_payload_resp; - wire readLogic_adapter_r_payload_last; - wire [3:0] _zz_readLogic_adapter_ar_payload_region; - wire readLogic_adapter_ar_halfPipe_valid; - wire readLogic_adapter_ar_halfPipe_ready; - wire [31:0] readLogic_adapter_ar_halfPipe_payload_addr; - wire [3:0] readLogic_adapter_ar_halfPipe_payload_region; - wire [7:0] readLogic_adapter_ar_halfPipe_payload_len; - wire [2:0] readLogic_adapter_ar_halfPipe_payload_size; - wire [1:0] readLogic_adapter_ar_halfPipe_payload_burst; - wire [0:0] readLogic_adapter_ar_halfPipe_payload_lock; - wire [3:0] readLogic_adapter_ar_halfPipe_payload_cache; - wire [3:0] readLogic_adapter_ar_halfPipe_payload_qos; - wire [2:0] readLogic_adapter_ar_halfPipe_payload_prot; - reg readLogic_adapter_ar_rValid; - wire readLogic_adapter_ar_halfPipe_fire; - reg [31:0] readLogic_adapter_ar_rData_addr; - reg [3:0] readLogic_adapter_ar_rData_region; - reg [7:0] readLogic_adapter_ar_rData_len; - reg [2:0] readLogic_adapter_ar_rData_size; - reg [1:0] readLogic_adapter_ar_rData_burst; - reg [0:0] readLogic_adapter_ar_rData_lock; - reg [3:0] readLogic_adapter_ar_rData_cache; - reg [3:0] readLogic_adapter_ar_rData_qos; - reg [2:0] readLogic_adapter_ar_rData_prot; - wire read_r_s2mPipe_valid; - reg read_r_s2mPipe_ready; - wire [127:0] read_r_s2mPipe_payload_data; - wire [1:0] read_r_s2mPipe_payload_resp; - wire read_r_s2mPipe_payload_last; - reg read_r_rValidN; - reg [127:0] read_r_rData_data; - reg [1:0] read_r_rData_resp; - reg read_r_rData_last; - wire readLogic_beforeQueue_valid; - wire readLogic_beforeQueue_ready; - wire [127:0] readLogic_beforeQueue_payload_data; - wire [1:0] readLogic_beforeQueue_payload_resp; - wire readLogic_beforeQueue_payload_last; - reg read_r_s2mPipe_rValid; - reg [127:0] read_r_s2mPipe_rData_data; - reg [1:0] read_r_s2mPipe_rData_resp; - reg read_r_s2mPipe_rData_last; - wire when_Stream_l375_1; - wire writeLogic_resized_cmd_valid; - wire writeLogic_resized_cmd_ready; - wire writeLogic_resized_cmd_payload_last; - wire [0:0] writeLogic_resized_cmd_payload_fragment_source; - wire [0:0] writeLogic_resized_cmd_payload_fragment_opcode; - wire [31:0] writeLogic_resized_cmd_payload_fragment_address; - wire [11:0] writeLogic_resized_cmd_payload_fragment_length; - wire [127:0] writeLogic_resized_cmd_payload_fragment_data; - wire [15:0] writeLogic_resized_cmd_payload_fragment_mask; - wire [12:0] writeLogic_resized_cmd_payload_fragment_context; - wire writeLogic_resized_rsp_valid; - wire writeLogic_resized_rsp_ready; - wire writeLogic_resized_rsp_payload_last; - wire [0:0] writeLogic_resized_rsp_payload_fragment_source; - wire [0:0] writeLogic_resized_rsp_payload_fragment_opcode; - wire [12:0] writeLogic_resized_rsp_payload_fragment_context; - wire interconnect_write_aggregated_cmd_m2sPipe_valid; - wire interconnect_write_aggregated_cmd_m2sPipe_ready; - wire interconnect_write_aggregated_cmd_m2sPipe_payload_last; - wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; - wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; - wire [31:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; - wire [11:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; - wire [127:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; - wire [15:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; - wire [12:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; - reg interconnect_write_aggregated_cmd_rValid; - reg interconnect_write_aggregated_cmd_rData_last; - reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_source; - reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_opcode; - reg [31:0] interconnect_write_aggregated_cmd_rData_fragment_address; - reg [11:0] interconnect_write_aggregated_cmd_rData_fragment_length; - reg [127:0] interconnect_write_aggregated_cmd_rData_fragment_data; - reg [15:0] interconnect_write_aggregated_cmd_rData_fragment_mask; - reg [12:0] interconnect_write_aggregated_cmd_rData_fragment_context; - wire when_Stream_l375_2; - wire writeLogic_resized_rsp_combStage_valid; - wire writeLogic_resized_rsp_combStage_ready; - wire writeLogic_resized_rsp_combStage_payload_last; - wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_source; - wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_opcode; - wire [12:0] writeLogic_resized_rsp_combStage_payload_fragment_context; - wire writeLogic_adapter_aw_valid; - wire writeLogic_adapter_aw_ready; - wire [31:0] writeLogic_adapter_aw_payload_addr; - wire [3:0] writeLogic_adapter_aw_payload_region; - wire [7:0] writeLogic_adapter_aw_payload_len; - wire [2:0] writeLogic_adapter_aw_payload_size; - wire [1:0] writeLogic_adapter_aw_payload_burst; - wire [0:0] writeLogic_adapter_aw_payload_lock; - wire [3:0] writeLogic_adapter_aw_payload_cache; - wire [3:0] writeLogic_adapter_aw_payload_qos; - wire [2:0] writeLogic_adapter_aw_payload_prot; - wire writeLogic_adapter_w_valid; - wire writeLogic_adapter_w_ready; - wire [127:0] writeLogic_adapter_w_payload_data; - wire [15:0] writeLogic_adapter_w_payload_strb; - wire writeLogic_adapter_w_payload_last; - wire writeLogic_adapter_b_valid; - wire writeLogic_adapter_b_ready; - wire [1:0] writeLogic_adapter_b_payload_resp; - wire [3:0] _zz_writeLogic_adapter_aw_payload_region; - wire writeLogic_adapter_aw_halfPipe_valid; - wire writeLogic_adapter_aw_halfPipe_ready; - wire [31:0] writeLogic_adapter_aw_halfPipe_payload_addr; - wire [3:0] writeLogic_adapter_aw_halfPipe_payload_region; - wire [7:0] writeLogic_adapter_aw_halfPipe_payload_len; - wire [2:0] writeLogic_adapter_aw_halfPipe_payload_size; - wire [1:0] writeLogic_adapter_aw_halfPipe_payload_burst; - wire [0:0] writeLogic_adapter_aw_halfPipe_payload_lock; - wire [3:0] writeLogic_adapter_aw_halfPipe_payload_cache; - wire [3:0] writeLogic_adapter_aw_halfPipe_payload_qos; - wire [2:0] writeLogic_adapter_aw_halfPipe_payload_prot; - reg writeLogic_adapter_aw_rValid; - wire writeLogic_adapter_aw_halfPipe_fire; - reg [31:0] writeLogic_adapter_aw_rData_addr; - reg [3:0] writeLogic_adapter_aw_rData_region; - reg [7:0] writeLogic_adapter_aw_rData_len; - reg [2:0] writeLogic_adapter_aw_rData_size; - reg [1:0] writeLogic_adapter_aw_rData_burst; - reg [0:0] writeLogic_adapter_aw_rData_lock; - reg [3:0] writeLogic_adapter_aw_rData_cache; - reg [3:0] writeLogic_adapter_aw_rData_qos; - reg [2:0] writeLogic_adapter_aw_rData_prot; - wire writeLogic_adapter_w_s2mPipe_valid; - reg writeLogic_adapter_w_s2mPipe_ready; - wire [127:0] writeLogic_adapter_w_s2mPipe_payload_data; - wire [15:0] writeLogic_adapter_w_s2mPipe_payload_strb; - wire writeLogic_adapter_w_s2mPipe_payload_last; - reg writeLogic_adapter_w_rValidN; - reg [127:0] writeLogic_adapter_w_rData_data; - reg [15:0] writeLogic_adapter_w_rData_strb; - reg writeLogic_adapter_w_rData_last; - wire writeLogic_adapter_w_s2mPipe_m2sPipe_valid; - wire writeLogic_adapter_w_s2mPipe_m2sPipe_ready; - wire [127:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; - wire [15:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; - wire writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; - reg writeLogic_adapter_w_s2mPipe_rValid; - reg [127:0] writeLogic_adapter_w_s2mPipe_rData_data; - reg [15:0] writeLogic_adapter_w_s2mPipe_rData_strb; - reg writeLogic_adapter_w_s2mPipe_rData_last; - wire when_Stream_l375_3; - wire write_b_halfPipe_valid; - wire write_b_halfPipe_ready; - wire [1:0] write_b_halfPipe_payload_resp; - reg write_b_rValid; - wire write_b_halfPipe_fire; - reg [1:0] write_b_rData_resp; - wire io_pop_s2mPipe_valid; - reg io_pop_s2mPipe_ready; - wire [63:0] io_pop_s2mPipe_payload_data; - wire [7:0] io_pop_s2mPipe_payload_mask; - wire [3:0] io_pop_s2mPipe_payload_sink; - wire io_pop_s2mPipe_payload_last; - reg io_pop_rValidN; - reg [63:0] io_pop_rData_data; - reg [7:0] io_pop_rData_mask; - reg [3:0] io_pop_rData_sink; - reg io_pop_rData_last; - wire io_pop_s2mPipe_m2sPipe_valid; - wire io_pop_s2mPipe_m2sPipe_ready; - wire [63:0] io_pop_s2mPipe_m2sPipe_payload_data; - wire [7:0] io_pop_s2mPipe_m2sPipe_payload_mask; - wire [3:0] io_pop_s2mPipe_m2sPipe_payload_sink; - wire io_pop_s2mPipe_m2sPipe_payload_last; - reg io_pop_s2mPipe_rValid; - reg [63:0] io_pop_s2mPipe_rData_data; - reg [7:0] io_pop_s2mPipe_rData_mask; - reg [3:0] io_pop_s2mPipe_rData_sink; - reg io_pop_s2mPipe_rData_last; - wire when_Stream_l375_4; - wire io_outputs_0_s2mPipe_valid; - reg io_outputs_0_s2mPipe_ready; - wire [63:0] io_outputs_0_s2mPipe_payload_data; - wire [7:0] io_outputs_0_s2mPipe_payload_mask; - wire [3:0] io_outputs_0_s2mPipe_payload_sink; - wire io_outputs_0_s2mPipe_payload_last; - reg io_outputs_0_rValidN; - reg [63:0] io_outputs_0_rData_data; - reg [7:0] io_outputs_0_rData_mask; - reg [3:0] io_outputs_0_rData_sink; - reg io_outputs_0_rData_last; - wire outputsAdapter_0_ptr_valid; - wire outputsAdapter_0_ptr_ready; - wire [63:0] outputsAdapter_0_ptr_payload_data; - wire [7:0] outputsAdapter_0_ptr_payload_mask; - wire [3:0] outputsAdapter_0_ptr_payload_sink; - wire outputsAdapter_0_ptr_payload_last; - reg io_outputs_0_s2mPipe_rValid; - reg [63:0] io_outputs_0_s2mPipe_rData_data; - reg [7:0] io_outputs_0_s2mPipe_rData_mask; - reg [3:0] io_outputs_0_s2mPipe_rData_sink; - reg io_outputs_0_s2mPipe_rData_last; - wire when_Stream_l375_5; - - EfxDMA_Core core ( - .io_sgRead_cmd_valid (core_io_sgRead_cmd_valid ), //o - .io_sgRead_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i - .io_sgRead_cmd_payload_last (core_io_sgRead_cmd_payload_last ), //o - .io_sgRead_cmd_payload_fragment_opcode (core_io_sgRead_cmd_payload_fragment_opcode ), //o - .io_sgRead_cmd_payload_fragment_address (core_io_sgRead_cmd_payload_fragment_address[31:0] ), //o - .io_sgRead_cmd_payload_fragment_length (core_io_sgRead_cmd_payload_fragment_length[4:0] ), //o - .io_sgRead_cmd_payload_fragment_context (core_io_sgRead_cmd_payload_fragment_context ), //o - .io_sgRead_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i - .io_sgRead_rsp_ready (core_io_sgRead_rsp_ready ), //o - .io_sgRead_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i - .io_sgRead_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i - .io_sgRead_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data[127:0] ), //i - .io_sgRead_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i - .io_sgWrite_cmd_valid (core_io_sgWrite_cmd_valid ), //o - .io_sgWrite_cmd_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i - .io_sgWrite_cmd_payload_last (core_io_sgWrite_cmd_payload_last ), //o - .io_sgWrite_cmd_payload_fragment_opcode (core_io_sgWrite_cmd_payload_fragment_opcode ), //o - .io_sgWrite_cmd_payload_fragment_address (core_io_sgWrite_cmd_payload_fragment_address[31:0] ), //o - .io_sgWrite_cmd_payload_fragment_length (core_io_sgWrite_cmd_payload_fragment_length[1:0] ), //o - .io_sgWrite_cmd_payload_fragment_data (core_io_sgWrite_cmd_payload_fragment_data[127:0] ), //o - .io_sgWrite_cmd_payload_fragment_mask (core_io_sgWrite_cmd_payload_fragment_mask[15:0] ), //o - .io_sgWrite_cmd_payload_fragment_context (core_io_sgWrite_cmd_payload_fragment_context ), //o - .io_sgWrite_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i - .io_sgWrite_rsp_ready (core_io_sgWrite_rsp_ready ), //o - .io_sgWrite_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i - .io_sgWrite_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i - .io_sgWrite_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i - .io_read_cmd_valid (core_io_read_cmd_valid ), //o - .io_read_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready ), //i - .io_read_cmd_payload_last (core_io_read_cmd_payload_last ), //o - .io_read_cmd_payload_fragment_opcode (core_io_read_cmd_payload_fragment_opcode ), //o - .io_read_cmd_payload_fragment_address (core_io_read_cmd_payload_fragment_address[31:0] ), //o - .io_read_cmd_payload_fragment_length (core_io_read_cmd_payload_fragment_length[11:0] ), //o - .io_read_cmd_payload_fragment_context (core_io_read_cmd_payload_fragment_context[20:0] ), //o - .io_read_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i - .io_read_rsp_ready (core_io_read_rsp_ready ), //o - .io_read_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i - .io_read_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i - .io_read_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data[127:0] ), //i - .io_read_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[20:0] ), //i - .io_write_cmd_valid (core_io_write_cmd_valid ), //o - .io_write_cmd_ready (io_write_cmd_rValidN ), //i - .io_write_cmd_payload_last (core_io_write_cmd_payload_last ), //o - .io_write_cmd_payload_fragment_opcode (core_io_write_cmd_payload_fragment_opcode ), //o - .io_write_cmd_payload_fragment_address (core_io_write_cmd_payload_fragment_address[31:0] ), //o - .io_write_cmd_payload_fragment_length (core_io_write_cmd_payload_fragment_length[11:0] ), //o - .io_write_cmd_payload_fragment_data (core_io_write_cmd_payload_fragment_data[127:0] ), //o - .io_write_cmd_payload_fragment_mask (core_io_write_cmd_payload_fragment_mask[15:0] ), //o - .io_write_cmd_payload_fragment_context (core_io_write_cmd_payload_fragment_context[12:0] ), //o - .io_write_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i - .io_write_rsp_ready (core_io_write_rsp_ready ), //o - .io_write_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i - .io_write_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i - .io_write_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[12:0]), //i - .io_outputs_0_valid (core_io_outputs_0_valid ), //o - .io_outputs_0_ready (io_outputs_0_rValidN ), //i - .io_outputs_0_payload_data (core_io_outputs_0_payload_data[63:0] ), //o - .io_outputs_0_payload_mask (core_io_outputs_0_payload_mask[7:0] ), //o - .io_outputs_0_payload_sink (core_io_outputs_0_payload_sink[3:0] ), //o - .io_outputs_0_payload_last (core_io_outputs_0_payload_last ), //o - .io_inputs_0_valid (io_pop_s2mPipe_m2sPipe_valid ), //i - .io_inputs_0_ready (core_io_inputs_0_ready ), //o - .io_inputs_0_payload_data (io_pop_s2mPipe_m2sPipe_payload_data[63:0] ), //i - .io_inputs_0_payload_mask (io_pop_s2mPipe_m2sPipe_payload_mask[7:0] ), //i - .io_inputs_0_payload_sink (io_pop_s2mPipe_m2sPipe_payload_sink[3:0] ), //i - .io_inputs_0_payload_last (io_pop_s2mPipe_m2sPipe_payload_last ), //i - .io_interrupts (core_io_interrupts[1:0] ), //o - .io_ctrl_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //i - .io_ctrl_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //i - .io_ctrl_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //i - .io_ctrl_PREADY (core_io_ctrl_PREADY ), //o - .io_ctrl_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //i - .io_ctrl_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0] ), //i - .io_ctrl_PRDATA (core_io_ctrl_PRDATA[31:0] ), //o - .io_ctrl_PSLVERROR (core_io_ctrl_PSLVERROR ), //o - .ll_0_descriptorUpdate (core_ll_0_descriptorUpdate ), //o - .ll_1_descriptorUpdate (core_ll_1_descriptorUpdate ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_Apb3CC withCtrlCc_apbCc ( - .io_input_PADDR (ctrl_PADDR[13:0] ), //i - .io_input_PSEL (ctrl_PSEL ), //i - .io_input_PENABLE (ctrl_PENABLE ), //i - .io_input_PREADY (withCtrlCc_apbCc_io_input_PREADY ), //o - .io_input_PWRITE (ctrl_PWRITE ), //i - .io_input_PWDATA (ctrl_PWDATA[31:0] ), //i - .io_input_PRDATA (withCtrlCc_apbCc_io_input_PRDATA[31:0] ), //o - .io_input_PSLVERROR (withCtrlCc_apbCc_io_input_PSLVERROR ), //o - .io_output_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //o - .io_output_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //o - .io_output_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //o - .io_output_PREADY (core_io_ctrl_PREADY ), //i - .io_output_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //o - .io_output_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0]), //o - .io_output_PRDATA (core_io_ctrl_PRDATA[31:0] ), //i - .io_output_PSLVERROR (core_io_ctrl_PSLVERROR ), //i - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_6 io_interrupts_buffercc ( - .io_dataIn (core_io_interrupts[1:0] ), //i - .io_dataOut (io_interrupts_buffercc_io_dataOut[1:0]), //o - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ) //i - ); - EfxDMA_BmbSourceRemover readLogic_sourceRemover ( - .io_input_cmd_valid (readLogic_resized_cmd_valid ), //i - .io_input_cmd_ready (readLogic_sourceRemover_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (readLogic_resized_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (readLogic_resized_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (readLogic_resized_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (readLogic_resized_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (readLogic_resized_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_context (readLogic_resized_cmd_payload_fragment_context[20:0] ), //i - .io_input_rsp_valid (readLogic_sourceRemover_io_input_rsp_valid ), //o - .io_input_rsp_ready (readLogic_resized_rsp_ready ), //i - .io_input_rsp_payload_last (readLogic_sourceRemover_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (readLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (readLogic_sourceRemover_io_input_rsp_payload_fragment_data[127:0] ), //o - .io_input_rsp_payload_fragment_context (readLogic_sourceRemover_io_input_rsp_payload_fragment_context[20:0] ), //o - .io_output_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //o - .io_output_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //i - .io_output_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o - .io_output_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //o - .io_output_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //i - .io_output_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //i - .io_output_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ) //i - ); - EfxDMA_BmbToAxi4ReadOnlyBridge readLogic_bridge ( - .io_input_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //i - .io_input_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i - .io_input_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //i - .io_input_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //o - .io_input_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //i - .io_input_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //o - .io_input_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ), //o - .io_output_ar_valid (readLogic_bridge_io_output_ar_valid ), //o - .io_output_ar_ready (readLogic_adapter_ar_ready ), //i - .io_output_ar_payload_addr (readLogic_bridge_io_output_ar_payload_addr[31:0] ), //o - .io_output_ar_payload_len (readLogic_bridge_io_output_ar_payload_len[7:0] ), //o - .io_output_ar_payload_size (readLogic_bridge_io_output_ar_payload_size[2:0] ), //o - .io_output_ar_payload_cache (readLogic_bridge_io_output_ar_payload_cache[3:0] ), //o - .io_output_ar_payload_prot (readLogic_bridge_io_output_ar_payload_prot[2:0] ), //o - .io_output_r_valid (readLogic_adapter_r_valid ), //i - .io_output_r_ready (readLogic_bridge_io_output_r_ready ), //o - .io_output_r_payload_data (readLogic_adapter_r_payload_data[127:0] ), //i - .io_output_r_payload_resp (readLogic_adapter_r_payload_resp[1:0] ), //i - .io_output_r_payload_last (readLogic_adapter_r_payload_last ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_BmbSourceRemover_1 writeLogic_sourceRemover ( - .io_input_cmd_valid (writeLogic_resized_cmd_valid ), //i - .io_input_cmd_ready (writeLogic_sourceRemover_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (writeLogic_resized_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (writeLogic_resized_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (writeLogic_resized_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (writeLogic_resized_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (writeLogic_resized_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_data (writeLogic_resized_cmd_payload_fragment_data[127:0] ), //i - .io_input_cmd_payload_fragment_mask (writeLogic_resized_cmd_payload_fragment_mask[15:0] ), //i - .io_input_cmd_payload_fragment_context (writeLogic_resized_cmd_payload_fragment_context[12:0] ), //i - .io_input_rsp_valid (writeLogic_sourceRemover_io_input_rsp_valid ), //o - .io_input_rsp_ready (writeLogic_resized_rsp_ready ), //i - .io_input_rsp_payload_last (writeLogic_sourceRemover_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (writeLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_context (writeLogic_sourceRemover_io_input_rsp_payload_fragment_context[12:0] ), //o - .io_output_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //o - .io_output_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //i - .io_output_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o - .io_output_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //o - .io_output_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o - .io_output_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //o - .io_output_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //i - .io_output_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ) //i - ); - EfxDMA_BmbToAxi4WriteOnlyBridge writeLogic_bridge ( - .io_input_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //i - .io_input_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i - .io_input_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //i - .io_input_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //i - .io_input_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //i - .io_input_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //o - .io_input_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //i - .io_input_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ), //o - .io_output_aw_valid (writeLogic_bridge_io_output_aw_valid ), //o - .io_output_aw_ready (writeLogic_adapter_aw_ready ), //i - .io_output_aw_payload_addr (writeLogic_bridge_io_output_aw_payload_addr[31:0] ), //o - .io_output_aw_payload_len (writeLogic_bridge_io_output_aw_payload_len[7:0] ), //o - .io_output_aw_payload_size (writeLogic_bridge_io_output_aw_payload_size[2:0] ), //o - .io_output_aw_payload_cache (writeLogic_bridge_io_output_aw_payload_cache[3:0] ), //o - .io_output_aw_payload_prot (writeLogic_bridge_io_output_aw_payload_prot[2:0] ), //o - .io_output_w_valid (writeLogic_bridge_io_output_w_valid ), //o - .io_output_w_ready (writeLogic_adapter_w_ready ), //i - .io_output_w_payload_data (writeLogic_bridge_io_output_w_payload_data[127:0] ), //o - .io_output_w_payload_strb (writeLogic_bridge_io_output_w_payload_strb[15:0] ), //o - .io_output_w_payload_last (writeLogic_bridge_io_output_w_payload_last ), //o - .io_output_b_valid (writeLogic_adapter_b_valid ), //i - .io_output_b_ready (writeLogic_bridge_io_output_b_ready ), //o - .io_output_b_payload_resp (writeLogic_adapter_b_payload_resp[1:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_BsbUpSizerDense inputsAdapter_0_upsizer_logic ( - .io_input_valid (dat0_i_tvalid ), //i - .io_input_ready (inputsAdapter_0_upsizer_logic_io_input_ready ), //o - .io_input_payload_data (dat0_i_tdata[7:0] ), //i - .io_input_payload_mask (dat0_i_tkeep ), //i - .io_input_payload_sink (dat0_i_tdest[3:0] ), //i - .io_input_payload_last (dat0_i_tlast ), //i - .io_output_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //o - .io_output_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //i - .io_output_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //o - .io_output_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //o - .io_output_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //o - .io_output_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //o - .dat0_i_clk (dat0_i_clk ), //i - .dat0_i_reset (dat0_i_reset ) //i - ); - EfxDMA_StreamFifoCC inputsAdapter_0_crossclock_fifo ( - .io_push_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //i - .io_push_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //o - .io_push_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //i - .io_push_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //i - .io_push_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //i - .io_push_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //i - .io_pop_valid (inputsAdapter_0_crossclock_fifo_io_pop_valid ), //o - .io_pop_ready (io_pop_rValidN ), //i - .io_pop_payload_data (inputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //o - .io_pop_payload_mask (inputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o - .io_pop_payload_sink (inputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o - .io_pop_payload_last (inputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o - .io_pushOccupancy (inputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o - .io_popOccupancy (inputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o - .dat0_i_clk (dat0_i_clk ), //i - .dat0_i_reset (dat0_i_reset ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_StreamFifoCC_1 outputsAdapter_0_crossclock_fifo ( - .io_push_valid (outputsAdapter_0_ptr_valid ), //i - .io_push_ready (outputsAdapter_0_crossclock_fifo_io_push_ready ), //o - .io_push_payload_data (outputsAdapter_0_ptr_payload_data[63:0] ), //i - .io_push_payload_mask (outputsAdapter_0_ptr_payload_mask[7:0] ), //i - .io_push_payload_sink (outputsAdapter_0_ptr_payload_sink[3:0] ), //i - .io_push_payload_last (outputsAdapter_0_ptr_payload_last ), //i - .io_pop_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //o - .io_pop_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //i - .io_pop_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0]), //o - .io_pop_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o - .io_pop_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o - .io_pop_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o - .io_pushOccupancy (outputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o - .io_popOccupancy (outputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o - .clk (clk ), //i - .reset (reset ), //i - .dat1_o_clk (dat1_o_clk ), //i - .dat1_o_reset (dat1_o_reset ) //i - ); - EfxDMA_BsbDownSizerSparse outputsAdapter_0_sparseDownsizer_logic ( - .io_input_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //i - .io_input_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //o - .io_input_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //i - .io_input_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //i - .io_input_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //i - .io_input_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //i - .io_output_valid (outputsAdapter_0_sparseDownsizer_logic_io_output_valid ), //o - .io_output_ready (dat1_o_tready ), //i - .io_output_payload_data (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data[7:0]), //o - .io_output_payload_mask (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask ), //o - .io_output_payload_sink (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink[3:0]), //o - .io_output_payload_last (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last ), //o - .dat1_o_clk (dat1_o_clk ), //i - .dat1_o_reset (dat1_o_reset ) //i - ); - EfxDMA_BmbArbiter interconnect_read_aggregated_arbiter ( - .io_inputs_0_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i - .io_inputs_0_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready ), //o - .io_inputs_0_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i - .io_inputs_0_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_0_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_0_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[4:0] ), //i - .io_inputs_0_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i - .io_inputs_0_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid ), //o - .io_inputs_0_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i - .io_inputs_0_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o - .io_inputs_0_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o - .io_inputs_0_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data[127:0] ), //o - .io_inputs_0_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o - .io_inputs_1_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i - .io_inputs_1_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready ), //o - .io_inputs_1_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i - .io_inputs_1_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_1_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_1_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i - .io_inputs_1_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[20:0]), //i - .io_inputs_1_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid ), //o - .io_inputs_1_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i - .io_inputs_1_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o - .io_inputs_1_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o - .io_inputs_1_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data[127:0] ), //o - .io_inputs_1_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[20:0] ), //o - .io_output_cmd_valid (interconnect_read_aggregated_arbiter_io_output_cmd_valid ), //o - .io_output_cmd_ready (interconnect_read_aggregated_cmd_ready ), //i - .io_output_cmd_payload_last (interconnect_read_aggregated_arbiter_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_source (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o - .io_output_cmd_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_cmd_payload_fragment_context (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context[20:0] ), //o - .io_output_rsp_valid (interconnect_read_aggregated_rsp_valid ), //i - .io_output_rsp_ready (interconnect_read_aggregated_arbiter_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (interconnect_read_aggregated_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_source (interconnect_read_aggregated_rsp_payload_fragment_source ), //i - .io_output_rsp_payload_fragment_opcode (interconnect_read_aggregated_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (interconnect_read_aggregated_rsp_payload_fragment_data[127:0] ), //i - .io_output_rsp_payload_fragment_context (interconnect_read_aggregated_rsp_payload_fragment_context[20:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_BmbArbiter_1 interconnect_write_aggregated_arbiter ( - .io_inputs_0_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i - .io_inputs_0_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready ), //o - .io_inputs_0_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i - .io_inputs_0_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_0_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_0_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[1:0] ), //i - .io_inputs_0_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[127:0] ), //i - .io_inputs_0_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[15:0] ), //i - .io_inputs_0_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i - .io_inputs_0_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid ), //o - .io_inputs_0_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i - .io_inputs_0_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o - .io_inputs_0_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o - .io_inputs_0_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o - .io_inputs_1_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i - .io_inputs_1_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready ), //o - .io_inputs_1_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i - .io_inputs_1_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_1_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_1_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i - .io_inputs_1_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data[127:0] ), //i - .io_inputs_1_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask[15:0] ), //i - .io_inputs_1_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[12:0]), //i - .io_inputs_1_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid ), //o - .io_inputs_1_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i - .io_inputs_1_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o - .io_inputs_1_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o - .io_inputs_1_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[12:0] ), //o - .io_output_cmd_valid (interconnect_write_aggregated_arbiter_io_output_cmd_valid ), //o - .io_output_cmd_ready (interconnect_write_aggregated_cmd_ready ), //i - .io_output_cmd_payload_last (interconnect_write_aggregated_arbiter_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_source (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o - .io_output_cmd_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_cmd_payload_fragment_data (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data[127:0] ), //o - .io_output_cmd_payload_fragment_mask (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask[15:0] ), //o - .io_output_cmd_payload_fragment_context (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context[12:0] ), //o - .io_output_rsp_valid (interconnect_write_aggregated_rsp_valid ), //i - .io_output_rsp_ready (interconnect_write_aggregated_arbiter_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (interconnect_write_aggregated_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_source (interconnect_write_aggregated_rsp_payload_fragment_source ), //i - .io_output_rsp_payload_fragment_opcode (interconnect_write_aggregated_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_context (interconnect_write_aggregated_rsp_payload_fragment_context[12:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_0_descriptorUpdate = core_ll_0_descriptorUpdate; - assign io_1_descriptorUpdate = core_ll_1_descriptorUpdate; - assign ctrl_PREADY = withCtrlCc_apbCc_io_input_PREADY; - assign ctrl_PRDATA = withCtrlCc_apbCc_io_input_PRDATA; - assign ctrl_PSLVERROR = withCtrlCc_apbCc_io_input_PSLVERROR; - assign ctrl_interrupts = io_interrupts_buffercc_io_dataOut; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = core_io_read_cmd_valid; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_read_rsp_ready; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = core_io_read_cmd_payload_last; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = core_io_read_cmd_payload_fragment_opcode; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = core_io_read_cmd_payload_fragment_address; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = core_io_read_cmd_payload_fragment_length; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = core_io_read_cmd_payload_fragment_context; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgRead_cmd_valid; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgRead_rsp_ready; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgRead_cmd_payload_last; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgRead_cmd_payload_fragment_opcode; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgRead_cmd_payload_fragment_address; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgRead_cmd_payload_fragment_length; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgRead_cmd_payload_fragment_context; - assign io_write_cmd_s2mPipe_valid = (core_io_write_cmd_valid || (! io_write_cmd_rValidN)); - assign io_write_cmd_s2mPipe_payload_last = (io_write_cmd_rValidN ? core_io_write_cmd_payload_last : io_write_cmd_rData_last); - assign io_write_cmd_s2mPipe_payload_fragment_opcode = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_opcode : io_write_cmd_rData_fragment_opcode); - assign io_write_cmd_s2mPipe_payload_fragment_address = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_address : io_write_cmd_rData_fragment_address); - assign io_write_cmd_s2mPipe_payload_fragment_length = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_length : io_write_cmd_rData_fragment_length); - assign io_write_cmd_s2mPipe_payload_fragment_data = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_data : io_write_cmd_rData_fragment_data); - assign io_write_cmd_s2mPipe_payload_fragment_mask = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_mask : io_write_cmd_rData_fragment_mask); - assign io_write_cmd_s2mPipe_payload_fragment_context = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_context : io_write_cmd_rData_fragment_context); - always @(*) begin - io_write_cmd_s2mPipe_ready = io_write_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l375) begin - io_write_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! io_write_cmd_s2mPipe_m2sPipe_valid); - assign io_write_cmd_s2mPipe_m2sPipe_valid = io_write_cmd_s2mPipe_rValid; - assign io_write_cmd_s2mPipe_m2sPipe_payload_last = io_write_cmd_s2mPipe_rData_last; - assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = io_write_cmd_s2mPipe_rData_fragment_opcode; - assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address = io_write_cmd_s2mPipe_rData_fragment_address; - assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length = io_write_cmd_s2mPipe_rData_fragment_length; - assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data = io_write_cmd_s2mPipe_rData_fragment_data; - assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask = io_write_cmd_s2mPipe_rData_fragment_mask; - assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context = io_write_cmd_s2mPipe_rData_fragment_context; - assign io_write_cmd_s2mPipe_m2sPipe_ready = interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = io_write_cmd_s2mPipe_m2sPipe_valid; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_write_rsp_ready; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = io_write_cmd_s2mPipe_m2sPipe_payload_last; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgWrite_cmd_valid; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgWrite_rsp_ready; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgWrite_cmd_payload_last; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgWrite_cmd_payload_fragment_opcode; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgWrite_cmd_payload_fragment_address; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgWrite_cmd_payload_fragment_length; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = core_io_sgWrite_cmd_payload_fragment_data; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = core_io_sgWrite_cmd_payload_fragment_mask; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgWrite_cmd_payload_fragment_context; - assign interconnect_read_aggregated_cmd_halfPipe_fire = (interconnect_read_aggregated_cmd_halfPipe_valid && interconnect_read_aggregated_cmd_halfPipe_ready); - assign interconnect_read_aggregated_cmd_ready = (! interconnect_read_aggregated_cmd_rValid); - assign interconnect_read_aggregated_cmd_halfPipe_valid = interconnect_read_aggregated_cmd_rValid; - assign interconnect_read_aggregated_cmd_halfPipe_payload_last = interconnect_read_aggregated_cmd_rData_last; - assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source = interconnect_read_aggregated_cmd_rData_fragment_source; - assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode = interconnect_read_aggregated_cmd_rData_fragment_opcode; - assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address = interconnect_read_aggregated_cmd_rData_fragment_address; - assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length = interconnect_read_aggregated_cmd_rData_fragment_length; - assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context = interconnect_read_aggregated_cmd_rData_fragment_context; - assign readLogic_resized_cmd_valid = interconnect_read_aggregated_cmd_halfPipe_valid; - assign interconnect_read_aggregated_cmd_halfPipe_ready = readLogic_resized_cmd_ready; - assign readLogic_resized_cmd_payload_last = interconnect_read_aggregated_cmd_halfPipe_payload_last; - assign readLogic_resized_cmd_payload_fragment_source = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; - assign readLogic_resized_cmd_payload_fragment_opcode = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; - assign readLogic_resized_cmd_payload_fragment_address = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; - assign readLogic_resized_cmd_payload_fragment_length = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; - assign readLogic_resized_cmd_payload_fragment_context = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; - assign readLogic_resized_rsp_combStage_valid = readLogic_resized_rsp_valid; - assign readLogic_resized_rsp_ready = readLogic_resized_rsp_combStage_ready; - assign readLogic_resized_rsp_combStage_payload_last = readLogic_resized_rsp_payload_last; - assign readLogic_resized_rsp_combStage_payload_fragment_source = readLogic_resized_rsp_payload_fragment_source; - assign readLogic_resized_rsp_combStage_payload_fragment_opcode = readLogic_resized_rsp_payload_fragment_opcode; - assign readLogic_resized_rsp_combStage_payload_fragment_data = readLogic_resized_rsp_payload_fragment_data; - assign readLogic_resized_rsp_combStage_payload_fragment_context = readLogic_resized_rsp_payload_fragment_context; - assign interconnect_read_aggregated_rsp_valid = readLogic_resized_rsp_combStage_valid; - assign readLogic_resized_rsp_combStage_ready = interconnect_read_aggregated_rsp_ready; - assign interconnect_read_aggregated_rsp_payload_last = readLogic_resized_rsp_combStage_payload_last; - assign interconnect_read_aggregated_rsp_payload_fragment_source = readLogic_resized_rsp_combStage_payload_fragment_source; - assign interconnect_read_aggregated_rsp_payload_fragment_opcode = readLogic_resized_rsp_combStage_payload_fragment_opcode; - assign interconnect_read_aggregated_rsp_payload_fragment_data = readLogic_resized_rsp_combStage_payload_fragment_data; - assign interconnect_read_aggregated_rsp_payload_fragment_context = readLogic_resized_rsp_combStage_payload_fragment_context; - assign readLogic_resized_cmd_ready = readLogic_sourceRemover_io_input_cmd_ready; - assign readLogic_resized_rsp_valid = readLogic_sourceRemover_io_input_rsp_valid; - assign readLogic_resized_rsp_payload_last = readLogic_sourceRemover_io_input_rsp_payload_last; - assign readLogic_resized_rsp_payload_fragment_source = readLogic_sourceRemover_io_input_rsp_payload_fragment_source; - assign readLogic_resized_rsp_payload_fragment_opcode = readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; - assign readLogic_resized_rsp_payload_fragment_data = readLogic_sourceRemover_io_input_rsp_payload_fragment_data; - assign readLogic_resized_rsp_payload_fragment_context = readLogic_sourceRemover_io_input_rsp_payload_fragment_context; - assign readLogic_adapter_ar_valid = readLogic_bridge_io_output_ar_valid; - assign readLogic_adapter_ar_payload_addr = readLogic_bridge_io_output_ar_payload_addr; - assign _zz_readLogic_adapter_ar_payload_region[3 : 0] = 4'b0000; - assign readLogic_adapter_ar_payload_region = _zz_readLogic_adapter_ar_payload_region; - assign readLogic_adapter_ar_payload_len = readLogic_bridge_io_output_ar_payload_len; - assign readLogic_adapter_ar_payload_size = readLogic_bridge_io_output_ar_payload_size; - assign readLogic_adapter_ar_payload_burst = 2'b01; - assign readLogic_adapter_ar_payload_lock = 1'b0; - assign readLogic_adapter_ar_payload_cache = readLogic_bridge_io_output_ar_payload_cache; - assign readLogic_adapter_ar_payload_qos = 4'b0000; - assign readLogic_adapter_ar_payload_prot = readLogic_bridge_io_output_ar_payload_prot; - assign readLogic_adapter_r_ready = readLogic_bridge_io_output_r_ready; - assign readLogic_adapter_ar_halfPipe_fire = (readLogic_adapter_ar_halfPipe_valid && readLogic_adapter_ar_halfPipe_ready); - assign readLogic_adapter_ar_ready = (! readLogic_adapter_ar_rValid); - assign readLogic_adapter_ar_halfPipe_valid = readLogic_adapter_ar_rValid; - assign readLogic_adapter_ar_halfPipe_payload_addr = readLogic_adapter_ar_rData_addr; - assign readLogic_adapter_ar_halfPipe_payload_region = readLogic_adapter_ar_rData_region; - assign readLogic_adapter_ar_halfPipe_payload_len = readLogic_adapter_ar_rData_len; - assign readLogic_adapter_ar_halfPipe_payload_size = readLogic_adapter_ar_rData_size; - assign readLogic_adapter_ar_halfPipe_payload_burst = readLogic_adapter_ar_rData_burst; - assign readLogic_adapter_ar_halfPipe_payload_lock = readLogic_adapter_ar_rData_lock; - assign readLogic_adapter_ar_halfPipe_payload_cache = readLogic_adapter_ar_rData_cache; - assign readLogic_adapter_ar_halfPipe_payload_qos = readLogic_adapter_ar_rData_qos; - assign readLogic_adapter_ar_halfPipe_payload_prot = readLogic_adapter_ar_rData_prot; - assign read_arvalid = readLogic_adapter_ar_halfPipe_valid; - assign readLogic_adapter_ar_halfPipe_ready = read_arready; - assign read_araddr = readLogic_adapter_ar_halfPipe_payload_addr; - assign read_arregion = readLogic_adapter_ar_halfPipe_payload_region; - assign read_arlen = readLogic_adapter_ar_halfPipe_payload_len; - assign read_arsize = readLogic_adapter_ar_halfPipe_payload_size; - assign read_arburst = readLogic_adapter_ar_halfPipe_payload_burst; - assign read_arlock = readLogic_adapter_ar_halfPipe_payload_lock; - assign read_arcache = readLogic_adapter_ar_halfPipe_payload_cache; - assign read_arqos = readLogic_adapter_ar_halfPipe_payload_qos; - assign read_arprot = readLogic_adapter_ar_halfPipe_payload_prot; - assign read_rready = read_r_rValidN; - assign read_r_s2mPipe_valid = (read_rvalid || (! read_r_rValidN)); - assign read_r_s2mPipe_payload_data = (read_r_rValidN ? read_rdata : read_r_rData_data); - assign read_r_s2mPipe_payload_resp = (read_r_rValidN ? read_rresp : read_r_rData_resp); - assign read_r_s2mPipe_payload_last = (read_r_rValidN ? read_rlast : read_r_rData_last); - always @(*) begin - read_r_s2mPipe_ready = readLogic_beforeQueue_ready; - if(when_Stream_l375_1) begin - read_r_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l375_1 = (! readLogic_beforeQueue_valid); - assign readLogic_beforeQueue_valid = read_r_s2mPipe_rValid; - assign readLogic_beforeQueue_payload_data = read_r_s2mPipe_rData_data; - assign readLogic_beforeQueue_payload_resp = read_r_s2mPipe_rData_resp; - assign readLogic_beforeQueue_payload_last = read_r_s2mPipe_rData_last; - assign readLogic_adapter_r_valid = readLogic_beforeQueue_valid; - assign readLogic_beforeQueue_ready = readLogic_adapter_r_ready; - assign readLogic_adapter_r_payload_data = readLogic_beforeQueue_payload_data; - assign readLogic_adapter_r_payload_resp = readLogic_beforeQueue_payload_resp; - assign readLogic_adapter_r_payload_last = readLogic_beforeQueue_payload_last; - always @(*) begin - interconnect_write_aggregated_cmd_ready = interconnect_write_aggregated_cmd_m2sPipe_ready; - if(when_Stream_l375_2) begin - interconnect_write_aggregated_cmd_ready = 1'b1; - end - end - - assign when_Stream_l375_2 = (! interconnect_write_aggregated_cmd_m2sPipe_valid); - assign interconnect_write_aggregated_cmd_m2sPipe_valid = interconnect_write_aggregated_cmd_rValid; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_last = interconnect_write_aggregated_cmd_rData_last; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source = interconnect_write_aggregated_cmd_rData_fragment_source; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode = interconnect_write_aggregated_cmd_rData_fragment_opcode; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address = interconnect_write_aggregated_cmd_rData_fragment_address; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length = interconnect_write_aggregated_cmd_rData_fragment_length; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data = interconnect_write_aggregated_cmd_rData_fragment_data; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask = interconnect_write_aggregated_cmd_rData_fragment_mask; - assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context = interconnect_write_aggregated_cmd_rData_fragment_context; - assign writeLogic_resized_cmd_valid = interconnect_write_aggregated_cmd_m2sPipe_valid; - assign interconnect_write_aggregated_cmd_m2sPipe_ready = writeLogic_resized_cmd_ready; - assign writeLogic_resized_cmd_payload_last = interconnect_write_aggregated_cmd_m2sPipe_payload_last; - assign writeLogic_resized_cmd_payload_fragment_source = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; - assign writeLogic_resized_cmd_payload_fragment_opcode = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; - assign writeLogic_resized_cmd_payload_fragment_address = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; - assign writeLogic_resized_cmd_payload_fragment_length = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; - assign writeLogic_resized_cmd_payload_fragment_data = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; - assign writeLogic_resized_cmd_payload_fragment_mask = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; - assign writeLogic_resized_cmd_payload_fragment_context = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; - assign writeLogic_resized_rsp_combStage_valid = writeLogic_resized_rsp_valid; - assign writeLogic_resized_rsp_ready = writeLogic_resized_rsp_combStage_ready; - assign writeLogic_resized_rsp_combStage_payload_last = writeLogic_resized_rsp_payload_last; - assign writeLogic_resized_rsp_combStage_payload_fragment_source = writeLogic_resized_rsp_payload_fragment_source; - assign writeLogic_resized_rsp_combStage_payload_fragment_opcode = writeLogic_resized_rsp_payload_fragment_opcode; - assign writeLogic_resized_rsp_combStage_payload_fragment_context = writeLogic_resized_rsp_payload_fragment_context; - assign interconnect_write_aggregated_rsp_valid = writeLogic_resized_rsp_combStage_valid; - assign writeLogic_resized_rsp_combStage_ready = interconnect_write_aggregated_rsp_ready; - assign interconnect_write_aggregated_rsp_payload_last = writeLogic_resized_rsp_combStage_payload_last; - assign interconnect_write_aggregated_rsp_payload_fragment_source = writeLogic_resized_rsp_combStage_payload_fragment_source; - assign interconnect_write_aggregated_rsp_payload_fragment_opcode = writeLogic_resized_rsp_combStage_payload_fragment_opcode; - assign interconnect_write_aggregated_rsp_payload_fragment_context = writeLogic_resized_rsp_combStage_payload_fragment_context; - assign writeLogic_resized_cmd_ready = writeLogic_sourceRemover_io_input_cmd_ready; - assign writeLogic_resized_rsp_valid = writeLogic_sourceRemover_io_input_rsp_valid; - assign writeLogic_resized_rsp_payload_last = writeLogic_sourceRemover_io_input_rsp_payload_last; - assign writeLogic_resized_rsp_payload_fragment_source = writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; - assign writeLogic_resized_rsp_payload_fragment_opcode = writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; - assign writeLogic_resized_rsp_payload_fragment_context = writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; - assign writeLogic_adapter_aw_valid = writeLogic_bridge_io_output_aw_valid; - assign writeLogic_adapter_aw_payload_addr = writeLogic_bridge_io_output_aw_payload_addr; - assign _zz_writeLogic_adapter_aw_payload_region[3 : 0] = 4'b0000; - assign writeLogic_adapter_aw_payload_region = _zz_writeLogic_adapter_aw_payload_region; - assign writeLogic_adapter_aw_payload_len = writeLogic_bridge_io_output_aw_payload_len; - assign writeLogic_adapter_aw_payload_size = writeLogic_bridge_io_output_aw_payload_size; - assign writeLogic_adapter_aw_payload_burst = 2'b01; - assign writeLogic_adapter_aw_payload_lock = 1'b0; - assign writeLogic_adapter_aw_payload_cache = writeLogic_bridge_io_output_aw_payload_cache; - assign writeLogic_adapter_aw_payload_qos = 4'b0000; - assign writeLogic_adapter_aw_payload_prot = writeLogic_bridge_io_output_aw_payload_prot; - assign writeLogic_adapter_w_valid = writeLogic_bridge_io_output_w_valid; - assign writeLogic_adapter_w_payload_data = writeLogic_bridge_io_output_w_payload_data; - assign writeLogic_adapter_w_payload_strb = writeLogic_bridge_io_output_w_payload_strb; - assign writeLogic_adapter_w_payload_last = writeLogic_bridge_io_output_w_payload_last; - assign writeLogic_adapter_b_ready = writeLogic_bridge_io_output_b_ready; - assign writeLogic_adapter_aw_halfPipe_fire = (writeLogic_adapter_aw_halfPipe_valid && writeLogic_adapter_aw_halfPipe_ready); - assign writeLogic_adapter_aw_ready = (! writeLogic_adapter_aw_rValid); - assign writeLogic_adapter_aw_halfPipe_valid = writeLogic_adapter_aw_rValid; - assign writeLogic_adapter_aw_halfPipe_payload_addr = writeLogic_adapter_aw_rData_addr; - assign writeLogic_adapter_aw_halfPipe_payload_region = writeLogic_adapter_aw_rData_region; - assign writeLogic_adapter_aw_halfPipe_payload_len = writeLogic_adapter_aw_rData_len; - assign writeLogic_adapter_aw_halfPipe_payload_size = writeLogic_adapter_aw_rData_size; - assign writeLogic_adapter_aw_halfPipe_payload_burst = writeLogic_adapter_aw_rData_burst; - assign writeLogic_adapter_aw_halfPipe_payload_lock = writeLogic_adapter_aw_rData_lock; - assign writeLogic_adapter_aw_halfPipe_payload_cache = writeLogic_adapter_aw_rData_cache; - assign writeLogic_adapter_aw_halfPipe_payload_qos = writeLogic_adapter_aw_rData_qos; - assign writeLogic_adapter_aw_halfPipe_payload_prot = writeLogic_adapter_aw_rData_prot; - assign write_awvalid = writeLogic_adapter_aw_halfPipe_valid; - assign writeLogic_adapter_aw_halfPipe_ready = write_awready; - assign write_awaddr = writeLogic_adapter_aw_halfPipe_payload_addr; - assign write_awregion = writeLogic_adapter_aw_halfPipe_payload_region; - assign write_awlen = writeLogic_adapter_aw_halfPipe_payload_len; - assign write_awsize = writeLogic_adapter_aw_halfPipe_payload_size; - assign write_awburst = writeLogic_adapter_aw_halfPipe_payload_burst; - assign write_awlock = writeLogic_adapter_aw_halfPipe_payload_lock; - assign write_awcache = writeLogic_adapter_aw_halfPipe_payload_cache; - assign write_awqos = writeLogic_adapter_aw_halfPipe_payload_qos; - assign write_awprot = writeLogic_adapter_aw_halfPipe_payload_prot; - assign writeLogic_adapter_w_ready = writeLogic_adapter_w_rValidN; - assign writeLogic_adapter_w_s2mPipe_valid = (writeLogic_adapter_w_valid || (! writeLogic_adapter_w_rValidN)); - assign writeLogic_adapter_w_s2mPipe_payload_data = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_data : writeLogic_adapter_w_rData_data); - assign writeLogic_adapter_w_s2mPipe_payload_strb = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_strb : writeLogic_adapter_w_rData_strb); - assign writeLogic_adapter_w_s2mPipe_payload_last = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_last : writeLogic_adapter_w_rData_last); - always @(*) begin - writeLogic_adapter_w_s2mPipe_ready = writeLogic_adapter_w_s2mPipe_m2sPipe_ready; - if(when_Stream_l375_3) begin - writeLogic_adapter_w_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l375_3 = (! writeLogic_adapter_w_s2mPipe_m2sPipe_valid); - assign writeLogic_adapter_w_s2mPipe_m2sPipe_valid = writeLogic_adapter_w_s2mPipe_rValid; - assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data = writeLogic_adapter_w_s2mPipe_rData_data; - assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb = writeLogic_adapter_w_s2mPipe_rData_strb; - assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last = writeLogic_adapter_w_s2mPipe_rData_last; - assign write_wvalid = writeLogic_adapter_w_s2mPipe_m2sPipe_valid; - assign writeLogic_adapter_w_s2mPipe_m2sPipe_ready = write_wready; - assign write_wdata = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; - assign write_wstrb = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; - assign write_wlast = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; - assign write_b_halfPipe_fire = (write_b_halfPipe_valid && write_b_halfPipe_ready); - assign write_bready = (! write_b_rValid); - assign write_b_halfPipe_valid = write_b_rValid; - assign write_b_halfPipe_payload_resp = write_b_rData_resp; - assign writeLogic_adapter_b_valid = write_b_halfPipe_valid; - assign write_b_halfPipe_ready = writeLogic_adapter_b_ready; - assign writeLogic_adapter_b_payload_resp = write_b_halfPipe_payload_resp; - assign dat0_i_tready = inputsAdapter_0_upsizer_logic_io_input_ready; - assign io_pop_s2mPipe_valid = (inputsAdapter_0_crossclock_fifo_io_pop_valid || (! io_pop_rValidN)); - assign io_pop_s2mPipe_payload_data = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_data : io_pop_rData_data); - assign io_pop_s2mPipe_payload_mask = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_mask : io_pop_rData_mask); - assign io_pop_s2mPipe_payload_sink = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_sink : io_pop_rData_sink); - assign io_pop_s2mPipe_payload_last = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_last : io_pop_rData_last); - always @(*) begin - io_pop_s2mPipe_ready = io_pop_s2mPipe_m2sPipe_ready; - if(when_Stream_l375_4) begin - io_pop_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l375_4 = (! io_pop_s2mPipe_m2sPipe_valid); - assign io_pop_s2mPipe_m2sPipe_valid = io_pop_s2mPipe_rValid; - assign io_pop_s2mPipe_m2sPipe_payload_data = io_pop_s2mPipe_rData_data; - assign io_pop_s2mPipe_m2sPipe_payload_mask = io_pop_s2mPipe_rData_mask; - assign io_pop_s2mPipe_m2sPipe_payload_sink = io_pop_s2mPipe_rData_sink; - assign io_pop_s2mPipe_m2sPipe_payload_last = io_pop_s2mPipe_rData_last; - assign io_pop_s2mPipe_m2sPipe_ready = core_io_inputs_0_ready; - assign io_outputs_0_s2mPipe_valid = (core_io_outputs_0_valid || (! io_outputs_0_rValidN)); - assign io_outputs_0_s2mPipe_payload_data = (io_outputs_0_rValidN ? core_io_outputs_0_payload_data : io_outputs_0_rData_data); - assign io_outputs_0_s2mPipe_payload_mask = (io_outputs_0_rValidN ? core_io_outputs_0_payload_mask : io_outputs_0_rData_mask); - assign io_outputs_0_s2mPipe_payload_sink = (io_outputs_0_rValidN ? core_io_outputs_0_payload_sink : io_outputs_0_rData_sink); - assign io_outputs_0_s2mPipe_payload_last = (io_outputs_0_rValidN ? core_io_outputs_0_payload_last : io_outputs_0_rData_last); - always @(*) begin - io_outputs_0_s2mPipe_ready = outputsAdapter_0_ptr_ready; - if(when_Stream_l375_5) begin - io_outputs_0_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l375_5 = (! outputsAdapter_0_ptr_valid); - assign outputsAdapter_0_ptr_valid = io_outputs_0_s2mPipe_rValid; - assign outputsAdapter_0_ptr_payload_data = io_outputs_0_s2mPipe_rData_data; - assign outputsAdapter_0_ptr_payload_mask = io_outputs_0_s2mPipe_rData_mask; - assign outputsAdapter_0_ptr_payload_sink = io_outputs_0_s2mPipe_rData_sink; - assign outputsAdapter_0_ptr_payload_last = io_outputs_0_s2mPipe_rData_last; - assign outputsAdapter_0_ptr_ready = outputsAdapter_0_crossclock_fifo_io_push_ready; - assign dat1_o_tvalid = outputsAdapter_0_sparseDownsizer_logic_io_output_valid; - assign dat1_o_tdata = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; - assign dat1_o_tkeep = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; - assign dat1_o_tdest = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; - assign dat1_o_tlast = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; - assign interconnect_read_aggregated_cmd_valid = interconnect_read_aggregated_arbiter_io_output_cmd_valid; - assign interconnect_read_aggregated_rsp_ready = interconnect_read_aggregated_arbiter_io_output_rsp_ready; - assign interconnect_read_aggregated_cmd_payload_last = interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; - assign interconnect_read_aggregated_cmd_payload_fragment_source = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; - assign interconnect_read_aggregated_cmd_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; - assign interconnect_read_aggregated_cmd_payload_fragment_address = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; - assign interconnect_read_aggregated_cmd_payload_fragment_length = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; - assign interconnect_read_aggregated_cmd_payload_fragment_context = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; - assign interconnect_write_aggregated_cmd_valid = interconnect_write_aggregated_arbiter_io_output_cmd_valid; - assign interconnect_write_aggregated_rsp_ready = interconnect_write_aggregated_arbiter_io_output_rsp_ready; - assign interconnect_write_aggregated_cmd_payload_last = interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; - assign interconnect_write_aggregated_cmd_payload_fragment_source = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; - assign interconnect_write_aggregated_cmd_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; - assign interconnect_write_aggregated_cmd_payload_fragment_address = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; - assign interconnect_write_aggregated_cmd_payload_fragment_length = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; - assign interconnect_write_aggregated_cmd_payload_fragment_data = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; - assign interconnect_write_aggregated_cmd_payload_fragment_mask = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; - assign interconnect_write_aggregated_cmd_payload_fragment_context = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; - assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; - assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; - always @(posedge clk) begin - if(reset) begin - io_write_cmd_rValidN <= 1'b1; - io_write_cmd_s2mPipe_rValid <= 1'b0; - interconnect_read_aggregated_cmd_rValid <= 1'b0; - readLogic_adapter_ar_rValid <= 1'b0; - read_r_rValidN <= 1'b1; - read_r_s2mPipe_rValid <= 1'b0; - interconnect_write_aggregated_cmd_rValid <= 1'b0; - writeLogic_adapter_aw_rValid <= 1'b0; - writeLogic_adapter_w_rValidN <= 1'b1; - writeLogic_adapter_w_s2mPipe_rValid <= 1'b0; - write_b_rValid <= 1'b0; - io_pop_rValidN <= 1'b1; - io_pop_s2mPipe_rValid <= 1'b0; - io_outputs_0_rValidN <= 1'b1; - io_outputs_0_s2mPipe_rValid <= 1'b0; - end else begin - if(core_io_write_cmd_valid) begin - io_write_cmd_rValidN <= 1'b0; - end - if(io_write_cmd_s2mPipe_ready) begin - io_write_cmd_rValidN <= 1'b1; - end - if(io_write_cmd_s2mPipe_ready) begin - io_write_cmd_s2mPipe_rValid <= io_write_cmd_s2mPipe_valid; - end - if(interconnect_read_aggregated_cmd_valid) begin - interconnect_read_aggregated_cmd_rValid <= 1'b1; - end - if(interconnect_read_aggregated_cmd_halfPipe_fire) begin - interconnect_read_aggregated_cmd_rValid <= 1'b0; - end - if(readLogic_adapter_ar_valid) begin - readLogic_adapter_ar_rValid <= 1'b1; - end - if(readLogic_adapter_ar_halfPipe_fire) begin - readLogic_adapter_ar_rValid <= 1'b0; - end - if(read_rvalid) begin - read_r_rValidN <= 1'b0; - end - if(read_r_s2mPipe_ready) begin - read_r_rValidN <= 1'b1; - end - if(read_r_s2mPipe_ready) begin - read_r_s2mPipe_rValid <= read_r_s2mPipe_valid; - end - if(interconnect_write_aggregated_cmd_ready) begin - interconnect_write_aggregated_cmd_rValid <= interconnect_write_aggregated_cmd_valid; - end - if(writeLogic_adapter_aw_valid) begin - writeLogic_adapter_aw_rValid <= 1'b1; - end - if(writeLogic_adapter_aw_halfPipe_fire) begin - writeLogic_adapter_aw_rValid <= 1'b0; - end - if(writeLogic_adapter_w_valid) begin - writeLogic_adapter_w_rValidN <= 1'b0; - end - if(writeLogic_adapter_w_s2mPipe_ready) begin - writeLogic_adapter_w_rValidN <= 1'b1; - end - if(writeLogic_adapter_w_s2mPipe_ready) begin - writeLogic_adapter_w_s2mPipe_rValid <= writeLogic_adapter_w_s2mPipe_valid; - end - if(write_bvalid) begin - write_b_rValid <= 1'b1; - end - if(write_b_halfPipe_fire) begin - write_b_rValid <= 1'b0; - end - if(inputsAdapter_0_crossclock_fifo_io_pop_valid) begin - io_pop_rValidN <= 1'b0; - end - if(io_pop_s2mPipe_ready) begin - io_pop_rValidN <= 1'b1; - end - if(io_pop_s2mPipe_ready) begin - io_pop_s2mPipe_rValid <= io_pop_s2mPipe_valid; - end - if(core_io_outputs_0_valid) begin - io_outputs_0_rValidN <= 1'b0; - end - if(io_outputs_0_s2mPipe_ready) begin - io_outputs_0_rValidN <= 1'b1; - end - if(io_outputs_0_s2mPipe_ready) begin - io_outputs_0_s2mPipe_rValid <= io_outputs_0_s2mPipe_valid; - end - end - end - - always @(posedge clk) begin - if(io_write_cmd_rValidN) begin - io_write_cmd_rData_last <= core_io_write_cmd_payload_last; - io_write_cmd_rData_fragment_opcode <= core_io_write_cmd_payload_fragment_opcode; - io_write_cmd_rData_fragment_address <= core_io_write_cmd_payload_fragment_address; - io_write_cmd_rData_fragment_length <= core_io_write_cmd_payload_fragment_length; - io_write_cmd_rData_fragment_data <= core_io_write_cmd_payload_fragment_data; - io_write_cmd_rData_fragment_mask <= core_io_write_cmd_payload_fragment_mask; - io_write_cmd_rData_fragment_context <= core_io_write_cmd_payload_fragment_context; - end - if(io_write_cmd_s2mPipe_ready) begin - io_write_cmd_s2mPipe_rData_last <= io_write_cmd_s2mPipe_payload_last; - io_write_cmd_s2mPipe_rData_fragment_opcode <= io_write_cmd_s2mPipe_payload_fragment_opcode; - io_write_cmd_s2mPipe_rData_fragment_address <= io_write_cmd_s2mPipe_payload_fragment_address; - io_write_cmd_s2mPipe_rData_fragment_length <= io_write_cmd_s2mPipe_payload_fragment_length; - io_write_cmd_s2mPipe_rData_fragment_data <= io_write_cmd_s2mPipe_payload_fragment_data; - io_write_cmd_s2mPipe_rData_fragment_mask <= io_write_cmd_s2mPipe_payload_fragment_mask; - io_write_cmd_s2mPipe_rData_fragment_context <= io_write_cmd_s2mPipe_payload_fragment_context; - end - if(interconnect_read_aggregated_cmd_ready) begin - interconnect_read_aggregated_cmd_rData_last <= interconnect_read_aggregated_cmd_payload_last; - interconnect_read_aggregated_cmd_rData_fragment_source <= interconnect_read_aggregated_cmd_payload_fragment_source; - interconnect_read_aggregated_cmd_rData_fragment_opcode <= interconnect_read_aggregated_cmd_payload_fragment_opcode; - interconnect_read_aggregated_cmd_rData_fragment_address <= interconnect_read_aggregated_cmd_payload_fragment_address; - interconnect_read_aggregated_cmd_rData_fragment_length <= interconnect_read_aggregated_cmd_payload_fragment_length; - interconnect_read_aggregated_cmd_rData_fragment_context <= interconnect_read_aggregated_cmd_payload_fragment_context; - end - if(readLogic_adapter_ar_ready) begin - readLogic_adapter_ar_rData_addr <= readLogic_adapter_ar_payload_addr; - readLogic_adapter_ar_rData_region <= readLogic_adapter_ar_payload_region; - readLogic_adapter_ar_rData_len <= readLogic_adapter_ar_payload_len; - readLogic_adapter_ar_rData_size <= readLogic_adapter_ar_payload_size; - readLogic_adapter_ar_rData_burst <= readLogic_adapter_ar_payload_burst; - readLogic_adapter_ar_rData_lock <= readLogic_adapter_ar_payload_lock; - readLogic_adapter_ar_rData_cache <= readLogic_adapter_ar_payload_cache; - readLogic_adapter_ar_rData_qos <= readLogic_adapter_ar_payload_qos; - readLogic_adapter_ar_rData_prot <= readLogic_adapter_ar_payload_prot; - end - if(read_rready) begin - read_r_rData_data <= read_rdata; - read_r_rData_resp <= read_rresp; - read_r_rData_last <= read_rlast; - end - if(read_r_s2mPipe_ready) begin - read_r_s2mPipe_rData_data <= read_r_s2mPipe_payload_data; - read_r_s2mPipe_rData_resp <= read_r_s2mPipe_payload_resp; - read_r_s2mPipe_rData_last <= read_r_s2mPipe_payload_last; - end - if(interconnect_write_aggregated_cmd_ready) begin - interconnect_write_aggregated_cmd_rData_last <= interconnect_write_aggregated_cmd_payload_last; - interconnect_write_aggregated_cmd_rData_fragment_source <= interconnect_write_aggregated_cmd_payload_fragment_source; - interconnect_write_aggregated_cmd_rData_fragment_opcode <= interconnect_write_aggregated_cmd_payload_fragment_opcode; - interconnect_write_aggregated_cmd_rData_fragment_address <= interconnect_write_aggregated_cmd_payload_fragment_address; - interconnect_write_aggregated_cmd_rData_fragment_length <= interconnect_write_aggregated_cmd_payload_fragment_length; - interconnect_write_aggregated_cmd_rData_fragment_data <= interconnect_write_aggregated_cmd_payload_fragment_data; - interconnect_write_aggregated_cmd_rData_fragment_mask <= interconnect_write_aggregated_cmd_payload_fragment_mask; - interconnect_write_aggregated_cmd_rData_fragment_context <= interconnect_write_aggregated_cmd_payload_fragment_context; - end - if(writeLogic_adapter_aw_ready) begin - writeLogic_adapter_aw_rData_addr <= writeLogic_adapter_aw_payload_addr; - writeLogic_adapter_aw_rData_region <= writeLogic_adapter_aw_payload_region; - writeLogic_adapter_aw_rData_len <= writeLogic_adapter_aw_payload_len; - writeLogic_adapter_aw_rData_size <= writeLogic_adapter_aw_payload_size; - writeLogic_adapter_aw_rData_burst <= writeLogic_adapter_aw_payload_burst; - writeLogic_adapter_aw_rData_lock <= writeLogic_adapter_aw_payload_lock; - writeLogic_adapter_aw_rData_cache <= writeLogic_adapter_aw_payload_cache; - writeLogic_adapter_aw_rData_qos <= writeLogic_adapter_aw_payload_qos; - writeLogic_adapter_aw_rData_prot <= writeLogic_adapter_aw_payload_prot; - end - if(writeLogic_adapter_w_ready) begin - writeLogic_adapter_w_rData_data <= writeLogic_adapter_w_payload_data; - writeLogic_adapter_w_rData_strb <= writeLogic_adapter_w_payload_strb; - writeLogic_adapter_w_rData_last <= writeLogic_adapter_w_payload_last; - end - if(writeLogic_adapter_w_s2mPipe_ready) begin - writeLogic_adapter_w_s2mPipe_rData_data <= writeLogic_adapter_w_s2mPipe_payload_data; - writeLogic_adapter_w_s2mPipe_rData_strb <= writeLogic_adapter_w_s2mPipe_payload_strb; - writeLogic_adapter_w_s2mPipe_rData_last <= writeLogic_adapter_w_s2mPipe_payload_last; - end - if(write_bready) begin - write_b_rData_resp <= write_bresp; - end - if(io_pop_rValidN) begin - io_pop_rData_data <= inputsAdapter_0_crossclock_fifo_io_pop_payload_data; - io_pop_rData_mask <= inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; - io_pop_rData_sink <= inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; - io_pop_rData_last <= inputsAdapter_0_crossclock_fifo_io_pop_payload_last; - end - if(io_pop_s2mPipe_ready) begin - io_pop_s2mPipe_rData_data <= io_pop_s2mPipe_payload_data; - io_pop_s2mPipe_rData_mask <= io_pop_s2mPipe_payload_mask; - io_pop_s2mPipe_rData_sink <= io_pop_s2mPipe_payload_sink; - io_pop_s2mPipe_rData_last <= io_pop_s2mPipe_payload_last; - end - if(io_outputs_0_rValidN) begin - io_outputs_0_rData_data <= core_io_outputs_0_payload_data; - io_outputs_0_rData_mask <= core_io_outputs_0_payload_mask; - io_outputs_0_rData_sink <= core_io_outputs_0_payload_sink; - io_outputs_0_rData_last <= core_io_outputs_0_payload_last; - end - if(io_outputs_0_s2mPipe_ready) begin - io_outputs_0_s2mPipe_rData_data <= io_outputs_0_s2mPipe_payload_data; - io_outputs_0_s2mPipe_rData_mask <= io_outputs_0_s2mPipe_payload_mask; - io_outputs_0_s2mPipe_rData_sink <= io_outputs_0_s2mPipe_payload_sink; - io_outputs_0_s2mPipe_rData_last <= io_outputs_0_s2mPipe_payload_last; - end - end - - -endmodule - -module EfxDMA_BmbArbiter_1 ( - input wire io_inputs_0_cmd_valid, - output wire io_inputs_0_cmd_ready, - input wire io_inputs_0_cmd_payload_last, - input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, - input wire [31:0] io_inputs_0_cmd_payload_fragment_address, - input wire [1:0] io_inputs_0_cmd_payload_fragment_length, - input wire [127:0] io_inputs_0_cmd_payload_fragment_data, - input wire [15:0] io_inputs_0_cmd_payload_fragment_mask, - input wire [0:0] io_inputs_0_cmd_payload_fragment_context, - output wire io_inputs_0_rsp_valid, - input wire io_inputs_0_rsp_ready, - output wire io_inputs_0_rsp_payload_last, - output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, - output wire [0:0] io_inputs_0_rsp_payload_fragment_context, - input wire io_inputs_1_cmd_valid, - output wire io_inputs_1_cmd_ready, - input wire io_inputs_1_cmd_payload_last, - input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, - input wire [31:0] io_inputs_1_cmd_payload_fragment_address, - input wire [11:0] io_inputs_1_cmd_payload_fragment_length, - input wire [127:0] io_inputs_1_cmd_payload_fragment_data, - input wire [15:0] io_inputs_1_cmd_payload_fragment_mask, - input wire [12:0] io_inputs_1_cmd_payload_fragment_context, - output wire io_inputs_1_rsp_valid, - input wire io_inputs_1_rsp_ready, - output wire io_inputs_1_rsp_payload_last, - output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, - output wire [12:0] io_inputs_1_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_source, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [127:0] io_output_cmd_payload_fragment_data, - output wire [15:0] io_output_cmd_payload_fragment_mask, - output wire [12:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_source, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [12:0] io_output_rsp_payload_fragment_context, - input wire clk, - input wire reset -); - - wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; - wire [12:0] memory_arbiter_io_inputs_0_payload_fragment_context; - wire memory_arbiter_io_inputs_0_ready; - wire memory_arbiter_io_inputs_1_ready; - wire memory_arbiter_io_output_valid; - wire memory_arbiter_io_output_payload_last; - wire [0:0] memory_arbiter_io_output_payload_fragment_source; - wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; - wire [31:0] memory_arbiter_io_output_payload_fragment_address; - wire [11:0] memory_arbiter_io_output_payload_fragment_length; - wire [127:0] memory_arbiter_io_output_payload_fragment_data; - wire [15:0] memory_arbiter_io_output_payload_fragment_mask; - wire [12:0] memory_arbiter_io_output_payload_fragment_context; - wire [0:0] memory_arbiter_io_chosen; - wire [1:0] memory_arbiter_io_chosenOH; - wire [1:0] _zz_io_output_cmd_payload_fragment_source; - reg _zz_io_output_rsp_ready; - wire [0:0] memory_rspSel; - - assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; - EfxDMA_StreamArbiter_1 memory_arbiter ( - .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i - .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o - .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i - .io_inputs_0_payload_fragment_source (1'b0 ), //i - .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i - .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[127:0] ), //i - .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[15:0] ), //i - .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[12:0]), //i - .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i - .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o - .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i - .io_inputs_1_payload_fragment_source (1'b0 ), //i - .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i - .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i - .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[127:0] ), //i - .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[15:0] ), //i - .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[12:0] ), //i - .io_output_valid (memory_arbiter_io_output_valid ), //o - .io_output_ready (io_output_cmd_ready ), //i - .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o - .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o - .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o - .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o - .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o - .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[127:0] ), //o - .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[15:0] ), //o - .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[12:0] ), //o - .io_chosen (memory_arbiter_io_chosen ), //o - .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(memory_rspSel) - 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; - default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; - endcase - end - - assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; - assign memory_arbiter_io_inputs_0_payload_fragment_length = {10'd0, io_inputs_0_cmd_payload_fragment_length}; - assign memory_arbiter_io_inputs_0_payload_fragment_context = {12'd0, io_inputs_0_cmd_payload_fragment_context}; - assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; - assign io_output_cmd_valid = memory_arbiter_io_output_valid; - assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; - assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; - assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; - assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; - assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); - assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; - assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); - assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_output_rsp_ready = _zz_io_output_rsp_ready; - -endmodule - -module EfxDMA_BmbArbiter ( - input wire io_inputs_0_cmd_valid, - output wire io_inputs_0_cmd_ready, - input wire io_inputs_0_cmd_payload_last, - input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, - input wire [31:0] io_inputs_0_cmd_payload_fragment_address, - input wire [4:0] io_inputs_0_cmd_payload_fragment_length, - input wire [0:0] io_inputs_0_cmd_payload_fragment_context, - output wire io_inputs_0_rsp_valid, - input wire io_inputs_0_rsp_ready, - output wire io_inputs_0_rsp_payload_last, - output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, - output wire [127:0] io_inputs_0_rsp_payload_fragment_data, - output wire [0:0] io_inputs_0_rsp_payload_fragment_context, - input wire io_inputs_1_cmd_valid, - output wire io_inputs_1_cmd_ready, - input wire io_inputs_1_cmd_payload_last, - input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, - input wire [31:0] io_inputs_1_cmd_payload_fragment_address, - input wire [11:0] io_inputs_1_cmd_payload_fragment_length, - input wire [20:0] io_inputs_1_cmd_payload_fragment_context, - output wire io_inputs_1_rsp_valid, - input wire io_inputs_1_rsp_ready, - output wire io_inputs_1_rsp_payload_last, - output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, - output wire [127:0] io_inputs_1_rsp_payload_fragment_data, - output wire [20:0] io_inputs_1_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_source, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [20:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_source, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [127:0] io_output_rsp_payload_fragment_data, - input wire [20:0] io_output_rsp_payload_fragment_context, - input wire clk, - input wire reset -); - - wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; - wire [20:0] memory_arbiter_io_inputs_0_payload_fragment_context; - wire memory_arbiter_io_inputs_0_ready; - wire memory_arbiter_io_inputs_1_ready; - wire memory_arbiter_io_output_valid; - wire memory_arbiter_io_output_payload_last; - wire [0:0] memory_arbiter_io_output_payload_fragment_source; - wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; - wire [31:0] memory_arbiter_io_output_payload_fragment_address; - wire [11:0] memory_arbiter_io_output_payload_fragment_length; - wire [20:0] memory_arbiter_io_output_payload_fragment_context; - wire [0:0] memory_arbiter_io_chosen; - wire [1:0] memory_arbiter_io_chosenOH; - wire [1:0] _zz_io_output_cmd_payload_fragment_source; - reg _zz_io_output_rsp_ready; - wire [0:0] memory_rspSel; - - assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; - EfxDMA_StreamArbiter memory_arbiter ( - .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i - .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o - .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i - .io_inputs_0_payload_fragment_source (1'b0 ), //i - .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i - .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[20:0]), //i - .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i - .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o - .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i - .io_inputs_1_payload_fragment_source (1'b0 ), //i - .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i - .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i - .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[20:0] ), //i - .io_output_valid (memory_arbiter_io_output_valid ), //o - .io_output_ready (io_output_cmd_ready ), //i - .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o - .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o - .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o - .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o - .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o - .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[20:0] ), //o - .io_chosen (memory_arbiter_io_chosen ), //o - .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(memory_rspSel) - 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; - default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; - endcase - end - - assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; - assign memory_arbiter_io_inputs_0_payload_fragment_length = {7'd0, io_inputs_0_cmd_payload_fragment_length}; - assign memory_arbiter_io_inputs_0_payload_fragment_context = {20'd0, io_inputs_0_cmd_payload_fragment_context}; - assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; - assign io_output_cmd_valid = memory_arbiter_io_output_valid; - assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; - assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; - assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; - assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; - assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; - assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); - assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; - assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); - assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_output_rsp_ready = _zz_io_output_rsp_ready; - -endmodule - -module EfxDMA_BsbDownSizerSparse ( - input wire io_input_valid, - output wire io_input_ready, - input wire [63:0] io_input_payload_data, - input wire [7:0] io_input_payload_mask, - input wire [3:0] io_input_payload_sink, - input wire io_input_payload_last, - output wire io_output_valid, - input wire io_output_ready, - output wire [7:0] io_output_payload_data, - output wire [0:0] io_output_payload_mask, - output wire [3:0] io_output_payload_sink, - output wire io_output_payload_last, - input wire dat1_o_clk, - input wire dat1_o_reset -); - - reg [7:0] _zz_io_output_payload_data; - reg [0:0] _zz_io_output_payload_mask; - reg [2:0] counter; - wire end_1; - wire io_output_fire; - - always @(*) begin - case(counter) - 3'b000 : begin - _zz_io_output_payload_data = io_input_payload_data[7 : 0]; - _zz_io_output_payload_mask = io_input_payload_mask[0 : 0]; - end - 3'b001 : begin - _zz_io_output_payload_data = io_input_payload_data[15 : 8]; - _zz_io_output_payload_mask = io_input_payload_mask[1 : 1]; - end - 3'b010 : begin - _zz_io_output_payload_data = io_input_payload_data[23 : 16]; - _zz_io_output_payload_mask = io_input_payload_mask[2 : 2]; - end - 3'b011 : begin - _zz_io_output_payload_data = io_input_payload_data[31 : 24]; - _zz_io_output_payload_mask = io_input_payload_mask[3 : 3]; - end - 3'b100 : begin - _zz_io_output_payload_data = io_input_payload_data[39 : 32]; - _zz_io_output_payload_mask = io_input_payload_mask[4 : 4]; - end - 3'b101 : begin - _zz_io_output_payload_data = io_input_payload_data[47 : 40]; - _zz_io_output_payload_mask = io_input_payload_mask[5 : 5]; - end - 3'b110 : begin - _zz_io_output_payload_data = io_input_payload_data[55 : 48]; - _zz_io_output_payload_mask = io_input_payload_mask[6 : 6]; - end - default : begin - _zz_io_output_payload_data = io_input_payload_data[63 : 56]; - _zz_io_output_payload_mask = io_input_payload_mask[7 : 7]; - end - endcase - end - - assign end_1 = (counter == 3'b111); - assign io_output_fire = (io_output_valid && io_output_ready); - assign io_input_ready = (io_output_ready && end_1); - assign io_output_valid = io_input_valid; - assign io_output_payload_data = _zz_io_output_payload_data; - assign io_output_payload_mask = _zz_io_output_payload_mask; - assign io_output_payload_sink = io_input_payload_sink; - assign io_output_payload_last = (io_input_payload_last && end_1); - always @(posedge dat1_o_clk) begin - if(dat1_o_reset) begin - counter <= 3'b000; - end else begin - if(io_output_fire) begin - counter <= (counter + 3'b001); - end - end - end - - -endmodule - -module EfxDMA_StreamFifoCC_1 ( - input wire io_push_valid, - output wire io_push_ready, - input wire [63:0] io_push_payload_data, - input wire [7:0] io_push_payload_mask, - input wire [3:0] io_push_payload_sink, - input wire io_push_payload_last, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [63:0] io_pop_payload_data, - output wire [7:0] io_pop_payload_mask, - output wire [3:0] io_pop_payload_sink, - output wire io_pop_payload_last, - output wire [4:0] io_pushOccupancy, - output wire [4:0] io_popOccupancy, - input wire clk, - input wire reset, - input wire dat1_o_clk, - input wire dat1_o_reset -); - - reg [76:0] ram_spinal_port1; - wire [4:0] popToPushGray_buffercc_io_dataOut; - wire [4:0] pushToPopGray_buffercc_io_dataOut; - wire [4:0] _zz_pushCC_pushPtrGray; - wire [3:0] _zz_ram_port; - wire [76:0] _zz_ram_port_1; - wire [4:0] _zz_popCC_popPtrGray; - reg _zz_1; - wire [4:0] popToPushGray; - wire [4:0] pushToPopGray; - reg [4:0] pushCC_pushPtr; - wire [4:0] pushCC_pushPtrPlus; - wire io_push_fire; - reg [4:0] pushCC_pushPtrGray; - wire [4:0] pushCC_popPtrGray; - wire pushCC_full; - wire _zz_io_pushOccupancy; - wire _zz_io_pushOccupancy_1; - wire _zz_io_pushOccupancy_2; - wire _zz_io_pushOccupancy_3; - reg [4:0] popCC_popPtr; - (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; - wire [4:0] popCC_popPtrGray; - wire [4:0] popCC_pushPtrGray; - wire popCC_addressGen_valid; - reg popCC_addressGen_ready; - wire [3:0] popCC_addressGen_payload; - wire popCC_empty; - wire popCC_addressGen_fire; - wire popCC_readArbitation_valid; - wire popCC_readArbitation_ready; - wire [3:0] popCC_readArbitation_payload; - reg popCC_addressGen_rValid; - reg [3:0] popCC_addressGen_rData; - wire when_Stream_l375; - wire popCC_readPort_cmd_valid; - wire [3:0] popCC_readPort_cmd_payload; - wire [63:0] popCC_readPort_rsp_data; - wire [7:0] popCC_readPort_rsp_mask; - wire [3:0] popCC_readPort_rsp_sink; - wire popCC_readPort_rsp_last; - wire [76:0] _zz_popCC_readPort_rsp_data; - wire popCC_readArbitation_translated_valid; - wire popCC_readArbitation_translated_ready; - wire [63:0] popCC_readArbitation_translated_payload_data; - wire [7:0] popCC_readArbitation_translated_payload_mask; - wire [3:0] popCC_readArbitation_translated_payload_sink; - wire popCC_readArbitation_translated_payload_last; - wire popCC_readArbitation_fire; - reg [4:0] popCC_ptrToPush; - reg [4:0] popCC_ptrToOccupancy; - wire _zz_io_popOccupancy; - wire _zz_io_popOccupancy_1; - wire _zz_io_popOccupancy_2; - wire _zz_io_popOccupancy_3; - reg [76:0] ram [0:15]; - - assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); - assign _zz_ram_port = pushCC_pushPtr[3:0]; - assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); - assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; - always @(posedge clk) begin - if(_zz_1) begin - ram[_zz_ram_port] <= _zz_ram_port_1; - end - end - - always @(posedge dat1_o_clk) begin - if(popCC_readPort_cmd_valid) begin - ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; - end - end - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3 popToPushGray_buffercc ( - .io_dataIn (popToPushGray[4:0] ), //i - .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_5 pushToPopGray_buffercc ( - .io_dataIn (pushToPopGray[4:0] ), //i - .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o - .dat1_o_clk (dat1_o_clk ), //i - .dat1_o_reset (dat1_o_reset ) //i - ); - always @(*) begin - _zz_1 = 1'b0; - if(io_push_fire) begin - _zz_1 = 1'b1; - end - end - - assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); - assign io_push_fire = (io_push_valid && io_push_ready); - assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; - assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); - assign io_push_ready = (! pushCC_full); - assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); - assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); - assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); - assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; - assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); - assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); - assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); - assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; - assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); - assign popCC_addressGen_valid = (! popCC_empty); - assign popCC_addressGen_payload = popCC_popPtr[3:0]; - assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); - always @(*) begin - popCC_addressGen_ready = popCC_readArbitation_ready; - if(when_Stream_l375) begin - popCC_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCC_readArbitation_valid); - assign popCC_readArbitation_valid = popCC_addressGen_rValid; - assign popCC_readArbitation_payload = popCC_addressGen_rData; - assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; - assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; - assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; - assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; - assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; - assign popCC_readPort_cmd_valid = popCC_addressGen_fire; - assign popCC_readPort_cmd_payload = popCC_addressGen_payload; - assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; - assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; - assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; - assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; - assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; - assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; - assign io_pop_valid = popCC_readArbitation_translated_valid; - assign popCC_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; - assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; - assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; - assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; - assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); - assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); - assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); - assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); - assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; - assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); - assign pushToPopGray = pushCC_pushPtrGray; - assign popToPushGray = popCC_ptrToPush; - always @(posedge clk) begin - if(reset) begin - pushCC_pushPtr <= 5'h0; - pushCC_pushPtrGray <= 5'h0; - end else begin - if(io_push_fire) begin - pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); - end - if(io_push_fire) begin - pushCC_pushPtr <= pushCC_pushPtrPlus; - end - end - end - - always @(posedge dat1_o_clk) begin - if(dat1_o_reset) begin - popCC_popPtr <= 5'h0; - popCC_addressGen_rValid <= 1'b0; - popCC_ptrToPush <= 5'h0; - popCC_ptrToOccupancy <= 5'h0; - end else begin - if(popCC_addressGen_fire) begin - popCC_popPtr <= popCC_popPtrPlus; - end - if(popCC_addressGen_ready) begin - popCC_addressGen_rValid <= popCC_addressGen_valid; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToPush <= popCC_popPtrGray; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToOccupancy <= popCC_popPtr; - end - end - end - - always @(posedge dat1_o_clk) begin - if(popCC_addressGen_ready) begin - popCC_addressGen_rData <= popCC_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_StreamFifoCC ( - input wire io_push_valid, - output wire io_push_ready, - input wire [63:0] io_push_payload_data, - input wire [7:0] io_push_payload_mask, - input wire [3:0] io_push_payload_sink, - input wire io_push_payload_last, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [63:0] io_pop_payload_data, - output wire [7:0] io_pop_payload_mask, - output wire [3:0] io_pop_payload_sink, - output wire io_pop_payload_last, - output wire [4:0] io_pushOccupancy, - output wire [4:0] io_popOccupancy, - input wire dat0_i_clk, - input wire dat0_i_reset, - input wire clk, - input wire reset -); - - reg [76:0] ram_spinal_port1; - wire [4:0] popToPushGray_buffercc_io_dataOut; - wire [4:0] pushToPopGray_buffercc_io_dataOut; - wire [4:0] _zz_pushCC_pushPtrGray; - wire [3:0] _zz_ram_port; - wire [76:0] _zz_ram_port_1; - wire [4:0] _zz_popCC_popPtrGray; - reg _zz_1; - wire [4:0] popToPushGray; - wire [4:0] pushToPopGray; - reg [4:0] pushCC_pushPtr; - wire [4:0] pushCC_pushPtrPlus; - wire io_push_fire; - reg [4:0] pushCC_pushPtrGray; - wire [4:0] pushCC_popPtrGray; - wire pushCC_full; - wire _zz_io_pushOccupancy; - wire _zz_io_pushOccupancy_1; - wire _zz_io_pushOccupancy_2; - wire _zz_io_pushOccupancy_3; - reg [4:0] popCC_popPtr; - (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; - wire [4:0] popCC_popPtrGray; - wire [4:0] popCC_pushPtrGray; - wire popCC_addressGen_valid; - reg popCC_addressGen_ready; - wire [3:0] popCC_addressGen_payload; - wire popCC_empty; - wire popCC_addressGen_fire; - wire popCC_readArbitation_valid; - wire popCC_readArbitation_ready; - wire [3:0] popCC_readArbitation_payload; - reg popCC_addressGen_rValid; - reg [3:0] popCC_addressGen_rData; - wire when_Stream_l375; - wire popCC_readPort_cmd_valid; - wire [3:0] popCC_readPort_cmd_payload; - wire [63:0] popCC_readPort_rsp_data; - wire [7:0] popCC_readPort_rsp_mask; - wire [3:0] popCC_readPort_rsp_sink; - wire popCC_readPort_rsp_last; - wire [76:0] _zz_popCC_readPort_rsp_data; - wire popCC_readArbitation_translated_valid; - wire popCC_readArbitation_translated_ready; - wire [63:0] popCC_readArbitation_translated_payload_data; - wire [7:0] popCC_readArbitation_translated_payload_mask; - wire [3:0] popCC_readArbitation_translated_payload_sink; - wire popCC_readArbitation_translated_payload_last; - wire popCC_readArbitation_fire; - reg [4:0] popCC_ptrToPush; - reg [4:0] popCC_ptrToOccupancy; - wire _zz_io_popOccupancy; - wire _zz_io_popOccupancy_1; - wire _zz_io_popOccupancy_2; - wire _zz_io_popOccupancy_3; - reg [76:0] ram [0:15]; - - assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); - assign _zz_ram_port = pushCC_pushPtr[3:0]; - assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); - assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; - always @(posedge dat0_i_clk) begin - if(_zz_1) begin - ram[_zz_ram_port] <= _zz_ram_port_1; - end - end - - always @(posedge clk) begin - if(popCC_readPort_cmd_valid) begin - ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; - end - end - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_2 popToPushGray_buffercc ( - .io_dataIn (popToPushGray[4:0] ), //i - .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o - .dat0_i_clk (dat0_i_clk ), //i - .dat0_i_reset (dat0_i_reset ) //i - ); - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3 pushToPopGray_buffercc ( - .io_dataIn (pushToPopGray[4:0] ), //i - .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - _zz_1 = 1'b0; - if(io_push_fire) begin - _zz_1 = 1'b1; - end - end - - assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); - assign io_push_fire = (io_push_valid && io_push_ready); - assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; - assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); - assign io_push_ready = (! pushCC_full); - assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); - assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); - assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); - assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; - assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); - assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); - assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); - assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; - assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); - assign popCC_addressGen_valid = (! popCC_empty); - assign popCC_addressGen_payload = popCC_popPtr[3:0]; - assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); - always @(*) begin - popCC_addressGen_ready = popCC_readArbitation_ready; - if(when_Stream_l375) begin - popCC_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCC_readArbitation_valid); - assign popCC_readArbitation_valid = popCC_addressGen_rValid; - assign popCC_readArbitation_payload = popCC_addressGen_rData; - assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; - assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; - assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; - assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; - assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; - assign popCC_readPort_cmd_valid = popCC_addressGen_fire; - assign popCC_readPort_cmd_payload = popCC_addressGen_payload; - assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; - assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; - assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; - assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; - assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; - assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; - assign io_pop_valid = popCC_readArbitation_translated_valid; - assign popCC_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; - assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; - assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; - assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; - assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); - assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); - assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); - assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); - assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; - assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); - assign pushToPopGray = pushCC_pushPtrGray; - assign popToPushGray = popCC_ptrToPush; - always @(posedge dat0_i_clk) begin - if(dat0_i_reset) begin - pushCC_pushPtr <= 5'h0; - pushCC_pushPtrGray <= 5'h0; - end else begin - if(io_push_fire) begin - pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); - end - if(io_push_fire) begin - pushCC_pushPtr <= pushCC_pushPtrPlus; - end - end - end - - always @(posedge clk) begin - if(reset) begin - popCC_popPtr <= 5'h0; - popCC_addressGen_rValid <= 1'b0; - popCC_ptrToPush <= 5'h0; - popCC_ptrToOccupancy <= 5'h0; - end else begin - if(popCC_addressGen_fire) begin - popCC_popPtr <= popCC_popPtrPlus; - end - if(popCC_addressGen_ready) begin - popCC_addressGen_rValid <= popCC_addressGen_valid; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToPush <= popCC_popPtrGray; - end - if(popCC_readArbitation_fire) begin - popCC_ptrToOccupancy <= popCC_popPtr; - end - end - end - - always @(posedge clk) begin - if(popCC_addressGen_ready) begin - popCC_addressGen_rData <= popCC_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_BsbUpSizerDense ( - input wire io_input_valid, - output wire io_input_ready, - input wire [7:0] io_input_payload_data, - input wire [0:0] io_input_payload_mask, - input wire [3:0] io_input_payload_sink, - input wire io_input_payload_last, - output wire io_output_valid, - input wire io_output_ready, - output wire [63:0] io_output_payload_data, - output wire [7:0] io_output_payload_mask, - output wire [3:0] io_output_payload_sink, - output wire io_output_payload_last, - input wire dat0_i_clk, - input wire dat0_i_reset -); - - reg valid; - reg [2:0] counter; - reg [63:0] buffer_data; - reg [7:0] buffer_mask; - reg [3:0] buffer_sink; - reg buffer_last; - wire full; - wire canAggregate; - wire onOutput; - wire [2:0] counterSample; - wire io_output_fire; - wire io_input_fire; - wire [7:0] _zz_1; - wire [7:0] _zz_2; - - assign full = ((counter == 3'b000) || buffer_last); - assign canAggregate = ((((valid && (! buffer_last)) && (! full)) && 1'b1) && (buffer_sink == io_input_payload_sink)); - assign counterSample = (canAggregate ? counter : 3'b000); - assign io_output_fire = (io_output_valid && io_output_ready); - assign io_input_fire = (io_input_valid && io_input_ready); - assign _zz_1 = ({7'd0,1'b1} <<< counterSample); - assign _zz_2 = ({7'd0,1'b1} <<< counterSample); - assign io_output_valid = (valid && ((valid && full) || (io_input_valid && (! canAggregate)))); - assign io_output_payload_data = buffer_data; - assign io_output_payload_mask = buffer_mask; - assign io_output_payload_sink = buffer_sink; - assign io_output_payload_last = buffer_last; - assign io_input_ready = (((! valid) || canAggregate) || io_output_ready); - always @(posedge dat0_i_clk) begin - if(dat0_i_reset) begin - valid <= 1'b0; - counter <= 3'b000; - buffer_last <= 1'b0; - buffer_mask <= 8'h0; - end else begin - if(io_output_fire) begin - valid <= 1'b0; - buffer_mask <= 8'h0; - end - if(io_input_fire) begin - valid <= 1'b1; - if(_zz_2[0]) begin - buffer_mask[0 : 0] <= io_input_payload_mask; - end - if(_zz_2[1]) begin - buffer_mask[1 : 1] <= io_input_payload_mask; - end - if(_zz_2[2]) begin - buffer_mask[2 : 2] <= io_input_payload_mask; - end - if(_zz_2[3]) begin - buffer_mask[3 : 3] <= io_input_payload_mask; - end - if(_zz_2[4]) begin - buffer_mask[4 : 4] <= io_input_payload_mask; - end - if(_zz_2[5]) begin - buffer_mask[5 : 5] <= io_input_payload_mask; - end - if(_zz_2[6]) begin - buffer_mask[6 : 6] <= io_input_payload_mask; - end - if(_zz_2[7]) begin - buffer_mask[7 : 7] <= io_input_payload_mask; - end - buffer_last <= io_input_payload_last; - counter <= (counterSample + 3'b001); - end - end - end - - always @(posedge dat0_i_clk) begin - if(io_input_fire) begin - buffer_sink <= io_input_payload_sink; - if(_zz_1[0]) begin - buffer_data[7 : 0] <= io_input_payload_data; - end - if(_zz_1[1]) begin - buffer_data[15 : 8] <= io_input_payload_data; - end - if(_zz_1[2]) begin - buffer_data[23 : 16] <= io_input_payload_data; - end - if(_zz_1[3]) begin - buffer_data[31 : 24] <= io_input_payload_data; - end - if(_zz_1[4]) begin - buffer_data[39 : 32] <= io_input_payload_data; - end - if(_zz_1[5]) begin - buffer_data[47 : 40] <= io_input_payload_data; - end - if(_zz_1[6]) begin - buffer_data[55 : 48] <= io_input_payload_data; - end - if(_zz_1[7]) begin - buffer_data[63 : 56] <= io_input_payload_data; - end - end - end - - -endmodule - -module EfxDMA_BmbToAxi4WriteOnlyBridge ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [127:0] io_input_cmd_payload_fragment_data, - input wire [15:0] io_input_cmd_payload_fragment_mask, - input wire [13:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [13:0] io_input_rsp_payload_fragment_context, - output wire io_output_aw_valid, - input wire io_output_aw_ready, - output wire [31:0] io_output_aw_payload_addr, - output wire [7:0] io_output_aw_payload_len, - output wire [2:0] io_output_aw_payload_size, - output wire [3:0] io_output_aw_payload_cache, - output wire [2:0] io_output_aw_payload_prot, - output wire io_output_w_valid, - input wire io_output_w_ready, - output wire [127:0] io_output_w_payload_data, - output wire [15:0] io_output_w_payload_strb, - output wire io_output_w_payload_last, - input wire io_output_b_valid, - output wire io_output_b_ready, - input wire [1:0] io_output_b_payload_resp, - input wire clk, - input wire reset -); - - reg contextRemover_io_output_cmd_ready; - reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; - wire contextRemover_io_input_cmd_ready; - wire contextRemover_io_input_rsp_valid; - wire contextRemover_io_input_rsp_payload_last; - wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; - wire [13:0] contextRemover_io_input_rsp_payload_fragment_context; - wire contextRemover_io_output_cmd_valid; - wire contextRemover_io_output_cmd_payload_last; - wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; - wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; - wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; - wire [127:0] contextRemover_io_output_cmd_payload_fragment_data; - wire [15:0] contextRemover_io_output_cmd_payload_fragment_mask; - wire contextRemover_io_output_rsp_ready; - wire [8:0] _zz_io_output_aw_payload_len; - wire [12:0] _zz_io_output_aw_payload_len_1; - wire [12:0] _zz_io_output_aw_payload_len_2; - wire [3:0] _zz_io_output_aw_payload_len_3; - wire cmdFork_valid; - reg cmdFork_ready; - wire cmdFork_payload_last; - wire [0:0] cmdFork_payload_fragment_opcode; - wire [31:0] cmdFork_payload_fragment_address; - wire [11:0] cmdFork_payload_fragment_length; - wire [127:0] cmdFork_payload_fragment_data; - wire [15:0] cmdFork_payload_fragment_mask; - wire dataFork_valid; - wire dataFork_ready; - wire dataFork_payload_last; - wire [0:0] dataFork_payload_fragment_opcode; - wire [31:0] dataFork_payload_fragment_address; - wire [11:0] dataFork_payload_fragment_length; - wire [127:0] dataFork_payload_fragment_data; - wire [15:0] dataFork_payload_fragment_mask; - reg contextRemover_io_output_cmd_fork2_logic_linkEnable_0; - reg contextRemover_io_output_cmd_fork2_logic_linkEnable_1; - wire when_Stream_l1063; - wire when_Stream_l1063_1; - wire cmdFork_fire; - wire dataFork_fire; - wire contextRemover_io_output_cmd_fire; - reg contextRemover_io_output_cmd_payload_first; - wire when_Stream_l445; - reg cmdStage_valid; - wire cmdStage_ready; - wire cmdStage_payload_last; - wire [0:0] cmdStage_payload_fragment_opcode; - wire [31:0] cmdStage_payload_fragment_address; - wire [11:0] cmdStage_payload_fragment_length; - wire [127:0] cmdStage_payload_fragment_data; - wire [15:0] cmdStage_payload_fragment_mask; - wire when_BmbToAxi4Bridge_l297; - - assign _zz_io_output_aw_payload_len = _zz_io_output_aw_payload_len_1[12 : 4]; - assign _zz_io_output_aw_payload_len_1 = ({1'b0,cmdStage_payload_fragment_length} + _zz_io_output_aw_payload_len_2); - assign _zz_io_output_aw_payload_len_3 = cmdStage_payload_fragment_address[3 : 0]; - assign _zz_io_output_aw_payload_len_2 = {9'd0, _zz_io_output_aw_payload_len_3}; - EfxDMA_BmbContextRemover_1 contextRemover ( - .io_input_cmd_valid (io_input_cmd_valid ), //i - .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_data (io_input_cmd_payload_fragment_data[127:0] ), //i - .io_input_cmd_payload_fragment_mask (io_input_cmd_payload_fragment_mask[15:0] ), //i - .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[13:0] ), //i - .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_input_rsp_ready ), //i - .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[13:0] ), //o - .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o - .io_output_cmd_ready (contextRemover_io_output_cmd_ready ), //i - .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o - .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_cmd_payload_fragment_data (contextRemover_io_output_cmd_payload_fragment_data[127:0] ), //o - .io_output_cmd_payload_fragment_mask (contextRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o - .io_output_rsp_valid (io_output_b_valid ), //i - .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (1'b1 ), //i - .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; - assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; - assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; - always @(*) begin - contextRemover_io_output_cmd_ready = 1'b1; - if(when_Stream_l1063) begin - contextRemover_io_output_cmd_ready = 1'b0; - end - if(when_Stream_l1063_1) begin - contextRemover_io_output_cmd_ready = 1'b0; - end - end - - assign when_Stream_l1063 = ((! cmdFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); - assign when_Stream_l1063_1 = ((! dataFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); - assign cmdFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); - assign cmdFork_payload_last = contextRemover_io_output_cmd_payload_last; - assign cmdFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; - assign cmdFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; - assign cmdFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; - assign cmdFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; - assign cmdFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; - assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); - assign dataFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); - assign dataFork_payload_last = contextRemover_io_output_cmd_payload_last; - assign dataFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; - assign dataFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; - assign dataFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; - assign dataFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; - assign dataFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; - assign dataFork_fire = (dataFork_valid && dataFork_ready); - assign contextRemover_io_output_cmd_fire = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_ready); - assign when_Stream_l445 = (! contextRemover_io_output_cmd_payload_first); - always @(*) begin - cmdStage_valid = cmdFork_valid; - if(when_Stream_l445) begin - cmdStage_valid = 1'b0; - end - end - - always @(*) begin - cmdFork_ready = cmdStage_ready; - if(when_Stream_l445) begin - cmdFork_ready = 1'b1; - end - end - - assign cmdStage_payload_last = cmdFork_payload_last; - assign cmdStage_payload_fragment_opcode = cmdFork_payload_fragment_opcode; - assign cmdStage_payload_fragment_address = cmdFork_payload_fragment_address; - assign cmdStage_payload_fragment_length = cmdFork_payload_fragment_length; - assign cmdStage_payload_fragment_data = cmdFork_payload_fragment_data; - assign cmdStage_payload_fragment_mask = cmdFork_payload_fragment_mask; - assign io_output_aw_valid = cmdStage_valid; - assign cmdStage_ready = io_output_aw_ready; - assign io_output_aw_payload_addr = cmdStage_payload_fragment_address; - assign io_output_aw_payload_len = _zz_io_output_aw_payload_len[7:0]; - assign io_output_aw_payload_size = 3'b100; - assign io_output_aw_payload_prot = 3'b010; - assign io_output_aw_payload_cache = 4'b1111; - assign io_output_w_valid = dataFork_valid; - assign dataFork_ready = io_output_w_ready; - assign io_output_w_payload_data = dataFork_payload_fragment_data; - assign io_output_w_payload_strb = dataFork_payload_fragment_mask; - assign io_output_w_payload_last = dataFork_payload_last; - assign io_output_b_ready = contextRemover_io_output_rsp_ready; - assign when_BmbToAxi4Bridge_l297 = (io_output_b_payload_resp == 2'b00); - always @(*) begin - if(when_BmbToAxi4Bridge_l297) begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; - end else begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; - end - end - - always @(posedge clk) begin - if(reset) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; - contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; - contextRemover_io_output_cmd_payload_first <= 1'b1; - end else begin - if(cmdFork_fire) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b0; - end - if(dataFork_fire) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b0; - end - if(contextRemover_io_output_cmd_ready) begin - contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; - contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; - end - if(contextRemover_io_output_cmd_fire) begin - contextRemover_io_output_cmd_payload_first <= contextRemover_io_output_cmd_payload_last; - end - end - end - - -endmodule - -module EfxDMA_BmbSourceRemover_1 ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [127:0] io_input_cmd_payload_fragment_data, - input wire [15:0] io_input_cmd_payload_fragment_mask, - input wire [12:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_source, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [12:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [127:0] io_output_cmd_payload_fragment_data, - output wire [15:0] io_output_cmd_payload_fragment_mask, - output wire [13:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [13:0] io_output_rsp_payload_fragment_context -); - - wire [0:0] cmdContext_source; - wire [12:0] cmdContext_context; - wire [0:0] rspContext_source; - wire [12:0] rspContext_context; - wire [13:0] _zz_rspContext_source; - - assign cmdContext_source = io_input_cmd_payload_fragment_source; - assign cmdContext_context = io_input_cmd_payload_fragment_context; - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; - assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; - assign rspContext_source = _zz_rspContext_source[0 : 0]; - assign rspContext_context = _zz_rspContext_source[13 : 1]; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_context = rspContext_context; - -endmodule - -module EfxDMA_BmbToAxi4ReadOnlyBridge ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [21:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [127:0] io_input_rsp_payload_fragment_data, - output wire [21:0] io_input_rsp_payload_fragment_context, - output wire io_output_ar_valid, - input wire io_output_ar_ready, - output wire [31:0] io_output_ar_payload_addr, - output wire [7:0] io_output_ar_payload_len, - output wire [2:0] io_output_ar_payload_size, - output wire [3:0] io_output_ar_payload_cache, - output wire [2:0] io_output_ar_payload_prot, - input wire io_output_r_valid, - output wire io_output_r_ready, - input wire [127:0] io_output_r_payload_data, - input wire [1:0] io_output_r_payload_resp, - input wire io_output_r_payload_last, - input wire clk, - input wire reset -); - - reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; - wire contextRemover_io_input_cmd_ready; - wire contextRemover_io_input_rsp_valid; - wire contextRemover_io_input_rsp_payload_last; - wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; - wire [127:0] contextRemover_io_input_rsp_payload_fragment_data; - wire [21:0] contextRemover_io_input_rsp_payload_fragment_context; - wire contextRemover_io_output_cmd_valid; - wire contextRemover_io_output_cmd_payload_last; - wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; - wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; - wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; - wire contextRemover_io_output_rsp_ready; - wire [8:0] _zz_io_output_ar_payload_len; - wire [12:0] _zz_io_output_ar_payload_len_1; - wire [12:0] _zz_io_output_ar_payload_len_2; - wire [3:0] _zz_io_output_ar_payload_len_3; - wire when_BmbToAxi4Bridge_l243; - - assign _zz_io_output_ar_payload_len = _zz_io_output_ar_payload_len_1[12 : 4]; - assign _zz_io_output_ar_payload_len_1 = ({1'b0,contextRemover_io_output_cmd_payload_fragment_length} + _zz_io_output_ar_payload_len_2); - assign _zz_io_output_ar_payload_len_3 = contextRemover_io_output_cmd_payload_fragment_address[3 : 0]; - assign _zz_io_output_ar_payload_len_2 = {9'd0, _zz_io_output_ar_payload_len_3}; - EfxDMA_BmbContextRemover contextRemover ( - .io_input_cmd_valid (io_input_cmd_valid ), //i - .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i - .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[21:0] ), //i - .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_input_rsp_ready ), //i - .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (contextRemover_io_input_rsp_payload_fragment_data[127:0] ), //o - .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[21:0] ), //o - .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o - .io_output_cmd_ready (io_output_ar_ready ), //i - .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o - .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o - .io_output_rsp_valid (io_output_r_valid ), //i - .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (io_output_r_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (io_output_r_payload_data[127:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; - assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; - assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = contextRemover_io_input_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; - assign io_output_ar_valid = contextRemover_io_output_cmd_valid; - assign io_output_ar_payload_addr = contextRemover_io_output_cmd_payload_fragment_address; - assign io_output_ar_payload_len = _zz_io_output_ar_payload_len[7:0]; - assign io_output_ar_payload_size = 3'b100; - assign io_output_ar_payload_prot = 3'b010; - assign io_output_ar_payload_cache = 4'b1111; - assign io_output_r_ready = contextRemover_io_output_rsp_ready; - assign when_BmbToAxi4Bridge_l243 = (io_output_r_payload_resp == 2'b00); - always @(*) begin - if(when_BmbToAxi4Bridge_l243) begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; - end else begin - contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; - end - end - - -endmodule - -module EfxDMA_BmbSourceRemover ( - input wire io_input_cmd_valid, - output wire io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_source, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [20:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_source, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [127:0] io_input_rsp_payload_fragment_data, - output wire [20:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [21:0] io_output_cmd_payload_fragment_context, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [127:0] io_output_rsp_payload_fragment_data, - input wire [21:0] io_output_rsp_payload_fragment_context -); - - wire [0:0] cmdContext_source; - wire [20:0] cmdContext_context; - wire [0:0] rspContext_source; - wire [20:0] rspContext_context; - wire [21:0] _zz_rspContext_source; - - assign cmdContext_source = io_input_cmd_payload_fragment_source; - assign cmdContext_context = io_input_cmd_payload_fragment_context; - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; - assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; - assign rspContext_source = _zz_rspContext_source[0 : 0]; - assign rspContext_context = _zz_rspContext_source[21 : 1]; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_context = rspContext_context; - -endmodule - -module EfxDMA_BufferCC_6 ( - input wire [1:0] io_dataIn, - output wire [1:0] io_dataOut, - input wire ctrl_clk, - input wire ctrl_reset -); - - (* async_reg = "true" *) reg [1:0] buffers_0; - (* async_reg = "true" *) reg [1:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge ctrl_clk) begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - - -endmodule - -module EfxDMA_Apb3CC ( - input wire [13:0] io_input_PADDR, - input wire [0:0] io_input_PSEL, - input wire io_input_PENABLE, - output wire io_input_PREADY, - input wire io_input_PWRITE, - input wire [31:0] io_input_PWDATA, - output wire [31:0] io_input_PRDATA, - output wire io_input_PSLVERROR, - output wire [13:0] io_output_PADDR, - output reg [0:0] io_output_PSEL, - output reg io_output_PENABLE, - input wire io_output_PREADY, - output wire io_output_PWRITE, - output wire [31:0] io_output_PWDATA, - input wire [31:0] io_output_PRDATA, - input wire io_output_PSLVERROR, - input wire ctrl_clk, - input wire ctrl_reset, - input wire clk, - input wire reset -); - - wire flowCCUnsafeByToggle_io_output_valid; - wire [13:0] flowCCUnsafeByToggle_io_output_payload_PADDR; - wire flowCCUnsafeByToggle_io_output_payload_PWRITE; - wire [31:0] flowCCUnsafeByToggle_io_output_payload_PWDATA; - wire flowCCUnsafeByToggle_1_io_output_valid; - wire [31:0] flowCCUnsafeByToggle_1_io_output_payload_PRDATA; - wire flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; - wire inputLogic_inputCmd_valid; - wire [13:0] inputLogic_inputCmd_payload_PADDR; - wire inputLogic_inputCmd_payload_PWRITE; - wire [31:0] inputLogic_inputCmd_payload_PWDATA; - wire inputLogic_inputRsp_valid; - wire [31:0] inputLogic_inputRsp_payload_PRDATA; - wire inputLogic_inputRsp_payload_PSLVERROR; - reg inputLogic_state; - wire flowCCUnsafeByToggle_io_output_toStream_valid; - reg flowCCUnsafeByToggle_io_output_toStream_ready; - wire [13:0] flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; - wire flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; - wire [31:0] flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; - wire outputLogic_outputCmd_valid; - reg outputLogic_outputCmd_ready; - wire [13:0] outputLogic_outputCmd_payload_PADDR; - wire outputLogic_outputCmd_payload_PWRITE; - wire [31:0] outputLogic_outputCmd_payload_PWDATA; - reg flowCCUnsafeByToggle_io_output_toStream_rValid; - wire flowCCUnsafeByToggle_io_output_toStream_fire; - (* async_reg = "true" *) reg [13:0] flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; - (* async_reg = "true" *) reg flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; - (* async_reg = "true" *) reg [31:0] flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; - wire when_Stream_l375; - reg outputLogic_state; - wire when_Apb3CCToggle_l81; - wire outputLogic_outputRsp_valid; - wire [31:0] outputLogic_outputRsp_payload_PRDATA; - wire outputLogic_outputRsp_payload_PSLVERROR; - wire outputLogic_outputCmd_fire; - - EfxDMA_FlowCCUnsafeByToggle flowCCUnsafeByToggle ( - .io_input_valid (inputLogic_inputCmd_valid ), //i - .io_input_payload_PADDR (inputLogic_inputCmd_payload_PADDR[13:0] ), //i - .io_input_payload_PWRITE (inputLogic_inputCmd_payload_PWRITE ), //i - .io_input_payload_PWDATA (inputLogic_inputCmd_payload_PWDATA[31:0] ), //i - .io_output_valid (flowCCUnsafeByToggle_io_output_valid ), //o - .io_output_payload_PADDR (flowCCUnsafeByToggle_io_output_payload_PADDR[13:0] ), //o - .io_output_payload_PWRITE (flowCCUnsafeByToggle_io_output_payload_PWRITE ), //o - .io_output_payload_PWDATA (flowCCUnsafeByToggle_io_output_payload_PWDATA[31:0]), //o - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_FlowCCUnsafeByToggle_1 flowCCUnsafeByToggle_1 ( - .io_input_valid (outputLogic_outputRsp_valid ), //i - .io_input_payload_PRDATA (outputLogic_outputRsp_payload_PRDATA[31:0] ), //i - .io_input_payload_PSLVERROR (outputLogic_outputRsp_payload_PSLVERROR ), //i - .io_output_valid (flowCCUnsafeByToggle_1_io_output_valid ), //o - .io_output_payload_PRDATA (flowCCUnsafeByToggle_1_io_output_payload_PRDATA[31:0]), //o - .io_output_payload_PSLVERROR (flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR ), //o - .clk (clk ), //i - .reset (reset ), //i - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ) //i - ); - assign inputLogic_inputCmd_valid = ((io_input_PSEL[0] && io_input_PENABLE) && (! inputLogic_state)); - assign inputLogic_inputCmd_payload_PADDR = io_input_PADDR; - assign inputLogic_inputCmd_payload_PWRITE = io_input_PWRITE; - assign inputLogic_inputCmd_payload_PWDATA = io_input_PWDATA; - assign io_input_PREADY = inputLogic_inputRsp_valid; - assign io_input_PRDATA = inputLogic_inputRsp_payload_PRDATA; - assign io_input_PSLVERROR = inputLogic_inputRsp_payload_PSLVERROR; - assign flowCCUnsafeByToggle_io_output_toStream_valid = flowCCUnsafeByToggle_io_output_valid; - assign flowCCUnsafeByToggle_io_output_toStream_payload_PADDR = flowCCUnsafeByToggle_io_output_payload_PADDR; - assign flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE = flowCCUnsafeByToggle_io_output_payload_PWRITE; - assign flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA = flowCCUnsafeByToggle_io_output_payload_PWDATA; - assign flowCCUnsafeByToggle_io_output_toStream_fire = (flowCCUnsafeByToggle_io_output_toStream_valid && flowCCUnsafeByToggle_io_output_toStream_ready); - always @(*) begin - flowCCUnsafeByToggle_io_output_toStream_ready = outputLogic_outputCmd_ready; - if(when_Stream_l375) begin - flowCCUnsafeByToggle_io_output_toStream_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! outputLogic_outputCmd_valid); - assign outputLogic_outputCmd_valid = flowCCUnsafeByToggle_io_output_toStream_rValid; - assign outputLogic_outputCmd_payload_PADDR = flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; - assign outputLogic_outputCmd_payload_PWRITE = flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; - assign outputLogic_outputCmd_payload_PWDATA = flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; - always @(*) begin - io_output_PENABLE = 1'b0; - if(outputLogic_outputCmd_valid) begin - if(when_Apb3CCToggle_l81) begin - io_output_PENABLE = 1'b0; - end else begin - io_output_PENABLE = 1'b1; - end - end - end - - always @(*) begin - io_output_PSEL = 1'b0; - if(outputLogic_outputCmd_valid) begin - io_output_PSEL = 1'b1; - end - end - - assign io_output_PADDR = outputLogic_outputCmd_payload_PADDR; - assign io_output_PWDATA = outputLogic_outputCmd_payload_PWDATA; - assign io_output_PWRITE = outputLogic_outputCmd_payload_PWRITE; - always @(*) begin - outputLogic_outputCmd_ready = 1'b0; - if(outputLogic_outputCmd_valid) begin - if(!when_Apb3CCToggle_l81) begin - if(io_output_PREADY) begin - outputLogic_outputCmd_ready = 1'b1; - end - end - end - end - - assign when_Apb3CCToggle_l81 = (! outputLogic_state); - assign outputLogic_outputCmd_fire = (outputLogic_outputCmd_valid && outputLogic_outputCmd_ready); - assign outputLogic_outputRsp_valid = outputLogic_outputCmd_fire; - assign outputLogic_outputRsp_payload_PRDATA = io_output_PRDATA; - assign outputLogic_outputRsp_payload_PSLVERROR = io_output_PSLVERROR; - assign inputLogic_inputRsp_valid = flowCCUnsafeByToggle_1_io_output_valid; - assign inputLogic_inputRsp_payload_PRDATA = flowCCUnsafeByToggle_1_io_output_payload_PRDATA; - assign inputLogic_inputRsp_payload_PSLVERROR = flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - inputLogic_state <= 1'b0; - end else begin - if(inputLogic_inputCmd_valid) begin - inputLogic_state <= 1'b1; - end - if(inputLogic_inputRsp_valid) begin - inputLogic_state <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(reset) begin - flowCCUnsafeByToggle_io_output_toStream_rValid <= 1'b0; - outputLogic_state <= 1'b0; - end else begin - if(flowCCUnsafeByToggle_io_output_toStream_ready) begin - flowCCUnsafeByToggle_io_output_toStream_rValid <= flowCCUnsafeByToggle_io_output_toStream_valid; - end - if(outputLogic_outputCmd_valid) begin - if(when_Apb3CCToggle_l81) begin - outputLogic_state <= 1'b1; - end else begin - if(io_output_PREADY) begin - outputLogic_state <= 1'b0; - end - end - end - end - end - - always @(posedge clk) begin - if(flowCCUnsafeByToggle_io_output_toStream_fire) begin - flowCCUnsafeByToggle_io_output_toStream_rData_PADDR <= flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; - flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE <= flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; - flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA <= flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; - end - end - - -endmodule - -module EfxDMA_Core ( - output wire io_sgRead_cmd_valid, - input wire io_sgRead_cmd_ready, - output wire io_sgRead_cmd_payload_last, - output wire [0:0] io_sgRead_cmd_payload_fragment_opcode, - output wire [31:0] io_sgRead_cmd_payload_fragment_address, - output wire [4:0] io_sgRead_cmd_payload_fragment_length, - output wire [0:0] io_sgRead_cmd_payload_fragment_context, - input wire io_sgRead_rsp_valid, - output wire io_sgRead_rsp_ready, - input wire io_sgRead_rsp_payload_last, - input wire [0:0] io_sgRead_rsp_payload_fragment_opcode, - input wire [127:0] io_sgRead_rsp_payload_fragment_data, - input wire [0:0] io_sgRead_rsp_payload_fragment_context, - output wire io_sgWrite_cmd_valid, - input wire io_sgWrite_cmd_ready, - output wire io_sgWrite_cmd_payload_last, - output wire [0:0] io_sgWrite_cmd_payload_fragment_opcode, - output wire [31:0] io_sgWrite_cmd_payload_fragment_address, - output wire [1:0] io_sgWrite_cmd_payload_fragment_length, - output reg [127:0] io_sgWrite_cmd_payload_fragment_data, - output reg [15:0] io_sgWrite_cmd_payload_fragment_mask, - output wire [0:0] io_sgWrite_cmd_payload_fragment_context, - input wire io_sgWrite_rsp_valid, - output wire io_sgWrite_rsp_ready, - input wire io_sgWrite_rsp_payload_last, - input wire [0:0] io_sgWrite_rsp_payload_fragment_opcode, - input wire [0:0] io_sgWrite_rsp_payload_fragment_context, - output reg io_read_cmd_valid, - input wire io_read_cmd_ready, - output wire io_read_cmd_payload_last, - output wire [0:0] io_read_cmd_payload_fragment_opcode, - output wire [31:0] io_read_cmd_payload_fragment_address, - output wire [11:0] io_read_cmd_payload_fragment_length, - output wire [20:0] io_read_cmd_payload_fragment_context, - input wire io_read_rsp_valid, - output wire io_read_rsp_ready, - input wire io_read_rsp_payload_last, - input wire [0:0] io_read_rsp_payload_fragment_opcode, - input wire [127:0] io_read_rsp_payload_fragment_data, - input wire [20:0] io_read_rsp_payload_fragment_context, - output wire io_write_cmd_valid, - input wire io_write_cmd_ready, - output wire io_write_cmd_payload_last, - output wire [0:0] io_write_cmd_payload_fragment_opcode, - output wire [31:0] io_write_cmd_payload_fragment_address, - output wire [11:0] io_write_cmd_payload_fragment_length, - output wire [127:0] io_write_cmd_payload_fragment_data, - output wire [15:0] io_write_cmd_payload_fragment_mask, - output wire [12:0] io_write_cmd_payload_fragment_context, - input wire io_write_rsp_valid, - output wire io_write_rsp_ready, - input wire io_write_rsp_payload_last, - input wire [0:0] io_write_rsp_payload_fragment_opcode, - input wire [12:0] io_write_rsp_payload_fragment_context, - output wire io_outputs_0_valid, - input wire io_outputs_0_ready, - output wire [63:0] io_outputs_0_payload_data, - output wire [7:0] io_outputs_0_payload_mask, - output wire [3:0] io_outputs_0_payload_sink, - output wire io_outputs_0_payload_last, - input wire io_inputs_0_valid, - output reg io_inputs_0_ready, - input wire [63:0] io_inputs_0_payload_data, - input wire [7:0] io_inputs_0_payload_mask, - input wire [3:0] io_inputs_0_payload_sink, - input wire io_inputs_0_payload_last, - output reg [1:0] io_interrupts, - input wire [13:0] io_ctrl_PADDR, - input wire [0:0] io_ctrl_PSEL, - input wire io_ctrl_PENABLE, - output wire io_ctrl_PREADY, - input wire io_ctrl_PWRITE, - input wire [31:0] io_ctrl_PWDATA, - output reg [31:0] io_ctrl_PRDATA, - output wire io_ctrl_PSLVERROR, - output wire ll_0_descriptorUpdate, - output wire ll_1_descriptorUpdate, - input wire clk, - input wire reset -); - - wire [9:0] memory_core_io_writes_0_cmd_payload_address; - wire [6:0] memory_core_io_writes_0_cmd_payload_context; - wire [9:0] memory_core_io_writes_1_cmd_payload_address; - reg [15:0] memory_core_io_writes_1_cmd_payload_mask; - wire [6:0] memory_core_io_writes_1_cmd_payload_context; - wire memory_core_io_reads_0_cmd_valid; - wire [9:0] memory_core_io_reads_0_cmd_payload_address; - wire [2:0] memory_core_io_reads_0_cmd_payload_context; - wire [9:0] memory_core_io_reads_1_cmd_payload_address; - wire [11:0] memory_core_io_reads_1_cmd_payload_context; - wire [15:0] b2m_fsm_aggregate_engine_io_input_payload_mask; - wire b2m_fsm_aggregate_engine_io_flush; - wire [3:0] b2m_fsm_aggregate_engine_io_offset; - wire memory_core_io_writes_0_cmd_ready; - wire memory_core_io_writes_0_rsp_valid; - wire [6:0] memory_core_io_writes_0_rsp_payload_context; - wire memory_core_io_writes_1_cmd_ready; - wire memory_core_io_writes_1_rsp_valid; - wire [6:0] memory_core_io_writes_1_rsp_payload_context; - wire memory_core_io_reads_0_cmd_ready; - wire memory_core_io_reads_0_rsp_valid; - wire [63:0] memory_core_io_reads_0_rsp_payload_data; - wire [7:0] memory_core_io_reads_0_rsp_payload_mask; - wire [2:0] memory_core_io_reads_0_rsp_payload_context; - wire memory_core_io_reads_1_cmd_ready; - wire memory_core_io_reads_1_rsp_valid; - wire [127:0] memory_core_io_reads_1_rsp_payload_data; - wire [15:0] memory_core_io_reads_1_rsp_payload_mask; - wire [11:0] memory_core_io_reads_1_rsp_payload_context; - wire b2m_fsm_aggregate_engine_io_input_ready; - wire [127:0] b2m_fsm_aggregate_engine_io_output_data; - wire [15:0] b2m_fsm_aggregate_engine_io_output_mask; - wire b2m_fsm_aggregate_engine_io_output_consumed; - wire [3:0] b2m_fsm_aggregate_engine_io_output_usedUntil; - wire [26:0] _zz_channels_0_bytesProbe_value; - wire [26:0] _zz_channels_0_bytesProbe_value_1; - wire [13:0] _zz_channels_0_fifo_pop_withOverride_backupNext; - wire [13:0] _zz_channels_0_fifo_pop_withOverride_exposed; - wire [26:0] _zz_channels_0_pop_b2m_selfFlush; - wire [13:0] _zz_channels_0_pop_b2m_request; - wire [10:0] _zz_channels_0_pop_b2m_request_1; - wire [9:0] _zz_channels_0_pop_b2m_request_2; - wire [3:0] _zz_channels_0_pop_b2m_memPending; - wire [3:0] _zz_channels_0_pop_b2m_memPending_1; - wire [0:0] _zz_channels_0_pop_b2m_memPending_2; - wire [3:0] _zz_channels_0_pop_b2m_memPending_3; - wire [0:0] _zz_channels_0_pop_b2m_memPending_4; - wire [10:0] _zz_channels_0_fifo_push_available; - wire [26:0] _zz_channels_1_bytesProbe_value; - wire [26:0] _zz_channels_1_bytesProbe_value_1; - wire [13:0] _zz_channels_1_fifo_pop_withoutOverride_exposed; - wire [3:0] _zz_channels_1_push_m2b_memPending; - wire [3:0] _zz_channels_1_push_m2b_memPending_1; - wire [0:0] _zz_channels_1_push_m2b_memPending_2; - wire [3:0] _zz_channels_1_push_m2b_memPending_3; - wire [0:0] _zz_channels_1_push_m2b_memPending_4; - wire [10:0] _zz_channels_1_push_m2b_loadRequest; - wire [8:0] _zz_channels_1_push_m2b_loadRequest_1; - wire [25:0] _zz_when_DmaSg_l486; - wire [10:0] _zz_channels_1_fifo_push_available; - wire [0:0] _zz_s2b_0_cmd_firsts; - wire [4:0] _zz_s2b_0_cmd_firsts_1; - wire [3:0] _zz_s2b_0_cmd_byteCount_8; - reg [3:0] _zz_s2b_0_cmd_byteCount_9; - wire [2:0] _zz_s2b_0_cmd_byteCount_10; - reg [3:0] _zz_s2b_0_cmd_byteCount_11; - wire [2:0] _zz_s2b_0_cmd_byteCount_12; - reg [3:0] _zz_s2b_0_cmd_byteCount_13; - wire [2:0] _zz_s2b_0_cmd_byteCount_14; - wire [1:0] _zz_s2b_0_cmd_byteCount_15; - wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2; - wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1; - wire [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2; - reg [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; - wire [25:0] _zz_m2b_cmd_s0_length; - wire [25:0] _zz_m2b_cmd_s0_length_1; - wire [25:0] _zz_m2b_cmd_s0_length_2; - wire [25:0] _zz_m2b_cmd_s0_lastBurst; - wire [31:0] _zz_m2b_cmd_s1_context_stop; - wire [31:0] _zz_m2b_cmd_s1_context_stop_1; - wire [31:0] _zz_m2b_cmd_s1_addressNext; - wire [31:0] _zz_m2b_cmd_s1_addressNext_1; - wire [25:0] _zz_m2b_cmd_s1_byteLeftNext; - wire [25:0] _zz_m2b_cmd_s1_byteLeftNext_1; - wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr; - wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_1; - wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_2; - wire [3:0] _zz_m2b_cmd_s1_fifoPushDecr_3; - wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr_4; - wire [1:0] _zz_m2b_cmd_s1_fifoPushDecr_5; - wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; - wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1; - wire [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2; - reg [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; - wire [0:0] _zz_when; - wire [12:0] _zz_b2m_fsm_bytesInBurstP1; - wire [1:0] _zz_b2m_fsm_bytesInBurstP1_1; - wire [31:0] _zz_b2m_fsm_addressNext; - wire [26:0] _zz_b2m_fsm_bytesLeftNext; - wire [13:0] _zz_b2m_fsm_bytesLeftNext_1; - wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1; - wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1_1; - wire [11:0] _zz__zz_b2m_fsm_sel_bytesInBurst_2; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_3; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_4; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_5; - wire [13:0] _zz_b2m_fsm_fifoCompletion; - wire [13:0] _zz_b2m_fsm_fifoCompletion_1; - wire [11:0] _zz_b2m_fsm_beatCounter; - wire [11:0] _zz_b2m_fsm_beatCounter_1; - wire [3:0] _zz_b2m_fsm_beatCounter_2; - wire [10:0] _zz_b2m_fsm_sel_ptr; - wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_1; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_2; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_3; - wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_4; - wire [9:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_5; - wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_6; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_7; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_8; - wire _zz_b2m_fsm_aggregate_bytesToSkipMask_9; - wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_10; - wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_11; - wire [3:0] _zz_b2m_fsm_cmd_maskLastTriggerComb; - wire [3:0] _zz_b2m_fsm_cmd_maskLast; - wire _zz_b2m_fsm_cmd_maskLast_1; - wire [0:0] _zz_b2m_fsm_cmd_maskLast_2; - wire [7:0] _zz_b2m_fsm_cmd_maskLast_3; - wire [3:0] _zz_b2m_fsm_cmd_maskLast_4; - wire [3:0] _zz_b2m_fsm_cmd_maskLast_5; - wire [3:0] _zz_b2m_fsm_cmd_maskFirst; - wire _zz_b2m_fsm_cmd_maskFirst_1; - wire [0:0] _zz_b2m_fsm_cmd_maskFirst_2; - wire [7:0] _zz_b2m_fsm_cmd_maskFirst_3; - wire [3:0] _zz_b2m_fsm_cmd_maskFirst_4; - wire [3:0] _zz_b2m_fsm_cmd_maskFirst_5; - wire [0:0] _zz_when_1; - wire [0:0] _zz_when_2; - wire [1:0] _zz__zz_ll_arbiter_head_1; - wire [1:0] _zz__zz_ll_arbiter_head_1_1; - wire [1:0] _zz_ll_arbiter_head_2; - wire [1:0] _zz_ll_arbiter_isJustASink; - wire [1:0] _zz_ll_arbiter_doDescriptorStall; - wire [1:0] _zz_ll_arbiter_onSgStream; - wire [1:0] _zz_ll_cmd_ptr; - wire [1:0] _zz_ll_cmd_ptrNext; - wire [1:0] _zz_ll_cmd_endOfPacket; - wire [0:0] _zz_channels_0_channelStart; - wire [0:0] _zz_channels_0_ctrl_kick; - wire [0:0] _zz_channels_0_channelStart_1; - wire [0:0] _zz_channels_0_ll_sgStart; - wire [0:0] _zz_channels_0_interrupts_completion_valid; - wire [0:0] _zz_channels_0_interrupts_onChannelCompletion_valid; - wire [0:0] _zz_channels_0_interrupts_onLinkedListUpdate_valid; - wire [0:0] _zz_channels_0_interrupts_s2mPacket_valid; - wire [0:0] _zz_channels_1_channelStart; - wire [0:0] _zz_channels_1_ctrl_kick; - wire [0:0] _zz_channels_1_channelStart_1; - wire [0:0] _zz_channels_1_ll_sgStart; - wire [0:0] _zz_channels_1_interrupts_completion_valid; - wire [0:0] _zz_channels_1_interrupts_onChannelCompletion_valid; - wire [0:0] _zz_channels_1_interrupts_onLinkedListUpdate_valid; - wire [31:0] _zz_io_ctrl_PRDATA; - wire [31:0] _zz_io_ctrl_PRDATA_1; - wire [10:0] _zz_channels_0_fifo_push_ptrIncr_value; - wire [0:0] _zz_channels_0_fifo_push_ptrIncr_value_1; - wire [13:0] _zz_channels_0_fifo_pop_bytesIncr_value_1; - wire [3:0] _zz_channels_0_fifo_pop_bytesIncr_value_2; - wire [10:0] _zz_channels_0_fifo_pop_ptrIncr_value; - wire [1:0] _zz_channels_0_fifo_pop_ptrIncr_value_1; - wire [10:0] _zz_channels_1_fifo_push_ptrIncr_value_1; - wire [1:0] _zz_channels_1_fifo_push_ptrIncr_value_2; - wire [13:0] _zz_channels_1_fifo_pop_bytesIncr_value_1; - wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_2; - wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_3; - wire [10:0] _zz_channels_1_fifo_pop_ptrIncr_value; - wire [0:0] _zz_channels_1_fifo_pop_ptrIncr_value_1; - wire ctrl_readErrorFlag; - wire ctrl_writeErrorFlag; - wire ctrl_askWrite; - wire ctrl_askRead; - wire ctrl_doWrite; - wire ctrl_doRead; - reg channels_0_channelStart; - reg channels_0_channelStop; - reg channels_0_channelCompletion; - reg channels_0_channelValid; - reg channels_0_descriptorStart; - reg channels_0_descriptorCompletion; - reg channels_0_descriptorValid; - reg [25:0] channels_0_bytes; - reg [1:0] channels_0_priority; - reg [1:0] channels_0_weight; - reg channels_0_readyToStop; - reg [26:0] channels_0_bytesProbe_value; - reg channels_0_bytesProbe_incr_valid; - reg [11:0] channels_0_bytesProbe_incr_payload; - reg channels_0_ctrl_kick; - reg channels_0_ll_sgStart; - reg channels_0_ll_valid; - reg channels_0_ll_onSgStream; - reg channels_0_ll_head; - reg channels_0_ll_justASync; - reg channels_0_ll_waitDone; - reg channels_0_ll_readDone; - reg channels_0_ll_writeDone; - reg channels_0_ll_gotDescriptorStall; - reg channels_0_ll_controlNoCompletion; - reg channels_0_ll_packet; - reg channels_0_ll_requireSync; - reg [31:0] channels_0_ll_ptr; - reg [31:0] channels_0_ll_ptrNext; - wire channels_0_ll_requestLl; - reg channels_0_ll_descriptorUpdated; - wire when_DmaSg_l318; - wire when_DmaSg_l320; - wire when_DmaSg_l322; - wire when_DmaSg_l328; - wire [10:0] channels_0_fifo_base; - wire [10:0] channels_0_fifo_words; - reg [10:0] channels_0_fifo_push_available; - wire [10:0] channels_0_fifo_push_availableDecr; - reg [10:0] channels_0_fifo_push_ptr; - wire [10:0] channels_0_fifo_push_ptrWithBase; - wire [10:0] channels_0_fifo_push_ptrIncr_value; - reg [10:0] channels_0_fifo_pop_ptr; - wire [13:0] channels_0_fifo_pop_bytes; - wire [10:0] channels_0_fifo_pop_ptrWithBase; - wire [13:0] channels_0_fifo_pop_bytesIncr_value; - wire [13:0] channels_0_fifo_pop_bytesDecr_value; - wire channels_0_fifo_pop_empty; - wire [10:0] channels_0_fifo_pop_ptrIncr_value; - reg [13:0] channels_0_fifo_pop_withOverride_backup; - wire [13:0] channels_0_fifo_pop_withOverride_backupNext; - reg channels_0_fifo_pop_withOverride_load; - reg channels_0_fifo_pop_withOverride_unload; - reg [13:0] channels_0_fifo_pop_withOverride_exposed; - reg channels_0_fifo_pop_withOverride_valid; - wire when_DmaSg_l409; - wire channels_0_fifo_empty; - reg channels_0_push_memory; - reg channels_0_push_s2b_completionOnLast; - reg channels_0_push_s2b_packetEvent; - reg channels_0_push_s2b_packetLock; - reg channels_0_push_s2b_waitFirst; - wire when_DmaSg_l457; - reg channels_0_pop_memory; - wire [11:0] channels_0_pop_b2m_bytePerBurst; - reg channels_0_pop_b2m_fire; - reg channels_0_pop_b2m_waitFinalRsp; - reg channels_0_pop_b2m_flush; - reg channels_0_pop_b2m_packetSync; - reg channels_0_pop_b2m_packet; - wire when_DmaSg_l505; - reg channels_0_pop_b2m_memRsp; - reg [3:0] channels_0_pop_b2m_memPending; - reg [31:0] channels_0_pop_b2m_address; - reg [26:0] channels_0_pop_b2m_bytesLeft; - wire channels_0_pop_b2m_selfFlush; - wire channels_0_pop_b2m_request; - reg [3:0] channels_0_pop_b2m_bytesToSkip; - reg [13:0] channels_0_pop_b2m_decrBytes; - reg channels_0_pop_b2m_memPendingInc; - wire when_DmaSg_l523; - wire when_DmaSg_l532; - wire when_DmaSg_l536; - wire when_DmaSg_l547; - wire when_DmaSg_l563; - wire channels_0_readyForChannelCompletion; - wire when_DmaSg_l575; - reg _zz_when_DmaSg_l593; - wire when_DmaSg_l593; - wire channels_0_s2b_full; - reg [10:0] channels_0_fifo_pop_ptrIncr_value_regNext; - wire when_DmaSg_l255; - reg channels_0_interrupts_completion_enable; - reg channels_0_interrupts_completion_valid; - wire when_DmaSg_l255_1; - wire when_DmaSg_l255_2; - reg channels_0_interrupts_onChannelCompletion_enable; - reg channels_0_interrupts_onChannelCompletion_valid; - wire when_DmaSg_l255_3; - reg channels_0_interrupts_onLinkedListUpdate_enable; - reg channels_0_interrupts_onLinkedListUpdate_valid; - wire when_DmaSg_l255_4; - reg channels_0_interrupts_s2mPacket_enable; - reg channels_0_interrupts_s2mPacket_valid; - wire when_DmaSg_l255_5; - wire when_DmaSg_l625; - reg channels_1_channelStart; - reg channels_1_channelStop; - reg channels_1_channelCompletion; - reg channels_1_channelValid; - reg channels_1_descriptorStart; - reg channels_1_descriptorCompletion; - reg channels_1_descriptorValid; - reg [25:0] channels_1_bytes; - reg [1:0] channels_1_priority; - reg [1:0] channels_1_weight; - reg channels_1_readyToStop; - reg [26:0] channels_1_bytesProbe_value; - reg channels_1_bytesProbe_incr_valid; - reg [11:0] channels_1_bytesProbe_incr_payload; - reg channels_1_ctrl_kick; - reg channels_1_ll_sgStart; - reg channels_1_ll_valid; - reg channels_1_ll_onSgStream; - reg channels_1_ll_head; - reg channels_1_ll_justASync; - reg channels_1_ll_waitDone; - reg channels_1_ll_readDone; - reg channels_1_ll_writeDone; - reg channels_1_ll_gotDescriptorStall; - reg channels_1_ll_controlNoCompletion; - reg channels_1_ll_packet; - reg channels_1_ll_requireSync; - reg [31:0] channels_1_ll_ptr; - reg [31:0] channels_1_ll_ptrNext; - wire channels_1_ll_requestLl; - reg channels_1_ll_descriptorUpdated; - wire when_DmaSg_l318_1; - wire when_DmaSg_l320_1; - wire when_DmaSg_l322_1; - wire when_DmaSg_l328_1; - wire [10:0] channels_1_fifo_base; - wire [10:0] channels_1_fifo_words; - reg [10:0] channels_1_fifo_push_available; - reg [10:0] channels_1_fifo_push_availableDecr; - reg [10:0] channels_1_fifo_push_ptr; - wire [10:0] channels_1_fifo_push_ptrWithBase; - wire [10:0] channels_1_fifo_push_ptrIncr_value; - reg [10:0] channels_1_fifo_pop_ptr; - wire [13:0] channels_1_fifo_pop_bytes; - wire [10:0] channels_1_fifo_pop_ptrWithBase; - wire [13:0] channels_1_fifo_pop_bytesIncr_value; - wire [13:0] channels_1_fifo_pop_bytesDecr_value; - wire channels_1_fifo_pop_empty; - wire [10:0] channels_1_fifo_pop_ptrIncr_value; - reg [13:0] channels_1_fifo_pop_withoutOverride_exposed; - wire channels_1_fifo_empty; - reg channels_1_push_memory; - reg [31:0] channels_1_push_m2b_address; - wire [11:0] channels_1_push_m2b_bytePerBurst; - reg channels_1_push_m2b_loadDone; - reg [25:0] channels_1_push_m2b_bytesLeft; - reg [3:0] channels_1_push_m2b_memPending; - reg channels_1_push_m2b_memPendingIncr; - reg channels_1_push_m2b_memPendingDecr; - reg channels_1_push_m2b_loadRequest; - reg channels_1_pop_memory; - reg channels_1_pop_b2s_last; - reg [3:0] channels_1_pop_b2s_sinkId; - reg channels_1_pop_b2s_veryLastTrigger; - reg channels_1_pop_b2s_veryLastValid; - wire when_DmaSg_l474; - reg [10:0] channels_1_pop_b2s_veryLastPtr; - reg channels_1_pop_b2s_veryLastEndPacket; - wire when_DmaSg_l483; - wire when_DmaSg_l486; - wire when_DmaSg_l562; - reg channels_1_readyForChannelCompletion; - wire when_DmaSg_l566; - wire when_DmaSg_l575_1; - reg _zz_when_DmaSg_l593_1; - wire when_DmaSg_l593_1; - wire channels_1_s2b_full; - reg [10:0] channels_1_fifo_pop_ptrIncr_value_regNext; - wire when_DmaSg_l255_6; - reg channels_1_interrupts_completion_enable; - reg channels_1_interrupts_completion_valid; - wire when_DmaSg_l255_7; - wire when_DmaSg_l255_8; - reg channels_1_interrupts_onChannelCompletion_enable; - reg channels_1_interrupts_onChannelCompletion_valid; - wire when_DmaSg_l255_9; - reg channels_1_interrupts_onLinkedListUpdate_enable; - reg channels_1_interrupts_onLinkedListUpdate_valid; - wire when_DmaSg_l255_10; - wire when_DmaSg_l625_1; - wire io_inputs_0_fire; - wire when_package_l12; - reg io_inputs_0_payload_last_regNextWhen; - wire when_package_l12_1; - reg io_inputs_0_payload_last_regNextWhen_1; - wire when_package_l12_2; - reg io_inputs_0_payload_last_regNextWhen_2; - wire when_package_l12_3; - reg io_inputs_0_payload_last_regNextWhen_3; - wire when_package_l12_4; - reg io_inputs_0_payload_last_regNextWhen_4; - wire when_package_l12_5; - reg io_inputs_0_payload_last_regNextWhen_5; - wire when_package_l12_6; - reg io_inputs_0_payload_last_regNextWhen_6; - wire when_package_l12_7; - reg io_inputs_0_payload_last_regNextWhen_7; - wire when_package_l12_8; - reg io_inputs_0_payload_last_regNextWhen_8; - wire when_package_l12_9; - reg io_inputs_0_payload_last_regNextWhen_9; - wire when_package_l12_10; - reg io_inputs_0_payload_last_regNextWhen_10; - wire when_package_l12_11; - reg io_inputs_0_payload_last_regNextWhen_11; - wire when_package_l12_12; - reg io_inputs_0_payload_last_regNextWhen_12; - wire when_package_l12_13; - reg io_inputs_0_payload_last_regNextWhen_13; - wire when_package_l12_14; - reg io_inputs_0_payload_last_regNextWhen_14; - wire when_package_l12_15; - reg io_inputs_0_payload_last_regNextWhen_15; - wire [15:0] s2b_0_cmd_firsts; - wire s2b_0_cmd_first; - wire [0:0] s2b_0_cmd_channelsOh; - wire s2b_0_cmd_noHit; - wire [0:0] s2b_0_cmd_channelsFull; - reg io_inputs_0_thrown_valid; - wire io_inputs_0_thrown_ready; - wire [63:0] io_inputs_0_thrown_payload_data; - wire [7:0] io_inputs_0_thrown_payload_mask; - wire [3:0] io_inputs_0_thrown_payload_sink; - wire io_inputs_0_thrown_payload_last; - wire _zz_io_inputs_0_thrown_ready; - wire s2b_0_cmd_sinkHalted_valid; - wire s2b_0_cmd_sinkHalted_ready; - wire [63:0] s2b_0_cmd_sinkHalted_payload_data; - wire [7:0] s2b_0_cmd_sinkHalted_payload_mask; - wire [3:0] s2b_0_cmd_sinkHalted_payload_sink; - wire s2b_0_cmd_sinkHalted_payload_last; - wire [3:0] _zz_s2b_0_cmd_byteCount; - wire [3:0] _zz_s2b_0_cmd_byteCount_1; - wire [3:0] _zz_s2b_0_cmd_byteCount_2; - wire [3:0] _zz_s2b_0_cmd_byteCount_3; - wire [3:0] _zz_s2b_0_cmd_byteCount_4; - wire [3:0] _zz_s2b_0_cmd_byteCount_5; - wire [3:0] _zz_s2b_0_cmd_byteCount_6; - wire [3:0] _zz_s2b_0_cmd_byteCount_7; - wire [3:0] s2b_0_cmd_byteCount; - wire [0:0] s2b_0_cmd_context_channel; - wire [3:0] s2b_0_cmd_context_bytes; - wire s2b_0_cmd_context_flush; - wire s2b_0_cmd_context_packet; - wire memory_core_io_writes_0_cmd_fire; - wire when_DmaSg_l665; - wire [0:0] s2b_0_rsp_context_channel; - wire [3:0] s2b_0_rsp_context_bytes; - wire s2b_0_rsp_context_flush; - wire s2b_0_rsp_context_packet; - wire [6:0] _zz_s2b_0_rsp_context_channel; - wire _zz_channels_0_fifo_pop_bytesIncr_value; - wire when_DmaSg_l679; - wire when_DmaSg_l681; - wire when_DmaSg_l682; - wire [0:0] b2s_0_cmd_channelsOh; - wire [0:0] b2s_0_cmd_context_channel; - wire b2s_0_cmd_context_veryLast; - wire b2s_0_cmd_context_endPacket; - wire [10:0] b2s_0_cmd_veryLastPtr; - wire [10:0] b2s_0_cmd_address; - wire [0:0] b2s_0_rsp_context_channel; - wire b2s_0_rsp_context_veryLast; - wire b2s_0_rsp_context_endPacket; - wire [2:0] _zz_b2s_0_rsp_context_channel; - wire io_outputs_0_fire; - wire when_DmaSg_l725; - wire when_DmaSg_l726; - reg m2b_cmd_s0_valid; - wire [1:0] _zz_m2b_cmd_s0_priority_masked; - wire [0:0] m2b_cmd_s0_priority_masked; - reg [0:0] m2b_cmd_s0_priority_roundRobins_0; - reg [0:0] m2b_cmd_s0_priority_roundRobins_1; - reg [0:0] m2b_cmd_s0_priority_roundRobins_2; - reg [0:0] m2b_cmd_s0_priority_roundRobins_3; - reg [1:0] m2b_cmd_s0_priority_counter; - wire [0:0] _zz_m2b_cmd_s0_priority_chosenOh; - wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_1; - wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_2; - wire [0:0] m2b_cmd_s0_priority_chosenOh; - wire m2b_cmd_s0_priority_weightLast; - wire [0:0] m2b_cmd_s0_priority_contextNext; - wire when_DmaSg_l758; - wire when_DmaSg_l760; - wire when_DmaSg_l763; - wire when_DmaSg_l763_1; - wire when_DmaSg_l763_2; - wire when_DmaSg_l763_3; - wire when_DmaSg_l773; - wire [31:0] m2b_cmd_s0_address; - wire [25:0] m2b_cmd_s0_bytesLeft; - wire [11:0] m2b_cmd_s0_readAddressBurstRange; - wire [11:0] m2b_cmd_s0_lengthHead; - wire [11:0] m2b_cmd_s0_length; - wire m2b_cmd_s0_lastBurst; - reg m2b_cmd_s1_valid; - reg [31:0] m2b_cmd_s1_address; - reg [11:0] m2b_cmd_s1_length; - reg m2b_cmd_s1_lastBurst; - reg [25:0] m2b_cmd_s1_bytesLeft; - wire [3:0] m2b_cmd_s1_context_start; - wire [3:0] m2b_cmd_s1_context_stop; - wire [11:0] m2b_cmd_s1_context_length; - wire m2b_cmd_s1_context_last; - wire [31:0] m2b_cmd_s1_addressNext; - wire [25:0] m2b_cmd_s1_byteLeftNext; - wire [9:0] m2b_cmd_s1_fifoPushDecr; - wire when_DmaSg_l828; - wire [3:0] m2b_rsp_context_start; - wire [3:0] m2b_rsp_context_stop; - wire [11:0] m2b_rsp_context_length; - wire m2b_rsp_context_last; - wire [20:0] _zz_m2b_rsp_context_start; - wire m2b_rsp_veryLast; - wire io_read_rsp_fire; - wire when_DmaSg_l847; - wire when_DmaSg_l848; - reg m2b_rsp_first; - wire m2b_rsp_writeContext_last; - wire m2b_rsp_writeContext_lastOfBurst; - wire [4:0] m2b_rsp_writeContext_loadByteInNextBeat; - wire memory_core_io_writes_1_cmd_fire; - wire _zz_channels_1_fifo_push_ptrIncr_value; - wire when_DmaSg_l874; - wire m2b_writeRsp_context_last; - wire m2b_writeRsp_context_lastOfBurst; - wire [4:0] m2b_writeRsp_context_loadByteInNextBeat; - wire [6:0] _zz_m2b_writeRsp_context_last; - wire _zz_channels_1_fifo_pop_bytesIncr_value; - wire when_DmaSg_l893; - reg b2m_fsm_sel_valid; - reg b2m_fsm_sel_ready; - reg [11:0] b2m_fsm_sel_bytePerBurst; - reg [11:0] b2m_fsm_sel_bytesInBurst; - reg [13:0] b2m_fsm_sel_bytesInFifo; - reg [31:0] b2m_fsm_sel_address; - reg [10:0] b2m_fsm_sel_ptr; - reg [10:0] b2m_fsm_sel_ptrMask; - reg b2m_fsm_sel_flush; - reg b2m_fsm_sel_packet; - reg [25:0] b2m_fsm_sel_bytesLeft; - reg b2m_fsm_arbiter_logic_valid; - wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_masked; - wire [0:0] b2m_fsm_arbiter_logic_priority_masked; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_0; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_1; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_2; - reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_3; - reg [1:0] b2m_fsm_arbiter_logic_priority_counter; - wire [0:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh; - wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1; - wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; - wire [0:0] b2m_fsm_arbiter_logic_priority_chosenOh; - wire b2m_fsm_arbiter_logic_priority_weightLast; - wire [0:0] b2m_fsm_arbiter_logic_priority_contextNext; - wire when_DmaSg_l758_1; - wire when_DmaSg_l760_1; - wire when_DmaSg_l763_4; - wire when_DmaSg_l763_5; - wire when_DmaSg_l763_6; - wire when_DmaSg_l763_7; - wire when_DmaSg_l773_1; - wire when_DmaSg_l935; - wire [12:0] b2m_fsm_bytesInBurstP1; - wire [31:0] b2m_fsm_addressNext; - wire [26:0] b2m_fsm_bytesLeftNext; - wire b2m_fsm_isFinalCmd; - reg [7:0] b2m_fsm_beatCounter; - reg b2m_fsm_sel_valid_regNext; - wire b2m_fsm_s0; - reg b2m_fsm_s1; - reg b2m_fsm_s2; - wire when_DmaSg_l986; - wire [13:0] _zz_b2m_fsm_sel_bytesInBurst; - wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_1; - wire [11:0] _zz_b2m_fsm_sel_bytesInBurst_2; - wire b2m_fsm_fifoCompletion; - wire when_DmaSg_l996; - wire when_DmaSg_l1001; - reg b2m_fsm_toggle; - wire when_DmaSg_l1013; - wire [10:0] b2m_fsm_fetch_context_ptr; - wire b2m_fsm_fetch_context_toggle; - wire when_DmaSg_l1033; - wire [10:0] b2m_fsm_aggregate_context_ptr; - wire b2m_fsm_aggregate_context_toggle; - wire [11:0] _zz_b2m_fsm_aggregate_context_ptr; - wire memory_core_io_reads_1_rsp_s2mPipe_valid; - reg memory_core_io_reads_1_rsp_s2mPipe_ready; - wire [127:0] memory_core_io_reads_1_rsp_s2mPipe_payload_data; - wire [15:0] memory_core_io_reads_1_rsp_s2mPipe_payload_mask; - wire [11:0] memory_core_io_reads_1_rsp_s2mPipe_payload_context; - reg memory_core_io_reads_1_rsp_rValidN; - reg [127:0] memory_core_io_reads_1_rsp_rData_data; - reg [15:0] memory_core_io_reads_1_rsp_rData_mask; - reg [11:0] memory_core_io_reads_1_rsp_rData_context; - wire when_Stream_l445; - reg b2m_fsm_aggregate_memoryPort_valid; - wire b2m_fsm_aggregate_memoryPort_ready; - wire [127:0] b2m_fsm_aggregate_memoryPort_payload_data; - wire [15:0] b2m_fsm_aggregate_memoryPort_payload_mask; - wire [11:0] b2m_fsm_aggregate_memoryPort_payload_context; - reg b2m_fsm_aggregate_first; - wire b2m_fsm_aggregate_memoryPort_fire; - wire when_DmaSg_l1050; - wire [3:0] b2m_fsm_aggregate_bytesToSkip; - wire [15:0] b2m_fsm_aggregate_bytesToSkipMask; - reg _zz_io_flush; - wire [3:0] b2m_fsm_cmd_maskFirstTrigger; - wire [3:0] b2m_fsm_cmd_maskLastTriggerComb; - reg [3:0] b2m_fsm_cmd_maskLastTriggerReg; - reg [15:0] b2m_fsm_cmd_maskLast; - wire [15:0] b2m_fsm_cmd_maskFirst; - wire b2m_fsm_cmd_enoughAggregation; - wire io_write_cmd_fire; - reg io_write_cmd_payload_first; - wire b2m_fsm_cmd_doPtrIncr; - wire [11:0] b2m_fsm_cmd_context_length; - wire b2m_fsm_cmd_context_doPacketSync; - wire when_DmaSg_l1102; - wire [11:0] b2m_rsp_context_length; - wire b2m_rsp_context_doPacketSync; - wire [12:0] _zz_b2m_rsp_context_length; - wire io_write_rsp_fire; - wire when_DmaSg_l1116; - wire [1:0] _zz_ll_arbiter_head; - wire _zz_ll_arbiter_head_1; - wire ll_arbiter_head; - wire ll_arbiter_isJustASink; - wire ll_arbiter_doDescriptorStall; - wire ll_arbiter_onSgStream; - reg ll_cmd_valid; - wire when_DmaSg_l1149; - reg ll_cmd_oh_0; - reg ll_cmd_oh_1; - wire when_DmaSg_l1148; - reg [31:0] ll_cmd_ptr; - wire when_DmaSg_l1148_1; - reg [31:0] ll_cmd_ptrNext; - wire when_DmaSg_l1148_2; - reg [26:0] ll_cmd_bytesDone; - wire when_DmaSg_l1148_3; - reg ll_cmd_endOfPacket; - wire when_DmaSg_l1154; - reg ll_cmd_isJustASink; - wire when_DmaSg_l1155; - reg ll_cmd_doDescriptorStall; - wire when_DmaSg_l1156; - reg ll_cmd_onSgStream; - reg ll_cmd_readFired; - reg ll_cmd_writeFired; - wire when_DmaSg_l1160; - wire when_DmaSg_l1161; - wire when_DmaSg_l1169; - wire when_DmaSg_l1169_1; - wire when_DmaSg_l1177; - wire [0:0] ll_cmd_context_channel; - wire [3:0] ll_cmd_writeMaskSplit_0; - wire [3:0] ll_cmd_writeMaskSplit_1; - wire [3:0] ll_cmd_writeMaskSplit_2; - wire [3:0] ll_cmd_writeMaskSplit_3; - wire [31:0] ll_cmd_writeDataSplit_0; - wire [31:0] ll_cmd_writeDataSplit_1; - wire [31:0] ll_cmd_writeDataSplit_2; - wire [31:0] ll_cmd_writeDataSplit_3; - wire io_sgRead_cmd_fire; - wire io_sgWrite_cmd_fire; - wire [0:0] ll_readRsp_context_channel; - wire [1:0] _zz_ll_readRsp_oh_0; - wire ll_readRsp_oh_0; - wire ll_readRsp_oh_1; - reg [0:0] ll_readRsp_beatCounter; - reg ll_readRsp_completed; - wire io_sgRead_rsp_fire; - wire when_DmaSg_l1248; - wire when_DmaSg_l1248_1; - wire when_DmaSg_l1248_2; - wire when_DmaSg_l1248_3; - wire when_DmaSg_l1248_4; - wire when_DmaSg_l1248_5; - wire when_DmaSg_l1248_6; - wire when_DmaSg_l1271; - wire [0:0] ll_writeRsp_context_channel; - wire [1:0] _zz_ll_writeRsp_oh_0; - wire ll_writeRsp_oh_0; - wire ll_writeRsp_oh_1; - wire io_sgWrite_rsp_fire; - reg when_BusSlaveFactory_l377; - wire when_BusSlaveFactory_l379; - reg when_BusSlaveFactory_l377_1; - wire when_BusSlaveFactory_l379_1; - reg when_BusSlaveFactory_l377_2; - wire when_BusSlaveFactory_l379_2; - reg when_BusSlaveFactory_l377_3; - wire when_BusSlaveFactory_l379_3; - reg when_BusSlaveFactory_l341; - wire when_BusSlaveFactory_l347; - reg when_BusSlaveFactory_l341_1; - wire when_BusSlaveFactory_l347_1; - reg when_BusSlaveFactory_l341_2; - wire when_BusSlaveFactory_l347_2; - reg when_BusSlaveFactory_l341_3; - wire when_BusSlaveFactory_l347_3; - reg when_BusSlaveFactory_l377_4; - wire when_BusSlaveFactory_l379_4; - reg when_BusSlaveFactory_l377_5; - wire when_BusSlaveFactory_l379_5; - reg when_BusSlaveFactory_l377_6; - wire when_BusSlaveFactory_l379_6; - reg when_BusSlaveFactory_l377_7; - wire when_BusSlaveFactory_l379_7; - reg when_BusSlaveFactory_l341_4; - wire when_BusSlaveFactory_l347_4; - reg when_BusSlaveFactory_l341_5; - wire when_BusSlaveFactory_l347_5; - reg when_BusSlaveFactory_l341_6; - wire when_BusSlaveFactory_l347_6; - wire when_Apb3SlaveFactory_l81; - wire when_Apb3SlaveFactory_l81_1; - wire when_Apb3SlaveFactory_l81_2; - wire when_Apb3SlaveFactory_l81_3; - function [15:0] zz_io_sgWrite_cmd_payload_fragment_mask(input dummy); - begin - zz_io_sgWrite_cmd_payload_fragment_mask[7 : 4] = 4'b0000; - zz_io_sgWrite_cmd_payload_fragment_mask[11 : 8] = 4'b0000; - zz_io_sgWrite_cmd_payload_fragment_mask[15 : 12] = 4'b0000; - zz_io_sgWrite_cmd_payload_fragment_mask[3 : 0] = 4'b1111; - end - endfunction - wire [15:0] _zz_1; - - assign _zz_channels_0_bytesProbe_value = (channels_0_bytesProbe_value + _zz_channels_0_bytesProbe_value_1); - assign _zz_channels_0_bytesProbe_value_1 = {15'd0, channels_0_bytesProbe_incr_payload}; - assign _zz_channels_0_fifo_pop_withOverride_backupNext = (channels_0_fifo_pop_withOverride_backup + channels_0_fifo_pop_bytesIncr_value); - assign _zz_channels_0_fifo_pop_withOverride_exposed = (channels_0_fifo_pop_withOverride_exposed - channels_0_fifo_pop_bytesDecr_value); - assign _zz_channels_0_pop_b2m_selfFlush = {13'd0, channels_0_fifo_pop_bytes}; - assign _zz_channels_0_pop_b2m_request = {2'd0, channels_0_pop_b2m_bytePerBurst}; - assign _zz_channels_0_pop_b2m_request_2 = (channels_0_fifo_words >>> 1'd1); - assign _zz_channels_0_pop_b2m_request_1 = {1'd0, _zz_channels_0_pop_b2m_request_2}; - assign _zz_channels_0_pop_b2m_memPending = (channels_0_pop_b2m_memPending + _zz_channels_0_pop_b2m_memPending_1); - assign _zz_channels_0_pop_b2m_memPending_2 = channels_0_pop_b2m_memPendingInc; - assign _zz_channels_0_pop_b2m_memPending_1 = {3'd0, _zz_channels_0_pop_b2m_memPending_2}; - assign _zz_channels_0_pop_b2m_memPending_4 = channels_0_pop_b2m_memRsp; - assign _zz_channels_0_pop_b2m_memPending_3 = {3'd0, _zz_channels_0_pop_b2m_memPending_4}; - assign _zz_channels_0_fifo_push_available = (channels_0_fifo_push_available + channels_0_fifo_pop_ptrIncr_value_regNext); - assign _zz_channels_1_bytesProbe_value = (channels_1_bytesProbe_value + _zz_channels_1_bytesProbe_value_1); - assign _zz_channels_1_bytesProbe_value_1 = {15'd0, channels_1_bytesProbe_incr_payload}; - assign _zz_channels_1_fifo_pop_withoutOverride_exposed = (channels_1_fifo_pop_withoutOverride_exposed + channels_1_fifo_pop_bytesIncr_value); - assign _zz_channels_1_push_m2b_memPending = (channels_1_push_m2b_memPending + _zz_channels_1_push_m2b_memPending_1); - assign _zz_channels_1_push_m2b_memPending_2 = channels_1_push_m2b_memPendingIncr; - assign _zz_channels_1_push_m2b_memPending_1 = {3'd0, _zz_channels_1_push_m2b_memPending_2}; - assign _zz_channels_1_push_m2b_memPending_4 = channels_1_push_m2b_memPendingDecr; - assign _zz_channels_1_push_m2b_memPending_3 = {3'd0, _zz_channels_1_push_m2b_memPending_4}; - assign _zz_channels_1_push_m2b_loadRequest_1 = (channels_1_push_m2b_bytePerBurst >>> 2'd3); - assign _zz_channels_1_push_m2b_loadRequest = {2'd0, _zz_channels_1_push_m2b_loadRequest_1}; - assign _zz_when_DmaSg_l486 = {14'd0, channels_1_push_m2b_bytePerBurst}; - assign _zz_channels_1_fifo_push_available = (channels_1_fifo_push_available + channels_1_fifo_pop_ptrIncr_value_regNext); - assign _zz_s2b_0_cmd_byteCount_8 = (_zz_s2b_0_cmd_byteCount_9 + _zz_s2b_0_cmd_byteCount_11); - assign _zz_s2b_0_cmd_byteCount_15 = {s2b_0_cmd_sinkHalted_payload_mask[7],s2b_0_cmd_sinkHalted_payload_mask[6]}; - assign _zz_s2b_0_cmd_byteCount_14 = {1'd0, _zz_s2b_0_cmd_byteCount_15}; - assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 - _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1); - assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2 = _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; - assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1 = {1'd0, _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2}; - assign _zz_m2b_cmd_s0_length = ((_zz_m2b_cmd_s0_length_1 < m2b_cmd_s0_bytesLeft) ? _zz_m2b_cmd_s0_length_2 : m2b_cmd_s0_bytesLeft); - assign _zz_m2b_cmd_s0_length_1 = {14'd0, m2b_cmd_s0_lengthHead}; - assign _zz_m2b_cmd_s0_length_2 = {14'd0, m2b_cmd_s0_lengthHead}; - assign _zz_m2b_cmd_s0_lastBurst = {14'd0, m2b_cmd_s0_length}; - assign _zz_m2b_cmd_s1_context_stop = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_context_stop_1); - assign _zz_m2b_cmd_s1_context_stop_1 = {20'd0, m2b_cmd_s1_length}; - assign _zz_m2b_cmd_s1_addressNext = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_addressNext_1); - assign _zz_m2b_cmd_s1_addressNext_1 = {20'd0, m2b_cmd_s1_length}; - assign _zz_m2b_cmd_s1_byteLeftNext = (m2b_cmd_s1_bytesLeft - _zz_m2b_cmd_s1_byteLeftNext_1); - assign _zz_m2b_cmd_s1_byteLeftNext_1 = {14'd0, m2b_cmd_s1_length}; - assign _zz_m2b_cmd_s1_fifoPushDecr = ({1'b0,(_zz_m2b_cmd_s1_fifoPushDecr_1 | 12'h00f)} + _zz_m2b_cmd_s1_fifoPushDecr_4); - assign _zz_m2b_cmd_s1_fifoPushDecr_1 = (_zz_m2b_cmd_s1_fifoPushDecr_2 + io_read_cmd_payload_fragment_length); - assign _zz_m2b_cmd_s1_fifoPushDecr_3 = m2b_cmd_s1_address[3 : 0]; - assign _zz_m2b_cmd_s1_fifoPushDecr_2 = {8'd0, _zz_m2b_cmd_s1_fifoPushDecr_3}; - assign _zz_m2b_cmd_s1_fifoPushDecr_5 = {1'b0,1'b1}; - assign _zz_m2b_cmd_s1_fifoPushDecr_4 = {11'd0, _zz_m2b_cmd_s1_fifoPushDecr_5}; - assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 - _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1); - assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2 = _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; - assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1 = {1'd0, _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2}; - assign _zz_when = 1'b1; - assign _zz_b2m_fsm_bytesInBurstP1_1 = {1'b0,1'b1}; - assign _zz_b2m_fsm_bytesInBurstP1 = {11'd0, _zz_b2m_fsm_bytesInBurstP1_1}; - assign _zz_b2m_fsm_addressNext = {19'd0, b2m_fsm_bytesInBurstP1}; - assign _zz_b2m_fsm_bytesLeftNext_1 = {1'b0,b2m_fsm_bytesInBurstP1}; - assign _zz_b2m_fsm_bytesLeftNext = {13'd0, _zz_b2m_fsm_bytesLeftNext_1}; - assign _zz__zz_b2m_fsm_sel_bytesInBurst_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; - assign _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; - assign _zz__zz_b2m_fsm_sel_bytesInBurst_2 = b2m_fsm_sel_address[11:0]; - assign _zz_b2m_fsm_sel_bytesInBurst_3 = ((_zz_b2m_fsm_sel_bytesInBurst_1 < _zz_b2m_fsm_sel_bytesInBurst_4) ? _zz_b2m_fsm_sel_bytesInBurst_1 : _zz_b2m_fsm_sel_bytesInBurst_5); - assign _zz_b2m_fsm_sel_bytesInBurst_4 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; - assign _zz_b2m_fsm_sel_bytesInBurst_5 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; - assign _zz_b2m_fsm_fifoCompletion = {2'd0, b2m_fsm_sel_bytesInBurst}; - assign _zz_b2m_fsm_fifoCompletion_1 = (b2m_fsm_sel_bytesInFifo - 14'h0001); - assign _zz_b2m_fsm_beatCounter = (_zz_b2m_fsm_beatCounter_1 + b2m_fsm_sel_bytesInBurst); - assign _zz_b2m_fsm_beatCounter_2 = b2m_fsm_sel_address[3 : 0]; - assign _zz_b2m_fsm_beatCounter_1 = {8'd0, _zz_b2m_fsm_beatCounter_2}; - assign _zz_b2m_fsm_sel_ptr = (b2m_fsm_sel_ptr + 11'h002); - assign _zz_b2m_fsm_cmd_maskLastTriggerComb = b2m_fsm_sel_bytesInBurst[3:0]; - assign _zz_when_1 = 1'b1; - assign _zz_when_2 = 1'b1; - assign _zz__zz_ll_arbiter_head_1 = (_zz_ll_arbiter_head & (~ _zz__zz_ll_arbiter_head_1_1)); - assign _zz__zz_ll_arbiter_head_1_1 = (_zz_ll_arbiter_head - 2'b01); - assign _zz_ll_arbiter_head_2 = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_isJustASink = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_doDescriptorStall = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_onSgStream = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_cmd_ptr = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_cmd_ptrNext = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_ll_cmd_endOfPacket = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; - assign _zz_channels_0_channelStart = 1'b1; - assign _zz_channels_0_ctrl_kick = 1'b1; - assign _zz_channels_0_channelStart_1 = 1'b1; - assign _zz_channels_0_ll_sgStart = 1'b1; - assign _zz_channels_0_interrupts_completion_valid = 1'b0; - assign _zz_channels_0_interrupts_onChannelCompletion_valid = 1'b0; - assign _zz_channels_0_interrupts_onLinkedListUpdate_valid = 1'b0; - assign _zz_channels_0_interrupts_s2mPacket_valid = 1'b0; - assign _zz_channels_1_channelStart = 1'b1; - assign _zz_channels_1_ctrl_kick = 1'b1; - assign _zz_channels_1_channelStart_1 = 1'b1; - assign _zz_channels_1_ll_sgStart = 1'b1; - assign _zz_channels_1_interrupts_completion_valid = 1'b0; - assign _zz_channels_1_interrupts_onChannelCompletion_valid = 1'b0; - assign _zz_channels_1_interrupts_onLinkedListUpdate_valid = 1'b0; - assign _zz_io_ctrl_PRDATA = channels_0_ll_ptr; - assign _zz_io_ctrl_PRDATA_1 = channels_1_ll_ptr; - assign _zz_channels_0_fifo_push_ptrIncr_value_1 = ((when_DmaSg_l665 && (|s2b_0_cmd_sinkHalted_payload_mask)) ? 1'b1 : 1'b0); - assign _zz_channels_0_fifo_push_ptrIncr_value = {10'd0, _zz_channels_0_fifo_push_ptrIncr_value_1}; - assign _zz_channels_0_fifo_pop_bytesIncr_value_2 = (_zz_channels_0_fifo_pop_bytesIncr_value ? s2b_0_rsp_context_bytes : 4'b0000); - assign _zz_channels_0_fifo_pop_bytesIncr_value_1 = {10'd0, _zz_channels_0_fifo_pop_bytesIncr_value_2}; - assign _zz_channels_0_fifo_pop_ptrIncr_value_1 = ((b2m_fsm_cmd_doPtrIncr && 1'b1) ? 2'b10 : 2'b00); - assign _zz_channels_0_fifo_pop_ptrIncr_value = {9'd0, _zz_channels_0_fifo_pop_ptrIncr_value_1}; - assign _zz_channels_1_fifo_push_ptrIncr_value_2 = (_zz_channels_1_fifo_push_ptrIncr_value ? 2'b10 : 2'b00); - assign _zz_channels_1_fifo_push_ptrIncr_value_1 = {9'd0, _zz_channels_1_fifo_push_ptrIncr_value_2}; - assign _zz_channels_1_fifo_pop_bytesIncr_value_2 = (_zz_channels_1_fifo_pop_bytesIncr_value ? _zz_channels_1_fifo_pop_bytesIncr_value_3 : 5'h0); - assign _zz_channels_1_fifo_pop_bytesIncr_value_1 = {9'd0, _zz_channels_1_fifo_pop_bytesIncr_value_2}; - assign _zz_channels_1_fifo_pop_bytesIncr_value_3 = (m2b_writeRsp_context_loadByteInNextBeat + 5'h01); - assign _zz_channels_1_fifo_pop_ptrIncr_value_1 = ((b2s_0_cmd_channelsOh[0] && memory_core_io_reads_0_cmd_ready) ? 1'b1 : 1'b0); - assign _zz_channels_1_fifo_pop_ptrIncr_value = {10'd0, _zz_channels_1_fifo_pop_ptrIncr_value_1}; - assign _zz_s2b_0_cmd_byteCount_10 = {s2b_0_cmd_sinkHalted_payload_mask[2],{s2b_0_cmd_sinkHalted_payload_mask[1],s2b_0_cmd_sinkHalted_payload_mask[0]}}; - assign _zz_s2b_0_cmd_byteCount_12 = {s2b_0_cmd_sinkHalted_payload_mask[5],{s2b_0_cmd_sinkHalted_payload_mask[4],s2b_0_cmd_sinkHalted_payload_mask[3]}}; - assign _zz_s2b_0_cmd_firsts = io_inputs_0_payload_last_regNextWhen_5; - assign _zz_s2b_0_cmd_firsts_1 = {io_inputs_0_payload_last_regNextWhen_4,{io_inputs_0_payload_last_regNextWhen_3,{io_inputs_0_payload_last_regNextWhen_2,{io_inputs_0_payload_last_regNextWhen_1,io_inputs_0_payload_last_regNextWhen}}}}; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask = 4'b1101; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_1 = (! b2m_fsm_aggregate_first); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_2 = (b2m_fsm_aggregate_bytesToSkip <= 4'b1100); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_3 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1011)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_4 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1010)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_5 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1001)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1000)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask_6)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_7 || _zz_b2m_fsm_aggregate_bytesToSkipMask_8),{_zz_b2m_fsm_aggregate_bytesToSkipMask_9,{_zz_b2m_fsm_aggregate_bytesToSkipMask_10,_zz_b2m_fsm_aggregate_bytesToSkipMask_11}}}}}}; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_6 = 4'b0111; - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_7 = (! b2m_fsm_aggregate_first); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_8 = (b2m_fsm_aggregate_bytesToSkip <= 4'b0110); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_9 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0101)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_10 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0100)); - assign _zz_b2m_fsm_aggregate_bytesToSkipMask_11 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0011)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0010)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0001)),((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0000))}}}; - assign _zz_b2m_fsm_cmd_maskLast = 4'b1010; - assign _zz_b2m_fsm_cmd_maskLast_1 = (4'b1001 <= b2m_fsm_cmd_maskLastTriggerComb); - assign _zz_b2m_fsm_cmd_maskLast_2 = (4'b1000 <= b2m_fsm_cmd_maskLastTriggerComb); - assign _zz_b2m_fsm_cmd_maskLast_3 = {(4'b0111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0011 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0010 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast_4 <= b2m_fsm_cmd_maskLastTriggerComb),(_zz_b2m_fsm_cmd_maskLast_5 <= b2m_fsm_cmd_maskLastTriggerComb)}}}}}}}; - assign _zz_b2m_fsm_cmd_maskLast_4 = 4'b0001; - assign _zz_b2m_fsm_cmd_maskLast_5 = 4'b0000; - assign _zz_b2m_fsm_cmd_maskFirst = 4'b1010; - assign _zz_b2m_fsm_cmd_maskFirst_1 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1001); - assign _zz_b2m_fsm_cmd_maskFirst_2 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1000); - assign _zz_b2m_fsm_cmd_maskFirst_3 = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b0111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0011),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0010),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_4),(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_5)}}}}}}}; - assign _zz_b2m_fsm_cmd_maskFirst_4 = 4'b0001; - assign _zz_b2m_fsm_cmd_maskFirst_5 = 4'b0000; - EfxDMA_DmaMemoryCore memory_core ( - .io_writes_0_cmd_valid (s2b_0_cmd_sinkHalted_valid ), //i - .io_writes_0_cmd_ready (memory_core_io_writes_0_cmd_ready ), //o - .io_writes_0_cmd_payload_address (memory_core_io_writes_0_cmd_payload_address[9:0]), //i - .io_writes_0_cmd_payload_data (s2b_0_cmd_sinkHalted_payload_data[63:0] ), //i - .io_writes_0_cmd_payload_mask (s2b_0_cmd_sinkHalted_payload_mask[7:0] ), //i - .io_writes_0_cmd_payload_priority (channels_0_priority[1:0] ), //i - .io_writes_0_cmd_payload_context (memory_core_io_writes_0_cmd_payload_context[6:0]), //i - .io_writes_0_rsp_valid (memory_core_io_writes_0_rsp_valid ), //o - .io_writes_0_rsp_payload_context (memory_core_io_writes_0_rsp_payload_context[6:0]), //o - .io_writes_1_cmd_valid (io_read_rsp_valid ), //i - .io_writes_1_cmd_ready (memory_core_io_writes_1_cmd_ready ), //o - .io_writes_1_cmd_payload_address (memory_core_io_writes_1_cmd_payload_address[9:0]), //i - .io_writes_1_cmd_payload_data (io_read_rsp_payload_fragment_data[127:0] ), //i - .io_writes_1_cmd_payload_mask (memory_core_io_writes_1_cmd_payload_mask[15:0] ), //i - .io_writes_1_cmd_payload_context (memory_core_io_writes_1_cmd_payload_context[6:0]), //i - .io_writes_1_rsp_valid (memory_core_io_writes_1_rsp_valid ), //o - .io_writes_1_rsp_payload_context (memory_core_io_writes_1_rsp_payload_context[6:0]), //o - .io_reads_0_cmd_valid (memory_core_io_reads_0_cmd_valid ), //i - .io_reads_0_cmd_ready (memory_core_io_reads_0_cmd_ready ), //o - .io_reads_0_cmd_payload_address (memory_core_io_reads_0_cmd_payload_address[9:0] ), //i - .io_reads_0_cmd_payload_priority (channels_1_priority[1:0] ), //i - .io_reads_0_cmd_payload_context (memory_core_io_reads_0_cmd_payload_context[2:0] ), //i - .io_reads_0_rsp_valid (memory_core_io_reads_0_rsp_valid ), //o - .io_reads_0_rsp_ready (io_outputs_0_ready ), //i - .io_reads_0_rsp_payload_data (memory_core_io_reads_0_rsp_payload_data[63:0] ), //o - .io_reads_0_rsp_payload_mask (memory_core_io_reads_0_rsp_payload_mask[7:0] ), //o - .io_reads_0_rsp_payload_context (memory_core_io_reads_0_rsp_payload_context[2:0] ), //o - .io_reads_1_cmd_valid (b2m_fsm_sel_valid ), //i - .io_reads_1_cmd_ready (memory_core_io_reads_1_cmd_ready ), //o - .io_reads_1_cmd_payload_address (memory_core_io_reads_1_cmd_payload_address[9:0] ), //i - .io_reads_1_cmd_payload_context (memory_core_io_reads_1_cmd_payload_context[11:0]), //i - .io_reads_1_rsp_valid (memory_core_io_reads_1_rsp_valid ), //o - .io_reads_1_rsp_ready (memory_core_io_reads_1_rsp_rValidN ), //i - .io_reads_1_rsp_payload_data (memory_core_io_reads_1_rsp_payload_data[127:0] ), //o - .io_reads_1_rsp_payload_mask (memory_core_io_reads_1_rsp_payload_mask[15:0] ), //o - .io_reads_1_rsp_payload_context (memory_core_io_reads_1_rsp_payload_context[11:0]), //o - .clk (clk ), //i - .reset (reset ) //i - ); - EfxDMA_Aggregator b2m_fsm_aggregate_engine ( - .io_input_valid (b2m_fsm_aggregate_memoryPort_valid ), //i - .io_input_ready (b2m_fsm_aggregate_engine_io_input_ready ), //o - .io_input_payload_data (b2m_fsm_aggregate_memoryPort_payload_data[127:0] ), //i - .io_input_payload_mask (b2m_fsm_aggregate_engine_io_input_payload_mask[15:0]), //i - .io_output_data (b2m_fsm_aggregate_engine_io_output_data[127:0] ), //o - .io_output_mask (b2m_fsm_aggregate_engine_io_output_mask[15:0] ), //o - .io_output_enough (b2m_fsm_cmd_enoughAggregation ), //i - .io_output_consume (io_write_cmd_fire ), //i - .io_output_consumed (b2m_fsm_aggregate_engine_io_output_consumed ), //o - .io_output_lastByteUsed (b2m_fsm_cmd_maskLastTriggerReg[3:0] ), //i - .io_output_usedUntil (b2m_fsm_aggregate_engine_io_output_usedUntil[3:0] ), //o - .io_flush (b2m_fsm_aggregate_engine_io_flush ), //i - .io_offset (b2m_fsm_aggregate_engine_io_offset[3:0] ), //i - .io_burstLength (b2m_fsm_sel_bytesInBurst[11:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(_zz_s2b_0_cmd_byteCount_10) - 3'b000 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount; - 3'b001 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_1; - 3'b010 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_2; - 3'b011 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_3; - 3'b100 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_4; - 3'b101 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_5; - 3'b110 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_6; - default : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_7; - endcase - end - - always @(*) begin - case(_zz_s2b_0_cmd_byteCount_12) - 3'b000 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount; - 3'b001 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_1; - 3'b010 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_2; - 3'b011 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_3; - 3'b100 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_4; - 3'b101 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_5; - 3'b110 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_6; - default : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_7; - endcase - end - - always @(*) begin - case(_zz_s2b_0_cmd_byteCount_14) - 3'b000 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount; - 3'b001 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_1; - 3'b010 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_2; - 3'b011 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_3; - 3'b100 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_4; - 3'b101 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_5; - 3'b110 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_6; - default : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_7; - endcase - end - - always @(*) begin - case(_zz_m2b_cmd_s0_priority_masked) - 2'b00 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_0; - 2'b01 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_1; - 2'b10 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_2; - default : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_3; - endcase - end - - always @(*) begin - case(_zz_b2m_fsm_arbiter_logic_priority_masked) - 2'b00 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_0; - 2'b01 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_1; - 2'b10 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_2; - default : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_3; - endcase - end - - assign ctrl_readErrorFlag = 1'b0; - assign ctrl_writeErrorFlag = 1'b0; - assign io_ctrl_PREADY = 1'b1; - always @(*) begin - io_ctrl_PRDATA = 32'h0; - case(io_ctrl_PADDR) - 14'h002c : begin - io_ctrl_PRDATA[0 : 0] = channels_0_channelValid; - end - 14'h0054 : begin - io_ctrl_PRDATA[0 : 0] = channels_0_interrupts_completion_valid; - io_ctrl_PRDATA[2 : 2] = channels_0_interrupts_onChannelCompletion_valid; - io_ctrl_PRDATA[3 : 3] = channels_0_interrupts_onLinkedListUpdate_valid; - io_ctrl_PRDATA[4 : 4] = channels_0_interrupts_s2mPacket_valid; - end - 14'h0060 : begin - io_ctrl_PRDATA[26 : 0] = channels_0_bytesProbe_value; - end - 14'h00ac : begin - io_ctrl_PRDATA[0 : 0] = channels_1_channelValid; - end - 14'h00d4 : begin - io_ctrl_PRDATA[0 : 0] = channels_1_interrupts_completion_valid; - io_ctrl_PRDATA[2 : 2] = channels_1_interrupts_onChannelCompletion_valid; - io_ctrl_PRDATA[3 : 3] = channels_1_interrupts_onLinkedListUpdate_valid; - end - 14'h00e0 : begin - io_ctrl_PRDATA[26 : 0] = channels_1_bytesProbe_value; - end - default : begin - end - endcase - if(when_Apb3SlaveFactory_l81_1) begin - io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA[31 : 0]; - end - if(when_Apb3SlaveFactory_l81_3) begin - io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA_1[31 : 0]; - end - end - - assign ctrl_askWrite = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PWRITE); - assign ctrl_askRead = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && (! io_ctrl_PWRITE)); - assign ctrl_doWrite = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && io_ctrl_PWRITE); - assign ctrl_doRead = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && (! io_ctrl_PWRITE)); - assign io_ctrl_PSLVERROR = ((ctrl_doWrite && ctrl_writeErrorFlag) || (ctrl_doRead && ctrl_readErrorFlag)); - always @(*) begin - channels_0_channelStart = 1'b0; - if(when_BusSlaveFactory_l377) begin - if(when_BusSlaveFactory_l379) begin - channels_0_channelStart = _zz_channels_0_channelStart[0]; - end - end - if(when_BusSlaveFactory_l377_2) begin - if(when_BusSlaveFactory_l379_2) begin - channels_0_channelStart = _zz_channels_0_channelStart_1[0]; - end - end - end - - always @(*) begin - channels_0_channelCompletion = 1'b0; - if(channels_0_channelValid) begin - if(channels_0_channelStop) begin - if(channels_0_readyToStop) begin - channels_0_channelCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_0_descriptorStart = 1'b0; - if(channels_0_ctrl_kick) begin - channels_0_descriptorStart = 1'b1; - end - if(when_DmaSg_l318) begin - if(when_DmaSg_l320) begin - if(when_DmaSg_l322) begin - channels_0_descriptorStart = 1'b1; - end - end - end - end - - always @(*) begin - channels_0_descriptorCompletion = 1'b0; - if(channels_0_pop_b2m_packetSync) begin - if(when_DmaSg_l532) begin - if(channels_0_push_s2b_completionOnLast) begin - channels_0_descriptorCompletion = 1'b1; - end - end - end - if(when_DmaSg_l547) begin - channels_0_descriptorCompletion = 1'b1; - end - if(channels_0_channelValid) begin - if(channels_0_channelStop) begin - if(channels_0_readyToStop) begin - channels_0_descriptorCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_0_readyToStop = 1'b1; - if(channels_0_ll_waitDone) begin - channels_0_readyToStop = 1'b0; - end - if(when_DmaSg_l563) begin - channels_0_readyToStop = 1'b0; - end - end - - always @(*) begin - channels_0_bytesProbe_incr_valid = 1'b0; - if(io_write_rsp_fire) begin - if(when_DmaSg_l1116) begin - channels_0_bytesProbe_incr_valid = 1'b1; - end - end - end - - always @(*) begin - channels_0_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; - if(io_write_rsp_fire) begin - if(when_DmaSg_l1116) begin - channels_0_bytesProbe_incr_payload = b2m_rsp_context_length; - end - end - end - - always @(*) begin - channels_0_ll_sgStart = 1'b0; - if(when_BusSlaveFactory_l377_3) begin - if(when_BusSlaveFactory_l379_3) begin - channels_0_ll_sgStart = _zz_channels_0_ll_sgStart[0]; - end - end - end - - assign channels_0_ll_requestLl = ((((channels_0_channelValid && channels_0_ll_valid) && (! channels_0_channelStop)) && (! channels_0_ll_waitDone)) && ((! channels_0_descriptorValid) || channels_0_ll_requireSync)); - always @(*) begin - channels_0_ll_descriptorUpdated = 1'b0; - if(when_DmaSg_l318) begin - if(when_DmaSg_l328) begin - channels_0_ll_descriptorUpdated = 1'b1; - end - end - end - - assign when_DmaSg_l318 = (((channels_0_ll_valid && channels_0_ll_waitDone) && channels_0_ll_writeDone) && channels_0_ll_readDone); - assign when_DmaSg_l320 = (! channels_0_ll_justASync); - assign when_DmaSg_l322 = (! channels_0_ll_gotDescriptorStall); - assign when_DmaSg_l328 = (! channels_0_ll_head); - assign channels_0_fifo_base = 11'h0; - assign channels_0_fifo_words = 11'h1ff; - assign channels_0_fifo_push_availableDecr = 11'h0; - assign channels_0_fifo_push_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_push_ptr & channels_0_fifo_words)); - assign channels_0_fifo_pop_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_pop_ptr & channels_0_fifo_words)); - assign channels_0_fifo_pop_empty = (channels_0_fifo_pop_ptr == channels_0_fifo_push_ptr); - assign channels_0_fifo_pop_withOverride_backupNext = (_zz_channels_0_fifo_pop_withOverride_backupNext - channels_0_fifo_pop_bytesDecr_value); - always @(*) begin - channels_0_fifo_pop_withOverride_load = 1'b0; - if(when_DmaSg_l457) begin - channels_0_fifo_pop_withOverride_load = 1'b1; - end - end - - always @(*) begin - channels_0_fifo_pop_withOverride_unload = 1'b0; - if(channels_0_pop_b2m_packetSync) begin - channels_0_fifo_pop_withOverride_unload = 1'b1; - end - end - - assign when_DmaSg_l409 = (channels_0_channelStart || channels_0_fifo_pop_withOverride_unload); - assign channels_0_fifo_pop_bytes = channels_0_fifo_pop_withOverride_exposed; - assign channels_0_fifo_empty = (channels_0_fifo_push_ptr == channels_0_fifo_pop_ptr); - always @(*) begin - channels_0_push_s2b_packetEvent = 1'b0; - if(when_DmaSg_l679) begin - channels_0_push_s2b_packetEvent = 1'b1; - end - end - - assign when_DmaSg_l457 = (channels_0_push_s2b_packetEvent && channels_0_push_s2b_completionOnLast); - assign channels_0_pop_b2m_bytePerBurst = 12'h3ff; - always @(*) begin - channels_0_pop_b2m_fire = 1'b0; - if(when_DmaSg_l935) begin - if(_zz_when[0]) begin - channels_0_pop_b2m_fire = 1'b1; - end - end - end - - always @(*) begin - channels_0_pop_b2m_packetSync = 1'b0; - if(when_DmaSg_l523) begin - if(channels_0_pop_b2m_packet) begin - channels_0_pop_b2m_packetSync = 1'b1; - end - end - if(io_write_rsp_fire) begin - if(when_DmaSg_l1116) begin - if(b2m_rsp_context_doPacketSync) begin - channels_0_pop_b2m_packetSync = 1'b1; - end - end - end - end - - assign when_DmaSg_l505 = (channels_0_channelStart || channels_0_pop_b2m_fire); - always @(*) begin - channels_0_pop_b2m_memRsp = 1'b0; - if(io_write_rsp_fire) begin - if(_zz_when_2[0]) begin - channels_0_pop_b2m_memRsp = 1'b1; - end - end - end - - assign channels_0_pop_b2m_selfFlush = (channels_0_pop_b2m_bytesLeft < _zz_channels_0_pop_b2m_selfFlush); - assign channels_0_pop_b2m_request = ((((((channels_0_descriptorValid && (! channels_0_channelStop)) && (! channels_0_pop_b2m_waitFinalRsp)) && channels_0_pop_memory) && ((_zz_channels_0_pop_b2m_request < channels_0_fifo_pop_bytes) || (((channels_0_fifo_push_available < _zz_channels_0_pop_b2m_request_1) || channels_0_pop_b2m_flush) || channels_0_pop_b2m_selfFlush))) && (channels_0_fifo_pop_bytes != 14'h0)) && (channels_0_pop_b2m_memPending != 4'b1111)); - always @(*) begin - channels_0_pop_b2m_memPendingInc = 1'b0; - if(when_DmaSg_l758_1) begin - if(when_DmaSg_l773_1) begin - channels_0_pop_b2m_memPendingInc = 1'b1; - end - end - end - - always @(*) begin - channels_0_pop_b2m_decrBytes = 14'h0; - if(b2m_fsm_s1) begin - if(when_DmaSg_l996) begin - channels_0_pop_b2m_decrBytes = {1'd0, b2m_fsm_bytesInBurstP1}; - end - end - end - - assign when_DmaSg_l523 = ((channels_0_pop_b2m_memPending == 4'b0000) && (channels_0_fifo_pop_bytes == 14'h0)); - assign when_DmaSg_l532 = (channels_0_descriptorValid && (! channels_0_push_memory)); - assign when_DmaSg_l536 = (! channels_0_pop_b2m_waitFinalRsp); - assign when_DmaSg_l547 = ((channels_0_descriptorValid && (channels_0_pop_b2m_memPending == 4'b0000)) && channels_0_pop_b2m_waitFinalRsp); - assign when_DmaSg_l563 = (channels_0_pop_b2m_memPending != 4'b0000); - assign channels_0_readyForChannelCompletion = 1'b1; - assign when_DmaSg_l575 = (! channels_0_descriptorValid); - always @(*) begin - _zz_when_DmaSg_l593 = 1'b1; - if(channels_0_ctrl_kick) begin - _zz_when_DmaSg_l593 = 1'b0; - end - if(channels_0_ll_valid) begin - _zz_when_DmaSg_l593 = 1'b0; - end - end - - assign when_DmaSg_l593 = (_zz_when_DmaSg_l593 && channels_0_readyForChannelCompletion); - assign channels_0_s2b_full = (channels_0_fifo_push_available < 11'h002); - assign when_DmaSg_l255 = (channels_0_descriptorValid && channels_0_descriptorCompletion); - assign when_DmaSg_l255_1 = (! channels_0_interrupts_completion_enable); - assign when_DmaSg_l255_2 = (channels_0_channelValid && channels_0_channelCompletion); - assign when_DmaSg_l255_3 = (! channels_0_interrupts_onChannelCompletion_enable); - assign when_DmaSg_l255_4 = (! channels_0_interrupts_onLinkedListUpdate_enable); - assign when_DmaSg_l255_5 = (! channels_0_interrupts_s2mPacket_enable); - assign when_DmaSg_l625 = (channels_0_channelStart || channels_0_descriptorStart); - always @(*) begin - channels_1_channelStart = 1'b0; - if(when_BusSlaveFactory_l377_4) begin - if(when_BusSlaveFactory_l379_4) begin - channels_1_channelStart = _zz_channels_1_channelStart[0]; - end - end - if(when_BusSlaveFactory_l377_6) begin - if(when_BusSlaveFactory_l379_6) begin - channels_1_channelStart = _zz_channels_1_channelStart_1[0]; - end - end - end - - always @(*) begin - channels_1_channelCompletion = 1'b0; - if(channels_1_channelValid) begin - if(channels_1_channelStop) begin - if(channels_1_readyToStop) begin - channels_1_channelCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_1_descriptorStart = 1'b0; - if(channels_1_ctrl_kick) begin - channels_1_descriptorStart = 1'b1; - end - if(when_DmaSg_l318_1) begin - if(when_DmaSg_l320_1) begin - if(when_DmaSg_l322_1) begin - channels_1_descriptorStart = 1'b1; - end - end - end - end - - always @(*) begin - channels_1_descriptorCompletion = 1'b0; - if(when_DmaSg_l483) begin - channels_1_descriptorCompletion = 1'b1; - end - if(channels_1_channelValid) begin - if(channels_1_channelStop) begin - if(channels_1_readyToStop) begin - channels_1_descriptorCompletion = 1'b1; - end - end - end - end - - always @(*) begin - channels_1_readyToStop = 1'b1; - if(channels_1_ll_waitDone) begin - channels_1_readyToStop = 1'b0; - end - if(when_DmaSg_l562) begin - channels_1_readyToStop = 1'b0; - end - end - - always @(*) begin - channels_1_bytesProbe_incr_valid = 1'b0; - if(when_DmaSg_l874) begin - channels_1_bytesProbe_incr_valid = 1'b1; - end - end - - always @(*) begin - channels_1_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; - if(when_DmaSg_l874) begin - channels_1_bytesProbe_incr_payload = m2b_rsp_context_length; - end - end - - always @(*) begin - channels_1_ll_sgStart = 1'b0; - if(when_BusSlaveFactory_l377_7) begin - if(when_BusSlaveFactory_l379_7) begin - channels_1_ll_sgStart = _zz_channels_1_ll_sgStart[0]; - end - end - end - - assign channels_1_ll_requestLl = ((((channels_1_channelValid && channels_1_ll_valid) && (! channels_1_channelStop)) && (! channels_1_ll_waitDone)) && ((! channels_1_descriptorValid) || channels_1_ll_requireSync)); - always @(*) begin - channels_1_ll_descriptorUpdated = 1'b0; - if(when_DmaSg_l318_1) begin - if(when_DmaSg_l328_1) begin - channels_1_ll_descriptorUpdated = 1'b1; - end - end - end - - assign when_DmaSg_l318_1 = (((channels_1_ll_valid && channels_1_ll_waitDone) && channels_1_ll_writeDone) && channels_1_ll_readDone); - assign when_DmaSg_l320_1 = (! channels_1_ll_justASync); - assign when_DmaSg_l322_1 = (! channels_1_ll_gotDescriptorStall); - assign when_DmaSg_l328_1 = (! channels_1_ll_head); - assign channels_1_fifo_base = 11'h200; - assign channels_1_fifo_words = 11'h1ff; - always @(*) begin - channels_1_fifo_push_availableDecr = 11'h0; - if(m2b_cmd_s1_valid) begin - if(io_read_cmd_ready) begin - if(when_DmaSg_l828) begin - channels_1_fifo_push_availableDecr = {1'd0, m2b_cmd_s1_fifoPushDecr}; - end - end - end - end - - assign channels_1_fifo_push_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_push_ptr & channels_1_fifo_words)); - assign channels_1_fifo_pop_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_pop_ptr & channels_1_fifo_words)); - assign channels_1_fifo_pop_empty = (channels_1_fifo_pop_ptr == channels_1_fifo_push_ptr); - assign channels_1_fifo_pop_bytes = channels_1_fifo_pop_withoutOverride_exposed; - assign channels_1_fifo_empty = (channels_1_fifo_push_ptr == channels_1_fifo_pop_ptr); - assign channels_1_push_m2b_bytePerBurst = 12'h3ff; - always @(*) begin - channels_1_push_m2b_memPendingIncr = 1'b0; - if(when_DmaSg_l758) begin - if(when_DmaSg_l773) begin - channels_1_push_m2b_memPendingIncr = 1'b1; - end - end - end - - always @(*) begin - channels_1_push_m2b_memPendingDecr = 1'b0; - if(when_DmaSg_l893) begin - channels_1_push_m2b_memPendingDecr = 1'b1; - end - end - - always @(*) begin - channels_1_push_m2b_loadRequest = (((((channels_1_descriptorValid && (! channels_1_channelStop)) && (! channels_1_push_m2b_loadDone)) && channels_1_push_memory) && (_zz_channels_1_push_m2b_loadRequest < channels_1_fifo_push_available)) && (channels_1_push_m2b_memPending != 4'b1111)); - if(when_DmaSg_l486) begin - channels_1_push_m2b_loadRequest = 1'b0; - end - end - - always @(*) begin - channels_1_pop_b2s_veryLastTrigger = 1'b0; - if(when_DmaSg_l847) begin - if(when_DmaSg_l848) begin - channels_1_pop_b2s_veryLastTrigger = 1'b1; - end - end - end - - assign when_DmaSg_l474 = (channels_1_pop_b2s_veryLastTrigger && channels_1_pop_b2s_last); - assign when_DmaSg_l483 = ((((channels_1_descriptorValid && (! channels_1_pop_memory)) && channels_1_push_memory) && channels_1_push_m2b_loadDone) && (channels_1_push_m2b_memPending == 4'b0000)); - assign when_DmaSg_l486 = (((! channels_1_pop_memory) && channels_1_pop_b2s_veryLastValid) && (channels_1_push_m2b_bytesLeft <= _zz_when_DmaSg_l486)); - assign when_DmaSg_l562 = (channels_1_push_m2b_memPending != 4'b0000); - always @(*) begin - channels_1_readyForChannelCompletion = 1'b1; - if(when_DmaSg_l566) begin - channels_1_readyForChannelCompletion = 1'b0; - end - end - - assign when_DmaSg_l566 = ((! channels_1_pop_memory) && (! channels_1_fifo_pop_empty)); - assign when_DmaSg_l575_1 = (! channels_1_descriptorValid); - always @(*) begin - _zz_when_DmaSg_l593_1 = 1'b1; - if(channels_1_ctrl_kick) begin - _zz_when_DmaSg_l593_1 = 1'b0; - end - if(channels_1_ll_valid) begin - _zz_when_DmaSg_l593_1 = 1'b0; - end - end - - assign when_DmaSg_l593_1 = (_zz_when_DmaSg_l593_1 && channels_1_readyForChannelCompletion); - assign channels_1_s2b_full = (channels_1_fifo_push_available < 11'h002); - assign when_DmaSg_l255_6 = (channels_1_descriptorValid && channels_1_descriptorCompletion); - assign when_DmaSg_l255_7 = (! channels_1_interrupts_completion_enable); - assign when_DmaSg_l255_8 = (channels_1_channelValid && channels_1_channelCompletion); - assign when_DmaSg_l255_9 = (! channels_1_interrupts_onChannelCompletion_enable); - assign when_DmaSg_l255_10 = (! channels_1_interrupts_onLinkedListUpdate_enable); - assign when_DmaSg_l625_1 = (channels_1_channelStart || channels_1_descriptorStart); - assign io_inputs_0_fire = (io_inputs_0_valid && io_inputs_0_ready); - assign when_package_l12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0000)); - assign when_package_l12_1 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0001)); - assign when_package_l12_2 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0010)); - assign when_package_l12_3 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0011)); - assign when_package_l12_4 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0100)); - assign when_package_l12_5 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0101)); - assign when_package_l12_6 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0110)); - assign when_package_l12_7 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0111)); - assign when_package_l12_8 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1000)); - assign when_package_l12_9 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1001)); - assign when_package_l12_10 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1010)); - assign when_package_l12_11 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1011)); - assign when_package_l12_12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1100)); - assign when_package_l12_13 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1101)); - assign when_package_l12_14 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1110)); - assign when_package_l12_15 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1111)); - assign s2b_0_cmd_firsts = {io_inputs_0_payload_last_regNextWhen_15,{io_inputs_0_payload_last_regNextWhen_14,{io_inputs_0_payload_last_regNextWhen_13,{io_inputs_0_payload_last_regNextWhen_12,{io_inputs_0_payload_last_regNextWhen_11,{io_inputs_0_payload_last_regNextWhen_10,{io_inputs_0_payload_last_regNextWhen_9,{io_inputs_0_payload_last_regNextWhen_8,{io_inputs_0_payload_last_regNextWhen_7,{io_inputs_0_payload_last_regNextWhen_6,{_zz_s2b_0_cmd_firsts,_zz_s2b_0_cmd_firsts_1}}}}}}}}}}}; - assign s2b_0_cmd_first = s2b_0_cmd_firsts[io_inputs_0_payload_sink]; - assign s2b_0_cmd_channelsOh = ((((channels_0_channelValid && (s2b_0_cmd_first || (! channels_0_push_s2b_waitFirst))) && (! channels_0_push_memory)) && 1'b1) && (io_inputs_0_payload_sink == 4'b0000)); - assign s2b_0_cmd_noHit = (! (|s2b_0_cmd_channelsOh)); - assign s2b_0_cmd_channelsFull = (channels_0_s2b_full || (channels_0_push_s2b_packetLock && io_inputs_0_payload_last)); - always @(*) begin - io_inputs_0_thrown_valid = io_inputs_0_valid; - if(s2b_0_cmd_noHit) begin - io_inputs_0_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_inputs_0_ready = io_inputs_0_thrown_ready; - if(s2b_0_cmd_noHit) begin - io_inputs_0_ready = 1'b1; - end - end - - assign io_inputs_0_thrown_payload_data = io_inputs_0_payload_data; - assign io_inputs_0_thrown_payload_mask = io_inputs_0_payload_mask; - assign io_inputs_0_thrown_payload_sink = io_inputs_0_payload_sink; - assign io_inputs_0_thrown_payload_last = io_inputs_0_payload_last; - assign _zz_io_inputs_0_thrown_ready = (! (|(s2b_0_cmd_channelsOh & s2b_0_cmd_channelsFull))); - assign s2b_0_cmd_sinkHalted_valid = (io_inputs_0_thrown_valid && _zz_io_inputs_0_thrown_ready); - assign io_inputs_0_thrown_ready = (s2b_0_cmd_sinkHalted_ready && _zz_io_inputs_0_thrown_ready); - assign s2b_0_cmd_sinkHalted_payload_data = io_inputs_0_thrown_payload_data; - assign s2b_0_cmd_sinkHalted_payload_mask = io_inputs_0_thrown_payload_mask; - assign s2b_0_cmd_sinkHalted_payload_sink = io_inputs_0_thrown_payload_sink; - assign s2b_0_cmd_sinkHalted_payload_last = io_inputs_0_thrown_payload_last; - assign _zz_s2b_0_cmd_byteCount = 4'b0000; - assign _zz_s2b_0_cmd_byteCount_1 = 4'b0001; - assign _zz_s2b_0_cmd_byteCount_2 = 4'b0001; - assign _zz_s2b_0_cmd_byteCount_3 = 4'b0010; - assign _zz_s2b_0_cmd_byteCount_4 = 4'b0001; - assign _zz_s2b_0_cmd_byteCount_5 = 4'b0010; - assign _zz_s2b_0_cmd_byteCount_6 = 4'b0010; - assign _zz_s2b_0_cmd_byteCount_7 = 4'b0011; - assign s2b_0_cmd_byteCount = (_zz_s2b_0_cmd_byteCount_8 + _zz_s2b_0_cmd_byteCount_13); - assign s2b_0_cmd_context_channel = s2b_0_cmd_channelsOh; - assign s2b_0_cmd_context_bytes = s2b_0_cmd_byteCount; - assign s2b_0_cmd_context_flush = io_inputs_0_payload_last; - assign s2b_0_cmd_context_packet = io_inputs_0_payload_last; - assign s2b_0_cmd_sinkHalted_ready = memory_core_io_writes_0_cmd_ready; - assign memory_core_io_writes_0_cmd_payload_address = channels_0_fifo_push_ptrWithBase[9:0]; - assign memory_core_io_writes_0_cmd_payload_context = {s2b_0_cmd_context_packet,{s2b_0_cmd_context_flush,{s2b_0_cmd_context_bytes,s2b_0_cmd_context_channel}}}; - assign memory_core_io_writes_0_cmd_fire = (s2b_0_cmd_sinkHalted_valid && memory_core_io_writes_0_cmd_ready); - assign when_DmaSg_l665 = (s2b_0_cmd_channelsOh[0] && memory_core_io_writes_0_cmd_fire); - assign _zz_s2b_0_rsp_context_channel = memory_core_io_writes_0_rsp_payload_context; - assign s2b_0_rsp_context_channel = _zz_s2b_0_rsp_context_channel[0 : 0]; - assign s2b_0_rsp_context_bytes = _zz_s2b_0_rsp_context_channel[4 : 1]; - assign s2b_0_rsp_context_flush = _zz_s2b_0_rsp_context_channel[5]; - assign s2b_0_rsp_context_packet = _zz_s2b_0_rsp_context_channel[6]; - assign _zz_channels_0_fifo_pop_bytesIncr_value = (memory_core_io_writes_0_rsp_valid && s2b_0_rsp_context_channel[0]); - assign when_DmaSg_l679 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); - assign when_DmaSg_l681 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_flush); - assign when_DmaSg_l682 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); - assign b2s_0_cmd_channelsOh = (((channels_1_channelValid && (! channels_1_pop_memory)) && 1'b1) && (! channels_1_fifo_pop_empty)); - assign b2s_0_cmd_veryLastPtr = channels_1_pop_b2s_veryLastPtr; - assign b2s_0_cmd_address = channels_1_fifo_pop_ptrWithBase; - assign b2s_0_cmd_context_channel = b2s_0_cmd_channelsOh; - assign b2s_0_cmd_context_veryLast = ((channels_1_pop_b2s_veryLastValid && (b2s_0_cmd_address[10 : 1] == b2s_0_cmd_veryLastPtr[10 : 1])) && (b2s_0_cmd_address[0 : 0] == 1'b1)); - assign b2s_0_cmd_context_endPacket = channels_1_pop_b2s_veryLastEndPacket; - assign memory_core_io_reads_0_cmd_valid = (|b2s_0_cmd_channelsOh); - assign memory_core_io_reads_0_cmd_payload_address = b2s_0_cmd_address[9:0]; - assign memory_core_io_reads_0_cmd_payload_context = {b2s_0_cmd_context_endPacket,{b2s_0_cmd_context_veryLast,b2s_0_cmd_context_channel}}; - assign _zz_b2s_0_rsp_context_channel = memory_core_io_reads_0_rsp_payload_context; - assign b2s_0_rsp_context_channel = _zz_b2s_0_rsp_context_channel[0 : 0]; - assign b2s_0_rsp_context_veryLast = _zz_b2s_0_rsp_context_channel[1]; - assign b2s_0_rsp_context_endPacket = _zz_b2s_0_rsp_context_channel[2]; - assign io_outputs_0_valid = memory_core_io_reads_0_rsp_valid; - assign io_outputs_0_payload_data = memory_core_io_reads_0_rsp_payload_data; - assign io_outputs_0_payload_mask = memory_core_io_reads_0_rsp_payload_mask; - assign io_outputs_0_payload_sink = channels_1_pop_b2s_sinkId; - assign io_outputs_0_payload_last = (b2s_0_rsp_context_veryLast && b2s_0_rsp_context_endPacket); - assign io_outputs_0_fire = (io_outputs_0_valid && io_outputs_0_ready); - assign when_DmaSg_l725 = (io_outputs_0_fire && b2s_0_rsp_context_veryLast); - assign when_DmaSg_l726 = b2s_0_rsp_context_channel[0]; - assign _zz_m2b_cmd_s0_priority_masked = channels_1_priority; - assign m2b_cmd_s0_priority_masked = (channels_1_push_m2b_loadRequest && (channels_1_priority == _zz_m2b_cmd_s0_priority_masked)); - assign _zz_m2b_cmd_s0_priority_chosenOh = m2b_cmd_s0_priority_masked; - assign _zz_m2b_cmd_s0_priority_chosenOh_1 = {_zz_m2b_cmd_s0_priority_chosenOh,_zz_m2b_cmd_s0_priority_chosenOh}; - assign _zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 & (~ _zz__zz_m2b_cmd_s0_priority_chosenOh_2)); - assign m2b_cmd_s0_priority_chosenOh = (_zz_m2b_cmd_s0_priority_chosenOh_2[1 : 1] | _zz_m2b_cmd_s0_priority_chosenOh_2[0 : 0]); - assign m2b_cmd_s0_priority_weightLast = (channels_1_weight == m2b_cmd_s0_priority_counter); - assign m2b_cmd_s0_priority_contextNext = (m2b_cmd_s0_priority_weightLast ? m2b_cmd_s0_priority_chosenOh[0 : 0] : m2b_cmd_s0_priority_chosenOh); - assign when_DmaSg_l758 = (! m2b_cmd_s0_valid); - assign when_DmaSg_l760 = (|channels_1_push_m2b_loadRequest); - assign when_DmaSg_l763 = (2'b00 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l763_1 = (2'b01 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l763_2 = (2'b10 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l763_3 = (2'b11 == _zz_m2b_cmd_s0_priority_masked); - assign when_DmaSg_l773 = (channels_1_push_m2b_loadRequest && m2b_cmd_s0_priority_chosenOh[0]); - assign m2b_cmd_s0_address = channels_1_push_m2b_address; - assign m2b_cmd_s0_bytesLeft = channels_1_push_m2b_bytesLeft; - assign m2b_cmd_s0_readAddressBurstRange = m2b_cmd_s0_address[11 : 0]; - assign m2b_cmd_s0_lengthHead = ((~ m2b_cmd_s0_readAddressBurstRange) & channels_1_push_m2b_bytePerBurst); - assign m2b_cmd_s0_length = _zz_m2b_cmd_s0_length[11:0]; - assign m2b_cmd_s0_lastBurst = (m2b_cmd_s0_bytesLeft == _zz_m2b_cmd_s0_lastBurst); - assign m2b_cmd_s1_context_start = m2b_cmd_s1_address[3:0]; - assign m2b_cmd_s1_context_stop = _zz_m2b_cmd_s1_context_stop[3:0]; - assign m2b_cmd_s1_context_last = m2b_cmd_s1_lastBurst; - assign m2b_cmd_s1_context_length = m2b_cmd_s1_length; - always @(*) begin - io_read_cmd_valid = 1'b0; - if(m2b_cmd_s1_valid) begin - io_read_cmd_valid = 1'b1; - end - end - - assign io_read_cmd_payload_last = 1'b1; - assign io_read_cmd_payload_fragment_opcode = 1'b0; - assign io_read_cmd_payload_fragment_address = m2b_cmd_s1_address; - assign io_read_cmd_payload_fragment_length = m2b_cmd_s1_length; - assign io_read_cmd_payload_fragment_context = {m2b_cmd_s1_context_last,{m2b_cmd_s1_context_length,{m2b_cmd_s1_context_stop,m2b_cmd_s1_context_start}}}; - assign m2b_cmd_s1_addressNext = (_zz_m2b_cmd_s1_addressNext + 32'h00000001); - assign m2b_cmd_s1_byteLeftNext = (_zz_m2b_cmd_s1_byteLeftNext - 26'h0000001); - assign m2b_cmd_s1_fifoPushDecr = (_zz_m2b_cmd_s1_fifoPushDecr >>> 2'd3); - assign when_DmaSg_l828 = 1'b1; - assign _zz_m2b_rsp_context_start = io_read_rsp_payload_fragment_context; - assign m2b_rsp_context_start = _zz_m2b_rsp_context_start[3 : 0]; - assign m2b_rsp_context_stop = _zz_m2b_rsp_context_start[7 : 4]; - assign m2b_rsp_context_length = _zz_m2b_rsp_context_start[19 : 8]; - assign m2b_rsp_context_last = _zz_m2b_rsp_context_start[20]; - assign m2b_rsp_veryLast = (m2b_rsp_context_last && io_read_rsp_payload_last); - assign io_read_rsp_fire = (io_read_rsp_valid && io_read_rsp_ready); - assign when_DmaSg_l847 = (io_read_rsp_fire && m2b_rsp_veryLast); - assign when_DmaSg_l848 = 1'b1; - always @(*) begin - memory_core_io_writes_1_cmd_payload_mask[0] = ((! (m2b_rsp_first && (4'b0000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0000)))); - memory_core_io_writes_1_cmd_payload_mask[1] = ((! (m2b_rsp_first && (4'b0001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0001)))); - memory_core_io_writes_1_cmd_payload_mask[2] = ((! (m2b_rsp_first && (4'b0010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0010)))); - memory_core_io_writes_1_cmd_payload_mask[3] = ((! (m2b_rsp_first && (4'b0011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0011)))); - memory_core_io_writes_1_cmd_payload_mask[4] = ((! (m2b_rsp_first && (4'b0100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0100)))); - memory_core_io_writes_1_cmd_payload_mask[5] = ((! (m2b_rsp_first && (4'b0101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0101)))); - memory_core_io_writes_1_cmd_payload_mask[6] = ((! (m2b_rsp_first && (4'b0110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0110)))); - memory_core_io_writes_1_cmd_payload_mask[7] = ((! (m2b_rsp_first && (4'b0111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0111)))); - memory_core_io_writes_1_cmd_payload_mask[8] = ((! (m2b_rsp_first && (4'b1000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1000)))); - memory_core_io_writes_1_cmd_payload_mask[9] = ((! (m2b_rsp_first && (4'b1001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1001)))); - memory_core_io_writes_1_cmd_payload_mask[10] = ((! (m2b_rsp_first && (4'b1010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1010)))); - memory_core_io_writes_1_cmd_payload_mask[11] = ((! (m2b_rsp_first && (4'b1011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1011)))); - memory_core_io_writes_1_cmd_payload_mask[12] = ((! (m2b_rsp_first && (4'b1100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1100)))); - memory_core_io_writes_1_cmd_payload_mask[13] = ((! (m2b_rsp_first && (4'b1101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1101)))); - memory_core_io_writes_1_cmd_payload_mask[14] = ((! (m2b_rsp_first && (4'b1110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1110)))); - memory_core_io_writes_1_cmd_payload_mask[15] = ((! (m2b_rsp_first && (4'b1111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1111)))); - end - - assign m2b_rsp_writeContext_last = m2b_rsp_veryLast; - assign m2b_rsp_writeContext_lastOfBurst = io_read_rsp_payload_last; - assign m2b_rsp_writeContext_loadByteInNextBeat = ({1'b0,(io_read_rsp_payload_last ? m2b_rsp_context_stop : 4'b1111)} - {1'b0,(m2b_rsp_first ? m2b_rsp_context_start : 4'b0000)}); - assign memory_core_io_writes_1_cmd_payload_address = channels_1_fifo_push_ptrWithBase[9:0]; - assign io_read_rsp_ready = memory_core_io_writes_1_cmd_ready; - assign memory_core_io_writes_1_cmd_payload_context = {m2b_rsp_writeContext_loadByteInNextBeat,{m2b_rsp_writeContext_lastOfBurst,m2b_rsp_writeContext_last}}; - assign memory_core_io_writes_1_cmd_fire = (io_read_rsp_valid && memory_core_io_writes_1_cmd_ready); - assign _zz_channels_1_fifo_push_ptrIncr_value = (memory_core_io_writes_1_cmd_fire && 1'b1); - assign when_DmaSg_l874 = (_zz_channels_1_fifo_push_ptrIncr_value && io_read_rsp_payload_last); - assign _zz_m2b_writeRsp_context_last = memory_core_io_writes_1_rsp_payload_context; - assign m2b_writeRsp_context_last = _zz_m2b_writeRsp_context_last[0]; - assign m2b_writeRsp_context_lastOfBurst = _zz_m2b_writeRsp_context_last[1]; - assign m2b_writeRsp_context_loadByteInNextBeat = _zz_m2b_writeRsp_context_last[6 : 2]; - assign _zz_channels_1_fifo_pop_bytesIncr_value = (memory_core_io_writes_1_rsp_valid && 1'b1); - assign when_DmaSg_l893 = (_zz_channels_1_fifo_pop_bytesIncr_value && m2b_writeRsp_context_lastOfBurst); - assign _zz_b2m_fsm_arbiter_logic_priority_masked = channels_0_priority; - assign b2m_fsm_arbiter_logic_priority_masked = (channels_0_pop_b2m_request && (channels_0_priority == _zz_b2m_fsm_arbiter_logic_priority_masked)); - assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh = b2m_fsm_arbiter_logic_priority_masked; - assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 = {_zz_b2m_fsm_arbiter_logic_priority_chosenOh,_zz_b2m_fsm_arbiter_logic_priority_chosenOh}; - assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 & (~ _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2)); - assign b2m_fsm_arbiter_logic_priority_chosenOh = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[1 : 1] | _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[0 : 0]); - assign b2m_fsm_arbiter_logic_priority_weightLast = (channels_0_weight == b2m_fsm_arbiter_logic_priority_counter); - assign b2m_fsm_arbiter_logic_priority_contextNext = (b2m_fsm_arbiter_logic_priority_weightLast ? b2m_fsm_arbiter_logic_priority_chosenOh[0 : 0] : b2m_fsm_arbiter_logic_priority_chosenOh); - assign when_DmaSg_l758_1 = (! b2m_fsm_arbiter_logic_valid); - assign when_DmaSg_l760_1 = (|channels_0_pop_b2m_request); - assign when_DmaSg_l763_4 = (2'b00 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l763_5 = (2'b01 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l763_6 = (2'b10 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l763_7 = (2'b11 == _zz_b2m_fsm_arbiter_logic_priority_masked); - assign when_DmaSg_l773_1 = (channels_0_pop_b2m_request && b2m_fsm_arbiter_logic_priority_chosenOh[0]); - assign when_DmaSg_l935 = ((! b2m_fsm_sel_valid) && b2m_fsm_arbiter_logic_valid); - assign b2m_fsm_bytesInBurstP1 = ({1'b0,b2m_fsm_sel_bytesInBurst} + _zz_b2m_fsm_bytesInBurstP1); - assign b2m_fsm_addressNext = (b2m_fsm_sel_address + _zz_b2m_fsm_addressNext); - assign b2m_fsm_bytesLeftNext = ({1'b0,b2m_fsm_sel_bytesLeft} - _zz_b2m_fsm_bytesLeftNext); - assign b2m_fsm_isFinalCmd = b2m_fsm_bytesLeftNext[26]; - assign b2m_fsm_s0 = (b2m_fsm_sel_valid && (! b2m_fsm_sel_valid_regNext)); - assign when_DmaSg_l986 = (! b2m_fsm_sel_valid); - assign _zz_b2m_fsm_sel_bytesInBurst = (b2m_fsm_sel_bytesInFifo - 14'h0001); - assign _zz_b2m_fsm_sel_bytesInBurst_1 = ((_zz__zz_b2m_fsm_sel_bytesInBurst_1 < b2m_fsm_sel_bytesLeft) ? _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 : b2m_fsm_sel_bytesLeft); - assign _zz_b2m_fsm_sel_bytesInBurst_2 = (b2m_fsm_sel_bytePerBurst - (_zz__zz_b2m_fsm_sel_bytesInBurst_2 & b2m_fsm_sel_bytePerBurst)); - assign b2m_fsm_fifoCompletion = (_zz_b2m_fsm_fifoCompletion == _zz_b2m_fsm_fifoCompletion_1); - assign when_DmaSg_l996 = 1'b1; - assign when_DmaSg_l1001 = (! b2m_fsm_fifoCompletion); - assign when_DmaSg_l1013 = (b2m_fsm_sel_valid && b2m_fsm_sel_ready); - always @(*) begin - b2m_fsm_sel_ready = 1'b0; - if(when_DmaSg_l1102) begin - b2m_fsm_sel_ready = 1'b1; - end - end - - assign b2m_fsm_fetch_context_ptr = channels_0_fifo_pop_ptr; - assign b2m_fsm_fetch_context_toggle = b2m_fsm_toggle; - assign memory_core_io_reads_1_cmd_payload_address = b2m_fsm_sel_ptr[9:0]; - assign memory_core_io_reads_1_cmd_payload_context = {b2m_fsm_fetch_context_toggle,b2m_fsm_fetch_context_ptr}; - assign when_DmaSg_l1033 = (b2m_fsm_sel_valid && memory_core_io_reads_1_cmd_ready); - assign _zz_b2m_fsm_aggregate_context_ptr = memory_core_io_reads_1_rsp_payload_context; - assign b2m_fsm_aggregate_context_ptr = _zz_b2m_fsm_aggregate_context_ptr[10 : 0]; - assign b2m_fsm_aggregate_context_toggle = _zz_b2m_fsm_aggregate_context_ptr[11]; - assign memory_core_io_reads_1_rsp_s2mPipe_valid = (memory_core_io_reads_1_rsp_valid || (! memory_core_io_reads_1_rsp_rValidN)); - assign memory_core_io_reads_1_rsp_s2mPipe_payload_data = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_data : memory_core_io_reads_1_rsp_rData_data); - assign memory_core_io_reads_1_rsp_s2mPipe_payload_mask = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_mask : memory_core_io_reads_1_rsp_rData_mask); - assign memory_core_io_reads_1_rsp_s2mPipe_payload_context = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_context : memory_core_io_reads_1_rsp_rData_context); - assign when_Stream_l445 = (b2m_fsm_aggregate_context_toggle != b2m_fsm_toggle); - always @(*) begin - b2m_fsm_aggregate_memoryPort_valid = memory_core_io_reads_1_rsp_s2mPipe_valid; - if(when_Stream_l445) begin - b2m_fsm_aggregate_memoryPort_valid = 1'b0; - end - end - - always @(*) begin - memory_core_io_reads_1_rsp_s2mPipe_ready = b2m_fsm_aggregate_memoryPort_ready; - if(when_Stream_l445) begin - memory_core_io_reads_1_rsp_s2mPipe_ready = 1'b1; - end - end - - assign b2m_fsm_aggregate_memoryPort_payload_data = memory_core_io_reads_1_rsp_s2mPipe_payload_data; - assign b2m_fsm_aggregate_memoryPort_payload_mask = memory_core_io_reads_1_rsp_s2mPipe_payload_mask; - assign b2m_fsm_aggregate_memoryPort_payload_context = memory_core_io_reads_1_rsp_s2mPipe_payload_context; - assign b2m_fsm_aggregate_memoryPort_fire = (b2m_fsm_aggregate_memoryPort_valid && b2m_fsm_aggregate_memoryPort_ready); - assign when_DmaSg_l1050 = (! (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready))); - assign b2m_fsm_aggregate_bytesToSkip = channels_0_pop_b2m_bytesToSkip; - assign b2m_fsm_aggregate_bytesToSkipMask = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1111)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1110)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_1 || _zz_b2m_fsm_aggregate_bytesToSkipMask_2),{_zz_b2m_fsm_aggregate_bytesToSkipMask_3,{_zz_b2m_fsm_aggregate_bytesToSkipMask_4,_zz_b2m_fsm_aggregate_bytesToSkipMask_5}}}}}}; - assign b2m_fsm_aggregate_memoryPort_ready = b2m_fsm_aggregate_engine_io_input_ready; - assign b2m_fsm_aggregate_engine_io_input_payload_mask = (b2m_fsm_aggregate_memoryPort_payload_mask & b2m_fsm_aggregate_bytesToSkipMask); - assign b2m_fsm_aggregate_engine_io_offset = b2m_fsm_sel_address[3:0]; - assign b2m_fsm_aggregate_engine_io_flush = (! _zz_io_flush); - assign b2m_fsm_cmd_maskFirstTrigger = b2m_fsm_sel_address[3:0]; - assign b2m_fsm_cmd_maskLastTriggerComb = (b2m_fsm_cmd_maskFirstTrigger + _zz_b2m_fsm_cmd_maskLastTriggerComb); - assign b2m_fsm_cmd_maskFirst = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b1111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1011),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst),{_zz_b2m_fsm_cmd_maskFirst_1,{_zz_b2m_fsm_cmd_maskFirst_2,_zz_b2m_fsm_cmd_maskFirst_3}}}}}}}}; - assign b2m_fsm_cmd_enoughAggregation = (((b2m_fsm_s2 && b2m_fsm_sel_valid) && (! b2m_fsm_aggregate_engine_io_flush)) && (io_write_cmd_payload_last ? ((b2m_fsm_aggregate_engine_io_output_mask & b2m_fsm_cmd_maskLast) == b2m_fsm_cmd_maskLast) : (&b2m_fsm_aggregate_engine_io_output_mask))); - assign io_write_cmd_fire = (io_write_cmd_valid && io_write_cmd_ready); - assign io_write_cmd_valid = b2m_fsm_cmd_enoughAggregation; - assign io_write_cmd_payload_last = (b2m_fsm_beatCounter == 8'h0); - assign io_write_cmd_payload_fragment_address = b2m_fsm_sel_address; - assign io_write_cmd_payload_fragment_opcode = 1'b1; - assign io_write_cmd_payload_fragment_data = b2m_fsm_aggregate_engine_io_output_data; - assign io_write_cmd_payload_fragment_mask = (~ ((io_write_cmd_payload_first ? (~ b2m_fsm_cmd_maskFirst) : 16'h0) | (io_write_cmd_payload_last ? (~ b2m_fsm_cmd_maskLast) : 16'h0))); - assign io_write_cmd_payload_fragment_length = b2m_fsm_sel_bytesInBurst; - assign b2m_fsm_cmd_doPtrIncr = (b2m_fsm_sel_valid && (b2m_fsm_aggregate_engine_io_output_consumed || ((io_write_cmd_fire && io_write_cmd_payload_last) && (b2m_fsm_aggregate_engine_io_output_usedUntil == 4'b1111)))); - assign b2m_fsm_cmd_context_length = b2m_fsm_sel_bytesInBurst; - assign b2m_fsm_cmd_context_doPacketSync = (b2m_fsm_sel_packet && b2m_fsm_fifoCompletion); - assign io_write_cmd_payload_fragment_context = {b2m_fsm_cmd_context_doPacketSync,b2m_fsm_cmd_context_length}; - assign when_DmaSg_l1102 = (io_write_cmd_fire && io_write_cmd_payload_last); - assign io_write_rsp_ready = 1'b1; - assign _zz_b2m_rsp_context_length = io_write_rsp_payload_fragment_context; - assign b2m_rsp_context_length = _zz_b2m_rsp_context_length[11 : 0]; - assign b2m_rsp_context_doPacketSync = _zz_b2m_rsp_context_length[12]; - assign io_write_rsp_fire = (io_write_rsp_valid && io_write_rsp_ready); - assign when_DmaSg_l1116 = 1'b1; - assign _zz_ll_arbiter_head = {channels_1_ll_requestLl,channels_0_ll_requestLl}; - assign _zz_ll_arbiter_head_1 = _zz__zz_ll_arbiter_head_1[1]; - assign ll_arbiter_head = (_zz_ll_arbiter_head_2[0] ? channels_0_ll_head : channels_1_ll_head); - assign ll_arbiter_isJustASink = (_zz_ll_arbiter_isJustASink[0] ? channels_0_descriptorValid : channels_1_descriptorValid); - assign ll_arbiter_doDescriptorStall = (_zz_ll_arbiter_doDescriptorStall[0] ? ((! channels_0_ll_controlNoCompletion) || channels_0_ll_gotDescriptorStall) : ((! channels_1_ll_controlNoCompletion) || channels_1_ll_gotDescriptorStall)); - assign ll_arbiter_onSgStream = (_zz_ll_arbiter_onSgStream[0] ? channels_0_ll_onSgStream : channels_1_ll_onSgStream); - assign when_DmaSg_l1149 = (! ll_cmd_valid); - assign when_DmaSg_l1148 = (! ll_cmd_valid); - assign when_DmaSg_l1148_1 = (! ll_cmd_valid); - assign when_DmaSg_l1148_2 = (! ll_cmd_valid); - assign when_DmaSg_l1148_3 = (! ll_cmd_valid); - assign when_DmaSg_l1154 = (! ll_cmd_valid); - assign when_DmaSg_l1155 = (! ll_cmd_valid); - assign when_DmaSg_l1156 = (! ll_cmd_valid); - assign when_DmaSg_l1160 = (! ll_cmd_valid); - assign when_DmaSg_l1161 = (|{_zz_ll_arbiter_head_1,channels_0_ll_requestLl}); - assign when_DmaSg_l1169 = (! ll_arbiter_isJustASink); - assign when_DmaSg_l1169_1 = (! ll_arbiter_isJustASink); - assign when_DmaSg_l1177 = (ll_cmd_writeFired && ll_cmd_readFired); - assign ll_cmd_context_channel = ll_cmd_oh_1; - assign io_sgRead_cmd_valid = ((ll_cmd_valid && (! ll_cmd_readFired)) && (! ll_cmd_onSgStream)); - assign io_sgRead_cmd_payload_last = 1'b1; - assign io_sgRead_cmd_payload_fragment_address = {ll_cmd_ptrNext[31 : 5],5'h0}; - assign io_sgRead_cmd_payload_fragment_length = 5'h1f; - assign io_sgRead_cmd_payload_fragment_opcode = 1'b0; - assign io_sgRead_cmd_payload_fragment_context = ll_cmd_context_channel; - assign io_sgWrite_cmd_valid = ((ll_cmd_valid && (! ll_cmd_writeFired)) && (! ll_cmd_onSgStream)); - assign io_sgWrite_cmd_payload_last = 1'b1; - assign io_sgWrite_cmd_payload_fragment_address = {ll_cmd_ptr[31 : 5],5'h0}; - assign io_sgWrite_cmd_payload_fragment_length = 2'b11; - assign io_sgWrite_cmd_payload_fragment_opcode = 1'b1; - assign io_sgWrite_cmd_payload_fragment_context = ll_cmd_context_channel; - assign ll_cmd_writeMaskSplit_0 = io_sgWrite_cmd_payload_fragment_mask[3 : 0]; - assign ll_cmd_writeMaskSplit_1 = io_sgWrite_cmd_payload_fragment_mask[7 : 4]; - assign ll_cmd_writeMaskSplit_2 = io_sgWrite_cmd_payload_fragment_mask[11 : 8]; - assign ll_cmd_writeMaskSplit_3 = io_sgWrite_cmd_payload_fragment_mask[15 : 12]; - assign ll_cmd_writeDataSplit_0 = io_sgWrite_cmd_payload_fragment_data[31 : 0]; - assign ll_cmd_writeDataSplit_1 = io_sgWrite_cmd_payload_fragment_data[63 : 32]; - assign ll_cmd_writeDataSplit_2 = io_sgWrite_cmd_payload_fragment_data[95 : 64]; - assign ll_cmd_writeDataSplit_3 = io_sgWrite_cmd_payload_fragment_data[127 : 96]; - assign _zz_1 = zz_io_sgWrite_cmd_payload_fragment_mask(1'b0); - always @(*) io_sgWrite_cmd_payload_fragment_mask = _zz_1; - always @(*) begin - io_sgWrite_cmd_payload_fragment_data[63 : 32] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - io_sgWrite_cmd_payload_fragment_data[95 : 64] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - io_sgWrite_cmd_payload_fragment_data[127 : 96] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - io_sgWrite_cmd_payload_fragment_data[31 : 0] = 32'h0; - io_sgWrite_cmd_payload_fragment_data[26 : 0] = ll_cmd_bytesDone; - io_sgWrite_cmd_payload_fragment_data[30] = ll_cmd_endOfPacket; - io_sgWrite_cmd_payload_fragment_data[31] = ((! ll_cmd_isJustASink) && ll_cmd_doDescriptorStall); - end - - assign io_sgRead_cmd_fire = (io_sgRead_cmd_valid && io_sgRead_cmd_ready); - assign io_sgWrite_cmd_fire = (io_sgWrite_cmd_valid && io_sgWrite_cmd_ready); - assign ll_readRsp_context_channel = io_sgRead_rsp_payload_fragment_context[0 : 0]; - assign _zz_ll_readRsp_oh_0 = (2'b01 <<< ll_readRsp_context_channel); - assign ll_readRsp_oh_0 = _zz_ll_readRsp_oh_0[0]; - assign ll_readRsp_oh_1 = _zz_ll_readRsp_oh_0[1]; - assign io_sgRead_rsp_ready = 1'b1; - assign io_sgRead_rsp_fire = (io_sgRead_rsp_valid && io_sgRead_rsp_ready); - assign when_DmaSg_l1248 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_1 = (1'b1 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_2 = (1'b1 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_3 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_4 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_5 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1248_6 = (1'b0 == ll_readRsp_beatCounter); - assign when_DmaSg_l1271 = (io_sgRead_rsp_fire && io_sgRead_rsp_payload_last); - assign ll_writeRsp_context_channel = io_sgWrite_rsp_payload_fragment_context[0 : 0]; - assign _zz_ll_writeRsp_oh_0 = (2'b01 <<< ll_writeRsp_context_channel); - assign ll_writeRsp_oh_0 = _zz_ll_writeRsp_oh_0[0]; - assign ll_writeRsp_oh_1 = _zz_ll_writeRsp_oh_0[1]; - assign io_sgWrite_rsp_ready = 1'b1; - assign io_sgWrite_rsp_fire = (io_sgWrite_rsp_valid && io_sgWrite_rsp_ready); - always @(*) begin - io_interrupts = 2'b00; - if(channels_0_interrupts_completion_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_0_interrupts_onChannelCompletion_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_0_interrupts_onLinkedListUpdate_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_0_interrupts_s2mPacket_valid) begin - io_interrupts[0] = 1'b1; - end - if(channels_1_interrupts_completion_valid) begin - io_interrupts[1] = 1'b1; - end - if(channels_1_interrupts_onChannelCompletion_valid) begin - io_interrupts[1] = 1'b1; - end - if(channels_1_interrupts_onLinkedListUpdate_valid) begin - io_interrupts[1] = 1'b1; - end - end - - always @(*) begin - when_BusSlaveFactory_l377 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_1 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_1 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_2 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_2 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l377_3 = 1'b0; - case(io_ctrl_PADDR) - 14'h002c : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_3 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l341 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l341_1 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_1 = io_ctrl_PWDATA[2]; - always @(*) begin - when_BusSlaveFactory_l341_2 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_2 = io_ctrl_PWDATA[3]; - always @(*) begin - when_BusSlaveFactory_l341_3 = 1'b0; - case(io_ctrl_PADDR) - 14'h0054 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_3 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l377_4 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_4 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_4 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_5 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_5 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_5 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l377_6 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_6 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_6 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l377_7 = 1'b0; - case(io_ctrl_PADDR) - 14'h00ac : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l377_7 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l379_7 = io_ctrl_PWDATA[4]; - always @(*) begin - when_BusSlaveFactory_l341_4 = 1'b0; - case(io_ctrl_PADDR) - 14'h00d4 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_4 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_4 = io_ctrl_PWDATA[0]; - always @(*) begin - when_BusSlaveFactory_l341_5 = 1'b0; - case(io_ctrl_PADDR) - 14'h00d4 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_5 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_5 = io_ctrl_PWDATA[2]; - always @(*) begin - when_BusSlaveFactory_l341_6 = 1'b0; - case(io_ctrl_PADDR) - 14'h00d4 : begin - if(ctrl_doWrite) begin - when_BusSlaveFactory_l341_6 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l347_6 = io_ctrl_PWDATA[3]; - assign when_Apb3SlaveFactory_l81 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0010); - assign when_Apb3SlaveFactory_l81_1 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0070); - assign when_Apb3SlaveFactory_l81_2 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0080); - assign when_Apb3SlaveFactory_l81_3 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h00f0); - assign channels_0_fifo_push_ptrIncr_value = _zz_channels_0_fifo_push_ptrIncr_value; - assign channels_0_fifo_pop_bytesIncr_value = _zz_channels_0_fifo_pop_bytesIncr_value_1; - assign channels_0_fifo_pop_bytesDecr_value = channels_0_pop_b2m_decrBytes; - assign channels_0_fifo_pop_ptrIncr_value = _zz_channels_0_fifo_pop_ptrIncr_value; - assign channels_1_fifo_push_ptrIncr_value = _zz_channels_1_fifo_push_ptrIncr_value_1; - assign channels_1_fifo_pop_bytesIncr_value = _zz_channels_1_fifo_pop_bytesIncr_value_1; - assign channels_1_fifo_pop_bytesDecr_value = 14'h0; - assign channels_1_fifo_pop_ptrIncr_value = _zz_channels_1_fifo_pop_ptrIncr_value; - assign ll_0_descriptorUpdate = (channels_0_ll_descriptorUpdated && (! channels_0_ll_gotDescriptorStall)); - assign ll_1_descriptorUpdate = (channels_1_ll_descriptorUpdated && (! channels_1_ll_gotDescriptorStall)); - always @(posedge clk) begin - if(reset) begin - channels_0_channelValid <= 1'b0; - channels_0_descriptorValid <= 1'b0; - channels_0_priority <= 2'b00; - channels_0_weight <= 2'b00; - channels_0_ctrl_kick <= 1'b0; - channels_0_ll_valid <= 1'b0; - channels_0_ll_onSgStream <= 1'b0; - channels_0_pop_b2m_memPending <= 4'b0000; - channels_0_interrupts_completion_enable <= 1'b0; - channels_0_interrupts_completion_valid <= 1'b0; - channels_0_interrupts_onChannelCompletion_enable <= 1'b0; - channels_0_interrupts_onChannelCompletion_valid <= 1'b0; - channels_0_interrupts_onLinkedListUpdate_enable <= 1'b0; - channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; - channels_0_interrupts_s2mPacket_enable <= 1'b0; - channels_0_interrupts_s2mPacket_valid <= 1'b0; - channels_1_channelValid <= 1'b0; - channels_1_descriptorValid <= 1'b0; - channels_1_priority <= 2'b00; - channels_1_weight <= 2'b00; - channels_1_ctrl_kick <= 1'b0; - channels_1_ll_valid <= 1'b0; - channels_1_ll_onSgStream <= 1'b0; - channels_1_push_m2b_loadDone <= 1'b1; - channels_1_push_m2b_memPending <= 4'b0000; - channels_1_interrupts_completion_enable <= 1'b0; - channels_1_interrupts_completion_valid <= 1'b0; - channels_1_interrupts_onChannelCompletion_enable <= 1'b0; - channels_1_interrupts_onChannelCompletion_valid <= 1'b0; - channels_1_interrupts_onLinkedListUpdate_enable <= 1'b0; - channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; - io_inputs_0_payload_last_regNextWhen <= 1'b1; - io_inputs_0_payload_last_regNextWhen_1 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_2 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_3 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_4 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_5 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_6 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_7 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_8 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_9 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_10 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_11 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_12 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_13 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_14 <= 1'b1; - io_inputs_0_payload_last_regNextWhen_15 <= 1'b1; - m2b_cmd_s0_valid <= 1'b0; - m2b_cmd_s0_priority_roundRobins_0 <= 1'b1; - m2b_cmd_s0_priority_roundRobins_1 <= 1'b1; - m2b_cmd_s0_priority_roundRobins_2 <= 1'b1; - m2b_cmd_s0_priority_roundRobins_3 <= 1'b1; - m2b_cmd_s0_priority_counter <= 2'b00; - m2b_cmd_s1_valid <= 1'b0; - m2b_rsp_first <= 1'b1; - b2m_fsm_sel_valid <= 1'b0; - b2m_fsm_arbiter_logic_valid <= 1'b0; - b2m_fsm_arbiter_logic_priority_roundRobins_0 <= 1'b1; - b2m_fsm_arbiter_logic_priority_roundRobins_1 <= 1'b1; - b2m_fsm_arbiter_logic_priority_roundRobins_2 <= 1'b1; - b2m_fsm_arbiter_logic_priority_roundRobins_3 <= 1'b1; - b2m_fsm_arbiter_logic_priority_counter <= 2'b00; - b2m_fsm_sel_valid_regNext <= 1'b0; - b2m_fsm_s1 <= 1'b0; - b2m_fsm_s2 <= 1'b0; - b2m_fsm_toggle <= 1'b0; - memory_core_io_reads_1_rsp_rValidN <= 1'b1; - _zz_io_flush <= 1'b0; - io_write_cmd_payload_first <= 1'b1; - ll_cmd_valid <= 1'b0; - ll_readRsp_beatCounter <= 1'b0; - end else begin - if(channels_0_channelStart) begin - channels_0_channelValid <= 1'b1; - end - if(channels_0_channelCompletion) begin - channels_0_channelValid <= 1'b0; - end - if(channels_0_descriptorStart) begin - channels_0_descriptorValid <= 1'b1; - end - if(channels_0_descriptorCompletion) begin - channels_0_descriptorValid <= 1'b0; - end - channels_0_ctrl_kick <= 1'b0; - if(channels_0_channelCompletion) begin - channels_0_ctrl_kick <= 1'b0; - end - if(when_DmaSg_l318) begin - if(when_DmaSg_l320) begin - if(!when_DmaSg_l322) begin - channels_0_ll_valid <= 1'b0; - end - end - end - if(channels_0_ll_sgStart) begin - channels_0_ll_valid <= 1'b1; - end - if(channels_0_channelCompletion) begin - channels_0_ll_valid <= 1'b0; - end - channels_0_pop_b2m_memPending <= (_zz_channels_0_pop_b2m_memPending - _zz_channels_0_pop_b2m_memPending_3); - if(when_DmaSg_l255) begin - channels_0_interrupts_completion_valid <= 1'b1; - end - if(when_DmaSg_l255_1) begin - channels_0_interrupts_completion_valid <= 1'b0; - end - if(when_DmaSg_l255_2) begin - channels_0_interrupts_onChannelCompletion_valid <= 1'b1; - end - if(when_DmaSg_l255_3) begin - channels_0_interrupts_onChannelCompletion_valid <= 1'b0; - end - if(channels_0_ll_descriptorUpdated) begin - channels_0_interrupts_onLinkedListUpdate_valid <= 1'b1; - end - if(when_DmaSg_l255_4) begin - channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; - end - if(channels_0_pop_b2m_packetSync) begin - channels_0_interrupts_s2mPacket_valid <= 1'b1; - end - if(when_DmaSg_l255_5) begin - channels_0_interrupts_s2mPacket_valid <= 1'b0; - end - if(channels_1_channelStart) begin - channels_1_channelValid <= 1'b1; - end - if(channels_1_channelCompletion) begin - channels_1_channelValid <= 1'b0; - end - if(channels_1_descriptorStart) begin - channels_1_descriptorValid <= 1'b1; - end - if(channels_1_descriptorCompletion) begin - channels_1_descriptorValid <= 1'b0; - end - channels_1_ctrl_kick <= 1'b0; - if(channels_1_channelCompletion) begin - channels_1_ctrl_kick <= 1'b0; - end - if(when_DmaSg_l318_1) begin - if(when_DmaSg_l320_1) begin - if(!when_DmaSg_l322_1) begin - channels_1_ll_valid <= 1'b0; - end - end - end - if(channels_1_ll_sgStart) begin - channels_1_ll_valid <= 1'b1; - end - if(channels_1_channelCompletion) begin - channels_1_ll_valid <= 1'b0; - end - channels_1_push_m2b_memPending <= (_zz_channels_1_push_m2b_memPending - _zz_channels_1_push_m2b_memPending_3); - if(channels_1_descriptorStart) begin - channels_1_push_m2b_loadDone <= 1'b0; - end - if(when_DmaSg_l255_6) begin - channels_1_interrupts_completion_valid <= 1'b1; - end - if(when_DmaSg_l255_7) begin - channels_1_interrupts_completion_valid <= 1'b0; - end - if(when_DmaSg_l255_8) begin - channels_1_interrupts_onChannelCompletion_valid <= 1'b1; - end - if(when_DmaSg_l255_9) begin - channels_1_interrupts_onChannelCompletion_valid <= 1'b0; - end - if(channels_1_ll_descriptorUpdated) begin - channels_1_interrupts_onLinkedListUpdate_valid <= 1'b1; - end - if(when_DmaSg_l255_10) begin - channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; - end - if(when_package_l12) begin - io_inputs_0_payload_last_regNextWhen <= io_inputs_0_payload_last; - end - if(when_package_l12_1) begin - io_inputs_0_payload_last_regNextWhen_1 <= io_inputs_0_payload_last; - end - if(when_package_l12_2) begin - io_inputs_0_payload_last_regNextWhen_2 <= io_inputs_0_payload_last; - end - if(when_package_l12_3) begin - io_inputs_0_payload_last_regNextWhen_3 <= io_inputs_0_payload_last; - end - if(when_package_l12_4) begin - io_inputs_0_payload_last_regNextWhen_4 <= io_inputs_0_payload_last; - end - if(when_package_l12_5) begin - io_inputs_0_payload_last_regNextWhen_5 <= io_inputs_0_payload_last; - end - if(when_package_l12_6) begin - io_inputs_0_payload_last_regNextWhen_6 <= io_inputs_0_payload_last; - end - if(when_package_l12_7) begin - io_inputs_0_payload_last_regNextWhen_7 <= io_inputs_0_payload_last; - end - if(when_package_l12_8) begin - io_inputs_0_payload_last_regNextWhen_8 <= io_inputs_0_payload_last; - end - if(when_package_l12_9) begin - io_inputs_0_payload_last_regNextWhen_9 <= io_inputs_0_payload_last; - end - if(when_package_l12_10) begin - io_inputs_0_payload_last_regNextWhen_10 <= io_inputs_0_payload_last; - end - if(when_package_l12_11) begin - io_inputs_0_payload_last_regNextWhen_11 <= io_inputs_0_payload_last; - end - if(when_package_l12_12) begin - io_inputs_0_payload_last_regNextWhen_12 <= io_inputs_0_payload_last; - end - if(when_package_l12_13) begin - io_inputs_0_payload_last_regNextWhen_13 <= io_inputs_0_payload_last; - end - if(when_package_l12_14) begin - io_inputs_0_payload_last_regNextWhen_14 <= io_inputs_0_payload_last; - end - if(when_package_l12_15) begin - io_inputs_0_payload_last_regNextWhen_15 <= io_inputs_0_payload_last; - end - if(when_DmaSg_l758) begin - if(when_DmaSg_l760) begin - m2b_cmd_s0_valid <= 1'b1; - if(when_DmaSg_l763) begin - m2b_cmd_s0_priority_roundRobins_0 <= m2b_cmd_s0_priority_contextNext; - end - if(when_DmaSg_l763_1) begin - m2b_cmd_s0_priority_roundRobins_1 <= m2b_cmd_s0_priority_contextNext; - end - if(when_DmaSg_l763_2) begin - m2b_cmd_s0_priority_roundRobins_2 <= m2b_cmd_s0_priority_contextNext; - end - if(when_DmaSg_l763_3) begin - m2b_cmd_s0_priority_roundRobins_3 <= m2b_cmd_s0_priority_contextNext; - end - m2b_cmd_s0_priority_counter <= (m2b_cmd_s0_priority_counter + 2'b01); - if(m2b_cmd_s0_priority_weightLast) begin - m2b_cmd_s0_priority_counter <= 2'b00; - end - end - end - if(m2b_cmd_s0_valid) begin - m2b_cmd_s1_valid <= 1'b1; - end - if(m2b_cmd_s1_valid) begin - if(io_read_cmd_ready) begin - m2b_cmd_s0_valid <= 1'b0; - m2b_cmd_s1_valid <= 1'b0; - if(when_DmaSg_l828) begin - if(m2b_cmd_s1_lastBurst) begin - channels_1_push_m2b_loadDone <= 1'b1; - end - end - end - end - if(io_read_rsp_fire) begin - m2b_rsp_first <= io_read_rsp_payload_last; - end - if(when_DmaSg_l758_1) begin - if(when_DmaSg_l760_1) begin - b2m_fsm_arbiter_logic_valid <= 1'b1; - if(when_DmaSg_l763_4) begin - b2m_fsm_arbiter_logic_priority_roundRobins_0 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - if(when_DmaSg_l763_5) begin - b2m_fsm_arbiter_logic_priority_roundRobins_1 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - if(when_DmaSg_l763_6) begin - b2m_fsm_arbiter_logic_priority_roundRobins_2 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - if(when_DmaSg_l763_7) begin - b2m_fsm_arbiter_logic_priority_roundRobins_3 <= b2m_fsm_arbiter_logic_priority_contextNext; - end - b2m_fsm_arbiter_logic_priority_counter <= (b2m_fsm_arbiter_logic_priority_counter + 2'b01); - if(b2m_fsm_arbiter_logic_priority_weightLast) begin - b2m_fsm_arbiter_logic_priority_counter <= 2'b00; - end - end - end - if(b2m_fsm_sel_ready) begin - b2m_fsm_sel_valid <= 1'b0; - if(b2m_fsm_sel_valid) begin - b2m_fsm_arbiter_logic_valid <= 1'b0; - end - end - if(when_DmaSg_l935) begin - b2m_fsm_sel_valid <= 1'b1; - end - b2m_fsm_sel_valid_regNext <= b2m_fsm_sel_valid; - b2m_fsm_s1 <= b2m_fsm_s0; - if(b2m_fsm_s1) begin - b2m_fsm_s2 <= 1'b1; - end - if(when_DmaSg_l986) begin - b2m_fsm_s2 <= 1'b0; - end - if(when_DmaSg_l1013) begin - b2m_fsm_toggle <= (! b2m_fsm_toggle); - end - if(memory_core_io_reads_1_rsp_valid) begin - memory_core_io_reads_1_rsp_rValidN <= 1'b0; - end - if(memory_core_io_reads_1_rsp_s2mPipe_ready) begin - memory_core_io_reads_1_rsp_rValidN <= 1'b1; - end - _zz_io_flush <= (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready)); - if(io_write_cmd_fire) begin - io_write_cmd_payload_first <= io_write_cmd_payload_last; - end - if(when_DmaSg_l1160) begin - if(when_DmaSg_l1161) begin - ll_cmd_valid <= 1'b1; - end - end else begin - if(when_DmaSg_l1177) begin - ll_cmd_valid <= 1'b0; - end - end - if(io_sgRead_rsp_fire) begin - ll_readRsp_beatCounter <= (ll_readRsp_beatCounter + 1'b1); - end - if(when_BusSlaveFactory_l377_1) begin - if(when_BusSlaveFactory_l379_1) begin - channels_0_ctrl_kick <= _zz_channels_0_ctrl_kick[0]; - end - end - if(when_BusSlaveFactory_l341) begin - if(when_BusSlaveFactory_l347) begin - channels_0_interrupts_completion_valid <= _zz_channels_0_interrupts_completion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_1) begin - if(when_BusSlaveFactory_l347_1) begin - channels_0_interrupts_onChannelCompletion_valid <= _zz_channels_0_interrupts_onChannelCompletion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_2) begin - if(when_BusSlaveFactory_l347_2) begin - channels_0_interrupts_onLinkedListUpdate_valid <= _zz_channels_0_interrupts_onLinkedListUpdate_valid[0]; - end - end - if(when_BusSlaveFactory_l341_3) begin - if(when_BusSlaveFactory_l347_3) begin - channels_0_interrupts_s2mPacket_valid <= _zz_channels_0_interrupts_s2mPacket_valid[0]; - end - end - if(when_BusSlaveFactory_l377_5) begin - if(when_BusSlaveFactory_l379_5) begin - channels_1_ctrl_kick <= _zz_channels_1_ctrl_kick[0]; - end - end - if(when_BusSlaveFactory_l341_4) begin - if(when_BusSlaveFactory_l347_4) begin - channels_1_interrupts_completion_valid <= _zz_channels_1_interrupts_completion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_5) begin - if(when_BusSlaveFactory_l347_5) begin - channels_1_interrupts_onChannelCompletion_valid <= _zz_channels_1_interrupts_onChannelCompletion_valid[0]; - end - end - if(when_BusSlaveFactory_l341_6) begin - if(when_BusSlaveFactory_l347_6) begin - channels_1_interrupts_onLinkedListUpdate_valid <= _zz_channels_1_interrupts_onLinkedListUpdate_valid[0]; - end - end - case(io_ctrl_PADDR) - 14'h0078 : begin - if(ctrl_doWrite) begin - channels_0_ll_onSgStream <= io_ctrl_PWDATA[0]; - end - end - 14'h0044 : begin - if(ctrl_doWrite) begin - channels_0_priority <= io_ctrl_PWDATA[1 : 0]; - channels_0_weight <= io_ctrl_PWDATA[9 : 8]; - end - end - 14'h0050 : begin - if(ctrl_doWrite) begin - channels_0_interrupts_completion_enable <= io_ctrl_PWDATA[0]; - channels_0_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; - channels_0_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; - channels_0_interrupts_s2mPacket_enable <= io_ctrl_PWDATA[4]; - end - end - 14'h00f8 : begin - if(ctrl_doWrite) begin - channels_1_ll_onSgStream <= io_ctrl_PWDATA[0]; - end - end - 14'h00c4 : begin - if(ctrl_doWrite) begin - channels_1_priority <= io_ctrl_PWDATA[1 : 0]; - channels_1_weight <= io_ctrl_PWDATA[9 : 8]; - end - end - 14'h00d0 : begin - if(ctrl_doWrite) begin - channels_1_interrupts_completion_enable <= io_ctrl_PWDATA[0]; - channels_1_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; - channels_1_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; - end - end - default : begin - end - endcase - end - end - - always @(posedge clk) begin - if(channels_0_bytesProbe_incr_valid) begin - channels_0_bytesProbe_value <= (_zz_channels_0_bytesProbe_value + 27'h0000001); - end - if(channels_0_descriptorStart) begin - channels_0_ll_packet <= 1'b0; - end - if(channels_0_descriptorStart) begin - channels_0_ll_requireSync <= 1'b0; - end - if(when_DmaSg_l318) begin - channels_0_ll_waitDone <= 1'b0; - if(when_DmaSg_l320) begin - channels_0_ll_head <= 1'b0; - end - end - if(channels_0_channelStart) begin - channels_0_ll_waitDone <= 1'b0; - channels_0_ll_head <= 1'b1; - end - channels_0_fifo_push_ptr <= (channels_0_fifo_push_ptr + channels_0_fifo_push_ptrIncr_value); - if(channels_0_channelStart) begin - channels_0_fifo_push_ptr <= 11'h0; - end - channels_0_fifo_pop_ptr <= (channels_0_fifo_pop_ptr + channels_0_fifo_pop_ptrIncr_value); - channels_0_fifo_pop_withOverride_backup <= channels_0_fifo_pop_withOverride_backupNext; - if(when_DmaSg_l409) begin - channels_0_fifo_pop_withOverride_valid <= 1'b0; - end - if(channels_0_fifo_pop_withOverride_load) begin - channels_0_fifo_pop_withOverride_valid <= 1'b1; - end - channels_0_fifo_pop_withOverride_exposed <= ((! channels_0_fifo_pop_withOverride_valid) ? channels_0_fifo_pop_withOverride_backupNext : _zz_channels_0_fifo_pop_withOverride_exposed); - if(channels_0_channelStart) begin - channels_0_fifo_pop_withOverride_backup <= 14'h0; - channels_0_fifo_pop_withOverride_valid <= 1'b0; - end - if(channels_0_channelStart) begin - channels_0_push_s2b_packetLock <= 1'b0; - end - if(channels_0_pop_b2m_fire) begin - channels_0_pop_b2m_flush <= 1'b0; - end - if(when_DmaSg_l505) begin - channels_0_pop_b2m_packet <= 1'b0; - end - if(when_DmaSg_l523) begin - channels_0_pop_b2m_flush <= 1'b0; - channels_0_pop_b2m_packet <= 1'b0; - end - if(channels_0_pop_b2m_packetSync) begin - channels_0_push_s2b_packetLock <= 1'b0; - if(when_DmaSg_l532) begin - if(!channels_0_push_s2b_completionOnLast) begin - if(when_DmaSg_l536) begin - channels_0_ll_requireSync <= 1'b1; - end - end - channels_0_ll_packet <= 1'b1; - end - end - if(channels_0_channelStart) begin - channels_0_pop_b2m_bytesToSkip <= 4'b0000; - channels_0_pop_b2m_flush <= 1'b0; - end - if(channels_0_descriptorStart) begin - channels_0_pop_b2m_bytesLeft <= {1'd0, channels_0_bytes}; - channels_0_pop_b2m_waitFinalRsp <= 1'b0; - end - if(channels_0_channelValid) begin - if(!channels_0_channelStop) begin - if(when_DmaSg_l575) begin - if(when_DmaSg_l593) begin - channels_0_channelStop <= 1'b1; - end - end - end - end - channels_0_fifo_pop_ptrIncr_value_regNext <= channels_0_fifo_pop_ptrIncr_value; - channels_0_fifo_push_available <= (_zz_channels_0_fifo_push_available - (channels_0_push_memory ? channels_0_fifo_push_availableDecr : channels_0_fifo_push_ptrIncr_value)); - if(channels_0_channelStart) begin - channels_0_fifo_push_ptr <= 11'h0; - channels_0_fifo_push_available <= (channels_0_fifo_words + 11'h001); - channels_0_fifo_pop_ptr <= 11'h0; - end - if(when_DmaSg_l625) begin - channels_0_bytesProbe_value <= 27'h0; - end - if(channels_1_bytesProbe_incr_valid) begin - channels_1_bytesProbe_value <= (_zz_channels_1_bytesProbe_value + 27'h0000001); - end - if(channels_1_descriptorStart) begin - channels_1_ll_packet <= 1'b0; - end - if(channels_1_descriptorStart) begin - channels_1_ll_requireSync <= 1'b0; - end - if(when_DmaSg_l318_1) begin - channels_1_ll_waitDone <= 1'b0; - if(when_DmaSg_l320_1) begin - channels_1_ll_head <= 1'b0; - end - end - if(channels_1_channelStart) begin - channels_1_ll_waitDone <= 1'b0; - channels_1_ll_head <= 1'b1; - end - channels_1_fifo_push_ptr <= (channels_1_fifo_push_ptr + channels_1_fifo_push_ptrIncr_value); - if(channels_1_channelStart) begin - channels_1_fifo_push_ptr <= 11'h0; - end - channels_1_fifo_pop_ptr <= (channels_1_fifo_pop_ptr + channels_1_fifo_pop_ptrIncr_value); - channels_1_fifo_pop_withoutOverride_exposed <= (_zz_channels_1_fifo_pop_withoutOverride_exposed - channels_1_fifo_pop_bytesDecr_value); - if(channels_1_channelStart) begin - channels_1_fifo_pop_withoutOverride_exposed <= 14'h0; - end - if(channels_1_descriptorStart) begin - channels_1_push_m2b_bytesLeft <= channels_1_bytes; - end - if(when_DmaSg_l474) begin - channels_1_pop_b2s_veryLastValid <= 1'b1; - end - if(channels_1_pop_b2s_veryLastTrigger) begin - channels_1_pop_b2s_veryLastPtr <= channels_1_fifo_push_ptrWithBase; - channels_1_pop_b2s_veryLastEndPacket <= channels_1_pop_b2s_last; - end - if(channels_1_channelStart) begin - channels_1_pop_b2s_veryLastValid <= 1'b0; - end - if(channels_1_channelValid) begin - if(!channels_1_channelStop) begin - if(when_DmaSg_l575_1) begin - if(when_DmaSg_l593_1) begin - channels_1_channelStop <= 1'b1; - end - end - end - end - channels_1_fifo_pop_ptrIncr_value_regNext <= channels_1_fifo_pop_ptrIncr_value; - channels_1_fifo_push_available <= (_zz_channels_1_fifo_push_available - (channels_1_push_memory ? channels_1_fifo_push_availableDecr : channels_1_fifo_push_ptrIncr_value)); - if(channels_1_channelStart) begin - channels_1_fifo_push_ptr <= 11'h0; - channels_1_fifo_push_available <= (channels_1_fifo_words + 11'h001); - channels_1_fifo_pop_ptr <= 11'h0; - end - if(when_DmaSg_l625_1) begin - channels_1_bytesProbe_value <= 27'h0; - end - if(when_DmaSg_l665) begin - channels_0_push_s2b_waitFirst <= 1'b0; - if(io_inputs_0_payload_last) begin - channels_0_push_s2b_packetLock <= 1'b1; - end - end - if(when_DmaSg_l681) begin - channels_0_pop_b2m_flush <= 1'b1; - end - if(when_DmaSg_l682) begin - channels_0_pop_b2m_packet <= 1'b1; - end - if(when_DmaSg_l725) begin - if(when_DmaSg_l726) begin - channels_1_pop_b2s_veryLastValid <= 1'b0; - end - end - m2b_cmd_s1_address <= m2b_cmd_s0_address; - m2b_cmd_s1_length <= m2b_cmd_s0_length; - m2b_cmd_s1_lastBurst <= m2b_cmd_s0_lastBurst; - m2b_cmd_s1_bytesLeft <= m2b_cmd_s0_bytesLeft; - if(m2b_cmd_s1_valid) begin - if(io_read_cmd_ready) begin - if(when_DmaSg_l828) begin - channels_1_push_m2b_address <= m2b_cmd_s1_addressNext; - channels_1_push_m2b_bytesLeft <= m2b_cmd_s1_byteLeftNext; - end - end - end - if(when_DmaSg_l935) begin - b2m_fsm_sel_address <= channels_0_pop_b2m_address; - b2m_fsm_sel_ptr <= channels_0_fifo_pop_ptrWithBase; - b2m_fsm_sel_ptrMask <= channels_0_fifo_words; - b2m_fsm_sel_bytePerBurst <= channels_0_pop_b2m_bytePerBurst; - b2m_fsm_sel_bytesInFifo <= channels_0_fifo_pop_bytes; - b2m_fsm_sel_flush <= channels_0_pop_b2m_flush; - b2m_fsm_sel_packet <= channels_0_pop_b2m_packet; - b2m_fsm_sel_bytesLeft <= channels_0_pop_b2m_bytesLeft[25:0]; - end - if(b2m_fsm_s0) begin - b2m_fsm_sel_bytesInBurst <= _zz_b2m_fsm_sel_bytesInBurst_3[11:0]; - end - if(b2m_fsm_s1) begin - b2m_fsm_beatCounter <= (_zz_b2m_fsm_beatCounter >>> 3'd4); - if(when_DmaSg_l996) begin - channels_0_pop_b2m_address <= b2m_fsm_addressNext; - channels_0_pop_b2m_bytesLeft <= b2m_fsm_bytesLeftNext; - if(b2m_fsm_isFinalCmd) begin - channels_0_pop_b2m_waitFinalRsp <= 1'b1; - end - if(when_DmaSg_l1001) begin - if(b2m_fsm_sel_flush) begin - channels_0_pop_b2m_flush <= 1'b1; - end - if(b2m_fsm_sel_packet) begin - channels_0_pop_b2m_packet <= 1'b1; - end - end - end - end - if(when_DmaSg_l1033) begin - b2m_fsm_sel_ptr <= ((b2m_fsm_sel_ptr & (~ b2m_fsm_sel_ptrMask)) | (_zz_b2m_fsm_sel_ptr & b2m_fsm_sel_ptrMask)); - end - if(memory_core_io_reads_1_rsp_rValidN) begin - memory_core_io_reads_1_rsp_rData_data <= memory_core_io_reads_1_rsp_payload_data; - memory_core_io_reads_1_rsp_rData_mask <= memory_core_io_reads_1_rsp_payload_mask; - memory_core_io_reads_1_rsp_rData_context <= memory_core_io_reads_1_rsp_payload_context; - end - if(b2m_fsm_aggregate_memoryPort_fire) begin - b2m_fsm_aggregate_first <= 1'b0; - end - if(when_DmaSg_l1050) begin - b2m_fsm_aggregate_first <= 1'b1; - end - b2m_fsm_cmd_maskLastTriggerReg <= b2m_fsm_cmd_maskLastTriggerComb; - b2m_fsm_cmd_maskLast <= {(4'b1111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1011 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast <= b2m_fsm_cmd_maskLastTriggerComb),{_zz_b2m_fsm_cmd_maskLast_1,{_zz_b2m_fsm_cmd_maskLast_2,_zz_b2m_fsm_cmd_maskLast_3}}}}}}}}; - if(io_write_cmd_fire) begin - b2m_fsm_beatCounter <= (b2m_fsm_beatCounter - 8'h01); - end - if(when_DmaSg_l1102) begin - if(_zz_when_1[0]) begin - channels_0_pop_b2m_bytesToSkip <= (b2m_fsm_aggregate_engine_io_output_usedUntil + 4'b0001); - end - end - if(when_DmaSg_l1149) begin - ll_cmd_oh_0 <= channels_0_ll_requestLl; - ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; - end - if(when_DmaSg_l1148) begin - ll_cmd_ptr <= (_zz_ll_cmd_ptr[0] ? channels_0_ll_ptr : channels_1_ll_ptr); - end - if(when_DmaSg_l1148_1) begin - ll_cmd_ptrNext <= (_zz_ll_cmd_ptrNext[0] ? channels_0_ll_ptrNext : channels_1_ll_ptrNext); - end - if(when_DmaSg_l1148_2) begin - ll_cmd_bytesDone <= channels_0_bytesProbe_value; - end - if(when_DmaSg_l1148_3) begin - ll_cmd_endOfPacket <= (_zz_ll_cmd_endOfPacket[0] ? channels_0_ll_packet : channels_1_ll_packet); - end - if(when_DmaSg_l1154) begin - ll_cmd_isJustASink <= ll_arbiter_isJustASink; - end - if(when_DmaSg_l1155) begin - ll_cmd_doDescriptorStall <= ll_arbiter_doDescriptorStall; - end - if(when_DmaSg_l1156) begin - ll_cmd_onSgStream <= ll_arbiter_onSgStream; - end - if(when_DmaSg_l1160) begin - ll_cmd_oh_0 <= channels_0_ll_requestLl; - ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; - if(channels_0_ll_requestLl) begin - channels_0_ll_waitDone <= 1'b1; - channels_0_ll_writeDone <= ll_arbiter_head; - channels_0_ll_justASync <= ll_arbiter_isJustASink; - channels_0_ll_packet <= 1'b0; - channels_0_ll_requireSync <= 1'b0; - if(when_DmaSg_l1169) begin - channels_0_ll_ptr <= channels_0_ll_ptrNext; - end - channels_0_ll_readDone <= ll_arbiter_isJustASink; - end - if(_zz_ll_arbiter_head_1) begin - channels_1_ll_waitDone <= 1'b1; - channels_1_ll_writeDone <= ll_arbiter_head; - channels_1_ll_justASync <= ll_arbiter_isJustASink; - channels_1_ll_packet <= 1'b0; - channels_1_ll_requireSync <= 1'b0; - if(when_DmaSg_l1169_1) begin - channels_1_ll_ptr <= channels_1_ll_ptrNext; - end - channels_1_ll_readDone <= ll_arbiter_isJustASink; - end - ll_cmd_readFired <= ll_arbiter_isJustASink; - ll_cmd_writeFired <= ll_arbiter_head; - end - if(io_sgRead_cmd_fire) begin - ll_cmd_readFired <= 1'b1; - end - if(io_sgWrite_cmd_fire) begin - ll_cmd_writeFired <= 1'b1; - end - if(io_sgRead_rsp_fire) begin - if(when_DmaSg_l1248) begin - if(ll_readRsp_oh_1) begin - channels_1_push_m2b_address <= io_sgRead_rsp_payload_fragment_data[95 : 64]; - end - end - if(when_DmaSg_l1248_1) begin - if(ll_readRsp_oh_0) begin - channels_0_pop_b2m_address <= io_sgRead_rsp_payload_fragment_data[31 : 0]; - end - end - if(when_DmaSg_l1248_2) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; - end - end - if(when_DmaSg_l1248_3) begin - if(ll_readRsp_oh_0) begin - channels_0_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; - end - if(ll_readRsp_oh_1) begin - channels_1_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; - end - end - if(when_DmaSg_l1248_4) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; - end - end - if(when_DmaSg_l1248_5) begin - if(ll_readRsp_oh_1) begin - channels_1_pop_b2s_last <= io_sgRead_rsp_payload_fragment_data[62]; - end - end - if(when_DmaSg_l1248_6) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; - end - end - if(when_DmaSg_l1271) begin - if(ll_readRsp_oh_0) begin - channels_0_ll_readDone <= 1'b1; - end - if(ll_readRsp_oh_1) begin - channels_1_ll_readDone <= 1'b1; - end - end - end - if(io_sgWrite_rsp_fire) begin - if(ll_writeRsp_oh_0) begin - channels_0_ll_writeDone <= 1'b1; - end - if(ll_writeRsp_oh_1) begin - channels_1_ll_writeDone <= 1'b1; - end - end - case(io_ctrl_PADDR) - 14'h000c : begin - if(ctrl_doWrite) begin - channels_0_push_memory <= io_ctrl_PWDATA[12]; - channels_0_push_s2b_completionOnLast <= io_ctrl_PWDATA[13]; - channels_0_push_s2b_waitFirst <= io_ctrl_PWDATA[14]; - end - end - 14'h001c : begin - if(ctrl_doWrite) begin - channels_0_pop_memory <= io_ctrl_PWDATA[12]; - end - end - 14'h002c : begin - if(ctrl_doWrite) begin - channels_0_channelStop <= io_ctrl_PWDATA[2]; - end - end - 14'h0020 : begin - if(ctrl_doWrite) begin - channels_0_bytes <= io_ctrl_PWDATA[25 : 0]; - end - end - 14'h008c : begin - if(ctrl_doWrite) begin - channels_1_push_memory <= io_ctrl_PWDATA[12]; - end - end - 14'h0098 : begin - if(ctrl_doWrite) begin - channels_1_pop_b2s_sinkId <= io_ctrl_PWDATA[19 : 16]; - end - end - 14'h009c : begin - if(ctrl_doWrite) begin - channels_1_pop_memory <= io_ctrl_PWDATA[12]; - channels_1_pop_b2s_last <= io_ctrl_PWDATA[13]; - end - end - 14'h00ac : begin - if(ctrl_doWrite) begin - channels_1_channelStop <= io_ctrl_PWDATA[2]; - end - end - 14'h00a0 : begin - if(ctrl_doWrite) begin - channels_1_bytes <= io_ctrl_PWDATA[25 : 0]; - end - end - default : begin - end - endcase - if(when_Apb3SlaveFactory_l81) begin - if(ctrl_doWrite) begin - channels_0_pop_b2m_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - if(when_Apb3SlaveFactory_l81_1) begin - if(ctrl_doWrite) begin - channels_0_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - if(when_Apb3SlaveFactory_l81_2) begin - if(ctrl_doWrite) begin - channels_1_push_m2b_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - if(when_Apb3SlaveFactory_l81_3) begin - if(ctrl_doWrite) begin - channels_1_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; - end - end - end - - -endmodule - -module EfxDMA_StreamArbiter_1 ( - input wire io_inputs_0_valid, - output wire io_inputs_0_ready, - input wire io_inputs_0_payload_last, - input wire [0:0] io_inputs_0_payload_fragment_source, - input wire [0:0] io_inputs_0_payload_fragment_opcode, - input wire [31:0] io_inputs_0_payload_fragment_address, - input wire [11:0] io_inputs_0_payload_fragment_length, - input wire [127:0] io_inputs_0_payload_fragment_data, - input wire [15:0] io_inputs_0_payload_fragment_mask, - input wire [12:0] io_inputs_0_payload_fragment_context, - input wire io_inputs_1_valid, - output wire io_inputs_1_ready, - input wire io_inputs_1_payload_last, - input wire [0:0] io_inputs_1_payload_fragment_source, - input wire [0:0] io_inputs_1_payload_fragment_opcode, - input wire [31:0] io_inputs_1_payload_fragment_address, - input wire [11:0] io_inputs_1_payload_fragment_length, - input wire [127:0] io_inputs_1_payload_fragment_data, - input wire [15:0] io_inputs_1_payload_fragment_mask, - input wire [12:0] io_inputs_1_payload_fragment_context, - output wire io_output_valid, - input wire io_output_ready, - output wire io_output_payload_last, - output wire [0:0] io_output_payload_fragment_source, - output wire [0:0] io_output_payload_fragment_opcode, - output wire [31:0] io_output_payload_fragment_address, - output wire [11:0] io_output_payload_fragment_length, - output wire [127:0] io_output_payload_fragment_data, - output wire [15:0] io_output_payload_fragment_mask, - output wire [12:0] io_output_payload_fragment_context, - output wire [0:0] io_chosen, - output wire [1:0] io_chosenOH, - input wire clk, - input wire reset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l683; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l683 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); - assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge clk) begin - if(reset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l683) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module EfxDMA_StreamArbiter ( - input wire io_inputs_0_valid, - output wire io_inputs_0_ready, - input wire io_inputs_0_payload_last, - input wire [0:0] io_inputs_0_payload_fragment_source, - input wire [0:0] io_inputs_0_payload_fragment_opcode, - input wire [31:0] io_inputs_0_payload_fragment_address, - input wire [11:0] io_inputs_0_payload_fragment_length, - input wire [20:0] io_inputs_0_payload_fragment_context, - input wire io_inputs_1_valid, - output wire io_inputs_1_ready, - input wire io_inputs_1_payload_last, - input wire [0:0] io_inputs_1_payload_fragment_source, - input wire [0:0] io_inputs_1_payload_fragment_opcode, - input wire [31:0] io_inputs_1_payload_fragment_address, - input wire [11:0] io_inputs_1_payload_fragment_length, - input wire [20:0] io_inputs_1_payload_fragment_context, - output wire io_output_valid, - input wire io_output_ready, - output wire io_output_payload_last, - output wire [0:0] io_output_payload_fragment_source, - output wire [0:0] io_output_payload_fragment_opcode, - output wire [31:0] io_output_payload_fragment_address, - output wire [11:0] io_output_payload_fragment_length, - output wire [20:0] io_output_payload_fragment_context, - output wire [0:0] io_chosen, - output wire [1:0] io_chosenOH, - input wire clk, - input wire reset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l683; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l683 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge clk) begin - if(reset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l683) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module EfxDMA_BufferCC_5 ( - input wire [4:0] io_dataIn, - output wire [4:0] io_dataOut, - input wire dat1_o_clk, - input wire dat1_o_reset -); - - (* async_reg = "true" *) reg [4:0] buffers_0; - (* async_reg = "true" *) reg [4:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge dat1_o_clk) begin - if(dat1_o_reset) begin - buffers_0 <= 5'h0; - buffers_1 <= 5'h0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -//EfxDMA_BufferCC_4 replaced by EfxDMA_BufferCC_3 - -module EfxDMA_BufferCC_3 ( - input wire [4:0] io_dataIn, - output wire [4:0] io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg [4:0] buffers_0; - (* async_reg = "true" *) reg [4:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 5'h0; - buffers_1 <= 5'h0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module EfxDMA_BufferCC_2 ( - input wire [4:0] io_dataIn, - output wire [4:0] io_dataOut, - input wire dat0_i_clk, - input wire dat0_i_reset -); - - (* async_reg = "true" *) reg [4:0] buffers_0; - (* async_reg = "true" *) reg [4:0] buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge dat0_i_clk) begin - if(dat0_i_reset) begin - buffers_0 <= 5'h0; - buffers_1 <= 5'h0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module EfxDMA_BmbContextRemover_1 ( - input wire io_input_cmd_valid, - output reg io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [127:0] io_input_cmd_payload_fragment_data, - input wire [15:0] io_input_cmd_payload_fragment_mask, - input wire [13:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [13:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - output wire [127:0] io_output_cmd_payload_fragment_data, - output wire [15:0] io_output_cmd_payload_fragment_mask, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire clk, - input wire reset -); - - reg fifoFork_thrown_translated_fifo_io_pop_ready; - wire fifoFork_thrown_translated_fifo_io_push_ready; - wire fifoFork_thrown_translated_fifo_io_pop_valid; - wire [13:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; - wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; - wire [2:0] fifoFork_thrown_translated_fifo_io_availability; - wire fifoFork_valid; - reg fifoFork_ready; - wire fifoFork_payload_last; - wire [0:0] fifoFork_payload_fragment_opcode; - wire [31:0] fifoFork_payload_fragment_address; - wire [11:0] fifoFork_payload_fragment_length; - wire [127:0] fifoFork_payload_fragment_data; - wire [15:0] fifoFork_payload_fragment_mask; - wire [13:0] fifoFork_payload_fragment_context; - wire cmdFork_valid; - wire cmdFork_ready; - wire cmdFork_payload_last; - wire [0:0] cmdFork_payload_fragment_opcode; - wire [31:0] cmdFork_payload_fragment_address; - wire [11:0] cmdFork_payload_fragment_length; - wire [127:0] cmdFork_payload_fragment_data; - wire [15:0] cmdFork_payload_fragment_mask; - wire [13:0] cmdFork_payload_fragment_context; - reg io_input_cmd_fork2_logic_linkEnable_0; - reg io_input_cmd_fork2_logic_linkEnable_1; - wire when_Stream_l1063; - wire when_Stream_l1063_1; - wire fifoFork_fire; - wire cmdFork_fire; - wire [13:0] pushCtx_context; - reg fifoFork_payload_first; - wire when_Stream_l445; - reg fifoFork_thrown_valid; - wire fifoFork_thrown_ready; - wire fifoFork_thrown_payload_last; - wire [0:0] fifoFork_thrown_payload_fragment_opcode; - wire [31:0] fifoFork_thrown_payload_fragment_address; - wire [11:0] fifoFork_thrown_payload_fragment_length; - wire [127:0] fifoFork_thrown_payload_fragment_data; - wire [15:0] fifoFork_thrown_payload_fragment_mask; - wire [13:0] fifoFork_thrown_payload_fragment_context; - wire fifoFork_thrown_translated_valid; - wire fifoFork_thrown_translated_ready; - wire [13:0] fifoFork_thrown_translated_payload_context; - wire popCtx_valid; - wire popCtx_ready; - wire [13:0] popCtx_payload_context; - reg fifoFork_thrown_translated_fifo_io_pop_rValid; - reg [13:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; - wire when_Stream_l375; - wire _zz_io_input_rsp_valid; - - EfxDMA_StreamFifo_1 fifoFork_thrown_translated_fifo ( - .io_push_valid (fifoFork_thrown_translated_valid ), //i - .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o - .io_push_payload_context (fifoFork_thrown_translated_payload_context[13:0] ), //i - .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o - .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i - .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[13:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o - .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - io_input_cmd_ready = 1'b1; - if(when_Stream_l1063) begin - io_input_cmd_ready = 1'b0; - end - if(when_Stream_l1063_1) begin - io_input_cmd_ready = 1'b0; - end - end - - assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); - assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); - assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); - assign fifoFork_payload_last = io_input_cmd_payload_last; - assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign fifoFork_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign fifoFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); - assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); - assign cmdFork_payload_last = io_input_cmd_payload_last; - assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign cmdFork_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign cmdFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); - assign io_output_cmd_valid = cmdFork_valid; - assign cmdFork_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = cmdFork_payload_last; - assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = cmdFork_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = cmdFork_payload_fragment_mask; - assign pushCtx_context = fifoFork_payload_fragment_context; - assign when_Stream_l445 = (! fifoFork_payload_first); - always @(*) begin - fifoFork_thrown_valid = fifoFork_valid; - if(when_Stream_l445) begin - fifoFork_thrown_valid = 1'b0; - end - end - - always @(*) begin - fifoFork_ready = fifoFork_thrown_ready; - if(when_Stream_l445) begin - fifoFork_ready = 1'b1; - end - end - - assign fifoFork_thrown_payload_last = fifoFork_payload_last; - assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; - assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; - assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; - assign fifoFork_thrown_payload_fragment_data = fifoFork_payload_fragment_data; - assign fifoFork_thrown_payload_fragment_mask = fifoFork_payload_fragment_mask; - assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; - assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; - assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; - assign fifoFork_thrown_translated_payload_context = pushCtx_context; - assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; - always @(*) begin - fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; - if(when_Stream_l375) begin - fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCtx_valid); - assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; - assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; - assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); - assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); - assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); - assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_context = popCtx_payload_context; - always @(posedge clk) begin - if(reset) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - fifoFork_payload_first <= 1'b1; - fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; - end else begin - if(fifoFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_cmd_ready) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - end - if(fifoFork_fire) begin - fifoFork_payload_first <= fifoFork_payload_last; - end - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; - end - end - end - - always @(posedge clk) begin - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; - end - end - - -endmodule - -module EfxDMA_BmbContextRemover ( - input wire io_input_cmd_valid, - output reg io_input_cmd_ready, - input wire io_input_cmd_payload_last, - input wire [0:0] io_input_cmd_payload_fragment_opcode, - input wire [31:0] io_input_cmd_payload_fragment_address, - input wire [11:0] io_input_cmd_payload_fragment_length, - input wire [21:0] io_input_cmd_payload_fragment_context, - output wire io_input_rsp_valid, - input wire io_input_rsp_ready, - output wire io_input_rsp_payload_last, - output wire [0:0] io_input_rsp_payload_fragment_opcode, - output wire [127:0] io_input_rsp_payload_fragment_data, - output wire [21:0] io_input_rsp_payload_fragment_context, - output wire io_output_cmd_valid, - input wire io_output_cmd_ready, - output wire io_output_cmd_payload_last, - output wire [0:0] io_output_cmd_payload_fragment_opcode, - output wire [31:0] io_output_cmd_payload_fragment_address, - output wire [11:0] io_output_cmd_payload_fragment_length, - input wire io_output_rsp_valid, - output wire io_output_rsp_ready, - input wire io_output_rsp_payload_last, - input wire [0:0] io_output_rsp_payload_fragment_opcode, - input wire [127:0] io_output_rsp_payload_fragment_data, - input wire clk, - input wire reset -); - - reg fifoFork_thrown_translated_fifo_io_pop_ready; - wire fifoFork_thrown_translated_fifo_io_push_ready; - wire fifoFork_thrown_translated_fifo_io_pop_valid; - wire [21:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; - wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; - wire [2:0] fifoFork_thrown_translated_fifo_io_availability; - wire fifoFork_valid; - reg fifoFork_ready; - wire fifoFork_payload_last; - wire [0:0] fifoFork_payload_fragment_opcode; - wire [31:0] fifoFork_payload_fragment_address; - wire [11:0] fifoFork_payload_fragment_length; - wire [21:0] fifoFork_payload_fragment_context; - wire cmdFork_valid; - wire cmdFork_ready; - wire cmdFork_payload_last; - wire [0:0] cmdFork_payload_fragment_opcode; - wire [31:0] cmdFork_payload_fragment_address; - wire [11:0] cmdFork_payload_fragment_length; - wire [21:0] cmdFork_payload_fragment_context; - reg io_input_cmd_fork2_logic_linkEnable_0; - reg io_input_cmd_fork2_logic_linkEnable_1; - wire when_Stream_l1063; - wire when_Stream_l1063_1; - wire fifoFork_fire; - wire cmdFork_fire; - wire [21:0] pushCtx_context; - reg fifoFork_payload_first; - wire when_Stream_l445; - reg fifoFork_thrown_valid; - wire fifoFork_thrown_ready; - wire fifoFork_thrown_payload_last; - wire [0:0] fifoFork_thrown_payload_fragment_opcode; - wire [31:0] fifoFork_thrown_payload_fragment_address; - wire [11:0] fifoFork_thrown_payload_fragment_length; - wire [21:0] fifoFork_thrown_payload_fragment_context; - wire fifoFork_thrown_translated_valid; - wire fifoFork_thrown_translated_ready; - wire [21:0] fifoFork_thrown_translated_payload_context; - wire popCtx_valid; - wire popCtx_ready; - wire [21:0] popCtx_payload_context; - reg fifoFork_thrown_translated_fifo_io_pop_rValid; - reg [21:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; - wire when_Stream_l375; - wire _zz_io_input_rsp_valid; - - EfxDMA_StreamFifo fifoFork_thrown_translated_fifo ( - .io_push_valid (fifoFork_thrown_translated_valid ), //i - .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o - .io_push_payload_context (fifoFork_thrown_translated_payload_context[21:0] ), //i - .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o - .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i - .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[21:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o - .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - io_input_cmd_ready = 1'b1; - if(when_Stream_l1063) begin - io_input_cmd_ready = 1'b0; - end - if(when_Stream_l1063_1) begin - io_input_cmd_ready = 1'b0; - end - end - - assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); - assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); - assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); - assign fifoFork_payload_last = io_input_cmd_payload_last; - assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); - assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); - assign cmdFork_payload_last = io_input_cmd_payload_last; - assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); - assign io_output_cmd_valid = cmdFork_valid; - assign cmdFork_ready = io_output_cmd_ready; - assign io_output_cmd_payload_last = cmdFork_payload_last; - assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; - assign pushCtx_context = fifoFork_payload_fragment_context; - assign when_Stream_l445 = (! fifoFork_payload_first); - always @(*) begin - fifoFork_thrown_valid = fifoFork_valid; - if(when_Stream_l445) begin - fifoFork_thrown_valid = 1'b0; - end - end - - always @(*) begin - fifoFork_ready = fifoFork_thrown_ready; - if(when_Stream_l445) begin - fifoFork_ready = 1'b1; - end - end - - assign fifoFork_thrown_payload_last = fifoFork_payload_last; - assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; - assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; - assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; - assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; - assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; - assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; - assign fifoFork_thrown_translated_payload_context = pushCtx_context; - assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; - always @(*) begin - fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; - if(when_Stream_l375) begin - fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! popCtx_valid); - assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; - assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; - assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); - assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); - assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); - assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = popCtx_payload_context; - always @(posedge clk) begin - if(reset) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - fifoFork_payload_first <= 1'b1; - fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; - end else begin - if(fifoFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdFork_fire) begin - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_cmd_ready) begin - io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; - io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; - end - if(fifoFork_fire) begin - fifoFork_payload_first <= fifoFork_payload_last; - end - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; - end - end - end - - always @(posedge clk) begin - if(fifoFork_thrown_translated_fifo_io_pop_ready) begin - fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; - end - end - - -endmodule - -module EfxDMA_FlowCCUnsafeByToggle_1 ( - input wire io_input_valid, - input wire [31:0] io_input_payload_PRDATA, - input wire io_input_payload_PSLVERROR, - output wire io_output_valid, - output wire [31:0] io_output_payload_PRDATA, - output wire io_output_payload_PSLVERROR, - input wire clk, - input wire reset, - input wire ctrl_clk, - input wire ctrl_reset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg [31:0] inputArea_data_PRDATA; - reg inputArea_data_PSLVERROR; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire [31:0] outputArea_flow_payload_PRDATA; - wire outputArea_flow_payload_PSLVERROR; - reg outputArea_flow_m2sPipe_valid; - (* async_reg = "true" *) reg [31:0] outputArea_flow_m2sPipe_payload_PRDATA; - (* async_reg = "true" *) reg outputArea_flow_m2sPipe_payload_PSLVERROR; - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_1 inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .ctrl_clk (ctrl_clk ), //i - .ctrl_reset (ctrl_reset ) //i - ); - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_PRDATA = inputArea_data_PRDATA; - assign outputArea_flow_payload_PSLVERROR = inputArea_data_PSLVERROR; - assign io_output_valid = outputArea_flow_m2sPipe_valid; - assign io_output_payload_PRDATA = outputArea_flow_m2sPipe_payload_PRDATA; - assign io_output_payload_PSLVERROR = outputArea_flow_m2sPipe_payload_PSLVERROR; - always @(posedge clk) begin - if(reset) begin - inputArea_target <= 1'b0; - end else begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - end - end - end - - always @(posedge clk) begin - if(io_input_valid) begin - inputArea_data_PRDATA <= io_input_payload_PRDATA; - inputArea_data_PSLVERROR <= io_input_payload_PSLVERROR; - end - end - - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - outputArea_flow_m2sPipe_valid <= 1'b0; - outputArea_hit <= 1'b0; - end else begin - outputArea_hit <= outputArea_target; - outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; - end - end - - always @(posedge ctrl_clk) begin - if(outputArea_flow_valid) begin - outputArea_flow_m2sPipe_payload_PRDATA <= outputArea_flow_payload_PRDATA; - outputArea_flow_m2sPipe_payload_PSLVERROR <= outputArea_flow_payload_PSLVERROR; - end - end - - -endmodule - -module EfxDMA_FlowCCUnsafeByToggle ( - input wire io_input_valid, - input wire [13:0] io_input_payload_PADDR, - input wire io_input_payload_PWRITE, - input wire [31:0] io_input_payload_PWDATA, - output wire io_output_valid, - output wire [13:0] io_output_payload_PADDR, - output wire io_output_payload_PWRITE, - output wire [31:0] io_output_payload_PWDATA, - input wire ctrl_clk, - input wire ctrl_reset, - input wire clk, - input wire reset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg [13:0] inputArea_data_PADDR; - reg inputArea_data_PWRITE; - reg [31:0] inputArea_data_PWDATA; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire [13:0] outputArea_flow_payload_PADDR; - wire outputArea_flow_payload_PWRITE; - wire [31:0] outputArea_flow_payload_PWDATA; - - (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .clk (clk ), //i - .reset (reset ) //i - ); - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_PADDR = inputArea_data_PADDR; - assign outputArea_flow_payload_PWRITE = inputArea_data_PWRITE; - assign outputArea_flow_payload_PWDATA = inputArea_data_PWDATA; - assign io_output_valid = outputArea_flow_valid; - assign io_output_payload_PADDR = outputArea_flow_payload_PADDR; - assign io_output_payload_PWRITE = outputArea_flow_payload_PWRITE; - assign io_output_payload_PWDATA = outputArea_flow_payload_PWDATA; - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - inputArea_target <= 1'b0; - end else begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - end - end - end - - always @(posedge ctrl_clk) begin - if(io_input_valid) begin - inputArea_data_PADDR <= io_input_payload_PADDR; - inputArea_data_PWRITE <= io_input_payload_PWRITE; - inputArea_data_PWDATA <= io_input_payload_PWDATA; - end - end - - always @(posedge clk) begin - if(reset) begin - outputArea_hit <= 1'b0; - end else begin - outputArea_hit <= outputArea_target; - end - end - - -endmodule - -module EfxDMA_Aggregator ( - input wire io_input_valid, - output reg io_input_ready, - input wire [127:0] io_input_payload_data, - input wire [15:0] io_input_payload_mask, - output reg [127:0] io_output_data, - output reg [15:0] io_output_mask, - input wire io_output_enough, - input wire io_output_consume, - output wire io_output_consumed, - input wire [3:0] io_output_lastByteUsed, - output wire [3:0] io_output_usedUntil, - input wire io_flush, - input wire [3:0] io_offset, - input wire [11:0] io_burstLength, - input wire clk, - input wire reset -); - - reg [0:0] _zz_s0_countOnesLogic_0_1; - wire [0:0] _zz_s0_countOnesLogic_0_2; - reg [1:0] _zz_s0_countOnesLogic_1_1; - wire [1:0] _zz_s0_countOnesLogic_1_2; - reg [1:0] _zz_s0_countOnesLogic_2_1; - wire [2:0] _zz_s0_countOnesLogic_2_2; - reg [2:0] _zz_s0_countOnesLogic_3_9; - wire [2:0] _zz_s0_countOnesLogic_3_10; - reg [2:0] _zz_s0_countOnesLogic_3_11; - wire [2:0] _zz_s0_countOnesLogic_3_12; - wire [0:0] _zz_s0_countOnesLogic_3_13; - reg [2:0] _zz_s0_countOnesLogic_4_9; - wire [2:0] _zz_s0_countOnesLogic_4_10; - reg [2:0] _zz_s0_countOnesLogic_4_11; - wire [2:0] _zz_s0_countOnesLogic_4_12; - wire [1:0] _zz_s0_countOnesLogic_4_13; - reg [2:0] _zz_s0_countOnesLogic_5_9; - wire [2:0] _zz_s0_countOnesLogic_5_10; - reg [2:0] _zz_s0_countOnesLogic_5_11; - wire [2:0] _zz_s0_countOnesLogic_5_12; - wire [2:0] _zz_s0_countOnesLogic_6_9; - reg [2:0] _zz_s0_countOnesLogic_6_10; - wire [2:0] _zz_s0_countOnesLogic_6_11; - reg [2:0] _zz_s0_countOnesLogic_6_12; - wire [2:0] _zz_s0_countOnesLogic_6_13; - reg [2:0] _zz_s0_countOnesLogic_6_14; - wire [2:0] _zz_s0_countOnesLogic_6_15; - wire [0:0] _zz_s0_countOnesLogic_6_16; - wire [3:0] _zz_s0_countOnesLogic_7_9; - reg [3:0] _zz_s0_countOnesLogic_7_10; - wire [2:0] _zz_s0_countOnesLogic_7_11; - reg [3:0] _zz_s0_countOnesLogic_7_12; - wire [2:0] _zz_s0_countOnesLogic_7_13; - reg [3:0] _zz_s0_countOnesLogic_7_14; - wire [2:0] _zz_s0_countOnesLogic_7_15; - wire [1:0] _zz_s0_countOnesLogic_7_16; - wire [3:0] _zz_s0_countOnesLogic_8_9; - reg [3:0] _zz_s0_countOnesLogic_8_10; - wire [2:0] _zz_s0_countOnesLogic_8_11; - reg [3:0] _zz_s0_countOnesLogic_8_12; - wire [2:0] _zz_s0_countOnesLogic_8_13; - reg [3:0] _zz_s0_countOnesLogic_8_14; - wire [2:0] _zz_s0_countOnesLogic_8_15; - wire [3:0] _zz_s0_countOnesLogic_9_9; - reg [3:0] _zz_s0_countOnesLogic_9_10; - wire [2:0] _zz_s0_countOnesLogic_9_11; - reg [3:0] _zz_s0_countOnesLogic_9_12; - wire [2:0] _zz_s0_countOnesLogic_9_13; - wire [3:0] _zz_s0_countOnesLogic_9_14; - reg [3:0] _zz_s0_countOnesLogic_9_15; - wire [2:0] _zz_s0_countOnesLogic_9_16; - reg [3:0] _zz_s0_countOnesLogic_9_17; - wire [2:0] _zz_s0_countOnesLogic_9_18; - wire [0:0] _zz_s0_countOnesLogic_9_19; - wire [3:0] _zz_s0_countOnesLogic_10_9; - reg [3:0] _zz_s0_countOnesLogic_10_10; - wire [2:0] _zz_s0_countOnesLogic_10_11; - reg [3:0] _zz_s0_countOnesLogic_10_12; - wire [2:0] _zz_s0_countOnesLogic_10_13; - wire [3:0] _zz_s0_countOnesLogic_10_14; - reg [3:0] _zz_s0_countOnesLogic_10_15; - wire [2:0] _zz_s0_countOnesLogic_10_16; - reg [3:0] _zz_s0_countOnesLogic_10_17; - wire [2:0] _zz_s0_countOnesLogic_10_18; - wire [1:0] _zz_s0_countOnesLogic_10_19; - wire [3:0] _zz_s0_countOnesLogic_11_9; - reg [3:0] _zz_s0_countOnesLogic_11_10; - wire [2:0] _zz_s0_countOnesLogic_11_11; - reg [3:0] _zz_s0_countOnesLogic_11_12; - wire [2:0] _zz_s0_countOnesLogic_11_13; - wire [3:0] _zz_s0_countOnesLogic_11_14; - reg [3:0] _zz_s0_countOnesLogic_11_15; - wire [2:0] _zz_s0_countOnesLogic_11_16; - reg [3:0] _zz_s0_countOnesLogic_11_17; - wire [2:0] _zz_s0_countOnesLogic_11_18; - wire [3:0] _zz_s0_countOnesLogic_12_9; - wire [3:0] _zz_s0_countOnesLogic_12_10; - reg [3:0] _zz_s0_countOnesLogic_12_11; - wire [2:0] _zz_s0_countOnesLogic_12_12; - reg [3:0] _zz_s0_countOnesLogic_12_13; - wire [2:0] _zz_s0_countOnesLogic_12_14; - wire [3:0] _zz_s0_countOnesLogic_12_15; - reg [3:0] _zz_s0_countOnesLogic_12_16; - wire [2:0] _zz_s0_countOnesLogic_12_17; - reg [3:0] _zz_s0_countOnesLogic_12_18; - wire [2:0] _zz_s0_countOnesLogic_12_19; - reg [3:0] _zz_s0_countOnesLogic_12_20; - wire [2:0] _zz_s0_countOnesLogic_12_21; - wire [0:0] _zz_s0_countOnesLogic_12_22; - wire [3:0] _zz_s0_countOnesLogic_13_9; - wire [3:0] _zz_s0_countOnesLogic_13_10; - reg [3:0] _zz_s0_countOnesLogic_13_11; - wire [2:0] _zz_s0_countOnesLogic_13_12; - reg [3:0] _zz_s0_countOnesLogic_13_13; - wire [2:0] _zz_s0_countOnesLogic_13_14; - wire [3:0] _zz_s0_countOnesLogic_13_15; - reg [3:0] _zz_s0_countOnesLogic_13_16; - wire [2:0] _zz_s0_countOnesLogic_13_17; - reg [3:0] _zz_s0_countOnesLogic_13_18; - wire [2:0] _zz_s0_countOnesLogic_13_19; - reg [3:0] _zz_s0_countOnesLogic_13_20; - wire [2:0] _zz_s0_countOnesLogic_13_21; - wire [1:0] _zz_s0_countOnesLogic_13_22; - wire [3:0] _zz_s0_countOnesLogic_14_9; - wire [3:0] _zz_s0_countOnesLogic_14_10; - reg [3:0] _zz_s0_countOnesLogic_14_11; - wire [2:0] _zz_s0_countOnesLogic_14_12; - reg [3:0] _zz_s0_countOnesLogic_14_13; - wire [2:0] _zz_s0_countOnesLogic_14_14; - wire [3:0] _zz_s0_countOnesLogic_14_15; - reg [3:0] _zz_s0_countOnesLogic_14_16; - wire [2:0] _zz_s0_countOnesLogic_14_17; - reg [3:0] _zz_s0_countOnesLogic_14_18; - wire [2:0] _zz_s0_countOnesLogic_14_19; - reg [3:0] _zz_s0_countOnesLogic_14_20; - wire [2:0] _zz_s0_countOnesLogic_14_21; - wire [4:0] _zz_s0_countOnesLogic_15_8; - wire [4:0] _zz_s0_countOnesLogic_15_9; - reg [4:0] _zz_s0_countOnesLogic_15_10; - wire [2:0] _zz_s0_countOnesLogic_15_11; - reg [4:0] _zz_s0_countOnesLogic_15_12; - wire [2:0] _zz_s0_countOnesLogic_15_13; - wire [4:0] _zz_s0_countOnesLogic_15_14; - reg [4:0] _zz_s0_countOnesLogic_15_15; - wire [2:0] _zz_s0_countOnesLogic_15_16; - reg [4:0] _zz_s0_countOnesLogic_15_17; - wire [2:0] _zz_s0_countOnesLogic_15_18; - wire [4:0] _zz_s0_countOnesLogic_15_19; - reg [4:0] _zz_s0_countOnesLogic_15_20; - wire [2:0] _zz_s0_countOnesLogic_15_21; - reg [4:0] _zz_s0_countOnesLogic_15_22; - wire [2:0] _zz_s0_countOnesLogic_15_23; - wire [0:0] _zz_s0_countOnesLogic_15_24; - wire [4:0] _zz_s1_offsetNext; - wire [12:0] _zz_s1_byteCounter; - wire [3:0] _zz_s1_inputIndexes_1; - wire [3:0] _zz_s1_inputIndexes_2; - wire [3:0] _zz_s1_inputIndexes_3; - wire [3:0] _zz_s1_inputIndexes_4; - wire [3:0] _zz_s1_inputIndexes_5; - wire [3:0] _zz_s1_inputIndexes_6; - wire [3:0] _zz_s1_inputIndexes_7; - wire [0:0] _zz_s1_outputPayload_selValid_240; - wire [6:0] _zz_s1_outputPayload_selValid_241; - wire [0:0] _zz_s1_outputPayload_selValid_242; - wire [6:0] _zz_s1_outputPayload_selValid_243; - wire [0:0] _zz_s1_outputPayload_selValid_244; - wire [6:0] _zz_s1_outputPayload_selValid_245; - wire [0:0] _zz_s1_outputPayload_selValid_246; - wire [6:0] _zz_s1_outputPayload_selValid_247; - wire [0:0] _zz_s1_outputPayload_selValid_248; - wire [6:0] _zz_s1_outputPayload_selValid_249; - wire [0:0] _zz_s1_outputPayload_selValid_250; - wire [6:0] _zz_s1_outputPayload_selValid_251; - wire [0:0] _zz_s1_outputPayload_selValid_252; - wire [6:0] _zz_s1_outputPayload_selValid_253; - wire [0:0] _zz_s1_outputPayload_selValid_254; - wire [6:0] _zz_s1_outputPayload_selValid_255; - wire [0:0] _zz_s1_outputPayload_selValid_256; - wire [6:0] _zz_s1_outputPayload_selValid_257; - wire [0:0] _zz_s1_outputPayload_selValid_258; - wire [6:0] _zz_s1_outputPayload_selValid_259; - wire [0:0] _zz_s1_outputPayload_selValid_260; - wire [6:0] _zz_s1_outputPayload_selValid_261; - wire [0:0] _zz_s1_outputPayload_selValid_262; - wire [6:0] _zz_s1_outputPayload_selValid_263; - wire [0:0] _zz_s1_outputPayload_selValid_264; - wire [6:0] _zz_s1_outputPayload_selValid_265; - wire [0:0] _zz_s1_outputPayload_selValid_266; - wire [6:0] _zz_s1_outputPayload_selValid_267; - wire [0:0] _zz_s1_outputPayload_selValid_268; - wire [6:0] _zz_s1_outputPayload_selValid_269; - wire [0:0] _zz_s1_outputPayload_selValid_270; - wire [6:0] _zz_s1_outputPayload_selValid_271; - wire [12:0] _zz_when_DmaSg_l1464; - reg [7:0] _zz_s2_byteLogic_0_inputData; - reg [7:0] _zz_s2_byteLogic_1_inputData; - reg [7:0] _zz_s2_byteLogic_2_inputData; - reg [7:0] _zz_s2_byteLogic_3_inputData; - reg [7:0] _zz_s2_byteLogic_4_inputData; - reg [7:0] _zz_s2_byteLogic_5_inputData; - reg [7:0] _zz_s2_byteLogic_6_inputData; - reg [7:0] _zz_s2_byteLogic_7_inputData; - reg [7:0] _zz_s2_byteLogic_8_inputData; - reg [7:0] _zz_s2_byteLogic_9_inputData; - reg [7:0] _zz_s2_byteLogic_10_inputData; - reg [7:0] _zz_s2_byteLogic_11_inputData; - reg [7:0] _zz_s2_byteLogic_12_inputData; - reg [7:0] _zz_s2_byteLogic_13_inputData; - reg [7:0] _zz_s2_byteLogic_14_inputData; - reg [7:0] _zz_s2_byteLogic_15_inputData; - reg [3:0] _zz_io_output_usedUntil_4; - wire [3:0] _zz_io_output_usedUntil_5; - wire s0_input_valid; - wire s0_input_ready; - wire [127:0] s0_input_payload_data; - wire [15:0] s0_input_payload_mask; - reg io_input_rValid; - reg [127:0] io_input_rData_data; - reg [15:0] io_input_rData_mask; - wire when_Stream_l375; - wire _zz_s0_countOnesLogic_0; - wire _zz_s0_countOnesLogic_1; - wire _zz_s0_countOnesLogic_2; - wire _zz_s0_countOnesLogic_3; - wire _zz_s0_countOnesLogic_4; - wire _zz_s0_countOnesLogic_5; - wire _zz_s0_countOnesLogic_6; - wire _zz_s0_countOnesLogic_7; - wire _zz_s0_countOnesLogic_8; - wire _zz_s0_countOnesLogic_9; - wire _zz_s0_countOnesLogic_10; - wire _zz_s0_countOnesLogic_11; - wire _zz_s0_countOnesLogic_12; - wire _zz_s0_countOnesLogic_13; - wire _zz_s0_countOnesLogic_14; - wire [0:0] s0_countOnesLogic_0; - wire [1:0] s0_countOnesLogic_1; - wire [1:0] s0_countOnesLogic_2; - wire [2:0] _zz_s0_countOnesLogic_3_1; - wire [2:0] _zz_s0_countOnesLogic_3_2; - wire [2:0] _zz_s0_countOnesLogic_3_3; - wire [2:0] _zz_s0_countOnesLogic_3_4; - wire [2:0] _zz_s0_countOnesLogic_3_5; - wire [2:0] _zz_s0_countOnesLogic_3_6; - wire [2:0] _zz_s0_countOnesLogic_3_7; - wire [2:0] _zz_s0_countOnesLogic_3_8; - wire [2:0] s0_countOnesLogic_3; - wire [2:0] _zz_s0_countOnesLogic_4_1; - wire [2:0] _zz_s0_countOnesLogic_4_2; - wire [2:0] _zz_s0_countOnesLogic_4_3; - wire [2:0] _zz_s0_countOnesLogic_4_4; - wire [2:0] _zz_s0_countOnesLogic_4_5; - wire [2:0] _zz_s0_countOnesLogic_4_6; - wire [2:0] _zz_s0_countOnesLogic_4_7; - wire [2:0] _zz_s0_countOnesLogic_4_8; - wire [2:0] s0_countOnesLogic_4; - wire [2:0] _zz_s0_countOnesLogic_5_1; - wire [2:0] _zz_s0_countOnesLogic_5_2; - wire [2:0] _zz_s0_countOnesLogic_5_3; - wire [2:0] _zz_s0_countOnesLogic_5_4; - wire [2:0] _zz_s0_countOnesLogic_5_5; - wire [2:0] _zz_s0_countOnesLogic_5_6; - wire [2:0] _zz_s0_countOnesLogic_5_7; - wire [2:0] _zz_s0_countOnesLogic_5_8; - wire [2:0] s0_countOnesLogic_5; - wire [2:0] _zz_s0_countOnesLogic_6_1; - wire [2:0] _zz_s0_countOnesLogic_6_2; - wire [2:0] _zz_s0_countOnesLogic_6_3; - wire [2:0] _zz_s0_countOnesLogic_6_4; - wire [2:0] _zz_s0_countOnesLogic_6_5; - wire [2:0] _zz_s0_countOnesLogic_6_6; - wire [2:0] _zz_s0_countOnesLogic_6_7; - wire [2:0] _zz_s0_countOnesLogic_6_8; - wire [2:0] s0_countOnesLogic_6; - wire [3:0] _zz_s0_countOnesLogic_7_1; - wire [3:0] _zz_s0_countOnesLogic_7_2; - wire [3:0] _zz_s0_countOnesLogic_7_3; - wire [3:0] _zz_s0_countOnesLogic_7_4; - wire [3:0] _zz_s0_countOnesLogic_7_5; - wire [3:0] _zz_s0_countOnesLogic_7_6; - wire [3:0] _zz_s0_countOnesLogic_7_7; - wire [3:0] _zz_s0_countOnesLogic_7_8; - wire [3:0] s0_countOnesLogic_7; - wire [3:0] _zz_s0_countOnesLogic_8_1; - wire [3:0] _zz_s0_countOnesLogic_8_2; - wire [3:0] _zz_s0_countOnesLogic_8_3; - wire [3:0] _zz_s0_countOnesLogic_8_4; - wire [3:0] _zz_s0_countOnesLogic_8_5; - wire [3:0] _zz_s0_countOnesLogic_8_6; - wire [3:0] _zz_s0_countOnesLogic_8_7; - wire [3:0] _zz_s0_countOnesLogic_8_8; - wire [3:0] s0_countOnesLogic_8; - wire [3:0] _zz_s0_countOnesLogic_9_1; - wire [3:0] _zz_s0_countOnesLogic_9_2; - wire [3:0] _zz_s0_countOnesLogic_9_3; - wire [3:0] _zz_s0_countOnesLogic_9_4; - wire [3:0] _zz_s0_countOnesLogic_9_5; - wire [3:0] _zz_s0_countOnesLogic_9_6; - wire [3:0] _zz_s0_countOnesLogic_9_7; - wire [3:0] _zz_s0_countOnesLogic_9_8; - wire [3:0] s0_countOnesLogic_9; - wire [3:0] _zz_s0_countOnesLogic_10_1; - wire [3:0] _zz_s0_countOnesLogic_10_2; - wire [3:0] _zz_s0_countOnesLogic_10_3; - wire [3:0] _zz_s0_countOnesLogic_10_4; - wire [3:0] _zz_s0_countOnesLogic_10_5; - wire [3:0] _zz_s0_countOnesLogic_10_6; - wire [3:0] _zz_s0_countOnesLogic_10_7; - wire [3:0] _zz_s0_countOnesLogic_10_8; - wire [3:0] s0_countOnesLogic_10; - wire [3:0] _zz_s0_countOnesLogic_11_1; - wire [3:0] _zz_s0_countOnesLogic_11_2; - wire [3:0] _zz_s0_countOnesLogic_11_3; - wire [3:0] _zz_s0_countOnesLogic_11_4; - wire [3:0] _zz_s0_countOnesLogic_11_5; - wire [3:0] _zz_s0_countOnesLogic_11_6; - wire [3:0] _zz_s0_countOnesLogic_11_7; - wire [3:0] _zz_s0_countOnesLogic_11_8; - wire [3:0] s0_countOnesLogic_11; - wire [3:0] _zz_s0_countOnesLogic_12_1; - wire [3:0] _zz_s0_countOnesLogic_12_2; - wire [3:0] _zz_s0_countOnesLogic_12_3; - wire [3:0] _zz_s0_countOnesLogic_12_4; - wire [3:0] _zz_s0_countOnesLogic_12_5; - wire [3:0] _zz_s0_countOnesLogic_12_6; - wire [3:0] _zz_s0_countOnesLogic_12_7; - wire [3:0] _zz_s0_countOnesLogic_12_8; - wire [3:0] s0_countOnesLogic_12; - wire [3:0] _zz_s0_countOnesLogic_13_1; - wire [3:0] _zz_s0_countOnesLogic_13_2; - wire [3:0] _zz_s0_countOnesLogic_13_3; - wire [3:0] _zz_s0_countOnesLogic_13_4; - wire [3:0] _zz_s0_countOnesLogic_13_5; - wire [3:0] _zz_s0_countOnesLogic_13_6; - wire [3:0] _zz_s0_countOnesLogic_13_7; - wire [3:0] _zz_s0_countOnesLogic_13_8; - wire [3:0] s0_countOnesLogic_13; - wire [3:0] _zz_s0_countOnesLogic_14_1; - wire [3:0] _zz_s0_countOnesLogic_14_2; - wire [3:0] _zz_s0_countOnesLogic_14_3; - wire [3:0] _zz_s0_countOnesLogic_14_4; - wire [3:0] _zz_s0_countOnesLogic_14_5; - wire [3:0] _zz_s0_countOnesLogic_14_6; - wire [3:0] _zz_s0_countOnesLogic_14_7; - wire [3:0] _zz_s0_countOnesLogic_14_8; - wire [3:0] s0_countOnesLogic_14; - wire [4:0] _zz_s0_countOnesLogic_15; - wire [4:0] _zz_s0_countOnesLogic_15_1; - wire [4:0] _zz_s0_countOnesLogic_15_2; - wire [4:0] _zz_s0_countOnesLogic_15_3; - wire [4:0] _zz_s0_countOnesLogic_15_4; - wire [4:0] _zz_s0_countOnesLogic_15_5; - wire [4:0] _zz_s0_countOnesLogic_15_6; - wire [4:0] _zz_s0_countOnesLogic_15_7; - wire [4:0] s0_countOnesLogic_15; - wire [127:0] s0_outputPayload_cmd_data; - wire [15:0] s0_outputPayload_cmd_mask; - wire [0:0] s0_outputPayload_countOnes_0; - wire [1:0] s0_outputPayload_countOnes_1; - wire [1:0] s0_outputPayload_countOnes_2; - wire [2:0] s0_outputPayload_countOnes_3; - wire [2:0] s0_outputPayload_countOnes_4; - wire [2:0] s0_outputPayload_countOnes_5; - wire [2:0] s0_outputPayload_countOnes_6; - wire [3:0] s0_outputPayload_countOnes_7; - wire [3:0] s0_outputPayload_countOnes_8; - wire [3:0] s0_outputPayload_countOnes_9; - wire [3:0] s0_outputPayload_countOnes_10; - wire [3:0] s0_outputPayload_countOnes_11; - wire [3:0] s0_outputPayload_countOnes_12; - wire [3:0] s0_outputPayload_countOnes_13; - wire [3:0] s0_outputPayload_countOnes_14; - wire [4:0] s0_outputPayload_countOnes_15; - wire s0_output_valid; - reg s0_output_ready; - wire [127:0] s0_output_payload_cmd_data; - wire [15:0] s0_output_payload_cmd_mask; - wire [0:0] s0_output_payload_countOnes_0; - wire [1:0] s0_output_payload_countOnes_1; - wire [1:0] s0_output_payload_countOnes_2; - wire [2:0] s0_output_payload_countOnes_3; - wire [2:0] s0_output_payload_countOnes_4; - wire [2:0] s0_output_payload_countOnes_5; - wire [2:0] s0_output_payload_countOnes_6; - wire [3:0] s0_output_payload_countOnes_7; - wire [3:0] s0_output_payload_countOnes_8; - wire [3:0] s0_output_payload_countOnes_9; - wire [3:0] s0_output_payload_countOnes_10; - wire [3:0] s0_output_payload_countOnes_11; - wire [3:0] s0_output_payload_countOnes_12; - wire [3:0] s0_output_payload_countOnes_13; - wire [3:0] s0_output_payload_countOnes_14; - wire [4:0] s0_output_payload_countOnes_15; - wire s1_input_valid; - wire s1_input_ready; - wire [127:0] s1_input_payload_cmd_data; - wire [15:0] s1_input_payload_cmd_mask; - wire [0:0] s1_input_payload_countOnes_0; - wire [1:0] s1_input_payload_countOnes_1; - wire [1:0] s1_input_payload_countOnes_2; - wire [2:0] s1_input_payload_countOnes_3; - wire [2:0] s1_input_payload_countOnes_4; - wire [2:0] s1_input_payload_countOnes_5; - wire [2:0] s1_input_payload_countOnes_6; - wire [3:0] s1_input_payload_countOnes_7; - wire [3:0] s1_input_payload_countOnes_8; - wire [3:0] s1_input_payload_countOnes_9; - wire [3:0] s1_input_payload_countOnes_10; - wire [3:0] s1_input_payload_countOnes_11; - wire [3:0] s1_input_payload_countOnes_12; - wire [3:0] s1_input_payload_countOnes_13; - wire [3:0] s1_input_payload_countOnes_14; - wire [4:0] s1_input_payload_countOnes_15; - reg s0_output_rValid; - reg [127:0] s0_output_rData_cmd_data; - reg [15:0] s0_output_rData_cmd_mask; - reg [0:0] s0_output_rData_countOnes_0; - reg [1:0] s0_output_rData_countOnes_1; - reg [1:0] s0_output_rData_countOnes_2; - reg [2:0] s0_output_rData_countOnes_3; - reg [2:0] s0_output_rData_countOnes_4; - reg [2:0] s0_output_rData_countOnes_5; - reg [2:0] s0_output_rData_countOnes_6; - reg [3:0] s0_output_rData_countOnes_7; - reg [3:0] s0_output_rData_countOnes_8; - reg [3:0] s0_output_rData_countOnes_9; - reg [3:0] s0_output_rData_countOnes_10; - reg [3:0] s0_output_rData_countOnes_11; - reg [3:0] s0_output_rData_countOnes_12; - reg [3:0] s0_output_rData_countOnes_13; - reg [3:0] s0_output_rData_countOnes_14; - reg [4:0] s0_output_rData_countOnes_15; - wire when_Stream_l375_1; - reg [3:0] s1_offset; - wire [4:0] s1_offsetNext; - wire s1_input_fire; - reg [12:0] s1_byteCounter; - wire [3:0] s1_inputIndexes_0; - wire [3:0] s1_inputIndexes_1; - wire [3:0] s1_inputIndexes_2; - wire [3:0] s1_inputIndexes_3; - wire [3:0] s1_inputIndexes_4; - wire [3:0] s1_inputIndexes_5; - wire [3:0] s1_inputIndexes_6; - wire [3:0] s1_inputIndexes_7; - wire [3:0] s1_inputIndexes_8; - wire [3:0] s1_inputIndexes_9; - wire [3:0] s1_inputIndexes_10; - wire [3:0] s1_inputIndexes_11; - wire [3:0] s1_inputIndexes_12; - wire [3:0] s1_inputIndexes_13; - wire [3:0] s1_inputIndexes_14; - wire [3:0] s1_inputIndexes_15; - wire [127:0] s1_outputPayload_cmd_data; - wire [15:0] s1_outputPayload_cmd_mask; - wire [3:0] s1_outputPayload_index_0; - wire [3:0] s1_outputPayload_index_1; - wire [3:0] s1_outputPayload_index_2; - wire [3:0] s1_outputPayload_index_3; - wire [3:0] s1_outputPayload_index_4; - wire [3:0] s1_outputPayload_index_5; - wire [3:0] s1_outputPayload_index_6; - wire [3:0] s1_outputPayload_index_7; - wire [3:0] s1_outputPayload_index_8; - wire [3:0] s1_outputPayload_index_9; - wire [3:0] s1_outputPayload_index_10; - wire [3:0] s1_outputPayload_index_11; - wire [3:0] s1_outputPayload_index_12; - wire [3:0] s1_outputPayload_index_13; - wire [3:0] s1_outputPayload_index_14; - wire [3:0] s1_outputPayload_index_15; - wire s1_outputPayload_last; - wire [3:0] s1_outputPayload_sel_0; - wire [3:0] s1_outputPayload_sel_1; - wire [3:0] s1_outputPayload_sel_2; - wire [3:0] s1_outputPayload_sel_3; - wire [3:0] s1_outputPayload_sel_4; - wire [3:0] s1_outputPayload_sel_5; - wire [3:0] s1_outputPayload_sel_6; - wire [3:0] s1_outputPayload_sel_7; - wire [3:0] s1_outputPayload_sel_8; - wire [3:0] s1_outputPayload_sel_9; - wire [3:0] s1_outputPayload_sel_10; - wire [3:0] s1_outputPayload_sel_11; - wire [3:0] s1_outputPayload_sel_12; - wire [3:0] s1_outputPayload_sel_13; - wire [3:0] s1_outputPayload_sel_14; - wire [3:0] s1_outputPayload_sel_15; - reg [15:0] s1_outputPayload_selValid; - wire _zz_s1_outputPayload_selValid; - wire _zz_s1_outputPayload_selValid_1; - wire _zz_s1_outputPayload_selValid_2; - wire _zz_s1_outputPayload_selValid_3; - wire _zz_s1_outputPayload_selValid_4; - wire _zz_s1_outputPayload_selValid_5; - wire _zz_s1_outputPayload_selValid_6; - wire _zz_s1_outputPayload_selValid_7; - wire _zz_s1_outputPayload_selValid_8; - wire _zz_s1_outputPayload_selValid_9; - wire _zz_s1_outputPayload_selValid_10; - wire _zz_s1_outputPayload_selValid_11; - wire _zz_s1_outputPayload_selValid_12; - wire _zz_s1_outputPayload_selValid_13; - wire _zz_s1_outputPayload_selValid_14; - wire _zz_s1_outputPayload_sel_0; - wire _zz_s1_outputPayload_sel_0_1; - wire _zz_s1_outputPayload_sel_0_2; - wire _zz_s1_outputPayload_sel_0_3; - wire _zz_s1_outputPayload_selValid_15; - wire _zz_s1_outputPayload_selValid_16; - wire _zz_s1_outputPayload_selValid_17; - wire _zz_s1_outputPayload_selValid_18; - wire _zz_s1_outputPayload_selValid_19; - wire _zz_s1_outputPayload_selValid_20; - wire _zz_s1_outputPayload_selValid_21; - wire _zz_s1_outputPayload_selValid_22; - wire _zz_s1_outputPayload_selValid_23; - wire _zz_s1_outputPayload_selValid_24; - wire _zz_s1_outputPayload_selValid_25; - wire _zz_s1_outputPayload_selValid_26; - wire _zz_s1_outputPayload_selValid_27; - wire _zz_s1_outputPayload_selValid_28; - wire _zz_s1_outputPayload_selValid_29; - wire _zz_s1_outputPayload_sel_1; - wire _zz_s1_outputPayload_sel_1_1; - wire _zz_s1_outputPayload_sel_1_2; - wire _zz_s1_outputPayload_sel_1_3; - wire _zz_s1_outputPayload_selValid_30; - wire _zz_s1_outputPayload_selValid_31; - wire _zz_s1_outputPayload_selValid_32; - wire _zz_s1_outputPayload_selValid_33; - wire _zz_s1_outputPayload_selValid_34; - wire _zz_s1_outputPayload_selValid_35; - wire _zz_s1_outputPayload_selValid_36; - wire _zz_s1_outputPayload_selValid_37; - wire _zz_s1_outputPayload_selValid_38; - wire _zz_s1_outputPayload_selValid_39; - wire _zz_s1_outputPayload_selValid_40; - wire _zz_s1_outputPayload_selValid_41; - wire _zz_s1_outputPayload_selValid_42; - wire _zz_s1_outputPayload_selValid_43; - wire _zz_s1_outputPayload_selValid_44; - wire _zz_s1_outputPayload_sel_2; - wire _zz_s1_outputPayload_sel_2_1; - wire _zz_s1_outputPayload_sel_2_2; - wire _zz_s1_outputPayload_sel_2_3; - wire _zz_s1_outputPayload_selValid_45; - wire _zz_s1_outputPayload_selValid_46; - wire _zz_s1_outputPayload_selValid_47; - wire _zz_s1_outputPayload_selValid_48; - wire _zz_s1_outputPayload_selValid_49; - wire _zz_s1_outputPayload_selValid_50; - wire _zz_s1_outputPayload_selValid_51; - wire _zz_s1_outputPayload_selValid_52; - wire _zz_s1_outputPayload_selValid_53; - wire _zz_s1_outputPayload_selValid_54; - wire _zz_s1_outputPayload_selValid_55; - wire _zz_s1_outputPayload_selValid_56; - wire _zz_s1_outputPayload_selValid_57; - wire _zz_s1_outputPayload_selValid_58; - wire _zz_s1_outputPayload_selValid_59; - wire _zz_s1_outputPayload_sel_3; - wire _zz_s1_outputPayload_sel_3_1; - wire _zz_s1_outputPayload_sel_3_2; - wire _zz_s1_outputPayload_sel_3_3; - wire _zz_s1_outputPayload_selValid_60; - wire _zz_s1_outputPayload_selValid_61; - wire _zz_s1_outputPayload_selValid_62; - wire _zz_s1_outputPayload_selValid_63; - wire _zz_s1_outputPayload_selValid_64; - wire _zz_s1_outputPayload_selValid_65; - wire _zz_s1_outputPayload_selValid_66; - wire _zz_s1_outputPayload_selValid_67; - wire _zz_s1_outputPayload_selValid_68; - wire _zz_s1_outputPayload_selValid_69; - wire _zz_s1_outputPayload_selValid_70; - wire _zz_s1_outputPayload_selValid_71; - wire _zz_s1_outputPayload_selValid_72; - wire _zz_s1_outputPayload_selValid_73; - wire _zz_s1_outputPayload_selValid_74; - wire _zz_s1_outputPayload_sel_4; - wire _zz_s1_outputPayload_sel_4_1; - wire _zz_s1_outputPayload_sel_4_2; - wire _zz_s1_outputPayload_sel_4_3; - wire _zz_s1_outputPayload_selValid_75; - wire _zz_s1_outputPayload_selValid_76; - wire _zz_s1_outputPayload_selValid_77; - wire _zz_s1_outputPayload_selValid_78; - wire _zz_s1_outputPayload_selValid_79; - wire _zz_s1_outputPayload_selValid_80; - wire _zz_s1_outputPayload_selValid_81; - wire _zz_s1_outputPayload_selValid_82; - wire _zz_s1_outputPayload_selValid_83; - wire _zz_s1_outputPayload_selValid_84; - wire _zz_s1_outputPayload_selValid_85; - wire _zz_s1_outputPayload_selValid_86; - wire _zz_s1_outputPayload_selValid_87; - wire _zz_s1_outputPayload_selValid_88; - wire _zz_s1_outputPayload_selValid_89; - wire _zz_s1_outputPayload_sel_5; - wire _zz_s1_outputPayload_sel_5_1; - wire _zz_s1_outputPayload_sel_5_2; - wire _zz_s1_outputPayload_sel_5_3; - wire _zz_s1_outputPayload_selValid_90; - wire _zz_s1_outputPayload_selValid_91; - wire _zz_s1_outputPayload_selValid_92; - wire _zz_s1_outputPayload_selValid_93; - wire _zz_s1_outputPayload_selValid_94; - wire _zz_s1_outputPayload_selValid_95; - wire _zz_s1_outputPayload_selValid_96; - wire _zz_s1_outputPayload_selValid_97; - wire _zz_s1_outputPayload_selValid_98; - wire _zz_s1_outputPayload_selValid_99; - wire _zz_s1_outputPayload_selValid_100; - wire _zz_s1_outputPayload_selValid_101; - wire _zz_s1_outputPayload_selValid_102; - wire _zz_s1_outputPayload_selValid_103; - wire _zz_s1_outputPayload_selValid_104; - wire _zz_s1_outputPayload_sel_6; - wire _zz_s1_outputPayload_sel_6_1; - wire _zz_s1_outputPayload_sel_6_2; - wire _zz_s1_outputPayload_sel_6_3; - wire _zz_s1_outputPayload_selValid_105; - wire _zz_s1_outputPayload_selValid_106; - wire _zz_s1_outputPayload_selValid_107; - wire _zz_s1_outputPayload_selValid_108; - wire _zz_s1_outputPayload_selValid_109; - wire _zz_s1_outputPayload_selValid_110; - wire _zz_s1_outputPayload_selValid_111; - wire _zz_s1_outputPayload_selValid_112; - wire _zz_s1_outputPayload_selValid_113; - wire _zz_s1_outputPayload_selValid_114; - wire _zz_s1_outputPayload_selValid_115; - wire _zz_s1_outputPayload_selValid_116; - wire _zz_s1_outputPayload_selValid_117; - wire _zz_s1_outputPayload_selValid_118; - wire _zz_s1_outputPayload_selValid_119; - wire _zz_s1_outputPayload_sel_7; - wire _zz_s1_outputPayload_sel_7_1; - wire _zz_s1_outputPayload_sel_7_2; - wire _zz_s1_outputPayload_sel_7_3; - wire _zz_s1_outputPayload_selValid_120; - wire _zz_s1_outputPayload_selValid_121; - wire _zz_s1_outputPayload_selValid_122; - wire _zz_s1_outputPayload_selValid_123; - wire _zz_s1_outputPayload_selValid_124; - wire _zz_s1_outputPayload_selValid_125; - wire _zz_s1_outputPayload_selValid_126; - wire _zz_s1_outputPayload_selValid_127; - wire _zz_s1_outputPayload_selValid_128; - wire _zz_s1_outputPayload_selValid_129; - wire _zz_s1_outputPayload_selValid_130; - wire _zz_s1_outputPayload_selValid_131; - wire _zz_s1_outputPayload_selValid_132; - wire _zz_s1_outputPayload_selValid_133; - wire _zz_s1_outputPayload_selValid_134; - wire _zz_s1_outputPayload_sel_8; - wire _zz_s1_outputPayload_sel_8_1; - wire _zz_s1_outputPayload_sel_8_2; - wire _zz_s1_outputPayload_sel_8_3; - wire _zz_s1_outputPayload_selValid_135; - wire _zz_s1_outputPayload_selValid_136; - wire _zz_s1_outputPayload_selValid_137; - wire _zz_s1_outputPayload_selValid_138; - wire _zz_s1_outputPayload_selValid_139; - wire _zz_s1_outputPayload_selValid_140; - wire _zz_s1_outputPayload_selValid_141; - wire _zz_s1_outputPayload_selValid_142; - wire _zz_s1_outputPayload_selValid_143; - wire _zz_s1_outputPayload_selValid_144; - wire _zz_s1_outputPayload_selValid_145; - wire _zz_s1_outputPayload_selValid_146; - wire _zz_s1_outputPayload_selValid_147; - wire _zz_s1_outputPayload_selValid_148; - wire _zz_s1_outputPayload_selValid_149; - wire _zz_s1_outputPayload_sel_9; - wire _zz_s1_outputPayload_sel_9_1; - wire _zz_s1_outputPayload_sel_9_2; - wire _zz_s1_outputPayload_sel_9_3; - wire _zz_s1_outputPayload_selValid_150; - wire _zz_s1_outputPayload_selValid_151; - wire _zz_s1_outputPayload_selValid_152; - wire _zz_s1_outputPayload_selValid_153; - wire _zz_s1_outputPayload_selValid_154; - wire _zz_s1_outputPayload_selValid_155; - wire _zz_s1_outputPayload_selValid_156; - wire _zz_s1_outputPayload_selValid_157; - wire _zz_s1_outputPayload_selValid_158; - wire _zz_s1_outputPayload_selValid_159; - wire _zz_s1_outputPayload_selValid_160; - wire _zz_s1_outputPayload_selValid_161; - wire _zz_s1_outputPayload_selValid_162; - wire _zz_s1_outputPayload_selValid_163; - wire _zz_s1_outputPayload_selValid_164; - wire _zz_s1_outputPayload_sel_10; - wire _zz_s1_outputPayload_sel_10_1; - wire _zz_s1_outputPayload_sel_10_2; - wire _zz_s1_outputPayload_sel_10_3; - wire _zz_s1_outputPayload_selValid_165; - wire _zz_s1_outputPayload_selValid_166; - wire _zz_s1_outputPayload_selValid_167; - wire _zz_s1_outputPayload_selValid_168; - wire _zz_s1_outputPayload_selValid_169; - wire _zz_s1_outputPayload_selValid_170; - wire _zz_s1_outputPayload_selValid_171; - wire _zz_s1_outputPayload_selValid_172; - wire _zz_s1_outputPayload_selValid_173; - wire _zz_s1_outputPayload_selValid_174; - wire _zz_s1_outputPayload_selValid_175; - wire _zz_s1_outputPayload_selValid_176; - wire _zz_s1_outputPayload_selValid_177; - wire _zz_s1_outputPayload_selValid_178; - wire _zz_s1_outputPayload_selValid_179; - wire _zz_s1_outputPayload_sel_11; - wire _zz_s1_outputPayload_sel_11_1; - wire _zz_s1_outputPayload_sel_11_2; - wire _zz_s1_outputPayload_sel_11_3; - wire _zz_s1_outputPayload_selValid_180; - wire _zz_s1_outputPayload_selValid_181; - wire _zz_s1_outputPayload_selValid_182; - wire _zz_s1_outputPayload_selValid_183; - wire _zz_s1_outputPayload_selValid_184; - wire _zz_s1_outputPayload_selValid_185; - wire _zz_s1_outputPayload_selValid_186; - wire _zz_s1_outputPayload_selValid_187; - wire _zz_s1_outputPayload_selValid_188; - wire _zz_s1_outputPayload_selValid_189; - wire _zz_s1_outputPayload_selValid_190; - wire _zz_s1_outputPayload_selValid_191; - wire _zz_s1_outputPayload_selValid_192; - wire _zz_s1_outputPayload_selValid_193; - wire _zz_s1_outputPayload_selValid_194; - wire _zz_s1_outputPayload_sel_12; - wire _zz_s1_outputPayload_sel_12_1; - wire _zz_s1_outputPayload_sel_12_2; - wire _zz_s1_outputPayload_sel_12_3; - wire _zz_s1_outputPayload_selValid_195; - wire _zz_s1_outputPayload_selValid_196; - wire _zz_s1_outputPayload_selValid_197; - wire _zz_s1_outputPayload_selValid_198; - wire _zz_s1_outputPayload_selValid_199; - wire _zz_s1_outputPayload_selValid_200; - wire _zz_s1_outputPayload_selValid_201; - wire _zz_s1_outputPayload_selValid_202; - wire _zz_s1_outputPayload_selValid_203; - wire _zz_s1_outputPayload_selValid_204; - wire _zz_s1_outputPayload_selValid_205; - wire _zz_s1_outputPayload_selValid_206; - wire _zz_s1_outputPayload_selValid_207; - wire _zz_s1_outputPayload_selValid_208; - wire _zz_s1_outputPayload_selValid_209; - wire _zz_s1_outputPayload_sel_13; - wire _zz_s1_outputPayload_sel_13_1; - wire _zz_s1_outputPayload_sel_13_2; - wire _zz_s1_outputPayload_sel_13_3; - wire _zz_s1_outputPayload_selValid_210; - wire _zz_s1_outputPayload_selValid_211; - wire _zz_s1_outputPayload_selValid_212; - wire _zz_s1_outputPayload_selValid_213; - wire _zz_s1_outputPayload_selValid_214; - wire _zz_s1_outputPayload_selValid_215; - wire _zz_s1_outputPayload_selValid_216; - wire _zz_s1_outputPayload_selValid_217; - wire _zz_s1_outputPayload_selValid_218; - wire _zz_s1_outputPayload_selValid_219; - wire _zz_s1_outputPayload_selValid_220; - wire _zz_s1_outputPayload_selValid_221; - wire _zz_s1_outputPayload_selValid_222; - wire _zz_s1_outputPayload_selValid_223; - wire _zz_s1_outputPayload_selValid_224; - wire _zz_s1_outputPayload_sel_14; - wire _zz_s1_outputPayload_sel_14_1; - wire _zz_s1_outputPayload_sel_14_2; - wire _zz_s1_outputPayload_sel_14_3; - wire _zz_s1_outputPayload_selValid_225; - wire _zz_s1_outputPayload_selValid_226; - wire _zz_s1_outputPayload_selValid_227; - wire _zz_s1_outputPayload_selValid_228; - wire _zz_s1_outputPayload_selValid_229; - wire _zz_s1_outputPayload_selValid_230; - wire _zz_s1_outputPayload_selValid_231; - wire _zz_s1_outputPayload_selValid_232; - wire _zz_s1_outputPayload_selValid_233; - wire _zz_s1_outputPayload_selValid_234; - wire _zz_s1_outputPayload_selValid_235; - wire _zz_s1_outputPayload_selValid_236; - wire _zz_s1_outputPayload_selValid_237; - wire _zz_s1_outputPayload_selValid_238; - wire _zz_s1_outputPayload_selValid_239; - wire _zz_s1_outputPayload_sel_15; - wire _zz_s1_outputPayload_sel_15_1; - wire _zz_s1_outputPayload_sel_15_2; - wire _zz_s1_outputPayload_sel_15_3; - wire s1_output_valid; - reg s1_output_ready; - wire [127:0] s1_output_payload_cmd_data; - wire [15:0] s1_output_payload_cmd_mask; - wire [3:0] s1_output_payload_index_0; - wire [3:0] s1_output_payload_index_1; - wire [3:0] s1_output_payload_index_2; - wire [3:0] s1_output_payload_index_3; - wire [3:0] s1_output_payload_index_4; - wire [3:0] s1_output_payload_index_5; - wire [3:0] s1_output_payload_index_6; - wire [3:0] s1_output_payload_index_7; - wire [3:0] s1_output_payload_index_8; - wire [3:0] s1_output_payload_index_9; - wire [3:0] s1_output_payload_index_10; - wire [3:0] s1_output_payload_index_11; - wire [3:0] s1_output_payload_index_12; - wire [3:0] s1_output_payload_index_13; - wire [3:0] s1_output_payload_index_14; - wire [3:0] s1_output_payload_index_15; - wire s1_output_payload_last; - wire [3:0] s1_output_payload_sel_0; - wire [3:0] s1_output_payload_sel_1; - wire [3:0] s1_output_payload_sel_2; - wire [3:0] s1_output_payload_sel_3; - wire [3:0] s1_output_payload_sel_4; - wire [3:0] s1_output_payload_sel_5; - wire [3:0] s1_output_payload_sel_6; - wire [3:0] s1_output_payload_sel_7; - wire [3:0] s1_output_payload_sel_8; - wire [3:0] s1_output_payload_sel_9; - wire [3:0] s1_output_payload_sel_10; - wire [3:0] s1_output_payload_sel_11; - wire [3:0] s1_output_payload_sel_12; - wire [3:0] s1_output_payload_sel_13; - wire [3:0] s1_output_payload_sel_14; - wire [3:0] s1_output_payload_sel_15; - wire [15:0] s1_output_payload_selValid; - wire s2_input_valid; - reg s2_input_ready; - wire [127:0] s2_input_payload_cmd_data; - wire [15:0] s2_input_payload_cmd_mask; - wire [3:0] s2_input_payload_index_0; - wire [3:0] s2_input_payload_index_1; - wire [3:0] s2_input_payload_index_2; - wire [3:0] s2_input_payload_index_3; - wire [3:0] s2_input_payload_index_4; - wire [3:0] s2_input_payload_index_5; - wire [3:0] s2_input_payload_index_6; - wire [3:0] s2_input_payload_index_7; - wire [3:0] s2_input_payload_index_8; - wire [3:0] s2_input_payload_index_9; - wire [3:0] s2_input_payload_index_10; - wire [3:0] s2_input_payload_index_11; - wire [3:0] s2_input_payload_index_12; - wire [3:0] s2_input_payload_index_13; - wire [3:0] s2_input_payload_index_14; - wire [3:0] s2_input_payload_index_15; - wire s2_input_payload_last; - wire [3:0] s2_input_payload_sel_0; - wire [3:0] s2_input_payload_sel_1; - wire [3:0] s2_input_payload_sel_2; - wire [3:0] s2_input_payload_sel_3; - wire [3:0] s2_input_payload_sel_4; - wire [3:0] s2_input_payload_sel_5; - wire [3:0] s2_input_payload_sel_6; - wire [3:0] s2_input_payload_sel_7; - wire [3:0] s2_input_payload_sel_8; - wire [3:0] s2_input_payload_sel_9; - wire [3:0] s2_input_payload_sel_10; - wire [3:0] s2_input_payload_sel_11; - wire [3:0] s2_input_payload_sel_12; - wire [3:0] s2_input_payload_sel_13; - wire [3:0] s2_input_payload_sel_14; - wire [3:0] s2_input_payload_sel_15; - wire [15:0] s2_input_payload_selValid; - reg s1_output_rValid; - reg [127:0] s1_output_rData_cmd_data; - reg [15:0] s1_output_rData_cmd_mask; - reg [3:0] s1_output_rData_index_0; - reg [3:0] s1_output_rData_index_1; - reg [3:0] s1_output_rData_index_2; - reg [3:0] s1_output_rData_index_3; - reg [3:0] s1_output_rData_index_4; - reg [3:0] s1_output_rData_index_5; - reg [3:0] s1_output_rData_index_6; - reg [3:0] s1_output_rData_index_7; - reg [3:0] s1_output_rData_index_8; - reg [3:0] s1_output_rData_index_9; - reg [3:0] s1_output_rData_index_10; - reg [3:0] s1_output_rData_index_11; - reg [3:0] s1_output_rData_index_12; - reg [3:0] s1_output_rData_index_13; - reg [3:0] s1_output_rData_index_14; - reg [3:0] s1_output_rData_index_15; - reg s1_output_rData_last; - reg [3:0] s1_output_rData_sel_0; - reg [3:0] s1_output_rData_sel_1; - reg [3:0] s1_output_rData_sel_2; - reg [3:0] s1_output_rData_sel_3; - reg [3:0] s1_output_rData_sel_4; - reg [3:0] s1_output_rData_sel_5; - reg [3:0] s1_output_rData_sel_6; - reg [3:0] s1_output_rData_sel_7; - reg [3:0] s1_output_rData_sel_8; - reg [3:0] s1_output_rData_sel_9; - reg [3:0] s1_output_rData_sel_10; - reg [3:0] s1_output_rData_sel_11; - reg [3:0] s1_output_rData_sel_12; - reg [3:0] s1_output_rData_sel_13; - reg [3:0] s1_output_rData_sel_14; - reg [3:0] s1_output_rData_sel_15; - reg [15:0] s1_output_rData_selValid; - wire when_Stream_l375_2; - wire when_DmaSg_l1464; - wire s2_input_fire; - wire [7:0] s2_inputDataBytes_0; - wire [7:0] s2_inputDataBytes_1; - wire [7:0] s2_inputDataBytes_2; - wire [7:0] s2_inputDataBytes_3; - wire [7:0] s2_inputDataBytes_4; - wire [7:0] s2_inputDataBytes_5; - wire [7:0] s2_inputDataBytes_6; - wire [7:0] s2_inputDataBytes_7; - wire [7:0] s2_inputDataBytes_8; - wire [7:0] s2_inputDataBytes_9; - wire [7:0] s2_inputDataBytes_10; - wire [7:0] s2_inputDataBytes_11; - wire [7:0] s2_inputDataBytes_12; - wire [7:0] s2_inputDataBytes_13; - wire [7:0] s2_inputDataBytes_14; - wire [7:0] s2_inputDataBytes_15; - reg s2_byteLogic_0_buffer_valid; - reg [7:0] s2_byteLogic_0_buffer_data; - wire s2_byteLogic_0_lastUsed; - wire s2_byteLogic_0_inputMask; - wire [7:0] s2_byteLogic_0_inputData; - wire s2_byteLogic_0_outputMask; - wire [7:0] s2_byteLogic_0_outputData; - wire when_DmaSg_l1493; - reg s2_byteLogic_1_buffer_valid; - reg [7:0] s2_byteLogic_1_buffer_data; - wire s2_byteLogic_1_lastUsed; - wire s2_byteLogic_1_inputMask; - wire [7:0] s2_byteLogic_1_inputData; - wire s2_byteLogic_1_outputMask; - wire [7:0] s2_byteLogic_1_outputData; - wire when_DmaSg_l1493_1; - reg s2_byteLogic_2_buffer_valid; - reg [7:0] s2_byteLogic_2_buffer_data; - wire s2_byteLogic_2_lastUsed; - wire s2_byteLogic_2_inputMask; - wire [7:0] s2_byteLogic_2_inputData; - wire s2_byteLogic_2_outputMask; - wire [7:0] s2_byteLogic_2_outputData; - wire when_DmaSg_l1493_2; - reg s2_byteLogic_3_buffer_valid; - reg [7:0] s2_byteLogic_3_buffer_data; - wire s2_byteLogic_3_lastUsed; - wire s2_byteLogic_3_inputMask; - wire [7:0] s2_byteLogic_3_inputData; - wire s2_byteLogic_3_outputMask; - wire [7:0] s2_byteLogic_3_outputData; - wire when_DmaSg_l1493_3; - reg s2_byteLogic_4_buffer_valid; - reg [7:0] s2_byteLogic_4_buffer_data; - wire s2_byteLogic_4_lastUsed; - wire s2_byteLogic_4_inputMask; - wire [7:0] s2_byteLogic_4_inputData; - wire s2_byteLogic_4_outputMask; - wire [7:0] s2_byteLogic_4_outputData; - wire when_DmaSg_l1493_4; - reg s2_byteLogic_5_buffer_valid; - reg [7:0] s2_byteLogic_5_buffer_data; - wire s2_byteLogic_5_lastUsed; - wire s2_byteLogic_5_inputMask; - wire [7:0] s2_byteLogic_5_inputData; - wire s2_byteLogic_5_outputMask; - wire [7:0] s2_byteLogic_5_outputData; - wire when_DmaSg_l1493_5; - reg s2_byteLogic_6_buffer_valid; - reg [7:0] s2_byteLogic_6_buffer_data; - wire s2_byteLogic_6_lastUsed; - wire s2_byteLogic_6_inputMask; - wire [7:0] s2_byteLogic_6_inputData; - wire s2_byteLogic_6_outputMask; - wire [7:0] s2_byteLogic_6_outputData; - wire when_DmaSg_l1493_6; - reg s2_byteLogic_7_buffer_valid; - reg [7:0] s2_byteLogic_7_buffer_data; - wire s2_byteLogic_7_lastUsed; - wire s2_byteLogic_7_inputMask; - wire [7:0] s2_byteLogic_7_inputData; - wire s2_byteLogic_7_outputMask; - wire [7:0] s2_byteLogic_7_outputData; - wire when_DmaSg_l1493_7; - reg s2_byteLogic_8_buffer_valid; - reg [7:0] s2_byteLogic_8_buffer_data; - wire s2_byteLogic_8_lastUsed; - wire s2_byteLogic_8_inputMask; - wire [7:0] s2_byteLogic_8_inputData; - wire s2_byteLogic_8_outputMask; - wire [7:0] s2_byteLogic_8_outputData; - wire when_DmaSg_l1493_8; - reg s2_byteLogic_9_buffer_valid; - reg [7:0] s2_byteLogic_9_buffer_data; - wire s2_byteLogic_9_lastUsed; - wire s2_byteLogic_9_inputMask; - wire [7:0] s2_byteLogic_9_inputData; - wire s2_byteLogic_9_outputMask; - wire [7:0] s2_byteLogic_9_outputData; - wire when_DmaSg_l1493_9; - reg s2_byteLogic_10_buffer_valid; - reg [7:0] s2_byteLogic_10_buffer_data; - wire s2_byteLogic_10_lastUsed; - wire s2_byteLogic_10_inputMask; - wire [7:0] s2_byteLogic_10_inputData; - wire s2_byteLogic_10_outputMask; - wire [7:0] s2_byteLogic_10_outputData; - wire when_DmaSg_l1493_10; - reg s2_byteLogic_11_buffer_valid; - reg [7:0] s2_byteLogic_11_buffer_data; - wire s2_byteLogic_11_lastUsed; - wire s2_byteLogic_11_inputMask; - wire [7:0] s2_byteLogic_11_inputData; - wire s2_byteLogic_11_outputMask; - wire [7:0] s2_byteLogic_11_outputData; - wire when_DmaSg_l1493_11; - reg s2_byteLogic_12_buffer_valid; - reg [7:0] s2_byteLogic_12_buffer_data; - wire s2_byteLogic_12_lastUsed; - wire s2_byteLogic_12_inputMask; - wire [7:0] s2_byteLogic_12_inputData; - wire s2_byteLogic_12_outputMask; - wire [7:0] s2_byteLogic_12_outputData; - wire when_DmaSg_l1493_12; - reg s2_byteLogic_13_buffer_valid; - reg [7:0] s2_byteLogic_13_buffer_data; - wire s2_byteLogic_13_lastUsed; - wire s2_byteLogic_13_inputMask; - wire [7:0] s2_byteLogic_13_inputData; - wire s2_byteLogic_13_outputMask; - wire [7:0] s2_byteLogic_13_outputData; - wire when_DmaSg_l1493_13; - reg s2_byteLogic_14_buffer_valid; - reg [7:0] s2_byteLogic_14_buffer_data; - wire s2_byteLogic_14_lastUsed; - wire s2_byteLogic_14_inputMask; - wire [7:0] s2_byteLogic_14_inputData; - wire s2_byteLogic_14_outputMask; - wire [7:0] s2_byteLogic_14_outputData; - wire when_DmaSg_l1493_14; - reg s2_byteLogic_15_buffer_valid; - reg [7:0] s2_byteLogic_15_buffer_data; - wire s2_byteLogic_15_lastUsed; - wire s2_byteLogic_15_inputMask; - wire [7:0] s2_byteLogic_15_inputData; - wire s2_byteLogic_15_outputMask; - wire [7:0] s2_byteLogic_15_outputData; - wire when_DmaSg_l1493_15; - wire _zz_io_output_usedUntil; - wire _zz_io_output_usedUntil_1; - wire _zz_io_output_usedUntil_2; - wire _zz_io_output_usedUntil_3; - - assign _zz_s0_countOnesLogic_3_13 = _zz_s0_countOnesLogic_3; - assign _zz_s0_countOnesLogic_3_12 = {2'd0, _zz_s0_countOnesLogic_3_13}; - assign _zz_s0_countOnesLogic_4_13 = {_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}; - assign _zz_s0_countOnesLogic_4_12 = {1'd0, _zz_s0_countOnesLogic_4_13}; - assign _zz_s0_countOnesLogic_6_9 = (_zz_s0_countOnesLogic_6_10 + _zz_s0_countOnesLogic_6_12); - assign _zz_s0_countOnesLogic_6_16 = _zz_s0_countOnesLogic_6; - assign _zz_s0_countOnesLogic_6_15 = {2'd0, _zz_s0_countOnesLogic_6_16}; - assign _zz_s0_countOnesLogic_7_9 = (_zz_s0_countOnesLogic_7_10 + _zz_s0_countOnesLogic_7_12); - assign _zz_s0_countOnesLogic_7_16 = {_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}; - assign _zz_s0_countOnesLogic_7_15 = {1'd0, _zz_s0_countOnesLogic_7_16}; - assign _zz_s0_countOnesLogic_8_9 = (_zz_s0_countOnesLogic_8_10 + _zz_s0_countOnesLogic_8_12); - assign _zz_s0_countOnesLogic_9_9 = (_zz_s0_countOnesLogic_9_10 + _zz_s0_countOnesLogic_9_12); - assign _zz_s0_countOnesLogic_9_14 = (_zz_s0_countOnesLogic_9_15 + _zz_s0_countOnesLogic_9_17); - assign _zz_s0_countOnesLogic_9_19 = _zz_s0_countOnesLogic_9; - assign _zz_s0_countOnesLogic_9_18 = {2'd0, _zz_s0_countOnesLogic_9_19}; - assign _zz_s0_countOnesLogic_10_9 = (_zz_s0_countOnesLogic_10_10 + _zz_s0_countOnesLogic_10_12); - assign _zz_s0_countOnesLogic_10_14 = (_zz_s0_countOnesLogic_10_15 + _zz_s0_countOnesLogic_10_17); - assign _zz_s0_countOnesLogic_10_19 = {_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}; - assign _zz_s0_countOnesLogic_10_18 = {1'd0, _zz_s0_countOnesLogic_10_19}; - assign _zz_s0_countOnesLogic_11_9 = (_zz_s0_countOnesLogic_11_10 + _zz_s0_countOnesLogic_11_12); - assign _zz_s0_countOnesLogic_11_14 = (_zz_s0_countOnesLogic_11_15 + _zz_s0_countOnesLogic_11_17); - assign _zz_s0_countOnesLogic_12_9 = (_zz_s0_countOnesLogic_12_10 + _zz_s0_countOnesLogic_12_15); - assign _zz_s0_countOnesLogic_12_10 = (_zz_s0_countOnesLogic_12_11 + _zz_s0_countOnesLogic_12_13); - assign _zz_s0_countOnesLogic_12_15 = (_zz_s0_countOnesLogic_12_16 + _zz_s0_countOnesLogic_12_18); - assign _zz_s0_countOnesLogic_12_22 = _zz_s0_countOnesLogic_12; - assign _zz_s0_countOnesLogic_12_21 = {2'd0, _zz_s0_countOnesLogic_12_22}; - assign _zz_s0_countOnesLogic_13_9 = (_zz_s0_countOnesLogic_13_10 + _zz_s0_countOnesLogic_13_15); - assign _zz_s0_countOnesLogic_13_10 = (_zz_s0_countOnesLogic_13_11 + _zz_s0_countOnesLogic_13_13); - assign _zz_s0_countOnesLogic_13_15 = (_zz_s0_countOnesLogic_13_16 + _zz_s0_countOnesLogic_13_18); - assign _zz_s0_countOnesLogic_13_22 = {_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}; - assign _zz_s0_countOnesLogic_13_21 = {1'd0, _zz_s0_countOnesLogic_13_22}; - assign _zz_s0_countOnesLogic_14_9 = (_zz_s0_countOnesLogic_14_10 + _zz_s0_countOnesLogic_14_15); - assign _zz_s0_countOnesLogic_14_10 = (_zz_s0_countOnesLogic_14_11 + _zz_s0_countOnesLogic_14_13); - assign _zz_s0_countOnesLogic_14_15 = (_zz_s0_countOnesLogic_14_16 + _zz_s0_countOnesLogic_14_18); - assign _zz_s0_countOnesLogic_15_8 = (_zz_s0_countOnesLogic_15_9 + _zz_s0_countOnesLogic_15_14); - assign _zz_s0_countOnesLogic_15_9 = (_zz_s0_countOnesLogic_15_10 + _zz_s0_countOnesLogic_15_12); - assign _zz_s0_countOnesLogic_15_14 = (_zz_s0_countOnesLogic_15_15 + _zz_s0_countOnesLogic_15_17); - assign _zz_s0_countOnesLogic_15_19 = (_zz_s0_countOnesLogic_15_20 + _zz_s0_countOnesLogic_15_22); - assign _zz_s0_countOnesLogic_15_24 = s0_input_payload_mask[15]; - assign _zz_s0_countOnesLogic_15_23 = {2'd0, _zz_s0_countOnesLogic_15_24}; - assign _zz_s1_offsetNext = {1'd0, s1_offset}; - assign _zz_s1_byteCounter = {8'd0, s1_input_payload_countOnes_15}; - assign _zz_s1_inputIndexes_1 = {3'd0, s1_input_payload_countOnes_0}; - assign _zz_s1_inputIndexes_2 = {2'd0, s1_input_payload_countOnes_1}; - assign _zz_s1_inputIndexes_3 = {2'd0, s1_input_payload_countOnes_2}; - assign _zz_s1_inputIndexes_4 = {1'd0, s1_input_payload_countOnes_3}; - assign _zz_s1_inputIndexes_5 = {1'd0, s1_input_payload_countOnes_4}; - assign _zz_s1_inputIndexes_6 = {1'd0, s1_input_payload_countOnes_5}; - assign _zz_s1_inputIndexes_7 = {1'd0, s1_input_payload_countOnes_6}; - assign _zz_when_DmaSg_l1464 = {1'd0, io_burstLength}; - assign _zz_s0_countOnesLogic_0_2 = _zz_s0_countOnesLogic_0; - assign _zz_s0_countOnesLogic_1_2 = {_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}; - assign _zz_s0_countOnesLogic_2_2 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_3_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_4_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_5_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_5_12 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_6_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_6_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_7_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_7_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_8_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_8_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_8_15 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_9_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_9_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_9_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_10_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_10_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_10_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_11_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_11_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_11_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_11_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_12_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_12_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_12_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_12_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_13_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_13_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_13_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_13_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_14_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_14_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_14_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_14_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_14_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; - assign _zz_s0_countOnesLogic_15_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; - assign _zz_s0_countOnesLogic_15_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; - assign _zz_s0_countOnesLogic_15_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; - assign _zz_s0_countOnesLogic_15_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; - assign _zz_s0_countOnesLogic_15_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; - assign _zz_io_output_usedUntil_5 = {_zz_io_output_usedUntil_3,{_zz_io_output_usedUntil_2,{_zz_io_output_usedUntil_1,_zz_io_output_usedUntil}}}; - assign _zz_s1_outputPayload_selValid_240 = _zz_s1_outputPayload_selValid_6; - assign _zz_s1_outputPayload_selValid_241 = {_zz_s1_outputPayload_selValid_5,{_zz_s1_outputPayload_selValid_4,{_zz_s1_outputPayload_selValid_3,{_zz_s1_outputPayload_selValid_2,{_zz_s1_outputPayload_selValid_1,{_zz_s1_outputPayload_selValid,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0000))}}}}}}; - assign _zz_s1_outputPayload_selValid_242 = _zz_s1_outputPayload_selValid_21; - assign _zz_s1_outputPayload_selValid_243 = {_zz_s1_outputPayload_selValid_20,{_zz_s1_outputPayload_selValid_19,{_zz_s1_outputPayload_selValid_18,{_zz_s1_outputPayload_selValid_17,{_zz_s1_outputPayload_selValid_16,{_zz_s1_outputPayload_selValid_15,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0001))}}}}}}; - assign _zz_s1_outputPayload_selValid_244 = _zz_s1_outputPayload_selValid_36; - assign _zz_s1_outputPayload_selValid_245 = {_zz_s1_outputPayload_selValid_35,{_zz_s1_outputPayload_selValid_34,{_zz_s1_outputPayload_selValid_33,{_zz_s1_outputPayload_selValid_32,{_zz_s1_outputPayload_selValid_31,{_zz_s1_outputPayload_selValid_30,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0010))}}}}}}; - assign _zz_s1_outputPayload_selValid_246 = _zz_s1_outputPayload_selValid_51; - assign _zz_s1_outputPayload_selValid_247 = {_zz_s1_outputPayload_selValid_50,{_zz_s1_outputPayload_selValid_49,{_zz_s1_outputPayload_selValid_48,{_zz_s1_outputPayload_selValid_47,{_zz_s1_outputPayload_selValid_46,{_zz_s1_outputPayload_selValid_45,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0011))}}}}}}; - assign _zz_s1_outputPayload_selValid_248 = _zz_s1_outputPayload_selValid_66; - assign _zz_s1_outputPayload_selValid_249 = {_zz_s1_outputPayload_selValid_65,{_zz_s1_outputPayload_selValid_64,{_zz_s1_outputPayload_selValid_63,{_zz_s1_outputPayload_selValid_62,{_zz_s1_outputPayload_selValid_61,{_zz_s1_outputPayload_selValid_60,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0100))}}}}}}; - assign _zz_s1_outputPayload_selValid_250 = _zz_s1_outputPayload_selValid_81; - assign _zz_s1_outputPayload_selValid_251 = {_zz_s1_outputPayload_selValid_80,{_zz_s1_outputPayload_selValid_79,{_zz_s1_outputPayload_selValid_78,{_zz_s1_outputPayload_selValid_77,{_zz_s1_outputPayload_selValid_76,{_zz_s1_outputPayload_selValid_75,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0101))}}}}}}; - assign _zz_s1_outputPayload_selValid_252 = _zz_s1_outputPayload_selValid_96; - assign _zz_s1_outputPayload_selValid_253 = {_zz_s1_outputPayload_selValid_95,{_zz_s1_outputPayload_selValid_94,{_zz_s1_outputPayload_selValid_93,{_zz_s1_outputPayload_selValid_92,{_zz_s1_outputPayload_selValid_91,{_zz_s1_outputPayload_selValid_90,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0110))}}}}}}; - assign _zz_s1_outputPayload_selValid_254 = _zz_s1_outputPayload_selValid_111; - assign _zz_s1_outputPayload_selValid_255 = {_zz_s1_outputPayload_selValid_110,{_zz_s1_outputPayload_selValid_109,{_zz_s1_outputPayload_selValid_108,{_zz_s1_outputPayload_selValid_107,{_zz_s1_outputPayload_selValid_106,{_zz_s1_outputPayload_selValid_105,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0111))}}}}}}; - assign _zz_s1_outputPayload_selValid_256 = _zz_s1_outputPayload_selValid_126; - assign _zz_s1_outputPayload_selValid_257 = {_zz_s1_outputPayload_selValid_125,{_zz_s1_outputPayload_selValid_124,{_zz_s1_outputPayload_selValid_123,{_zz_s1_outputPayload_selValid_122,{_zz_s1_outputPayload_selValid_121,{_zz_s1_outputPayload_selValid_120,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1000))}}}}}}; - assign _zz_s1_outputPayload_selValid_258 = _zz_s1_outputPayload_selValid_141; - assign _zz_s1_outputPayload_selValid_259 = {_zz_s1_outputPayload_selValid_140,{_zz_s1_outputPayload_selValid_139,{_zz_s1_outputPayload_selValid_138,{_zz_s1_outputPayload_selValid_137,{_zz_s1_outputPayload_selValid_136,{_zz_s1_outputPayload_selValid_135,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1001))}}}}}}; - assign _zz_s1_outputPayload_selValid_260 = _zz_s1_outputPayload_selValid_156; - assign _zz_s1_outputPayload_selValid_261 = {_zz_s1_outputPayload_selValid_155,{_zz_s1_outputPayload_selValid_154,{_zz_s1_outputPayload_selValid_153,{_zz_s1_outputPayload_selValid_152,{_zz_s1_outputPayload_selValid_151,{_zz_s1_outputPayload_selValid_150,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1010))}}}}}}; - assign _zz_s1_outputPayload_selValid_262 = _zz_s1_outputPayload_selValid_171; - assign _zz_s1_outputPayload_selValid_263 = {_zz_s1_outputPayload_selValid_170,{_zz_s1_outputPayload_selValid_169,{_zz_s1_outputPayload_selValid_168,{_zz_s1_outputPayload_selValid_167,{_zz_s1_outputPayload_selValid_166,{_zz_s1_outputPayload_selValid_165,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1011))}}}}}}; - assign _zz_s1_outputPayload_selValid_264 = _zz_s1_outputPayload_selValid_186; - assign _zz_s1_outputPayload_selValid_265 = {_zz_s1_outputPayload_selValid_185,{_zz_s1_outputPayload_selValid_184,{_zz_s1_outputPayload_selValid_183,{_zz_s1_outputPayload_selValid_182,{_zz_s1_outputPayload_selValid_181,{_zz_s1_outputPayload_selValid_180,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1100))}}}}}}; - assign _zz_s1_outputPayload_selValid_266 = _zz_s1_outputPayload_selValid_201; - assign _zz_s1_outputPayload_selValid_267 = {_zz_s1_outputPayload_selValid_200,{_zz_s1_outputPayload_selValid_199,{_zz_s1_outputPayload_selValid_198,{_zz_s1_outputPayload_selValid_197,{_zz_s1_outputPayload_selValid_196,{_zz_s1_outputPayload_selValid_195,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1101))}}}}}}; - assign _zz_s1_outputPayload_selValid_268 = _zz_s1_outputPayload_selValid_216; - assign _zz_s1_outputPayload_selValid_269 = {_zz_s1_outputPayload_selValid_215,{_zz_s1_outputPayload_selValid_214,{_zz_s1_outputPayload_selValid_213,{_zz_s1_outputPayload_selValid_212,{_zz_s1_outputPayload_selValid_211,{_zz_s1_outputPayload_selValid_210,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1110))}}}}}}; - assign _zz_s1_outputPayload_selValid_270 = _zz_s1_outputPayload_selValid_231; - assign _zz_s1_outputPayload_selValid_271 = {_zz_s1_outputPayload_selValid_230,{_zz_s1_outputPayload_selValid_229,{_zz_s1_outputPayload_selValid_228,{_zz_s1_outputPayload_selValid_227,{_zz_s1_outputPayload_selValid_226,{_zz_s1_outputPayload_selValid_225,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1111))}}}}}}; - always @(*) begin - case(_zz_s0_countOnesLogic_0_2) - 1'b0 : _zz_s0_countOnesLogic_0_1 = 1'b0; - default : _zz_s0_countOnesLogic_0_1 = 1'b1; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_1_2) - 2'b00 : _zz_s0_countOnesLogic_1_1 = 2'b00; - 2'b01 : _zz_s0_countOnesLogic_1_1 = 2'b01; - 2'b10 : _zz_s0_countOnesLogic_1_1 = 2'b01; - default : _zz_s0_countOnesLogic_1_1 = 2'b10; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_2_2) - 3'b000 : _zz_s0_countOnesLogic_2_1 = 2'b00; - 3'b001 : _zz_s0_countOnesLogic_2_1 = 2'b01; - 3'b010 : _zz_s0_countOnesLogic_2_1 = 2'b01; - 3'b011 : _zz_s0_countOnesLogic_2_1 = 2'b10; - 3'b100 : _zz_s0_countOnesLogic_2_1 = 2'b01; - 3'b101 : _zz_s0_countOnesLogic_2_1 = 2'b10; - 3'b110 : _zz_s0_countOnesLogic_2_1 = 2'b10; - default : _zz_s0_countOnesLogic_2_1 = 2'b11; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_3_10) - 3'b000 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_1; - 3'b001 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_2; - 3'b010 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_3; - 3'b011 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_4; - 3'b100 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_5; - 3'b101 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_6; - 3'b110 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_7; - default : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_3_12) - 3'b000 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_1; - 3'b001 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_2; - 3'b010 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_3; - 3'b011 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_4; - 3'b100 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_5; - 3'b101 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_6; - 3'b110 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_7; - default : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_4_10) - 3'b000 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_1; - 3'b001 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_2; - 3'b010 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_3; - 3'b011 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_4; - 3'b100 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_5; - 3'b101 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_6; - 3'b110 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_7; - default : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_4_12) - 3'b000 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_1; - 3'b001 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_2; - 3'b010 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_3; - 3'b011 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_4; - 3'b100 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_5; - 3'b101 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_6; - 3'b110 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_7; - default : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_5_10) - 3'b000 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_1; - 3'b001 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_2; - 3'b010 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_3; - 3'b011 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_4; - 3'b100 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_5; - 3'b101 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_6; - 3'b110 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_7; - default : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_5_12) - 3'b000 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_1; - 3'b001 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_2; - 3'b010 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_3; - 3'b011 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_4; - 3'b100 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_5; - 3'b101 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_6; - 3'b110 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_7; - default : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_6_11) - 3'b000 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_1; - 3'b001 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_2; - 3'b010 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_3; - 3'b011 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_4; - 3'b100 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_5; - 3'b101 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_6; - 3'b110 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_7; - default : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_6_13) - 3'b000 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_1; - 3'b001 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_2; - 3'b010 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_3; - 3'b011 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_4; - 3'b100 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_5; - 3'b101 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_6; - 3'b110 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_7; - default : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_6_15) - 3'b000 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_1; - 3'b001 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_2; - 3'b010 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_3; - 3'b011 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_4; - 3'b100 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_5; - 3'b101 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_6; - 3'b110 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_7; - default : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_7_11) - 3'b000 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_1; - 3'b001 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_2; - 3'b010 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_3; - 3'b011 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_4; - 3'b100 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_5; - 3'b101 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_6; - 3'b110 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_7; - default : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_7_13) - 3'b000 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_1; - 3'b001 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_2; - 3'b010 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_3; - 3'b011 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_4; - 3'b100 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_5; - 3'b101 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_6; - 3'b110 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_7; - default : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_7_15) - 3'b000 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_1; - 3'b001 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_2; - 3'b010 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_3; - 3'b011 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_4; - 3'b100 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_5; - 3'b101 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_6; - 3'b110 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_7; - default : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_8_11) - 3'b000 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_1; - 3'b001 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_2; - 3'b010 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_3; - 3'b011 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_4; - 3'b100 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_5; - 3'b101 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_6; - 3'b110 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_7; - default : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_8_13) - 3'b000 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_1; - 3'b001 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_2; - 3'b010 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_3; - 3'b011 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_4; - 3'b100 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_5; - 3'b101 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_6; - 3'b110 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_7; - default : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_8_15) - 3'b000 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_1; - 3'b001 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_2; - 3'b010 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_3; - 3'b011 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_4; - 3'b100 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_5; - 3'b101 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_6; - 3'b110 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_7; - default : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_11) - 3'b000 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_13) - 3'b000 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_16) - 3'b000 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_9_18) - 3'b000 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_1; - 3'b001 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_2; - 3'b010 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_3; - 3'b011 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_4; - 3'b100 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_5; - 3'b101 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_6; - 3'b110 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_7; - default : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_11) - 3'b000 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_13) - 3'b000 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_16) - 3'b000 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_10_18) - 3'b000 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_1; - 3'b001 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_2; - 3'b010 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_3; - 3'b011 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_4; - 3'b100 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_5; - 3'b101 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_6; - 3'b110 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_7; - default : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_11) - 3'b000 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_13) - 3'b000 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_16) - 3'b000 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_11_18) - 3'b000 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_1; - 3'b001 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_2; - 3'b010 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_3; - 3'b011 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_4; - 3'b100 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_5; - 3'b101 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_6; - 3'b110 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_7; - default : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_12) - 3'b000 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_14) - 3'b000 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_17) - 3'b000 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_19) - 3'b000 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_12_21) - 3'b000 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_1; - 3'b001 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_2; - 3'b010 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_3; - 3'b011 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_4; - 3'b100 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_5; - 3'b101 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_6; - 3'b110 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_7; - default : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_12) - 3'b000 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_14) - 3'b000 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_17) - 3'b000 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_19) - 3'b000 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_13_21) - 3'b000 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_1; - 3'b001 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_2; - 3'b010 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_3; - 3'b011 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_4; - 3'b100 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_5; - 3'b101 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_6; - 3'b110 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_7; - default : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_12) - 3'b000 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_14) - 3'b000 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_17) - 3'b000 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_19) - 3'b000 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_14_21) - 3'b000 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_1; - 3'b001 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_2; - 3'b010 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_3; - 3'b011 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_4; - 3'b100 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_5; - 3'b101 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_6; - 3'b110 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_7; - default : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_8; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_11) - 3'b000 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_13) - 3'b000 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_16) - 3'b000 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_18) - 3'b000 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_21) - 3'b000 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(_zz_s0_countOnesLogic_15_23) - 3'b000 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15; - 3'b001 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_1; - 3'b010 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_2; - 3'b011 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_3; - 3'b100 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_4; - 3'b101 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_5; - 3'b110 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_6; - default : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_7; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_0) - 4'b0000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_1) - 4'b0000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_2) - 4'b0000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_3) - 4'b0000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_4) - 4'b0000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_5) - 4'b0000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_6) - 4'b0000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_7) - 4'b0000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_8) - 4'b0000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_9) - 4'b0000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_10) - 4'b0000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_11) - 4'b0000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_12) - 4'b0000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_13) - 4'b0000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_14) - 4'b0000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(s2_input_payload_sel_15) - 4'b0000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_0; - 4'b0001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_1; - 4'b0010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_2; - 4'b0011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_3; - 4'b0100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_4; - 4'b0101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_5; - 4'b0110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_6; - 4'b0111 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_7; - 4'b1000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_8; - 4'b1001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_9; - 4'b1010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_10; - 4'b1011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_11; - 4'b1100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_12; - 4'b1101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_13; - 4'b1110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_14; - default : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_15; - endcase - end - - always @(*) begin - case(_zz_io_output_usedUntil_5) - 4'b0000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_0; - 4'b0001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_1; - 4'b0010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_2; - 4'b0011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_3; - 4'b0100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_4; - 4'b0101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_5; - 4'b0110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_6; - 4'b0111 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_7; - 4'b1000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_8; - 4'b1001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_9; - 4'b1010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_10; - 4'b1011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_11; - 4'b1100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_12; - 4'b1101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_13; - 4'b1110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_14; - default : _zz_io_output_usedUntil_4 = s2_input_payload_sel_15; - endcase - end - - always @(*) begin - io_input_ready = s0_input_ready; - if(when_Stream_l375) begin - io_input_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! s0_input_valid); - assign s0_input_valid = io_input_rValid; - assign s0_input_payload_data = io_input_rData_data; - assign s0_input_payload_mask = io_input_rData_mask; - assign _zz_s0_countOnesLogic_0 = s0_input_payload_mask[0]; - assign _zz_s0_countOnesLogic_1 = s0_input_payload_mask[1]; - assign _zz_s0_countOnesLogic_2 = s0_input_payload_mask[2]; - assign _zz_s0_countOnesLogic_3 = s0_input_payload_mask[3]; - assign _zz_s0_countOnesLogic_4 = s0_input_payload_mask[4]; - assign _zz_s0_countOnesLogic_5 = s0_input_payload_mask[5]; - assign _zz_s0_countOnesLogic_6 = s0_input_payload_mask[6]; - assign _zz_s0_countOnesLogic_7 = s0_input_payload_mask[7]; - assign _zz_s0_countOnesLogic_8 = s0_input_payload_mask[8]; - assign _zz_s0_countOnesLogic_9 = s0_input_payload_mask[9]; - assign _zz_s0_countOnesLogic_10 = s0_input_payload_mask[10]; - assign _zz_s0_countOnesLogic_11 = s0_input_payload_mask[11]; - assign _zz_s0_countOnesLogic_12 = s0_input_payload_mask[12]; - assign _zz_s0_countOnesLogic_13 = s0_input_payload_mask[13]; - assign _zz_s0_countOnesLogic_14 = s0_input_payload_mask[14]; - assign s0_countOnesLogic_0 = _zz_s0_countOnesLogic_0_1; - assign s0_countOnesLogic_1 = _zz_s0_countOnesLogic_1_1; - assign s0_countOnesLogic_2 = _zz_s0_countOnesLogic_2_1; - assign _zz_s0_countOnesLogic_3_1 = 3'b000; - assign _zz_s0_countOnesLogic_3_2 = 3'b001; - assign _zz_s0_countOnesLogic_3_3 = 3'b001; - assign _zz_s0_countOnesLogic_3_4 = 3'b010; - assign _zz_s0_countOnesLogic_3_5 = 3'b001; - assign _zz_s0_countOnesLogic_3_6 = 3'b010; - assign _zz_s0_countOnesLogic_3_7 = 3'b010; - assign _zz_s0_countOnesLogic_3_8 = 3'b011; - assign s0_countOnesLogic_3 = (_zz_s0_countOnesLogic_3_9 + _zz_s0_countOnesLogic_3_11); - assign _zz_s0_countOnesLogic_4_1 = 3'b000; - assign _zz_s0_countOnesLogic_4_2 = 3'b001; - assign _zz_s0_countOnesLogic_4_3 = 3'b001; - assign _zz_s0_countOnesLogic_4_4 = 3'b010; - assign _zz_s0_countOnesLogic_4_5 = 3'b001; - assign _zz_s0_countOnesLogic_4_6 = 3'b010; - assign _zz_s0_countOnesLogic_4_7 = 3'b010; - assign _zz_s0_countOnesLogic_4_8 = 3'b011; - assign s0_countOnesLogic_4 = (_zz_s0_countOnesLogic_4_9 + _zz_s0_countOnesLogic_4_11); - assign _zz_s0_countOnesLogic_5_1 = 3'b000; - assign _zz_s0_countOnesLogic_5_2 = 3'b001; - assign _zz_s0_countOnesLogic_5_3 = 3'b001; - assign _zz_s0_countOnesLogic_5_4 = 3'b010; - assign _zz_s0_countOnesLogic_5_5 = 3'b001; - assign _zz_s0_countOnesLogic_5_6 = 3'b010; - assign _zz_s0_countOnesLogic_5_7 = 3'b010; - assign _zz_s0_countOnesLogic_5_8 = 3'b011; - assign s0_countOnesLogic_5 = (_zz_s0_countOnesLogic_5_9 + _zz_s0_countOnesLogic_5_11); - assign _zz_s0_countOnesLogic_6_1 = 3'b000; - assign _zz_s0_countOnesLogic_6_2 = 3'b001; - assign _zz_s0_countOnesLogic_6_3 = 3'b001; - assign _zz_s0_countOnesLogic_6_4 = 3'b010; - assign _zz_s0_countOnesLogic_6_5 = 3'b001; - assign _zz_s0_countOnesLogic_6_6 = 3'b010; - assign _zz_s0_countOnesLogic_6_7 = 3'b010; - assign _zz_s0_countOnesLogic_6_8 = 3'b011; - assign s0_countOnesLogic_6 = (_zz_s0_countOnesLogic_6_9 + _zz_s0_countOnesLogic_6_14); - assign _zz_s0_countOnesLogic_7_1 = 4'b0000; - assign _zz_s0_countOnesLogic_7_2 = 4'b0001; - assign _zz_s0_countOnesLogic_7_3 = 4'b0001; - assign _zz_s0_countOnesLogic_7_4 = 4'b0010; - assign _zz_s0_countOnesLogic_7_5 = 4'b0001; - assign _zz_s0_countOnesLogic_7_6 = 4'b0010; - assign _zz_s0_countOnesLogic_7_7 = 4'b0010; - assign _zz_s0_countOnesLogic_7_8 = 4'b0011; - assign s0_countOnesLogic_7 = (_zz_s0_countOnesLogic_7_9 + _zz_s0_countOnesLogic_7_14); - assign _zz_s0_countOnesLogic_8_1 = 4'b0000; - assign _zz_s0_countOnesLogic_8_2 = 4'b0001; - assign _zz_s0_countOnesLogic_8_3 = 4'b0001; - assign _zz_s0_countOnesLogic_8_4 = 4'b0010; - assign _zz_s0_countOnesLogic_8_5 = 4'b0001; - assign _zz_s0_countOnesLogic_8_6 = 4'b0010; - assign _zz_s0_countOnesLogic_8_7 = 4'b0010; - assign _zz_s0_countOnesLogic_8_8 = 4'b0011; - assign s0_countOnesLogic_8 = (_zz_s0_countOnesLogic_8_9 + _zz_s0_countOnesLogic_8_14); - assign _zz_s0_countOnesLogic_9_1 = 4'b0000; - assign _zz_s0_countOnesLogic_9_2 = 4'b0001; - assign _zz_s0_countOnesLogic_9_3 = 4'b0001; - assign _zz_s0_countOnesLogic_9_4 = 4'b0010; - assign _zz_s0_countOnesLogic_9_5 = 4'b0001; - assign _zz_s0_countOnesLogic_9_6 = 4'b0010; - assign _zz_s0_countOnesLogic_9_7 = 4'b0010; - assign _zz_s0_countOnesLogic_9_8 = 4'b0011; - assign s0_countOnesLogic_9 = (_zz_s0_countOnesLogic_9_9 + _zz_s0_countOnesLogic_9_14); - assign _zz_s0_countOnesLogic_10_1 = 4'b0000; - assign _zz_s0_countOnesLogic_10_2 = 4'b0001; - assign _zz_s0_countOnesLogic_10_3 = 4'b0001; - assign _zz_s0_countOnesLogic_10_4 = 4'b0010; - assign _zz_s0_countOnesLogic_10_5 = 4'b0001; - assign _zz_s0_countOnesLogic_10_6 = 4'b0010; - assign _zz_s0_countOnesLogic_10_7 = 4'b0010; - assign _zz_s0_countOnesLogic_10_8 = 4'b0011; - assign s0_countOnesLogic_10 = (_zz_s0_countOnesLogic_10_9 + _zz_s0_countOnesLogic_10_14); - assign _zz_s0_countOnesLogic_11_1 = 4'b0000; - assign _zz_s0_countOnesLogic_11_2 = 4'b0001; - assign _zz_s0_countOnesLogic_11_3 = 4'b0001; - assign _zz_s0_countOnesLogic_11_4 = 4'b0010; - assign _zz_s0_countOnesLogic_11_5 = 4'b0001; - assign _zz_s0_countOnesLogic_11_6 = 4'b0010; - assign _zz_s0_countOnesLogic_11_7 = 4'b0010; - assign _zz_s0_countOnesLogic_11_8 = 4'b0011; - assign s0_countOnesLogic_11 = (_zz_s0_countOnesLogic_11_9 + _zz_s0_countOnesLogic_11_14); - assign _zz_s0_countOnesLogic_12_1 = 4'b0000; - assign _zz_s0_countOnesLogic_12_2 = 4'b0001; - assign _zz_s0_countOnesLogic_12_3 = 4'b0001; - assign _zz_s0_countOnesLogic_12_4 = 4'b0010; - assign _zz_s0_countOnesLogic_12_5 = 4'b0001; - assign _zz_s0_countOnesLogic_12_6 = 4'b0010; - assign _zz_s0_countOnesLogic_12_7 = 4'b0010; - assign _zz_s0_countOnesLogic_12_8 = 4'b0011; - assign s0_countOnesLogic_12 = (_zz_s0_countOnesLogic_12_9 + _zz_s0_countOnesLogic_12_20); - assign _zz_s0_countOnesLogic_13_1 = 4'b0000; - assign _zz_s0_countOnesLogic_13_2 = 4'b0001; - assign _zz_s0_countOnesLogic_13_3 = 4'b0001; - assign _zz_s0_countOnesLogic_13_4 = 4'b0010; - assign _zz_s0_countOnesLogic_13_5 = 4'b0001; - assign _zz_s0_countOnesLogic_13_6 = 4'b0010; - assign _zz_s0_countOnesLogic_13_7 = 4'b0010; - assign _zz_s0_countOnesLogic_13_8 = 4'b0011; - assign s0_countOnesLogic_13 = (_zz_s0_countOnesLogic_13_9 + _zz_s0_countOnesLogic_13_20); - assign _zz_s0_countOnesLogic_14_1 = 4'b0000; - assign _zz_s0_countOnesLogic_14_2 = 4'b0001; - assign _zz_s0_countOnesLogic_14_3 = 4'b0001; - assign _zz_s0_countOnesLogic_14_4 = 4'b0010; - assign _zz_s0_countOnesLogic_14_5 = 4'b0001; - assign _zz_s0_countOnesLogic_14_6 = 4'b0010; - assign _zz_s0_countOnesLogic_14_7 = 4'b0010; - assign _zz_s0_countOnesLogic_14_8 = 4'b0011; - assign s0_countOnesLogic_14 = (_zz_s0_countOnesLogic_14_9 + _zz_s0_countOnesLogic_14_20); - assign _zz_s0_countOnesLogic_15 = 5'h0; - assign _zz_s0_countOnesLogic_15_1 = 5'h01; - assign _zz_s0_countOnesLogic_15_2 = 5'h01; - assign _zz_s0_countOnesLogic_15_3 = 5'h02; - assign _zz_s0_countOnesLogic_15_4 = 5'h01; - assign _zz_s0_countOnesLogic_15_5 = 5'h02; - assign _zz_s0_countOnesLogic_15_6 = 5'h02; - assign _zz_s0_countOnesLogic_15_7 = 5'h03; - assign s0_countOnesLogic_15 = (_zz_s0_countOnesLogic_15_8 + _zz_s0_countOnesLogic_15_19); - assign s0_outputPayload_cmd_data = s0_input_payload_data; - assign s0_outputPayload_cmd_mask = s0_input_payload_mask; - assign s0_outputPayload_countOnes_0 = s0_countOnesLogic_0; - assign s0_outputPayload_countOnes_1 = s0_countOnesLogic_1; - assign s0_outputPayload_countOnes_2 = s0_countOnesLogic_2; - assign s0_outputPayload_countOnes_3 = s0_countOnesLogic_3; - assign s0_outputPayload_countOnes_4 = s0_countOnesLogic_4; - assign s0_outputPayload_countOnes_5 = s0_countOnesLogic_5; - assign s0_outputPayload_countOnes_6 = s0_countOnesLogic_6; - assign s0_outputPayload_countOnes_7 = s0_countOnesLogic_7; - assign s0_outputPayload_countOnes_8 = s0_countOnesLogic_8; - assign s0_outputPayload_countOnes_9 = s0_countOnesLogic_9; - assign s0_outputPayload_countOnes_10 = s0_countOnesLogic_10; - assign s0_outputPayload_countOnes_11 = s0_countOnesLogic_11; - assign s0_outputPayload_countOnes_12 = s0_countOnesLogic_12; - assign s0_outputPayload_countOnes_13 = s0_countOnesLogic_13; - assign s0_outputPayload_countOnes_14 = s0_countOnesLogic_14; - assign s0_outputPayload_countOnes_15 = s0_countOnesLogic_15; - assign s0_output_valid = s0_input_valid; - assign s0_input_ready = s0_output_ready; - assign s0_output_payload_cmd_data = s0_outputPayload_cmd_data; - assign s0_output_payload_cmd_mask = s0_outputPayload_cmd_mask; - assign s0_output_payload_countOnes_0 = s0_outputPayload_countOnes_0; - assign s0_output_payload_countOnes_1 = s0_outputPayload_countOnes_1; - assign s0_output_payload_countOnes_2 = s0_outputPayload_countOnes_2; - assign s0_output_payload_countOnes_3 = s0_outputPayload_countOnes_3; - assign s0_output_payload_countOnes_4 = s0_outputPayload_countOnes_4; - assign s0_output_payload_countOnes_5 = s0_outputPayload_countOnes_5; - assign s0_output_payload_countOnes_6 = s0_outputPayload_countOnes_6; - assign s0_output_payload_countOnes_7 = s0_outputPayload_countOnes_7; - assign s0_output_payload_countOnes_8 = s0_outputPayload_countOnes_8; - assign s0_output_payload_countOnes_9 = s0_outputPayload_countOnes_9; - assign s0_output_payload_countOnes_10 = s0_outputPayload_countOnes_10; - assign s0_output_payload_countOnes_11 = s0_outputPayload_countOnes_11; - assign s0_output_payload_countOnes_12 = s0_outputPayload_countOnes_12; - assign s0_output_payload_countOnes_13 = s0_outputPayload_countOnes_13; - assign s0_output_payload_countOnes_14 = s0_outputPayload_countOnes_14; - assign s0_output_payload_countOnes_15 = s0_outputPayload_countOnes_15; - always @(*) begin - s0_output_ready = s1_input_ready; - if(when_Stream_l375_1) begin - s0_output_ready = 1'b1; - end - end - - assign when_Stream_l375_1 = (! s1_input_valid); - assign s1_input_valid = s0_output_rValid; - assign s1_input_payload_cmd_data = s0_output_rData_cmd_data; - assign s1_input_payload_cmd_mask = s0_output_rData_cmd_mask; - assign s1_input_payload_countOnes_0 = s0_output_rData_countOnes_0; - assign s1_input_payload_countOnes_1 = s0_output_rData_countOnes_1; - assign s1_input_payload_countOnes_2 = s0_output_rData_countOnes_2; - assign s1_input_payload_countOnes_3 = s0_output_rData_countOnes_3; - assign s1_input_payload_countOnes_4 = s0_output_rData_countOnes_4; - assign s1_input_payload_countOnes_5 = s0_output_rData_countOnes_5; - assign s1_input_payload_countOnes_6 = s0_output_rData_countOnes_6; - assign s1_input_payload_countOnes_7 = s0_output_rData_countOnes_7; - assign s1_input_payload_countOnes_8 = s0_output_rData_countOnes_8; - assign s1_input_payload_countOnes_9 = s0_output_rData_countOnes_9; - assign s1_input_payload_countOnes_10 = s0_output_rData_countOnes_10; - assign s1_input_payload_countOnes_11 = s0_output_rData_countOnes_11; - assign s1_input_payload_countOnes_12 = s0_output_rData_countOnes_12; - assign s1_input_payload_countOnes_13 = s0_output_rData_countOnes_13; - assign s1_input_payload_countOnes_14 = s0_output_rData_countOnes_14; - assign s1_input_payload_countOnes_15 = s0_output_rData_countOnes_15; - assign s1_offsetNext = (_zz_s1_offsetNext + s1_input_payload_countOnes_15); - assign s1_input_fire = (s1_input_valid && s1_input_ready); - assign s1_inputIndexes_0 = (4'b0000 + s1_offset); - assign s1_inputIndexes_1 = (_zz_s1_inputIndexes_1 + s1_offset); - assign s1_inputIndexes_2 = (_zz_s1_inputIndexes_2 + s1_offset); - assign s1_inputIndexes_3 = (_zz_s1_inputIndexes_3 + s1_offset); - assign s1_inputIndexes_4 = (_zz_s1_inputIndexes_4 + s1_offset); - assign s1_inputIndexes_5 = (_zz_s1_inputIndexes_5 + s1_offset); - assign s1_inputIndexes_6 = (_zz_s1_inputIndexes_6 + s1_offset); - assign s1_inputIndexes_7 = (_zz_s1_inputIndexes_7 + s1_offset); - assign s1_inputIndexes_8 = (s1_input_payload_countOnes_7 + s1_offset); - assign s1_inputIndexes_9 = (s1_input_payload_countOnes_8 + s1_offset); - assign s1_inputIndexes_10 = (s1_input_payload_countOnes_9 + s1_offset); - assign s1_inputIndexes_11 = (s1_input_payload_countOnes_10 + s1_offset); - assign s1_inputIndexes_12 = (s1_input_payload_countOnes_11 + s1_offset); - assign s1_inputIndexes_13 = (s1_input_payload_countOnes_12 + s1_offset); - assign s1_inputIndexes_14 = (s1_input_payload_countOnes_13 + s1_offset); - assign s1_inputIndexes_15 = (s1_input_payload_countOnes_14 + s1_offset); - assign s1_outputPayload_cmd_data = s1_input_payload_cmd_data; - assign s1_outputPayload_cmd_mask = s1_input_payload_cmd_mask; - assign s1_outputPayload_index_0 = s1_inputIndexes_0; - assign s1_outputPayload_index_1 = s1_inputIndexes_1; - assign s1_outputPayload_index_2 = s1_inputIndexes_2; - assign s1_outputPayload_index_3 = s1_inputIndexes_3; - assign s1_outputPayload_index_4 = s1_inputIndexes_4; - assign s1_outputPayload_index_5 = s1_inputIndexes_5; - assign s1_outputPayload_index_6 = s1_inputIndexes_6; - assign s1_outputPayload_index_7 = s1_inputIndexes_7; - assign s1_outputPayload_index_8 = s1_inputIndexes_8; - assign s1_outputPayload_index_9 = s1_inputIndexes_9; - assign s1_outputPayload_index_10 = s1_inputIndexes_10; - assign s1_outputPayload_index_11 = s1_inputIndexes_11; - assign s1_outputPayload_index_12 = s1_inputIndexes_12; - assign s1_outputPayload_index_13 = s1_inputIndexes_13; - assign s1_outputPayload_index_14 = s1_inputIndexes_14; - assign s1_outputPayload_index_15 = s1_inputIndexes_15; - assign s1_outputPayload_last = s1_offsetNext[4]; - assign _zz_s1_outputPayload_selValid = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_1 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_2 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_3 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_4 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_5 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_6 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_7 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_8 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_9 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_10 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_11 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_12 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_13 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0000)); - assign _zz_s1_outputPayload_selValid_14 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0000)); - assign _zz_s1_outputPayload_sel_0 = (((((((_zz_s1_outputPayload_selValid || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_14); - assign _zz_s1_outputPayload_sel_0_1 = (((((((_zz_s1_outputPayload_selValid_1 || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); - assign _zz_s1_outputPayload_sel_0_2 = (((((((_zz_s1_outputPayload_selValid_3 || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); - assign _zz_s1_outputPayload_sel_0_3 = (((((((_zz_s1_outputPayload_selValid_7 || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); - assign s1_outputPayload_sel_0 = {_zz_s1_outputPayload_sel_0_3,{_zz_s1_outputPayload_sel_0_2,{_zz_s1_outputPayload_sel_0_1,_zz_s1_outputPayload_sel_0}}}; - always @(*) begin - s1_outputPayload_selValid[0] = ((|{_zz_s1_outputPayload_selValid_14,{_zz_s1_outputPayload_selValid_13,{_zz_s1_outputPayload_selValid_12,{_zz_s1_outputPayload_selValid_11,{_zz_s1_outputPayload_selValid_10,{_zz_s1_outputPayload_selValid_9,{_zz_s1_outputPayload_selValid_8,{_zz_s1_outputPayload_selValid_7,{_zz_s1_outputPayload_selValid_240,_zz_s1_outputPayload_selValid_241}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_0]); - s1_outputPayload_selValid[1] = ((|{_zz_s1_outputPayload_selValid_29,{_zz_s1_outputPayload_selValid_28,{_zz_s1_outputPayload_selValid_27,{_zz_s1_outputPayload_selValid_26,{_zz_s1_outputPayload_selValid_25,{_zz_s1_outputPayload_selValid_24,{_zz_s1_outputPayload_selValid_23,{_zz_s1_outputPayload_selValid_22,{_zz_s1_outputPayload_selValid_242,_zz_s1_outputPayload_selValid_243}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_1]); - s1_outputPayload_selValid[2] = ((|{_zz_s1_outputPayload_selValid_44,{_zz_s1_outputPayload_selValid_43,{_zz_s1_outputPayload_selValid_42,{_zz_s1_outputPayload_selValid_41,{_zz_s1_outputPayload_selValid_40,{_zz_s1_outputPayload_selValid_39,{_zz_s1_outputPayload_selValid_38,{_zz_s1_outputPayload_selValid_37,{_zz_s1_outputPayload_selValid_244,_zz_s1_outputPayload_selValid_245}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_2]); - s1_outputPayload_selValid[3] = ((|{_zz_s1_outputPayload_selValid_59,{_zz_s1_outputPayload_selValid_58,{_zz_s1_outputPayload_selValid_57,{_zz_s1_outputPayload_selValid_56,{_zz_s1_outputPayload_selValid_55,{_zz_s1_outputPayload_selValid_54,{_zz_s1_outputPayload_selValid_53,{_zz_s1_outputPayload_selValid_52,{_zz_s1_outputPayload_selValid_246,_zz_s1_outputPayload_selValid_247}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_3]); - s1_outputPayload_selValid[4] = ((|{_zz_s1_outputPayload_selValid_74,{_zz_s1_outputPayload_selValid_73,{_zz_s1_outputPayload_selValid_72,{_zz_s1_outputPayload_selValid_71,{_zz_s1_outputPayload_selValid_70,{_zz_s1_outputPayload_selValid_69,{_zz_s1_outputPayload_selValid_68,{_zz_s1_outputPayload_selValid_67,{_zz_s1_outputPayload_selValid_248,_zz_s1_outputPayload_selValid_249}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_4]); - s1_outputPayload_selValid[5] = ((|{_zz_s1_outputPayload_selValid_89,{_zz_s1_outputPayload_selValid_88,{_zz_s1_outputPayload_selValid_87,{_zz_s1_outputPayload_selValid_86,{_zz_s1_outputPayload_selValid_85,{_zz_s1_outputPayload_selValid_84,{_zz_s1_outputPayload_selValid_83,{_zz_s1_outputPayload_selValid_82,{_zz_s1_outputPayload_selValid_250,_zz_s1_outputPayload_selValid_251}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_5]); - s1_outputPayload_selValid[6] = ((|{_zz_s1_outputPayload_selValid_104,{_zz_s1_outputPayload_selValid_103,{_zz_s1_outputPayload_selValid_102,{_zz_s1_outputPayload_selValid_101,{_zz_s1_outputPayload_selValid_100,{_zz_s1_outputPayload_selValid_99,{_zz_s1_outputPayload_selValid_98,{_zz_s1_outputPayload_selValid_97,{_zz_s1_outputPayload_selValid_252,_zz_s1_outputPayload_selValid_253}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_6]); - s1_outputPayload_selValid[7] = ((|{_zz_s1_outputPayload_selValid_119,{_zz_s1_outputPayload_selValid_118,{_zz_s1_outputPayload_selValid_117,{_zz_s1_outputPayload_selValid_116,{_zz_s1_outputPayload_selValid_115,{_zz_s1_outputPayload_selValid_114,{_zz_s1_outputPayload_selValid_113,{_zz_s1_outputPayload_selValid_112,{_zz_s1_outputPayload_selValid_254,_zz_s1_outputPayload_selValid_255}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_7]); - s1_outputPayload_selValid[8] = ((|{_zz_s1_outputPayload_selValid_134,{_zz_s1_outputPayload_selValid_133,{_zz_s1_outputPayload_selValid_132,{_zz_s1_outputPayload_selValid_131,{_zz_s1_outputPayload_selValid_130,{_zz_s1_outputPayload_selValid_129,{_zz_s1_outputPayload_selValid_128,{_zz_s1_outputPayload_selValid_127,{_zz_s1_outputPayload_selValid_256,_zz_s1_outputPayload_selValid_257}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_8]); - s1_outputPayload_selValid[9] = ((|{_zz_s1_outputPayload_selValid_149,{_zz_s1_outputPayload_selValid_148,{_zz_s1_outputPayload_selValid_147,{_zz_s1_outputPayload_selValid_146,{_zz_s1_outputPayload_selValid_145,{_zz_s1_outputPayload_selValid_144,{_zz_s1_outputPayload_selValid_143,{_zz_s1_outputPayload_selValid_142,{_zz_s1_outputPayload_selValid_258,_zz_s1_outputPayload_selValid_259}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_9]); - s1_outputPayload_selValid[10] = ((|{_zz_s1_outputPayload_selValid_164,{_zz_s1_outputPayload_selValid_163,{_zz_s1_outputPayload_selValid_162,{_zz_s1_outputPayload_selValid_161,{_zz_s1_outputPayload_selValid_160,{_zz_s1_outputPayload_selValid_159,{_zz_s1_outputPayload_selValid_158,{_zz_s1_outputPayload_selValid_157,{_zz_s1_outputPayload_selValid_260,_zz_s1_outputPayload_selValid_261}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_10]); - s1_outputPayload_selValid[11] = ((|{_zz_s1_outputPayload_selValid_179,{_zz_s1_outputPayload_selValid_178,{_zz_s1_outputPayload_selValid_177,{_zz_s1_outputPayload_selValid_176,{_zz_s1_outputPayload_selValid_175,{_zz_s1_outputPayload_selValid_174,{_zz_s1_outputPayload_selValid_173,{_zz_s1_outputPayload_selValid_172,{_zz_s1_outputPayload_selValid_262,_zz_s1_outputPayload_selValid_263}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_11]); - s1_outputPayload_selValid[12] = ((|{_zz_s1_outputPayload_selValid_194,{_zz_s1_outputPayload_selValid_193,{_zz_s1_outputPayload_selValid_192,{_zz_s1_outputPayload_selValid_191,{_zz_s1_outputPayload_selValid_190,{_zz_s1_outputPayload_selValid_189,{_zz_s1_outputPayload_selValid_188,{_zz_s1_outputPayload_selValid_187,{_zz_s1_outputPayload_selValid_264,_zz_s1_outputPayload_selValid_265}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_12]); - s1_outputPayload_selValid[13] = ((|{_zz_s1_outputPayload_selValid_209,{_zz_s1_outputPayload_selValid_208,{_zz_s1_outputPayload_selValid_207,{_zz_s1_outputPayload_selValid_206,{_zz_s1_outputPayload_selValid_205,{_zz_s1_outputPayload_selValid_204,{_zz_s1_outputPayload_selValid_203,{_zz_s1_outputPayload_selValid_202,{_zz_s1_outputPayload_selValid_266,_zz_s1_outputPayload_selValid_267}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_13]); - s1_outputPayload_selValid[14] = ((|{_zz_s1_outputPayload_selValid_224,{_zz_s1_outputPayload_selValid_223,{_zz_s1_outputPayload_selValid_222,{_zz_s1_outputPayload_selValid_221,{_zz_s1_outputPayload_selValid_220,{_zz_s1_outputPayload_selValid_219,{_zz_s1_outputPayload_selValid_218,{_zz_s1_outputPayload_selValid_217,{_zz_s1_outputPayload_selValid_268,_zz_s1_outputPayload_selValid_269}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_14]); - s1_outputPayload_selValid[15] = ((|{_zz_s1_outputPayload_selValid_239,{_zz_s1_outputPayload_selValid_238,{_zz_s1_outputPayload_selValid_237,{_zz_s1_outputPayload_selValid_236,{_zz_s1_outputPayload_selValid_235,{_zz_s1_outputPayload_selValid_234,{_zz_s1_outputPayload_selValid_233,{_zz_s1_outputPayload_selValid_232,{_zz_s1_outputPayload_selValid_270,_zz_s1_outputPayload_selValid_271}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_15]); - end - - assign _zz_s1_outputPayload_selValid_15 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_16 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_17 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_18 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_19 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_20 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_21 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_22 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_23 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_24 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_25 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_26 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_27 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_28 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0001)); - assign _zz_s1_outputPayload_selValid_29 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0001)); - assign _zz_s1_outputPayload_sel_1 = (((((((_zz_s1_outputPayload_selValid_15 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_29); - assign _zz_s1_outputPayload_sel_1_1 = (((((((_zz_s1_outputPayload_selValid_16 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); - assign _zz_s1_outputPayload_sel_1_2 = (((((((_zz_s1_outputPayload_selValid_18 || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); - assign _zz_s1_outputPayload_sel_1_3 = (((((((_zz_s1_outputPayload_selValid_22 || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); - assign s1_outputPayload_sel_1 = {_zz_s1_outputPayload_sel_1_3,{_zz_s1_outputPayload_sel_1_2,{_zz_s1_outputPayload_sel_1_1,_zz_s1_outputPayload_sel_1}}}; - assign _zz_s1_outputPayload_selValid_30 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_31 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_32 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_33 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_34 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_35 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_36 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_37 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_38 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_39 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_40 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_41 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_42 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_43 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0010)); - assign _zz_s1_outputPayload_selValid_44 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0010)); - assign _zz_s1_outputPayload_sel_2 = (((((((_zz_s1_outputPayload_selValid_30 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_44); - assign _zz_s1_outputPayload_sel_2_1 = (((((((_zz_s1_outputPayload_selValid_31 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); - assign _zz_s1_outputPayload_sel_2_2 = (((((((_zz_s1_outputPayload_selValid_33 || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); - assign _zz_s1_outputPayload_sel_2_3 = (((((((_zz_s1_outputPayload_selValid_37 || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); - assign s1_outputPayload_sel_2 = {_zz_s1_outputPayload_sel_2_3,{_zz_s1_outputPayload_sel_2_2,{_zz_s1_outputPayload_sel_2_1,_zz_s1_outputPayload_sel_2}}}; - assign _zz_s1_outputPayload_selValid_45 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_46 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_47 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_48 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_49 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_50 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_51 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_52 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_53 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_54 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_55 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_56 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_57 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_58 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0011)); - assign _zz_s1_outputPayload_selValid_59 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0011)); - assign _zz_s1_outputPayload_sel_3 = (((((((_zz_s1_outputPayload_selValid_45 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_59); - assign _zz_s1_outputPayload_sel_3_1 = (((((((_zz_s1_outputPayload_selValid_46 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); - assign _zz_s1_outputPayload_sel_3_2 = (((((((_zz_s1_outputPayload_selValid_48 || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); - assign _zz_s1_outputPayload_sel_3_3 = (((((((_zz_s1_outputPayload_selValid_52 || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); - assign s1_outputPayload_sel_3 = {_zz_s1_outputPayload_sel_3_3,{_zz_s1_outputPayload_sel_3_2,{_zz_s1_outputPayload_sel_3_1,_zz_s1_outputPayload_sel_3}}}; - assign _zz_s1_outputPayload_selValid_60 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_61 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_62 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_63 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_64 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_65 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_66 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_67 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_68 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_69 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_70 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_71 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_72 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_73 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0100)); - assign _zz_s1_outputPayload_selValid_74 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0100)); - assign _zz_s1_outputPayload_sel_4 = (((((((_zz_s1_outputPayload_selValid_60 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_74); - assign _zz_s1_outputPayload_sel_4_1 = (((((((_zz_s1_outputPayload_selValid_61 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); - assign _zz_s1_outputPayload_sel_4_2 = (((((((_zz_s1_outputPayload_selValid_63 || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); - assign _zz_s1_outputPayload_sel_4_3 = (((((((_zz_s1_outputPayload_selValid_67 || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); - assign s1_outputPayload_sel_4 = {_zz_s1_outputPayload_sel_4_3,{_zz_s1_outputPayload_sel_4_2,{_zz_s1_outputPayload_sel_4_1,_zz_s1_outputPayload_sel_4}}}; - assign _zz_s1_outputPayload_selValid_75 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_76 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_77 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_78 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_79 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_80 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_81 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_82 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_83 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_84 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_85 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_86 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_87 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_88 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0101)); - assign _zz_s1_outputPayload_selValid_89 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0101)); - assign _zz_s1_outputPayload_sel_5 = (((((((_zz_s1_outputPayload_selValid_75 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_89); - assign _zz_s1_outputPayload_sel_5_1 = (((((((_zz_s1_outputPayload_selValid_76 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); - assign _zz_s1_outputPayload_sel_5_2 = (((((((_zz_s1_outputPayload_selValid_78 || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); - assign _zz_s1_outputPayload_sel_5_3 = (((((((_zz_s1_outputPayload_selValid_82 || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); - assign s1_outputPayload_sel_5 = {_zz_s1_outputPayload_sel_5_3,{_zz_s1_outputPayload_sel_5_2,{_zz_s1_outputPayload_sel_5_1,_zz_s1_outputPayload_sel_5}}}; - assign _zz_s1_outputPayload_selValid_90 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_91 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_92 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_93 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_94 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_95 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_96 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_97 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_98 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_99 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_100 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_101 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_102 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_103 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0110)); - assign _zz_s1_outputPayload_selValid_104 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0110)); - assign _zz_s1_outputPayload_sel_6 = (((((((_zz_s1_outputPayload_selValid_90 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_104); - assign _zz_s1_outputPayload_sel_6_1 = (((((((_zz_s1_outputPayload_selValid_91 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); - assign _zz_s1_outputPayload_sel_6_2 = (((((((_zz_s1_outputPayload_selValid_93 || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); - assign _zz_s1_outputPayload_sel_6_3 = (((((((_zz_s1_outputPayload_selValid_97 || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); - assign s1_outputPayload_sel_6 = {_zz_s1_outputPayload_sel_6_3,{_zz_s1_outputPayload_sel_6_2,{_zz_s1_outputPayload_sel_6_1,_zz_s1_outputPayload_sel_6}}}; - assign _zz_s1_outputPayload_selValid_105 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_106 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_107 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_108 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_109 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_110 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_111 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_112 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_113 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_114 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_115 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_116 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_117 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_118 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0111)); - assign _zz_s1_outputPayload_selValid_119 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0111)); - assign _zz_s1_outputPayload_sel_7 = (((((((_zz_s1_outputPayload_selValid_105 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_119); - assign _zz_s1_outputPayload_sel_7_1 = (((((((_zz_s1_outputPayload_selValid_106 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); - assign _zz_s1_outputPayload_sel_7_2 = (((((((_zz_s1_outputPayload_selValid_108 || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); - assign _zz_s1_outputPayload_sel_7_3 = (((((((_zz_s1_outputPayload_selValid_112 || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); - assign s1_outputPayload_sel_7 = {_zz_s1_outputPayload_sel_7_3,{_zz_s1_outputPayload_sel_7_2,{_zz_s1_outputPayload_sel_7_1,_zz_s1_outputPayload_sel_7}}}; - assign _zz_s1_outputPayload_selValid_120 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_121 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_122 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_123 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_124 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_125 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_126 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_127 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_128 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_129 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_130 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_131 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_132 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_133 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1000)); - assign _zz_s1_outputPayload_selValid_134 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1000)); - assign _zz_s1_outputPayload_sel_8 = (((((((_zz_s1_outputPayload_selValid_120 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_134); - assign _zz_s1_outputPayload_sel_8_1 = (((((((_zz_s1_outputPayload_selValid_121 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); - assign _zz_s1_outputPayload_sel_8_2 = (((((((_zz_s1_outputPayload_selValid_123 || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); - assign _zz_s1_outputPayload_sel_8_3 = (((((((_zz_s1_outputPayload_selValid_127 || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); - assign s1_outputPayload_sel_8 = {_zz_s1_outputPayload_sel_8_3,{_zz_s1_outputPayload_sel_8_2,{_zz_s1_outputPayload_sel_8_1,_zz_s1_outputPayload_sel_8}}}; - assign _zz_s1_outputPayload_selValid_135 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_136 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_137 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_138 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_139 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_140 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_141 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_142 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_143 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_144 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_145 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_146 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_147 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_148 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1001)); - assign _zz_s1_outputPayload_selValid_149 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1001)); - assign _zz_s1_outputPayload_sel_9 = (((((((_zz_s1_outputPayload_selValid_135 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_149); - assign _zz_s1_outputPayload_sel_9_1 = (((((((_zz_s1_outputPayload_selValid_136 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); - assign _zz_s1_outputPayload_sel_9_2 = (((((((_zz_s1_outputPayload_selValid_138 || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); - assign _zz_s1_outputPayload_sel_9_3 = (((((((_zz_s1_outputPayload_selValid_142 || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); - assign s1_outputPayload_sel_9 = {_zz_s1_outputPayload_sel_9_3,{_zz_s1_outputPayload_sel_9_2,{_zz_s1_outputPayload_sel_9_1,_zz_s1_outputPayload_sel_9}}}; - assign _zz_s1_outputPayload_selValid_150 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_151 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_152 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_153 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_154 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_155 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_156 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_157 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_158 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_159 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_160 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_161 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_162 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_163 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1010)); - assign _zz_s1_outputPayload_selValid_164 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1010)); - assign _zz_s1_outputPayload_sel_10 = (((((((_zz_s1_outputPayload_selValid_150 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_164); - assign _zz_s1_outputPayload_sel_10_1 = (((((((_zz_s1_outputPayload_selValid_151 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); - assign _zz_s1_outputPayload_sel_10_2 = (((((((_zz_s1_outputPayload_selValid_153 || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); - assign _zz_s1_outputPayload_sel_10_3 = (((((((_zz_s1_outputPayload_selValid_157 || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); - assign s1_outputPayload_sel_10 = {_zz_s1_outputPayload_sel_10_3,{_zz_s1_outputPayload_sel_10_2,{_zz_s1_outputPayload_sel_10_1,_zz_s1_outputPayload_sel_10}}}; - assign _zz_s1_outputPayload_selValid_165 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_166 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_167 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_168 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_169 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_170 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_171 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_172 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_173 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_174 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_175 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_176 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_177 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_178 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1011)); - assign _zz_s1_outputPayload_selValid_179 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1011)); - assign _zz_s1_outputPayload_sel_11 = (((((((_zz_s1_outputPayload_selValid_165 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_179); - assign _zz_s1_outputPayload_sel_11_1 = (((((((_zz_s1_outputPayload_selValid_166 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); - assign _zz_s1_outputPayload_sel_11_2 = (((((((_zz_s1_outputPayload_selValid_168 || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); - assign _zz_s1_outputPayload_sel_11_3 = (((((((_zz_s1_outputPayload_selValid_172 || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); - assign s1_outputPayload_sel_11 = {_zz_s1_outputPayload_sel_11_3,{_zz_s1_outputPayload_sel_11_2,{_zz_s1_outputPayload_sel_11_1,_zz_s1_outputPayload_sel_11}}}; - assign _zz_s1_outputPayload_selValid_180 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_181 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_182 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_183 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_184 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_185 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_186 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_187 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_188 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_189 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_190 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_191 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_192 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_193 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1100)); - assign _zz_s1_outputPayload_selValid_194 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1100)); - assign _zz_s1_outputPayload_sel_12 = (((((((_zz_s1_outputPayload_selValid_180 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_194); - assign _zz_s1_outputPayload_sel_12_1 = (((((((_zz_s1_outputPayload_selValid_181 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); - assign _zz_s1_outputPayload_sel_12_2 = (((((((_zz_s1_outputPayload_selValid_183 || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); - assign _zz_s1_outputPayload_sel_12_3 = (((((((_zz_s1_outputPayload_selValid_187 || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); - assign s1_outputPayload_sel_12 = {_zz_s1_outputPayload_sel_12_3,{_zz_s1_outputPayload_sel_12_2,{_zz_s1_outputPayload_sel_12_1,_zz_s1_outputPayload_sel_12}}}; - assign _zz_s1_outputPayload_selValid_195 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_196 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_197 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_198 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_199 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_200 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_201 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_202 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_203 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_204 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_205 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_206 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_207 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_208 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1101)); - assign _zz_s1_outputPayload_selValid_209 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1101)); - assign _zz_s1_outputPayload_sel_13 = (((((((_zz_s1_outputPayload_selValid_195 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_209); - assign _zz_s1_outputPayload_sel_13_1 = (((((((_zz_s1_outputPayload_selValid_196 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); - assign _zz_s1_outputPayload_sel_13_2 = (((((((_zz_s1_outputPayload_selValid_198 || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); - assign _zz_s1_outputPayload_sel_13_3 = (((((((_zz_s1_outputPayload_selValid_202 || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); - assign s1_outputPayload_sel_13 = {_zz_s1_outputPayload_sel_13_3,{_zz_s1_outputPayload_sel_13_2,{_zz_s1_outputPayload_sel_13_1,_zz_s1_outputPayload_sel_13}}}; - assign _zz_s1_outputPayload_selValid_210 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_211 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_212 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_213 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_214 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_215 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_216 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_217 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_218 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_219 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_220 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_221 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_222 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_223 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1110)); - assign _zz_s1_outputPayload_selValid_224 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1110)); - assign _zz_s1_outputPayload_sel_14 = (((((((_zz_s1_outputPayload_selValid_210 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_224); - assign _zz_s1_outputPayload_sel_14_1 = (((((((_zz_s1_outputPayload_selValid_211 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); - assign _zz_s1_outputPayload_sel_14_2 = (((((((_zz_s1_outputPayload_selValid_213 || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); - assign _zz_s1_outputPayload_sel_14_3 = (((((((_zz_s1_outputPayload_selValid_217 || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); - assign s1_outputPayload_sel_14 = {_zz_s1_outputPayload_sel_14_3,{_zz_s1_outputPayload_sel_14_2,{_zz_s1_outputPayload_sel_14_1,_zz_s1_outputPayload_sel_14}}}; - assign _zz_s1_outputPayload_selValid_225 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_226 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_227 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_228 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_229 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_230 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_231 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_232 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_233 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_234 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_235 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_236 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_237 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_238 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1111)); - assign _zz_s1_outputPayload_selValid_239 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1111)); - assign _zz_s1_outputPayload_sel_15 = (((((((_zz_s1_outputPayload_selValid_225 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_239); - assign _zz_s1_outputPayload_sel_15_1 = (((((((_zz_s1_outputPayload_selValid_226 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); - assign _zz_s1_outputPayload_sel_15_2 = (((((((_zz_s1_outputPayload_selValid_228 || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); - assign _zz_s1_outputPayload_sel_15_3 = (((((((_zz_s1_outputPayload_selValid_232 || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); - assign s1_outputPayload_sel_15 = {_zz_s1_outputPayload_sel_15_3,{_zz_s1_outputPayload_sel_15_2,{_zz_s1_outputPayload_sel_15_1,_zz_s1_outputPayload_sel_15}}}; - assign s1_output_valid = s1_input_valid; - assign s1_input_ready = s1_output_ready; - assign s1_output_payload_cmd_data = s1_outputPayload_cmd_data; - assign s1_output_payload_cmd_mask = s1_outputPayload_cmd_mask; - assign s1_output_payload_index_0 = s1_outputPayload_index_0; - assign s1_output_payload_index_1 = s1_outputPayload_index_1; - assign s1_output_payload_index_2 = s1_outputPayload_index_2; - assign s1_output_payload_index_3 = s1_outputPayload_index_3; - assign s1_output_payload_index_4 = s1_outputPayload_index_4; - assign s1_output_payload_index_5 = s1_outputPayload_index_5; - assign s1_output_payload_index_6 = s1_outputPayload_index_6; - assign s1_output_payload_index_7 = s1_outputPayload_index_7; - assign s1_output_payload_index_8 = s1_outputPayload_index_8; - assign s1_output_payload_index_9 = s1_outputPayload_index_9; - assign s1_output_payload_index_10 = s1_outputPayload_index_10; - assign s1_output_payload_index_11 = s1_outputPayload_index_11; - assign s1_output_payload_index_12 = s1_outputPayload_index_12; - assign s1_output_payload_index_13 = s1_outputPayload_index_13; - assign s1_output_payload_index_14 = s1_outputPayload_index_14; - assign s1_output_payload_index_15 = s1_outputPayload_index_15; - assign s1_output_payload_last = s1_outputPayload_last; - assign s1_output_payload_sel_0 = s1_outputPayload_sel_0; - assign s1_output_payload_sel_1 = s1_outputPayload_sel_1; - assign s1_output_payload_sel_2 = s1_outputPayload_sel_2; - assign s1_output_payload_sel_3 = s1_outputPayload_sel_3; - assign s1_output_payload_sel_4 = s1_outputPayload_sel_4; - assign s1_output_payload_sel_5 = s1_outputPayload_sel_5; - assign s1_output_payload_sel_6 = s1_outputPayload_sel_6; - assign s1_output_payload_sel_7 = s1_outputPayload_sel_7; - assign s1_output_payload_sel_8 = s1_outputPayload_sel_8; - assign s1_output_payload_sel_9 = s1_outputPayload_sel_9; - assign s1_output_payload_sel_10 = s1_outputPayload_sel_10; - assign s1_output_payload_sel_11 = s1_outputPayload_sel_11; - assign s1_output_payload_sel_12 = s1_outputPayload_sel_12; - assign s1_output_payload_sel_13 = s1_outputPayload_sel_13; - assign s1_output_payload_sel_14 = s1_outputPayload_sel_14; - assign s1_output_payload_sel_15 = s1_outputPayload_sel_15; - assign s1_output_payload_selValid = s1_outputPayload_selValid; - always @(*) begin - s1_output_ready = s2_input_ready; - if(when_Stream_l375_2) begin - s1_output_ready = 1'b1; - end - end - - assign when_Stream_l375_2 = (! s2_input_valid); - assign s2_input_valid = s1_output_rValid; - assign s2_input_payload_cmd_data = s1_output_rData_cmd_data; - assign s2_input_payload_cmd_mask = s1_output_rData_cmd_mask; - assign s2_input_payload_index_0 = s1_output_rData_index_0; - assign s2_input_payload_index_1 = s1_output_rData_index_1; - assign s2_input_payload_index_2 = s1_output_rData_index_2; - assign s2_input_payload_index_3 = s1_output_rData_index_3; - assign s2_input_payload_index_4 = s1_output_rData_index_4; - assign s2_input_payload_index_5 = s1_output_rData_index_5; - assign s2_input_payload_index_6 = s1_output_rData_index_6; - assign s2_input_payload_index_7 = s1_output_rData_index_7; - assign s2_input_payload_index_8 = s1_output_rData_index_8; - assign s2_input_payload_index_9 = s1_output_rData_index_9; - assign s2_input_payload_index_10 = s1_output_rData_index_10; - assign s2_input_payload_index_11 = s1_output_rData_index_11; - assign s2_input_payload_index_12 = s1_output_rData_index_12; - assign s2_input_payload_index_13 = s1_output_rData_index_13; - assign s2_input_payload_index_14 = s1_output_rData_index_14; - assign s2_input_payload_index_15 = s1_output_rData_index_15; - assign s2_input_payload_last = s1_output_rData_last; - assign s2_input_payload_sel_0 = s1_output_rData_sel_0; - assign s2_input_payload_sel_1 = s1_output_rData_sel_1; - assign s2_input_payload_sel_2 = s1_output_rData_sel_2; - assign s2_input_payload_sel_3 = s1_output_rData_sel_3; - assign s2_input_payload_sel_4 = s1_output_rData_sel_4; - assign s2_input_payload_sel_5 = s1_output_rData_sel_5; - assign s2_input_payload_sel_6 = s1_output_rData_sel_6; - assign s2_input_payload_sel_7 = s1_output_rData_sel_7; - assign s2_input_payload_sel_8 = s1_output_rData_sel_8; - assign s2_input_payload_sel_9 = s1_output_rData_sel_9; - assign s2_input_payload_sel_10 = s1_output_rData_sel_10; - assign s2_input_payload_sel_11 = s1_output_rData_sel_11; - assign s2_input_payload_sel_12 = s1_output_rData_sel_12; - assign s2_input_payload_sel_13 = s1_output_rData_sel_13; - assign s2_input_payload_sel_14 = s1_output_rData_sel_14; - assign s2_input_payload_sel_15 = s1_output_rData_sel_15; - assign s2_input_payload_selValid = s1_output_rData_selValid; - always @(*) begin - s2_input_ready = ((! io_output_enough) || io_output_consume); - if(when_DmaSg_l1464) begin - s2_input_ready = 1'b0; - end - end - - assign when_DmaSg_l1464 = (_zz_when_DmaSg_l1464 < s1_byteCounter); - assign s2_input_fire = (s2_input_valid && s2_input_ready); - assign io_output_consumed = s2_input_fire; - assign s2_inputDataBytes_0 = s2_input_payload_cmd_data[7 : 0]; - assign s2_inputDataBytes_1 = s2_input_payload_cmd_data[15 : 8]; - assign s2_inputDataBytes_2 = s2_input_payload_cmd_data[23 : 16]; - assign s2_inputDataBytes_3 = s2_input_payload_cmd_data[31 : 24]; - assign s2_inputDataBytes_4 = s2_input_payload_cmd_data[39 : 32]; - assign s2_inputDataBytes_5 = s2_input_payload_cmd_data[47 : 40]; - assign s2_inputDataBytes_6 = s2_input_payload_cmd_data[55 : 48]; - assign s2_inputDataBytes_7 = s2_input_payload_cmd_data[63 : 56]; - assign s2_inputDataBytes_8 = s2_input_payload_cmd_data[71 : 64]; - assign s2_inputDataBytes_9 = s2_input_payload_cmd_data[79 : 72]; - assign s2_inputDataBytes_10 = s2_input_payload_cmd_data[87 : 80]; - assign s2_inputDataBytes_11 = s2_input_payload_cmd_data[95 : 88]; - assign s2_inputDataBytes_12 = s2_input_payload_cmd_data[103 : 96]; - assign s2_inputDataBytes_13 = s2_input_payload_cmd_data[111 : 104]; - assign s2_inputDataBytes_14 = s2_input_payload_cmd_data[119 : 112]; - assign s2_inputDataBytes_15 = s2_input_payload_cmd_data[127 : 120]; - assign s2_byteLogic_0_lastUsed = (4'b0000 == io_output_lastByteUsed); - assign s2_byteLogic_0_inputMask = s2_input_payload_selValid[0]; - assign s2_byteLogic_0_inputData = _zz_s2_byteLogic_0_inputData; - assign s2_byteLogic_0_outputMask = (s2_byteLogic_0_buffer_valid || (s2_input_valid && s2_byteLogic_0_inputMask)); - assign s2_byteLogic_0_outputData = (s2_byteLogic_0_buffer_valid ? s2_byteLogic_0_buffer_data : s2_byteLogic_0_inputData); - always @(*) begin - io_output_mask[0] = s2_byteLogic_0_outputMask; - io_output_mask[1] = s2_byteLogic_1_outputMask; - io_output_mask[2] = s2_byteLogic_2_outputMask; - io_output_mask[3] = s2_byteLogic_3_outputMask; - io_output_mask[4] = s2_byteLogic_4_outputMask; - io_output_mask[5] = s2_byteLogic_5_outputMask; - io_output_mask[6] = s2_byteLogic_6_outputMask; - io_output_mask[7] = s2_byteLogic_7_outputMask; - io_output_mask[8] = s2_byteLogic_8_outputMask; - io_output_mask[9] = s2_byteLogic_9_outputMask; - io_output_mask[10] = s2_byteLogic_10_outputMask; - io_output_mask[11] = s2_byteLogic_11_outputMask; - io_output_mask[12] = s2_byteLogic_12_outputMask; - io_output_mask[13] = s2_byteLogic_13_outputMask; - io_output_mask[14] = s2_byteLogic_14_outputMask; - io_output_mask[15] = s2_byteLogic_15_outputMask; - end - - always @(*) begin - io_output_data[7 : 0] = s2_byteLogic_0_outputData; - io_output_data[15 : 8] = s2_byteLogic_1_outputData; - io_output_data[23 : 16] = s2_byteLogic_2_outputData; - io_output_data[31 : 24] = s2_byteLogic_3_outputData; - io_output_data[39 : 32] = s2_byteLogic_4_outputData; - io_output_data[47 : 40] = s2_byteLogic_5_outputData; - io_output_data[55 : 48] = s2_byteLogic_6_outputData; - io_output_data[63 : 56] = s2_byteLogic_7_outputData; - io_output_data[71 : 64] = s2_byteLogic_8_outputData; - io_output_data[79 : 72] = s2_byteLogic_9_outputData; - io_output_data[87 : 80] = s2_byteLogic_10_outputData; - io_output_data[95 : 88] = s2_byteLogic_11_outputData; - io_output_data[103 : 96] = s2_byteLogic_12_outputData; - io_output_data[111 : 104] = s2_byteLogic_13_outputData; - io_output_data[119 : 112] = s2_byteLogic_14_outputData; - io_output_data[127 : 120] = s2_byteLogic_15_outputData; - end - - assign when_DmaSg_l1493 = (s2_byteLogic_0_inputMask && ((! io_output_consume) || s2_byteLogic_0_buffer_valid)); - assign s2_byteLogic_1_lastUsed = (4'b0001 == io_output_lastByteUsed); - assign s2_byteLogic_1_inputMask = s2_input_payload_selValid[1]; - assign s2_byteLogic_1_inputData = _zz_s2_byteLogic_1_inputData; - assign s2_byteLogic_1_outputMask = (s2_byteLogic_1_buffer_valid || (s2_input_valid && s2_byteLogic_1_inputMask)); - assign s2_byteLogic_1_outputData = (s2_byteLogic_1_buffer_valid ? s2_byteLogic_1_buffer_data : s2_byteLogic_1_inputData); - assign when_DmaSg_l1493_1 = (s2_byteLogic_1_inputMask && ((! io_output_consume) || s2_byteLogic_1_buffer_valid)); - assign s2_byteLogic_2_lastUsed = (4'b0010 == io_output_lastByteUsed); - assign s2_byteLogic_2_inputMask = s2_input_payload_selValid[2]; - assign s2_byteLogic_2_inputData = _zz_s2_byteLogic_2_inputData; - assign s2_byteLogic_2_outputMask = (s2_byteLogic_2_buffer_valid || (s2_input_valid && s2_byteLogic_2_inputMask)); - assign s2_byteLogic_2_outputData = (s2_byteLogic_2_buffer_valid ? s2_byteLogic_2_buffer_data : s2_byteLogic_2_inputData); - assign when_DmaSg_l1493_2 = (s2_byteLogic_2_inputMask && ((! io_output_consume) || s2_byteLogic_2_buffer_valid)); - assign s2_byteLogic_3_lastUsed = (4'b0011 == io_output_lastByteUsed); - assign s2_byteLogic_3_inputMask = s2_input_payload_selValid[3]; - assign s2_byteLogic_3_inputData = _zz_s2_byteLogic_3_inputData; - assign s2_byteLogic_3_outputMask = (s2_byteLogic_3_buffer_valid || (s2_input_valid && s2_byteLogic_3_inputMask)); - assign s2_byteLogic_3_outputData = (s2_byteLogic_3_buffer_valid ? s2_byteLogic_3_buffer_data : s2_byteLogic_3_inputData); - assign when_DmaSg_l1493_3 = (s2_byteLogic_3_inputMask && ((! io_output_consume) || s2_byteLogic_3_buffer_valid)); - assign s2_byteLogic_4_lastUsed = (4'b0100 == io_output_lastByteUsed); - assign s2_byteLogic_4_inputMask = s2_input_payload_selValid[4]; - assign s2_byteLogic_4_inputData = _zz_s2_byteLogic_4_inputData; - assign s2_byteLogic_4_outputMask = (s2_byteLogic_4_buffer_valid || (s2_input_valid && s2_byteLogic_4_inputMask)); - assign s2_byteLogic_4_outputData = (s2_byteLogic_4_buffer_valid ? s2_byteLogic_4_buffer_data : s2_byteLogic_4_inputData); - assign when_DmaSg_l1493_4 = (s2_byteLogic_4_inputMask && ((! io_output_consume) || s2_byteLogic_4_buffer_valid)); - assign s2_byteLogic_5_lastUsed = (4'b0101 == io_output_lastByteUsed); - assign s2_byteLogic_5_inputMask = s2_input_payload_selValid[5]; - assign s2_byteLogic_5_inputData = _zz_s2_byteLogic_5_inputData; - assign s2_byteLogic_5_outputMask = (s2_byteLogic_5_buffer_valid || (s2_input_valid && s2_byteLogic_5_inputMask)); - assign s2_byteLogic_5_outputData = (s2_byteLogic_5_buffer_valid ? s2_byteLogic_5_buffer_data : s2_byteLogic_5_inputData); - assign when_DmaSg_l1493_5 = (s2_byteLogic_5_inputMask && ((! io_output_consume) || s2_byteLogic_5_buffer_valid)); - assign s2_byteLogic_6_lastUsed = (4'b0110 == io_output_lastByteUsed); - assign s2_byteLogic_6_inputMask = s2_input_payload_selValid[6]; - assign s2_byteLogic_6_inputData = _zz_s2_byteLogic_6_inputData; - assign s2_byteLogic_6_outputMask = (s2_byteLogic_6_buffer_valid || (s2_input_valid && s2_byteLogic_6_inputMask)); - assign s2_byteLogic_6_outputData = (s2_byteLogic_6_buffer_valid ? s2_byteLogic_6_buffer_data : s2_byteLogic_6_inputData); - assign when_DmaSg_l1493_6 = (s2_byteLogic_6_inputMask && ((! io_output_consume) || s2_byteLogic_6_buffer_valid)); - assign s2_byteLogic_7_lastUsed = (4'b0111 == io_output_lastByteUsed); - assign s2_byteLogic_7_inputMask = s2_input_payload_selValid[7]; - assign s2_byteLogic_7_inputData = _zz_s2_byteLogic_7_inputData; - assign s2_byteLogic_7_outputMask = (s2_byteLogic_7_buffer_valid || (s2_input_valid && s2_byteLogic_7_inputMask)); - assign s2_byteLogic_7_outputData = (s2_byteLogic_7_buffer_valid ? s2_byteLogic_7_buffer_data : s2_byteLogic_7_inputData); - assign when_DmaSg_l1493_7 = (s2_byteLogic_7_inputMask && ((! io_output_consume) || s2_byteLogic_7_buffer_valid)); - assign s2_byteLogic_8_lastUsed = (4'b1000 == io_output_lastByteUsed); - assign s2_byteLogic_8_inputMask = s2_input_payload_selValid[8]; - assign s2_byteLogic_8_inputData = _zz_s2_byteLogic_8_inputData; - assign s2_byteLogic_8_outputMask = (s2_byteLogic_8_buffer_valid || (s2_input_valid && s2_byteLogic_8_inputMask)); - assign s2_byteLogic_8_outputData = (s2_byteLogic_8_buffer_valid ? s2_byteLogic_8_buffer_data : s2_byteLogic_8_inputData); - assign when_DmaSg_l1493_8 = (s2_byteLogic_8_inputMask && ((! io_output_consume) || s2_byteLogic_8_buffer_valid)); - assign s2_byteLogic_9_lastUsed = (4'b1001 == io_output_lastByteUsed); - assign s2_byteLogic_9_inputMask = s2_input_payload_selValid[9]; - assign s2_byteLogic_9_inputData = _zz_s2_byteLogic_9_inputData; - assign s2_byteLogic_9_outputMask = (s2_byteLogic_9_buffer_valid || (s2_input_valid && s2_byteLogic_9_inputMask)); - assign s2_byteLogic_9_outputData = (s2_byteLogic_9_buffer_valid ? s2_byteLogic_9_buffer_data : s2_byteLogic_9_inputData); - assign when_DmaSg_l1493_9 = (s2_byteLogic_9_inputMask && ((! io_output_consume) || s2_byteLogic_9_buffer_valid)); - assign s2_byteLogic_10_lastUsed = (4'b1010 == io_output_lastByteUsed); - assign s2_byteLogic_10_inputMask = s2_input_payload_selValid[10]; - assign s2_byteLogic_10_inputData = _zz_s2_byteLogic_10_inputData; - assign s2_byteLogic_10_outputMask = (s2_byteLogic_10_buffer_valid || (s2_input_valid && s2_byteLogic_10_inputMask)); - assign s2_byteLogic_10_outputData = (s2_byteLogic_10_buffer_valid ? s2_byteLogic_10_buffer_data : s2_byteLogic_10_inputData); - assign when_DmaSg_l1493_10 = (s2_byteLogic_10_inputMask && ((! io_output_consume) || s2_byteLogic_10_buffer_valid)); - assign s2_byteLogic_11_lastUsed = (4'b1011 == io_output_lastByteUsed); - assign s2_byteLogic_11_inputMask = s2_input_payload_selValid[11]; - assign s2_byteLogic_11_inputData = _zz_s2_byteLogic_11_inputData; - assign s2_byteLogic_11_outputMask = (s2_byteLogic_11_buffer_valid || (s2_input_valid && s2_byteLogic_11_inputMask)); - assign s2_byteLogic_11_outputData = (s2_byteLogic_11_buffer_valid ? s2_byteLogic_11_buffer_data : s2_byteLogic_11_inputData); - assign when_DmaSg_l1493_11 = (s2_byteLogic_11_inputMask && ((! io_output_consume) || s2_byteLogic_11_buffer_valid)); - assign s2_byteLogic_12_lastUsed = (4'b1100 == io_output_lastByteUsed); - assign s2_byteLogic_12_inputMask = s2_input_payload_selValid[12]; - assign s2_byteLogic_12_inputData = _zz_s2_byteLogic_12_inputData; - assign s2_byteLogic_12_outputMask = (s2_byteLogic_12_buffer_valid || (s2_input_valid && s2_byteLogic_12_inputMask)); - assign s2_byteLogic_12_outputData = (s2_byteLogic_12_buffer_valid ? s2_byteLogic_12_buffer_data : s2_byteLogic_12_inputData); - assign when_DmaSg_l1493_12 = (s2_byteLogic_12_inputMask && ((! io_output_consume) || s2_byteLogic_12_buffer_valid)); - assign s2_byteLogic_13_lastUsed = (4'b1101 == io_output_lastByteUsed); - assign s2_byteLogic_13_inputMask = s2_input_payload_selValid[13]; - assign s2_byteLogic_13_inputData = _zz_s2_byteLogic_13_inputData; - assign s2_byteLogic_13_outputMask = (s2_byteLogic_13_buffer_valid || (s2_input_valid && s2_byteLogic_13_inputMask)); - assign s2_byteLogic_13_outputData = (s2_byteLogic_13_buffer_valid ? s2_byteLogic_13_buffer_data : s2_byteLogic_13_inputData); - assign when_DmaSg_l1493_13 = (s2_byteLogic_13_inputMask && ((! io_output_consume) || s2_byteLogic_13_buffer_valid)); - assign s2_byteLogic_14_lastUsed = (4'b1110 == io_output_lastByteUsed); - assign s2_byteLogic_14_inputMask = s2_input_payload_selValid[14]; - assign s2_byteLogic_14_inputData = _zz_s2_byteLogic_14_inputData; - assign s2_byteLogic_14_outputMask = (s2_byteLogic_14_buffer_valid || (s2_input_valid && s2_byteLogic_14_inputMask)); - assign s2_byteLogic_14_outputData = (s2_byteLogic_14_buffer_valid ? s2_byteLogic_14_buffer_data : s2_byteLogic_14_inputData); - assign when_DmaSg_l1493_14 = (s2_byteLogic_14_inputMask && ((! io_output_consume) || s2_byteLogic_14_buffer_valid)); - assign s2_byteLogic_15_lastUsed = (4'b1111 == io_output_lastByteUsed); - assign s2_byteLogic_15_inputMask = s2_input_payload_selValid[15]; - assign s2_byteLogic_15_inputData = _zz_s2_byteLogic_15_inputData; - assign s2_byteLogic_15_outputMask = (s2_byteLogic_15_buffer_valid || (s2_input_valid && s2_byteLogic_15_inputMask)); - assign s2_byteLogic_15_outputData = (s2_byteLogic_15_buffer_valid ? s2_byteLogic_15_buffer_data : s2_byteLogic_15_inputData); - assign when_DmaSg_l1493_15 = (s2_byteLogic_15_inputMask && ((! io_output_consume) || s2_byteLogic_15_buffer_valid)); - assign _zz_io_output_usedUntil = (((((((s2_byteLogic_1_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_5_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_9_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_15_lastUsed); - assign _zz_io_output_usedUntil_1 = (((((((s2_byteLogic_2_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); - assign _zz_io_output_usedUntil_2 = (((((((s2_byteLogic_4_lastUsed || s2_byteLogic_5_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); - assign _zz_io_output_usedUntil_3 = (((((((s2_byteLogic_8_lastUsed || s2_byteLogic_9_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); - assign io_output_usedUntil = _zz_io_output_usedUntil_4; - always @(posedge clk) begin - if(reset) begin - io_input_rValid <= 1'b0; - s0_output_rValid <= 1'b0; - s1_output_rValid <= 1'b0; - end else begin - if(io_input_ready) begin - io_input_rValid <= io_input_valid; - end - if(io_flush) begin - io_input_rValid <= 1'b0; - end - if(s0_output_ready) begin - s0_output_rValid <= s0_output_valid; - end - if(io_flush) begin - s0_output_rValid <= 1'b0; - end - if(s1_output_ready) begin - s1_output_rValid <= s1_output_valid; - end - if(io_flush) begin - s1_output_rValid <= 1'b0; - end - end - end - - always @(posedge clk) begin - if(io_input_ready) begin - io_input_rData_data <= io_input_payload_data; - io_input_rData_mask <= io_input_payload_mask; - end - if(s0_output_ready) begin - s0_output_rData_cmd_data <= s0_output_payload_cmd_data; - s0_output_rData_cmd_mask <= s0_output_payload_cmd_mask; - s0_output_rData_countOnes_0 <= s0_output_payload_countOnes_0; - s0_output_rData_countOnes_1 <= s0_output_payload_countOnes_1; - s0_output_rData_countOnes_2 <= s0_output_payload_countOnes_2; - s0_output_rData_countOnes_3 <= s0_output_payload_countOnes_3; - s0_output_rData_countOnes_4 <= s0_output_payload_countOnes_4; - s0_output_rData_countOnes_5 <= s0_output_payload_countOnes_5; - s0_output_rData_countOnes_6 <= s0_output_payload_countOnes_6; - s0_output_rData_countOnes_7 <= s0_output_payload_countOnes_7; - s0_output_rData_countOnes_8 <= s0_output_payload_countOnes_8; - s0_output_rData_countOnes_9 <= s0_output_payload_countOnes_9; - s0_output_rData_countOnes_10 <= s0_output_payload_countOnes_10; - s0_output_rData_countOnes_11 <= s0_output_payload_countOnes_11; - s0_output_rData_countOnes_12 <= s0_output_payload_countOnes_12; - s0_output_rData_countOnes_13 <= s0_output_payload_countOnes_13; - s0_output_rData_countOnes_14 <= s0_output_payload_countOnes_14; - s0_output_rData_countOnes_15 <= s0_output_payload_countOnes_15; - end - if(s1_input_fire) begin - s1_offset <= s1_offsetNext[3:0]; - end - if(io_flush) begin - s1_offset <= io_offset; - end - if(s1_input_fire) begin - s1_byteCounter <= (s1_byteCounter + _zz_s1_byteCounter); - end - if(io_flush) begin - s1_byteCounter <= 13'h0; - end - if(s1_output_ready) begin - s1_output_rData_cmd_data <= s1_output_payload_cmd_data; - s1_output_rData_cmd_mask <= s1_output_payload_cmd_mask; - s1_output_rData_index_0 <= s1_output_payload_index_0; - s1_output_rData_index_1 <= s1_output_payload_index_1; - s1_output_rData_index_2 <= s1_output_payload_index_2; - s1_output_rData_index_3 <= s1_output_payload_index_3; - s1_output_rData_index_4 <= s1_output_payload_index_4; - s1_output_rData_index_5 <= s1_output_payload_index_5; - s1_output_rData_index_6 <= s1_output_payload_index_6; - s1_output_rData_index_7 <= s1_output_payload_index_7; - s1_output_rData_index_8 <= s1_output_payload_index_8; - s1_output_rData_index_9 <= s1_output_payload_index_9; - s1_output_rData_index_10 <= s1_output_payload_index_10; - s1_output_rData_index_11 <= s1_output_payload_index_11; - s1_output_rData_index_12 <= s1_output_payload_index_12; - s1_output_rData_index_13 <= s1_output_payload_index_13; - s1_output_rData_index_14 <= s1_output_payload_index_14; - s1_output_rData_index_15 <= s1_output_payload_index_15; - s1_output_rData_last <= s1_output_payload_last; - s1_output_rData_sel_0 <= s1_output_payload_sel_0; - s1_output_rData_sel_1 <= s1_output_payload_sel_1; - s1_output_rData_sel_2 <= s1_output_payload_sel_2; - s1_output_rData_sel_3 <= s1_output_payload_sel_3; - s1_output_rData_sel_4 <= s1_output_payload_sel_4; - s1_output_rData_sel_5 <= s1_output_payload_sel_5; - s1_output_rData_sel_6 <= s1_output_payload_sel_6; - s1_output_rData_sel_7 <= s1_output_payload_sel_7; - s1_output_rData_sel_8 <= s1_output_payload_sel_8; - s1_output_rData_sel_9 <= s1_output_payload_sel_9; - s1_output_rData_sel_10 <= s1_output_payload_sel_10; - s1_output_rData_sel_11 <= s1_output_payload_sel_11; - s1_output_rData_sel_12 <= s1_output_payload_sel_12; - s1_output_rData_sel_13 <= s1_output_payload_sel_13; - s1_output_rData_sel_14 <= s1_output_payload_sel_14; - s1_output_rData_sel_15 <= s1_output_payload_sel_15; - s1_output_rData_selValid <= s1_output_payload_selValid; - end - if(io_output_consume) begin - s2_byteLogic_0_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_0_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493) begin - s2_byteLogic_0_buffer_valid <= 1'b1; - s2_byteLogic_0_buffer_data <= s2_byteLogic_0_inputData; - end - end - if(io_flush) begin - s2_byteLogic_0_buffer_valid <= (4'b0000 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_1_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_1_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_1) begin - s2_byteLogic_1_buffer_valid <= 1'b1; - s2_byteLogic_1_buffer_data <= s2_byteLogic_1_inputData; - end - end - if(io_flush) begin - s2_byteLogic_1_buffer_valid <= (4'b0001 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_2_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_2_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_2) begin - s2_byteLogic_2_buffer_valid <= 1'b1; - s2_byteLogic_2_buffer_data <= s2_byteLogic_2_inputData; - end - end - if(io_flush) begin - s2_byteLogic_2_buffer_valid <= (4'b0010 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_3_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_3_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_3) begin - s2_byteLogic_3_buffer_valid <= 1'b1; - s2_byteLogic_3_buffer_data <= s2_byteLogic_3_inputData; - end - end - if(io_flush) begin - s2_byteLogic_3_buffer_valid <= (4'b0011 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_4_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_4_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_4) begin - s2_byteLogic_4_buffer_valid <= 1'b1; - s2_byteLogic_4_buffer_data <= s2_byteLogic_4_inputData; - end - end - if(io_flush) begin - s2_byteLogic_4_buffer_valid <= (4'b0100 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_5_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_5_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_5) begin - s2_byteLogic_5_buffer_valid <= 1'b1; - s2_byteLogic_5_buffer_data <= s2_byteLogic_5_inputData; - end - end - if(io_flush) begin - s2_byteLogic_5_buffer_valid <= (4'b0101 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_6_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_6_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_6) begin - s2_byteLogic_6_buffer_valid <= 1'b1; - s2_byteLogic_6_buffer_data <= s2_byteLogic_6_inputData; - end - end - if(io_flush) begin - s2_byteLogic_6_buffer_valid <= (4'b0110 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_7_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_7_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_7) begin - s2_byteLogic_7_buffer_valid <= 1'b1; - s2_byteLogic_7_buffer_data <= s2_byteLogic_7_inputData; - end - end - if(io_flush) begin - s2_byteLogic_7_buffer_valid <= (4'b0111 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_8_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_8_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_8) begin - s2_byteLogic_8_buffer_valid <= 1'b1; - s2_byteLogic_8_buffer_data <= s2_byteLogic_8_inputData; - end - end - if(io_flush) begin - s2_byteLogic_8_buffer_valid <= (4'b1000 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_9_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_9_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_9) begin - s2_byteLogic_9_buffer_valid <= 1'b1; - s2_byteLogic_9_buffer_data <= s2_byteLogic_9_inputData; - end - end - if(io_flush) begin - s2_byteLogic_9_buffer_valid <= (4'b1001 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_10_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_10_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_10) begin - s2_byteLogic_10_buffer_valid <= 1'b1; - s2_byteLogic_10_buffer_data <= s2_byteLogic_10_inputData; - end - end - if(io_flush) begin - s2_byteLogic_10_buffer_valid <= (4'b1010 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_11_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_11_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_11) begin - s2_byteLogic_11_buffer_valid <= 1'b1; - s2_byteLogic_11_buffer_data <= s2_byteLogic_11_inputData; - end - end - if(io_flush) begin - s2_byteLogic_11_buffer_valid <= (4'b1011 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_12_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_12_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_12) begin - s2_byteLogic_12_buffer_valid <= 1'b1; - s2_byteLogic_12_buffer_data <= s2_byteLogic_12_inputData; - end - end - if(io_flush) begin - s2_byteLogic_12_buffer_valid <= (4'b1100 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_13_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_13_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_13) begin - s2_byteLogic_13_buffer_valid <= 1'b1; - s2_byteLogic_13_buffer_data <= s2_byteLogic_13_inputData; - end - end - if(io_flush) begin - s2_byteLogic_13_buffer_valid <= (4'b1101 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_14_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_14_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_14) begin - s2_byteLogic_14_buffer_valid <= 1'b1; - s2_byteLogic_14_buffer_data <= s2_byteLogic_14_inputData; - end - end - if(io_flush) begin - s2_byteLogic_14_buffer_valid <= (4'b1110 < io_offset); - end - if(io_output_consume) begin - s2_byteLogic_15_buffer_valid <= 1'b0; - end - if(s2_input_fire) begin - if(s2_input_payload_last) begin - s2_byteLogic_15_buffer_valid <= 1'b0; - end - if(when_DmaSg_l1493_15) begin - s2_byteLogic_15_buffer_valid <= 1'b1; - s2_byteLogic_15_buffer_data <= s2_byteLogic_15_inputData; - end - end - if(io_flush) begin - s2_byteLogic_15_buffer_valid <= (4'b1111 < io_offset); - end - end - - -endmodule - -module EfxDMA_DmaMemoryCore ( - input wire io_writes_0_cmd_valid, - output wire io_writes_0_cmd_ready, - input wire [9:0] io_writes_0_cmd_payload_address, - input wire [63:0] io_writes_0_cmd_payload_data, - input wire [7:0] io_writes_0_cmd_payload_mask, - input wire [1:0] io_writes_0_cmd_payload_priority, - input wire [6:0] io_writes_0_cmd_payload_context, - output wire io_writes_0_rsp_valid, - output wire [6:0] io_writes_0_rsp_payload_context, - input wire io_writes_1_cmd_valid, - output wire io_writes_1_cmd_ready, - input wire [9:0] io_writes_1_cmd_payload_address, - input wire [127:0] io_writes_1_cmd_payload_data, - input wire [15:0] io_writes_1_cmd_payload_mask, - input wire [6:0] io_writes_1_cmd_payload_context, - output wire io_writes_1_rsp_valid, - output wire [6:0] io_writes_1_rsp_payload_context, - input wire io_reads_0_cmd_valid, - output wire io_reads_0_cmd_ready, - input wire [9:0] io_reads_0_cmd_payload_address, - input wire [1:0] io_reads_0_cmd_payload_priority, - input wire [2:0] io_reads_0_cmd_payload_context, - output wire io_reads_0_rsp_valid, - input wire io_reads_0_rsp_ready, - output wire [63:0] io_reads_0_rsp_payload_data, - output wire [7:0] io_reads_0_rsp_payload_mask, - output wire [2:0] io_reads_0_rsp_payload_context, - input wire io_reads_1_cmd_valid, - output wire io_reads_1_cmd_ready, - input wire [9:0] io_reads_1_cmd_payload_address, - input wire [11:0] io_reads_1_cmd_payload_context, - output wire io_reads_1_rsp_valid, - input wire io_reads_1_rsp_ready, - output wire [127:0] io_reads_1_rsp_payload_data, - output wire [15:0] io_reads_1_rsp_payload_mask, - output wire [11:0] io_reads_1_rsp_payload_context, - input wire clk, - input wire reset -); - - reg [71:0] banks_0_ram_spinal_port1; - reg [71:0] banks_1_ram_spinal_port1; - wire [71:0] _zz_banks_0_ram_port; - wire [71:0] _zz_banks_1_ram_port; - wire [3:0] _zz_write_ports_0_priority_value; - wire [9:0] _zz_when_MemoryCore_l136; - wire [9:0] _zz_when_MemoryCore_l136_1; - reg [63:0] _zz_read_ports_0_buffer_bufferIn_payload_data; - reg [7:0] _zz_read_ports_0_buffer_bufferIn_payload_mask; - wire [3:0] _zz_read_ports_0_priority_value; - wire [9:0] _zz_when_MemoryCore_l221; - wire [9:0] _zz_when_MemoryCore_l221_1; - reg _zz_1; - reg _zz_2; - reg banks_0_write_valid; - reg [8:0] banks_0_write_payload_address; - reg [63:0] banks_0_write_payload_data_data; - reg [7:0] banks_0_write_payload_data_mask; - wire banks_0_read_cmd_valid; - wire [8:0] banks_0_read_cmd_payload; - wire [63:0] banks_0_read_rsp_data; - wire [7:0] banks_0_read_rsp_mask; - wire [71:0] _zz_banks_0_read_rsp_data; - wire banks_0_writeOr_value_valid; - wire [8:0] banks_0_writeOr_value_payload_address; - wire [63:0] banks_0_writeOr_value_payload_data_data; - wire [7:0] banks_0_writeOr_value_payload_data_mask; - wire banks_0_readOr_value_valid; - wire [8:0] banks_0_readOr_value_payload; - reg banks_1_write_valid; - reg [8:0] banks_1_write_payload_address; - reg [63:0] banks_1_write_payload_data_data; - reg [7:0] banks_1_write_payload_data_mask; - wire banks_1_read_cmd_valid; - wire [8:0] banks_1_read_cmd_payload; - wire [63:0] banks_1_read_rsp_data; - wire [7:0] banks_1_read_rsp_mask; - wire [71:0] _zz_banks_1_read_rsp_data; - wire banks_1_writeOr_value_valid; - wire [8:0] banks_1_writeOr_value_payload_address; - wire [63:0] banks_1_writeOr_value_payload_data_data; - wire [7:0] banks_1_writeOr_value_payload_data_mask; - wire banks_1_readOr_value_valid; - wire [8:0] banks_1_readOr_value_payload; - reg [3:0] write_ports_0_priority_value; - wire write_nodes_0_0_priority; - wire write_nodes_0_0_conflict; - wire write_nodes_0_1_priority; - wire write_nodes_0_1_conflict; - wire write_nodes_1_0_priority; - wire write_nodes_1_0_conflict; - wire write_nodes_1_1_priority; - wire write_nodes_1_1_conflict; - wire [0:0] write_arbiter_0_losedAgainst; - reg write_arbiter_0_doIt; - reg _zz_banks_0_writeOr_value_valid; - reg [8:0] _zz_banks_0_writeOr_value_valid_1; - reg [63:0] _zz_banks_0_writeOr_value_valid_2; - reg [7:0] _zz_banks_0_writeOr_value_valid_3; - wire when_MemoryCore_l136; - reg _zz_banks_1_writeOr_value_valid; - reg [8:0] _zz_banks_1_writeOr_value_valid_1; - reg [63:0] _zz_banks_1_writeOr_value_valid_2; - reg [7:0] _zz_banks_1_writeOr_value_valid_3; - wire when_MemoryCore_l136_1; - reg write_arbiter_0_doIt_regNext; - reg [6:0] io_writes_0_cmd_payload_context_regNext; - wire [0:0] write_arbiter_1_losedAgainst; - reg write_arbiter_1_doIt; - reg _zz_banks_0_writeOr_value_valid_4; - reg [8:0] _zz_banks_0_writeOr_value_valid_5; - reg [63:0] _zz_banks_0_writeOr_value_valid_6; - reg [7:0] _zz_banks_0_writeOr_value_valid_7; - wire when_MemoryCore_l136_2; - reg _zz_banks_1_writeOr_value_valid_4; - reg [8:0] _zz_banks_1_writeOr_value_valid_5; - reg [63:0] _zz_banks_1_writeOr_value_valid_6; - reg [7:0] _zz_banks_1_writeOr_value_valid_7; - wire when_MemoryCore_l136_3; - reg write_arbiter_1_doIt_regNext; - reg [6:0] io_writes_1_cmd_payload_context_regNext; - wire read_ports_0_buffer_s0_valid; - wire [2:0] read_ports_0_buffer_s0_payload_context; - wire [9:0] read_ports_0_buffer_s0_payload_address; - reg read_ports_0_buffer_s1_valid; - reg [2:0] read_ports_0_buffer_s1_payload_context; - reg [9:0] read_ports_0_buffer_s1_payload_address; - wire [0:0] read_ports_0_buffer_groupSel; - wire read_ports_0_buffer_bufferIn_valid; - wire read_ports_0_buffer_bufferIn_ready; - wire [63:0] read_ports_0_buffer_bufferIn_payload_data; - wire [7:0] read_ports_0_buffer_bufferIn_payload_mask; - wire [2:0] read_ports_0_buffer_bufferIn_payload_context; - wire read_ports_0_buffer_bufferOut_valid; - wire read_ports_0_buffer_bufferOut_ready; - wire [63:0] read_ports_0_buffer_bufferOut_payload_data; - wire [7:0] read_ports_0_buffer_bufferOut_payload_mask; - wire [2:0] read_ports_0_buffer_bufferOut_payload_context; - reg read_ports_0_buffer_bufferIn_rValidN; - reg [63:0] read_ports_0_buffer_bufferIn_rData_data; - reg [7:0] read_ports_0_buffer_bufferIn_rData_mask; - reg [2:0] read_ports_0_buffer_bufferIn_rData_context; - wire read_ports_0_buffer_full; - wire _zz_io_reads_0_cmd_ready; - wire read_ports_0_cmd_valid; - wire read_ports_0_cmd_ready; - wire [9:0] read_ports_0_cmd_payload_address; - wire [1:0] read_ports_0_cmd_payload_priority; - wire [2:0] read_ports_0_cmd_payload_context; - reg [3:0] read_ports_0_priority_value; - wire read_ports_1_buffer_s0_valid; - wire [11:0] read_ports_1_buffer_s0_payload_context; - wire [9:0] read_ports_1_buffer_s0_payload_address; - reg read_ports_1_buffer_s1_valid; - reg [11:0] read_ports_1_buffer_s1_payload_context; - reg [9:0] read_ports_1_buffer_s1_payload_address; - wire read_ports_1_buffer_bufferIn_valid; - wire read_ports_1_buffer_bufferIn_ready; - wire [127:0] read_ports_1_buffer_bufferIn_payload_data; - wire [15:0] read_ports_1_buffer_bufferIn_payload_mask; - wire [11:0] read_ports_1_buffer_bufferIn_payload_context; - wire read_ports_1_buffer_bufferOut_valid; - wire read_ports_1_buffer_bufferOut_ready; - wire [127:0] read_ports_1_buffer_bufferOut_payload_data; - wire [15:0] read_ports_1_buffer_bufferOut_payload_mask; - wire [11:0] read_ports_1_buffer_bufferOut_payload_context; - reg read_ports_1_buffer_bufferIn_rValidN; - reg [127:0] read_ports_1_buffer_bufferIn_rData_data; - reg [15:0] read_ports_1_buffer_bufferIn_rData_mask; - reg [11:0] read_ports_1_buffer_bufferIn_rData_context; - wire read_ports_1_buffer_full; - wire _zz_io_reads_1_cmd_ready; - wire read_ports_1_cmd_valid; - wire read_ports_1_cmd_ready; - wire [9:0] read_ports_1_cmd_payload_address; - wire [11:0] read_ports_1_cmd_payload_context; - wire read_nodes_0_0_priority; - wire read_nodes_0_0_conflict; - wire read_nodes_0_1_priority; - wire read_nodes_0_1_conflict; - wire read_nodes_1_0_priority; - wire read_nodes_1_0_conflict; - wire read_nodes_1_1_priority; - wire read_nodes_1_1_conflict; - wire [0:0] read_arbiter_0_losedAgainst; - wire read_arbiter_0_doIt; - reg _zz_banks_0_readOr_value_valid; - reg [8:0] _zz_banks_0_readOr_value_valid_1; - wire when_MemoryCore_l221; - reg _zz_banks_1_readOr_value_valid; - reg [8:0] _zz_banks_1_readOr_value_valid_1; - wire when_MemoryCore_l221_1; - wire [0:0] read_arbiter_1_losedAgainst; - wire read_arbiter_1_doIt; - reg _zz_banks_0_readOr_value_valid_2; - reg [8:0] _zz_banks_0_readOr_value_valid_3; - wire when_MemoryCore_l221_2; - reg _zz_banks_1_readOr_value_valid_2; - reg [8:0] _zz_banks_1_readOr_value_valid_3; - wire when_MemoryCore_l221_3; - reg [9:0] initialiser_counter; - wire initialiser_done; - wire when_MemoryCore_l239; - wire [71:0] _zz_banks_0_write_payload_data_data; - wire [71:0] _zz_banks_1_write_payload_data_data; - wire [81:0] _zz_banks_0_writeOr_value_valid_8; - wire [80:0] _zz_banks_0_writeOr_value_payload_address; - wire [71:0] _zz_banks_0_writeOr_value_payload_data_data; - wire [9:0] _zz_banks_0_readOr_value_valid_4; - wire [81:0] _zz_banks_1_writeOr_value_valid_8; - wire [80:0] _zz_banks_1_writeOr_value_payload_address; - wire [71:0] _zz_banks_1_writeOr_value_payload_data_data; - wire [9:0] _zz_banks_1_readOr_value_valid_4; - (* ram_style = "block" *) reg [71:0] banks_0_ram [0:511]; - (* ram_style = "block" *) reg [71:0] banks_1_ram [0:511]; - - assign _zz_write_ports_0_priority_value = {2'd0, io_writes_0_cmd_payload_priority}; - assign _zz_when_MemoryCore_l136 = (io_writes_0_cmd_payload_address ^ 10'h0); - assign _zz_when_MemoryCore_l136_1 = (io_writes_0_cmd_payload_address ^ 10'h001); - assign _zz_read_ports_0_priority_value = {2'd0, read_ports_0_cmd_payload_priority}; - assign _zz_when_MemoryCore_l221 = (read_ports_0_cmd_payload_address ^ 10'h0); - assign _zz_when_MemoryCore_l221_1 = (read_ports_0_cmd_payload_address ^ 10'h001); - assign _zz_banks_0_ram_port = {banks_0_write_payload_data_mask,banks_0_write_payload_data_data}; - assign _zz_banks_1_ram_port = {banks_1_write_payload_data_mask,banks_1_write_payload_data_data}; - always @(posedge clk) begin - if(_zz_2) begin - banks_0_ram[banks_0_write_payload_address] <= _zz_banks_0_ram_port; - end - end - - always @(posedge clk) begin - if(banks_0_read_cmd_valid) begin - banks_0_ram_spinal_port1 <= banks_0_ram[banks_0_read_cmd_payload]; - end - end - - always @(posedge clk) begin - if(_zz_1) begin - banks_1_ram[banks_1_write_payload_address] <= _zz_banks_1_ram_port; - end - end - - always @(posedge clk) begin - if(banks_1_read_cmd_valid) begin - banks_1_ram_spinal_port1 <= banks_1_ram[banks_1_read_cmd_payload]; - end - end - - initial begin - `ifndef SYNTHESIS - write_ports_0_priority_value = {$urandom}; - read_ports_0_priority_value = {$urandom}; - `endif - end - - always @(*) begin - case(read_ports_0_buffer_groupSel) - 1'b0 : begin - _zz_read_ports_0_buffer_bufferIn_payload_data = banks_0_read_rsp_data; - _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_0_read_rsp_mask; - end - default : begin - _zz_read_ports_0_buffer_bufferIn_payload_data = banks_1_read_rsp_data; - _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_1_read_rsp_mask; - end - endcase - end - - always @(*) begin - _zz_1 = 1'b0; - if(banks_1_write_valid) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(banks_0_write_valid) begin - _zz_2 = 1'b1; - end - end - - assign _zz_banks_0_read_rsp_data = banks_0_ram_spinal_port1; - assign banks_0_read_rsp_data = _zz_banks_0_read_rsp_data[63 : 0]; - assign banks_0_read_rsp_mask = _zz_banks_0_read_rsp_data[71 : 64]; - always @(*) begin - banks_0_write_valid = banks_0_writeOr_value_valid; - if(when_MemoryCore_l239) begin - banks_0_write_valid = 1'b1; - end - end - - always @(*) begin - banks_0_write_payload_address = banks_0_writeOr_value_payload_address; - if(when_MemoryCore_l239) begin - banks_0_write_payload_address = initialiser_counter[8:0]; - end - end - - always @(*) begin - banks_0_write_payload_data_data = banks_0_writeOr_value_payload_data_data; - if(when_MemoryCore_l239) begin - banks_0_write_payload_data_data = _zz_banks_0_write_payload_data_data[63 : 0]; - end - end - - always @(*) begin - banks_0_write_payload_data_mask = banks_0_writeOr_value_payload_data_mask; - if(when_MemoryCore_l239) begin - banks_0_write_payload_data_mask = _zz_banks_0_write_payload_data_data[71 : 64]; - end - end - - assign banks_0_read_cmd_valid = banks_0_readOr_value_valid; - assign banks_0_read_cmd_payload = banks_0_readOr_value_payload; - assign _zz_banks_1_read_rsp_data = banks_1_ram_spinal_port1; - assign banks_1_read_rsp_data = _zz_banks_1_read_rsp_data[63 : 0]; - assign banks_1_read_rsp_mask = _zz_banks_1_read_rsp_data[71 : 64]; - always @(*) begin - banks_1_write_valid = banks_1_writeOr_value_valid; - if(when_MemoryCore_l239) begin - banks_1_write_valid = 1'b1; - end - end - - always @(*) begin - banks_1_write_payload_address = banks_1_writeOr_value_payload_address; - if(when_MemoryCore_l239) begin - banks_1_write_payload_address = initialiser_counter[8:0]; - end - end - - always @(*) begin - banks_1_write_payload_data_data = banks_1_writeOr_value_payload_data_data; - if(when_MemoryCore_l239) begin - banks_1_write_payload_data_data = _zz_banks_1_write_payload_data_data[63 : 0]; - end - end - - always @(*) begin - banks_1_write_payload_data_mask = banks_1_writeOr_value_payload_data_mask; - if(when_MemoryCore_l239) begin - banks_1_write_payload_data_mask = _zz_banks_1_write_payload_data_data[71 : 64]; - end - end - - assign banks_1_read_cmd_valid = banks_1_readOr_value_valid; - assign banks_1_read_cmd_payload = banks_1_readOr_value_payload; - assign write_nodes_0_1_priority = 1'b0; - assign write_nodes_1_0_priority = 1'b1; - assign write_nodes_0_1_conflict = ((io_writes_0_cmd_valid && io_writes_1_cmd_valid) && (((io_writes_0_cmd_payload_address ^ io_writes_1_cmd_payload_address) & 10'h0) == 10'h0)); - assign write_nodes_1_0_conflict = write_nodes_0_1_conflict; - assign write_arbiter_0_losedAgainst = (write_nodes_0_1_conflict && (! write_nodes_0_1_priority)); - always @(*) begin - write_arbiter_0_doIt = (io_writes_0_cmd_valid && (write_arbiter_0_losedAgainst == 1'b0)); - if(when_MemoryCore_l239) begin - write_arbiter_0_doIt = 1'b0; - end - end - - assign when_MemoryCore_l136 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid = 1'b1; - end else begin - _zz_banks_0_writeOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_writeOr_value_valid_1 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_2 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136) begin - _zz_banks_0_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_3 = 8'h0; - end - end - - assign when_MemoryCore_l136_1 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136_1[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid = 1'b1; - end else begin - _zz_banks_1_writeOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_writeOr_value_valid_1 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; - end else begin - _zz_banks_1_writeOr_value_valid_2 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_1) begin - _zz_banks_1_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; - end else begin - _zz_banks_1_writeOr_value_valid_3 = 8'h0; - end - end - - assign io_writes_0_cmd_ready = write_arbiter_0_doIt; - assign io_writes_0_rsp_valid = write_arbiter_0_doIt_regNext; - assign io_writes_0_rsp_payload_context = io_writes_0_cmd_payload_context_regNext; - assign write_arbiter_1_losedAgainst = (write_nodes_1_0_conflict && (! write_nodes_1_0_priority)); - always @(*) begin - write_arbiter_1_doIt = (io_writes_1_cmd_valid && (write_arbiter_1_losedAgainst == 1'b0)); - if(when_MemoryCore_l239) begin - write_arbiter_1_doIt = 1'b0; - end - end - - assign when_MemoryCore_l136_2 = (write_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_4 = 1'b1; - end else begin - _zz_banks_0_writeOr_value_valid_4 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_writeOr_value_valid_5 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[63 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_6 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_2) begin - _zz_banks_0_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[7 : 0]; - end else begin - _zz_banks_0_writeOr_value_valid_7 = 8'h0; - end - end - - assign when_MemoryCore_l136_3 = (write_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_4 = 1'b1; - end else begin - _zz_banks_1_writeOr_value_valid_4 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_writeOr_value_valid_5 = 9'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[127 : 64]; - end else begin - _zz_banks_1_writeOr_value_valid_6 = 64'h0; - end - end - - always @(*) begin - if(when_MemoryCore_l136_3) begin - _zz_banks_1_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[15 : 8]; - end else begin - _zz_banks_1_writeOr_value_valid_7 = 8'h0; - end - end - - assign io_writes_1_cmd_ready = write_arbiter_1_doIt; - assign io_writes_1_rsp_valid = write_arbiter_1_doIt_regNext; - assign io_writes_1_rsp_payload_context = io_writes_1_cmd_payload_context_regNext; - assign read_ports_0_buffer_groupSel = read_ports_0_buffer_s1_payload_address[0 : 0]; - assign read_ports_0_buffer_bufferIn_valid = read_ports_0_buffer_s1_valid; - assign read_ports_0_buffer_bufferIn_payload_context = read_ports_0_buffer_s1_payload_context; - assign read_ports_0_buffer_bufferIn_payload_data = _zz_read_ports_0_buffer_bufferIn_payload_data; - assign read_ports_0_buffer_bufferIn_payload_mask = _zz_read_ports_0_buffer_bufferIn_payload_mask; - assign read_ports_0_buffer_bufferIn_ready = read_ports_0_buffer_bufferIn_rValidN; - assign read_ports_0_buffer_bufferOut_valid = (read_ports_0_buffer_bufferIn_valid || (! read_ports_0_buffer_bufferIn_rValidN)); - assign read_ports_0_buffer_bufferOut_payload_data = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_data : read_ports_0_buffer_bufferIn_rData_data); - assign read_ports_0_buffer_bufferOut_payload_mask = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_mask : read_ports_0_buffer_bufferIn_rData_mask); - assign read_ports_0_buffer_bufferOut_payload_context = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_context : read_ports_0_buffer_bufferIn_rData_context); - assign io_reads_0_rsp_valid = read_ports_0_buffer_bufferOut_valid; - assign read_ports_0_buffer_bufferOut_ready = io_reads_0_rsp_ready; - assign io_reads_0_rsp_payload_data = read_ports_0_buffer_bufferOut_payload_data; - assign io_reads_0_rsp_payload_mask = read_ports_0_buffer_bufferOut_payload_mask; - assign io_reads_0_rsp_payload_context = read_ports_0_buffer_bufferOut_payload_context; - assign read_ports_0_buffer_full = (read_ports_0_buffer_bufferOut_valid && (! read_ports_0_buffer_bufferOut_ready)); - assign _zz_io_reads_0_cmd_ready = (! read_ports_0_buffer_full); - assign read_ports_0_cmd_valid = (io_reads_0_cmd_valid && _zz_io_reads_0_cmd_ready); - assign io_reads_0_cmd_ready = (read_ports_0_cmd_ready && _zz_io_reads_0_cmd_ready); - assign read_ports_0_cmd_payload_address = io_reads_0_cmd_payload_address; - assign read_ports_0_cmd_payload_priority = io_reads_0_cmd_payload_priority; - assign read_ports_0_cmd_payload_context = io_reads_0_cmd_payload_context; - assign read_ports_1_buffer_bufferIn_valid = read_ports_1_buffer_s1_valid; - assign read_ports_1_buffer_bufferIn_payload_context = read_ports_1_buffer_s1_payload_context; - assign read_ports_1_buffer_bufferIn_payload_data = {banks_1_read_rsp_data,banks_0_read_rsp_data}; - assign read_ports_1_buffer_bufferIn_payload_mask = {banks_1_read_rsp_mask,banks_0_read_rsp_mask}; - assign read_ports_1_buffer_bufferIn_ready = read_ports_1_buffer_bufferIn_rValidN; - assign read_ports_1_buffer_bufferOut_valid = (read_ports_1_buffer_bufferIn_valid || (! read_ports_1_buffer_bufferIn_rValidN)); - assign read_ports_1_buffer_bufferOut_payload_data = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_data : read_ports_1_buffer_bufferIn_rData_data); - assign read_ports_1_buffer_bufferOut_payload_mask = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_mask : read_ports_1_buffer_bufferIn_rData_mask); - assign read_ports_1_buffer_bufferOut_payload_context = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_context : read_ports_1_buffer_bufferIn_rData_context); - assign io_reads_1_rsp_valid = read_ports_1_buffer_bufferOut_valid; - assign read_ports_1_buffer_bufferOut_ready = io_reads_1_rsp_ready; - assign io_reads_1_rsp_payload_data = read_ports_1_buffer_bufferOut_payload_data; - assign io_reads_1_rsp_payload_mask = read_ports_1_buffer_bufferOut_payload_mask; - assign io_reads_1_rsp_payload_context = read_ports_1_buffer_bufferOut_payload_context; - assign read_ports_1_buffer_full = (read_ports_1_buffer_bufferOut_valid && (! read_ports_1_buffer_bufferOut_ready)); - assign _zz_io_reads_1_cmd_ready = (! read_ports_1_buffer_full); - assign read_ports_1_cmd_valid = (io_reads_1_cmd_valid && _zz_io_reads_1_cmd_ready); - assign io_reads_1_cmd_ready = (read_ports_1_cmd_ready && _zz_io_reads_1_cmd_ready); - assign read_ports_1_cmd_payload_address = io_reads_1_cmd_payload_address; - assign read_ports_1_cmd_payload_context = io_reads_1_cmd_payload_context; - assign read_nodes_0_1_priority = 1'b0; - assign read_nodes_1_0_priority = 1'b1; - assign read_nodes_0_1_conflict = ((read_ports_0_cmd_valid && read_ports_1_cmd_valid) && (((read_ports_0_cmd_payload_address ^ io_reads_1_cmd_payload_address) & 10'h0) == 10'h0)); - assign read_nodes_1_0_conflict = read_nodes_0_1_conflict; - assign read_arbiter_0_losedAgainst = (read_nodes_0_1_conflict && (! read_nodes_0_1_priority)); - assign read_arbiter_0_doIt = (read_ports_0_cmd_valid && (read_arbiter_0_losedAgainst == 1'b0)); - assign when_MemoryCore_l221 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l221) begin - _zz_banks_0_readOr_value_valid = 1'b1; - end else begin - _zz_banks_0_readOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221) begin - _zz_banks_0_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_readOr_value_valid_1 = 9'h0; - end - end - - assign when_MemoryCore_l221_1 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221_1[0 : 0] == 1'b0)); - always @(*) begin - if(when_MemoryCore_l221_1) begin - _zz_banks_1_readOr_value_valid = 1'b1; - end else begin - _zz_banks_1_readOr_value_valid = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221_1) begin - _zz_banks_1_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_readOr_value_valid_1 = 9'h0; - end - end - - assign read_ports_0_cmd_ready = read_arbiter_0_doIt; - assign read_ports_0_buffer_s0_valid = read_arbiter_0_doIt; - assign read_ports_0_buffer_s0_payload_context = read_ports_0_cmd_payload_context; - assign read_ports_0_buffer_s0_payload_address = read_ports_0_cmd_payload_address; - assign read_arbiter_1_losedAgainst = (read_nodes_1_0_conflict && (! read_nodes_1_0_priority)); - assign read_arbiter_1_doIt = (read_ports_1_cmd_valid && (read_arbiter_1_losedAgainst == 1'b0)); - assign when_MemoryCore_l221_2 = (read_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l221_2) begin - _zz_banks_0_readOr_value_valid_2 = 1'b1; - end else begin - _zz_banks_0_readOr_value_valid_2 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221_2) begin - _zz_banks_0_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_0_readOr_value_valid_3 = 9'h0; - end - end - - assign when_MemoryCore_l221_3 = (read_arbiter_1_doIt && 1'b1); - always @(*) begin - if(when_MemoryCore_l221_3) begin - _zz_banks_1_readOr_value_valid_2 = 1'b1; - end else begin - _zz_banks_1_readOr_value_valid_2 = 1'b0; - end - end - - always @(*) begin - if(when_MemoryCore_l221_3) begin - _zz_banks_1_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); - end else begin - _zz_banks_1_readOr_value_valid_3 = 9'h0; - end - end - - assign read_ports_1_cmd_ready = read_arbiter_1_doIt; - assign read_ports_1_buffer_s0_valid = read_arbiter_1_doIt; - assign read_ports_1_buffer_s0_payload_context = read_ports_1_cmd_payload_context; - assign read_ports_1_buffer_s0_payload_address = read_ports_1_cmd_payload_address; - assign initialiser_done = initialiser_counter[9]; - assign when_MemoryCore_l239 = (! initialiser_done); - assign _zz_banks_0_write_payload_data_data = 72'h0; - assign _zz_banks_1_write_payload_data_data = 72'h0; - assign _zz_banks_0_writeOr_value_valid_8 = ({{{_zz_banks_0_writeOr_value_valid_3,_zz_banks_0_writeOr_value_valid_2},_zz_banks_0_writeOr_value_valid_1},_zz_banks_0_writeOr_value_valid} | {{{_zz_banks_0_writeOr_value_valid_7,_zz_banks_0_writeOr_value_valid_6},_zz_banks_0_writeOr_value_valid_5},_zz_banks_0_writeOr_value_valid_4}); - assign banks_0_writeOr_value_valid = _zz_banks_0_writeOr_value_valid_8[0]; - assign _zz_banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_valid_8[81 : 1]; - assign banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_payload_address[8 : 0]; - assign _zz_banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_address[80 : 9]; - assign banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_data_data[63 : 0]; - assign banks_0_writeOr_value_payload_data_mask = _zz_banks_0_writeOr_value_payload_data_data[71 : 64]; - assign _zz_banks_0_readOr_value_valid_4 = ({_zz_banks_0_readOr_value_valid_1,_zz_banks_0_readOr_value_valid} | {_zz_banks_0_readOr_value_valid_3,_zz_banks_0_readOr_value_valid_2}); - assign banks_0_readOr_value_valid = _zz_banks_0_readOr_value_valid_4[0]; - assign banks_0_readOr_value_payload = _zz_banks_0_readOr_value_valid_4[9 : 1]; - assign _zz_banks_1_writeOr_value_valid_8 = ({{{_zz_banks_1_writeOr_value_valid_3,_zz_banks_1_writeOr_value_valid_2},_zz_banks_1_writeOr_value_valid_1},_zz_banks_1_writeOr_value_valid} | {{{_zz_banks_1_writeOr_value_valid_7,_zz_banks_1_writeOr_value_valid_6},_zz_banks_1_writeOr_value_valid_5},_zz_banks_1_writeOr_value_valid_4}); - assign banks_1_writeOr_value_valid = _zz_banks_1_writeOr_value_valid_8[0]; - assign _zz_banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_valid_8[81 : 1]; - assign banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_payload_address[8 : 0]; - assign _zz_banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_address[80 : 9]; - assign banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_data_data[63 : 0]; - assign banks_1_writeOr_value_payload_data_mask = _zz_banks_1_writeOr_value_payload_data_data[71 : 64]; - assign _zz_banks_1_readOr_value_valid_4 = ({_zz_banks_1_readOr_value_valid_1,_zz_banks_1_readOr_value_valid} | {_zz_banks_1_readOr_value_valid_3,_zz_banks_1_readOr_value_valid_2}); - assign banks_1_readOr_value_valid = _zz_banks_1_readOr_value_valid_4[0]; - assign banks_1_readOr_value_payload = _zz_banks_1_readOr_value_valid_4[9 : 1]; - always @(posedge clk) begin - if(io_writes_0_cmd_valid) begin - write_ports_0_priority_value <= (write_ports_0_priority_value + _zz_write_ports_0_priority_value); - if(io_writes_0_cmd_ready) begin - write_ports_0_priority_value <= 4'b0000; - end - end - io_writes_0_cmd_payload_context_regNext <= io_writes_0_cmd_payload_context; - io_writes_1_cmd_payload_context_regNext <= io_writes_1_cmd_payload_context; - read_ports_0_buffer_s1_payload_context <= read_ports_0_buffer_s0_payload_context; - read_ports_0_buffer_s1_payload_address <= read_ports_0_buffer_s0_payload_address; - if(read_ports_0_buffer_bufferIn_ready) begin - read_ports_0_buffer_bufferIn_rData_data <= read_ports_0_buffer_bufferIn_payload_data; - read_ports_0_buffer_bufferIn_rData_mask <= read_ports_0_buffer_bufferIn_payload_mask; - read_ports_0_buffer_bufferIn_rData_context <= read_ports_0_buffer_bufferIn_payload_context; - end - if(read_ports_0_cmd_valid) begin - read_ports_0_priority_value <= (read_ports_0_priority_value + _zz_read_ports_0_priority_value); - if(read_ports_0_cmd_ready) begin - read_ports_0_priority_value <= 4'b0000; - end - end - read_ports_1_buffer_s1_payload_context <= read_ports_1_buffer_s0_payload_context; - read_ports_1_buffer_s1_payload_address <= read_ports_1_buffer_s0_payload_address; - if(read_ports_1_buffer_bufferIn_ready) begin - read_ports_1_buffer_bufferIn_rData_data <= read_ports_1_buffer_bufferIn_payload_data; - read_ports_1_buffer_bufferIn_rData_mask <= read_ports_1_buffer_bufferIn_payload_mask; - read_ports_1_buffer_bufferIn_rData_context <= read_ports_1_buffer_bufferIn_payload_context; - end - end - - always @(posedge clk) begin - if(reset) begin - write_arbiter_0_doIt_regNext <= 1'b0; - write_arbiter_1_doIt_regNext <= 1'b0; - read_ports_0_buffer_s1_valid <= 1'b0; - read_ports_0_buffer_bufferIn_rValidN <= 1'b1; - read_ports_1_buffer_s1_valid <= 1'b0; - read_ports_1_buffer_bufferIn_rValidN <= 1'b1; - initialiser_counter <= 10'h0; - end else begin - write_arbiter_0_doIt_regNext <= write_arbiter_0_doIt; - write_arbiter_1_doIt_regNext <= write_arbiter_1_doIt; - read_ports_0_buffer_s1_valid <= read_ports_0_buffer_s0_valid; - if(read_ports_0_buffer_bufferIn_valid) begin - read_ports_0_buffer_bufferIn_rValidN <= 1'b0; - end - if(read_ports_0_buffer_bufferOut_ready) begin - read_ports_0_buffer_bufferIn_rValidN <= 1'b1; - end - read_ports_1_buffer_s1_valid <= read_ports_1_buffer_s0_valid; - if(read_ports_1_buffer_bufferIn_valid) begin - read_ports_1_buffer_bufferIn_rValidN <= 1'b0; - end - if(read_ports_1_buffer_bufferOut_ready) begin - read_ports_1_buffer_bufferIn_rValidN <= 1'b1; - end - if(when_MemoryCore_l239) begin - initialiser_counter <= (initialiser_counter + 10'h001); - end - end - end - - -endmodule - -module EfxDMA_StreamFifo_1 ( - input wire io_push_valid, - output wire io_push_ready, - input wire [13:0] io_push_payload_context, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [13:0] io_pop_payload_context, - input wire io_flush, - output wire [2:0] io_occupancy, - output wire [2:0] io_availability, - input wire clk, - input wire reset -); - - reg [13:0] logic_ram_spinal_port1; - wire [2:0] _zz_logic_ptr_notPow2_counter; - wire [2:0] _zz_logic_ptr_notPow2_counter_1; - wire [0:0] _zz_logic_ptr_notPow2_counter_2; - wire [2:0] _zz_logic_ptr_notPow2_counter_3; - wire [0:0] _zz_logic_ptr_notPow2_counter_4; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [2:0] logic_ptr_push; - reg [2:0] logic_ptr_pop; - wire [2:0] logic_ptr_occupancy; - wire [2:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire when_Stream_l1283; - wire when_Stream_l1287; - reg [2:0] logic_ptr_notPow2_counter; - wire io_push_fire; - wire io_pop_fire; - wire logic_push_onRam_write_valid; - wire [2:0] logic_push_onRam_write_payload_address; - wire [13:0] logic_push_onRam_write_payload_data_context; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [2:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [2:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [2:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [2:0] logic_pop_sync_readPort_cmd_payload; - wire [13:0] logic_pop_sync_readPort_rsp_context; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [13:0] logic_pop_sync_readArbitation_translated_payload_context; - wire logic_pop_sync_readArbitation_fire; - reg [2:0] logic_pop_sync_popReg; - reg [13:0] logic_ram [0:6]; - - assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); - assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; - assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; - assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; - assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); - assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); - assign when_Stream_l1283 = (logic_ptr_push == 3'b110); - assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); - assign io_push_fire = (io_push_valid && io_push_ready); - assign io_pop_fire = (io_pop_valid && io_pop_ready); - assign logic_ptr_occupancy = logic_ptr_notPow2_counter; - assign io_push_ready = (! logic_ptr_full); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push; - assign logic_push_onRam_write_payload_data_context = io_push_payload_context; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[13 : 0]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (3'b111 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - logic_ptr_wentUp <= 1'b0; - logic_ptr_notPow2_counter <= 3'b000; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 3'b000; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 3'b001); - if(when_Stream_l1283) begin - logic_ptr_push <= 3'b000; - end - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 3'b001); - if(when_Stream_l1287) begin - logic_ptr_pop <= 3'b000; - end - end - if(io_flush) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - end - logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); - if(io_flush) begin - logic_ptr_notPow2_counter <= 3'b000; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 3'b000; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_StreamFifo ( - input wire io_push_valid, - output wire io_push_ready, - input wire [21:0] io_push_payload_context, - output wire io_pop_valid, - input wire io_pop_ready, - output wire [21:0] io_pop_payload_context, - input wire io_flush, - output wire [2:0] io_occupancy, - output wire [2:0] io_availability, - input wire clk, - input wire reset -); - - reg [21:0] logic_ram_spinal_port1; - wire [2:0] _zz_logic_ptr_notPow2_counter; - wire [2:0] _zz_logic_ptr_notPow2_counter_1; - wire [0:0] _zz_logic_ptr_notPow2_counter_2; - wire [2:0] _zz_logic_ptr_notPow2_counter_3; - wire [0:0] _zz_logic_ptr_notPow2_counter_4; - reg _zz_1; - wire logic_ptr_doPush; - wire logic_ptr_doPop; - wire logic_ptr_full; - wire logic_ptr_empty; - reg [2:0] logic_ptr_push; - reg [2:0] logic_ptr_pop; - wire [2:0] logic_ptr_occupancy; - wire [2:0] logic_ptr_popOnIo; - wire when_Stream_l1248; - reg logic_ptr_wentUp; - wire when_Stream_l1283; - wire when_Stream_l1287; - reg [2:0] logic_ptr_notPow2_counter; - wire io_push_fire; - wire io_pop_fire; - wire logic_push_onRam_write_valid; - wire [2:0] logic_push_onRam_write_payload_address; - wire [21:0] logic_push_onRam_write_payload_data_context; - wire logic_pop_addressGen_valid; - reg logic_pop_addressGen_ready; - wire [2:0] logic_pop_addressGen_payload; - wire logic_pop_addressGen_fire; - wire logic_pop_sync_readArbitation_valid; - wire logic_pop_sync_readArbitation_ready; - wire [2:0] logic_pop_sync_readArbitation_payload; - reg logic_pop_addressGen_rValid; - reg [2:0] logic_pop_addressGen_rData; - wire when_Stream_l375; - wire logic_pop_sync_readPort_cmd_valid; - wire [2:0] logic_pop_sync_readPort_cmd_payload; - wire [21:0] logic_pop_sync_readPort_rsp_context; - wire logic_pop_sync_readArbitation_translated_valid; - wire logic_pop_sync_readArbitation_translated_ready; - wire [21:0] logic_pop_sync_readArbitation_translated_payload_context; - wire logic_pop_sync_readArbitation_fire; - reg [2:0] logic_pop_sync_popReg; - reg [21:0] logic_ram [0:6]; - - assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); - assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; - assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; - assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; - assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; - end - end - - always @(posedge clk) begin - if(logic_pop_sync_readPort_cmd_valid) begin - logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_push_onRam_write_valid) begin - _zz_1 = 1'b1; - end - end - - assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); - assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); - assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); - assign when_Stream_l1283 = (logic_ptr_push == 3'b110); - assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); - assign io_push_fire = (io_push_valid && io_push_ready); - assign io_pop_fire = (io_pop_valid && io_pop_ready); - assign logic_ptr_occupancy = logic_ptr_notPow2_counter; - assign io_push_ready = (! logic_ptr_full); - assign logic_ptr_doPush = io_push_fire; - assign logic_push_onRam_write_valid = io_push_fire; - assign logic_push_onRam_write_payload_address = logic_ptr_push; - assign logic_push_onRam_write_payload_data_context = io_push_payload_context; - assign logic_pop_addressGen_valid = (! logic_ptr_empty); - assign logic_pop_addressGen_payload = logic_ptr_pop; - assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); - assign logic_ptr_doPop = logic_pop_addressGen_fire; - always @(*) begin - logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; - if(when_Stream_l375) begin - logic_pop_addressGen_ready = 1'b1; - end - end - - assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); - assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; - assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; - assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[21 : 0]; - assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; - assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; - assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; - assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; - assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; - assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; - assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; - assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; - assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); - assign logic_ptr_popOnIo = logic_pop_sync_popReg; - assign io_occupancy = logic_ptr_occupancy; - assign io_availability = (3'b111 - logic_ptr_occupancy); - always @(posedge clk) begin - if(reset) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - logic_ptr_wentUp <= 1'b0; - logic_ptr_notPow2_counter <= 3'b000; - logic_pop_addressGen_rValid <= 1'b0; - logic_pop_sync_popReg <= 3'b000; - end else begin - if(when_Stream_l1248) begin - logic_ptr_wentUp <= logic_ptr_doPush; - end - if(io_flush) begin - logic_ptr_wentUp <= 1'b0; - end - if(logic_ptr_doPush) begin - logic_ptr_push <= (logic_ptr_push + 3'b001); - if(when_Stream_l1283) begin - logic_ptr_push <= 3'b000; - end - end - if(logic_ptr_doPop) begin - logic_ptr_pop <= (logic_ptr_pop + 3'b001); - if(when_Stream_l1287) begin - logic_ptr_pop <= 3'b000; - end - end - if(io_flush) begin - logic_ptr_push <= 3'b000; - logic_ptr_pop <= 3'b000; - end - logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); - if(io_flush) begin - logic_ptr_notPow2_counter <= 3'b000; - end - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; - end - if(io_flush) begin - logic_pop_addressGen_rValid <= 1'b0; - end - if(logic_pop_sync_readArbitation_fire) begin - logic_pop_sync_popReg <= logic_ptr_pop; - end - if(io_flush) begin - logic_pop_sync_popReg <= 3'b000; - end - end - end - - always @(posedge clk) begin - if(logic_pop_addressGen_ready) begin - logic_pop_addressGen_rData <= logic_pop_addressGen_payload; - end - end - - -endmodule - -module EfxDMA_BufferCC_1 ( - input wire io_dataIn, - output wire io_dataOut, - input wire ctrl_clk, - input wire ctrl_reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge ctrl_clk) begin - if(ctrl_reset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module EfxDMA_BufferCC ( - input wire io_dataIn, - output wire io_dataOut, - input wire clk, - input wire reset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge clk) begin - if(reset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule diff --git a/fpga/ip/gDMA/source/dma_config.json b/fpga/ip/gDMA/source/dma_config.json deleted file mode 100644 index 1229f91..0000000 --- a/fpga/ip/gDMA/source/dma_config.json +++ /dev/null @@ -1,71 +0,0 @@ -{ - "name": "EfxDMA", - "efinix_ddr": false, - "with_sg_bus": false, - "with_ddr_write_queue": false, - "with_ddr_read_queue": false, - "ctrl": { - "asynchronous": true - }, - "buffer": { - "bank_count": 2, - "bank_width": 64, - "bank_words": 512 - }, - "read": { - "address_width": 32, - "data_width_external": 128, - "data_width_internal": 128 - }, - "write": { - "address_width": 32, - "data_width_external": 128, - "data_width_internal": 128 - }, - "channels": { - "c0": { - "progress_probe": true, - "direct_ctrl_capable": true, - "linked_list_capable": true, - "memory_to_memory": false, - "inputs": [ - "dat0_i" - ], - "half_completion_interrupt": false, - "self_restart_capable": false, - "bytes_per_burst": 1024, - "buffer_address": 0, - "buffer_size": 4096 - }, - "c1": { - "progress_probe": true, - "direct_ctrl_capable": true, - "linked_list_capable": true, - "memory_to_memory": false, - "outputs": [ - "dat1_o" - ], - "half_completion_interrupt": false, - "self_restart_capable": false, - "bytes_per_burst": 1024, - "buffer_address": 4096, - "buffer_size": 4096 - } - }, - "inputs": { - "dat0_i": { - "data_width": 8, - "tid_width": 0, - "tdest_width": 4, - "asynchronous": true - } - }, - "outputs": { - "dat1_o": { - "data_width": 8, - "tid_width": 0, - "tdest_width": 4, - "asynchronous": true - } - } -} \ No newline at end of file diff --git a/fpga/ip/gSDHC/.gitignore b/fpga/ip/gSDHC/.gitignore new file mode 100644 index 0000000..4e31dc3 --- /dev/null +++ b/fpga/ip/gSDHC/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!settings.json \ No newline at end of file diff --git a/fpga/ip/gSDHC/gSDHC.v b/fpga/ip/gSDHC/gSDHC.v deleted file mode 100644 index 718f399..0000000 --- a/fpga/ip/gSDHC/gSDHC.v +++ /dev/null @@ -1,12571 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 6.0 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _5b3f2212c953407c83e1cf8c9cc77ea9 -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gSDHC -( - input sd_rst, - input sd_base_clk, - output sd_int, - input sd_cd_n, - input sd_wp, - input [9:0] s_axi_awaddr, - input s_axi_aclk, - output s_axi_awready, - input s_axi_awvalid, - input [31:0] s_axi_wdata, - output s_axi_wready, - input s_axi_wvalid, - output [1:0] s_axi_bresp, - output s_axi_bvalid, - input [9:0] s_axi_araddr, - input s_axi_bready, - output s_axi_arready, - input s_axi_arvalid, - output [1:0] s_axi_rresp, - output [31:0] s_axi_rdata, - output s_axi_rvalid, - input s_axi_rready, - output [31:0] m_axi_awaddr, - output m_axi_awvalid, - input m_axi_clk, - output [7:0] m_axi_awlen, - input m_axi_awready, - output [2:0] m_axi_awsize, - output [3:0] m_axi_awcache, - output [1:0] m_axi_awlock, - output [2:0] m_axi_awprot, - output m_axi_wlast, - output m_axi_wvalid, - input m_axi_wready, - input [1:0] m_axi_bresp, - input m_axi_bvalid, - output m_axi_bready, - output m_axi_arvalid, - output [31:0] m_axi_araddr, - output [7:0] m_axi_arlen, - output [2:0] m_axi_arsize, - output [1:0] m_axi_arburst, - output [2:0] m_axi_arprot, - output [1:0] m_axi_arlock, - output [3:0] m_axi_arcache, - input m_axi_arready, - input m_axi_rvalid, - input m_axi_rlast, - input [1:0] m_axi_rresp, - output m_axi_rready, - output sd_clk_hi, - output sd_clk_lo, - input sd_cmd_i, - output sd_cmd_o, - output sd_cmd_oe, - input [3:0] sd_dat_i, - output [3:0] sd_dat_o, - output sd_dat_oe, - output [1:0] m_axi_awburst, - output [127:0] m_axi_wdata, - output [15:0] m_axi_wstrb, - input [127:0] m_axi_rdata, - input [3:0] s_axi_wstrb -); -`IP_MODULE_NAME(sdhc) -#( - .DATA_BUFFER_DEPTH (512), - .ADMA_DATA_WIDTH (128) -) -u_sdhc -( - .sd_rst ( sd_rst ), - .sd_base_clk ( sd_base_clk ), - .sd_int ( sd_int ), - .sd_cd_n ( sd_cd_n ), - .sd_wp ( sd_wp ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_aclk ( s_axi_aclk ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_bready ( s_axi_bready ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rready ( s_axi_rready ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_clk ( m_axi_clk ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awready ( m_axi_awready ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awprot ( m_axi_awprot ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wready ( m_axi_wready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_bready ( m_axi_bready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arready ( m_axi_arready ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_rready ( m_axi_rready ), - .sd_clk_hi ( sd_clk_hi ), - .sd_clk_lo ( sd_clk_lo ), - .sd_cmd_i ( sd_cmd_i ), - .sd_cmd_o ( sd_cmd_o ), - .sd_cmd_oe ( sd_cmd_oe ), - .sd_dat_i ( sd_dat_i ), - .sd_dat_o ( sd_dat_o ), - .sd_dat_oe ( sd_dat_oe ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_rdata ( m_axi_rdata ), - .s_axi_wstrb ( s_axi_wstrb ) -); -endmodule - -// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 -// Component : Asic32To128UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 -// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a - -`timescale 1ns/1ps - -module Asic32To128UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - input io_input_ar_valid, - output io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output [7:0] io_output_aw_payload_len, - output [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [127:0] io_output_w_payload_data, - output [15:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [127:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire readOnly_io_input_ar_ready; - wire readOnly_io_input_r_valid; - wire [31:0] readOnly_io_input_r_payload_data; - wire [7:0] readOnly_io_input_r_payload_id; - wire [1:0] readOnly_io_input_r_payload_resp; - wire readOnly_io_input_r_payload_last; - wire readOnly_io_output_ar_valid; - wire [31:0] readOnly_io_output_ar_payload_addr; - wire [7:0] readOnly_io_output_ar_payload_id; - wire [3:0] readOnly_io_output_ar_payload_region; - wire [7:0] readOnly_io_output_ar_payload_len; - wire [2:0] readOnly_io_output_ar_payload_size; - wire [1:0] readOnly_io_output_ar_payload_burst; - wire [0:0] readOnly_io_output_ar_payload_lock; - wire [3:0] readOnly_io_output_ar_payload_cache; - wire [3:0] readOnly_io_output_ar_payload_qos; - wire [2:0] readOnly_io_output_ar_payload_prot; - wire readOnly_io_output_r_ready; - wire writeOnly_io_input_aw_ready; - wire writeOnly_io_input_w_ready; - wire writeOnly_io_input_b_valid; - wire [7:0] writeOnly_io_input_b_payload_id; - wire [1:0] writeOnly_io_input_b_payload_resp; - wire writeOnly_io_output_aw_valid; - wire [31:0] writeOnly_io_output_aw_payload_addr; - wire [7:0] writeOnly_io_output_aw_payload_id; - wire [3:0] writeOnly_io_output_aw_payload_region; - wire [7:0] writeOnly_io_output_aw_payload_len; - wire [2:0] writeOnly_io_output_aw_payload_size; - wire [1:0] writeOnly_io_output_aw_payload_burst; - wire [0:0] writeOnly_io_output_aw_payload_lock; - wire [3:0] writeOnly_io_output_aw_payload_cache; - wire [3:0] writeOnly_io_output_aw_payload_qos; - wire [2:0] writeOnly_io_output_aw_payload_prot; - wire writeOnly_io_output_w_valid; - wire [127:0] writeOnly_io_output_w_payload_data; - wire [15:0] writeOnly_io_output_w_payload_strb; - wire writeOnly_io_output_w_payload_last; - wire writeOnly_io_output_b_ready; - - Asic32To128UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( - .io_input_ar_valid (io_input_ar_valid ), //i - .io_input_ar_ready (readOnly_io_input_ar_ready ), //o - .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i - .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i - .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i - .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i - .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i - .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i - .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i - .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i - .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i - .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i - .io_input_r_valid (readOnly_io_input_r_valid ), //o - .io_input_r_ready (io_input_r_ready ), //i - .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o - .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o - .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o - .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o - .io_output_ar_valid (readOnly_io_output_ar_valid ), //o - .io_output_ar_ready (io_output_ar_ready ), //i - .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o - .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o - .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o - .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o - .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o - .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o - .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o - .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o - .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o - .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o - .io_output_r_valid (io_output_r_valid ), //i - .io_output_r_ready (readOnly_io_output_r_ready ), //o - .io_output_r_payload_data (io_output_r_payload_data[127:0] ), //i - .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i - .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i - .io_output_r_payload_last (io_output_r_payload_last ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Asic32To128UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( - .io_input_aw_valid (io_input_aw_valid ), //i - .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o - .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i - .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i - .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i - .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i - .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i - .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i - .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i - .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i - .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i - .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i - .io_input_w_valid (io_input_w_valid ), //i - .io_input_w_ready (writeOnly_io_input_w_ready ), //o - .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i - .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i - .io_input_w_payload_last (io_input_w_payload_last ), //i - .io_input_b_valid (writeOnly_io_input_b_valid ), //o - .io_input_b_ready (io_input_b_ready ), //i - .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o - .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o - .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o - .io_output_aw_ready (io_output_aw_ready ), //i - .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o - .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o - .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o - .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o - .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o - .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o - .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o - .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o - .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o - .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o - .io_output_w_valid (writeOnly_io_output_w_valid ), //o - .io_output_w_ready (io_output_w_ready ), //i - .io_output_w_payload_data (writeOnly_io_output_w_payload_data[127:0] ), //o - .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[15:0] ), //o - .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o - .io_output_b_valid (io_output_b_valid ), //i - .io_output_b_ready (writeOnly_io_output_b_ready ), //o - .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i - .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_ar_ready = readOnly_io_input_ar_ready; - assign io_input_r_valid = readOnly_io_input_r_valid; - assign io_input_r_payload_data = readOnly_io_input_r_payload_data; - assign io_input_r_payload_id = readOnly_io_input_r_payload_id; - assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; - assign io_input_r_payload_last = readOnly_io_input_r_payload_last; - assign io_input_aw_ready = writeOnly_io_input_aw_ready; - assign io_input_w_ready = writeOnly_io_input_w_ready; - assign io_input_b_valid = writeOnly_io_input_b_valid; - assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; - assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; - assign io_output_ar_valid = readOnly_io_output_ar_valid; - assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; - assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; - assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; - assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; - assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; - assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; - assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; - assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; - assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; - assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; - assign io_output_r_ready = readOnly_io_output_r_ready; - assign io_output_aw_valid = writeOnly_io_output_aw_valid; - assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; - assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; - assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; - assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; - assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; - assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; - assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; - assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; - assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; - assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; - assign io_output_w_valid = writeOnly_io_output_w_valid; - assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; - assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; - assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; - assign io_output_b_ready = writeOnly_io_output_b_ready; - -endmodule - -module Asic32To128UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output reg io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output reg [7:0] io_output_aw_payload_len, - output reg [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [127:0] io_output_w_payload_data, - output [15:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - input clk, - input reset -); - - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [3:0] _zz_cmdLogic_incrLen_2; - wire [4:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [15:0] _zz_dataLogic_byteActivity; - wire [1:0] _zz_dataLogic_byteActivity_1; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_aw_fork2_logic_linkEnable_0; - reg io_input_aw_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [6:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l21; - wire when_Axi4Upsizer_l24; - reg [3:0] dataLogic_byteCounter; - reg [2:0] dataLogic_size; - reg dataLogic_outputValid; - reg dataLogic_outputLast; - reg dataLogic_busy; - reg dataLogic_incrementByteCounter; - reg dataLogic_alwaysFire; - wire [4:0] dataLogic_byteCounterNext; - reg [127:0] dataLogic_dataBuffer; - reg [15:0] dataLogic_maskBuffer; - wire [15:0] dataLogic_byteActivity; - wire io_output_w_fire; - wire io_output_w_isStall; - wire io_input_w_fire; - wire when_Axi4Upsizer_l59; - wire when_Axi4Upsizer_l59_1; - wire when_Axi4Upsizer_l59_2; - wire when_Axi4Upsizer_l59_3; - wire when_Axi4Upsizer_l59_4; - wire when_Axi4Upsizer_l59_5; - wire when_Axi4Upsizer_l59_6; - wire when_Axi4Upsizer_l59_7; - wire when_Axi4Upsizer_l59_8; - wire when_Axi4Upsizer_l59_9; - wire when_Axi4Upsizer_l59_10; - wire when_Axi4Upsizer_l59_11; - wire when_Axi4Upsizer_l59_12; - wire when_Axi4Upsizer_l59_13; - wire when_Axi4Upsizer_l59_14; - wire when_Axi4Upsizer_l59_15; - wire cmdLogic_dataFork_fire_1; - wire when_Axi4Upsizer_l68; - wire when_Axi4Upsizer_l68_1; - wire when_Axi4Upsizer_l68_2; - wire when_Axi4Upsizer_l68_3; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[3 : 0]; - assign _zz_cmdLogic_incrLen_1 = {7'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[4:0]; - assign _zz_dataLogic_byteActivity_1 = dataLogic_size[1:0]; - always @(*) begin - case(_zz_dataLogic_byteActivity_1) - 2'b00 : _zz_dataLogic_byteActivity = 16'h0001; - 2'b01 : _zz_dataLogic_byteActivity = 16'h0003; - 2'b10 : _zz_dataLogic_byteActivity = 16'h000f; - default : _zz_dataLogic_byteActivity = 16'h00ff; - endcase - end - - always @(*) begin - io_input_aw_ready = 1'b1; - if(when_Stream_l993) begin - io_input_aw_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_aw_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_aw_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_aw_ready; - assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; - assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; - always @(*) begin - io_output_aw_payload_len = cmdLogic_outputFork_payload_len; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_len = {1'd0, cmdLogic_incrLen}; - end - end - - always @(*) begin - io_output_aw_payload_size = cmdLogic_outputFork_payload_size; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_size = 3'b100; - if(when_Axi4Upsizer_l24) begin - io_output_aw_payload_size = io_input_aw_payload_size; - end - end - end - - assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 4]; - assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); - assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); - assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); - assign io_output_w_valid = dataLogic_outputValid; - assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); - assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); - assign io_output_w_payload_data = dataLogic_dataBuffer; - assign io_output_w_payload_strb = dataLogic_maskBuffer; - assign io_output_w_payload_last = dataLogic_outputLast; - assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); - assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; - assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; - assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; - assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; - assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; - assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; - assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; - assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; - assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; - assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; - assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; - assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; - assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; - assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; - assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; - assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; - assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); - assign cmdLogic_dataFork_ready = (! dataLogic_busy); - assign io_input_b_valid = io_output_b_valid; - assign io_output_b_ready = io_input_b_ready; - assign io_input_b_payload_id = io_output_b_payload_id; - assign io_input_b_payload_resp = io_output_b_payload_resp; - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_outputValid <= 1'b0; - dataLogic_busy <= 1'b0; - dataLogic_maskBuffer <= 16'h0000; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_aw_ready) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - end - if(io_output_w_ready) begin - dataLogic_outputValid <= 1'b0; - end - if(io_output_w_fire) begin - dataLogic_maskBuffer <= 16'h0000; - end - if(io_input_w_fire) begin - dataLogic_outputValid <= ((dataLogic_byteCounterNext[4] || io_input_w_payload_last) || dataLogic_alwaysFire); - if(io_input_w_payload_last) begin - dataLogic_busy <= 1'b0; - end - if(when_Axi4Upsizer_l59) begin - dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_8) begin - dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_9) begin - dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_10) begin - dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_11) begin - dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_12) begin - dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_13) begin - dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_14) begin - dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_15) begin - dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_busy <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(io_input_w_fire) begin - if(dataLogic_incrementByteCounter) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[3:0]; - end - dataLogic_outputLast <= io_input_w_payload_last; - if(when_Axi4Upsizer_l59) begin - dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_8) begin - dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_9) begin - dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_10) begin - dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_11) begin - dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_12) begin - dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_13) begin - dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_14) begin - dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_15) begin - dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[3:0]; - if(when_Axi4Upsizer_l68) begin - dataLogic_byteCounter[0] <= 1'b0; - end - if(when_Axi4Upsizer_l68_1) begin - dataLogic_byteCounter[1] <= 1'b0; - end - if(when_Axi4Upsizer_l68_2) begin - dataLogic_byteCounter[2] <= 1'b0; - end - if(when_Axi4Upsizer_l68_3) begin - dataLogic_byteCounter[3] <= 1'b0; - end - dataLogic_size <= cmdLogic_dataFork_payload_size; - dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); - dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); - end - end - - -endmodule - -module Asic32To128UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_ar_valid, - output reg io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output reg [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [127:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire dataLogic_cmdPush_fifo_io_pop_ready; - wire dataLogic_cmdPush_fifo_io_push_ready; - wire dataLogic_cmdPush_fifo_io_pop_valid; - wire [3:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; - wire [3:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; - wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; - wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; - wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; - wire [4:0] dataLogic_cmdPush_fifo_io_availability; - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [3:0] _zz_cmdLogic_incrLen_2; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; - wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; - wire [4:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [31:0] _zz_io_input_r_payload_data; - wire [1:0] _zz_io_input_r_payload_data_1; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_ar_fork2_logic_linkEnable_0; - reg io_input_ar_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [6:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l108; - wire dataLogic_cmdPush_valid; - wire dataLogic_cmdPush_ready; - wire [3:0] dataLogic_cmdPush_payload_startAt; - wire [3:0] dataLogic_cmdPush_payload_endAt; - wire [2:0] dataLogic_cmdPush_payload_size; - wire [7:0] dataLogic_cmdPush_payload_id; - reg [2:0] dataLogic_size; - reg dataLogic_busy; - reg [7:0] dataLogic_id; - reg [3:0] dataLogic_byteCounter; - reg [3:0] dataLogic_byteCounterLast; - wire [4:0] dataLogic_byteCounterNext; - wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; - wire io_input_r_fire; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[3 : 0]; - assign _zz_cmdLogic_incrLen_1 = {7'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); - assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); - assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[4:0]; - assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); - Asic32To128UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( - .io_push_valid (dataLogic_cmdPush_valid ), //i - .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o - .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[3:0] ), //i - .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[3:0] ), //i - .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i - .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i - .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o - .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i - .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[3:0]), //o - .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[3:0] ), //o - .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o - .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o - .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(_zz_io_input_r_payload_data_1) - 2'b00 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; - 2'b01 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; - 2'b10 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; - default : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; - endcase - end - - always @(*) begin - io_input_ar_ready = 1'b1; - if(when_Stream_l993) begin - io_input_ar_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_ar_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_ar_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_ar_ready; - assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; - assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 4]; - always @(*) begin - io_output_ar_payload_size = 3'b100; - if(when_Axi4Upsizer_l108) begin - io_output_ar_payload_size = io_input_ar_payload_size; - end - end - - assign io_output_ar_payload_len = {1'd0, cmdLogic_incrLen}; - assign io_output_ar_payload_id = 8'h00; - assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); - assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; - assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; - assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[3:0]; - assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[3:0]; - assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; - assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; - assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); - assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); - assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); - assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); - assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); - assign io_input_r_payload_resp = io_output_r_payload_resp; - assign io_input_r_payload_data = _zz_io_input_r_payload_data; - assign io_input_r_payload_id = dataLogic_id; - assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[4])); - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_busy <= 1'b0; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_ar_ready) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - end - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_busy <= 1'b1; - end - if(io_input_r_fire) begin - if(io_input_r_payload_last) begin - dataLogic_busy <= 1'b0; - end - end - end - end - - always @(posedge clk) begin - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; - dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; - dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; - dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; - end - if(io_input_r_fire) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[3:0]; - end - end - - -endmodule - -module Asic32To128UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_push_valid, - output io_push_ready, - input [3:0] io_push_payload_startAt, - input [3:0] io_push_payload_endAt, - input [2:0] io_push_payload_size, - input [7:0] io_push_payload_id, - output io_pop_valid, - input io_pop_ready, - output [3:0] io_pop_payload_startAt, - output [3:0] io_pop_payload_endAt, - output [2:0] io_pop_payload_size, - output [7:0] io_pop_payload_id, - input io_flush, - output [4:0] io_occupancy, - output [4:0] io_availability, - input clk, - input reset -); - - reg [18:0] _zz_logic_ram_port0; - wire [3:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [3:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz__zz_logic_ram_port0; - wire _zz__zz_io_pop_payload_startAt; - wire [18:0] _zz__zz_logic_ram_port1; - wire [3:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [3:0] logic_pushPtr_valueNext; - reg [3:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [3:0] logic_popPtr_valueNext; - reg [3:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [18:0] _zz_io_pop_payload_startAt; - wire when_Stream_l1123; - wire [3:0] logic_ptrDif; - reg [18:0] logic_ram [0:15]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_startAt = 1'b1; - assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; - always @(posedge clk) begin - if(_zz__zz_io_pop_payload_startAt) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 4'b0000; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 4'b0000; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; - assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[3 : 0]; - assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[7 : 4]; - assign io_pop_payload_size = _zz_io_pop_payload_startAt[10 : 8]; - assign io_pop_payload_id = _zz_io_pop_payload_startAt[18 : 11]; - assign when_Stream_l1123 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge clk or posedge reset) begin - if(reset) begin - logic_pushPtr_value <= 4'b0000; - logic_popPtr_value <= 4'b0000; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1123) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - - -// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 -// Component : Asic32To256UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 -// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a - -`timescale 1ns/1ps - -module Asic32To256UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - input io_input_ar_valid, - output io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output [7:0] io_output_aw_payload_len, - output [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [255:0] io_output_w_payload_data, - output [31:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [255:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire readOnly_io_input_ar_ready; - wire readOnly_io_input_r_valid; - wire [31:0] readOnly_io_input_r_payload_data; - wire [7:0] readOnly_io_input_r_payload_id; - wire [1:0] readOnly_io_input_r_payload_resp; - wire readOnly_io_input_r_payload_last; - wire readOnly_io_output_ar_valid; - wire [31:0] readOnly_io_output_ar_payload_addr; - wire [7:0] readOnly_io_output_ar_payload_id; - wire [3:0] readOnly_io_output_ar_payload_region; - wire [7:0] readOnly_io_output_ar_payload_len; - wire [2:0] readOnly_io_output_ar_payload_size; - wire [1:0] readOnly_io_output_ar_payload_burst; - wire [0:0] readOnly_io_output_ar_payload_lock; - wire [3:0] readOnly_io_output_ar_payload_cache; - wire [3:0] readOnly_io_output_ar_payload_qos; - wire [2:0] readOnly_io_output_ar_payload_prot; - wire readOnly_io_output_r_ready; - wire writeOnly_io_input_aw_ready; - wire writeOnly_io_input_w_ready; - wire writeOnly_io_input_b_valid; - wire [7:0] writeOnly_io_input_b_payload_id; - wire [1:0] writeOnly_io_input_b_payload_resp; - wire writeOnly_io_output_aw_valid; - wire [31:0] writeOnly_io_output_aw_payload_addr; - wire [7:0] writeOnly_io_output_aw_payload_id; - wire [3:0] writeOnly_io_output_aw_payload_region; - wire [7:0] writeOnly_io_output_aw_payload_len; - wire [2:0] writeOnly_io_output_aw_payload_size; - wire [1:0] writeOnly_io_output_aw_payload_burst; - wire [0:0] writeOnly_io_output_aw_payload_lock; - wire [3:0] writeOnly_io_output_aw_payload_cache; - wire [3:0] writeOnly_io_output_aw_payload_qos; - wire [2:0] writeOnly_io_output_aw_payload_prot; - wire writeOnly_io_output_w_valid; - wire [255:0] writeOnly_io_output_w_payload_data; - wire [31:0] writeOnly_io_output_w_payload_strb; - wire writeOnly_io_output_w_payload_last; - wire writeOnly_io_output_b_ready; - - Asic32To256UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( - .io_input_ar_valid (io_input_ar_valid ), //i - .io_input_ar_ready (readOnly_io_input_ar_ready ), //o - .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i - .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i - .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i - .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i - .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i - .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i - .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i - .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i - .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i - .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i - .io_input_r_valid (readOnly_io_input_r_valid ), //o - .io_input_r_ready (io_input_r_ready ), //i - .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o - .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o - .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o - .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o - .io_output_ar_valid (readOnly_io_output_ar_valid ), //o - .io_output_ar_ready (io_output_ar_ready ), //i - .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o - .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o - .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o - .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o - .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o - .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o - .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o - .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o - .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o - .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o - .io_output_r_valid (io_output_r_valid ), //i - .io_output_r_ready (readOnly_io_output_r_ready ), //o - .io_output_r_payload_data (io_output_r_payload_data[255:0] ), //i - .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i - .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i - .io_output_r_payload_last (io_output_r_payload_last ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Asic32To256UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( - .io_input_aw_valid (io_input_aw_valid ), //i - .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o - .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i - .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i - .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i - .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i - .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i - .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i - .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i - .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i - .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i - .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i - .io_input_w_valid (io_input_w_valid ), //i - .io_input_w_ready (writeOnly_io_input_w_ready ), //o - .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i - .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i - .io_input_w_payload_last (io_input_w_payload_last ), //i - .io_input_b_valid (writeOnly_io_input_b_valid ), //o - .io_input_b_ready (io_input_b_ready ), //i - .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o - .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o - .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o - .io_output_aw_ready (io_output_aw_ready ), //i - .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o - .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o - .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o - .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o - .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o - .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o - .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o - .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o - .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o - .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o - .io_output_w_valid (writeOnly_io_output_w_valid ), //o - .io_output_w_ready (io_output_w_ready ), //i - .io_output_w_payload_data (writeOnly_io_output_w_payload_data[255:0] ), //o - .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[31:0] ), //o - .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o - .io_output_b_valid (io_output_b_valid ), //i - .io_output_b_ready (writeOnly_io_output_b_ready ), //o - .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i - .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_ar_ready = readOnly_io_input_ar_ready; - assign io_input_r_valid = readOnly_io_input_r_valid; - assign io_input_r_payload_data = readOnly_io_input_r_payload_data; - assign io_input_r_payload_id = readOnly_io_input_r_payload_id; - assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; - assign io_input_r_payload_last = readOnly_io_input_r_payload_last; - assign io_input_aw_ready = writeOnly_io_input_aw_ready; - assign io_input_w_ready = writeOnly_io_input_w_ready; - assign io_input_b_valid = writeOnly_io_input_b_valid; - assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; - assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; - assign io_output_ar_valid = readOnly_io_output_ar_valid; - assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; - assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; - assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; - assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; - assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; - assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; - assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; - assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; - assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; - assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; - assign io_output_r_ready = readOnly_io_output_r_ready; - assign io_output_aw_valid = writeOnly_io_output_aw_valid; - assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; - assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; - assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; - assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; - assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; - assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; - assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; - assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; - assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; - assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; - assign io_output_w_valid = writeOnly_io_output_w_valid; - assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; - assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; - assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; - assign io_output_b_ready = writeOnly_io_output_b_ready; - -endmodule - -module Asic32To256UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output reg io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output reg [7:0] io_output_aw_payload_len, - output reg [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [255:0] io_output_w_payload_data, - output [31:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - input clk, - input reset -); - - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [4:0] _zz_cmdLogic_incrLen_2; - wire [5:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [31:0] _zz_dataLogic_byteActivity; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_aw_fork2_logic_linkEnable_0; - reg io_input_aw_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [5:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l21; - wire when_Axi4Upsizer_l24; - reg [4:0] dataLogic_byteCounter; - reg [2:0] dataLogic_size; - reg dataLogic_outputValid; - reg dataLogic_outputLast; - reg dataLogic_busy; - reg dataLogic_incrementByteCounter; - reg dataLogic_alwaysFire; - wire [5:0] dataLogic_byteCounterNext; - reg [255:0] dataLogic_dataBuffer; - reg [31:0] dataLogic_maskBuffer; - wire [31:0] dataLogic_byteActivity; - wire io_output_w_fire; - wire io_output_w_isStall; - wire io_input_w_fire; - wire when_Axi4Upsizer_l59; - wire when_Axi4Upsizer_l59_1; - wire when_Axi4Upsizer_l59_2; - wire when_Axi4Upsizer_l59_3; - wire when_Axi4Upsizer_l59_4; - wire when_Axi4Upsizer_l59_5; - wire when_Axi4Upsizer_l59_6; - wire when_Axi4Upsizer_l59_7; - wire when_Axi4Upsizer_l59_8; - wire when_Axi4Upsizer_l59_9; - wire when_Axi4Upsizer_l59_10; - wire when_Axi4Upsizer_l59_11; - wire when_Axi4Upsizer_l59_12; - wire when_Axi4Upsizer_l59_13; - wire when_Axi4Upsizer_l59_14; - wire when_Axi4Upsizer_l59_15; - wire when_Axi4Upsizer_l59_16; - wire when_Axi4Upsizer_l59_17; - wire when_Axi4Upsizer_l59_18; - wire when_Axi4Upsizer_l59_19; - wire when_Axi4Upsizer_l59_20; - wire when_Axi4Upsizer_l59_21; - wire when_Axi4Upsizer_l59_22; - wire when_Axi4Upsizer_l59_23; - wire when_Axi4Upsizer_l59_24; - wire when_Axi4Upsizer_l59_25; - wire when_Axi4Upsizer_l59_26; - wire when_Axi4Upsizer_l59_27; - wire when_Axi4Upsizer_l59_28; - wire when_Axi4Upsizer_l59_29; - wire when_Axi4Upsizer_l59_30; - wire when_Axi4Upsizer_l59_31; - wire cmdLogic_dataFork_fire_1; - wire when_Axi4Upsizer_l68; - wire when_Axi4Upsizer_l68_1; - wire when_Axi4Upsizer_l68_2; - wire when_Axi4Upsizer_l68_3; - wire when_Axi4Upsizer_l68_4; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[4 : 0]; - assign _zz_cmdLogic_incrLen_1 = {6'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[5:0]; - always @(*) begin - case(dataLogic_size) - 3'b000 : _zz_dataLogic_byteActivity = 32'h00000001; - 3'b001 : _zz_dataLogic_byteActivity = 32'h00000003; - 3'b010 : _zz_dataLogic_byteActivity = 32'h0000000f; - 3'b011 : _zz_dataLogic_byteActivity = 32'h000000ff; - default : _zz_dataLogic_byteActivity = 32'h0000ffff; - endcase - end - - always @(*) begin - io_input_aw_ready = 1'b1; - if(when_Stream_l993) begin - io_input_aw_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_aw_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_aw_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_aw_ready; - assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; - assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; - always @(*) begin - io_output_aw_payload_len = cmdLogic_outputFork_payload_len; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_len = {2'd0, cmdLogic_incrLen}; - end - end - - always @(*) begin - io_output_aw_payload_size = cmdLogic_outputFork_payload_size; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_size = 3'b101; - if(when_Axi4Upsizer_l24) begin - io_output_aw_payload_size = io_input_aw_payload_size; - end - end - end - - assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 5]; - assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); - assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); - assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); - assign io_output_w_valid = dataLogic_outputValid; - assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); - assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); - assign io_output_w_payload_data = dataLogic_dataBuffer; - assign io_output_w_payload_strb = dataLogic_maskBuffer; - assign io_output_w_payload_last = dataLogic_outputLast; - assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); - assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; - assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; - assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; - assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; - assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; - assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; - assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; - assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; - assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; - assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; - assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; - assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; - assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; - assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; - assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; - assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; - assign when_Axi4Upsizer_l59_16 = dataLogic_byteActivity[16]; - assign when_Axi4Upsizer_l59_17 = dataLogic_byteActivity[17]; - assign when_Axi4Upsizer_l59_18 = dataLogic_byteActivity[18]; - assign when_Axi4Upsizer_l59_19 = dataLogic_byteActivity[19]; - assign when_Axi4Upsizer_l59_20 = dataLogic_byteActivity[20]; - assign when_Axi4Upsizer_l59_21 = dataLogic_byteActivity[21]; - assign when_Axi4Upsizer_l59_22 = dataLogic_byteActivity[22]; - assign when_Axi4Upsizer_l59_23 = dataLogic_byteActivity[23]; - assign when_Axi4Upsizer_l59_24 = dataLogic_byteActivity[24]; - assign when_Axi4Upsizer_l59_25 = dataLogic_byteActivity[25]; - assign when_Axi4Upsizer_l59_26 = dataLogic_byteActivity[26]; - assign when_Axi4Upsizer_l59_27 = dataLogic_byteActivity[27]; - assign when_Axi4Upsizer_l59_28 = dataLogic_byteActivity[28]; - assign when_Axi4Upsizer_l59_29 = dataLogic_byteActivity[29]; - assign when_Axi4Upsizer_l59_30 = dataLogic_byteActivity[30]; - assign when_Axi4Upsizer_l59_31 = dataLogic_byteActivity[31]; - assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_4 = (3'b100 < cmdLogic_dataFork_payload_size); - assign cmdLogic_dataFork_ready = (! dataLogic_busy); - assign io_input_b_valid = io_output_b_valid; - assign io_output_b_ready = io_input_b_ready; - assign io_input_b_payload_id = io_output_b_payload_id; - assign io_input_b_payload_resp = io_output_b_payload_resp; - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_outputValid <= 1'b0; - dataLogic_busy <= 1'b0; - dataLogic_maskBuffer <= 32'h00000000; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_aw_ready) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - end - if(io_output_w_ready) begin - dataLogic_outputValid <= 1'b0; - end - if(io_output_w_fire) begin - dataLogic_maskBuffer <= 32'h00000000; - end - if(io_input_w_fire) begin - dataLogic_outputValid <= ((dataLogic_byteCounterNext[5] || io_input_w_payload_last) || dataLogic_alwaysFire); - if(io_input_w_payload_last) begin - dataLogic_busy <= 1'b0; - end - if(when_Axi4Upsizer_l59) begin - dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_8) begin - dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_9) begin - dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_10) begin - dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_11) begin - dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_12) begin - dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_13) begin - dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_14) begin - dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_15) begin - dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_16) begin - dataLogic_maskBuffer[16] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_17) begin - dataLogic_maskBuffer[17] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_18) begin - dataLogic_maskBuffer[18] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_19) begin - dataLogic_maskBuffer[19] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_20) begin - dataLogic_maskBuffer[20] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_21) begin - dataLogic_maskBuffer[21] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_22) begin - dataLogic_maskBuffer[22] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_23) begin - dataLogic_maskBuffer[23] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_24) begin - dataLogic_maskBuffer[24] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_25) begin - dataLogic_maskBuffer[25] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_26) begin - dataLogic_maskBuffer[26] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_27) begin - dataLogic_maskBuffer[27] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_28) begin - dataLogic_maskBuffer[28] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_29) begin - dataLogic_maskBuffer[29] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_30) begin - dataLogic_maskBuffer[30] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_31) begin - dataLogic_maskBuffer[31] <= io_input_w_payload_strb[3]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_busy <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(io_input_w_fire) begin - if(dataLogic_incrementByteCounter) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[4:0]; - end - dataLogic_outputLast <= io_input_w_payload_last; - if(when_Axi4Upsizer_l59) begin - dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_8) begin - dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_9) begin - dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_10) begin - dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_11) begin - dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_12) begin - dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_13) begin - dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_14) begin - dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_15) begin - dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_16) begin - dataLogic_dataBuffer[135 : 128] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_17) begin - dataLogic_dataBuffer[143 : 136] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_18) begin - dataLogic_dataBuffer[151 : 144] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_19) begin - dataLogic_dataBuffer[159 : 152] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_20) begin - dataLogic_dataBuffer[167 : 160] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_21) begin - dataLogic_dataBuffer[175 : 168] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_22) begin - dataLogic_dataBuffer[183 : 176] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_23) begin - dataLogic_dataBuffer[191 : 184] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_24) begin - dataLogic_dataBuffer[199 : 192] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_25) begin - dataLogic_dataBuffer[207 : 200] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_26) begin - dataLogic_dataBuffer[215 : 208] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_27) begin - dataLogic_dataBuffer[223 : 216] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_28) begin - dataLogic_dataBuffer[231 : 224] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_29) begin - dataLogic_dataBuffer[239 : 232] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_30) begin - dataLogic_dataBuffer[247 : 240] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_31) begin - dataLogic_dataBuffer[255 : 248] <= io_input_w_payload_data[31 : 24]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[4:0]; - if(when_Axi4Upsizer_l68) begin - dataLogic_byteCounter[0] <= 1'b0; - end - if(when_Axi4Upsizer_l68_1) begin - dataLogic_byteCounter[1] <= 1'b0; - end - if(when_Axi4Upsizer_l68_2) begin - dataLogic_byteCounter[2] <= 1'b0; - end - if(when_Axi4Upsizer_l68_3) begin - dataLogic_byteCounter[3] <= 1'b0; - end - if(when_Axi4Upsizer_l68_4) begin - dataLogic_byteCounter[4] <= 1'b0; - end - dataLogic_size <= cmdLogic_dataFork_payload_size; - dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); - dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); - end - end - - -endmodule - -module Asic32To256UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_ar_valid, - output reg io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output reg [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [255:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire dataLogic_cmdPush_fifo_io_pop_ready; - wire dataLogic_cmdPush_fifo_io_push_ready; - wire dataLogic_cmdPush_fifo_io_pop_valid; - wire [4:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; - wire [4:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; - wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; - wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; - wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; - wire [4:0] dataLogic_cmdPush_fifo_io_availability; - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [4:0] _zz_cmdLogic_incrLen_2; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; - wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; - wire [5:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [31:0] _zz_io_input_r_payload_data; - wire [2:0] _zz_io_input_r_payload_data_1; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_ar_fork2_logic_linkEnable_0; - reg io_input_ar_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [5:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l108; - wire dataLogic_cmdPush_valid; - wire dataLogic_cmdPush_ready; - wire [4:0] dataLogic_cmdPush_payload_startAt; - wire [4:0] dataLogic_cmdPush_payload_endAt; - wire [2:0] dataLogic_cmdPush_payload_size; - wire [7:0] dataLogic_cmdPush_payload_id; - reg [2:0] dataLogic_size; - reg dataLogic_busy; - reg [7:0] dataLogic_id; - reg [4:0] dataLogic_byteCounter; - reg [4:0] dataLogic_byteCounterLast; - wire [5:0] dataLogic_byteCounterNext; - wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; - wire io_input_r_fire; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[4 : 0]; - assign _zz_cmdLogic_incrLen_1 = {6'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); - assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); - assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[5:0]; - assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); - Asic32To256UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( - .io_push_valid (dataLogic_cmdPush_valid ), //i - .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o - .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[4:0] ), //i - .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[4:0] ), //i - .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i - .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i - .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o - .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i - .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[4:0]), //o - .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[4:0] ), //o - .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o - .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o - .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(_zz_io_input_r_payload_data_1) - 3'b000 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; - 3'b001 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; - 3'b010 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; - 3'b011 : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; - 3'b100 : _zz_io_input_r_payload_data = io_output_r_payload_data[159 : 128]; - 3'b101 : _zz_io_input_r_payload_data = io_output_r_payload_data[191 : 160]; - 3'b110 : _zz_io_input_r_payload_data = io_output_r_payload_data[223 : 192]; - default : _zz_io_input_r_payload_data = io_output_r_payload_data[255 : 224]; - endcase - end - - always @(*) begin - io_input_ar_ready = 1'b1; - if(when_Stream_l993) begin - io_input_ar_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_ar_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_ar_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_ar_ready; - assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; - assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 5]; - always @(*) begin - io_output_ar_payload_size = 3'b101; - if(when_Axi4Upsizer_l108) begin - io_output_ar_payload_size = io_input_ar_payload_size; - end - end - - assign io_output_ar_payload_len = {2'd0, cmdLogic_incrLen}; - assign io_output_ar_payload_id = 8'h00; - assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); - assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; - assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; - assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[4:0]; - assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[4:0]; - assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; - assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; - assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); - assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); - assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); - assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); - assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); - assign io_input_r_payload_resp = io_output_r_payload_resp; - assign io_input_r_payload_data = _zz_io_input_r_payload_data; - assign io_input_r_payload_id = dataLogic_id; - assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[5])); - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_busy <= 1'b0; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_ar_ready) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - end - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_busy <= 1'b1; - end - if(io_input_r_fire) begin - if(io_input_r_payload_last) begin - dataLogic_busy <= 1'b0; - end - end - end - end - - always @(posedge clk) begin - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; - dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; - dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; - dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; - end - if(io_input_r_fire) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[4:0]; - end - end - - -endmodule - -module Asic32To256UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_push_valid, - output io_push_ready, - input [4:0] io_push_payload_startAt, - input [4:0] io_push_payload_endAt, - input [2:0] io_push_payload_size, - input [7:0] io_push_payload_id, - output io_pop_valid, - input io_pop_ready, - output [4:0] io_pop_payload_startAt, - output [4:0] io_pop_payload_endAt, - output [2:0] io_pop_payload_size, - output [7:0] io_pop_payload_id, - input io_flush, - output [4:0] io_occupancy, - output [4:0] io_availability, - input clk, - input reset -); - - reg [20:0] _zz_logic_ram_port0; - wire [3:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [3:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz__zz_logic_ram_port0; - wire _zz__zz_io_pop_payload_startAt; - wire [20:0] _zz__zz_logic_ram_port1; - wire [3:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [3:0] logic_pushPtr_valueNext; - reg [3:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [3:0] logic_popPtr_valueNext; - reg [3:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [20:0] _zz_io_pop_payload_startAt; - wire when_Stream_l1123; - wire [3:0] logic_ptrDif; - reg [20:0] logic_ram [0:15]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_startAt = 1'b1; - assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; - always @(posedge clk) begin - if(_zz__zz_io_pop_payload_startAt) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 4'b0000; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 4'b0000; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; - assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[4 : 0]; - assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[9 : 5]; - assign io_pop_payload_size = _zz_io_pop_payload_startAt[12 : 10]; - assign io_pop_payload_id = _zz_io_pop_payload_startAt[20 : 13]; - assign when_Stream_l1123 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge clk or posedge reset) begin - if(reset) begin - logic_pushPtr_value <= 4'b0000; - logic_popPtr_value <= 4'b0000; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1123) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - - -// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 -// Component : Asic32To512UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 -// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a - -`timescale 1ns/1ps - -module Asic32To512UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - input io_input_ar_valid, - output io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output [7:0] io_output_aw_payload_len, - output [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [511:0] io_output_w_payload_data, - output [63:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [511:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire readOnly_io_input_ar_ready; - wire readOnly_io_input_r_valid; - wire [31:0] readOnly_io_input_r_payload_data; - wire [7:0] readOnly_io_input_r_payload_id; - wire [1:0] readOnly_io_input_r_payload_resp; - wire readOnly_io_input_r_payload_last; - wire readOnly_io_output_ar_valid; - wire [31:0] readOnly_io_output_ar_payload_addr; - wire [7:0] readOnly_io_output_ar_payload_id; - wire [3:0] readOnly_io_output_ar_payload_region; - wire [7:0] readOnly_io_output_ar_payload_len; - wire [2:0] readOnly_io_output_ar_payload_size; - wire [1:0] readOnly_io_output_ar_payload_burst; - wire [0:0] readOnly_io_output_ar_payload_lock; - wire [3:0] readOnly_io_output_ar_payload_cache; - wire [3:0] readOnly_io_output_ar_payload_qos; - wire [2:0] readOnly_io_output_ar_payload_prot; - wire readOnly_io_output_r_ready; - wire writeOnly_io_input_aw_ready; - wire writeOnly_io_input_w_ready; - wire writeOnly_io_input_b_valid; - wire [7:0] writeOnly_io_input_b_payload_id; - wire [1:0] writeOnly_io_input_b_payload_resp; - wire writeOnly_io_output_aw_valid; - wire [31:0] writeOnly_io_output_aw_payload_addr; - wire [7:0] writeOnly_io_output_aw_payload_id; - wire [3:0] writeOnly_io_output_aw_payload_region; - wire [7:0] writeOnly_io_output_aw_payload_len; - wire [2:0] writeOnly_io_output_aw_payload_size; - wire [1:0] writeOnly_io_output_aw_payload_burst; - wire [0:0] writeOnly_io_output_aw_payload_lock; - wire [3:0] writeOnly_io_output_aw_payload_cache; - wire [3:0] writeOnly_io_output_aw_payload_qos; - wire [2:0] writeOnly_io_output_aw_payload_prot; - wire writeOnly_io_output_w_valid; - wire [511:0] writeOnly_io_output_w_payload_data; - wire [63:0] writeOnly_io_output_w_payload_strb; - wire writeOnly_io_output_w_payload_last; - wire writeOnly_io_output_b_ready; - - Asic32To512UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( - .io_input_ar_valid (io_input_ar_valid ), //i - .io_input_ar_ready (readOnly_io_input_ar_ready ), //o - .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i - .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i - .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i - .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i - .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i - .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i - .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i - .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i - .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i - .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i - .io_input_r_valid (readOnly_io_input_r_valid ), //o - .io_input_r_ready (io_input_r_ready ), //i - .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o - .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o - .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o - .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o - .io_output_ar_valid (readOnly_io_output_ar_valid ), //o - .io_output_ar_ready (io_output_ar_ready ), //i - .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o - .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o - .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o - .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o - .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o - .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o - .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o - .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o - .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o - .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o - .io_output_r_valid (io_output_r_valid ), //i - .io_output_r_ready (readOnly_io_output_r_ready ), //o - .io_output_r_payload_data (io_output_r_payload_data[511:0] ), //i - .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i - .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i - .io_output_r_payload_last (io_output_r_payload_last ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Asic32To512UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( - .io_input_aw_valid (io_input_aw_valid ), //i - .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o - .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i - .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i - .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i - .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i - .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i - .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i - .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i - .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i - .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i - .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i - .io_input_w_valid (io_input_w_valid ), //i - .io_input_w_ready (writeOnly_io_input_w_ready ), //o - .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i - .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i - .io_input_w_payload_last (io_input_w_payload_last ), //i - .io_input_b_valid (writeOnly_io_input_b_valid ), //o - .io_input_b_ready (io_input_b_ready ), //i - .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o - .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o - .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o - .io_output_aw_ready (io_output_aw_ready ), //i - .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o - .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o - .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o - .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o - .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o - .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o - .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o - .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o - .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o - .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o - .io_output_w_valid (writeOnly_io_output_w_valid ), //o - .io_output_w_ready (io_output_w_ready ), //i - .io_output_w_payload_data (writeOnly_io_output_w_payload_data[511:0] ), //o - .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[63:0] ), //o - .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o - .io_output_b_valid (io_output_b_valid ), //i - .io_output_b_ready (writeOnly_io_output_b_ready ), //o - .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i - .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_ar_ready = readOnly_io_input_ar_ready; - assign io_input_r_valid = readOnly_io_input_r_valid; - assign io_input_r_payload_data = readOnly_io_input_r_payload_data; - assign io_input_r_payload_id = readOnly_io_input_r_payload_id; - assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; - assign io_input_r_payload_last = readOnly_io_input_r_payload_last; - assign io_input_aw_ready = writeOnly_io_input_aw_ready; - assign io_input_w_ready = writeOnly_io_input_w_ready; - assign io_input_b_valid = writeOnly_io_input_b_valid; - assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; - assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; - assign io_output_ar_valid = readOnly_io_output_ar_valid; - assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; - assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; - assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; - assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; - assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; - assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; - assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; - assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; - assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; - assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; - assign io_output_r_ready = readOnly_io_output_r_ready; - assign io_output_aw_valid = writeOnly_io_output_aw_valid; - assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; - assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; - assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; - assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; - assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; - assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; - assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; - assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; - assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; - assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; - assign io_output_w_valid = writeOnly_io_output_w_valid; - assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; - assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; - assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; - assign io_output_b_ready = writeOnly_io_output_b_ready; - -endmodule - -module Asic32To512UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output reg io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output reg [7:0] io_output_aw_payload_len, - output reg [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [511:0] io_output_w_payload_data, - output [63:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - input clk, - input reset -); - - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [5:0] _zz_cmdLogic_incrLen_2; - wire [6:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [63:0] _zz_dataLogic_byteActivity; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_aw_fork2_logic_linkEnable_0; - reg io_input_aw_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [4:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l21; - wire when_Axi4Upsizer_l24; - reg [5:0] dataLogic_byteCounter; - reg [2:0] dataLogic_size; - reg dataLogic_outputValid; - reg dataLogic_outputLast; - reg dataLogic_busy; - reg dataLogic_incrementByteCounter; - reg dataLogic_alwaysFire; - wire [6:0] dataLogic_byteCounterNext; - reg [511:0] dataLogic_dataBuffer; - reg [63:0] dataLogic_maskBuffer; - wire [63:0] dataLogic_byteActivity; - wire io_output_w_fire; - wire io_output_w_isStall; - wire io_input_w_fire; - wire when_Axi4Upsizer_l59; - wire when_Axi4Upsizer_l59_1; - wire when_Axi4Upsizer_l59_2; - wire when_Axi4Upsizer_l59_3; - wire when_Axi4Upsizer_l59_4; - wire when_Axi4Upsizer_l59_5; - wire when_Axi4Upsizer_l59_6; - wire when_Axi4Upsizer_l59_7; - wire when_Axi4Upsizer_l59_8; - wire when_Axi4Upsizer_l59_9; - wire when_Axi4Upsizer_l59_10; - wire when_Axi4Upsizer_l59_11; - wire when_Axi4Upsizer_l59_12; - wire when_Axi4Upsizer_l59_13; - wire when_Axi4Upsizer_l59_14; - wire when_Axi4Upsizer_l59_15; - wire when_Axi4Upsizer_l59_16; - wire when_Axi4Upsizer_l59_17; - wire when_Axi4Upsizer_l59_18; - wire when_Axi4Upsizer_l59_19; - wire when_Axi4Upsizer_l59_20; - wire when_Axi4Upsizer_l59_21; - wire when_Axi4Upsizer_l59_22; - wire when_Axi4Upsizer_l59_23; - wire when_Axi4Upsizer_l59_24; - wire when_Axi4Upsizer_l59_25; - wire when_Axi4Upsizer_l59_26; - wire when_Axi4Upsizer_l59_27; - wire when_Axi4Upsizer_l59_28; - wire when_Axi4Upsizer_l59_29; - wire when_Axi4Upsizer_l59_30; - wire when_Axi4Upsizer_l59_31; - wire when_Axi4Upsizer_l59_32; - wire when_Axi4Upsizer_l59_33; - wire when_Axi4Upsizer_l59_34; - wire when_Axi4Upsizer_l59_35; - wire when_Axi4Upsizer_l59_36; - wire when_Axi4Upsizer_l59_37; - wire when_Axi4Upsizer_l59_38; - wire when_Axi4Upsizer_l59_39; - wire when_Axi4Upsizer_l59_40; - wire when_Axi4Upsizer_l59_41; - wire when_Axi4Upsizer_l59_42; - wire when_Axi4Upsizer_l59_43; - wire when_Axi4Upsizer_l59_44; - wire when_Axi4Upsizer_l59_45; - wire when_Axi4Upsizer_l59_46; - wire when_Axi4Upsizer_l59_47; - wire when_Axi4Upsizer_l59_48; - wire when_Axi4Upsizer_l59_49; - wire when_Axi4Upsizer_l59_50; - wire when_Axi4Upsizer_l59_51; - wire when_Axi4Upsizer_l59_52; - wire when_Axi4Upsizer_l59_53; - wire when_Axi4Upsizer_l59_54; - wire when_Axi4Upsizer_l59_55; - wire when_Axi4Upsizer_l59_56; - wire when_Axi4Upsizer_l59_57; - wire when_Axi4Upsizer_l59_58; - wire when_Axi4Upsizer_l59_59; - wire when_Axi4Upsizer_l59_60; - wire when_Axi4Upsizer_l59_61; - wire when_Axi4Upsizer_l59_62; - wire when_Axi4Upsizer_l59_63; - wire cmdLogic_dataFork_fire_1; - wire when_Axi4Upsizer_l68; - wire when_Axi4Upsizer_l68_1; - wire when_Axi4Upsizer_l68_2; - wire when_Axi4Upsizer_l68_3; - wire when_Axi4Upsizer_l68_4; - wire when_Axi4Upsizer_l68_5; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[5 : 0]; - assign _zz_cmdLogic_incrLen_1 = {5'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[6:0]; - always @(*) begin - case(dataLogic_size) - 3'b000 : _zz_dataLogic_byteActivity = 64'h0000000000000001; - 3'b001 : _zz_dataLogic_byteActivity = 64'h0000000000000003; - 3'b010 : _zz_dataLogic_byteActivity = 64'h000000000000000f; - 3'b011 : _zz_dataLogic_byteActivity = 64'h00000000000000ff; - 3'b100 : _zz_dataLogic_byteActivity = 64'h000000000000ffff; - default : _zz_dataLogic_byteActivity = 64'h00000000ffffffff; - endcase - end - - always @(*) begin - io_input_aw_ready = 1'b1; - if(when_Stream_l993) begin - io_input_aw_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_aw_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_aw_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_aw_ready; - assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; - assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; - always @(*) begin - io_output_aw_payload_len = cmdLogic_outputFork_payload_len; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_len = {3'd0, cmdLogic_incrLen}; - end - end - - always @(*) begin - io_output_aw_payload_size = cmdLogic_outputFork_payload_size; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_size = 3'b110; - if(when_Axi4Upsizer_l24) begin - io_output_aw_payload_size = io_input_aw_payload_size; - end - end - end - - assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 6]; - assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); - assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); - assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); - assign io_output_w_valid = dataLogic_outputValid; - assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); - assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); - assign io_output_w_payload_data = dataLogic_dataBuffer; - assign io_output_w_payload_strb = dataLogic_maskBuffer; - assign io_output_w_payload_last = dataLogic_outputLast; - assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); - assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; - assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; - assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; - assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; - assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; - assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; - assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; - assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; - assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; - assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; - assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; - assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; - assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; - assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; - assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; - assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; - assign when_Axi4Upsizer_l59_16 = dataLogic_byteActivity[16]; - assign when_Axi4Upsizer_l59_17 = dataLogic_byteActivity[17]; - assign when_Axi4Upsizer_l59_18 = dataLogic_byteActivity[18]; - assign when_Axi4Upsizer_l59_19 = dataLogic_byteActivity[19]; - assign when_Axi4Upsizer_l59_20 = dataLogic_byteActivity[20]; - assign when_Axi4Upsizer_l59_21 = dataLogic_byteActivity[21]; - assign when_Axi4Upsizer_l59_22 = dataLogic_byteActivity[22]; - assign when_Axi4Upsizer_l59_23 = dataLogic_byteActivity[23]; - assign when_Axi4Upsizer_l59_24 = dataLogic_byteActivity[24]; - assign when_Axi4Upsizer_l59_25 = dataLogic_byteActivity[25]; - assign when_Axi4Upsizer_l59_26 = dataLogic_byteActivity[26]; - assign when_Axi4Upsizer_l59_27 = dataLogic_byteActivity[27]; - assign when_Axi4Upsizer_l59_28 = dataLogic_byteActivity[28]; - assign when_Axi4Upsizer_l59_29 = dataLogic_byteActivity[29]; - assign when_Axi4Upsizer_l59_30 = dataLogic_byteActivity[30]; - assign when_Axi4Upsizer_l59_31 = dataLogic_byteActivity[31]; - assign when_Axi4Upsizer_l59_32 = dataLogic_byteActivity[32]; - assign when_Axi4Upsizer_l59_33 = dataLogic_byteActivity[33]; - assign when_Axi4Upsizer_l59_34 = dataLogic_byteActivity[34]; - assign when_Axi4Upsizer_l59_35 = dataLogic_byteActivity[35]; - assign when_Axi4Upsizer_l59_36 = dataLogic_byteActivity[36]; - assign when_Axi4Upsizer_l59_37 = dataLogic_byteActivity[37]; - assign when_Axi4Upsizer_l59_38 = dataLogic_byteActivity[38]; - assign when_Axi4Upsizer_l59_39 = dataLogic_byteActivity[39]; - assign when_Axi4Upsizer_l59_40 = dataLogic_byteActivity[40]; - assign when_Axi4Upsizer_l59_41 = dataLogic_byteActivity[41]; - assign when_Axi4Upsizer_l59_42 = dataLogic_byteActivity[42]; - assign when_Axi4Upsizer_l59_43 = dataLogic_byteActivity[43]; - assign when_Axi4Upsizer_l59_44 = dataLogic_byteActivity[44]; - assign when_Axi4Upsizer_l59_45 = dataLogic_byteActivity[45]; - assign when_Axi4Upsizer_l59_46 = dataLogic_byteActivity[46]; - assign when_Axi4Upsizer_l59_47 = dataLogic_byteActivity[47]; - assign when_Axi4Upsizer_l59_48 = dataLogic_byteActivity[48]; - assign when_Axi4Upsizer_l59_49 = dataLogic_byteActivity[49]; - assign when_Axi4Upsizer_l59_50 = dataLogic_byteActivity[50]; - assign when_Axi4Upsizer_l59_51 = dataLogic_byteActivity[51]; - assign when_Axi4Upsizer_l59_52 = dataLogic_byteActivity[52]; - assign when_Axi4Upsizer_l59_53 = dataLogic_byteActivity[53]; - assign when_Axi4Upsizer_l59_54 = dataLogic_byteActivity[54]; - assign when_Axi4Upsizer_l59_55 = dataLogic_byteActivity[55]; - assign when_Axi4Upsizer_l59_56 = dataLogic_byteActivity[56]; - assign when_Axi4Upsizer_l59_57 = dataLogic_byteActivity[57]; - assign when_Axi4Upsizer_l59_58 = dataLogic_byteActivity[58]; - assign when_Axi4Upsizer_l59_59 = dataLogic_byteActivity[59]; - assign when_Axi4Upsizer_l59_60 = dataLogic_byteActivity[60]; - assign when_Axi4Upsizer_l59_61 = dataLogic_byteActivity[61]; - assign when_Axi4Upsizer_l59_62 = dataLogic_byteActivity[62]; - assign when_Axi4Upsizer_l59_63 = dataLogic_byteActivity[63]; - assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_4 = (3'b100 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_5 = (3'b101 < cmdLogic_dataFork_payload_size); - assign cmdLogic_dataFork_ready = (! dataLogic_busy); - assign io_input_b_valid = io_output_b_valid; - assign io_output_b_ready = io_input_b_ready; - assign io_input_b_payload_id = io_output_b_payload_id; - assign io_input_b_payload_resp = io_output_b_payload_resp; - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_outputValid <= 1'b0; - dataLogic_busy <= 1'b0; - dataLogic_maskBuffer <= 64'h0000000000000000; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_aw_ready) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - end - if(io_output_w_ready) begin - dataLogic_outputValid <= 1'b0; - end - if(io_output_w_fire) begin - dataLogic_maskBuffer <= 64'h0000000000000000; - end - if(io_input_w_fire) begin - dataLogic_outputValid <= ((dataLogic_byteCounterNext[6] || io_input_w_payload_last) || dataLogic_alwaysFire); - if(io_input_w_payload_last) begin - dataLogic_busy <= 1'b0; - end - if(when_Axi4Upsizer_l59) begin - dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_8) begin - dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_9) begin - dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_10) begin - dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_11) begin - dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_12) begin - dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_13) begin - dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_14) begin - dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_15) begin - dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_16) begin - dataLogic_maskBuffer[16] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_17) begin - dataLogic_maskBuffer[17] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_18) begin - dataLogic_maskBuffer[18] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_19) begin - dataLogic_maskBuffer[19] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_20) begin - dataLogic_maskBuffer[20] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_21) begin - dataLogic_maskBuffer[21] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_22) begin - dataLogic_maskBuffer[22] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_23) begin - dataLogic_maskBuffer[23] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_24) begin - dataLogic_maskBuffer[24] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_25) begin - dataLogic_maskBuffer[25] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_26) begin - dataLogic_maskBuffer[26] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_27) begin - dataLogic_maskBuffer[27] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_28) begin - dataLogic_maskBuffer[28] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_29) begin - dataLogic_maskBuffer[29] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_30) begin - dataLogic_maskBuffer[30] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_31) begin - dataLogic_maskBuffer[31] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_32) begin - dataLogic_maskBuffer[32] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_33) begin - dataLogic_maskBuffer[33] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_34) begin - dataLogic_maskBuffer[34] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_35) begin - dataLogic_maskBuffer[35] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_36) begin - dataLogic_maskBuffer[36] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_37) begin - dataLogic_maskBuffer[37] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_38) begin - dataLogic_maskBuffer[38] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_39) begin - dataLogic_maskBuffer[39] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_40) begin - dataLogic_maskBuffer[40] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_41) begin - dataLogic_maskBuffer[41] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_42) begin - dataLogic_maskBuffer[42] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_43) begin - dataLogic_maskBuffer[43] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_44) begin - dataLogic_maskBuffer[44] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_45) begin - dataLogic_maskBuffer[45] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_46) begin - dataLogic_maskBuffer[46] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_47) begin - dataLogic_maskBuffer[47] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_48) begin - dataLogic_maskBuffer[48] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_49) begin - dataLogic_maskBuffer[49] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_50) begin - dataLogic_maskBuffer[50] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_51) begin - dataLogic_maskBuffer[51] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_52) begin - dataLogic_maskBuffer[52] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_53) begin - dataLogic_maskBuffer[53] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_54) begin - dataLogic_maskBuffer[54] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_55) begin - dataLogic_maskBuffer[55] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_56) begin - dataLogic_maskBuffer[56] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_57) begin - dataLogic_maskBuffer[57] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_58) begin - dataLogic_maskBuffer[58] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_59) begin - dataLogic_maskBuffer[59] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_60) begin - dataLogic_maskBuffer[60] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_61) begin - dataLogic_maskBuffer[61] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_62) begin - dataLogic_maskBuffer[62] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_63) begin - dataLogic_maskBuffer[63] <= io_input_w_payload_strb[3]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_busy <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(io_input_w_fire) begin - if(dataLogic_incrementByteCounter) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[5:0]; - end - dataLogic_outputLast <= io_input_w_payload_last; - if(when_Axi4Upsizer_l59) begin - dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_8) begin - dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_9) begin - dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_10) begin - dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_11) begin - dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_12) begin - dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_13) begin - dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_14) begin - dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_15) begin - dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_16) begin - dataLogic_dataBuffer[135 : 128] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_17) begin - dataLogic_dataBuffer[143 : 136] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_18) begin - dataLogic_dataBuffer[151 : 144] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_19) begin - dataLogic_dataBuffer[159 : 152] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_20) begin - dataLogic_dataBuffer[167 : 160] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_21) begin - dataLogic_dataBuffer[175 : 168] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_22) begin - dataLogic_dataBuffer[183 : 176] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_23) begin - dataLogic_dataBuffer[191 : 184] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_24) begin - dataLogic_dataBuffer[199 : 192] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_25) begin - dataLogic_dataBuffer[207 : 200] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_26) begin - dataLogic_dataBuffer[215 : 208] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_27) begin - dataLogic_dataBuffer[223 : 216] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_28) begin - dataLogic_dataBuffer[231 : 224] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_29) begin - dataLogic_dataBuffer[239 : 232] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_30) begin - dataLogic_dataBuffer[247 : 240] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_31) begin - dataLogic_dataBuffer[255 : 248] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_32) begin - dataLogic_dataBuffer[263 : 256] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_33) begin - dataLogic_dataBuffer[271 : 264] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_34) begin - dataLogic_dataBuffer[279 : 272] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_35) begin - dataLogic_dataBuffer[287 : 280] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_36) begin - dataLogic_dataBuffer[295 : 288] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_37) begin - dataLogic_dataBuffer[303 : 296] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_38) begin - dataLogic_dataBuffer[311 : 304] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_39) begin - dataLogic_dataBuffer[319 : 312] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_40) begin - dataLogic_dataBuffer[327 : 320] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_41) begin - dataLogic_dataBuffer[335 : 328] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_42) begin - dataLogic_dataBuffer[343 : 336] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_43) begin - dataLogic_dataBuffer[351 : 344] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_44) begin - dataLogic_dataBuffer[359 : 352] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_45) begin - dataLogic_dataBuffer[367 : 360] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_46) begin - dataLogic_dataBuffer[375 : 368] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_47) begin - dataLogic_dataBuffer[383 : 376] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_48) begin - dataLogic_dataBuffer[391 : 384] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_49) begin - dataLogic_dataBuffer[399 : 392] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_50) begin - dataLogic_dataBuffer[407 : 400] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_51) begin - dataLogic_dataBuffer[415 : 408] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_52) begin - dataLogic_dataBuffer[423 : 416] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_53) begin - dataLogic_dataBuffer[431 : 424] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_54) begin - dataLogic_dataBuffer[439 : 432] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_55) begin - dataLogic_dataBuffer[447 : 440] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_56) begin - dataLogic_dataBuffer[455 : 448] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_57) begin - dataLogic_dataBuffer[463 : 456] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_58) begin - dataLogic_dataBuffer[471 : 464] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_59) begin - dataLogic_dataBuffer[479 : 472] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_60) begin - dataLogic_dataBuffer[487 : 480] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_61) begin - dataLogic_dataBuffer[495 : 488] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_62) begin - dataLogic_dataBuffer[503 : 496] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_63) begin - dataLogic_dataBuffer[511 : 504] <= io_input_w_payload_data[31 : 24]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[5:0]; - if(when_Axi4Upsizer_l68) begin - dataLogic_byteCounter[0] <= 1'b0; - end - if(when_Axi4Upsizer_l68_1) begin - dataLogic_byteCounter[1] <= 1'b0; - end - if(when_Axi4Upsizer_l68_2) begin - dataLogic_byteCounter[2] <= 1'b0; - end - if(when_Axi4Upsizer_l68_3) begin - dataLogic_byteCounter[3] <= 1'b0; - end - if(when_Axi4Upsizer_l68_4) begin - dataLogic_byteCounter[4] <= 1'b0; - end - if(when_Axi4Upsizer_l68_5) begin - dataLogic_byteCounter[5] <= 1'b0; - end - dataLogic_size <= cmdLogic_dataFork_payload_size; - dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); - dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); - end - end - - -endmodule - -module Asic32To512UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_ar_valid, - output reg io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output reg [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [511:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire dataLogic_cmdPush_fifo_io_pop_ready; - wire dataLogic_cmdPush_fifo_io_push_ready; - wire dataLogic_cmdPush_fifo_io_pop_valid; - wire [5:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; - wire [5:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; - wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; - wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; - wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; - wire [4:0] dataLogic_cmdPush_fifo_io_availability; - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [5:0] _zz_cmdLogic_incrLen_2; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; - wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; - wire [6:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [31:0] _zz_io_input_r_payload_data; - wire [3:0] _zz_io_input_r_payload_data_1; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_ar_fork2_logic_linkEnable_0; - reg io_input_ar_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [4:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l108; - wire dataLogic_cmdPush_valid; - wire dataLogic_cmdPush_ready; - wire [5:0] dataLogic_cmdPush_payload_startAt; - wire [5:0] dataLogic_cmdPush_payload_endAt; - wire [2:0] dataLogic_cmdPush_payload_size; - wire [7:0] dataLogic_cmdPush_payload_id; - reg [2:0] dataLogic_size; - reg dataLogic_busy; - reg [7:0] dataLogic_id; - reg [5:0] dataLogic_byteCounter; - reg [5:0] dataLogic_byteCounterLast; - wire [6:0] dataLogic_byteCounterNext; - wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; - wire io_input_r_fire; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[5 : 0]; - assign _zz_cmdLogic_incrLen_1 = {5'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); - assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); - assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[6:0]; - assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); - Asic32To512UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( - .io_push_valid (dataLogic_cmdPush_valid ), //i - .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o - .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[5:0] ), //i - .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[5:0] ), //i - .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i - .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i - .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o - .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i - .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[5:0]), //o - .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[5:0] ), //o - .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o - .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o - .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(_zz_io_input_r_payload_data_1) - 4'b0000 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; - 4'b0001 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; - 4'b0010 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; - 4'b0011 : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; - 4'b0100 : _zz_io_input_r_payload_data = io_output_r_payload_data[159 : 128]; - 4'b0101 : _zz_io_input_r_payload_data = io_output_r_payload_data[191 : 160]; - 4'b0110 : _zz_io_input_r_payload_data = io_output_r_payload_data[223 : 192]; - 4'b0111 : _zz_io_input_r_payload_data = io_output_r_payload_data[255 : 224]; - 4'b1000 : _zz_io_input_r_payload_data = io_output_r_payload_data[287 : 256]; - 4'b1001 : _zz_io_input_r_payload_data = io_output_r_payload_data[319 : 288]; - 4'b1010 : _zz_io_input_r_payload_data = io_output_r_payload_data[351 : 320]; - 4'b1011 : _zz_io_input_r_payload_data = io_output_r_payload_data[383 : 352]; - 4'b1100 : _zz_io_input_r_payload_data = io_output_r_payload_data[415 : 384]; - 4'b1101 : _zz_io_input_r_payload_data = io_output_r_payload_data[447 : 416]; - 4'b1110 : _zz_io_input_r_payload_data = io_output_r_payload_data[479 : 448]; - default : _zz_io_input_r_payload_data = io_output_r_payload_data[511 : 480]; - endcase - end - - always @(*) begin - io_input_ar_ready = 1'b1; - if(when_Stream_l993) begin - io_input_ar_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_ar_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_ar_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_ar_ready; - assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; - assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 6]; - always @(*) begin - io_output_ar_payload_size = 3'b110; - if(when_Axi4Upsizer_l108) begin - io_output_ar_payload_size = io_input_ar_payload_size; - end - end - - assign io_output_ar_payload_len = {3'd0, cmdLogic_incrLen}; - assign io_output_ar_payload_id = 8'h00; - assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); - assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; - assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; - assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[5:0]; - assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[5:0]; - assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; - assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; - assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); - assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); - assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); - assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); - assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); - assign io_input_r_payload_resp = io_output_r_payload_resp; - assign io_input_r_payload_data = _zz_io_input_r_payload_data; - assign io_input_r_payload_id = dataLogic_id; - assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[6])); - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_busy <= 1'b0; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_ar_ready) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - end - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_busy <= 1'b1; - end - if(io_input_r_fire) begin - if(io_input_r_payload_last) begin - dataLogic_busy <= 1'b0; - end - end - end - end - - always @(posedge clk) begin - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; - dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; - dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; - dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; - end - if(io_input_r_fire) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[5:0]; - end - end - - -endmodule - -module Asic32To512UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_push_valid, - output io_push_ready, - input [5:0] io_push_payload_startAt, - input [5:0] io_push_payload_endAt, - input [2:0] io_push_payload_size, - input [7:0] io_push_payload_id, - output io_pop_valid, - input io_pop_ready, - output [5:0] io_pop_payload_startAt, - output [5:0] io_pop_payload_endAt, - output [2:0] io_pop_payload_size, - output [7:0] io_pop_payload_id, - input io_flush, - output [4:0] io_occupancy, - output [4:0] io_availability, - input clk, - input reset -); - - reg [22:0] _zz_logic_ram_port0; - wire [3:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [3:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz__zz_logic_ram_port0; - wire _zz__zz_io_pop_payload_startAt; - wire [22:0] _zz__zz_logic_ram_port1; - wire [3:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [3:0] logic_pushPtr_valueNext; - reg [3:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [3:0] logic_popPtr_valueNext; - reg [3:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [22:0] _zz_io_pop_payload_startAt; - wire when_Stream_l1123; - wire [3:0] logic_ptrDif; - reg [22:0] logic_ram [0:15]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_startAt = 1'b1; - assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; - always @(posedge clk) begin - if(_zz__zz_io_pop_payload_startAt) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 4'b0000; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 4'b0000; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; - assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[5 : 0]; - assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[11 : 6]; - assign io_pop_payload_size = _zz_io_pop_payload_startAt[14 : 12]; - assign io_pop_payload_id = _zz_io_pop_payload_startAt[22 : 15]; - assign when_Stream_l1123 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge clk or posedge reset) begin - if(reset) begin - logic_pushPtr_value <= 4'b0000; - logic_popPtr_value <= 4'b0000; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1123) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - - -// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 -// Component : Asic32To64UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 -// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a - -`timescale 1ns/1ps - -module Asic32To64UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - input io_input_ar_valid, - output io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output [7:0] io_output_aw_payload_len, - output [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [63:0] io_output_w_payload_data, - output [7:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [63:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire readOnly_io_input_ar_ready; - wire readOnly_io_input_r_valid; - wire [31:0] readOnly_io_input_r_payload_data; - wire [7:0] readOnly_io_input_r_payload_id; - wire [1:0] readOnly_io_input_r_payload_resp; - wire readOnly_io_input_r_payload_last; - wire readOnly_io_output_ar_valid; - wire [31:0] readOnly_io_output_ar_payload_addr; - wire [7:0] readOnly_io_output_ar_payload_id; - wire [3:0] readOnly_io_output_ar_payload_region; - wire [7:0] readOnly_io_output_ar_payload_len; - wire [2:0] readOnly_io_output_ar_payload_size; - wire [1:0] readOnly_io_output_ar_payload_burst; - wire [0:0] readOnly_io_output_ar_payload_lock; - wire [3:0] readOnly_io_output_ar_payload_cache; - wire [3:0] readOnly_io_output_ar_payload_qos; - wire [2:0] readOnly_io_output_ar_payload_prot; - wire readOnly_io_output_r_ready; - wire writeOnly_io_input_aw_ready; - wire writeOnly_io_input_w_ready; - wire writeOnly_io_input_b_valid; - wire [7:0] writeOnly_io_input_b_payload_id; - wire [1:0] writeOnly_io_input_b_payload_resp; - wire writeOnly_io_output_aw_valid; - wire [31:0] writeOnly_io_output_aw_payload_addr; - wire [7:0] writeOnly_io_output_aw_payload_id; - wire [3:0] writeOnly_io_output_aw_payload_region; - wire [7:0] writeOnly_io_output_aw_payload_len; - wire [2:0] writeOnly_io_output_aw_payload_size; - wire [1:0] writeOnly_io_output_aw_payload_burst; - wire [0:0] writeOnly_io_output_aw_payload_lock; - wire [3:0] writeOnly_io_output_aw_payload_cache; - wire [3:0] writeOnly_io_output_aw_payload_qos; - wire [2:0] writeOnly_io_output_aw_payload_prot; - wire writeOnly_io_output_w_valid; - wire [63:0] writeOnly_io_output_w_payload_data; - wire [7:0] writeOnly_io_output_w_payload_strb; - wire writeOnly_io_output_w_payload_last; - wire writeOnly_io_output_b_ready; - - Asic32To64UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( - .io_input_ar_valid (io_input_ar_valid ), //i - .io_input_ar_ready (readOnly_io_input_ar_ready ), //o - .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i - .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i - .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i - .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i - .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i - .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i - .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i - .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i - .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i - .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i - .io_input_r_valid (readOnly_io_input_r_valid ), //o - .io_input_r_ready (io_input_r_ready ), //i - .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o - .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o - .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o - .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o - .io_output_ar_valid (readOnly_io_output_ar_valid ), //o - .io_output_ar_ready (io_output_ar_ready ), //i - .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o - .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o - .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o - .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o - .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o - .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o - .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o - .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o - .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o - .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o - .io_output_r_valid (io_output_r_valid ), //i - .io_output_r_ready (readOnly_io_output_r_ready ), //o - .io_output_r_payload_data (io_output_r_payload_data[63:0] ), //i - .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i - .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i - .io_output_r_payload_last (io_output_r_payload_last ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - Asic32To64UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( - .io_input_aw_valid (io_input_aw_valid ), //i - .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o - .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i - .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i - .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i - .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i - .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i - .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i - .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i - .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i - .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i - .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i - .io_input_w_valid (io_input_w_valid ), //i - .io_input_w_ready (writeOnly_io_input_w_ready ), //o - .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i - .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i - .io_input_w_payload_last (io_input_w_payload_last ), //i - .io_input_b_valid (writeOnly_io_input_b_valid ), //o - .io_input_b_ready (io_input_b_ready ), //i - .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o - .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o - .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o - .io_output_aw_ready (io_output_aw_ready ), //i - .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o - .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o - .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o - .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o - .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o - .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o - .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o - .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o - .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o - .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o - .io_output_w_valid (writeOnly_io_output_w_valid ), //o - .io_output_w_ready (io_output_w_ready ), //i - .io_output_w_payload_data (writeOnly_io_output_w_payload_data[63:0] ), //o - .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[7:0] ), //o - .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o - .io_output_b_valid (io_output_b_valid ), //i - .io_output_b_ready (writeOnly_io_output_b_ready ), //o - .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i - .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i - .clk (clk ), //i - .reset (reset ) //i - ); - assign io_input_ar_ready = readOnly_io_input_ar_ready; - assign io_input_r_valid = readOnly_io_input_r_valid; - assign io_input_r_payload_data = readOnly_io_input_r_payload_data; - assign io_input_r_payload_id = readOnly_io_input_r_payload_id; - assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; - assign io_input_r_payload_last = readOnly_io_input_r_payload_last; - assign io_input_aw_ready = writeOnly_io_input_aw_ready; - assign io_input_w_ready = writeOnly_io_input_w_ready; - assign io_input_b_valid = writeOnly_io_input_b_valid; - assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; - assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; - assign io_output_ar_valid = readOnly_io_output_ar_valid; - assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; - assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; - assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; - assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; - assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; - assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; - assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; - assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; - assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; - assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; - assign io_output_r_ready = readOnly_io_output_r_ready; - assign io_output_aw_valid = writeOnly_io_output_aw_valid; - assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; - assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; - assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; - assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; - assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; - assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; - assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; - assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; - assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; - assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; - assign io_output_w_valid = writeOnly_io_output_w_valid; - assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; - assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; - assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; - assign io_output_b_ready = writeOnly_io_output_b_ready; - -endmodule - -module Asic32To64UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_aw_valid, - output reg io_input_aw_ready, - input [31:0] io_input_aw_payload_addr, - input [7:0] io_input_aw_payload_id, - input [3:0] io_input_aw_payload_region, - input [7:0] io_input_aw_payload_len, - input [2:0] io_input_aw_payload_size, - input [1:0] io_input_aw_payload_burst, - input [0:0] io_input_aw_payload_lock, - input [3:0] io_input_aw_payload_cache, - input [3:0] io_input_aw_payload_qos, - input [2:0] io_input_aw_payload_prot, - input io_input_w_valid, - output io_input_w_ready, - input [31:0] io_input_w_payload_data, - input [3:0] io_input_w_payload_strb, - input io_input_w_payload_last, - output io_input_b_valid, - input io_input_b_ready, - output [7:0] io_input_b_payload_id, - output [1:0] io_input_b_payload_resp, - output io_output_aw_valid, - input io_output_aw_ready, - output [31:0] io_output_aw_payload_addr, - output [7:0] io_output_aw_payload_id, - output [3:0] io_output_aw_payload_region, - output reg [7:0] io_output_aw_payload_len, - output reg [2:0] io_output_aw_payload_size, - output [1:0] io_output_aw_payload_burst, - output [0:0] io_output_aw_payload_lock, - output [3:0] io_output_aw_payload_cache, - output [3:0] io_output_aw_payload_qos, - output [2:0] io_output_aw_payload_prot, - output io_output_w_valid, - input io_output_w_ready, - output [63:0] io_output_w_payload_data, - output [7:0] io_output_w_payload_strb, - output io_output_w_payload_last, - input io_output_b_valid, - output io_output_b_ready, - input [7:0] io_output_b_payload_id, - input [1:0] io_output_b_payload_resp, - input clk, - input reset -); - - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [2:0] _zz_cmdLogic_incrLen_2; - wire [3:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [7:0] _zz_dataLogic_byteActivity; - wire [1:0] _zz_dataLogic_byteActivity_1; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_aw_fork2_logic_linkEnable_0; - reg io_input_aw_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [7:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l21; - wire when_Axi4Upsizer_l24; - reg [2:0] dataLogic_byteCounter; - reg [2:0] dataLogic_size; - reg dataLogic_outputValid; - reg dataLogic_outputLast; - reg dataLogic_busy; - reg dataLogic_incrementByteCounter; - reg dataLogic_alwaysFire; - wire [3:0] dataLogic_byteCounterNext; - reg [63:0] dataLogic_dataBuffer; - reg [7:0] dataLogic_maskBuffer; - wire [7:0] dataLogic_byteActivity; - wire io_output_w_fire; - wire io_output_w_isStall; - wire io_input_w_fire; - wire when_Axi4Upsizer_l59; - wire when_Axi4Upsizer_l59_1; - wire when_Axi4Upsizer_l59_2; - wire when_Axi4Upsizer_l59_3; - wire when_Axi4Upsizer_l59_4; - wire when_Axi4Upsizer_l59_5; - wire when_Axi4Upsizer_l59_6; - wire when_Axi4Upsizer_l59_7; - wire cmdLogic_dataFork_fire_1; - wire when_Axi4Upsizer_l68; - wire when_Axi4Upsizer_l68_1; - wire when_Axi4Upsizer_l68_2; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[2 : 0]; - assign _zz_cmdLogic_incrLen_1 = {8'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[3:0]; - assign _zz_dataLogic_byteActivity_1 = dataLogic_size[1:0]; - always @(*) begin - case(_zz_dataLogic_byteActivity_1) - 2'b00 : _zz_dataLogic_byteActivity = 8'h01; - 2'b01 : _zz_dataLogic_byteActivity = 8'h03; - default : _zz_dataLogic_byteActivity = 8'h0f; - endcase - end - - always @(*) begin - io_input_aw_ready = 1'b1; - if(when_Stream_l993) begin - io_input_aw_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_aw_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_aw_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_aw_ready; - assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; - assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; - always @(*) begin - io_output_aw_payload_len = cmdLogic_outputFork_payload_len; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_len = cmdLogic_incrLen; - end - end - - always @(*) begin - io_output_aw_payload_size = cmdLogic_outputFork_payload_size; - if(when_Axi4Upsizer_l21) begin - io_output_aw_payload_size = 3'b011; - if(when_Axi4Upsizer_l24) begin - io_output_aw_payload_size = io_input_aw_payload_size; - end - end - end - - assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 3]; - assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); - assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); - assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); - assign io_output_w_valid = dataLogic_outputValid; - assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); - assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); - assign io_output_w_payload_data = dataLogic_dataBuffer; - assign io_output_w_payload_strb = dataLogic_maskBuffer; - assign io_output_w_payload_last = dataLogic_outputLast; - assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); - assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; - assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; - assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; - assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; - assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; - assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; - assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; - assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; - assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); - assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); - assign cmdLogic_dataFork_ready = (! dataLogic_busy); - assign io_input_b_valid = io_output_b_valid; - assign io_output_b_ready = io_input_b_ready; - assign io_input_b_payload_id = io_output_b_payload_id; - assign io_input_b_payload_resp = io_output_b_payload_resp; - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_outputValid <= 1'b0; - dataLogic_busy <= 1'b0; - dataLogic_maskBuffer <= 8'h00; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_aw_ready) begin - io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; - io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; - end - if(io_output_w_ready) begin - dataLogic_outputValid <= 1'b0; - end - if(io_output_w_fire) begin - dataLogic_maskBuffer <= 8'h00; - end - if(io_input_w_fire) begin - dataLogic_outputValid <= ((dataLogic_byteCounterNext[3] || io_input_w_payload_last) || dataLogic_alwaysFire); - if(io_input_w_payload_last) begin - dataLogic_busy <= 1'b0; - end - if(when_Axi4Upsizer_l59) begin - dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_busy <= 1'b1; - end - end - end - - always @(posedge clk) begin - if(io_input_w_fire) begin - if(dataLogic_incrementByteCounter) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[2:0]; - end - dataLogic_outputLast <= io_input_w_payload_last; - if(when_Axi4Upsizer_l59) begin - dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_1) begin - dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_2) begin - dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_3) begin - dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; - end - if(when_Axi4Upsizer_l59_4) begin - dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; - end - if(when_Axi4Upsizer_l59_5) begin - dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; - end - if(when_Axi4Upsizer_l59_6) begin - dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; - end - if(when_Axi4Upsizer_l59_7) begin - dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; - end - end - if(cmdLogic_dataFork_fire_1) begin - dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[2:0]; - if(when_Axi4Upsizer_l68) begin - dataLogic_byteCounter[0] <= 1'b0; - end - if(when_Axi4Upsizer_l68_1) begin - dataLogic_byteCounter[1] <= 1'b0; - end - if(when_Axi4Upsizer_l68_2) begin - dataLogic_byteCounter[2] <= 1'b0; - end - dataLogic_size <= cmdLogic_dataFork_payload_size; - dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); - dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); - end - end - - -endmodule - -module Asic32To64UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_input_ar_valid, - output reg io_input_ar_ready, - input [31:0] io_input_ar_payload_addr, - input [7:0] io_input_ar_payload_id, - input [3:0] io_input_ar_payload_region, - input [7:0] io_input_ar_payload_len, - input [2:0] io_input_ar_payload_size, - input [1:0] io_input_ar_payload_burst, - input [0:0] io_input_ar_payload_lock, - input [3:0] io_input_ar_payload_cache, - input [3:0] io_input_ar_payload_qos, - input [2:0] io_input_ar_payload_prot, - output io_input_r_valid, - input io_input_r_ready, - output [31:0] io_input_r_payload_data, - output [7:0] io_input_r_payload_id, - output [1:0] io_input_r_payload_resp, - output io_input_r_payload_last, - output io_output_ar_valid, - input io_output_ar_ready, - output [31:0] io_output_ar_payload_addr, - output [7:0] io_output_ar_payload_id, - output [3:0] io_output_ar_payload_region, - output [7:0] io_output_ar_payload_len, - output reg [2:0] io_output_ar_payload_size, - output [1:0] io_output_ar_payload_burst, - output [0:0] io_output_ar_payload_lock, - output [3:0] io_output_ar_payload_cache, - output [3:0] io_output_ar_payload_qos, - output [2:0] io_output_ar_payload_prot, - input io_output_r_valid, - output io_output_r_ready, - input [63:0] io_output_r_payload_data, - input [7:0] io_output_r_payload_id, - input [1:0] io_output_r_payload_resp, - input io_output_r_payload_last, - input clk, - input reset -); - - wire dataLogic_cmdPush_fifo_io_pop_ready; - wire dataLogic_cmdPush_fifo_io_push_ready; - wire dataLogic_cmdPush_fifo_io_pop_valid; - wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; - wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; - wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; - wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; - wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; - wire [4:0] dataLogic_cmdPush_fifo_io_availability; - wire [14:0] _zz_cmdLogic_byteCount; - wire [10:0] _zz_cmdLogic_incrLen; - wire [10:0] _zz_cmdLogic_incrLen_1; - wire [2:0] _zz_cmdLogic_incrLen_2; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; - wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; - wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; - wire [3:0] _zz_dataLogic_byteCounterNext; - wire [7:0] _zz_dataLogic_byteCounterNext_1; - reg [31:0] _zz_io_input_r_payload_data; - wire [0:0] _zz_io_input_r_payload_data_1; - wire cmdLogic_outputFork_valid; - wire cmdLogic_outputFork_ready; - wire [31:0] cmdLogic_outputFork_payload_addr; - wire [7:0] cmdLogic_outputFork_payload_id; - wire [3:0] cmdLogic_outputFork_payload_region; - wire [7:0] cmdLogic_outputFork_payload_len; - wire [2:0] cmdLogic_outputFork_payload_size; - wire [1:0] cmdLogic_outputFork_payload_burst; - wire [0:0] cmdLogic_outputFork_payload_lock; - wire [3:0] cmdLogic_outputFork_payload_cache; - wire [3:0] cmdLogic_outputFork_payload_qos; - wire [2:0] cmdLogic_outputFork_payload_prot; - wire cmdLogic_dataFork_valid; - wire cmdLogic_dataFork_ready; - wire [31:0] cmdLogic_dataFork_payload_addr; - wire [7:0] cmdLogic_dataFork_payload_id; - wire [3:0] cmdLogic_dataFork_payload_region; - wire [7:0] cmdLogic_dataFork_payload_len; - wire [2:0] cmdLogic_dataFork_payload_size; - wire [1:0] cmdLogic_dataFork_payload_burst; - wire [0:0] cmdLogic_dataFork_payload_lock; - wire [3:0] cmdLogic_dataFork_payload_cache; - wire [3:0] cmdLogic_dataFork_payload_qos; - wire [2:0] cmdLogic_dataFork_payload_prot; - reg io_input_ar_fork2_logic_linkEnable_0; - reg io_input_ar_fork2_logic_linkEnable_1; - wire when_Stream_l993; - wire when_Stream_l993_1; - wire cmdLogic_outputFork_fire; - wire cmdLogic_dataFork_fire; - wire [9:0] cmdLogic_byteCount; - wire [7:0] cmdLogic_incrLen; - wire when_Axi4Upsizer_l108; - wire dataLogic_cmdPush_valid; - wire dataLogic_cmdPush_ready; - wire [2:0] dataLogic_cmdPush_payload_startAt; - wire [2:0] dataLogic_cmdPush_payload_endAt; - wire [2:0] dataLogic_cmdPush_payload_size; - wire [7:0] dataLogic_cmdPush_payload_id; - reg [2:0] dataLogic_size; - reg dataLogic_busy; - reg [7:0] dataLogic_id; - reg [2:0] dataLogic_byteCounter; - reg [2:0] dataLogic_byteCounterLast; - wire [3:0] dataLogic_byteCounterNext; - wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; - wire io_input_r_fire; - - assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); - assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); - assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[2 : 0]; - assign _zz_cmdLogic_incrLen_1 = {8'd0, _zz_cmdLogic_incrLen_2}; - assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); - assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); - assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; - assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); - assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[3:0]; - assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); - Asic32To64UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( - .io_push_valid (dataLogic_cmdPush_valid ), //i - .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o - .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[2:0] ), //i - .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[2:0] ), //i - .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i - .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i - .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o - .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i - .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[2:0]), //o - .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[2:0] ), //o - .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o - .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o - .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o - .clk (clk ), //i - .reset (reset ) //i - ); - always @(*) begin - case(_zz_io_input_r_payload_data_1) - 1'b0 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; - default : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; - endcase - end - - always @(*) begin - io_input_ar_ready = 1'b1; - if(when_Stream_l993) begin - io_input_ar_ready = 1'b0; - end - if(when_Stream_l993_1) begin - io_input_ar_ready = 1'b0; - end - end - - assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); - assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); - assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); - assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); - assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; - assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; - assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; - assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; - assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; - assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; - assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; - assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; - assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; - assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; - assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); - assign io_output_ar_valid = cmdLogic_outputFork_valid; - assign cmdLogic_outputFork_ready = io_output_ar_ready; - assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; - assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; - assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; - assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; - assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; - assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; - assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; - assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; - assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 3]; - always @(*) begin - io_output_ar_payload_size = 3'b011; - if(when_Axi4Upsizer_l108) begin - io_output_ar_payload_size = io_input_ar_payload_size; - end - end - - assign io_output_ar_payload_len = cmdLogic_incrLen; - assign io_output_ar_payload_id = 8'h00; - assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); - assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; - assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; - assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[2:0]; - assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[2:0]; - assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; - assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; - assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; - assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); - assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); - assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); - assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); - assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); - assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); - assign io_input_r_payload_resp = io_output_r_payload_resp; - assign io_input_r_payload_data = _zz_io_input_r_payload_data; - assign io_input_r_payload_id = dataLogic_id; - assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[3])); - always @(posedge clk or posedge reset) begin - if(reset) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - dataLogic_busy <= 1'b0; - end else begin - if(cmdLogic_outputFork_fire) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; - end - if(cmdLogic_dataFork_fire) begin - io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; - end - if(io_input_ar_ready) begin - io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; - io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; - end - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_busy <= 1'b1; - end - if(io_input_r_fire) begin - if(io_input_r_payload_last) begin - dataLogic_busy <= 1'b0; - end - end - end - end - - always @(posedge clk) begin - if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin - dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; - dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; - dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; - dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; - end - if(io_input_r_fire) begin - dataLogic_byteCounter <= dataLogic_byteCounterNext[2:0]; - end - end - - -endmodule - -module Asic32To64UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( - input io_push_valid, - output io_push_ready, - input [2:0] io_push_payload_startAt, - input [2:0] io_push_payload_endAt, - input [2:0] io_push_payload_size, - input [7:0] io_push_payload_id, - output io_pop_valid, - input io_pop_ready, - output [2:0] io_pop_payload_startAt, - output [2:0] io_pop_payload_endAt, - output [2:0] io_pop_payload_size, - output [7:0] io_pop_payload_id, - input io_flush, - output [4:0] io_occupancy, - output [4:0] io_availability, - input clk, - input reset -); - - reg [16:0] _zz_logic_ram_port0; - wire [3:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [3:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz__zz_logic_ram_port0; - wire _zz__zz_io_pop_payload_startAt; - wire [16:0] _zz__zz_logic_ram_port1; - wire [3:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [3:0] logic_pushPtr_valueNext; - reg [3:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [3:0] logic_popPtr_valueNext; - reg [3:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [16:0] _zz_io_pop_payload_startAt; - wire when_Stream_l1123; - wire [3:0] logic_ptrDif; - reg [16:0] logic_ram [0:15]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_startAt = 1'b1; - assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; - always @(posedge clk) begin - if(_zz__zz_io_pop_payload_startAt) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge clk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 4'b0000; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 4'b0000; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; - assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[2 : 0]; - assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[5 : 3]; - assign io_pop_payload_size = _zz_io_pop_payload_startAt[8 : 6]; - assign io_pop_payload_id = _zz_io_pop_payload_startAt[16 : 9]; - assign when_Stream_l1123 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge clk or posedge reset) begin - if(reset) begin - logic_pushPtr_value <= 4'b0000; - logic_popPtr_value <= 4'b0000; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1123) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - - -`resetall -`timescale 1ns/1ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -OOoBg4gI2nZAz8wwveQb2xYziCO/14ylivOE2CroC0KR1q446pg5ZHoTPlNXu9oR -FRdk+YQI93EEtwl0LJTuMb+sGUNIUS2ieLbzb7gpgkBuOgUljkWzXsN0p2S8f9nQ -QN9I/ZlxuRJ+sjdUPzEEEWHeUFIamGV/bFLJQRvloxvTvwLpmavqG6GhWi2vdXHo -7WqQVvDZRXw2M1o9dR9PdlpAkysf1TragnGQk5AkUZ3qOXFRHbxOhnJyTnaE1GyX -Oq59frbbD4+rLXSfc5EcBvIcpDJOgpRiCtikYUTFmw45b5M9gLaBYasEi8c7ZLIR -hQNrovA1RmOBbD4PGOXIrw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 752 ) -`pragma protect data_block -om+C6TrXX7WvV09MgL6R62R+Od59uPw5eeLNNbNww55GLUXwwj/XGluwdblYZx9I -X+OGjlllzxPGhddDes1uu0dNKh2ykfPsuWVHff2KPOJBKoYeNx6pVHSJR6EuePH0 -AhyaQM8gII6oK6SM94NjiC9BWcfDvsjfNZytp9D451ZvKE98e0NYabL8MIo9s2kV -hXffla5eL/f4PK7O6Y5XPFWrEpZtzAnWBDgKmEsiwAaDCKqGSY4iiwUewIaBv+no -+Ka4H3jnDmn/kGjkCfbajYK06RFHwFFJlgAzE5OFkMY8Ksmj63sVYM69D9UbM9DF -niOhc7FJg8UxSMZivgX9broAWkURRuJv8CeV37kSTWQY3ZEYK5YVCUjgwJEDCYju -ttWTXEpc3zXD52bxJep6OqjHO4n3brwnDjGeWrfb2IENd5VuXBspvMZ+2N3dGmpM -2nyNRZa7erdjUbB3k9+o0Efs02Jvj7TCsviSczk7axZYkJZI4mxPF+b8FStXCvEB -LXfZ7zKmlAcvi4QhCJ3anblnrJDeiGvv5UisphO/KeahF76MYUcZZi2tkiS7KcqN -BgGiZEgzvz6q/euENKIJAJI7Z+YoEOXDZfFoEW20WgSe2LbF5HK0npobYc8MHqIs -Pj1UIlLucUKcAg865RSblbpeLgNK5ryqdU+QOwi1pM8JFsgF48JfdVWMaFu9sWdV -zMNn55XZ4AvwOAnua8nN1fZ6mOpwJX4Ebii/zW5S/6Mm0kbhHkqZg78eXQEQMbJP -5YUFRgm2EkdKkxUmk2qwycEMEqLvXk/aOg48zpGcLAp9LwMjFRotYNW5+ygxGGQ9 -WR2CYo06vLomSI/uE7XlTHHUArxUtH385f1fq7V4QRutX19Wjq6GyG/YJWl2JURc -u+WqUFTAylQRC8Fhb+BPUoP6oW1YmiFwJ0LDM6xFkFWk7by/1wO0DdZV+slmdKR2 -1sxJAK6dd4yk223AytIzJlN7eZ9pmgJa3n4/X0QNDSY= -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -lvtXQ11Z9LNNq59Ajdesxcgo5CSVwrUQlGzmWsibhgsAsHyCjqyj0vMRSR+QiEty -/yyi7z21Q4K7YH9jOeDy5ci704W9tiZzbY6jJLUXKIB8tCJnB8DHWfmPTJjac1+X -kAprlwdHkFxurVjCyvzvpsDzl+7qd3dfEhaBAOQTrigUU88CdOFxwRcXpGn8arty -jpeOR3kDUSTf2tPHovV/i7635KJFX7o+tzJgPU4pQpgxBuHNN2b2rUy4eZxHS8/K -SkBE3iIjiOUYaJHZOgUGks3PvjFmmj3eD3ktt+v8nt/ozHPjJ7+uP8/p3i+qPyOY -4YYq/Ldon1lQeJanU4emrg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 800 ) -`pragma protect data_block -LXRln5CGH/X3ZcC9f1s9GTxumdb3ijnQQ2FPf5CLS40wU3FpMlOGzCsOTBaQ0U2F -9oguD9QGHXfbD1Nd7PairdinewSLKx8JR2NJDQobGByPc+ysqVmUtvuhRNKAl33p -T6XjMlhW+ErrSsLQLWyzVl/WuxdW9LxIu0sJtoA07ny3Tlv/mazOJBv/qiQeV4MN -ME3SEpILxBCTIfkZTacMxEgSQWExjpebTwhrH+qQ6BlH+G5OLRJkwgGf3zlGBAOv -WooRGb02wwE4zZT8LVq75rMiXDHrLTYLa33sLqoXQlIBMH8+EyVUyg803Ob8M3T3 -P0pOvZ3YinKmZt0udsR76q1filXw7Vr4pNnqfY6jN5Tcx4SfVVOrAgATj0mb6yO4 -PN5I8gqTmaiF2qTM3Z9OvVEH/15Q+L5BIfkaD7NrXvexgwjTCbQZAqOhro8gUp8I -0FU85AMYy3vh0GId10O0gj9uIqlBOCzpSPp4v+vxYL9gXe71r8jkBkx7xWspnrlV -reIqWJt6b5eVQ0Evqm0zoWTq1f3KG2QlOcv2XRxexmjrZJxN18uWjtHJT79Z9HdF -zD0dyC2++DANYrfY3k2Bdjq9ul3WjDfIF1IZmie5nqpY/Doo06O4BvzJma47Ridu -McqvFIpZnD8bO/fJpsHFSTGOJ/XgjTD6L/mAUMgNg/xywOohLinUAFv7btl1cos3 -11npbTSOQo68RlTNeyZWtZ+Jl7ymhhjlYDbUu/vXwSN4eZuWWwL7ZggynnqMSRC6 -mkr+GDI2YWg+2zYAGJ2dbgcgug8yKlwu7pGL1jXD2NIGOTpSB4Za71jBoqh7baly -3w+qb2Jpj3QpmzfCsMJb/QfVrtQ9pXl6uRnvN0hp+MM+hkRTZmW2QcHa0qMk5408 -UYZQGWsUBKVwB9lktWOt7QSXi7MVPzzHtwB0LM0jAYZGP9JXj5w3GXjKQt5lfdv8 -7fEoOfhB23IpJpo70B2ONKCH6eIA2BI9kvFO0JaafaohQixe6ZP0x6E1H9Uj1d8Z -uBMxCVtI9jJ+5v6FXlHl19YPtiRAPje2oBZ7f5kz7jg= -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YZcxj4NiuiyaBjwj3+i08UfgElpJok6CAPrtf/VeNVjKQ4vA0nsIxPTauJCmLxEk -n2CsXLkWDAo0vTBJ27P2Gzis+Byuf3ie2/rrt4Nsk3r0oYiZI+/ne+066AsA5vmj -nqK12/q++uVjy1BnXRhJWwyJxZPo+9rnGQRERXZmgh+QZ6ejYS72L8ufrSK4hPmE -2/vPW+haIsw4iifrZaqfmJNT6OA24BG8ZnyU/hCNVUwzybiZ5NNgyzuo4U3x3eq/ -b3ZP5uRk7g57KmnXDVio+dAa5DNl+z4ImILcjLDJcqJ7TBRa26pECkiCFo/84A3K -87RH6WBz+a0EgK85kgWFBQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5808 ) -`pragma protect data_block -cFcWPJSU3e2Rdd62+/WBbQ4M/VpTw2qhSBMfL8eYbNpdXnkifLxwuRR4FoMccpQw -e8cxhwO6YChEAaXawYmul06piurwYwL47Mztl2oLZ79DYbrxpVSfHMHkHrhJ5mKK -gVdWjF9ihtQ0I/uuaoD8MUo9+0t5a1YFFaMVzO4L7If7ZXR+qwx/Qbog7MTv0eGj -uJTkdSBLo3RUC1eGaDV6ewUTjtCxeVAtmeQLHVPMGXQo7dkXXuemALW8ZmUf/M/J -6xCWZdr7rAHAcf3VKTWZipGdIoKTAhEilZWZLXyyseviBUQ8V/TEKrhS7ei1SIXk -xoJdCLu3HWmHy3uptWwZl0difB+wdl/wAv6R/ngi21ZH7ibyk/pWrrriGn+Jblkz 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-033gGDVBLLjTa1FRhbPwsfM8oELuGAoxlyemGiQKg/kpSZypLUbq1rf6NccDfeEo -mvL1KQo4mQeD+4PMfADDtTDrgTo04Q0+dyYY9k22s2/rS7hLjbRym+kvsZLekG11 -buSVQbMAkZlhVW1Iu7gcQdM2bNT6RCmE75FMI7vn7/jztTgPV129EPmee5laQNXd -GHnBcJ/dJ0JVwoBSvi62xer/61Xr+fNVlUjuJauFn/PsjLJZZsIbQ6iC7gl7wFaW -Xa81QIjPslAzLVq2OOCBfjUzhTWXE4Sb/BAbmylYxQnml1NSS6vnaTbji+pntP68 -pUaliLDS/OOIza2PlYxHVG3zuH6b4+iQ1bFWeJS1kPYQSBb1smoVlSMeWIp/D32r -XIGWcCKsLzpdP2bMk3FfM8niIXjn77DyPNej9N+hS0TqKOdKLAHx0i0kTWpMwlH9 -nhhKvfPxjr/oXwPfBapV4sjOXrwB50W8t8cA650jPWnQLv8SfeqjIBcocy9teGlF -3R7DIDOlt31yWL22elg1zoEJh50nvSbyZAhYsplQnGsUE3C/XfRDjb6O7kpBtCQJ -AWyoJ0wbkimpYv02vSac0yzTuxMrhdKs3aXuWczN3I4sGuyO25iHqruyO2CG/0RD -dJejxndB1DFwJ7JVHy/JaRFh5qmxehOVLJBmaeqH7GkBWvbnQSwoei0LN9qL/LPK -9rcFAMy7AtD/fXqe+IXxtzdmEdteo8IMN+vhCm5L9gxtIU8wCvxBvhWOxYo12NIp -frxsi3IuIvxnuLg+RKGfOaBQF7v5uDNkYLHBmT31zx7Ak1UAWnFcnFPC2yfC/qrA -7ZrIJlCEoigiNr2Yi6A2Zs4MSx9fMWgimfamgGP6+/ujmEQQZuu2xl3emmmc+XOg -Tnv6aQPfcQ7mfgJ8XZH7x5SBf7anOZ5EkiAQBRPSuMY6LwjD2cv4zZRg+ZmidxEH -TQ6cTMB5V7I7JvKj1GKYi/YtmULWziSI/RrI6bO760k96jz6Y4ni6KgdfQkbMXya -EpbqL+YyQN3qYLcjxFuzboZMrv2GrYatoiADyg3ROQ5cujyrOkxuv3r8hk5xv5et -O4lyBPRrC0wjR+edwSiecQ0Y73esrIU1CuoVV72gdLWfad98Li7pUUiyIn0mcfAO -MHas/cZtOU0VGILzY6ExVkizMDHAbiIUghmu3lPyMHGRsrAP4RYZHHRlAOowi5Sb -o+h3D3eflkK5rPIB36kDtMzzuhq1JEXr3Zj5HARBXnO57KbuoOw3GfvdK8g498zS -axGgz0m4OwqkwYBsuNi9y1tfITOdtxvjue4/mxzHLUWdyBTahq2Gq9UO7sPPb2F2 -0DAmbSrScu9S/dnZ1KQHx6rAWz1hWzx7oP0MgzOLJ/moyFGi6ljVwuRlxJEFr277 -SE3wbrkWgw2fBZa322gBujMzWTxx+L4xLma2qcdyJ2JM0/mKTucy1315BvnQA9dn -pJ21mZyh6XH4g5HmwYOyEFicj4YlEWrDN5ptFUzPjlgIYcH7DIjZMDfBCtLhIS1p -EwMqO7MXO3MqRZs5E5PiKrduY04kF41aB7x+1PSbRO47WHAVMhnWeCS4QzUTPRaV -vKo9uVM51UKszmxhXVhij/gi17Hml4tPJe6FteD1jP3LswycfifeDBgw/SCmdbGe -yP9D7xd4rLXtN2TBcyRDjFc0K/5fzMvxlWYTxrz7fdh5aLusbBjIETYFL5y0qOOx -uNnfezwVGFr/7Bp5HXrGwDLHBlRYOu2HrFhkrvoprISX2qgSHeJFL0kHH+2+V6mK -w3kpDJsDZi+QXVeenKqcti1txxSg/MOtNZhGb2eieYo8lI4FZKtQCFA3dWoeGjuU -SpZTDNzo7pIHakf4QUqrYIE1gFn2sNoCbBlx9CDx3ks/PzCDu3uqakh2O093kWQC -/8RxJuzcN+TXoLzz/H0BsGC+1K+Fo8YwQnsLj0YoXSBrHV1hoNBaDwo+ZdQE0KwT -B9huJ2kaIWOG3pej56lMiEiB1W6sQzCYlyfJzt0WCnCRwPNmCa6LGnABzJIYNNhV -SW+ddECTo6TgtdAKH0/k/QalAUjFJJcSRoWO4pgiR2yl65NSOH8R4bt3eMnHohWQ -aNi/l+UX/thdnaAvCZWa5Pw/coPPjvmwvGStTXXrLeLCiliL/DvGgcKSocebaki9 -iF38kB5/CrVvCeg+3G5cRfnjEj9Wcg20C8gRX9wyARDWq8IH78NxBzucmaPZjZyd -eSq09wViYxsMHYxVeblHqgyyzpS0sa9sqrgbPKIW1NtWQLpC7GQJ0nBYGbcaV3p1 -B+H4racUuzHzTbLgEkCXxnL4Iq4+l8nrao+CAKw/iEV7ZrCclvXRoDtOu0CZqBRz -8a90qCPA0xTDBSCkFFqmR0gLN8dKIj/k6fMijBRDtzk6xXqF1XXdYt8vZPTK4oMv -hOtL0ou35/o4JzD2QI3GoZhK4tx48gE9HZm/6pdHfCdyr6Czt2c/ravHkJYAyt7N -dVWd4ZJSsnE9oGXWqqUf/m0Nwilt86ouFanggwNJQzqBH9nAs7z3a1Ou3ML0wOBp -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -mEtbV9EGXcpC/6yko1/E5fksxy4umj6Ln9zdp/k87D3GnzU6MtGj2lR4GCbisMd+ -Rbqmu++LZV+2wB32AtLnsLppKmsYhO9jjXRe4xPQK1niY8CuPx9Fr5cd2zq0iVnF -bFX+yY9CqzKEM9Mvztoxmllg6ROMAs03PPD458s652wcEEnPn5klZ2tYXy1JQEyI -wuK0EmtlFp4B+IrUHiZZJoJBxmxQCtz1uIZrR8PF4sBs4OO9W5NB6s4hrEzn7Jkj -sQlyyW4RgbyZlTqNt3mz8Zwu3iGowx4s4CGhhIpgPPWdlJWY0smeNKsbmJXvOn+j -9uRi9+ghgR+LTAxZo0Ibig== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2048 ) -`pragma protect data_block -HUh4J+fK6YFhzi0NBDbJqMMdiOtZRe6d8QSG4h9yRGrUBaipIeawvKRtVUjxzOVk -Jrr8kMcAoGyqVG3ZA5rHQbVbOeS1eTWRktkUtgQJkbXJKY27q+jdqM6STe5Xyk/V -bUCeN7QwspaKVLlT+Z1OpcACekiWFgy7fiw79LHgI/wAeVv3w3YXmHvsC48YOuDq -XBKV7gOooz7/lzeIxEL61rgQfg7uOt/BwmbcqD0nzH6NRBrp6AA8vleKetSB8NMi -gRNcQ9ZHg1PxqCxNVVzBmtgFf0Cxn2FdzcyF0BfmBA78aD2dzze9hZT5orFv+/zV -fEQhjV2iAj84cfyH8tSIlnkWMMsYQX4fqdifZXOUtJ+45+uZQPkJ8idEnVj7k8be -zniyfaOum4sfspPnaa1fdpLwUMZQyOW7ZmKD0Ioistig9GqANK23zV43QKe/bexe -jmqhXDJANp4rJ2T23FciuAPkQGm0zeomzIgpjNFTtemGaDrHo2HYY+cpe92e14QB -0glxi1M35cP0FLbHXW4yFIjQswOFRLlY3/GbPvfn+9yJkzOjm4vhq0w40egknNfQ -2Np7SbqTtdRJDVnPZ2oo3UJkBCA7PM8kce1i3XmeIAFuN8m/TMKYV5WJQJiOTDyk -0XVcz6pahWl6rd2HwMLQgbpSejPudFTe3uLHS5Fi2aG2RTpHTYSCOIkNC+DovvB5 -+UzBIUJz4qx546ybA1OWuIWwmUl9BQnt8cxU6ARH+Sny7uRYL5X8RLR7G5qlVZGJ -gs61Eea2+hHgdnV/PJAx9HLDa0t6Tmwq4P8OD9OGH7PEPbPXY45/MDa9Ch3LX4Hh -HedkWuG3ryOYohdpMcmCr1zkojZ/DGaL7eqMKW7JprJxiXGZdoZ41aXt2eiCl74C -TVxPm+U4SSHQh3f0a78LWV7U4aSHb4SbAWaX4mUZE21RaF23DmqlUxuBYn/6+VLJ -SwZ8aH/eKwtPkXwaZ2gXtkGOMxbIgs/GKLRQ0k6sr/EMWEgYXpgY33LNzudM5u7q -XyWfoJMXciiY5uXUovD88q+1Ni3FUOD/brmf/3W3Hh3Db7zmkDcWvT1FDUDcGXep -5xdkPwBEmRaI8D4IYTVIr5kv+BsOFOQZWjLyShpJXPMRJ5g7qxSyUUhhKEgWkt5a -ZA79/VsXS+UQHfIPcWK38VPmkhnLopUe7Y2IoQiDxJJ8gkVfeNP8CvA8VRU2UMwy -SM+kjbARwKj/dLQ1GSYNOwEsTJ6/4M10Bc6kX6DCBxFjqs8dfN7LatGAvifFjmTt -Kdjb4at2888iGfE1UrrsE5NhETXXXdaCLYTk4n+vSvkH4aO4GaWq5el1NeZHvZ4+ -wFU0e8qENFYoZqM01NVm8ij5qtfSqEhuhtgEDhcYc9SXl7yoTgHQ7K/jG6dvfRx7 -p/LmrJj09+N+2ggcsnWOW7gWem7mLad7sAVHlxmYWWQCqU297iKmaHLaPBiqdw5z -/LXYK5ssju8oJaRyieEQFgD+kj6fZHoskYnyv/GA+PnGOkpyGyFaNZ+ZCoVfQWj/ -jGSosBOeflbi97GX9zcnz1kb6/XGWMZO0TQhRjQmLTECtusDlG1mDs0DVHXybjkF -N1fg1l4KuoOI5+sJkqPKAvq0LoOA+1hNUQ0IEMj51stxOiKdiIJV8P2TjFlZJYLs -YvQyBBeYej67sSKpFHPd2yrOtP44NNQAEpvjPt0mKhJXnzSN2qZvbKSBOgn4Sbk0 -9i4XJ0hXqI0JF23f/zw+aAlSGC6NiAIm554hbB94QmEyU3Ow4dojWO7jzkvqfjBR -ozkcMQfuqsBof3gEjovlJSAoHAvHK2w752D+xoLdSzT9iO+UlFCuzCAXblzpQCUO -Ud8xB1E4fgXx0HBegDqx4CRR6Levsch/Mldrxb0JqkgJ6Bkl+FxzmkjwaoYtwtZP -kCZly6WHPbc9D2tAJapm4P0FWFDsnBbF1ZmEz/aWKKkNVy+1P2RAUjChcjycAfue -3wygkO0ftd8oRoCRh2sfzZqJjip2nd0U3YeMhZMV9795zTA2S3v8nv3x0kScC7fK -fXCSZZtWr1J6P1pmcWOTd4f52+Ym5K30EDmu6aXC7tlnUYhBwP7zP4nhFy7ya+dy -eM3UvUd4oIPed/r5rvmF3uJycmC1ig9F6BCgKN2geT3+vi/bSD7RVlTua01tpcdT -dci8sQENmUG7hZ80aeZrZVmP8tWroI+a11/qAj6//drn9qo2/YnV1L4AWvtTnS71 -nbu8cx6B5LhuRMglPXNQWcPdcnqXG0Zu0WLNL5mbn/xjI6q1ksl9Ket0gyZiF3vv -u+c4jrQw4v+36b+nRby8L5rMDL4OdtLrg6ZJZu+nDIOpW4+XcKNDmS3GjgM1gBmI -Nniqq8O1a4Swei4JOAr6G0AJLDNZ6WZAd/bjUOFFg30a3+h9PwVuC34XI6XH1Y4b -nDDn6id74x0Fo82suxDTVUXcvLmO+YunWR/r6EOUmfFAVbww7vKsu6sGj0IVjifm -9sx7GJjNbunSQzLwcSQDMryZC/E/+uzBK+7Rfkynq5XTDPJlKTWxwsx8PmXB59DH -xR4MTfIS/h0JTnlxZfGAuHRoIccuaf3n3jI/OYEvyczsoV8PJKDSXtWsXeL5Sby8 -2jMXA2rVgYqb60AVjct58Qv2VCJ0FM2G7dxkENdAOwFb4yfKL+pynRvPYg6Q9UsA -1lGiJmNiNjrOEWcgXi92beZF2WZDdfs7ZIw/qwVgYuA= -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -J5uwiQrMgxLjAj13SAy3vsBmkypkUHuPQwyAno2NI+dh6ADhBeGoXkLbyWfXNO1S -b05RGEBtTRrRNY6f8sSoZPBYR58MJ73nuTvU++VlZj/tjtveso5nLIb3L9Vkcd9u -0AiQMLa2c0BwzGlJOtCwvWFRdnBcL99FI+19wu3C5WuQGCEmRoMY/ws1Iqm37Kqw -U1xX3Dwt8W6rsiXga2zZB25WuvJH7x4XHQfNqjaLhKknhS2JfB26tukpUQnAWPnW -dD5cGa9rs9jsi3/A7lx2vFtvkxyCF2QF4w0Gp/PVpiJE/shh4MsCHia43FXoq7AA -+ky0TMuOm0HojmlyU4c00Q== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8624 ) -`pragma protect data_block -oZ0GTgaY1jFft2IB2hWTqNnQiodJUwzfVbr6akyrVbz3jFePptbD6OJF+iN40U5m -0daNATJHzAAhGlugA6j6S54r25yU4y/t7UJwm+H831ajTDW4z9BGSYJz0wMNw3ju -4JMlN5OQxPLh+7lN1i192UAOe1M++DSrXrfGhCwrZD5RZMDC1UiXGtimTv8/5oQw -Zmbe9WZeFxEX2A+HofUOuEdMMchLziAg1HE8FW2cG3LL4c4Ymco67/+jdqrtpFIz -zZymAyvBPZd4u77o16AitfasOtKfKhn+wk4u/BvRNFNcd4x4N2vNR/b+MOp2Oz3v -0mESKr9rFsQcz+nn58QRO87AqKETfMbvC+H2mgLRR4jfdTDjb5wd8a2OAFIwdZmj -Dx9HxKyGAkbs1hDz25qYZHEN86Uok2UN4m4Y3x9edwjdprSd7e8hwzD1Dbfbhte7 -akuJglUszDNYuDqmJSvmZT1yE9P9Z+BKj4krcs0wQ6bRmPOmTC+v5pm53HC46sms -lwiy2x2BjLpyWJXWWBpmd4tHBpXJwy3xhc+YECnyGwgeTP+IfjlyYuSBw1XhjRMz -xCRuQ8ERkhThmquMpedpOcQqNlY/eOSXsaAb49b9lZAzJoYkysUJEugj3acXr8sQ -ixUwQAYHoZUFuf148eU75Pe5g46di9pJ/tsT1Lgw3+sIDUhHFVi05vsHop5EqVVU -tSyEF51g9pnpKYtniZUSC1wblp0pWZPr46kjDMQQf+TTOReFg6U9LVNkmNt7wXkL -zSl61xQdDP2SzIlJ9NZ4LuWtPbCv2phM95WMSzZpwpibh/r1RU+0+SACJCJ/Xv8I -m1k8xKAP30qKGYbwKAeL2eTizUNqxHHeMsikd2d/pi58Qn1NvtwZXvfGrpFdM0Pg -GIyj5BUMTpyDBODwpwdqtZnoOhbN8E0nu5Y6j2kbKkb9jVh67+GZga6BzDZ4HVTX -RexVm+BO2zaGk64cV6WC021eEauuKZs1OU/57uF+NrIN3FQ5s6ST+JOzT+lTySpG -9KeAaDJd2WI78e5ewytrhbE5XPo8Voi/kInyy1NnNIR4rOYU6SOxd7V4Jl6xaaqJ -c7GLAnTCSZn1T37LB7gV7fUYOigOX86fxTc8xD4TXRibkNODXeKCjE4T1j6RL7+y -hYLDCmysyURiXv+EYiWhdFESEYFopkex9y2YN5d55noXxp+am6KfhTVSgzMRD8+1 -Iy/Z5lN6GqPvejjnHbuDkxgFdDc0WSxDGjayOyExTprybFJ/HLOLf3m7DsPYttHr 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-6tchOOT/5XnWTj5UGmMHH6C+AD1EE+593b1qdhQv9DtD9gfF5xdqb2m0QbQc0Li3 -9iIrdCWC7cLalnsdn1m0hPZfA9dfqVfIQE19mO7YqQonV3uwLV6RBMvbvyoaIVRa -tSzwNYj5V9fc+J/1KU5XaY9V56XD6EjDa6RD/fyu5ZbpfLuvdavbswSDYnakHh5p -ctKeCrOK07oFPtSPCQjTc84eNRaw6gKaml8ZPtvuQwfJPsDnAJ4XeAqy7B+2A6Ij -NfLnGt54vskBkBnQz+VqemZBTAM+h5g6etoe0SdmVVOJviXT40oLyh3Hwd+jUPP+ -f4DfYwwqiW23WvEdEEKNEaTXfqc5gmmvGjcnqWFcLhScXIueeZcUa7HwtMTjSxtr -12a5UOwHEepebFzd6dMc6BkUnbBIqEKvGzZIJH7Kov12PrfzLk0FhiHMQVCrqmBg -xiq8i5zpt08Wxw8ZClp4v1USkVDR3yXcrAS4InvKa/ZxO7AWIUR1B5+w2mygbkxc -KMluz8sKuQWe8QJMxJ18haqRSXXFPK1sWwFQ3G2MDQtK0u5uzjaJWEzCixqIjEvG -aPiPoU6oKh4b0Tynsa/X6sibE8hPt121rb77zQSr27QLFSu2EEZZhk6GvtNMT88O -0o+fHPKo9UJVXTqCh/n0gjYLx5Fm9UR6hhUVKWS86LMqoq++UlK/VhlPifBer+W4 -Rm1U5WdsqmtVP1Af6Piq3YZhLxgOUZiOinlpT4LV2KkXdMlnEgAIUGH6RyTEtKF3 -JQ72fPPjsv3f4X4mm38soHmhIvf7hVJVcUKMFXuRan7qEpWiwsJSVHh/Mfkmowee -8MThc7HvPOj2OVeLWWTkW/UXxK2aD8xzlyr91BAm13PycbfjjHjKsv11sVm3ynK9 -F8T0B8oFaZfDshBGXENi4Ct/xPE1Cao+9ngrI5Y1SH1gNxWuP7GTmTW6hzcWHD5t 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-JRA643/2XOamn2oxrSEQHN7PU03HKVI8j4TYzU2kVtQ9ZqqeoqWGBMo70wCI9hIo -sXPt7UbwQ0jr28hfJZ/7bCZKiC36MX+7cKP63GNnIAILn8IuUwaO1y9Y2ejHIfuF -2N7ma1YPhjWKMsI0HYW9jjTdmqQ/xaAVXRvbTfjAXPSH+FNT2MkIMCZYYM/Ti8WU -vxnBpd0gSLKzsFvnNCDLTv5bXHWdoOJ2RJVf95B+SCeVqHUaik/iEXPxQVDrUOW6 -LLD1dQXpRCWiTiL3Ju9RtCLK4LKXBDAOqyWeK/MNN6IvmOd083bo7vlpJw3ksy8p -fl/FzC6o2cFT+Z1Dt1I/HypGuYgCthj72G5zNuTWEPnf7+cZRDTIaN32fUuobpmF -VhZNJUPcPv5lrHc2E1y6XRFS0m3Ngzg5Z81M1Je9bFVVWYcXz1RDJ3hqCS3fVbti -8rzMdh/lpmaXB3JMGXaoTGdJN2cTpWLHIQS8CG+Rf+LHjUDS1gCDNq80F+ip3yB9 -HBcwyl3MqEWyhiyY7wHaREvaM7f4NpLubezNM9nuu2FkiXbIN3UCCnbLK+rk231E -/yX3yqBrWGYVQNDq2CP5yDdRpHJLzDwTwX30lKYfwcI= -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -jUjs/IOtuXb97xlmyLq5Edj4QcB1X4njm+CwasvqhiKDISF/uEFDJMVIj/u+M795 -kVf3cOwkzvRxZbOyaqa3d3dNrJpmCfLcCQe9XSPq6gw7Zx5h7mCBR8CgBosd/bPN -dJDcmWwSeM2dAAY1L8RWZaVAt0ECVzK/jKZ13nbpAbZzrtXkLSGEm7C2YEoVz0ZN -pBI0A7g9Sefz2Hy6Y0d8HdbJMKW7zm7KRME3k29eMtEmlE1qKdJfxIduXCGWs2Mb -qKWPodTwUcLeIzd872zib1vwIJdgR6giq/AJhdiN5IcJxFDvjjatsulWYSfE1iO/ -jiC1tGg4ec/+iJP41bbQRw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 15200 ) -`pragma protect data_block -KdNDALrSiDzN/aVTuRIcd3tYoSHmqNEwKAMOby6rJyhY62B0zOwd1/PkXsicwrji -SE6MbG0JEsXRHFgNneDXFDdMCoHDYrKL1s41Iw6Tt7cmuszErzY5umojyGFgO9o+ -ChLfS8W6rbLMWO85cc8UwpiiEBKiKa7WF5aM3fLymhss6eFjoqtkjNCFjM8EtcLI -fAMWzSX9mWKiJMRZeknZpLP21dsjYDmEzWQ4ZNGVdxMme6lCd1xiwkQXp1tUnNoV -KFaab2gLghoP/JNsOtimnPV44pv+O7vp4Pcju9puVpB8u2V5JU9bVvjJ11aD2aNN -ETQPGtEPu12ABXNGhX1uIGwYdmBczC58WF2owIn8NMHMp9oiyj7mMIpr6YkHqGJD -7VUemv/WRidINkyXxkaJ8ArHXixKdT0EM+okMDz9hlh0fTXtAnOpiNMv/dclAGMa -xkDmWg3tYj40QfFgGIdfOhbWfg/4qTvHIP1VN6VXEdjaBsc+AVUvyZ099ERutDz/ -dBntwwOAyI7IjNGQbe44QCvty1cH7inGi1HEQ0i6Ca0ibm44mJK5h3e7j459MXJf -WM+FZa3P7A/kV46TljSuL0jyGvfPHwVchF9X8UWiQeNSQlk4qUrJkLAfqSJBZPNb -unAQ3GYpPs3rnbLZ3lQoIWc5+CZEgUA22ndLe9PwgwC20cSO9huHDWmnZPFZlPt+ -W2JyZ49wxmQUUJ+AToZ6mBKJSGlfsLtaoSVu/60ctxuIq8ASnGm/8iY0G5V6GEFD -b11srFlGG4dSG9XjGxj6+MIwUKucL3XUvi54KE/xj4u47YJCXgQV4mtDT0bo80wg -+tcc4uup4/cow0j2PDTjwlDqvGE7iPwsFm0oIjidzpfEuFxldIbFzk6DcVgOeqlb -dubk9E+/d0exqS5g2IqKEUfrQjntIdrXjs9b274JhgtLXzG6RQbjG08tGUVKmsYS -DDtJEeeTNu+qXM8hyixPLxVd+ABocUUeNrdPY7bgHX/IrVhtrep3HTVTR9tNNsOG -EtJN0PKWBeCL8Osq9zCdzTw6a5/dQPx01lwwRxwW351oSCZI5zwG3Tuqrt3cYkDK -y7uIY2aZWDFhzyYpclXknK2LZZIJdTJf1yF3ICAJlMNM6e90lnkp5E+ciDC5aiBu -FJBgUaxeBCLW9E1RCdl71Uet6ERBkEgF+Nb7W85MCXfTao7deD4W74hXDF4ueJo6 -005qPsnfR+r7MTum+1oKdQJdNpAEBAvVdJ88/hdL1rUvhwvrjMtZm3dz7ICxOOrV -I/SopOYKdzs0oyDnbjqHBKi2BKw+EuIuZG+Xc3sdS8jVzA4esWizOXumOOkl5MM0 -5WxXI8JcXsMjWm982wD7qFkET9puyDe6lSVk/nV6rjVplTYyu4Fd7nCQfkMDjEH1 -GfXrq6+BNCeT4jf6H1UT448OQZCBlj+gLDphg5Mp0fhhVGT+Fl8C1qVRhsSwBWC0 -s5yCaB3L9deYB37hHsd4MNMKBlUZOvd4p5YU6Kda/CaL0J3q1wSd2SgTnCJl04Di -iKdFNCVJCOxmvhd88WS9XiTUGj7gnJnFKpzQcTmYLzFkijnmdwvuSaHynfvd7pJ1 -8J2tbICPqZb0OyUQOMbr5+VLS57DMYvNaNMS+1LuPXYxhAGYnNBx/0CRL1Rc7LQw -X51OdaxfFU5AUx9J8upmbM0iivAk5rb0UvqXyeWvcSD8f/w3fg9fNBD7b7hVW79N -4BnXYghP9LIfPs5C+cd7R+uyLUk0HFrk0+DJjcSM5Npe9mL/Ic+my+HLagqRLbIg -R5p4Vu8oP9el2xZ4es8M2rpnL3C5yYv0lzdFb3txGTJojETfOShLDGcTLZsCDwVG -hiCO7z3GmFcyOpzwDp+tNkZdrBJY/4xJIId2LmNErDNlgVBEaGYYj63Gw2E+RGhL -SPY52ZCmYs3fHbYrJmsxbkP+Jak+kXoUYMZt6LRl2DNRHHCisHo8t7hDy040HxnI -bmgxE6DyC9JXEHZgVC2PpD0ihO+kvwSAhDe/1R4CIRkyCH3iQ3N2lGc76QPi3ggY -1l+crSQ+wyajwOyEiR8G6A9fzE2hgBV+dCWKzV+BNQxHiEomZkzp9WGY5gdHcuYF -d/5yFzT5nxFAAc+KEMQE8nQRYxL8EbCWFjqE4xzWCP4IgQlzxSj2LYcJFh+jnxcW -4r/oLZKEZZGUSNzqKOfZ/37ZXzwAMRH9Az/qUHIyZB6n9L67MRuehiigYTef4c3N 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-rCa73dD4UrFQk6/r2SzW/0kpPd7VCDHYKPhsvj8H9GMOSyH3NxsWtXEIKEW+WmPT -tGk8cniZerhT96aolQYq2xx4kYyJRa8jMHmTDUH0Ar+EQ/MO3BLAW1vbxQ+DStco -CJPdFSS9J0sWfK9BoimaaXT8yYlI3rSzcI5RdvmiJw4J/v4EHAOlkCyRj0NVPC/6 -brg3rUxQF2qtKT7YzS+Kh3O8LWnVlwgMNJbUoF4+Q2xK6hH5bjt+M4xpoEjKoAOS -EmfUsZvCkIt80O73PoIvXOAZay4pp4ry1Ssgdc79+XhIWD9G1jlpDzQ+w4ExZvhK -8NWdZ1R5JeoRoh0pQEPte2BXbZ62oEiK+5et7zvbHgCwWvVHzp2sK0zSFvFIZ8Ti -Og9yOXDXBGDOVW1BDBdgiiyMsxJq/rOAi099VQoZsdCDgmCT51mjvjsQ9HTQV+Y9 -h/oAHVXaU72ogYVQA1kEhzoXAGWz5P11UPh/6HaNircqniVnxK133P5BE4CwE91E -aB29X8Ds8DvxwDB66BGnkiV8k9OkG/qhb+FbFd3gR7f1gUI5LDCaBg54p+5yMv20 -6K7bPREX7+mNd/mz8/JPLtWGsNaTk5mMcyXzztWkX1Jx0SD7vZhj59nXoWLqxzjE -sKC7t9D9vJbccjM+ZZOu0pX5QvGKDd9ve82mV+OR/EaSy8W7nb+yXL1/CFGUbl/+ -7mwehw+R0PULXjFYtFB+HlhwtyNMibnGSA3iaXq25io= -`pragma protect end_protected - -//pragma protect end - - -`resetall -`timescale 1ns/1ps -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -PmlpB/6YO0aYZmLonOSfv1AKI1gSH8MDYymmabRlHFrShbqvDGa8mxE4q7jVthDq -MeTpb7dntYmVLpQ3jrou9qzgE3VzCDgyllo3TuIcQpf8xbi/clZ9EKTPRNrkLHXj -Jn2QVUXy1p5jRGkj8FP9VCUZbrPJDbUrwkO2Q2VtHlAdHQAM6Z7U9pJ6k+4Lt6z1 -rqGgvu8nZroCzTOKDA9a17sB/IvYRCebzdw86ug8kfwFO6z9joWnFo8nHyg56sAc -aAcfkjyAi9uRiIQ3EUPJmFFtDYsOMqGzh3SmruIKWWPaL4HbH8ef7gp6ZFGqR+Wb -scvgrPSCW0tEJhX8tcsUCA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9184 ) -`pragma protect data_block -FGHQV6qyvL9P2mdzMtBf6ysGowZyPSEb8mK2B/uwInbUMlQwqOl1LKarMIzLcVVN -pNXodSwWPs+yWcpFZo1A0q7pR8/KYA9ErUAfBLveXS3xtwJk/69qmW1J86sXrDb9 -EN4a2OGoQhCvs9FITpUsknvW1uSvMAXAgD4mSNXIsLV+HK2T1fKojXZadDHED4s5 -jPKZCPyAzVgfSIYTAPwui22k+hYubEUCNX1nXIqb8gF/2XTI/SW+4xvaRfFTiqw9 -BRJFIE4801ZSr7w05i0MOWzf3ITw7xa0itEPexfmE5ONII12ATMOBzi/9rfKgd42 -CitshmLHG85XD4ioUN1PAlpKWiq+KkqusFB5ApyLjwE1/4t2uQyS/RaCHhf6/p9B -9+v/nueQSjZFT7/LvfUoBEo2zFeiH6g922aX3BGWyXcloUzjn/yMQUBCQ5o9uJLe -18Ghi2Xhxqve/9uMUk247v2rmlwhla/LtkCH3DjnEawWLoK7Yw5V8VB81bug7S7M -uohJ09epc6KDVq5uputtQjBFmHQZ6x43bqNV8/hoAulTXbBwmMIdmsvqpPKZcncO -BwBJ6nxG2FxUoTUazAGsAMybFDRBQ0j5N0OUC4bR6FqeFJUYpGBm+MyNeiJe00UO -8a+yN1RwfwjiNvKy7PmiXw5b7SJxbU+2jA7uhGYy4sGqn+6ikxh/nVbzub50l3+9 -h6ma1i4wCxHu9WHqq46tNj48u8mrMxS2F+Q4VRAby7qGF1u2W+8D68Pe7RJyTtVj -IyKXly5CziAtte/wXJKLh8FQ2N9ZGzO/7/LQMwghsFeNYhg594eF/5EhPtco0SrB -O0o9JJrlsff6becYm7XFmqDAYrEbxjEBjDrthom31OGTz1vSA/kXMNlK5kMjrOyA -nfnOBCNrCB3+ZL4WftGEt9+XM0kMj4y1Y0s/RW+W0zBgUrspNWO5jjX41XDaXPun -4L+Ahmwo0POtjtt8skB8gbkJFk8wY7VwowKfOrHuuH5GQAA50Tiv07qoiLF5rjia -o4L55vE4AZdKaQu2fSaJYFVjzrd1JJyw9EgeatCyPJSJXbBUJB2nyq+2PzjmWzcH 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-wsThh+eO9vgDcf3/01iN52iGWRA9HtquG8Dkbl0LaW+KZslEHAv9hjKCkK/Rhpz6 -RNgrQgjJC0ErECLjkgoIfeFjroBOSmhlYKogIAFpUruS0kTRnjUxZ7PXlHrr8cfg -7loKXmU3NorEezi1B+SgabLkJKPV0L2/Px0LsvsE+MAjqM1fBqCb+GWI9zlEGKMv -hB+EfCw7C0bqVHiK0esOCbhBRd+azsd2gMQy/VkrvLkhyWtvfw//IOO3ngHbz8HK -mck2JQRiKcWB5gWkib1JK1Vp9MWllvVVWiv1q3ucs2G8p03F4VFfv7yd+ERtCauV -2EyrRHQsVLGSBuBRJeECDAJAKoMEF4gekzax9jAyOx2sGqfmwEDb1jL5G/+u1jtU -9Qk4dHKgULI8m05kPzk/PkWwDBQMV9S3FfWjKkrm8xR9ft52kBzAlzs0NzP1O5sz -6ZG1wZdJd9qR5QE4Lm3gaxPvccjdjlGoZH24mwloYWAG2mgXb4hutcoRBINLlkOo -c3Isz3kUwDcdTNryYiDmxkLECtp8g8bNrabmdI1goigD2qwcCqktvWZl8SxtFcnV -WspkIpJhdVSfmzKexGLmdg== -`pragma protect end_protected - -//pragma protect end - - -`resetall -`timescale 1ns/1ps -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -nUxQKBNOPAXm4SMK2ufDYCaxH6chMgD/G9EkTxUt+C4Nt0uAomJL0bJYD4mF8lOC -r95tiqs1UL9IxPtBQ7/tBv0W/JFRZJ/wPbPiqsu4V9ZtWkRNwuwhOdkOe7peQbYK -zj/GKqe/6NnDKvo2Xqr8SF+tE+6MaDB0XilqCHc+dyO0o3AqDAhL7mynjFjvo2j7 -F0v0ToZFohVnUNWznEKxKGU+H0NlmNfYSoUlYleeUiwQo0B/drPTh3EFxzaaGSSm -pPi3nW/4vKGCaEpyX/VJFfaWzNLoaHeq0OqPZ7aGQpV50GLpDMglFlYSca6t4OZR -MdwaEqtceeAjFhWd1AnrWg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7296 ) -`pragma protect data_block -Q6fip9AYrrc6csSM4j0nGbidOqnpUvFllvtr90ruMh3QiH6wgCa3Y1I6FB++ylFh -hIfnz0EzOo0+SG0Wc+s9BtsY+Q1dCChpha1qQ+FWmJwH0ylGnHU/vZF2G+coVnb/ -mnQLB03/zpjBEay172RecdOeH2x7ztWgIzA+bfJDtvnJ8tOYBmwP57I4zENEkq9V -YU834CcpTWctHvMPn9p5bdRWIMD5YGFGw6gENULNdAr1ISPBcDLCwwwDCrccHqo7 -B+7rlFPC/C2v6y6GiZDH8YBP2HfT5BcPJRdo+9HhGDIvUFgdbwiJLAsrctiEFHxo -y/kL3BEz4/CSFMIMIlcpwnBM/JRxCRuNBS3pHTJ0NzxOfP9KyLOduKFzGq5/5XYE -KbWo5Ww+/881aF6xY1qA0bUhMLx4aoU+4JA1Ny8jl/UU63kCqTDtDSg8LvR0bbFa -CHIiDjDyCvsQiIRSD/yOTuAn1/m5ZCYHLTRQo6ZtFb6ov+jrgbPThCEKNmVWJqoJ -3OPNjVnHf4JCP6EOCW4dvJ8jDecKctTqcEQuNgqHQcwggqlUfzM7JKRxyQQMHtCT -ELDN5DUETXncy1HO9hTCODvRAVJ6/gwOZ1/FEzPAnR0Atvq6YyOmPDe8fWO0wRRo -fJ2mCimbWcnDnYRYtUtlBex5f7joH9hc9beZiOJmwnf5Nfds0OvNSs2xlT2hxJEn -OcS371snjjJ+60l+b+qt45RbdwLVWzhEUm7FtaYRqX9b8L0wRYa9EKI6TedvhM6E -A2IhdD90G9eV6mcOQnvoLS4wJFJgHru5Xa/K56U8b7Vef5Sv3Jt4x2Zby1x6Mycq -s3C5qj0yNolPaJaM13SgMyZKf/OXD49EXPRhwQQJeV7/3V44GEjIbCJ49Q0Wskuf -n9jyn00Q9FGxrJReoBKodFy0A85lmBnNqX5Ni70pRh+lUOTnALFX+0veYpFf4CpI -W3vM+z0+WT4lr0zChxnFXDFhWAlkJjtOn8fcMMtMoyg5Jb/8C9oM8FSS6b4+Tqjv -saf8ujF7F+BDbOzswjqZP6cvj/WuIUPiW9MdWmg0FcEIuNFzMQfYciXi4pCc65cF -vgzZcLmiwLxZjQn51VvMjqPgK/gtmLqdLamWVBjIl5DTm0LxwjPsbkssQ/M5yvYV -nUo+Q7QbcnWQkV9R4D4mlLuU28An4OcdJeFRgpq7D3/97Z2IjqsrU3vDV+LDsdn/ -FR2cbyLD2ipf0jsGZbhhNxmfkTvYyYoGdklMGCfNVJDzlW3+AyYJAmE9jcfi5G63 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-Ap7oWVHmy2RSlDtGolQQpvBSvHOmolAP/5IuaPaXN5eyKRkfBk/YeYNtTaiBbNh9 -Ps8hFQjFw/TvZumIZVHY7NT3U5tHvI2ggrjlMkgHrDWGbPtZWVwWdmQwu1EFQUqq -MlI/TXlQZqXa5NC90NDGgBV1Fi9LWQb8KBRQGQI78U+NmnyiMThG6Iy9ROYAe+gW -Q5hTOtvg/PNxLniPcx6ak5ASFxKxwAggikXJnUexFVurxAGKZdiBxIUvdShZwmx/ -iutX1fZy232qr8OGxrv7ekQT3d//R3S94ezYaA9aKGWerGftBpORepKbrEtow10O -Sac1eo2+m4wBx19voN6mxnknfaVqYkkQydwXmWOeN+msSbbCsHOCpxVfWrznj9+A -VEF2g1vF8iYJRtWU9lzUBxSEk51Bra8DbMmvySFSvT0Sc1kz8wAYtGcQmkXkYLjh -AAeDMJkC5DGT9cO87uNe+yZjbtaoMlwTDlMzC6Pg6zjKlG672zB/kV6ay60jqT9Q -Usxy+cqV7FYQct90gsJlVgjx6tpYc2BHoJVz8srifZQygKdLcaMfSalT5NgqKEz8 -Yo5OTpILb1IfcWeM3GH8QI4SAVCRtVyoj8UxBZOMXXXyBp4Av7C9mRqW4YxX0GG7 -4XH60qtENX+q9eqIYQpQ0xqBlyNGJHtML+n07pwhb6G+RD4ZuWSrhfnIBxcc2jm1 -UwdRohaGn5ptVXFoUwzz5Pu41QWk6N2ZUfCosSz2vOojOQo2csahEBd+xhJL7uwV -`pragma protect end_protected - -//pragma protect end - - -`resetall -`timescale 1ns/1ps -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -MItf4LQolnfNNZYJvjTV4ETejF9FWX+Iw4l1AlQF8c/u5UZCDVmqg2Z2l3n+esxQ -tbWXCpsG/kio6VnHwWXHXsEhunA/mY2EAnxUsfL3KKUd4+4eAhtjJdq6aYmG1IAn -eLYlsFV5MOuibkR5Bk4JLcZMSNn6d1XdMUxIAvwj0O5grxxtVAj13Bcun1IXhnp2 -s8I7f+zNaUtQMTYUZNSicjSk7p8QVxCfaTAmwZK5E7qQMcaFvHjPEtG5nv9ne7PD -mQnlHeodgRtKy1OFs3ajfiit9bQRYdPfmBBJurC1Gn53Z+6x9PiMb6wTheXN42U1 -6PnKOGnFskNUTm9yXBibqA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8176 ) -`pragma protect data_block -AkpifhCv11FqdyW3SLOja2cvQGwIgr+vEkQ5XQrx9WBU4WbQPBi5r02VYk/j86Cl -Zkx7XpMYvsHTVC5SL/PRA98jiWoEr4FUfL3DbCS3KygzmxwjF2e64U2t1E2zCwhw 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-26FCC6I8GSYNnxrfwCQpXVcXfO0gG7y7Jk9eT8I4kNzyPAifyyvWJTAP1VfkVXGw -5dPtXyPKVuGKfa+Ie4kSgso4wyFuqY4DcSK/9eETXhdCJ0JcJiAa3SC6mNSQJbSW -EdMjVjOjxDOmI2tMzNVrCarF700Sd7EelcK6Q9Fq0g3/6lYWeq+XLav5Yj2aAuEB -Yftoo8DW41HDqmpgZj/tUg== -`pragma protect end_protected - -//pragma protect end - - -`resetall -`timescale 1ns/1ps -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IbSG7Grboq2nZ104ab+a/+lBKvy3RnVPf91eIPRpwQOtsDLKLPZ1ylPWfu5llh+u -0HiEpTDTBNXfL5Z/Bw0JVPbF658H8g4lvM2q35TW/+HM4h3PPwAG+H8j7XJ46HjA -QUI5/vpzx1W069wbVAKK9JZGH/SBrS0FKlV7pupYYQoUWwKULicdTyUn2enKQF1T -B/+KU8whV5QuENrwXYZ4JGl/WkO/WhC8xWW3G6NwnoxUenpB3Gzg/KsaekaN2GhI -FD3esESRqJsvtSUJRBOwm+QdjdhIm+pkvJq5eptgpqANXyyO6YVIJ54bKK4cCmbY -UuWQyYsM4xa1ficMoB6TIA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7280 ) -`pragma protect data_block -naLN5qhzy4XXLyb6zLajhcevS11hu/SfzYR7GfnloyPaUYlRclKMhyZ9F1AZraFl -BuymX3VA5Tv7D02ejw4vpgo+LCyJxGhxIE/esj+Hl5mTk/5s+dHeGIYwCi7DH9N0 -e0H9wNHRryN0kKnj4LVtJPuI65dRfU6N2p6aIIoBGj+fJva041sfAcE0StR0ijbV -pmzOxPNeIuaylF5Hwbs28IHMNnmJUj/2EjzStsIxaozgzwvHkGv0ldUgqSBfVla8 -9fEOsq9yjC179N5onPmsDD62CmaSgUoGzKl14irUndtToyHC+6+NjkSP7jABqQgU -+dE6c5sKAJM5EpxOHZZOQXEhAciZ+8zqwIPzsotXAb0AxDcW1dc7S9QJLEpPi4jA -Mbg0f0w18K7IVTpG5/Yt7iIMxaKaPuw8ez65cf6CdhVP2IdSzFvS9/MOieSiM16x -yRFmQQkzUfdPoWwH+uRPjZgqy8N+Hr11bbla1nUTL2E3C0w2tIi9U6R8iAbE2A3F -94CckZZor6nzBvidleuD+F2Vai2V/4Uh3YX145Pp4+r1KhnnT4ZMFbXb+n8I8fRn -dg9rpH0wotOJ9eREBeDWZe/lGQ838d/njGilvK1azurlR3e3jZowtlU/q/2d8m7G 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-KjRloh4BS4wIq0dNhblYSSuKj9S7kGeoQlstd1tbvLoS6S4CzrbdRwL0LlRicQau -6GywrhpkJpPMVypS7xEVPGvPK1bGfp+y1i9lJ77YmzWbAzrl0a84DCGgAjAF0ZtT -jObPhfdXNOEvo8YYwaCRscnU1xHaZWUuX/F96ej6bR0sGdM4sGyySYOH0gMJQAQ5 -+ft06ZZ/rRFAovTbZa8tV/LrZNspwjkjILRD2rw9jkKKP1BuDFLusATMDXAzeySk -05gSIfnpHz566yR7/yurZljJ1Owfm1FHHGZCLD6ecwoaKcvpSlXTiTnUvSDmel+i -iaJNNOIqcOAoP4PZ9DB1HgWqvc77FR2qlM35zH5IoSWg1VVN9f5ZS+wPwo8zRXru -H+ywdu++A8khD6Z6ukzkrKiDAbwjGxzwOqPayzImo/g= -`pragma protect end_protected - -//pragma protect end - - -`resetall -`timescale 1ns/1ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -Xm1S9sj1JuCixXxxRRYRKD14QoS3afZKjplPN6ZSLQnAvIon2j7qx5mq8XGsgaSS -IEzaBn837INyfSUXRKCDbOHB6vgrTaXMb6v0UzxxzPWS+b1IVkFQr8FAS35BRCmT -NbIAI/Yorvx0WO3MSnUTRRpDBG8iOn/eVIjECdf9yJE/4mpgec+WdTcvzPWMSgUN -AC41MmhJ+dYzesMt9m+NxO6FhP6/22rXjdUpKCdKZCyCQFtmRGfykI7AbREfU4zh -oGDWnkWlKck0HShR7nAecXqLfG7+Gq5YF7MGzZ2f7KqpVXIzMVxQ015P2LWLKD0Q -W1FNsNnFrHW1pzexa7KCDQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 688 ) -`pragma protect data_block -d9NgTXPSU17ADKmxgIGRfmNOqDVkC3xL8aQNJSfELvwqHjM12d0BwF921Y4NSrAB -2hny08w3bwVwZmMrG4mWIOg4TJhZFU8abxx16JZIuWDoFZArp2nzhXyunUk20E18 -DjbINy2UJjOconqd57OAgrFbkfE1sjygBNKBfNiWruHnc9ACTZgjNP4kMMKYnP4Q -+C7F9/Xpq93riPzugPgorK6JMDDO0j484pDigDe2pslBOviHjuiG1PusCsYQjS4k -8xyUzI+IMaFD1o2IH2CaHTBym+SFlLR4MF6uh+o2fsJ8sDM4MRnxJqfeQlsbmGsM -JEiYRkbaUze/Ftjp4hhnVIQwlkRQnqhKk2wI3RrFo3wNUKHuEZ9Jt+zFEI8VBUxU -xG5JozZ1GvO3bl3emvy0eqcjgNDycd+VzaGXIFIfkPyFI6t7a+VoPPWd5L5OY+E8 -CxORS71knWP3SH21cw/7DBok2mmAPRx6gM4RSmpLWGBILWNMdDEig5Cap21OX7kW -rNGUsqAyTBZZcRbvvubH7ON7IFuJqyGi7KCvM8q0j7GoWeJ66fcn0otjGNjPz3VJ -m2oVkFMjqkHqzDURgMpzkkAY7P9tpeLJEnt/ETbNwEp/epgl5QwjjNrig/HP37yK -t/hyIpWkFjWEjE2Es8U5/qbIaeYOGB3dHbMO+5cV6r8NfqB2hY3HivwDXVpI7pyl -vswOsuKJk9+V0f0jzzr2T2IFXBzer5qGpQhtGTugdfzMu+VsQMEDZWYh9+Ui0PSk -fQ25ZrSBkxXSck2Esed9zLN7WZvAEIeH84e9uGqHV73TJaW8pm6B9uc6S1kz8h2f -JVb0WcSJCfMoycYsEStOZgOpE1mZjhqG24gnM8NYZ1TlgrGwh9Z4kqhhlooetldC -cHL/fnhdSq7YRzoZsgU1lg== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YCP7u1cObVZvbCw+OVJy7l9oTBWleoq9pu7Q1OQPRSS0YTyAEOS46qp9gwzKKhwN -0zR5GV65ytGjNdr4ypFsh/u1ryyP+Xi25y1v0IaneY13gDBicykWGwlQqUcNiJM5 -hpa+wkVEQE+opumFfZGNlYO6XWC6VPewxzGFLG0jgTqLSxKckpAMOhtJRe9QDDID -1Ogm7c98iqLCmdne915Er6r79LaO2eiQ4skhTnXdhNl4fSnifNNJAOHRzuLqb3Or -nv8PDAzc22u35tJPGB2x/4lyeoh4L4sOlbn1xCyk/GoTqJaaB+cKDb6CkcwK6BMD -W/DKlLnHCsJtQqRpnPB8OA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6880 ) -`pragma protect data_block -tIJMLPz+Es2zE44XNEZaphc3xNIDE0DWrwDXZwanlE4+DEu0gwUKVHaIHCHiYaP/ -+iL7I0zAyRuQCAYC7iplK/3+YeKHiT4Rf8qdVORZqU8NFdayBFfx5par1YcSopM3 -bwf7Sl+ysL7y7Z12IStzoXWEGzwTE8jL43T4Oy4/u8lej7XbKcPuNubOiSKyctvA -2bWWOqRFB3kwb9WZzgQnEXqu/cYVnTtMg40x/46cEFJ42tIQ3hpv4APDzvHQLVzn -cER4PuwnsgjGp49n4m/qHNx9BSP/cod1d8P658Uwq7z8WRnxYqRmFu62VLtKSOjc -j+4XUh6EbulwKRRG5BKG4e6ke9CK83GQjZvygRfGW7aSBNccDfvAtWBU8Fdfmclq -NNgvvyUfsi8DPNX2Vk9qSwGzq8yJxXZWHs6Me71b+bH66amBd11yUslxiophwCRk -oM5WRdtZDJs6D6ochsv62c5qqJftPE9CrhzHOOKc4qFDOeg29Vup3LAdf/v31Qxi -8GO9U84yOmDDbniVOPBuVTntcb2ftAFJDfJQx/XPcVY9vqs2e98imCJsi1fL4eBd -KVwMT2ut6Uwle5BGNMsAvvUPMud7ujCNRKpjDJ9GN/cQKzP9/wWJkTMQ+K4qkGRw -VJ7K074M/b6spLgoopn4Yi1jh9bhn7lOr+/zKB0wsI3RtPlabUV3VNdnqggZ2mwa -Za3UOitMGGujkSFoJyTWA5GqHGK5TpRgk01hTOgLdxYgwWFci96Spj8CHok+1ZZb -nKbPIIRLM98EPTl+1QgrWGwBmLoPjq1NqIteySNzRcCd9wcmQ+0lTFM1la/lMwed -sbEueU28y6ClLbFDfqyLnlHr7LASyc11OAeXl8H9QV59b6wkUL32R6YegLwXUPCU -u1Cmv34bNPMhtoWePJ1BmJS62YxMeuy/OYNeVugzJiz0fU7D4GbAN8063xaoAlzV -YqihWNDLMAITg0SA+2Uc8yZVapOQ3EQqlBgiO1qRKmyQhCM2FqJ8R/J2SjNppicZ -fImEqq2DMC/TthwdWwtFhtR/zVFXIbibvusZP3U+UlXkBgAu0tOYl9N7IDylXJUL -4jsJrL9i8mTBrOOnaCM3ruEagjLBcyCAIhKgrJRJLxYLUVVI59kfZdOAHu9hANzz -XadvsYv2SgrJEWvb7pM6cYSoy61wvaI/dCa+m2MFaCef/Xuj+cD2GFsXKJCJV30j -ZMjm+EBMpgrzPkk0wzwV8eIT35yipmZPuMpVqMQJb4VLapzIhqXotEL7VbLwVbov -IdWy7gV8zblmMkzmb1cer7UgFu3c5Uelk/l+ynKmqFsdYeoBsNpJj/tXTJzyHn3e -PFMxvO4wX5UalH1uK++ygjja04oZt378+eEeRbikMwWm+EWvQQqCXGD1il0cj7X+ -d1sf0WR7sMIyMzL8ZMY/EfqNAUYDHgHTGohRaMg248Cz2gcb8KLSitxnga/VWu+2 -AtAEjB6C0sWfzPLaM2HwW4CAo3RAIOftC8ltT9pqjWsmrfvZhNEuTvbS92bgDyz4 -wCKX8HQdWemibAot+dQYI2WimGhq6WEYrfvQKPCZnYyLGWFTJUETgiN5+1K1H0JP -+gO9yWE7MnRDfXEm4pxTvLvVtu/AUSIgdOPkekHEElbMmBRpOQukIkduyraCUz+Q -wyRb0j1lkFckUK8egEdcJ5Ot6RPLx840zHkapofON8QHlB8oKJfQ1Ii5Fr3PN2BZ -I6yk2IsDQZpJgxm5gS/norXnz6CX8ABOe9gYhcSNMfOYXKEIsxkHxy+K1x5HkQAj -TyEagU56d2T4runPfI/Upgx3JztvPS0ui7/5yHikqgwnHHwcZiFhgELkTzDhSkJ4 -D51SlOQH+wdXreBpu5+uBqPMHlYxuXOiWIL9kagYYABDd39MDkx9OvoXmZ8d8ks2 -Ijs17qWnZ+MxpdurVAwQleVwXg5JHJi3tN2oCYgSB0EJ1jCujzHJ28GSjkvsTzzf -KytGWm4SH9RbhKZtmUtDOY2DGeuvtlH/ournvYWEfmnyNwbICGApeLRJ1VSaggY2 -NfuVA2trp/4+r0Zjfch7AsmmXArJy1bJK+GhKOky3Bu+KdWp3j+txXg0bG4haiWm -viedcLoQAY464HWysJHol292x+48kkiCN9zk6RvpHGhJFv9TbSIrIIlpiUiIt6KX -MOPKy/RmE8W88CpzolWB9ACo3G/rXfbQX5rkPdBvnV0vRxXLC5vYs+SDPqg5y7sm -4zCr/661kfV7F0lLZIA7rMSbdkjBNEWYoHKfOqIqBVJPmEBRbamge3i9fZuDi4y1 -aSmZrCWiCVzLM0mziv8TLtiIz0b07zkwWjiM1CTi9hJC4aXQJYbDYYa1yjW87+3a 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-WODE0xHvYv47l2Bxuupl5rs4E6CkBwxzY/CVY9FmifLcNdf5PsIcnx9zaxOA6iIo -NlEn4zFRz9DzC1X31AcUTxlF/rTNO+4vjkgFMHW+dM/BRX8FK7PiPBvQXornhQRQ -pP4dwx7wwomhAc7ywgzmODI4bhJHJj5w+1fRTE7aGhH4A2/u0shgz+EHQ1cPQukf -AZEURX0ay7ckNC47IIbeQ5vNRqxEdvv5CmxHbF983tEXmIwizM5lhP0WZ7/23hWC -2wVU6fGY7Bq0RP+23KCLp3cCPLLzBCC1csCY1i4pXVLr9Vtzi2E885/kt94wPuEm -Oq0DJ3wjzHvO03tiQvbo729zMY4AMBoH/Cyq7c2U8ZvPuB4NN+tdHMZRRYUlWqpf -yjZV7u+3sTqvzmLKjl98KyOcyHhj+0lxuqu9skR87lC/whL8c8ydlAj8tsjdNFGZ -XyOLphHHwpYsb2VxT85BlWHjmmNYzUqLl324bjtlnXHXvLpL5Xp359KxJgBx3w+N -dxXOSmpWi8X6XUSExPTGVDt0qfmWmxmedG+V9zvH5p9tHopBskZaosC6gqQoM9lj -Wq94fNIuRsTDqluCOCn50/IGsM79dakdbEoPsvInlM26XQMbOGQnfa1JfvE/qaT/ -Hb+U0VFpTG109vWMB9I3uE2IM3QFqOxurdpyGzWmGExAAdJEgquuxaUKchtRo0/h -swzA091pG9w8snK80AnIuTUE6WD1JJ0YM0q3Fj4i3Ucwhi7wzKaZLcei9C4KH8ak -RBErex4h7NxRySZGdmyj9r32hSUqeF9pdGE+AyXhCY9loV/0+IPQEBRw7dyS+kqu -k1oDCjQPIXNZSteVg2NEq9Ara+Nr5i8qBNEwCcbJfze3RwRRUJHfHUYZZv5Bw/Ma -UcqJGYuFA0TQxK2fwwr32E+9qtHQB6KabDjkfXkxos34RSOE4PuUwRP+Jlnp9LJj -P2uBo+YOxrlPfKLgavKoB+66pJqqBFxpkN2UjAls4A++BpHqrrD3GinOHtejw6LT -S2jcAZTRRhYfI2g/A6k3ew== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -UHE03qwRSxH7Y3SoeZzOc2GpMslhCPTTv2Gw5RwahMzvF3iwatslvcgDdd8fI2BD -Dlu1c84ye8ZtLWKjSb7N3GsBoo3WL36AoYpYmyVW+heegZ8mZ46dNYCnxJYxoED7 -IvzgWWoOU2Bm2YgFxPOT2mKantYJ/ATXd8bVM09X+TEBE0e71DYDwhKvq3zCRpBI -PRftlHhH8DbF/MWedexxU6i66X/9S2mAQwPN4YRBCOf/c7OJ/Ole/Zpf+Dnwo9qX -aJp6T1LTtodRLhqdPlIWFk0iFCi1UWfs2NSsVGEcn05HspdOy/Fp5sIeXIK72cob -oDG+vayEozPxF4e7YU1aAw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7968 ) -`pragma protect data_block -45VSHw6COPRciAp4YlIWeDNBlQFLxnoaBL7tEnrZqsDFxRJbl/F47dG5u/ha5AyD -xPbkq3jFeg3hEfPkniIXtKce2gZuH0X/X47X091eDfUgjgAJ18QpbQHNVovaB6+J -gKlnY6U28bOx4J8kuMnn69Ghg/4Uz9X/v5rVNiN5kDhYBs+nIO7aq1J3DvF0t6qA -AtRQOBAcFt0N7HHLvM0HP7NtjuyEk0LVFgvLnisDko7YC7HI0jKBgYG3YtVb9p0h -lgW89Uki861E0g5j7eKUfCHPQubEtpWo+x0QnI8BIecVowCTHC7ibLqBKbU/FbIG -EqtoCQ90d73V4sF0jRI6zT1Rvg9rNQSNg1xAOPB1oE8KJF/A9LyvPxPrCbvb5arT -luHxhRlMXtAfqwlUTh2BosyFNDSF3sKP9wR3VZeXh/ea5l8jOKdtHpDFQJIDLYrM -UhJRlsBM/cj2BXD1uMn5W8cUi+DlRcDrq9M0/UG0QCek+hGRRa5h9fcM82L2bVNC -CJHanBqB5f3Q3ysiPu3BOy7H/j9SFrerpYXVuFLUoy2oYnv8qf18UP6IsRJy4XDc -F02jGCHEpqn2itSCAmkorsQ9B2EiNL7qJnR2w8YoWbuz1qPL0LGoHmwAgHMJEW7z -BAp0+OBwj5FYAKteI3f12CTEriE1CxjzzUBHrCGyHBfpKe+BSmt1dFzsmYufK03b -xRGl6rwHv5qfNTvL6cZunfmLx9KLo0dopahxryVi4eCU9RMmSGdVEuthAG49NSAV -JU1nFyXQg5A2H2+pzRxwS953RYWH8zyNlVzpEu3coScuJRpB3sCLYq34eEWYpC0M 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-0CIIGfg5CvVm6rNRz9S9zJS20Om8ZrbkfL5hmXoDL2nq4C11r5d2m3Yyqrpl9hqE -7dRmAp9EHx+rGT77Rr5z1h+jXtFWwqhn5hvn+BmCFYUQGo3JL1bDnk7E6g4gHy0m -OgKHiCFwUHWYiLhR9afzNPuYKfydhjxTfz/fOPli2WJxK4O6mG4J3vXGJ7JBRTWv -xb+pr0HqR5huMNvVLLzvxUq9uEg0+IhY5sZj8cNV+NYnYPgBK9XIQYgDLu+9d91Q -UK7z8oo1M2ieR1EHxEEqz1Je/byjkjzXh1QTclKaPYJCqSzdG0ei3gs3RQHYqcri -ibwKPMEx/zwiRHhJ8js90S+Utw/inYdTDbBXhf/2jANGbWH53M+L+zwLU9JPUgzf -SKUqZomlgwzYoitnSwX3OWGLZQzC8KDDAh2tr9j+s8a4NwsPZtoMRibp8gl4jVwM -VQp3c19CrrLraOhkbCSCM5M03WSaUNHCu3X0hC6nRJUd+OI+vnHluU+wQ745UlPZ -mQySnl/aW9rjBoXpjGhDzfdmUOQ2X3MPnGyVYKZ/0THt01o4Yse9w4RbX8S0iTd/ -+fIma28pu0HIj4CytbffI5DCdRI9BP/A5j7nNnp/xZYfmU2J0U7N5+X8z+YZDGdr -KgyYIMwuVSWTgWA80mtGmlauVjBRFoM9QrFB5PlIQzuK9TzsMlzqbbt9CpYhwxd8 -20GJ62/I4tfnyAtSesj3Vxsmh2CcP8jncGmsswSacE5PjQ0OBbM0JRQzuqNS5fLr -cVpGYGEG5fOCPUmBdaXsR6ck36TM0W5yIX8cyKHjoGe7X6FtrNvTYzgxjhprlXdt -z+9H7hh4/n5TuFXCD/m3VxukTolCF4eThGusLF50AcvHh9LIpefTtYIKTDHyLK2I -7FPJZ/MCytqRTwcKxk3gdI2PM/hnHX3yS0IAmzjhYVhbKC6HulkPO4bKmaP1aEcB -iIftyAbivNxeZb37AmrSU9ongkc0rxk/63IKi/AJY5Mq0Op1RkJpt6TGQmfmgrbI -txdPUJ8EbETX/kEN1zDsEc9TNTkI9GTqPzpFtMbW9wL0Grce22pW+0c9teCkFqyZ -WCG5wKnmiQpeAVv1VHpYwdEOzjJv0UbAyfG8kRoSOC/TgG1aFA4o+/XW0wpw8Xhw -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -Z0bYUsBqE8947zdgGWPpqFrvmEzhq04RKLUN28rQ1wkTNc3p6zFpUJeEKPaQ9Q5V -tCYl0NaYT5qvQhZvCzl+x/jJ8wBpv9J3+d7GNb7nnUIy/NMuLGEslilaFQlBW3Jx -JcuDPbbVPZh2va/NooKz+kXCo82BfGYEKaWptjDHUpp3QHpOXlNpyho/A0yFqBSM -AejUEZks6PR4s5Chf6BKcUmh7/XmEjgEZW9NnltYPxumu4dD/IWfrOuVW8f8xwYR -Z97hT01NAlA3daomFvT8ZWfWFTypxCaR6SyOEXBxs3X3UloqjzT2lLIga9ZeNxnJ -dpGd3a3KAPmgul1Fz5Mtwg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 816 ) -`pragma protect data_block -Pf/yNaDaWKTTpcOJbNx90t35XxwYm/d9wJOyWLKd5c80p1TKmFatZvMBgclEa4wm -8M2luNdoyRCXtgCXi50UFmvDCdnKyfDg4RmdAGBqvP+DQXzbgq0r8Hcu3R2c3wRN -dTOMqbGACK9r8AnAP6JVOPyWpeKNQ6fdAs0PxUHD/zDAy3eIY8xzpFkIH0QIw5Vd -zg3YQ3fLlhg/CMJOliQARr+M0e286QIKm3zg4VEiVvBGJWAVCaM35O9a9Zk+yH6l -or2juNa5ufSiR0AWyOVS6UPlrT5E3bIcuwEhZa9K8mocpS8sd99uS3QYwilx6wTX -xpw3po/K6CcTc2xSIRZuGtIoDL7Nxa2aWlsl/pc2iho2+Y/HYDZThrmd7tw0XvFJ -PtsreaARZHeJ7ANRzyrlQMdPmAvHCT4CjKIiyVKvcbgFUw7D2hMP/688qBFJwEPf -OCQsn9Np7TGUpNWt6QG2R6M66lkyfaWYNx3vhn2qGO40/el4dpXgD1AlrDUgBuRu -ZpBP0qIOOvsxghto0MOUaTuj3+Q/4iCLSc0dJ6d5o2j8sxz0klLbzDJySqdohJrA -41mUZUvEZ4JN/flYe1TRCCHEdSk8h+KkvQfDqqJp/QDS7siyLQzm1JyvTKhFo8xu -9buiNusDvnLILyoCW98w5kFDRf+zHhWKN73zOeHGQKfR0aO7fX3pxXLsEwLhK54b -Wir5u7+9pv3n3v7469KZUa6zWzkjWcFjOHxaYA6DuURi4Smns05T0Y0rMtc8FSbF -iUZCA5mPFRKviK+6VE2SsjuGkMCA2zm8qz9z6Vgh9t9Njkr2HoPnzquYQg3c58Kl -iGHWXfuurDXwM/EkFVUF85ojRFGfXLF7sD1V5UNJYnKp4aQBM/8+TZkMB7aADvGS -/pmGmD4xlwLYjDOWgp/7091/kTLRZSLPoq1OEcfO6Z5VqaAnDiL61UTbl3/DLjMh -cH/jr8xaYKd9boxsCL5d/mSuu+iFFlVTYcZLhaoa8P4MYLRW2eaOjjuciNYperOb -CgHc+0M97uB37gtHJWr/eMavucWdrh9vHieFTjsQ/ov7ZK9++h/m3x0K9faH7SvB -`pragma protect end_protected - -//pragma protect end - - -`resetall -`timescale 1ns/1ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YgWaHP1VVrn8q56faPuNrQinWLe/8n2gJ9/4MU4MDUiGnK0PUfYovpXAmNkrRzRs -VtwlC6Jj7InRw6kd0R+Y+eTMlcbioFK/qAxJSWfvQxCOPX8d7BT5wuWQFVsUoS+M -oh+4OFFo4X9aa0mI7PEcrjEhR0n13PG73T68EVWvHz7FFgytscWtG8kwqOSOXmav -jLPII6xmu7YPzZm/HiNsnMvvViuwT5aJb2CnGBw6n76GIMmghRK9Q0a/Qiylcaxx -teyYIGLKW29sOz3rZ/ENSLo010LeR2MXNKrLgL+PIW6y4v/FQ362XfI1qYw2kVQm -jpzkoevv37iwQEH6GlMwgg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 480 ) -`pragma protect data_block -Dd6JpxWofdheIkHFwrjiQ2TUBTsSrHi5N4DZxL5ImyVO0a8v8bX+ETlfPNZUE+8r -SwuVh8rOFSay7+0pb14JXUqp+DkrtVuid+Hu0E/AF2LxkH8xuI4mtxHP4wpCkof+ -XA15pr/1OIO2oas5XoAkb3d4JYntYFFoODk4+Ry6tArSi0pQCUAbp2xlJccIS+7g -+yQ1oXZ31XRzEQ5dk0k3B51+5qfFF+dKhPCH/Df5via4wF9ZESfu2YPZlRfXdmiL -yy9HzqqqDPfcuBtnGBqdYg7E+a8JV3eJr31WINkRjB466nVEkWlBw8tBpYiaDqZo -u0czdrGrPhk/G0pUqGMW9g8fhtSf8+oKfEhbK/gLqlQ78J4aXdv53kni1ylyInQ3 -wV2jwkio/Mz4dx3QJbRxdjGpui22vVZ2a5YkBVEL4E2xARB/u4I0mhdtWP5+FIhJ -TeOjuvTS4qw9jLUgJTmvsHnAjDsfwZzqa+7FQRfiR63Y073cnUHmB0H9CT2EuM8S -Wb0yYNeBSqFL2A2zJNIj6ruwaUeT90eIoNB2hglHXBAkRfqiZM0hdbbuk/CcAjuz -XD31yYRsEQXfcMmJ9P647dvYwdzECtBFUlP/DaczaapgIKvsnSArzKsq6691veHZ -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -mUjzSHf+uYPqL1n4IVyPVci4v0CrLYmPDHLV4awO61biHqpmrq1JTFqZBQseHQkH -6cJcU4LYtSNM3V7yBbMqQgr+2S6WRbMzWLDk7oaYThKqu4qR52i/o1CLubg6qn1I -ZFZY4okKZs8sbexheNKJFEH4N3Wx6tgv6nV7d6h7M2htuzLclk8xDgldmWT/3b+p -G1LAS8Dq6Ll9eTtFx1t7AYLaCpaSUJfGQejrDqvXmTyUs09j8PYV+q84M8ow856B -r6VT7J4TsQhul/FwXdFtG3r6+gx0T6HnCq6M0DDmeoz7gLnekNXKa5FMEstTWXIl -ctxitcmi7/Z40dajl21emA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 816 ) -`pragma protect data_block -VLstfW6D5LEE7ZexczR1r7H5DG8rlhP4PiND05BP4I4l0Z+YIQHuCADYxsh6LEn4 -hfTsh68yilbNO1RYyv5EU2gjhG1upfVQG11+GG4wJ+ebrmO38+XL7NE4vKSi/uq1 -/FlhR19oRl1Xje3fr8W9zaMTqhu4zTBn09eWOORepwS4fMkhXDRdfK0Lcj6cfR32 -DajYlFXlce2ky2kjndjmYy4p+Ii2I3SMM253IdlwVcL/vDCxsPGhRjM1BbXXs3Rl -Fg0A1IZPwQbTFdpIK1uNMjbEGfX1Rd1Axz2dzVQIpouDD7GKfL7fcDbknBi8ax72 -z5dSqevuYtuAYkXME8N35J8kSEm+PDHri4PAQn+PTZ7SlAAdwGoCshfev9Wh0FuA -6dBHNnp1Xolo5hgBnLEpwk86eMfpCEmS2SOKT+PtQzbH/9ybtCy9cxyeQa94puNB -pqLt2Yz6ZADpH7a1qHCSWk0R0KsH3G28FWaDVmx3hMo3v1hO69SSL8MaDkY9VaSy -LeByRe8Ocunna3yDiT+ak3nldI6eEkox1A7a7fzP0wr/izyUB1nnoDUKTBTpUjQs -imcM6DvZ12xUdevxNNDoT35XfdHilBxnXNUHukbkfKKa9DgELM763LGt50La05JD -2DRS5asmgZUt3P6om/SMA5wupzfyGwJ1sD64NGeXn+9UY+o3kmQb1PFd3ojnGCSs -Yk09kJiIMVT/Fvaz5kh7T3Fwq4fW54zRwQvkbBzHW0g4v3hQ14CKOY5ay57C1KPA -Xd/gjm3erxvE5KRquwl9qBbPG5HXLdKGYsBkeHO2syi4KI8RepNnQMko2IFoQf3U -Dj4vIBHKC/ghUO9ivy4/445hL4JU9HiC1bFkmP2Ojg6j5gR++CI92d6VcPwzsR7+ -5Pan2unlYw3kppVlIX9wgI8lfRtiM5zHhTFf7akTXgwmzfV+L4QWrKzkjoNu56Lm -znT7+JDPsManGGeE+DsdMT6vcBDhrOC0AI82jEGnniFeT6Ftj/Mw9J+x9J8c3/z2 -LME6fkFQf6gsTUIeBwvpixHwCM2oIjWDkASPIl9AXmSnqjAWrFqtI7TuJfWIkx7I -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -Ye1kA25/n0nWVEkXGZy9SyuUjU4Y6TvdjEyZxdHOYyJqvaDK62VmGBEQpH39t1uf -G8L8coe+k7Rady+4qr3L1go2bL3nKa6Zs0iyCYjP+pJkLJCd8FNBNVuiXjHTLmaA -iCbjJ2285yoEhYQ48PIBTgBPoG68Vwof5V2YLee39KzlRpYFRuoW4j5BotITbxop -M9I7g2lHQpoxnmuMjZUaCRZOpg9YTqzaJ9bGFkZj/vOS+iLMgBpS8FDmw0+JzJgy -murJ26ZaRXJi9Kd6iHqxOXbae4vBRW9ICST2GFrNJ80p3zPkYroT+xnxhhHDUHEM -CifzZu0QanpCfZ2ZIgURxA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) -`pragma protect data_block -Garu6n66/nHyqmePOZzFG3PDA8QRaG7IaDod4zrXzSsO6ogd5o2PVUPNh5VMNGy9 -77oznQYEYGBW9IuZ9nDC/aq3FUmblLd4hWpjknTruUObUXBgYXaE6zMd3KjLtiM/ -4HMFuoRnCWnZyu3P7Dg3/DTIzYgrY25ZiQvg32jyrQBc7JVQX/Y/E9XSYLCAbBVL -oMLOlqe2q4buUzSavBhEQxxg+mbrCBeF0D+HkAv64VjUwYTLcq3cmDHG2FPNTcAt -4q16s7PqBBLVN0zu5nDAjR1odHpOwf9+2aNSHbAnCOf9vIs6plPeaJ2dTcGMnzbK -A5f0/sGUSCm6rerxL+40kvFbQNZwTBe5oCNzi50Qo3p+tlJJpUfWIE5Adfxd+5El -xm8NVIZsarHxpOQCmEJoAekwXHtguYTU/JAdEjvQeqV6yttJ21Cw/xpCXCdayaIc -w6rPPRuNOi4jGbQOlrqGkXDjaNXicd1qbCvv1pKKg/gG7bxQ140/0q0DMpRXbhL1 -82sVECjdRMV+eMCmK6hxiPDwgzUqCXGPZLwXrbnTZJ7jX6cJwpVEMXGI4IsKAqju -2BwaPCYMXPw6PxIDLs1j478nZUi7oBJGYOOT2sMI17gE5y6VHQFR9o1wPVU7QASv -/np7nqSaSEOdq3ayYfKG5YFEKesSD/5vEJS5OQqcVIqiERMhmo5ek+IugLUgDcpM -YKz8V3KZMPR+yrc59mMTBV6omcWLEB8RsejTADaKvILD3uOjHW/dWZcNe2d6e2cy -bkRCVUgodXyLhoZMiwcEovjMdfclnV+xESfrCRfBgKsyf5gIqq61T1FbHB0YEfb7 -1yEc9Kyl2Ysnj5J2UuoPhMwHx8yIwpKkCj8B9oTig0SlacnFmVs3gek9gm2LZ3Jc -zo2OPHngZcEwvgZK6/2dn+uK8ZzMQ0UDsDvuJ0kBG75cn7fdNMuVhcTJXQC6qyHZ -QHtyBoqt8Rcxj5wSb7yZRtcjINE0SIOeBzjTIAO8W14D7iWr9ASUKE/eEoXi+DJB -AEYJrIaAE/b5EcxHDXxmemU/KfB4mXbqifqCoJwd/bYxgrv0QaFsLcEvpvEgHGU3 -rg4digLRvmw330qRA7Vl2+XXE4VpcCAn7zYyk1/e1kqY3Auogqvv05f291LQ/PqH -coKVN1Jb9PwuZHxREjU2Ef/N8Vjne+33IiSVPP8V6BYUaeNTK2X9yd/r9VrknpGW -OwGqdheLqFABvI/5/pXuBh6qGxsZu/O6nHZtNCGIz+A9jF8sJ4FYvcWIQB1ZGHSU -aWeUO6EQrGl5iXv6L2n3IzhAlibOo5LUx4LlGtmAgSF1fcGw8/g59TjYE/XF0RIX -MuKrd6LkKTzcQwP0i1dsZV8POnyjddy0bDlKe136KYMAoBEJaGpTxl3fTFAwdnJo -lKypD9As61wWh/RvfvEzFepl74afSLx0hp20ap18naHyaTNX8iSbnRhderywFXGg -tNbBqygju/E8tSi6bAtMg8UxnKIiHRqZTfXvXeXywzxg+6Zu3IMJjB7ejZ+wROAy -W2qqvT2xIAKnTESeVYdebjIaF4Akjhn55d+fCKjLCcjtiYSEvH+8/YwEq1NsCe2v -BqPUcQnpIhQQ3h1+q3xgQxu9izSvSoMfnzcA0XJbnLEvjLXL/LNkEPygUO1vXpBd -ovxP89b2JvD5Yj8TlnrPd2zVXpGLizuYbiTkL+eMAIkWqGCeuxFjPdyFnu/ecPoT -v4xeadWKjrntjRyty43Ir8w55U9lL8t4uXf6pNvAnpkklklowO/KXOGYT/VsStj1 -k2hSgN8ODWKbf44Zvqq2OyMFjqg8Pll/Iz3UgvbGll4c9mdwvTsZS00etus7U9BK -X7o+9rt1SSr4jf4JfYpl6M07nDaFwFGpwO/G1oJ++sx6C/iiInH8tvIw2m63aPob -DagCnY9qhhMIsvfWQl99bHuRiajikI81oQGPCZda3m/guOv3aEzat9njTPuk20SG -RL4TSWqHRiL7aJm9QG57LjyeCSXKS6A97pbPXnNDaoWRkxpXTbM1EG2WQVxidS1P -tCgpf/HR8z39GbDT6O7uEirisfd6YS0r0PRYEGEKzSOIfH/sX0RU7SRiDz2t/EPA -BI+rdXHZWziUI/CqkUJnnEXjkIx78TvcJrgbyY//FENn8hw1K7ylBbHzIWrtbYRP -kyIFCE2HDgHg4oNEX3RzyZbeJgsPiz3gq9ZCH1A44K+YFDJeN1oadbFQ3ulpu1Bu -5ASwlCWwro6xmU7lnN4ICbg9lFnzd+XCmKSpzh7nM3OSDdReJ+lIxOiS5WQjVGyt -C07oNXUo/+fnvTG3hyoimK48X/3LLef1LKIl781mNlwEvrkmRDhKFtSYTFikH9GC -qreMKzZkYV6jV+/QN8t38WsgH6ggI0W3hBG3Ss689xQV6ZURLAAswSyqACD8IJGU -EZ0Mya4MZgvCLnwJAJvIYFxaaVgkNXMQPBa+KMtZ+w+dsNiJmT+OS1N7s8mMNd7C -whNLkDItqcD+DQp4eLUa1y7SDWaKBT1zn8ZnYFaVu2fvBlkSC9i/V7xudCy7s6Dz -CZls/n+CDakWQp2eZ9rs+hD1GrR+dlDoactpTFszWYY3ujiDcs+oB+PlKiCziGzD -2CXrv4rMXPfj86GCN4+2Pg== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -gsiyAh/zL1xUwpmprr6NAQQaIGczBGjhcuuUGvpHL8hMBxgMPcIMpvp8WS1ajEHn -py5FCDlR4mW8uXNvTts5kgng4OG96+DdQ4XdXqST/b20UGq4PinSXtk1LOUv7TFw -yYAQKVWJda29Ami/BKJegEbhdCks1D69roeJH1DSwVfXs4+eMQrjc7MbTbY1mpoi -+36fJivaA7U/YlJiaS+2qIhWoSM5Fyzla5dhoW23p2f9pCfJOwY9bYe6tjCBi/92 -qgy3zls0rjtKupkAlBZ6bW8ESkTjiRN/IyOih61JTRjJXR1AGRDFnndbdKW2JBRX -DDpVDAdIo0PQsrjeXscc0A== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1120 ) -`pragma protect data_block -oJzELbB5LZeNsNweu5uYWTTwjiMIVGEKkku/Cry+UEzxU3xbxPijNdpqwF1CUnIu -gyeQXm4W/aABy84cGADozOtQl9tYT+8iEZDzwxiL3TduRCLut952DiLthKX7tDiz -K/Sfo/5K8SoG+5gMrxRT+PS/OgH99ThFjftnZaeUDUL2YAVcGoD4l/tmXQMaYC1s -0Czgtprrh9KgH8U1OZPWXeGSCQ/Wcvby4cJ6waaHQd1XX9mgmkyX/DoGVWjHksfl -ON/V2l80YzUA7kz2S03VWrm4E0gsaemi9zjfxMffXLvxxFfUfh27bbeGbwIrV2P/ -e9ACpAixlZbLiy4SPN/TE/N/fx9mmqVCzM5nL5Hx1Y+zloPNKumf+FN8/LHE3vTI -X1HR4/qS0EV9dA01WpmmGNaHi6RZ7hoh80NoK+5VYpuJHrnzM5+ypXOqpKkAjzxA -PyB5y6AMGk75Zjm05EOdWq1bscTch9pxEYwmpnwNrD9SeE6QZK3cSzn6BWR7cGYa -Vh2bY6lwovJVl6uxaJms1dMTnny+SrkIitPqD8Z05k7gsEIdH8UjJnhvlhP9Vzg0 -vJx1pS8CW75PYm/7u0U4o8iVOebmW6uHmra+CbWEHrdv08OZ+VZdJhY33uao+Hhm -fKI7YBd4PCnbc9GiFI5j0hxpSxw70bDx4nkVZU1E27kM3unKmi3SkIE7cC7zFQUq -1OSt/GgzDEU9BzLXWd8ghruhmr/a9kORV7mPvMts9jKCMgXxS8LmXeyAwgw8GJYV -6fjbL0qWyPd4UQTGmBZOpQJKadU7ru9JPIrr+1w2kPg+jMqzH8+ctqwHsbx8lqzz -re+6w3Hin7b45rVm3ABrbdS1JwelNH4xoTy0X/oroQFQglbZ0vJPk4X8TLDsz1vK -OnDEtNKwlLg1QZLW+lEXBoSUk5LXQWQEgxmC5YU/svO/VqGARYosvV+pF8aA3pwa -HZkpdtk6kNHxhQO4OlV6Tq9+kp8XrvNYEjtTkwKCzqSuJqNL5cGqKCHMzfz0lmI4 -2Hg9HDZv4KxkbAx/5QFoSCAE7sO5sUxRed2562cljCUP1B7HSg5Otgw73Fz1UupU -MIIkAlf4wy8MNnM8pU/YiYqabOUUadN/Vs7mOg3Jnj/UfGRrKxAnYw1YGQTKAI4A -qu4GPVqmPP0dYEi8h06AD28jO4wlSHGwb894S1YlipYskzfVg4PD88UduuEmPkwk -ob9Zgj3JPMAErReBxRpJGxDLrK2CMpTdWGlYONQVoSkdKvTj5C1JEtymuUM4IgP2 -/DfWb2DbudqukHzzwVjXUdiXgul0T/LseZLKviSckTQar+nVfwHYH+9YNK+QzQ2E -QhYCBCm2tTG7f2xI7wjqUfEG3hedAoqoYGoq7GWaNHiW0sMK/WPVl9C464c34HWo -RLafYBMUzzXknRsFej2hOrLiGD4VHJFlUPXDEjiyQ194rUWtmjDJ9x+0cfOTPczJ -N17QQBmIYiQGeSX9Q/1rDg== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -E8dXbDShY+3zW/pawy6A7D9NWDBtkXfCt/ri36z9YJa8KqfJdswpb2811maQtonI -mB3I6Qx3vugXgBL+SuJDYWmPAuuK0s4V7CfYmd1uFx+gIl0nQmwrz7zGXxGxS1IC -Vo7cclA1Ux8nkd5kAV/a7XqDP9d1xr2IqDWp4sIwfXVYSpJ3b3Uv+AvVC5PLbSpW -WLZrBDJ+ktUNqvP25HjEDcwmdyKx+IYXtSdF2F0OTxq+KvyMkkhCjJDno9MKfPla -WDec0k3Tua9WFgnQXwkfgJtsFE7azzWpPTAIYYyNo/vsq82JL9wksdOpMC1Q6/Nc -ldjaRkUQ34XjBHxGGe3nUw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16432 ) -`pragma protect data_block -p6S9Mf9ezb5qk5YXeBF0LIfOw6RxpYgFZJx5NiE5aVzqjzLHCcAfDzR+wfDEMRnH -ugRW4ejCNXHLZ3kxkHGU7cPkawbGSlG/aHdksosyhU87kn9tY5IkMzUexUHcZ9Up -dE38e6Q8nKLcRJGOycCeInYlFvAHnuYfS323Hm3KWbmRPxZaa5Um7Y5lJeZtwcgr -53fckM/1BVxrst1Ml1lVrWuBZtRn5Myc+w3rvgatUHSxt53UkyFuefOxAjgZTXxB -AywmGpNk0BBWrLp2FbWx41HfBbT1T/WtnO5kEmNMHVuMcd3e55a4R7cCOAoclg5F -ObBPt8bCZKm773oRVCyY/9peEAr4ANfBoAWQpE0WrVFmNVRQH041+hTn3up8PVxd -ul/r4suz4eKLKpP6oYaExd2bALNTQIo4zV06NWtwK8iWRzk+XGN3JE9UFFmJcuGS -thyc0zET0dcPIzGGkKNDUEC6xtQ05cMiWGLvFsNjUZMExsKJC3luxBXHLhIyrgXa -MabHH+q5qC6qD6sicrxUx6K8HN7dD9CznT9B2Fe1HQtkkGDDxZz7XTmlE/gty9c9 -+7W/0icmzGCHzGaFr4UAPleM3vYmyBEgqx0xioFPBglmKnJGll/vk9lZZHktXJdo -l878DiRwpkrITmWOt+8tmYV82pYRrnz9ELSRE1eNiI9jC3XVDG1aWw+CzrM4nFKa -xV8wao2DAK8/Jx49uox1u5eE6swZ84AWBj2VGZYWawarhrBR0OdOtQ0YwMkrHMS7 -fqifOvJreMXHEJKVi9CO4M5QlmAUZtg04f85hunzEcc/ugjlCUc5XVqJLR1NGNED -zTh6stxoAwdedJNkPje8JJVCvO97QpfrEjgY+cCYCgroNSbKUzX4n2hOayfQ2dF7 -37GKvw2hj7gQURLrogK/WLaumnfV1GHZA2hSSV9AT7p/50uC4t8QgQd5dT6VzngC -QGGE2Ey4UcAi00q5oPwoft+aE/Rih4qA61D3ab5NUHg4VKKfjS75aLwv1mO9MUtm -Yfl8TuuN1XTno9Ar/UN/8Gqgjucp52YVrzBwt2D6dhCPdH12yM/+SXr6wxb6ab8C -q3nF4jBxOKh/lL7FiqWp0ksvXBqgySjbIEmny+fQIP6eb8/IFnG99L858Disp4dq -2zqVT3t4p4H/jdcVGtE4JNl0Q0ySD78eMmf/RWA9u8TleGSjIF+uUbHJZzmpUoRL -ZzqlAHnaYcOdgD3TnA5K3B+TKq3ELgQVUyPk2a8fWGeQYOLQ1409zW+5Y5Ceqb5u -mJWsNUqzdWT6oz/XX3tAbkbQHG9Xdo0TY6nkWGOVeWmHW84qsEGNPttSKc5x1IEW -ckNnU+2bU9sYh4FWMb8wi5HemLyP8hoKJRyVnZAK2aLfylFcJn8YsODkggcyfzTW -XRQhGbwcGwDhvOXSimKvE9eNGB7q/cPfl1j+rM0PNwXN7rzCAwAydG7B/4/uYkzo -vVxUuQa0P9VxtovXYVDXvoukQae2ui5nYB4MKDBhJ0INfkIHsM6KnuU28hwZ8g9k -krUq7Ow+HSpCy5S4V2UIg6Tb99REHIQvdURLbDWKEN8RTvz9Ywm4Xlu/QoHkiXE0 -0QFSnJHC4jNW8Zvdziz1ew3VnmO2aXB1hcyTk7jLAlImJ8v8/mPfrkQZy1KScjih -UJ2Wdel8L5K+0WvLMSTL4zVOMKSiPN3uC6pJei8dxbSoyQkZYtqzBPlI0aGHwmc+ -SdveDfiYOOG9PB2q6GpTP77afyGlrnPxAeEZoRrAq7Pk5CTR5CL8ptFGjx4yZNZ5 -UtM7WwoE7BMkiaLXfJH1vI9uXA7tty3lGl+5X37+9XUG0qwZ6GsCfzD2LjBsrIzw -1bAld9npILQK9iJk5qcdzq9RnozBbCo2VwtxSTuEKTfWixXHi2kruXy8c6JrRMah -DOouewRO5ecNGhjyNFKTuMYMmQx6dXBYJt9saekpPCG4ZCDPAbWzP+qARAU3Oax0 -TIOtkYqEQ0AnL3I2YfZ8/w54ZukM6qzwU60eTv4LH3TGXE6OU6Wt/Vv9tFH2gn9o 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-qoF4PacFlmo4sf2CtrqcawPMNaLjwSYTavBxubdGUS8XWFiIwGtA6neZgpu39gdP -BCT2pAWPYr5Q1AI0IUU/uGgLgUDR+IDvTqf6/Oc8pJqrbiuUpZOhY/AI3DfOXwnV -oqjcZ9MO+sbgaWL1ah34oMik+Hizaf9jY6Gg6htx7Y5MtjKUbOQ4SsSognoTmjdn -mCCyV4J7DdGHgR/VUkoghbU/qTN5rKqSJdNIYQsJZOj4U2EsS7uQn1ukE+arouDv -PaxNj5CyszH8+UUnjiP5VPxl+lLny0vlfYn8B1+3RNtQHrE1NC3AhGG0zhzetnTA -UHGCPkCudAhYRsfYnF0++r2eIjwst4ojWQEhLh3U8FxIEsVoXCarYvp6bt/ldkfO -BLZJMmAcZRO64umdvzTJ13A3esrnaxoy3ueZFNvUtPbRZUfxS17tk+vmkPAKgGSg -JZj5lV+5240xqCT9sebEKQasb0idjeDTkDyOL1J7k07eSPrn7zRd2u/st2FqvRTI -nImshMgENidTWbSi521415tdtxbVsRZhelHi9RkhlFPrJ8lfdu31tQizIm94lMd8 -LcgEM82AjktEp1f9tdHXk/tVM1S2O7acH0d3R6aoCb226xT5Q8lzRleFwXXZnUKd -ZHPg+aKAUszd2jux4LDCxg== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -l8pSZBuUsKv4mAjlYxaEkiVDG+rJC2E24ChAvazlVAUEO33jqkTqU9mRgJBkqPoX -NHPGUDldGPqKjTPawC+OSftjFiM8lMJzjAkfksW+XarV7lA5cu+qu7v2XbxDukoK -+uhYE4/EAf/rzRsh5USNikDLA+f31pWUZVpinXRjhv/X5UQe+9w9Hm77jKdn2Uwx -V0emfy78QX+lPds+RYQJOL/zv1iBbf5zGLRrdNyKznh5Q4hQem73AFfkn91wDKYZ -OzN+WxeSeYfSzmJ3fSs83IeIOJNsgFhF5z9clPfWlGUh0CkmBV+8OGu+/3+pOfhv -DiIQj8Jx3VxwINYa+WqsqA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 42304 ) -`pragma protect data_block -qQ6LZII2teZC7M9biVeS/s4BIfyoFyRdHbSsz1i5I2cIYWMRQg9JIUFh5wFo2gYh -nryE1wWICKrHtjOOxAiWfek6kWGep5CdYiN1IPqiWeIBBWJUfZYj1dFWY94iuPr7 -MhhvWzhoreki2JUlutxW3U78BDfBycv4rcaMTHa2U+QjeB0x4RkPpQdVKevm/E4D -QrlKM+EY8H2MbzJkMUp+qQQ1ZRiPAawwv1NWKqHY+U2uTht08ekD/MXrUk+fT381 -mqLnzFuMgy8NnSBG3V6lGw+R9YQrjZnNT7aCVsApWTSmCu/lcXOT6IXL/K5+I30d -zkc2/4HOFETY/LSl5yg1dpOKLBgWDME9RuUZCr4xVDdVSTDwsfwQGY2X4echNYyu -6sYJoAxJAK35veIbYcfjsYPgqs0pcQPtywGCPZD37hbj83ZckadcFMzOTh+DTBUZ -2gc/SzeSmb04Wy7EADxsxmnK3ykiGx7n128hDcUyF/9kMQfZXmJniQPXxKYxwqcN -22I7vpOQ6TGu9JLXo1JS1sSsmLNntDrhfERlUn9Ibk/iOYwnaZEFvhcK34WuJKki -aGnd02EZe+xAz/zqi3sCmAL6XKddckG/zrK6lfpjQBKwEE58Xd7Osl5TTTrbkQAr -vxulzMo0LgaEzg1j9pc02oHnqgVglM9ev1DOWMWGZn30kUgd6D9tw+8OCFSDd++3 -rmC4SqJNzsAc88sGvTxlNFMUJsnQfPlK/oJ9yUrTh/2TkLhr42qqfT/7u5o8bPDP -jojX2ey2fXIVTTYOCvS0w29e7HztnenwMiWhwzvcdauwpxZyYFWFXYlhI7+CMxN0 -JIB32KtSPFwg5n9fitRxxA2hlsYHo1NRFhquWoY3Gj/NfWIujSXsmTFsbNfRxx16 -SqoTkcGp2X3+ALQRIEaWjC2mgrhIVTkxeS22VpBzXfZjWvdzudqOP5ksceTgphE6 -b3mE8coDLrtaiMtfBPc52ONAO1Q4snxHoFXmZTD+BtL8bVA0AN1Gy5G+5EQn/x03 -UfhORbTVXeGK0rusj0J38+cFSvcd7OhKevfMvYekSfUVlzfPGVKu/RZ7tOeMJiBd -0jfEYla8qMz1xIJHdCqDAUFr86ca3hR18RgQHQ6E5rYVIQm7ZSd0Qy+QQiwwzA12 -GkcoQ8KkJrpLNvm7qp6Supitk3IuQErxUmw5t7xYCW10aEhzkpdv+r60BC3KuCMv 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-imQpWYNbnMhPRNXtVil13XXzZl/PUHBcKQSg9hGEn8uPPqQvcjwfCVX5MD0qu6H9 -cvuSTqi9aNlHfyNDOm0r05dtkVRstXoWbjXRrI8FdUMqP6yHrprHKF/a9WgqMcpx -qMpzkpvd//ZEjKMPoTicFo6rulap2/gHww5p3r6djDcNFfmGqB6RGwD9o12B2+71 -7OjC2+Z7Ai7T+CmfOuStooBVgfxuybBA/trKV7rVww3KetP+KltippsiMOukOhAU -2Jo0TBtYcAFFvZlVh4QgW47ATVcRCpqpqDMNMy2Wn3nnahQ8d7Q0IV9XXZZiD/0W -7ioaIclYcAI1WFspHWROoAzjOFYr6n01a5RoIm6rRVuZ9Ao/RXDyemlqVrdskeAd -6iq/aAnOrcpFtwKqFf5CHHp0OJmYB4LrI6ZImtwWpLGYW7Hg0Z32VG2rg1AUrI5/ -2L7DtE7dWHkPk6WSylj1ZQ== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -T3JVVv4olTqmMR7B97zmjDKAAUqT1HR3dA4mr7nZg7imRVPYr+xDs+3/lhQy92FC -czhXcdpkyt1b33Rs5P083o4weI51X3sRyi3HEkwCUu1XaupRk6Sw6k0Y36TQtWFJ -tUgv8wnSw1+0UdCO2a87/+reXVlx8SyGA8iDp48yhsqPZMA+RPnemFIyVfrmY6RK -MSstWf9ubliJLYM7oRKCEJzl2BQhLR2vQlKzYLAL5JvvsA11Syrps3oZMNq3TQy4 -HNGfGBSOgs26G/gi0Rdm6hP/gylYErMpf2WA72ULhWtBnZnyNGg9+l2l9kwdrWJE -G+hqYrrJLNDYKubNop7Lug== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 13344 ) -`pragma protect data_block -UfeheRgBRxdnaqiFTvEeC0Q/KuH9TVOzWZxM4U24sjhn2RQRPREHerSOK/3qaI+x -rfDb0OaF4D3GaMmC4S41VrXRwQmIRu52ShkWonVwf2z3h4z3BDOk7s17R8tzX7l+ -imJotpd8E+lOr30U0BIWTBbWIT4aZJ2hUMAxkCa6/g0otZNqObQenri5RJhQvnGA -HjVhegbZQdLVWuGH8Y85Vgi/+IJ9k04gvp8SpV+dgp4DF+bTcVVqMbz8CCC31kTD -210mJOvXnxhbyhikFen55GPZzqrg65Lu6Hj6zEidaqJNKcml9lmq3bajxYmcezEz -8yvSkxpytQMgHTgZl1oHypPxovxUd+l1rD5zJShPIXMnY2jybKvXS8l7l0B1EF8U -IKZnzYJPNb6HEQ81PxXaD5CexMQqth1iJXDbUuuA+sujmc93z0Rj1aByZAEf59Ms -9uQhUHBFCMEpHndl26JaBW8z3ApFpWVRfo66UwvQ/PUCvZcNv2GVKEm9wsO2yjPf -ZNuEK+NAAxP2vWruAuu5wW4pqk+Qhp0z68wgv9yI4j+KVwXs5weTTyWJsh5j8XAs -iYNYd5OaR17O2IEfKQ/XDSZlJzGjQt68XkM+VzHnULQ+jz3dxFCqL2uysExdEl+m -nj3uY4mSrPTrSPHVIrPqikhVtWfJ3QG+wGlbKbhKt6Glre3gJl6tw1HA/qY4ZB3w -YtmIrA0hx/zWKWAkJ8hrhegk2BWKj4NKtGfgu52HcOvZ1oENtJjSqI3YMyqZkKd2 -MZC7VtCAPqjuXBfPwJN5WYM8b2586IXgx1GFMQ5HCUzau39L4jxkPKVZkVqbE+IX -yDuzNa+TTlOCKiGnTLYNcsx7UFwc/Yv/jQdRXZmxL1VRSBNJEDJP4HR2jwA93Kwc -p5t320sj/7hVJiujQTQJChZhJYRjCGPZ/rh2dBTCGB0oRqSFbQTM/0OuaHrNcKke -OF1XwTBuV9BkhPwWGNK6QI1f1ulz04qxZe8YI/kHDgvqOzDtqiIH8kC3CVqU8L6y -QaDNWc94W6461Gq19w5tWWdvaBUon1Hfo8sdVP3mM08XOqNb7DSbDxPPSQIIvtqq -IlcVs6UWz7Kkp4wCy8J/sGMHDBi9vIoxk61pv79Hgo8fxhe7swnk2MBaHgRhPWI9 -MgZPOt08DEPbQS3hYX0MJ4MSoHh/zUQ5xrPdzz+JHiN76CrATpfTI87lY4ARbw3x -8TpW7HhRQtea+sjBb5QXh9Yr+ZPXQtTZmVczMZ3mpR3WC9GQLbinGdyYGM3SUEYz -pbU0f5B9teKsPQNJXJ8Y9TTG3zbC34aHnD+g2Ep+L3pG4l5ooRwfWCm0hKjRNblt -R+/5xE9hp/OmLB5wFp0Eiid4P1DuH7oojKrDpw6J1rJzJQfRIjc0B56lVw+/5t9L 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-vPHSOFdwU+WJ2rBrR78kV5Hdx+QcmbRMIOaVytbvWGGumu/Susso8EUUlSha7lVv -iQCG3yYU/UwWojBb20kEO7ZtySUgTE1GeX7GnsDomVg88bAxwweNiA6ajGDE31KA -+sthyYTjFc8BFGJMvZNP3Myk2LA6xBE7fGawPqaQaA7KLkUNu/eUwXg/3YAwgHEL -q854mENUOoVigUL80r7cIwhaMYdhNnrfFL7dbhLrIkAHx3Y80GitH0A04fQGYgJa -mRhpLpJrag4s8Defe8rLwxBIupfTS9+rWQXY5JBdVUFyO11GnEWGogFvvGR/7ATu -EpFMXh2f8JljpqrNl3CLFojZEx6kEhBFDmJV5yCGR3ceHMCD33uu02S9fuTmuQz0 -Uyr9Q/5xAbctKJzjbsbT1fv4y69259A4sRYw/PtWsJUdeH3U8rjEeQIw3yOkQi5s -KO3rqLh22T1mYp5ozTH7cTsz29xPYiEixqUZZE/NRVIuGP+k/NKd4WQdtuCfwyDn -O/QbxsdFpr36SF30z4C4EXOxSPWf+Skfn5c3Gqf5pjYcsE6rJgisDzYpppiq5x6c -iMfcxuAKmI1vAgrM6vKwN13j58icozNHRLjpmrSgq0UcAkvShLy2fQgsgSnE/Zkj -9bJ39ZYmx/WYeTOU66n5n/RXxXVVwm4A1j9AyuG+xoeIt6GDTRroDMZArIyvtCUO -Mduj6RjgxY0Ju1F596J2v9l0Auiwdwq6g/iNXz/J2IwZL/j0pMxVc6W11Zk1t1Xi -S7fW3xD/KFWvNPDeb0+wP6tLLaZp4vBnlckmkh2r49/+6glg1GvPsCK0zdseKbQZ -CpvUnz9gRxONxasd8iDMx4XP+cZU/qt24Yf1N7jT+SRhnVBpNw8hD2ARxNHUY5b9 -4EjQoZcw3C6NYSpZzbqqqUtftIhJAeewARw+Q5c+BBLtGTuUd7RagbKBSOouSNX1 -259lwPs2AJiCss77mpd3sJxhXrGBDGaSb5DNpftM3UAmMsWaY1vowGwkulWJmP86 -jp2VbN9GCK4IoGSO6iVNb7o+x7w+cwaOBfFXFg4LVUGLbqT/LSi0O4+y2mTPoZi1 -SruCYP5KmzAqToixBjl5l8vrDUB/paxNnDSOCp3nlPW6B7572K2DNCEYUpEreYAW -iKuOiiM9a/ikJau1sCFhL9PJ65WqdLWeMSH/6jf7peNsv2lK35ucMksieRK2jfHc -NWdrGetAMlcB2rVu0xiERh87SWP8ArnjLJomTpMV6aKuTB3gxhUkExfWbUQDQtA5 -EYCy+NPSfAPaLVSu6c/WsnFW+VwydK60bL+kZI/Lw+uRAGwF1RW05jYpAREDhvWm -C2sVIAXnjZ6bAHaLVt5WpJSmhoFoIrXOvX/2f22cdUcPxmi5r3N+am35jyICj7TZ -+foK8hpnT4uQF5gqaMw2UYhNNDribdOn8W4e1CL6p8ubP42dgvvPECvWRI8/jIhT -bHWKZAMhjeBxSBCiFi3GczMfg82lcwFBNrHUDrHBWhqwjlk5SRmgsDgnGmDBaRdn -OhaJ8qX8XkUMEXsUaTDC3VeXK6Vcw41JaOG5pgCceRjsGE3KOM9SJkOt8gl3qjV2 -4f8PfPgRSCkcOdRDkiDIQh9TDg4CK3Rkb8wYVziLfZHgbdLVrlJ5PM2lp4OGvArm -bU9dk4oCzdHAoEIys79FsuDVOLSdBJP24p3MQLLZN6P2XNSZ0WcL6ejN6XxGk+2N -aR6iwBUPpta4J7LNXNMeH4iEFgj/IfbtHg70zFk5ju0gt5AUyKRZz0wYHm6u13Ui -okhzQUM2WzLAsdXyYehTUxz2LJhJSYDg0r+d1TPTrXauzh/p6vMwZlh5ucaHAPuH -MqIJIgobWRKECbX0m3m4cLyNU8CBb+4H+26eIskpaShxtGpbWCSBjVNA6faG+lB9 -LdONLxhGhir1KpFPgt/O9N0FT37KiW4zHFroj1G8fHAmaAe/jLKCLb6j44P9psF8 -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -Lz6FbX/pVyGiIjjEfPgmiw9+t39Y8KY/9do6W/TSCEeKEEctN2g6bJQE8v5nII51 -HQbGd/vhbqxxBCE+F7odeXY2yLF1W+2PypPquLqJYyk7NUpJl/WduF/X7kY6MeYK -Pk/pHOnHR5bHZpq4LdjlBHexIla4ytk1fbeAUNpGqFXfdxUKHuhg11fsCHtiL9Dq -e1yEAbHO7lBU/2M6Qm7hP579EJ0mRY+Ig1KTH78gvnGxybc7j7db0iL8puxUVdPP -onAP5LlxeZuF4UycDVI368UfvPX6c7VtYauZ3+gl64CbFKm4PNUwhsB5RV8Vh/Jy -YgUU6BkJ4rwDsAJ9lWzKTg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) -`pragma protect data_block -Nu8my/ZeIqCKlm3k1LIhDfNqSTp8cd3KJe/bSS0MRXyvIthmdoUEvoeqsfQOFVfD -pp2eufeN3GoCh7J+3r+Phu01vJQLR8Xj6d1wgx5lyrvjCOUmFvFFalaBgF+3uAxT -A8NiL81w4ArWYfTqfTtii2tDTvcptbZSgg7pBn4ylCLXwufQOJfvBLB0Bk8cG5wv -sXg2J3jZyB0MrvgS2aXEE/bN2JWct+PKBKNfUUlbYEJmBe7gw3VUPrBto9CLOHX5 -nMPOUKtz4xRZDz8X6YB/FmBQjGMfR8Mxn/2IeGbmZG1jK6vKjjSIfoz9sPybFavN -V/vmHsbaTqB7PJLQZuW/Nk/v8ghiZ/WTOiljvFdHiDbUpLL7O/DBnNiHNZrIKqRS -xKp0D/r+mFHW9Y8qeD0YAFMfTe5ikm9fd/BQacaCJVt9T3I9ls/TF5vhS5INrLMj -TMW7Me8IpXpfzrxVHdSvuSScdayADuCD241qJ9XSStRV16lXAZsOPUYG58D8dPg/ -mbQaWZ2bUBKEUDilERYH/PUxcScQUFgRuP5GamoUxzCbKo/LzMFG+sYYtLHn836z -FjHPD8lkfHlbl9mgHF4VVJQw/Rs0Qv69p7xpGLFtOU9bV1y01u0vXio9VsggoKUn -/caeofCscxAH/MOVM4qTcB9cjPQavBQ0pjmsLKpR4C+GWaFRvRs30H2VKUxSUmRo -77yhZZGA5j4kgb3WsTVlsMfH2tPhoooQqfbSbFnDGMNg1SAmwfRv8NPOLDF4Kr0j -0JGbxMmioiKfQaHZBjj85xUhl+ro2mepDdna1r1zgyK/Zjr3DHJuvE8wTukFernn -JGeGkSkcV5kO9WR+DYc6Mec+osrCWn3D5EI+fzUKSgGRJjy/mYecaY8SQ4k5McYX -0GIQoHqm6Quv0auLsYnoi/9m+NV/lwaEMP2TMJ/rOVLXlY8sXy8VU5/bD/QVc4L0 -0W0wdxYz9G7gdh2HxLIRIhzq85ig6azxlLndlLJweSmcf9OxT9eA6GxAAjw9Mx6c -PfPz8iYqjG261x7sxJOwH0RkRouIXOmzKNVB16BfaJuXZjHZH02Fw0LCxbT/pbVv -+jbFg+TtbMv3guRyAMcLNwbUVe+8UBEYeaN6uc5pQUfTMtRoHbE80j8NY/jpbudU -m7ApSKt5ICdBSZ/wCHKTA+Re//Cz2BOJ/8u3ltlL8CVRrJ1Y7F8AGVHRpNuX+aXR -nKnpMJfEZw9z/6m8EkLWOa1fiuGYQHg/PLDRPiokyTMWzKbZSzZjmLoZs2dSs97V -X3MgZ1M8JYK/yBEFrnqjFp0I+cMuLaoPVk8Md/yglRpWDeH/rtRUSLZOOvPAYviX -yUceuOLEJcCTs6/lZt6zd79nj7gTp7x6t0kdxyYOP01LjRy7MmQOYaSj2ivIzRIZ -dLlQPtincVC2IuAfhrkLrZHUWk+M6eJy4FSI2FnB/4JZydYWbFgmJcKP46SV4/Sv -zh5cYPsnhA10nthWftm7tqucJ92upyvJUUh4IniyzEMuOWtAdv3I72mCd4e91SRo -su1u1tF6rXt2Y9nU/xZV5cX+xe8V/+tzX0OgsQXyp5nSNY+Sj0fXKJGJ6hw/EUoP -pJqW+FV2bVzlf5V2CS+ztVOS+tV1R3u6k5YtJJYY5qydjUfnZQsl2EhXxK3f5C69 -Dk0JiYoUCdkDWyWI9q+XIYEH0mKzhCDcKA2QDwTcULObaug3TwQW8wV7oDWL4O8b -ojats1eBZvP5jP8UkR9o5w== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TTxOuiZPb3z5XXLY5O7KZo9Sci79nGV1/MfaMohoe0ccAJaqk1GLzchKYcHE/uM8 -mq+Lgt+Lq5ExtX3mWQnmAaV5bf2YjuSduyCMYjYr/WfeFQBrvYNKJLOCq59+YxLz -R1Ad/3JrTQChewzV7VLmOrTi4b6Bi+rDUv/eCPyQZ3m2f4PErw7ca6P7QWDC58DQ -xpUxlnB0Do5YE6IOORhfzH2J+kWMIsNbu5b5aZ6GQN6SQfJD01HlPvwLe/Qd3aVe -PSqjzgzb2QHjnBWsZPDaphU2PQu357OnnEpf3tDzZxPLGgdN4cAJCd98mmfu6wAI -dGHx48AfKfxh4sbfr2V0bA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1024 ) -`pragma protect data_block -fJNRvOMBPIBRM0scZqncFSaKb9GwamqRassaxCczcSmNF8lcC+CosRzsWGqDDmoh -V3WvSyIsxrrqzsK405YwAg8C9eKJaCdieD9xRWROdJaM8lW4+KOdCYRRwSfNmPwb -Frh1AHi3c/YSX6Zp1iEyyQoiZlnCOgvfrQTUYSZjRMFqklJnLqQpBZOLRkw5X6JF -P/K0VFKoc2rsqnlDPvAzO2+mWAlcnec1pYEM1RElbmT7UpF31swFtOUruI/xU5Gx -y+Nc/Tz4c2rF45s1N8IydbP1VI8IyEzJ0efHLlujJ43Z2Yc9syMX0bzDX+rXHSFA -d+zaFPINa3yszIawwhLSqQlS2oDFwi/oRL1a/xBQiMHn6Bx1ldYGW579tQpqmY+T -dHHBJsV5UwMUv3mujvW2HF9J7XnIZUah3GG86n2VXJdZRMnYeA4ZZxfZdYlBccHV -3rAduoBxGe3tof66Pv9gMhN5pMe+w8a3njKo/CwLLCwK0WUMCphlGGoanAmvtGZf -tRu3d6q4eW1ACzG+qPfSsQK3ngH0Ts998DWee1VntgJr2h30KqUIJooJ0fwGIa8k -ILZKXUR0msmcyh1ti8Di7FlsiuPodnRaUCgXxVirmYalnCYT8kGASRzJYW7OzkHQ -xTZsFbSTactBcHjpvFZSv/qSK3BXR2BMGQtRmTUhVft+O1sLoycki1yTwjoFU2zg -JuenKFxnJmUl1Ac8R78Ikx2Fbn0EEFA4UEHoYRDm9mRwsdFpNEwf/WoZmA6CVYgh -pw/2DFRbirJYlv+QDz4E7xr4srHJfkbnUGr5T8kS6PTt90zGl7U3dvynTPMIAyz4 -GyAar2RCSSQKRe5qlWfVwZ2KIrtRWljAvHrq3KOcvll2vzKP9/Xfceqarm9UrydI -41HrB9c4GR5rkIjau5iSSkL7xo1VdUOqfc+l76NataG0KaZhSLL/UGhEfxw9j3qD -ebumDLu85CVO+eeB+xpMUOp1kG9jCIuUWlc2QJY2PSatE4vf7d9WZv3MjE+dCWna -9Zt9YawSS4nXGo5Fh1U3/KEdkMVIwZzEEq+48YTFNaEwxjeMmkWNB3LA7tB4aq2x -dyRdJRzn2ZFnpi+e+5sh1zyUUb/VtKgp67mGY7QYiD8s0Ld16MyjVFbg/8cJ217m -jwOaR8MzRR0YANi2hOfeKppvM2Ev1+fEM1Lce5AdoSSEcNuW2Mq1DJg7QL5TT+m6 -Uu+6EuhTWF8eArIXCX/MGms+//DSUYcn3+fjKqnyoiPMAeN4fN7X0qvfDFnuI5wB -P9IQQZrLuaA2YQbnaMCA5JrlclN/C/hGHQhh1VFOEB648lSTs/nnRr7kaMDRpVmx -xGA1BK7JL3oGZnE4JdvgSw== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -nkhAcPFy5CVC81K2XeH27Rc3XAcv7GTNij0DpNy/tGyGNqkfm8/I1LfCR4iJsPE8 -U6wXF59KtCx1ze1dlOrt4lb/rddSlMcjclAf/22Pk/Ic3DCXCY0Ma9YAKx/HDotN -1dAaTDyDrmMf0i4h8jArjVEkdRRMYvXcwIYMQLgdoUxnytiSl/z/kA+HNl9nfVla -F0F/7dY9wlvF2XLOT6OONbt4VXzzSKlXn8yTOKl5QXjp7NZg+R6xKHy8uv95jz7W -GAMfUNRgH0a3b/wnyq6xyxtaUxFg4EqRSmIB3/vuUWN6CTQhUgnUCMIr4vYn5G/S -ow6ZCwubW4TjcOE5DpOfdA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 17296 ) -`pragma protect data_block -Hdm6Faz9e16HFoSKmVivS8fV05dlV+LAzpIs6QDXyT9Y0Qi5oHgeb9r+PINXpgZo -KKUvkxr0RGfRoWE1tmxx1AXjU4aujlITqfm8eUr5YnHni6ny4wLXbYJemzd4Im/j -xoyaeleBgWEciGAYXNXIOVWi/ULg1ADkemz4F9opZrFpeT0xfPmSiVux9EalFf3s -J5MgOhOa5F3orX1Tc77ZKLMWc5DSJ5usMhkEz/xlR8NpzRdsMugaToGEWz8kki6G -zCjIppz9+iSbc63Sst0osVlQ8dkJVK+31yiiWwyufq73nsbKbEHtSOr6BLpgFSyE -QnnMyRVld0OnanTgECcKVbmcH/IU0Wqs/t5f8je7ccAfsZhILP49aQfocO7uPff1 -vQk7Xq1LPp3xWZuJ2SILGg2qzr8uOnZ6yFL+by/Xfw53vKIYNcedWOJTMx4OYjT7 -Xa2Qsy7qMs7gv1U2YGPW6Gm4f+b5C7wT9OGZnERTLX1cCqdE30tC8J1oMGJx84qF -xuNpnRv4xLSoSYdH73xu28yh1y/LAq573bwdjfxYG0+lpt6bPFiJiOT0HyRm/Cdc -gdaV47Ou/SP8/Z4LJQWaQy0D21AeVrT8WbxHBxy9+5pv8ogp0f+hQdp7+NPNuNMa -e5S78E62uhfaietO4AGAZTrN12usLW3OhT6O5p9Pfik4APPFyLJUd/TWqlzNy/mw -OUoi4AI+3PMR/zt5yKD6twD5FzryerMVh9qZkeiHXKrrgFLotgodz58m2si+nyrp -vg+Tu3jNSvq0A3TzzW8q3mNuWLV9l5O+ib6sEOw8ccFBBgWMv8I79Uv62uJH7AGX -RldIx5M612GtsxtCya2P8o+7Ds0b+9TmvLK7obcrDqD9/wumPpIWnVdtbjSu15Gb -+4+78Wuu0GivmcG33J+A3XUqwSnSqf6IbCwxYzuCeiSmChWqdAL1Q6f47J9Yo3HT -n0nND6OW/hjkzhtsuUJlA96yRoeU2lfX+Y6k4OOkScrDbick6fdfSpcMaDNkpFHf -ESC80xu7N/BooRPEj1XIO4vQ1dm3wGrFQ/JvO4VSPPrfXIoUVApqEYOJUD0zTp6T -xwhboEAQ4NPPavhznP3khd0scrq0m8fkzs2Ab7aORQLseuwSoNL2ks2egcOCAA4R -uXgMDfS/DN5Fyee/nsrPScKnaiBFawPPTDJ4RtltMvY7ttmdrwqtKqIufid2Tc9q -El274rdFSSxB2pHbGgg2L2M/JzNSFhEBxGwx9vuc92KYV724m/9Lp8qIvYsmDQ/D -YUIG0gYxeHLMHiGZjTdFQsvGGQ3D/pWLltTe0qmpedymXZyfs88oIygeMH299UJe -QsqZE+JHMLHPzueZDfNwCJVLRsWQMrKcKW/BNPqz3sCiNG+zCQBwoFJ1JLo5pAVd -q085F+QC98XvrqI1oiTv4fn2/4XZDljuQ3BN3ptVO5i2Iqkd8EdU+BFksCQJ5VZh -O9PAnZmtq+ak+AIVqwv7KQEDF3lYTQf2mY+0mWHVo/1uG7uOqiKVlDmZaGt7mNSn -AqA0vrN3NtwAIdslnA6IGbkBOjHi0NB0V0Rb2fDBf3CPgVOIRohgRzNt4/j10wBG -F9LyAUcXUMHnYwJ8PJecMoEfvPhMrQIznBBt81kNWNwxwUKjPQdNM4WNxon5Rgrc -Wl/CfwI3BJeMgs3o0OzWlZzeKBBGXDVrltQYL7M38PKo13VZ/LIR5oAjzRr4BrTq -bCHCaDU5OXlXQVwct4fj/mZIq+MxUWN7lDZvOEFbf/S1313YynEuf4vJTPfmhIe/ -Nl3fkMfM1nX3wZUNmPGf2Hw8KhMAn8698LnILSlCsNE+8dyjb1GcaTTR4KDYBBTQ -gO5JxfAhX4b/Ty9rtxhRf+RXkcxHqpeMjSQBCQy40stLQTRgCsVbHtOWwfZfSlyR -FTJ8VoVaauZ/eYTHhVBFU16hHKMErZRKhPZ0iQvad0Qj528ge66J5n7v/oG/xbV+ -L09vhKuL5jjyhRncmmQiPnpWfSAl/vRek+Gv2AkE2crDujkcCxZvsMRcz+3SqAOl -+cpZ3JqjBsgiIIKVWkfBXD4BBbDROKXDXMouA/8P3mLi/ZHrbw9YLrUP6OkLEC3R -pzzCROPR2/deBg0nm1Ptf2Oj7pj2IjLF8L2zJUZAKkF/xI407kfUfUQG31WaSjCu -0PkGhwgojIuFBYFrPej1SZqfrZmgyWL1Rx54OlajRTrylMy/BF77z8eJApIWsoDe -fD/pSz295Cpouvrkh0H/ijJ5s7LQ8xAYk5/PG3ojyHx7uDj7hpM7OeOZFpDm1Fqy -GMG4m+5fF2Y9qFV1Bbh/0A21k9xjf2YmNZU4IpDXNrmbnH+sLDojGNwdYFhaC2YU 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-/ITm9NqxLJ7iaoboVaMu313skoRTQAexCgfCbi3bHnu+09pKdqrYw6Xu5WcIg+JN -Vj0kessoTtgm44DT/jjmujG98CSvI1jG1l4RlhRe2vjMi3BZ6Uz4eF/xAwp1okhi -MRwj3HG2ymVg9IoMWnKG3DZO1KXZTTM4IwTZVuYEKcNdvZlyZ4in9c06sIeFViPq -JP1Spd7XDu3CI0s7SGstRwwcG9VB+q1PJlDuKPq3IG9hdoolGf6Gt/OaCo0UtAuo -iXFUVNFcDW1tXTqlwttSHiF5T/w3Ma9Q7Y0zRidtqU4b87/FjOHlj4S9x+c9u6x8 -WhueGU+1B6GkpkbsduV1JiaTXKCo+f5/DMJ/vxAL75SlmtrUB2rGlKNzK6Fmwupl -0n3XT3IOAN0hloJqBFOH3UyRFQjT0XVI/vPrqBLghtHguFx/eV2ADwYOnEOOkPjU -9FsRNevix+td71QaHz7yvWs8/57YXMU8YI64KITyvXu2WNJts6G0tyB/TcBAL8NV -eM99LElCOhN0M9qbaWYR+A== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -GI9zPoGKbJfy2uLvVqFFpipF7/f2E0S5JCwnjimYOsXWBfeTRJgBk40QuB7U6ppk -RnRJbZv2OAchR7CcU493ey11kvcRu+CeNfDt8W/FwNevjEwgx6j+pAQG62JczJDr -o/PnmspeWHplQXZHafFrk5KYU72ihYx7h/trZ2z6PscwC7iwkq6yxBspn/mTNfsI -+8dxS8+L4CJWMqe4N2/a8p/cEuapk+wDl7ZL/KiR+F+DZA56sm8QfQ0Lk6Q9Qeqj -hYmgKytI9gqPfVFnHs93nZ3nXu7PLVu/OVCtpZX5R1lTa6klr+sE+NzL6Ni4yPGd -1AlzNXunjlmbzVno8FSMaA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1824 ) -`pragma protect data_block -AXQ5Qa2OI464gGZ360Rr67vUd7TzolMvE+xgiKUVzC2VBgolXmsO1t90yfbP46dR -mh/jrH57yGnxqv8UUrBPLk0/tQadu3ezS3iYP7B7ktnIA3yhLj2dPmuUEivQgWGS -b4dwjQtWTDyGelChU66CogT4DFpaFJ32LDUqN9NOqRJYV5bILduoCjJpfBIJa4Cn -Hlz/tlSkwP3YgJJkc7yFXLgByqFqxKPaiZreu+P5ozbXvd+twLrBhF206HDosMYb -udnkVPMAEm3NIFM2W3/+jh2Pb+9NAbP/k1E+roMpISqIWGCyv0x5LIYyluqNNTTN -7t1YBLRi/tEXV9xPLl+0Uirdu2zkM9J4NnNjI4B6LgaQJyx90Fg3pELvZdQkcypk -ygl7L8ZLWnx3arcpBsWMexpBi3TbTtpS7wkwwPefAnWbI3IWGs5KJzT8ZUr8ko2s -Z6R9fKPFT6gw9tOoqkh04G7rJUqhWjfQwb3cBF42g4CdydwsqdnbBNAX+iu/umog -DbgYl8xXTu4tEiVGaeaWoU/fsskxQxN6WUp987ytSz+jSXZgqerOXbRRA4d9Fwnv -PlWzegeuPbjszIrWU6yQp4l2RhmG4zoe7UycyaCLW+6Bnrskysq077hnNLEHBFj1 -08LjWRFkaDr8KLcClHN6z0rUydt6EfeTMZhd2Ihnx79VronjC7aOq7jB91m1S+3s -iU4/5apxus6iK0sleXQZSWxkM2Ho6iqN65kd2OSDz+YnAfGP7K/GJJse0ZcI4Nz3 -5moYCZJayoxX3e/voS2oMqGaWjySs6qHcj6YHBWwtsAgwyllH9DsECMMfOWMsaDd -aHUYqLDz7jrPIbPWOoV92R1lr5oFBPU6JPv4AxngJ/Kr9/+ia+BPuKs7Lx61AboO -T/VjoctK5L4M79s3Lfy6YYS0jvFTqtZiuN7zLoME74gkSOXL0JnkuzpmiWaG+/AY -734rCDkTkiHlI7eP1wF1aREUg1+h0HcvzytBhFm4XfIkGpq+9Q+YqOEeIrahRSlJ -2ngxaIOlA6pp3242SqSaW0ihctnACi/UoxtA2HklHWNQl2WgMcWDsEqhA6n4Q5r2 -nGtDk6bbvwnjftokgIwekinx9e9T6wi1r2c5cLbIMF0DnXLwYvD6AGDqkuGg2FN1 -24my4mwnzCOVSUfr6XmE8oMo6BLParwh1fZC5zYowPRJSRXCT20L0o7uOpaAnwZr -oK0g0z6vzG3SAJlkEGQXdWw8V4ULn7ZtDYFHdRb3PAQXTOaHr8WjvSeT6DePCS8h -P3yxFBcR/mLUtA48SCUx04qH4l90Gi0taDVLC0Gu0/sBbrACFfURGqwneJ2oB4ER -fBHYiaONCWPS3EJ7btcoPjLxmebdX942OvVkjN1fDTLyY1ni81K3o5wPA0jOhGXD -U8PU+xldQjDAQFYYzJ99bnrhfKyQTxquYLUPZnqYy1d34kMC0swCLWhDGYucZqt3 -+RXetjN+bBSRknxd8O69HsJYIe814Uf9Hpc2GHUAbMaGzN9ixylh4i6qxgbCKxQk -UBgrK0xsILH75KnZP/OQLq0C+QWtHxQyOCllILP69QlRp8+EcQWnfh1F2BbnOisv -Y/pDX6rJ/qb4FvJnneIa0lzPR9NQMqyHgJrauuphCXA74HgRxvKgSBa2WpTmKEWk -wnL1Hx15qR8MqbS6kyvPww4FD7SJ2A+p61v8x9lmiK6tCsnBQZrNk/wNUWqk/jQm -BhVfPc8vFfkVdcR8+Bo2qo08qSVW8jp9ZbQ9Cr0c1QgeKm1u8T3ig3qZaevnehf6 -z7QpXCZHUY4FXSPKMUTPqPj6ETUbZi6qozi/CBKAsTG41/Ps+Wsix2X3IA0VdzwV -Azw53vScURpLzk25Hh+rm3AlOTnFQe3frjklqNekflvJ+6gHbx3xCHVqKP2RpwMB -5URU8WKvZXkso1j5oYxw51If+rOZDq7sNchOW5RJvnqY5s3FzyxtSVufn2JDLNWZ -h/EjUx3Of5U5psZAHYm6R5cN9fdkknxKN2XuuA56Nk3Kh+dS34/0w8cdRi4vgjYZ -bz5Geod3rcyu9gtNtE6qAUnaY8OT6vAkibllrQvZMbffuMOucpe0RI6ReI1mTh69 -EbN2m4fMLQyYvPWQ2xYaiatxeDG2ptL+PUF7Wcbfo4i3788cg5hO3Vug32Nv22YN -b2UIkqKqLpGGmCUI8QyrYlPzidzFMpJnIMDe02tMAOD+eV5T+o5zX/OFa1x3xKVQ -RHuTIbeWKNyN9pXUyeHaos/evAe6KkA71793lBLaIru2totmPZuqiNw0ZcWlPPgP -3yZC03I1kVMuVAcuOp9HWtTQTH5ymzpEwpzSJ9kq1rVMT/pvaRRnRa5So7Fh9xml -wjnrDkbbzTuGM7mqUEKXfmidtgnfA3bzq1I87BY/IGE6n8jHwMvBRwdEjnLdfj9k -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -FriMp8xwFwm0LMCvekNwlbVBo1AZgDrmVtXw5xoD88CNjKwH072pbhCEvnL8vRnl -vwGDwLxlRtlWQ4sJTitZ35eQEa1/sG6RQZQgx3YRT8HTCrZEOstluUKNA65H7R5F -RrDJXRVBFyM87875G2KnKbK1qciEHc7doXhzDW8cxk4WNln7mBb59Q8+4ulz7Jfb -6CzMT/u92j/YQMXR8AhnC6Pja8wdJWzpF6niWmDVnN5I/Cn5/moWgLPZcQGs5uX0 -EE61iFIk4nVjslZ2wvRuE2KADoIXbCvvM3dB0EI94cVmNvXbWccVsGk6CSLHTYe0 -AJXHTXUxbjKoGNyhUhGkLQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 41984 ) -`pragma protect data_block -JNjowIfsT2PtKwZSqh31spktaerSsONTTAwEjy3H6YNY2/rvCMy7Z1McdBBZM9K8 -4DGBOhpqLlYoul0cZLw02zLTFNumYLtIouMgePR4fj7782eYQuX7+vhemoWeIX7L -sdVpb0P+t12x4i3ph4BHmuHAwZrnfxfcz/38L0wkCzlnbT5ijPg4W5R09jbmOLRy -0U7myUXnbMhP3omnzh8cWV5MmRtg9dqQdLGCCuQlTRmffNwKhxs39uhcCVp64/oQ -7tOXWFgR4cRYs7zNCVtrBPTdDcjFO8dXSYyLqyYaEc8gmSFhSjMbzw1z7HTjJh74 -oHL/YUcqEVI3ZF87eh65KzwOXdsk4ni/hdI74CKS8vL+NCKafK7VhzfX7D45sRAU -8nzN4Kapit2hNwrpMmX5krUcziv2tBVteJ/fO6nRqU8RAHfZHITh+a9xH/KpZ57a -7uodaE7uM81gvcnvCy7PQ/2m4Pj1ej0n0yCOO22Gg1iuP8AIx4hzryQce4UbqR49 -M6FCFKhwl7SIG/GH1B3ZZ0j3mP3Lt4WIyTYh6Lhlz7H8x3wrQ0MYECsChRbr4ky5 -SCoCCUnT11N5btkcj+nrQEu//OACUjkYt4qJUZe8gO7llGR9eG/T12cnh/g+iN4R -do02kRKWo6Tde5fRM19uRHvtXHlH2IIIt6tQh0ceJQzX8HADIPgAASHdHCluRYnK -Nq34VVJ1roK4pK69ecqvfeymIPqCay1NCYUs+JlZcG2S3O0yZfGcNT37m0caga4S -Aao77wX6RlHdl5zBgSpiXZYqO2K+bL8XUUgzFVOu8Rd/eoK/PEagQBbrD6P1cauq -v1ZEAGpPeDm3zBbgz1Ukxa7sGohJlvjzr3MVChXdYQ2x0Wi5tmqSBUaiHLA+qtL9 -l13WeEXGsvgaI6X1MHzbOv/BC50PvHB0hMum5fzYgQoGEtt0hgCTTAmIZec5qc/q -0qoEt8Smr4elvH3eUz1EESxvEs+8BnymD8WR29hNTmhqHC124yd5exRszPWkQJXJ -BO02EPTwam6FxxjIttPd/3zwiFSMyoHAQbgdiB4hSZOdu/yuN8NJG63Ffus1Tndd -kyiFmIHVk1QwxeRa+vdfbJWAKuQmnUfY9d1CPeO5pUhG47JBK49XSCQRGklDrx/J -XXffrSFKfp3GbBk9TPhl14SCxCjk3ZKjRZYSKUT8LJxk156didFzni3D3nGvNAUE -r6Wn+R620kauXkypjBYgFfMLwTr/gK1A2SfPlg2taGs/esG6WJqNX75xdR4FXmdx -N4Uf2WaAUH/MxIggTtcx6J28uVGRGNY2wTNLviemtACjUAmbmcwxMnSZTewyIaab -YL687d9OdQyYfJxrXry4wQdd22vRiQDy0ecAowNYRsvLIIfQen1OLm4a9qV+iuh7 -zV2zaJdAsarydyHbrn6zwkNhEDrZHB/mWZOuwtWD2PPUjO+hThIoYDf4F91CiY9u -H5lHBIdKodPKpZovm8aCaQi+hQmlIC1sdJzDhhj8AO75WGTM4uTG0CyZCHg6+rTg -bF+5MRublv1HOJvMH26iHs9h2o44iAGQEPyPgiRIXxAnfGLKbJtxxCxESj47EbD2 -hM+eXxgv8bi7BPNcP6IOtChFzi9GawFpE/zwkjEMdx4qMaWYbqnmsTT7PF3Prygd -0xirj17+HrxoIBDKB+U4m7ZFRWJeY+elTMfolgn3RDNPWkiBNyx0YYQQhvRGJzDu -58Yj1lQYrjKZOFkJqJA4eb5aGiRxMGFfVjDV0g0MtJ2c5OqsLAk4UoNa1us/xo6z -pzgUlDXoPB1wEu3YVmAnv3A52DlgRxbDAAQhN/un1yebO8bvxQU8mQMwdyg8s0f6 -dc0P65NZIEVpXJ2T4/UvwkKL7ScO3eYraUJ0yxkkuV44BrB8q4QUH3QE+piooS0Z -oX1h8XbMXLvIiBEOBF9KqdZYO0XjpQhIZ9idF7pUkJ4oaH+kaWnE4DhdRehX0Eqn -TlTAVF78PGjMx0dBp3MQsP2slAxac7/x5ciIlX6JCqzHu86ue2GNcERRDVfDzrQ9 -J5OXnP/M0Y+f3gDfRu6c2knzOv2uTppYxf5VLgggvivkAsJApNyFLvV/fNcKSUL8 -MFe3R6whm9WTi7F2ux67pv86Loqqmy7BrCCkpHjuwaznClDtonSu3Ae1cXnUvoyZ -5is7MJjmCK+lPqAIh/uwITmxgNvNLDEN4I/bYI/dMgo7P959ZAwZXyjEDCfWjtl8 -xECu1CGLDDaxtLcBEjG6V2/0/bu6oGGY+qLJ6dzdRKhHsVxIPzQB98FgjvuN+i4U -Jf/SEoPgiUFFE3yvRj+tQdAe8t+gpFcbtS7nMFPa73gF5vSHCEZ379Kc7cm5hKjT -k5YX1S91S1LpA/2/sEWIFNBFGs0+lynwk17smQlbmyFbRcmWhgr24VOR9T2CS6Jv -k1/k1kT6nd6qNn2QRHsGSQUryVQa4wXKZezi70y0vDdpd7JQTbJy4dPTUGJfJ/jf -DadsedN6eyRUmDTmZ85lRo/goB8+kTS1WaC2wSXcG3B5JEK9oOam/aVIyymUhDQS -hgv/Cdq45UFwopRPlrTJVk+Ons5vOepNriWqBZH4wSjV0yqq4HeIFTlb0xRHiJsx -mH3ZjYvN9Tyhs0xmqI3yM+kDY7Er8HLKcrpF0iJKoHhUn4ZuT49iBdedG0Vg+YUW -PgvWrjqMgwlBJKKl/KjqVGlMPTf1ghpnW/LFqn5LD2tFONdldCtLBFDGlloPIGsB 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-2qgc+bWiPJEvVqosEkJBS32lLK6SPjiBONmPrLTsE/DYKkYrcfmEpmYCDuEC4ywg -ZPPjCeSAjCj7Yj7Ky3+JMOKFdN98vY0YZN7NDlX3VZ5IE0W95iQMi7TCUdY7D8bd -/ED1TactGMNlMDykPOx/aUB2snslA2NqC7rHMrrXLIo9pps+WjqQSKpJt3bUkM7f -OAuM4URSePUqyQ+NXT3yKsiGrmsE0HivaratDGSj6RfM2MhoYscx3+GDLle+52GL -FEXYXAwFIU+KrjvgzXGj28luy8ZPXDex9B15ORmH5oLUEEMcmz/gTuki+BojjHga -6210vAxd5rKEVjo5bMQbJXQwpSMUronxaHlhbFKWtXPFhtIvM0aS3varaPxrJ0mk -mncXBZiL7nYGmKLyjBybCQu6ZDVT2ROHW54fZeRne9g= -`pragma protect end_protected - -//pragma protect end - - -`timescale 1ns / 1ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -MTh6YEb8fd47amN2cKNawaQawHld8lPdghxaCndTGXumotjbHWt413hSK/NgcsEo -Gnt8Whe7lgFMcFazYmT08o77uaPY9mP8ImzOr6doHD6yp21HOzTAKEHU93tMh13D -H7s4W/dTurxPSDUL0ipbZxO2VZAj35Pme2xieR4PHJUM7jBgdbYEn+Y/ioiS2oFl -KywnU98yjp1OAHaQ+EEa9TUS25IEaVNIOaiFbTaJX6GYvqIgtv1piLkwfSU3PyRz -bvLUm4CsqqlbZrnuxrc7aAru9jx1Yw+hae1UzJQEJRnJ0xdmSx2wjq6SvVT60BfU -tM7iyI/3vbP39OroA7oiyQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 27872 ) -`pragma protect data_block -yEFH9TMGaoqsZtm+eXDLw4g797WYufoCS6kxNzsb7PdM0sF/jwquUBGpjjNmJbHb -HZXjotlyenEI3Q1Ywatqdfzm/FtafBQLgtn2FigpJi5zeQ2y56edjPZdaVL1cOWK -hYU35erakUi8qgU5Ku72vG/8waL85moGfQ2GNmm7eJTwrlejtb7PcMu7vgPKUQ27 -qL3ywQzzTgZAmyMJ13MGU+MA6oGFDX6T03tbO0ToPLUcp2cUzLYefW6LyJsHI/7r -buaEEy58FNW28Z2xJHJ7gi0OgAUvMkkdbKx5XCePm3dwc8WVJTk/yjoUjdpUKZo1 -0TiCEVvrzuGzKp83TKq7hp+3QbrFWrjpqAq8Sg6W+DwGTgAeYC8rnHcSZ34i8rOv -7smiFfL4TdR5A/y7a99uGueqFWKG1cGJC30s5BCWlix9xdCngV+YZUQWZdznNQqB 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-ZURAbjEygRzdLZ/Xv2HHJ6SJ7IQxtuYKOXNlXFwJdRd0B94qqJcs2VivvIZpDMw5 -3r/Lg8Rb1xOX25SKgL9WBrDHmhiYjw9rnRcwiOYM0s0OP58u/i/zcddMC7C7ZYz1 -g+R+C5z+0wQQbuOUqU8RPJ8AP4DNZdi0o6V2aivhocnuH/Bm6LcfdwS96pBH/uur -dPxsKgKewGUl4uj9UOJrNuKimz7qoUOD8bdIYuES+3wh3dcGRLlIa/uALpVKnBXD -b1rG3fea6munFwr3G76O3khv4jSdn7LFZt0tv9Zjjq4s6b2fJIIjNQVRyeqE3e0v -a3KUWalg22N4bYRMYTD8COWmaszxOOfKINahj5oklukATfYb8ya+ZuIuYyOU6DOB -yUerLTCE4ISOQRie3zqkPQNDpAQJrtzt3CCegh3LaNUWKK1k1cQOl6KFBN9z5COn -C2Z07OYh9goCmKDJerUYfbrwfGFMd7y5l15Xs7mGydMBc9IJXeB9q3EL8EWf/iKe -v95d+d2yzbYZmypGMD/pdCJ3H5JKg+mZgC/0nfXnT+Bu+gHL3+ynQ1+5kA5/4sVP -tUWnifc6tbMHEa2j7e6UUNtPriEI5wGTeLBjBeXB8fOVNEdZtN2s4p+zcXJ4Cx1W -tXZH3HXoxEPbHrgQEKvKVFWrcLSHZPLvhAoYOZoQI/+RMnR9qVVRacBTwXiNhqcn -HGhU8FSTK2DowTm110M+dgi5yhVmhnguyrWx9boMk8O0h6pITJU38aMFnPIoNYis -xaY2Ku+IlpBVsm8x6ggOj19977q1U+Km8QSFiYRU2zvYP3qQxyKM2Pi5TDodINqf -ynoUDmY99F/OTVBMLLme/7q7NbnGHohS8ekiEpXiIxy8f1SkzOwWLu3Ii5oX8tBd -wAM+yozXmOaId2eFqTexhnSx7EPkRC5anQRGXsJYTJh2dnJqgRFWtRhZhyr8Dwar -CSNIXmIfflCmV0ZxO2JOWYYpdI1I35pzscvDYhJ6SsDLMWzk6Rc3MxecziG1JBqL -J1XAp3596rLeP+7MTnGpgI6q3+OUSiYRLKRFqoO1qsLzVCuH4LJrMlov2pRFl5qm -O3IVCLxI0FIxw4HQb0Xpcr8WnqstBWoBoU1CcUecCkhrFgCDWSWPZL/PTVeLVv4N -vmNurotg9dTeV1wgziZfLpahgoeqfyH94zySTHZb5vZvI6HTVWK8+TnsMy4h3ABW -eQCTxksLsuutyiNSNMcXHE+dtkeeX4CiDIdeIud10yDV/wOSRxLkpUllxZT3avMz -ssD12W4Jt82Mn5bShg7BookbbAFFA2RKiOLhvYO89wOy8jcVerZc/jJmAkcayUf2 -v54ll13dkUiHlzVVA7t0N2/M179RbeuhIDOWncw20lWh8TdfTUfqANleqARUOn4b -4bgMvrMyP6jt0fU2Zw4P0HKn90YGO7GXhcyVgi1Dp6OPuGbeiAs6wQhlMpTp9Ao0 -J9S2JNRoPu+EffjBhfOxCYxuF+qlp3fIKbBPxEofbMCDBlLJTzQNi8qQ3kisvs2K -UshK2bRjbGCbCzDuwc1aPF/xa3x1OA121Fj65VHfL98TzbRr93wb1Aq1q1w49PeP -IvBaR2pzuKWRRReBvx+J7j7eXqcgMNx3MJZN95nEqmB1/CJ30Qn090FxPM+3+xZL -Y/9G23qsiowrEfgjvkV5Y2aSdtHQJ3FELwIH4mvevhSOiaFahZIyl/b7bzngKYSW -aWTI50Qv3bAyo3e3Ozz/iQm0CN2jUSpqYDqBnGQ5ynahyls2fB9OOxKLWHrrCC2m -ndUN/C4Acg9sTqGeSGwVeChLM/tF663M3VhsQj93Z6gjMBHmFR+r9yTUkp0UyHWP -mcJSOINBj3Fc1kvgUS9cj9zksl5eiG6AG95RAxXBxrKAa8YbfXgZScu4uneKaW30 -Se/uC/k3OWxtvw4vZoIclWFJVqdH24CsV+hzWy3bjjjjqG0fH1plN4xGsNF1gqxt -OYwVWW2m2CefkW4AM5+AbeTlykXquMQOcuYKlX4Z5GV1rg0NjfT0BF5oAKFdxyLO -NwtXHGOza+AzqMhl9yo5/0WCBGmkiviUzJJI2mDMHwM0ExKgb0O4Sy5CuGnomgAO -+xLD57vjb+s9pSMs6JCmw5/5wnGxY5yPXztxc9UGT2s= -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -GgbHzgThm+pxY8qJAenj6M1nMg+PiGn8p88tojq6cijNwxinCZAmPODaDelUBiV/ -7pt9zFVTV7grht3KSqQVNS0NNFR2RViANJyed9qeVdSo+i1niQsqbPxS+dVMrEAH -GLcA4c87U2QITQVVg7mqbwa39eel3uSw5jIs/cPWgUVZwOX65uNekkTj2RtXHhFd -d0pI3dQoLqLefXHWCbn9KLkxN0XEZfWthZgyZS3VmSWHt8u7zaOvBv47vhah3n+9 -KhPDKZWleg/lH12jwGNtIA+ITKMLpp85nyYO2opdw1uFpHhBC1eWGDzHbnzEyKPz -1lNcyRWK+pqU/AY4z4Ujwg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 880 ) -`pragma protect data_block -a2PDY7wD+DHw8OF9GdySBvuAv9crSSeitt71UCe4rRD8aRaQ7B7JOb87rVKNaP+Y -P/pNSHeTA0LgZbqqvIaFxo2MZorvxVDPD9t+dcY2+NwzC+guE60XPM7TRfEWjuoe -mCDMlV1FgD1JBxxH98/PCJ9FdWIitffatZK/6h0zBd1y20gPL4NCldEah/0dlzsE -ZYlSpoKDOkf4ffYl6KkI7rK5zPl/obVTsYxOGLgnsUf6KPLFF8wfh092jhr35joP -zJPi36aMCfqrd+EVpO1Ba+4f2HgslYMGhgxzSfiDw5+qDox8mLHJrH6YiIkPecqY -DWXyb9xcF53f08/oAFMiYMqaYQZqy0QHCrNw79H6/E15d6BdVnG7SVmAlaJXlAQM -RB0LmInhsRXkwvijDTY656LDiQHUezuR6a8w3gyVo/IODO1LU8C2HZj4/NLID8GP -/VQhkQDYOCWzMwG4flLhavf8TGaLmmcsLpB30ad2uGLu5GkPCWLw/xu3pPbHtZSH -QvuUOUfXPzCXwqDLBvLC0Q3vQktfghuGVwl+G5IUeoz+79V0RJxBwiugsA+9kSPc -adazmz2dYTZQg3XuS5fEwjW/PpvmI4AO5L/to3aLL7ScLIXVnAFG/RqthmRn8UA1 -UBBmFSbYLWoZD9+yYC5Z27zL4cpg3aO6/320kboJd09lPyT9dqU7J0sepyAHbSBe -8I/h4S3KDUpk0ZY3p1dq/+WbAAJbFbysshRIobC36fJEPf61smM2n8MSfy33wg0J -Zf7Ox2L7sy2gRSdjOQdz4ewzRS6FowglhyPo5GJOkEVER5oLRxLwmFtNNZ1Z5kgg -/YQ2hAsi7TZWcksSfpM38VL3yRExRkYApK1//eUdZLGG3B0XNL3kMCvO/w7/UyDv -KyZYuYh3rOMk9HN0unGrAYYK1rq4HRc7d+p04AtPql6+UFkj4u7mNkP6Obll0+Xt -RtzuEQvQ0hZvTswe99AhgjofpEIG/YObN9S/FEHmYwBf5CzOg442K4otNJ9USGp6 -xEXuVj4EGsrgId2plsBHWdHiUVPZacoxWIRIEpW3Qy5PXHqYMv4rwxPJAciabt3r -gKxplQKOCbzsgNb+UbbiNSVMtBIAYwgkdUZarHuethhgz5M+fEa+AqiLzEkj5N+5 -3W39ohLhggzKXrAnuVk7fg== -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -module `IP_MODULE_NAME(sdhc)#( - parameter VERSION = 32'h10, - parameter DATA_BUFFER_DEPTH = 512, - parameter ADMA_DATA_WIDTH = 32, - parameter FAMILY = "TITANIUM" -) -( -input sd_rst, -input sd_base_clk, -output wire sd_int, -input sd_wp, -input sd_cd_n, -input s_axi_aclk, -input [9:0] s_axi_awaddr, -input s_axi_awvalid, -output wire s_axi_awready, -input [31:0] s_axi_wdata, -input [3:0] s_axi_wstrb, -input s_axi_wvalid, -output wire s_axi_wready, -output wire [1:0] s_axi_bresp, -output wire s_axi_bvalid, -input s_axi_bready, -input [9:0] s_axi_araddr, -input s_axi_arvalid, -output wire s_axi_arready, -output wire [1:0] s_axi_rresp, -output wire [31:0] s_axi_rdata, -output wire s_axi_rvalid, -input s_axi_rready, -input m_axi_clk, -output wire m_axi_awvalid, -output wire [31:0] m_axi_awaddr, -output wire [7:0] m_axi_awlen, -output wire [2:0] m_axi_awsize, -output wire [1:0] m_axi_awburst, -output wire [2:0] m_axi_awprot, -output wire [1:0] m_axi_awlock, -output wire [3:0] m_axi_awcache, -input m_axi_awready, -output wire [ADMA_DATA_WIDTH-1:0] m_axi_wdata, -output wire [ADMA_DATA_WIDTH/8-1:0] m_axi_wstrb, -output wire m_axi_wlast, -output wire m_axi_wvalid, -input m_axi_wready, -input [1:0] m_axi_bresp, -input m_axi_bvalid, -output wire m_axi_bready, -output wire m_axi_arvalid, -output wire [31:0] m_axi_araddr, -output wire [7:0] m_axi_arlen, -output wire [2:0] m_axi_arsize, -output wire [1:0] m_axi_arburst, -output wire [2:0] m_axi_arprot, -output wire [1:0] m_axi_arlock, -output wire [3:0] m_axi_arcache, -input m_axi_arready, -input m_axi_rvalid, -input [ADMA_DATA_WIDTH-1:0] m_axi_rdata, -input m_axi_rlast, -input [1:0] m_axi_rresp, -output wire m_axi_rready, -output wire sd_clk_hi, -output wire sd_clk_lo, -input sd_cmd_i, -output wire sd_cmd_o, -output wire sd_cmd_oe, -input [3:0] sd_dat_i, -output wire [3:0] sd_dat_o, -output wire sd_dat_oe -); -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -At8NDOCc4kD0cT6FYsAsqOLQpaMw3bVfTTiE5FP1gKwP5J3rADYscuAA9znbPvis -MBOXI5NN1IOCBhY8docHxSOtWyofhmco6KiZiSxlTAMnmzRtihgtqcUXsQWTNJTE -7whQH53NWjSMVPv2SQrHMa1RpUZnyo5STupbfD+3UW/HzNlYy+PEUQwYAxlOnG2M -LOVENWcTIh7UmStLPYTtgneJd8aOpL+baFyO2aNiHXosS76QIqvTKZQ17Q03p5K3 -i8PCPzCbmM0BxPP9kfJ10GKVxW69hi9fUcUUgGpKsloUh/zrI9OINMKLSkzf1fVU -lCxpq+G9vTz3hl52Jvm2Hw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 47504 ) -`pragma protect data_block -6DtJMbz4Ibm2QCuJndBEjY814wOQN1ovsm0I1k/eQ5F6nXmL+8tc6Dg5H5R4TyKZ -q9fOUov9KWzcH+lSAAaN/zzJYb8+4MPvp+PEgjpW1X4DgO69hTRPHwcr5cAdpFGO -zjd8bfu036TONJBBYTZzmJAkxyj2p0KU3zkIpovpC9js6bioz5OgKp5u3XMI8a+1 -BjG+bSDznAAeOMwjYNQhDyLCmyJ0dscHZu/ntQ6a/yXr9eoQ1BV1Yp7+jXu6ouCt -lypRiID+AVbz2gyP3k+PRJts2jYpffgbwCPB85AkZnua3gXlfPWAUKvYub6//sSu -TBSd82JFbBrZEZA+rg9vuzt3RmM7/cO8VfqwOcQUYP5AX5m/+4DbQcSJUJxwLGAs -njVZQ/SNcmsAdAlo9d67Z9nM9jTfdNi1QZP2oJUs0/9heUXixobakPHNc9FdtgFD -5ZHvf54jmPdw5Ko296Xf1eGabMBwGP1O69p/vyHha8zR80v72e+tNuCiNy89ERMo -wp4awRnxntoidrwrJi3lCHd7NXiORFtkmY8Zac8rMBCQ2rHig5/Jlfn3ny/8Plea -lyTGc0FkW851f5MMMMmk9fIZG9hha8nCxTHzWzlW/Gdudz6+mYEfTugrI/OWVGOr -E7XfR0Runql4ANKLVNCzzjCYWBScPSo7bI1Y4IqlHStO6y+L19DZ4Q4dd8H+g8r4 -858IUd/SFT+0PbeiKb4biad+kULqoLLCYndauDNBSwP8cCtl8YTQx4O5Pz8ne5rs -Oks9WQU3PYs5/INVUBoNE7mQaaKK+gjYbcKhaXskEKpMCopy+9QA4k855XdL38DU -oZFMr2PT/EG2w8+5Qntd/ZGQILdijMnL0GJ7pyu0b46VLj8gI/Ofb6bSNCwHASWX -/b9SxX4EhMZ1uj8ZR+rmy0CJWvm0IFdocVofbEKlqKK4cptZ3msiO31/vpph/qEz -xqnc4vBChtqGRAj0rtWEP+4btqdFohKKvxpWCiFkq1J7g6c5xKzTiYzgdBbxyJkP -aS0ep6AZMeQGBftpKhNeBNQMW4Xb6OqrO3z5K5KOFxVWsY8fTxHOVV+u7pNPZfZS -eGPsGdUjFA5YSNXonGVcSnSeTEwMnHmUnyMgzM0QU9li4jlLpUu+ExqP1ajaf511 -a19zjSgBkzGBnkx02D1mIDyrSLl+7hYpXF+e5RiPblCpRAAGeX3Grh+LvrfChIqv -3pDO1BTNUJJ4fCsZiqjUB9HiQmY9q1ln8MNWjPdUQKJ8menPjblIzrXowXAdVvJS -zYwnv0FcTgRYVuh5cZrtZfUMJn0WaDlF9jOt2fxUxdppOCxshB2HRnHQGX0gG64x -wVKdXpo3TSFyNPKqD4d6O1EKY6BQh8VafJa+ot7DyqQJQvG1BR3pGKTVfDs08uzZ -eIrrmLy2/9AxFRCZxJe0eV8V/FDOWIkN4kjVZZNhzjLP7/HG9nZai0JP/PyTCq8b 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-vio/89cf3nIywv9dv1QwUhV6VWr/DuPHQqShdDPTEoiXVbKhMHRZh9V9bJudqYjc -dUesm7cBg8hYWfJhnJWFw2fac33z3PGefVWtlSwE83XdqjEncckNOWy+JrZeD9je -VevFKbCGmKxoe6pybqA9ALo/YiV8zhT+OK7y8GbvhB7p+F4pT4nz+i+uLdxY5MQL -yWaEamEUT5srUIJLYDVWSstc5Re3E4B9eps456KQ1F1/94ZSI+IzkSlQni+my7yh -tfPYn1abp6Zqos6hJnAxT2SzLWmpW/UK5R2//Fikj6Prllx5p7WfmpUVeGCZ+yiK -9O6wCavH/bHeK3yN4mglLtLmZXG1yK7HX2dUYZh5Hq80j8krVqKHInh8fKAANGXO -cdujBcyDE9KWNo5R5KQb86mqfk2IRkf4VbG82YQ/PD88UMsS/7UwxbMXsgODFRUI -LRsGgRJbin9b05Sr0uYov/VDT9UmJmK/miBAhw0IeyEPcrTzcAqfktVSlgKUYyXk -ZBJkEqu01joWzFKvajIGOlqBvLaWRfBlOMpVsWHtKmugiWyGYq6+8790hPsMNqOU -56N43wh/wDk3gHFFQP0r6Ui3jashTlXfTOR3iRUwG/wrVQLg+PzPAaMK2hYH6o54 -V+H8i/vDn7SiXbN5UIukBhuYAeaDe5d9uyrZP2nIYKzpVlyFF+g8yGKOAcQuO783 -3bhAyNCzaqo1l0CL26ZvQO16iXDP4AWUyAKqIgnf12RfwQJy1AhPZGMtpPSyMzCw -/jr0Iu6xgJUNa05E2z2jnZlLnCnHFCE02840u1XmTR8mA27sXSgQzSiGhmr8l6yi -flXW5ac30LeVj/xE4Mqknx+lh4ctydk9bRt+fNJ5gvYUgl2zLnJomFz0Rkwpw7ZL -BEwAP2+Hnp8jYq42TbatUIKRXu9cGhkYePwFZJcbi/Ybp9TH/z7fkXT8taVpgkSl -m3S9Mn3qoZphBjmo9ht/UPU0cWNjcRcUmhENZl3Vab/zf1ZLltgRGU2+7W1cnVd2 -z5tJA/WNDw/Bg0bIpE5vSmf4YcTVnjWvBibFO1w0Zd7+tgX3PCUnQb6HVGoVPP8D -yZ1bzRGIYGDrPj45oRyvuQW9Z4s6Kw6ZcGDFtS11rucRdhbgWilKnPijcUFJrmfv -8U4mVsBdNuiyzUt2PjyVr1jhjsH56S3dN8h8F6F6/cWYF+5BmiGUaFMeinOx9Jqy -cg07i6Iccdj4X/oO+R0i7ziX3dWOlsqIkE9HXIkGG7bDyoM86yJX6cogsqCn0AX2 -Xz76Jty+69/QBGD7s/OgBgW/C1O7AfYf1Inv4eSJ4IC/cxPKU+rYZwdK+gmXdCTU -fdVn7uoqFQDmDOuKCFUyVnYHjfgPiGsBkC1FnklTs9k= -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -J7KosW2ykKi5EFdAMLz/gyhLImwj2gD50cyEdEtO9kZx69ZgsPaqC2N/Cju0QOVu -OHSsUW3EwVk2dnUxhFc96WyyvuSeNjGSIjL+g0hg7h7U19HwGkjyDWXxI0FszAgU -8MtLn0zyRn7rDX4WKBW6e0eKZyxA+4TEGoEs79gD5JEm5GGH/XXqYNlNZhIY7AnO -PM3n/egkRGqxUxmVys4D/HKwWQJqiijl51581+v420/SeIz8g33QCnsj+FVv8FQY -rG0UviGcyHwANSYYV758eDBgsPuT0uRiqdzQaml7Lr1tI9riDfjD2N92Ga/lsJ2Q -1vT8YIB5wgEhiEjyQJNk8A== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2848 ) -`pragma protect data_block -ApxS0ov/xgjlDiDohm1kcyal7qO0JfHd7W1FXJZHw0gORD2rAIYiL865p8Htsfc1 -hVQtAzpQhmgZn2DvNj7XrLJkMxtf+zUJIx/g7lTELO6oCW0VuhgpGmWS+PKB/AHL -VYS1dcgI7YlztIjcw2Bpnt95fwMvB+dikPCkLZNtzZi+9CTcLpYNzqjA7unRpwv7 -vNS+iRBUQRHHBlxRRQtXW0T8kbRVEzEEgeV8CZ52nBLY/J9iN+uuvDL+inJEMb+s -nvWRAHQyPzLTrpTW7utm+FWRxBwvbT+PAmXrLf7gaJvFDQRbSq4qs6ADjKtFTDg/ -+AKAZNu2/emGZFaXxXwmALRK7yEYrbofI6HxezIDEgnvuBbuZXXSqH8lsI0h3eGA -PPlLRxnBBpU2UjNWefnRqUOdmkAxlMyLAtxjDDjhXF+yY5lQ5tRqZQiR2DfWxXTD -UeGyEfduJZvwERdkTVlTX8thCbPHmeVNHNAcsQBZJgCIq5hYp+y4O6z8rqKOtzX/ -9+0cRd4h3BPgMJNQbD7xBBf6Eui54SBvh6l/p9Zez760ITfu2jwHWVnCa9nvFqlS -20ki8PY4KHcauwYPHuccDIYsEiMVSv7SE9VM0dz5vzRLPADoGNKOpX12E0QO7PNr -Ve9Ld+QKeL3KeVk5l1Dm67uh2Dli5986Sp+axX3mtzqqUWv2bsyoTgm5/jIzbQTy -I2/LfwalvomI6yBPDWdEyTqislROQTj0YI4DOpITzZXV2tjeU1pAny7HBezc2Ywv -D31lq5KKzxiop3IIwf9eatZLTiD/SBsRzx+L9NdT/MramZwtE7FdDwrTwnCW3CO5 -T7phr6Kckvhj23cPJEHaOBx6Hr+y5w8eI/YvA7tVZAkMq9Ja+4O+J0atNuYc/4EE -/wq9wjB6sJDjsfBleR7u+SrWgX2LwacK+MBLSfQGgBgKbQRroRzAd8qAZgKmojtt -Mxlq7pNhxmJsRsKtNbIoGuc0epuFstBuTzqn2lA/YA+04orsjM2NW08gkjQZBY9s -w353o77r4l00jLIB/lrk4UlZ5w9HwbIyFyEG9y8kC6wr1J1fAjeJq8UfCFWoPhdE -lyTzH4E7JEArLElcUurHDLizruJUx9mD/mxs76xF2jvOg39WAxNBfijtt1boqJsA -dSuVj1yfDbY7SzJbrJ0zVD6aKRqr5Vpt2MeFCfVRsvpDdsb9abmZqpF7K/QZ/gl/ -2mVCrj/LYwePiDVlkpbtbzq5yr/y1FGgBn3i+TOo8Mgc2rK/GCqDIuRQMbi12fzg -Inw9B440YGaXcApJW+az2IPgyPeXaFQU0HSPDYr2svR3coZZ9dxmgrTLC344qvhY -bYVamm/WQhRAWeY+N2COlJPrBgoMr1lL5HLhMcpIfVdGc/5wDzdw2+fN/wEL2VKD -6feFMM/Vr+/Pjo3K450YgnqWFDfe6AcpDZqB64d+4b3BduUxiFcAxwzwowXLAQ2h -CuXHyVcX8ndmk5G7fgaL+Kg6Bc3Upl1SBBFs/NcexH3aWF7DIhEjKdIleBLPDGO7 -RrX9wR8PzLLFwbh2FO8sAvU2lh1syoZmpCqcN1+rK93CmeV3EJSN6Q/8+gaKySQR -GZvEM3dof6jIAGaLYKpe4LsmYnLfPydBpiiiFYTEDJXqho66gwyqZI5wxdV1zWWf -Af51a20NbmBUtnTGeag1Wiq/rwQ9eMfprNTZ2bTAxTVJCU1ZaTi249Xx3IZs8x22 -58Euw6ivKFj+p/gvE/orHoIZKFcFl315ZgKkn5uBVJYdhCrDiLzMKZxHl7PMlTJ9 -s79g2J+SA+KyIGyIT9Bgz7+JNpVlcQky4DGS8nyggJWbQ7yoBG+f0tmmMO7V6vIh -XE7x71gom5tY49p7Bdz0NK1XNOW+/YONEKlh4Bi9/MDqYk5VhGRb+4wHvwLCu56S -HYgtuZvqrFnpzCVxq1zBepFDOcGDuT2dx+klu+FfIBhNGIZR1PtvV27jP6e8Sw8O -PB7iHac7aApHhvibH0PkUTVb+VFoBZBb2jwkkknpxlARMLcjv5vIP1XkemRWMiYu -Hy6OrvjlaiNw+kJzmxh+jr2TxFhDYZX8xzDqjSNPI2MnP9JXWm2VqnAEi5NY8/qP -u3uS3zQ4FqMupGJz/jSzyF+vmHzD9OQZtIDKkrtYbkaXaPd5gGgr50f0OIpWwgaq -QQ3Q31jaNFkRgQgDoqanT5glDd/sHTdPgNKWdKhBb41BKDCO5W7KEOaV/W5EPlHf -K6uHYF6HST+fwotOJXVd5d/jmVnXXU//wHxpQa1sH0Si55jeEu4flRICfAxlbBMx -nu8CngFhOihbvXooeYmNrLk/Qb4l088PCbNXnjCyfw6p7Y7gkRejRxanXNBY/0mp -+Uz+fnw8lUiSDcioh9E0ISH1MFCAJQuKI0wCe4l8oUzIqDQ6hUKKgvjvF3HKlu4p -LhSDQeUts6ZNX3CXkIM4igj++o3L0J5Mn/0Y6gksZAUjfzs/SPZtzfvm6/Lm0eVY -JkpBjjDtTtof2yaciBNWPToV3AqMIQv/nODrkJDUuAPpazs9jmiWAXAucoK9FkjT -sWXKDpUDTHdkAGDKL/jiDyRTmdRe+SVX+nsAgJk6ziifNVGkMdoEtjI64Cpp6cEl -tfcfI1XPcSqIE+LRttHIl4PEVJlFGz4jpQcA07FMJc2nyRCzHWpFVA/Oag/zbI7c -WQ9GWIlI2/YzW3VbFyjuJCj2M5MatZBlkqZ863vH6XCWvqAtRO1zAs9bs34WwXPR -xwVPw6TBwsWOWoWvdWfCGbk/HysKEx3gx9b/nKcyE0xxV7QuOg8Tz3+EbKPz0mfb -N8ZJNOfNYhwO6F5C4aBL53HEwzoPzkMGL6d9uKsnHmaKFfymafClWB3fPwoIITol -+DXFS2X2oPPB49LLncsAxvkxoXWB4xwtezM9r2H4vOBtzDTHCL9UQJ/N6H4ZOoYX -SEyNCXNyaHBq41P+EEWTi4lAjUSxv8N2lE/7HBFnbKKMiaivlFZ57AkwHjhR+v2j -nyanQp2AF7c0Cb+XH8Ku9BsUZSKLtoDcGv09ZsIXYcZ4I6HutNLtRM1/NNvhrumx -LZY5GA20F+E3ATrbx7lWEwei1M6jdBuJMiUl7cW99ceL8JckKYUwLq0JTaDKyG2C -4vhDfTtuk8eI2NuKtCV7pCx68nUMMGbc699cGnnrLDTRZl66l0RyPkfxQWKWCtPd -QeZX7zGSm+w6ihwmvRyjB3kz+nymnKe1aTGGABCV7oNdX/5x2iJkoRgq0PTChqNj -Q40HXwizoKUTO0f7P+2SXTLJc6lKQmzHCvvJu6Wt7AR8X2wPlAxCqqHKC+73zY3o -skilQ4PglGzfWixxzE7XbuPhl0vhEukGAMIoGH5iyh7L1WvtCObK2sKCZdE9+MSp -GfCqpX72BfSF4xFFn0IT+AIOsi9AGSrMreXPko9Lue1WiYcELcEsxpHuYZX9I6IF -iA0aqOaO6yZ15oCXDF39cotuYBNeudW9/Jvl6njbAvOEMRbRz134g3fg7ceMZbDD -7NzCaIaSljBFLMS0SVieFxaCM4upKoqI+OMmePMHgZdtNWJqmDO9duysrzre8SPh -r25XGHo7ujT3L/WVz/xeEwbLYOxBrqltcNKtIVal6R4OeIVlUSopJZyvcELBOHhG -kFH2sMU3oZrPGTGF7xN0Kg9L1fD5pn6TlU56B0PJnWEK9FbKA9hDKX/YF/ErHzMw -M5zE+dXaUaAZlIWPUSsnsf9x0ybL4BBU5XMjQrr8rYjQoZGnZxZncHI3JM0kgqxz -o2AWhMH0WmP0QLXwjMSvXA== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -Qd0gHlsfc/XIgslwDiE9K9yr3xlKZY7dRCEA4nolcKqvt+nIsq3FL92/SaoeJGIo -CKSXu7GbU3S4jqPDe0b6FxNbar2owJoFHYDQnYxbcO647ljaPpBiv6x03zTZQgpB -M5+cIbxDDXPyUwmRJLwZAuQE/U8ywGMFDSApNib2YZPLO6URh/xvjhMIO4/ityTH -GRv9t3xhHHvyPfGB2Oa10v7Y98IptlsmWMPEg/cI/gRKKUNcEiTJqTmMFYUELkF+ -5iWuLPjdOzB9CLSbubxWA7at8ubRp5/EFs8cAmvD+yzglC9Txz5rkR+x3ryQkXzr -7HxEV+XcVvxiezPBQv4Sog== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2528 ) -`pragma protect data_block -XiV3gfci+H3rlSdIMWTxzJU8cLPDqoapCBHln6HDS8BmHn/Fwma0HpaXbMxwsDc7 -m8P265VvSuSMBdnIc1kZNyhKrr0lmSQgF1Z6+4PdX7502xF1ztSIj0FALgQfGnC7 -6emIbDmkjYr0FDhelXSc3r5hh7YsHqGr0AQgUEOT1QykJleSgdfrdZnz9PrL3FXQ -5jBZheIV5/d+P+j1A9CifQ1oFaU02dQ6sOEnFwiPSqGG3c0KPn3RptdK+dP9SYR7 -e3PkVS08nBuXUyC1wO4/qmL1XAsR16kE5nyxbp0ssSmf+WKvDnsyhS2Lm/S5DE3D -hFBouoZKBO41OqKEaOPqE0hHmY8rZ+UDiZ6FpSfPSypgzwRBKCVLHHecjUSnZClU -pb6PdrJqrlZqvAMw6snEDn84vJCY1DtbZ5tkLVbzobw4d/7MXoxjfkMwBdwVWymg -Wgpu2XZ2g48IvQnd22tr3bS4G9OG2ex3fPbaOMKY/LwaaXb6F91XLsjziVWmPR6v -ODOmlrKyknnsMJNwEl8yboPzyk1liTeCxnDRS0iCxPC7St5kY0A6neB9EGyXnFKw -wj19sKpeGx44YvT1UklpZlO/6f6VgPnfCfqosldhCfofKVHA+N3nHWOyr5efrYDP -UiGGLimJOJMUlMjgwh/Q6AHGU7/lGLv+TODXQH3kGwwtdtGQMvAQmCL3hMmnUW5w -xuQYu3a4bpXhPPeg7JgWUWTJCuzUcyBvuRLofPtQqhDJEh9fJuIQKUBq4O4Z9Xua -ItGcNR5Gho1oFm90LS/1+zuQB0XMBqrK+9P5zi97CJULS9Zirgs5EGB5S8tK19zo -OHNycDnFRJ9KpXgwPY+aV4lLZ2cKqd1EVMcf/BbyrMvb7Vj8NZmeJvDJAZFZUsiu -9Vu3jVLUdcoO+0KZCAaUoxunJOFgo+d0n6hGTjMrOCzUsDfFF1VBiEGDBeOOngt3 -Kaz5MN8saN6kFL1WlLGpe8BjMckUuVqjHDYiHuC6O3vNc5YwsFkllDKcAG9RPJT8 -HWFOcQarm6eAv8F50dCks+NAcbfTHoOTXYCjlPMAUzoRPUlc1H4YiyMzali+dzsu -i7u2dK8kpsYzQ40WqkLcA3OV7MD2Ip9sk9vyBzxxi8QZIBuDPBcSIOEHLPz3MFzu -38MeoxDozztBTzGKQzP09wtnb2+s56lfOywWoaHZiHvqoAlCRvF5zdQlI+qNo5ZG -W3gzFcY1UxuaOB7Lg4p+MRD0lWTA4J4vGiIzgY9S6hd4siLlXycmbKkxUrXTaeC8 -PdmFfxe5Oy2iHgW//s0IZ+D/Q0Zgt1E4Y8rmtnpfzKga2nu/J/gSUlqYFgPju/PV -Hy+U0l239VYXVjxpC/7EUwO4ayGLktCPuOqYK8pS/jh5KP/oZxIJa4TKmoJNN8h+ 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-cmxMGg9viRysyfyTTzkucX04i/vAfY1QnJKAfrF4nHoCp+hUUslqL3MpleLKwHBO -WYFiyIXH5TYqlsD4GihlrWY7NJ3iYT1KAjerkmAxMzf+RfANhejoiEpmXh3ERZoD -Ma5gUzFeDlJA6mQxIWXjktbQpcArWhLoXsovpZXJrW4QNPoSem0FCYlpnYL+ue9e -ZOANFYeDntpubIwE0u1QNsUjXOtYErl4fPP/vi5Z8aKoftwHdXA/xJqB7EJxhHai -28JI8dfYPKKPnRQtTIhxGFy/EbtjmFq4Iym7SOuDjGGFwfn/T6XkBbx+vMPvfnO4 -0wZHtufixei9ROJLrwFY0ZBoMcs3BW5dl4y23gB1kkI/4yrSU29D/Ml5RVl53eOC -D7a/X+oC6fhBsA488tIotPnZb5OVjuTVottdPygmW+rU3JZPQ4AHxymiLSP+9c+Q -FoeuCM1em+TGHFQFls2oUUjUGH5mUt+KTJdgU71nOLMl2GWGsUYErMWOwAqY1VBT -iIKBinugO7LV9e6AGqyB4ZDage6nytueroSwfpeae6/CcIANB10p67UistI7fofA -BAsNhDzoJBMsoiHuB1SnTMR15id3BDMv2IknKs22typ00DodzNEpwOcVgkceZTZV -M2lYksxFuOgjraBhFHPGHUtqnnlD/v6KXlJAU0m9Rp1GMaH4AY84mvsgBqCW4RRC -aIhbp/+oVBcW2CT0301R8orpUOpoHhYaurgjf9hcgL2tc/flNxUX5rkHwbjse04J -rENenqhYdRa4UdyvL7g2UXVWJV1VrOiNb/0zSw9E3NM1TQZ9M9z5o9LAXjDI20PI -quHHlk7sPJX9txbZyKKsY0SObguCB2uUt/civinqGKQxSys1+w7xakkxV3T6WXH8 -auGT6bqHySMGFcdBrb/g2Bi7bdcW1ACoSBIkpBT7OE0UDiZK5w8nR0B/iQFgV6BM -fLIndYjxwQRbuIRY2ea3aiNt0EdG4wO4b3Nrqx6rdek= -`pragma protect end_protected - -//pragma protect end - - -`timescale 1 ns / 1 ns -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -DOiPrSoOsOWFMnUIePF5KkkuP9M9CD3sIOJUMse5YjGpsWljrKw3wVgiaNNbbKIA -tZZ89fOVGIkVEtqDKovfN9hhA0AvJ8mf4/+brMg7PR5hv4fEfoTvaSiSOjxminpj -hDAU9j9J0EeKG8IbY8UBCawYm3GdcS+QXpoDDPl8pGbWFzEtgpqHwLPNdotkODuL -Cy/jYYjISPMG6+XBTCDGPlB5wHTuXk4r+btUx0HJQC86NboLhzI5xocnTZkES5xw -eOtqkXEjljvu/nu/NhhumVFQWtjfe6VAKlLnz9mcqkTlGcJBfXBEcJuVurHCods7 -hizyF/UB7hJKgVj5ZWx4uQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 13568 ) -`pragma protect data_block -Vj8vE3xLVzvw27QQ44bZ2zywreLuPxzb3fPXfP14qyoFQM3H+xA9qigVzMNWUD4N -ORBewg3/lJILIjWK5K0RcF/it1gdkXzzp2leuIQM0hT0eLiBdJwsRhuIbqpf0hHO -Hl7rgQWznqwcU4x2VEuzNj4SmOvP1qrymLItkEL4BuhLora2iGN5wCqJicpy5R/P -JMevjx1kDWakIzoChrsznItkUg1bEJUih0/3Py1PLWvVI+WaJ8Njc4HWGDpDeJ80 -SSYIHHEBFckS1DQSOXqHr9FdhqAk/qNxojOrb3+mBRcibwmpgivfH9ftYpStzC5G -xo2a+ftIH2AWV4/SabJIYwNrRlN9l4ThLouwSwT6u5cimsAegrLrOC9XFSqTcqnQ -x5eqmpE2pItMPml1YbxIqjyLCND/ATjJ6eGJuuLU6pOz6lWhbayLPn+jGrJdk0se -J3Q8iJLOAa2GpxHyfdsIyItbpg/ZR7DjGDocjQfU0vnqRSvPGCpjkToiW80LHokw -raxMIEHkwQK1OHsICbp7KqWi7DD49dYTehT4K7JZeCtViSTe3USPrpwLJo1Ab0m7 -iKIzW0j5fM70z62o893Rr8JFQB10jlGPe8OxwPCdU413oMz0m0MUG+DgXfHideUa -6f3Y47Dg9w+hc52jaMGIAo+Xe6GMbyTxZ1WxpuBGMHorD2aXFJUep6DXS3DD2wTk -/0NQV8mLPGtCzuo6JGIihEmj5duwZVi7zuP+EtEm1t2VLm0ULg4U44JC904TjwCi -kRLNsd3gERmejv54N0AklYGq/fQbm6ulMZTmbMVIwXQVbwY/wbbHzddNTBncvFJW -6c6EVY83ul30bHj+lUOsqe011Php02GE3dpi39ZS+78IiFKH5Eb8f4IFJ4p1gr0x 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-GH2k7KkkczOHl7P39lAGP7oT9/o6Y2U0v6fz+SDhx6cYcCRBYgtjL2C7LC7ZEGO7 -Y7rPwvmsE4fswMVo+SHJjiedzPUW0RNsXzRYxAOIBXyQZHG0BOoaibQVdw7hSa/Q -+kIkEI0t5roGDi9SURd1c9o9rSbMjQuv+S1JhfnZiLG4HbrHArem9X6sfhTPmCHh -lD9CFM98GDWloeK6p2rpobGD5J5uwRDEpMKKRcWmLH0RNg1kwY+Dtru5rjUcURuI -W8TkCMgnk7br9+wQG9pSvge/FoGs99zDtb86OgZVEBrz0q7pY0wnQG0x1Qai7D/y -MJRg2lsn1lJnLUiU68Nqm6PXRbKYxVUuEqiW3CeHW/ZzWl6sowZS2ovm6U6L3dWb -bTtpHo9LOWriodHi4Kx+ymcr0Gcww21xwAbPCzRmunhC/qWbwDfcFEAUe+8GpkdT -H7wOA4HUuHytgoPDiY4p072aNuUuJGd+rbbTCVw6MMy4lg3yx5KW7KAHAEigBD/l -NG0fgEI14rxnLRdG89o04b7irZ6gJHV3Y/Df/CILd8xM4JpHCsA0caIjapDvDStG -E8C2APF3fxW5vb58BqgRloHNOebMgxCDVNvT5/eckj0AurBwEsz9qvXGwTrYjaur -1QgRfeqD26CG2GBLWUfmshCevm3WwLP7AFz2zevUmPp3dOMJyTzRnPAw5rUsqK0B -+wqxTtAVBGpzzUpo4XX6ZecR39GSV5xmpZwpZyscvtX9fAvHCX4gP/tDgNqbrF/t -Y1zNR5VY1F60OYLzNmjC8sKIX9A++gwKlCLWch106gIUdnUFCYPJBNLRt9k1u3ms -o7JO5X5geg6rSQfTUb/LTerqZ5IFWRNal8e0bw/BjeuRV6OjWIcVNmPTRu7kKU/3 -S7pJAonfBAr3WD7+oUtQpOubgZOiyLiEmGchAWgym30TkEiIaHytrdEp43TNzNK7 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-`undef IP_MODULE_NAME diff --git a/fpga/ip/gSDHC/gSDHC_define.vh b/fpga/ip/gSDHC/gSDHC_define.vh deleted file mode 100644 index a261877..0000000 --- a/fpga/ip/gSDHC/gSDHC_define.vh +++ /dev/null @@ -1,47 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 6.0 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -localparam DATA_BUFFER_DEPTH = 512; -localparam ADMA_DATA_WIDTH = 128; diff --git a/fpga/ip/gSDHC/gSDHC_tmpl.v b/fpga/ip/gSDHC/gSDHC_tmpl.v deleted file mode 100644 index 84b81fc..0000000 --- a/fpga/ip/gSDHC/gSDHC_tmpl.v +++ /dev/null @@ -1,111 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 6.0 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -gSDHC u_gSDHC -( - .sd_rst ( sd_rst ), - .sd_base_clk ( sd_base_clk ), - .sd_int ( sd_int ), - .sd_cd_n ( sd_cd_n ), - .sd_wp ( sd_wp ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_aclk ( s_axi_aclk ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_bready ( s_axi_bready ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rready ( s_axi_rready ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_clk ( m_axi_clk ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awready ( m_axi_awready ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awprot ( m_axi_awprot ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wready ( m_axi_wready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_bready ( m_axi_bready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arready ( m_axi_arready ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_rready ( m_axi_rready ), - .sd_clk_hi ( sd_clk_hi ), - .sd_clk_lo ( sd_clk_lo ), - .sd_cmd_i ( sd_cmd_i ), - .sd_cmd_o ( sd_cmd_o ), - .sd_cmd_oe ( sd_cmd_oe ), - .sd_dat_i ( sd_dat_i ), - .sd_dat_o ( sd_dat_o ), - .sd_dat_oe ( sd_dat_oe ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_rdata ( m_axi_rdata ), - .s_axi_wstrb ( s_axi_wstrb ) -); diff --git a/fpga/ip/gSDHC/gSDHC_tmpl.vhd b/fpga/ip/gSDHC/gSDHC_tmpl.vhd deleted file mode 100644 index 98a4d2b..0000000 --- a/fpga/ip/gSDHC/gSDHC_tmpl.vhd +++ /dev/null @@ -1,177 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component gSDHC is -port ( - sd_rst : in std_logic; - sd_base_clk : in std_logic; - sd_int : out std_logic; - sd_cd_n : in std_logic; - sd_wp : in std_logic; - s_axi_awaddr : in std_logic_vector(9 downto 0); - s_axi_aclk : in std_logic; - s_axi_awready : out std_logic; - s_axi_awvalid : in std_logic; - s_axi_wdata : in std_logic_vector(31 downto 0); - s_axi_wready : out std_logic; - s_axi_wvalid : in std_logic; - s_axi_bresp : out std_logic_vector(1 downto 0); - s_axi_bvalid : out std_logic; - s_axi_araddr : in std_logic_vector(9 downto 0); - s_axi_bready : in std_logic; - s_axi_arready : out std_logic; - s_axi_arvalid : in std_logic; - s_axi_rresp : out std_logic_vector(1 downto 0); - s_axi_rdata : out std_logic_vector(31 downto 0); - s_axi_rvalid : out std_logic; - s_axi_rready : in std_logic; - m_axi_awaddr : out std_logic_vector(31 downto 0); - m_axi_awvalid : out std_logic; - m_axi_clk : in std_logic; - m_axi_awlen : out std_logic_vector(7 downto 0); - m_axi_awready : in std_logic; - m_axi_awsize : out std_logic_vector(2 downto 0); - m_axi_awcache : out std_logic_vector(3 downto 0); - m_axi_awlock : out std_logic_vector(1 downto 0); - m_axi_awprot : out std_logic_vector(2 downto 0); - m_axi_wlast : out std_logic; - m_axi_wvalid : out std_logic; - m_axi_wready : in std_logic; - m_axi_bresp : in std_logic_vector(1 downto 0); - m_axi_bvalid : in std_logic; - m_axi_bready : out std_logic; - m_axi_arvalid : out std_logic; - m_axi_araddr : out std_logic_vector(31 downto 0); - m_axi_arlen : out std_logic_vector(7 downto 0); - m_axi_arsize : out std_logic_vector(2 downto 0); - m_axi_arburst : out std_logic_vector(1 downto 0); - m_axi_arprot : out std_logic_vector(2 downto 0); - m_axi_arlock : out std_logic_vector(1 downto 0); - m_axi_arcache : out std_logic_vector(3 downto 0); - m_axi_arready : in std_logic; - m_axi_rvalid : in std_logic; - m_axi_rlast : in std_logic; - m_axi_rresp : in std_logic_vector(1 downto 0); - m_axi_rready : out std_logic; - sd_clk_hi : out std_logic; - sd_clk_lo : out std_logic; - sd_cmd_i : in std_logic; - sd_cmd_o : out std_logic; - sd_cmd_oe : out std_logic; - sd_dat_i : in std_logic_vector(3 downto 0); - sd_dat_o : out std_logic_vector(3 downto 0); - sd_dat_oe : out std_logic; - m_axi_awburst : out std_logic_vector(1 downto 0); - m_axi_wdata : out std_logic_vector(127 downto 0); - m_axi_wstrb : out std_logic_vector(15 downto 0); - m_axi_rdata : in std_logic_vector(127 downto 0); - s_axi_wstrb : in std_logic_vector(3 downto 0) -); -end component gSDHC; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_gSDHC : gSDHC -port map ( - sd_rst => sd_rst, - sd_base_clk => sd_base_clk, - sd_int => sd_int, - sd_cd_n => sd_cd_n, - sd_wp => sd_wp, - s_axi_awaddr => s_axi_awaddr, - s_axi_aclk => s_axi_aclk, - s_axi_awready => s_axi_awready, - s_axi_awvalid => s_axi_awvalid, - s_axi_wdata => s_axi_wdata, - s_axi_wready => s_axi_wready, - s_axi_wvalid => s_axi_wvalid, - s_axi_bresp => s_axi_bresp, - s_axi_bvalid => s_axi_bvalid, - s_axi_araddr => s_axi_araddr, - s_axi_bready => s_axi_bready, - s_axi_arready => s_axi_arready, - s_axi_arvalid => s_axi_arvalid, - s_axi_rresp => s_axi_rresp, - s_axi_rdata => s_axi_rdata, - s_axi_rvalid => s_axi_rvalid, - s_axi_rready => s_axi_rready, - m_axi_awaddr => m_axi_awaddr, - m_axi_awvalid => m_axi_awvalid, - m_axi_clk => m_axi_clk, - m_axi_awlen => m_axi_awlen, - m_axi_awready => m_axi_awready, - m_axi_awsize => m_axi_awsize, - m_axi_awcache => m_axi_awcache, - m_axi_awlock => m_axi_awlock, - m_axi_awprot => m_axi_awprot, - m_axi_wlast => m_axi_wlast, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_arvalid => m_axi_arvalid, - m_axi_araddr => m_axi_araddr, - m_axi_arlen => m_axi_arlen, - m_axi_arsize => m_axi_arsize, - m_axi_arburst => m_axi_arburst, - m_axi_arprot => m_axi_arprot, - m_axi_arlock => m_axi_arlock, - m_axi_arcache => m_axi_arcache, - m_axi_arready => m_axi_arready, - m_axi_rvalid => m_axi_rvalid, - m_axi_rlast => m_axi_rlast, - m_axi_rresp => m_axi_rresp, - m_axi_rready => m_axi_rready, - sd_clk_hi => sd_clk_hi, - sd_clk_lo => sd_clk_lo, - sd_cmd_i => sd_cmd_i, - sd_cmd_o => sd_cmd_o, - sd_cmd_oe => sd_cmd_oe, - sd_dat_i => sd_dat_i, - sd_dat_o => sd_dat_o, - sd_dat_oe => sd_dat_oe, - m_axi_awburst => m_axi_awburst, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_rdata => m_axi_rdata, - s_axi_wstrb => s_axi_wstrb -); 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1'h0: 1'h1 ; - else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ; - else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i]; - end - - ////////////// - if (i==0) - begin - assign CryOut[0] = GrayCnt[0] && CarryIn; - assign CryIn [1] = ~GrayCnt[0] && CarryIn; - end - else - begin - assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]); - assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ; - end - end - - endgenerate - - wire GrayCarry = CryOut[CW_C-2]; - -/////////////////////////////////////////////////////////// - reg CntHigh = 1'h0; - - always @( posedge SysClk) - begin - if (Reset) CntHigh <= # TCo_C 1'h0; - else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry); - end - -/////////////////////////////////////////////////////////// - assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output - assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output - -/////////////////////////////////////////////////////////// - -//111111111111111111111111111111111111111111111111111111111 - -endmodule - -////////////////////// GrayCnt //////////////////////////// - -module GrayDecode -# ( - parameter DataWidht_C = 8 - ) -( - input [DataWidht_C-1:0] GrayIn, - output [DataWidht_C-1:0] HexOut -); - - //Define Parameter - /////////////////////////////////////////////////////////////// - parameter TCo_C = 1; - - localparam DW_C = DataWidht_C; - - /////////////////////////////////////////////////////////////// - reg [DW_C-1:0] Hex; - - integer i; - - always @ (GrayIn) - begin - Hex[DW_C-1]=GrayIn[DW_C-1]; - for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i]; - end - - assign HexOut = Hex; - - /////////////////////////////////////////////////////////////// - -endmodule - - - diff --git a/fpga/ip/gTSE/T120F324_devkit/apb3_2_axi4_lite.v b/fpga/ip/gTSE/T120F324_devkit/apb3_2_axi4_lite.v deleted file mode 100644 index a167005..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/apb3_2_axi4_lite.v +++ /dev/null @@ -1,215 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module apb3_2_axi4_lite#( - parameter ADDR_WTH = 10 -) -( -//Globle Signals -input clk, -input rstn, -//APB3 Slave Interface -input [ADDR_WTH-1:0] s_apb3_paddr, -input s_apb3_psel, -input s_apb3_penable, -output reg s_apb3_pready, -input s_apb3_pwrite,//0:rd; 1:wr; -input [31:0] s_apb3_pwdata, -output reg [31:0] s_apb3_prdata, -output reg s_apb3_pslverror, -//AXI4-Lite Master Interface -output reg [ADDR_WTH-1:0] m_axi_awaddr,//Write Address. byte address. -output reg m_axi_awvalid,//Write address valid. -input m_axi_awready,//Write address ready. -output reg [31:0] m_axi_wdata,//Write data bus. -output reg m_axi_wvalid,//Write valid. -input m_axi_wready,//Write ready. -input [1:0] m_axi_bresp,//Write response. -input m_axi_bvalid,//Write response valid. -output wire m_axi_bready,//Response ready. -output reg [ADDR_WTH-1:0] m_axi_araddr,//Read address. byte address. -output reg m_axi_arvalid,//Read address valid. -input m_axi_arready,//Read address ready. -input [1:0] m_axi_rresp,//Read response. -input [31:0] m_axi_rdata,//Read data. -input m_axi_rvalid,//Read valid. -output wire m_axi_rready//Read ready. -); -// Parameter Define -parameter State_idle = 3'd0; -parameter State_wsetup = 3'd1; -parameter State_rsetup = 3'd2; -parameter State_ready = 3'd3; -parameter State_err = 3'd4; - -// Register Define -reg [2:0] cur_state; -reg [2:0] next_state; -reg [7:0] timeout_cnt; - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ - -/*----------------------- FSM Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - cur_state <= State_idle; - else - cur_state <= next_state; -end - -always @(*) -begin - case(cur_state) - State_idle : - if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - next_state = State_wsetup; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) - next_state = State_rsetup; - else - next_state = State_idle; - - State_wsetup : - if((m_axi_awvalid == 1'b0) && (m_axi_wvalid == 1'b0)) - next_state = State_ready; - else if(timeout_cnt[7] == 1'b1) - next_state = State_err; - else - next_state = State_wsetup; - - State_rsetup : - if(m_axi_rvalid == 1'b1) - next_state = State_ready; - else if(timeout_cnt[7] == 1'b1) - next_state = State_err; - else - next_state = State_rsetup; - - State_ready : - next_state = State_idle; - - State_err : - next_state = State_idle; - - default : - next_state = State_idle; - endcase -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - timeout_cnt <= 8'h0; - else if((cur_state == State_wsetup) || (cur_state == State_rsetup)) - timeout_cnt <= timeout_cnt + 1'b1; - else - timeout_cnt <= 8'h0; -end - -/*----------------------- APB3 Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - s_apb3_pready <= 1'b0; - else if((cur_state == State_ready) || (cur_state == State_err)) - s_apb3_pready <= 1'b1; - else - s_apb3_pready <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - s_apb3_pslverror <= 1'b0; - else if(cur_state == State_err) - s_apb3_pslverror <= 1'b1; - else - s_apb3_pslverror <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - s_apb3_prdata <= 32'h0; - else if(m_axi_rvalid == 1'b1) - s_apb3_prdata <= m_axi_rdata; -end - -/*----------------------- AXI4-Lite Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_awaddr <= {ADDR_WTH{1'b0}}; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_awaddr <= s_apb3_paddr; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_awvalid <= 1'b0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_awvalid <= 1'b1; - else if((m_axi_awready == 1'b1) || (cur_state == State_idle)) - m_axi_awvalid <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_wdata <= 32'h0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_wdata <= s_apb3_pwdata; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_wvalid <= 1'b0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_wvalid <= 1'b1; - else if((m_axi_wready == 1'b1) || (cur_state == State_idle)) - m_axi_wvalid <= 1'b0; -end - -assign m_axi_bready = 1'b1; - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_araddr <= {ADDR_WTH{1'b0}}; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) - m_axi_araddr <= s_apb3_paddr; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_arvalid <= 1'b0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) - m_axi_arvalid <= 1'b1; - else if((m_axi_arready == 1'b1) || (cur_state == State_idle)) - m_axi_arvalid <= 1'b0; -end - -assign m_axi_rready = 1'b1; - -endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v b/fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v deleted file mode 100644 index fc32c17..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v +++ /dev/null @@ -1,61 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module axi4_st_mux -( -//Globle Signals -input mux_select, -//Mux In 0 Interface -input [7:0] tdata0, -input tvalid0, -input tlast0, -input tuser0, -output wire tready0, -//Mux In 1 Interface -input [7:0] tdata1, -input tvalid1, -input tlast1, -input tuser1, -output wire tready1, -//Mux Out Interface -output wire [7:0] tdata, -output wire tvalid, -output wire tlast, -output wire tuser, -input tready -); - -// Parameter Define - -// Register Define - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ - -assign tdata = (mux_select) ? tdata1 : tdata0; -assign tvalid = (mux_select) ? tvalid1 : tvalid0; -assign tlast = (mux_select) ? tlast1 : tlast0; -assign tuser = (mux_select) ? tuser1 : tuser0; - -assign tready0 = (mux_select) ? 1'b1 : tready; -assign tready1 = (mux_select) ? tready : 1'b1; - - -endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/gTSE.sv b/fpga/ip/gTSE/T120F324_devkit/gTSE.sv deleted file mode 100644 index 8095d65..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/gTSE.sv +++ /dev/null @@ -1,9844 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.288.2.10 -// IP Version: 7.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _4c19f37180ff465ca20760e199a0613f -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gTSE -( - input mac_reset, - input proto_reset, - output rx_mac_aclk, - input tx_mac_aclk, - output [2:0] eth_speed, - input rx_axis_clk, - output rx_axis_mac_tuser, - output rx_axis_mac_tlast, - output rx_axis_mac_tvalid, - input rx_axis_mac_tready, - input tx_axis_clk, - input tx_axis_mac_tvalid, - input tx_axis_mac_tlast, - input tx_axis_mac_tuser, - output tx_axis_mac_tready, - output [3:0] rgmii_txd_HI, - output [3:0] rgmii_txd_LO, - output rgmii_tx_ctl_HI, - output rgmii_tx_ctl_LO, - output rgmii_txc_HI, - output rgmii_txc_LO, - input [3:0] rgmii_rxd_HI, - input [3:0] rgmii_rxd_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input rgmii_rxc, - input s_axi_aclk, - output [7:0] rx_axis_mac_tdata, - input [7:0] tx_axis_mac_tdata, - input [0:0] tx_axis_mac_tstrb, - output [0:0] rx_axis_mac_tstrb, - output MdoEn, - output Mdo, - input Mdi, - output Mdc, - input [9:0] s_axi_araddr, - output s_axi_arready, - input s_axi_arvalid, - input [9:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_awvalid, - input s_axi_bready, - output [1:0] s_axi_bresp, - output s_axi_bvalid, - output [31:0] s_axi_rdata, - input s_axi_rready, - output [1:0] s_axi_rresp, - output s_axi_rvalid, - input [31:0] s_axi_wdata, - output s_axi_wready, - input s_axi_wvalid -); -`IP_MODULE_NAME(efx_mac1gbe) -#( - .VERSION (16), - .TXFIFO_EN (1'b1), - .RXFIFO_EN (1'b1), - .TXFIFO_DTH (4096), - .RXFIFO_DTH (4096), - .PHY_INTF_MODE (0), - .AXIS_DW (8), - .RGMII_RXC_EDGE (1'b1), - .RGMII_TXC_DLY (1'b1), - .INTER_PACKET_GAP (6'd12), - .MTU_FRAME_LENGTH (16'd1518), - .MAC_SOURCE_ADDRESS (48'd0), - .ENABLE_BROADCAST_FILTERING (1'b1), - .LOOPBACK_EN (1'b1), - .APBIF (1'b0), - .FAMILY ("TITANIUM") -) -u_efx_mac1gbe -( - .mac_reset ( mac_reset ), - .proto_reset ( proto_reset ), - .rx_mac_aclk ( rx_mac_aclk ), - .tx_mac_aclk ( tx_mac_aclk ), - .eth_speed ( eth_speed ), - .rx_axis_clk ( rx_axis_clk ), - .rx_axis_mac_tuser ( rx_axis_mac_tuser ), - .rx_axis_mac_tlast ( rx_axis_mac_tlast ), - .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), - .rx_axis_mac_tready ( rx_axis_mac_tready ), - .tx_axis_clk ( tx_axis_clk ), - .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), - .tx_axis_mac_tlast ( tx_axis_mac_tlast ), - .tx_axis_mac_tuser ( tx_axis_mac_tuser ), - .tx_axis_mac_tready ( tx_axis_mac_tready ), - .rgmii_txd_HI ( rgmii_txd_HI ), - .rgmii_txd_LO ( rgmii_txd_LO ), - .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), - .rgmii_txc_HI ( rgmii_txc_HI ), - .rgmii_txc_LO ( rgmii_txc_LO ), - .rgmii_rxd_HI ( rgmii_rxd_HI ), - .rgmii_rxd_LO ( rgmii_rxd_LO ), - .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), - .rgmii_rxc ( rgmii_rxc ), - .s_axi_aclk ( s_axi_aclk ), - .rx_axis_mac_tdata ( rx_axis_mac_tdata ), - .tx_axis_mac_tdata ( tx_axis_mac_tdata ), - .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), - .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), - .MdoEn ( MdoEn ), - .Mdo ( Mdo ), - .Mdi ( Mdi ), - .Mdc ( Mdc ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rready ( s_axi_rready ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ) -); -endmodule - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_top) # ( - parameter FAMILY = "TRION", // New Param - parameter SYNC_CLK = 0, - parameter BYPASS_RESET_SYNC = 0, // New Param - parameter SYNC_STAGE = 2, // New Param - parameter MODE = "STANDARD", - parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) - parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) - parameter PIPELINE_REG = 1, // Reverted (By default is ON) - parameter OPTIONAL_FLAGS = 1, // Reverted - parameter OUTPUT_REG = 0, - parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_FULL_ASSERT = 27, - parameter PROG_FULL_NEGATE = 23, - parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_EMPTY_ASSERT = 5, - parameter PROG_EMPTY_NEGATE = 7, - parameter ALMOST_FLAG = OPTIONAL_FLAGS, - parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, - parameter ASYM_WIDTH_RATIO = 4, - parameter WADDR_WIDTH = depth2width(DEPTH), - parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), - parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), - parameter RADDR_WIDTH = depth2width(RD_DEPTH), - parameter ENDIANESS = 0, - parameter OVERFLOW_PROTECT = 1, - parameter UNDERFLOW_PROTECT = 1, - parameter RAM_STYLE = "block_ram" - -)( - input wire a_rst_i, - input wire a_wr_rst_i, - input wire a_rd_rst_i, - input wire clk_i, - input wire wr_clk_i, - input wire rd_clk_i, - input wire wr_en_i, - input wire rd_en_i, - input wire [DATA_WIDTH-1:0] wdata, - output wire almost_full_o, - output wire prog_full_o, - output wire full_o, - output wire overflow_o, - output wire wr_ack_o, - output wire [WADDR_WIDTH :0] datacount_o, - output wire [WADDR_WIDTH :0] wr_datacount_o, - output wire empty_o, - output wire almost_empty_o, - output wire prog_empty_o, - output wire underflow_o, - output wire rd_valid_o, - output wire [RDATA_WIDTH-1:0] rdata, - output wire [RADDR_WIDTH :0] rd_datacount_o, - output wire rst_busy -); - -localparam WR_DEPTH = DEPTH; -localparam WDATA_WIDTH = DATA_WIDTH; -localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; - -wire wr_rst_int; -wire rd_rst_int; -wire wr_en_int; -wire rd_en_int; -wire [WADDR_WIDTH-1:0] waddr; -wire [RADDR_WIDTH-1:0] raddr; -wire wr_clk_int; -wire rd_clk_int; -wire [WADDR_WIDTH :0] wr_datacount_int; -wire [RADDR_WIDTH :0] rd_datacount_int; - -generate - if (ASYM_WIDTH_RATIO == 4) begin - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - assign datacount_o = wr_datacount_int; - assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - end - end - else begin - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - end - end - - if (!SYNC_CLK) begin - //(* async_reg = "true" *) reg [1:0] wr_rst; - //(* async_reg = "true" *) reg [1:0] rd_rst; - // - //always @ (posedge wr_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // wr_rst <= 2'b11; - // else - // wr_rst <= {wr_rst[0],1'b0}; - //end - // - //always @ (posedge rd_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // rd_rst <= 2'b11; - // else - // rd_rst <= {rd_rst[0],1'b0}; - //end - - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_wr_rst_i; - assign rd_rst_int = a_rd_rst_i; - assign rst_busy = 1'b0; - end - else begin - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_wr_rst ( - .clk (wr_clk_int), - .reset (a_rst_i), - .d_o (wr_rst_int) - ); - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_rd_rst ( - .clk (rd_clk_int), - .reset (a_rst_i), - .d_o (rd_rst_int) - ); - assign rst_busy = wr_rst_int | rd_rst_int; - end - - end - else begin - //(* async_reg = "true" *) reg [1:0] a_rst; - // - //always @ (posedge clk_i or posedge a_rst_i) begin - // if (a_rst_i) - // a_rst <= 2'b11; - // else - // a_rst <= {a_rst[0],1'b0}; - //end - wire a_rst; - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_a_rst ( - .clk (clk_i), - .reset (a_rst_i), - .d_o (a_rst) - ); - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_rst_i; - assign rd_rst_int = a_rst_i; - assign rst_busy = 1'b0; - end - else begin - assign wr_rst_int = a_rst; - assign rd_rst_int = a_rst; - assign rst_busy = wr_rst_int | rd_rst_int; - end - end -endgenerate - -`IP_MODULE_NAME(efx_fifo_ram) # ( - .FAMILY (FAMILY), - .WR_DEPTH (WR_DEPTH), - .RD_DEPTH (RD_DEPTH), - .WDATA_WIDTH (WDATA_WIDTH), - .RDATA_WIDTH (RDATA_WIDTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .OUTPUT_REG (OUTPUT_REG), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .ENDIANESS (ENDIANESS), - .RAM_STYLE (RAM_STYLE) -) xefx_fifo_ram ( - .wdata (wdata), - .waddr (waddr), - .raddr (raddr), - .we (wr_en_int), - .re (rd_en_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .rdata (rdata) -); - -`IP_MODULE_NAME(efx_fifo_ctl) # ( - .SYNC_CLK (SYNC_CLK), - .SYNC_STAGE (SYNC_STAGE), - .MODE (MODE), - .WR_DEPTH (WR_DEPTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .PIPELINE_REG (PIPELINE_REG), - .ALMOST_FLAG (ALMOST_FLAG), - .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), - .PROG_FULL_ASSERT (PROG_FULL_ASSERT), - .PROG_FULL_NEGATE (PROG_FULL_NEGATE), - .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), - .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), - .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), - .OUTPUT_REG (OUTPUT_REG), - .HANDSHAKE_FLAG (HANDSHAKE_FLAG), - .OVERFLOW_PROTECT (OVERFLOW_PROTECT), - .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) -) xefx_fifo_ctl ( - .wr_rst (wr_rst_int), - .rd_rst (rd_rst_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .we (wr_en_i), - .re (rd_en_i), - .wr_full (full_o), - .wr_ack (wr_ack_o), - .rd_empty (empty_o), - .wr_almost_full (almost_full_o), - .rd_almost_empty (almost_empty_o), - .wr_prog_full (prog_full_o), - .rd_prog_empty (prog_empty_o), - .wr_en_int (wr_en_int), - .rd_en_int (rd_en_int), - .waddr (waddr), - .raddr (raddr), - .wr_datacount (wr_datacount_int), - .rd_datacount (rd_datacount_int), - .rd_vld (rd_valid_o), - .wr_overflow (overflow_o), - .rd_underflow (underflow_o) -); - -function integer depth2width; -input [31:0] depth; -begin : fnDepth2Width - if (depth > 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p -yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU -De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF -GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh -0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r -mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q -z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO 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-7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM -DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI -8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 -JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD -UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 -g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY -XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 -eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ -PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r -uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ -OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx -X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI -bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe -/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV -Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL -qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ -4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa -XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc -Ei7EaFpheCmlTJyxUg8TdA== -`pragma protect end_protected - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx>> 2); - assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); - BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_5 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_5_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .io_asyncReset (io_asyncReset ) //i - ); - BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_6 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_6_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset) //i - ); - VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b system_cores_0_logic_cpu ( - .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o - .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i - .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o - .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o - .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o - .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o - .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o - .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o - .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o - .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i - .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i - .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i - .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i - .timerInterrupt (_zz_timerInterrupt ), //i - .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i - .softwareInterrupt (_zz_softwareInterrupt ), //i - .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i - .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o - .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i - .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i - .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i - .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o - .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o - .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o - .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i - .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o - .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o - .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i - .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i - .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_jtagBridge ( - .io_ctrl_tdi (jtagCtrl_tdi ), //i - .io_ctrl_enable (jtagCtrl_enable ), //i - .io_ctrl_capture (jtagCtrl_capture ), //i - .io_ctrl_shift (jtagCtrl_shift ), //i - .io_ctrl_update (jtagCtrl_update ), //i - .io_ctrl_reset (jtagCtrl_reset ), //i - .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i - .jtagCtrl_tck (jtagCtrl_tck ) //i - ); - SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_debugger ( - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o - .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i - .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o - .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o - .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i - .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_7 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_7_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .system_cores_0_debugReset (system_cores_0_debugReset) //i - ); - BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b bmbDecoder_4 ( - .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i - .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i - .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_exclusiveMonitor_logic ( - .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i - .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i - .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i - .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i - ); - BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_iBus_bmb_decoder ( - .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i - ); - BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_arbiter ( - .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i - .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o - .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i - .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i - .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o - .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i - .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o - .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o - .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o - .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o - .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o - .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i - .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i - .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o - .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o - .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o - .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o - .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i - .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_decoder ( - .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o - .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i - .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o - .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b system_ramA_logic ( - .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i - .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i - .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i - .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify_1 ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b system_bmbPeripheral_bmb_decoder ( - .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i - .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i - .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i - .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i - .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i - .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i - .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i - .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o - .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i - .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o - .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o - .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o - .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i - .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o - .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i - .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i - .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i - .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i - .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o - .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i - .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o - .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o - .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o - .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i - .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o - .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i - .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i - .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i - .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i - .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o - .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i - .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o - .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o - .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o - .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i - .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o - .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i - .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i - .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i - .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b system_clint_logic ( - .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o - .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o - .io_time (system_clint_logic_io_time[63:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_uart_0_io_logic ( - .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i - .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i - .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i - .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o - .io_uart_rxd (system_uart_0_io_rxd ), //i - .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_spi_0_io_logic ( - .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o - .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i - .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i - .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o - .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o - .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o - .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o - .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o - .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i - .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i - .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i - .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i - .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o - .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o - .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b io_apbSlave_0_logic ( - .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o - .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o - .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o - .io_output_PREADY (io_apbSlave_0_PREADY ), //i - .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o - .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o - .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i - .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - initial begin - debugCd_logic_holdingLogic_resetCounter = 12'h0; - debugCd_logic_outputReset = 1'b1; - end - - always @(*) begin - debugCd_logic_inputResetTrigger = 1'b0; - if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin - debugCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - debugCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); - assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; - always @(*) begin - systemCd_logic_inputResetTrigger = 1'b0; - if(bufferCC_6_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - if(bufferCC_7_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - systemCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); - assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; - assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; - assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; - assign system_cores_0_iBus_cmd_payload_last = 1'b1; - assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_iBus_rsp_ready = 1'b1; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; - always @(*) begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; - case(system_cores_0_logic_cpu_dBus_cmd_payload_size) - 3'b000 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; - end - 3'b001 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; - end - 3'b010 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; - end - 3'b011 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; - end - 3'b100 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; - end - 3'b101 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; - end - 3'b110 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; - end - default : begin - end - endcase - end - - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; - always @(*) begin - system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; - if(when_DataCache_l532) begin - system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; - end - end - - assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; - assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; - assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; - assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; - assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; - always @(*) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; - if(when_Stream_l368) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); - assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; - assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; - assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; - assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; - assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; - assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; - always @(*) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; - if(when_Stream_l368_1) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; - assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; - assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; - assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; - always @(*) begin - case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) - 2'b00 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; - end - 2'b01 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; - end - default : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; - end - endcase - end - - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; - assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; - assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; - assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; - assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; - assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; - assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; - assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); - always @(*) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_2) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; - always @(*) begin - _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_3) begin - _zz_io_input_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; - assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; - assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); - assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; - assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; - assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; - assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; - assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; - assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; - assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; - assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; - assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; - assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; - assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; - assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; - if(when_Stream_l368_4) begin - system_fabric_iBus_bmb_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); - assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; - assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; - assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; - assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; - assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; - assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; - assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; - assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; - assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; - assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; - assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; - assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; - assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; - assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; - assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; - assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); - always @(*) begin - system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_5) begin - system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; - assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; - assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; - assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; - assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; - always @(*) begin - _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_6) begin - _zz_io_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; - assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; - assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); - assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; - assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; - assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; - assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; - assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; - assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; - assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; - assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); - assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); - assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); - assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; - assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; - assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; - assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; - assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; - assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; - assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; - assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; - assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; - assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_plic_logic_bus_readHaltTrigger = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bus_readHaltTrigger = 1'b1; - end - end - - assign system_plic_logic_bus_writeHaltTrigger = 1'b0; - assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); - assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); - always @(*) begin - _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; - if(when_Stream_l368_7) begin - _zz_system_plic_logic_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); - assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; - assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; - assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; - assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; - assign system_plic_logic_bus_rsp_payload_last = 1'b1; - assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; - end - 22'h001000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; - end - 22'h000010 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; - end - 22'h200000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; - end - 22'h200004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; - end - 22'h002000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; - end - default : begin - end - endcase - end - - assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; - assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; - assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; - assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; - assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; - assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); - assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; - assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); - assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); - assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); - assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; - assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; - always @(*) begin - system_plic_logic_bridge_claim_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_valid = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_claim_payload = 3'bxxx; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_completion_valid = 1'b0; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_valid = 1'b1; - end - end - - always @(*) begin - system_plic_logic_bridge_completion_payload = 3'bxxx; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; - end - end - - always @(*) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(when_BmbSlaveFactory_l71) begin - if(system_plic_logic_bus_askWrite) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(system_plic_logic_bus_askRead) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - end - end - - assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; - assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); - assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); - always @(*) begin - system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); - if(system_plic_logic_bridge_coherencyStall_willClear) begin - system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; - end - end - - assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); - assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; - always @(*) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doWrite) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; - assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; - assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; - assign when_BmbSlaveFactory_l71 = 1'b1; - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); - end - if(debugCd_logic_inputResetTrigger) begin - debugCd_logic_holdingLogic_resetCounter <= 12'h0; - end - debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); - end - if(systemCd_logic_inputResetTrigger) begin - systemCd_logic_holdingLogic_resetCounter <= 6'h0; - end - systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - io_systemReset <= systemCd_logic_outputReset; - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; - _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; - _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; - system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; - system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; - system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; - end - if(system_bridge_bmb_cmd_ready) begin - system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; - system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; - system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; - system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; - system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; - system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; - system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; - system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; - end - if(_zz_io_input_rsp_ready_1) begin - _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - end - _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; - _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready_1) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; - _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; - _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; - _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; - end - system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); - system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); - system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); - system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; - end - - always @(posedge io_systemClk) begin - system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_fabric_iBus_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; - system_plic_logic_bridge_coherencyStall_value <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; - end else begin - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; - end - if(system_bridge_bmb_cmd_valid) begin - system_bridge_bmb_cmd_rValid <= 1'b1; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_rValid <= 1'b0; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; - end - if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; - end - if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_uart_0_io_logic_io_bus_rsp_valid) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; - end - if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - end - if(when_PlicGateway_l21) begin - system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; - end - if(when_PlicGateway_l21_1) begin - system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); - end - if(system_plic_logic_bridge_claim_valid) begin - case(system_plic_logic_bridge_claim_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - default : begin - end - endcase - end - if(system_plic_logic_bridge_completion_valid) begin - case(system_plic_logic_bridge_completion_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - default : begin - end - endcase - end - system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h000010 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h200000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h002000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; - end else begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; - end - end - - -endmodule - -module BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [15:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [3:0] io_input_rsp_payload_fragment_context, - output [15:0] io_output_PADDR, - output [0:0] io_output_PSEL, - output io_output_PENABLE, - input io_output_PREADY, - output io_output_PWRITE, - output [31:0] io_output_PWDATA, - input [31:0] io_output_PRDATA, - input io_output_PSLVERROR, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire bmbBuffer_cmd_valid; - reg bmbBuffer_cmd_ready; - wire bmbBuffer_cmd_payload_last; - wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; - wire [15:0] bmbBuffer_cmd_payload_fragment_address; - wire [1:0] bmbBuffer_cmd_payload_fragment_length; - wire [31:0] bmbBuffer_cmd_payload_fragment_data; - wire [3:0] bmbBuffer_cmd_payload_fragment_context; - reg bmbBuffer_rsp_valid; - reg bmbBuffer_rsp_ready; - wire bmbBuffer_rsp_payload_last; - reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_payload_fragment_context; - wire io_input_rsp_isStall; - wire _zz_io_input_cmd_ready; - wire bmbBuffer_rsp_m2sPipe_valid; - wire bmbBuffer_rsp_m2sPipe_ready; - wire bmbBuffer_rsp_m2sPipe_payload_last; - wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; - reg bmbBuffer_rsp_rValid; - reg bmbBuffer_rsp_rData_last; - reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; - reg [31:0] bmbBuffer_rsp_rData_fragment_data; - reg [3:0] bmbBuffer_rsp_rData_fragment_context; - wire when_Stream_l368; - reg state; - wire when_BmbToApb3Bridge_l46; - - assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); - assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); - assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; - assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - always @(*) begin - bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; - if(when_Stream_l368) begin - bmbBuffer_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); - assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; - assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; - assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; - assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; - assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; - always @(*) begin - bmbBuffer_cmd_ready = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_cmd_ready = 1'b1; - end - end - end - - assign io_output_PSEL[0] = bmbBuffer_cmd_valid; - assign io_output_PENABLE = state; - assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); - assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; - assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; - always @(*) begin - bmbBuffer_rsp_valid = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_rsp_valid = 1'b1; - end - end - end - - assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; - assign when_BmbToApb3Bridge_l46 = (! state); - assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign bmbBuffer_rsp_payload_last = 1'b1; - always @(*) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b0; - if(io_output_PSLVERROR) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b1; - end - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - bmbBuffer_rsp_rValid <= 1'b0; - state <= 1'b0; - end else begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; - end - if(when_BmbToApb3Bridge_l46) begin - state <= bmbBuffer_cmd_valid; - end else begin - if(io_output_PREADY) begin - state <= 1'b0; - end - end - end - end - - always @(posedge io_systemClk) begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; - bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; - bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; - bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; - end - end - - -endmodule - -module BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_ctrl_cmd_valid, - output io_ctrl_cmd_ready, - input io_ctrl_cmd_payload_last, - input [0:0] io_ctrl_cmd_payload_fragment_opcode, - input [11:0] io_ctrl_cmd_payload_fragment_address, - input [1:0] io_ctrl_cmd_payload_fragment_length, - input [31:0] io_ctrl_cmd_payload_fragment_data, - input [3:0] io_ctrl_cmd_payload_fragment_context, - output io_ctrl_rsp_valid, - input io_ctrl_rsp_ready, - output io_ctrl_rsp_payload_last, - output [0:0] io_ctrl_rsp_payload_fragment_opcode, - output [31:0] io_ctrl_rsp_payload_fragment_data, - output [3:0] io_ctrl_rsp_payload_fragment_context, - output [0:0] io_spi_sclk_write, - output io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output [0:0] io_spi_data_0_write, - output io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output [0:0] io_spi_data_1_write, - output io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output [0:0] io_spi_data_2_write, - output io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; - wire ctrl_io_cmd_ready; - wire ctrl_io_rsp_valid; - wire [7:0] ctrl_io_rsp_payload_data; - wire [0:0] ctrl_io_spi_sclk_write; - wire [0:0] ctrl_io_spi_ss; - wire [0:0] ctrl_io_spi_data_0_write; - wire ctrl_io_spi_data_0_writeEnable; - wire [0:0] ctrl_io_spi_data_1_write; - wire ctrl_io_spi_data_1_writeEnable; - wire [0:0] ctrl_io_spi_data_2_write; - wire ctrl_io_spi_data_2_writeEnable; - wire [0:0] ctrl_io_spi_data_3_write; - wire ctrl_io_spi_data_3_writeEnable; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; - wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_ctrl_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_ctrl_rsp_valid_1; - reg _zz_io_ctrl_rsp_valid_2; - reg _zz_io_ctrl_rsp_payload_last; - reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; - reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_ctrl_cmd_fire; - wire factory_doWrite; - wire io_ctrl_cmd_fire_1; - wire factory_doRead; - wire [31:0] mapping_cmdLogic_writeData; - reg mapping_cmdLogic_doRegular; - reg mapping_cmdLogic_doWriteLarge; - reg mapping_cmdLogic_doReadWriteLarge; - wire mapping_cmdLogic_streamUnbuffered_valid; - wire mapping_cmdLogic_streamUnbuffered_ready; - wire mapping_cmdLogic_streamUnbuffered_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_payload_read; - wire mapping_cmdLogic_streamUnbuffered_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - wire when_Stream_l368_1; - wire ctrl_io_rsp_toStream_valid; - wire ctrl_io_rsp_toStream_ready; - wire [7:0] ctrl_io_rsp_toStream_payload_data; - reg _zz_io_pop_ready; - reg _zz_io_pop_ready_1; - reg mapping_interruptCtrl_cmdIntEnable; - reg mapping_interruptCtrl_rspIntEnable; - wire mapping_interruptCtrl_cmdInt; - wire mapping_interruptCtrl_rspInt; - wire mapping_interruptCtrl_interrupt; - reg _zz_io_config_kind_cpol; - reg _zz_io_config_kind_cpha; - reg [1:0] _zz_io_config_mod; - reg [11:0] _zz_io_config_sclkToogle; - reg [11:0] _zz_io_config_ss_setup; - reg [11:0] _zz_io_config_ss_hold; - reg [11:0] _zz_io_config_ss_disable; - reg [0:0] _zz_io_config_ss_activeHigh; - wire [1:0] _zz_io_config_kind_cpol_1; - - TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ctrl ( - .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i - .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i - .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i - .io_config_mod (_zz_io_config_mod[1:0] ), //i - .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i - .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i - .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i - .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i - .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i - .io_cmd_ready (ctrl_io_cmd_ready ), //o - .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i - .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i - .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i - .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i - .io_rsp_valid (ctrl_io_rsp_valid ), //o - .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o - .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (io_spi_data_0_read ), //i - .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (io_spi_data_1_read ), //i - .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (io_spi_data_2_read ), //i - .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (io_spi_data_3_read ), //i - .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o - .io_spi_ss (ctrl_io_spi_ss ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( - .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i - .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o - .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i - .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i - .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i - .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i - .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o - .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i - .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o - .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o - .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o - .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o - .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ctrl_io_rsp_queueWithOccupancy ( - .io_push_valid (ctrl_io_rsp_toStream_valid ), //i - .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o - .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i - .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o - .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_ctrl_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); - assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - 12'h004 : begin - factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; - end - 12'h00c : begin - factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; - factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; - factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; - factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; - end - 12'h058 : begin - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - default : begin - end - endcase - end - - assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - always @(*) begin - mapping_cmdLogic_doRegular = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doRegular = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h050 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doReadWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h054 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doReadWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); - assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; - assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); - always @(*) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_1) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; - assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; - assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; - assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; - always @(*) begin - _zz_io_pop_ready = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doRead) begin - _zz_io_pop_ready = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - _zz_io_pop_ready_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h058 : begin - if(factory_doRead) begin - _zz_io_pop_ready_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); - assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); - assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); - assign io_spi_sclk_write = ctrl_io_spi_sclk_write; - assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; - assign io_spi_data_0_write = ctrl_io_spi_data_0_write; - assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; - assign io_spi_data_1_write = ctrl_io_spi_data_1_write; - assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; - assign io_spi_data_2_write = ctrl_io_spi_data_2_write; - assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; - assign io_spi_data_3_write = ctrl_io_spi_data_3_write; - assign io_spi_ss = ctrl_io_spi_ss; - assign io_interrupt = mapping_interruptCtrl_interrupt; - assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; - assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_ctrl_rsp_valid_2 <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; - mapping_interruptCtrl_cmdIntEnable <= 1'b0; - mapping_interruptCtrl_rspIntEnable <= 1'b0; - _zz_io_config_ss_activeHigh <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h00c : begin - if(factory_doWrite) begin - mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; - mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; - end - end - 12'h030 : begin - if(factory_doWrite) begin - _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h008 : begin - if(factory_doWrite) begin - _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; - _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; - _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; - end - end - 12'h020 : begin - if(factory_doWrite) begin - _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h024 : begin - if(factory_doWrite) begin - _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h028 : begin - if(factory_doWrite) begin - _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h02c : begin - if(factory_doWrite) begin - _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - default : begin - end - endcase - end - - -endmodule - -module BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [5:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output io_uart_txd, - input io_uart_rxd, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; - wire uartCtrl_1_io_write_ready; - wire uartCtrl_1_io_read_valid; - wire [7:0] uartCtrl_1_io_read_payload; - wire uartCtrl_1_io_uart_txd; - wire uartCtrl_1_io_readError; - wire uartCtrl_1_io_readBreak; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; - wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; - wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; - wire [0:0] _zz_bridge_misc_readError; - wire [0:0] _zz_bridge_misc_readOverflowError; - wire [0:0] _zz_bridge_misc_breakDetected; - wire [0:0] _zz_bridge_misc_doBreak; - wire [0:0] _zz_bridge_misc_doBreak_1; - wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - wire [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [3:0] busCtrl_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_busCtrl_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_bus_cmd_fire; - wire busCtrl_doWrite; - wire io_bus_cmd_fire_1; - wire busCtrl_doRead; - reg [2:0] bridge_uartConfigReg_frame_dataLength; - reg [0:0] bridge_uartConfigReg_frame_stop; - reg [1:0] bridge_uartConfigReg_frame_parity; - reg [19:0] bridge_uartConfigReg_clockDivider; - reg _zz_bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_ready; - wire [7:0] bridge_write_streamUnbuffered_payload; - reg bridge_read_streamBreaked_valid; - reg bridge_read_streamBreaked_ready; - wire [7:0] bridge_read_streamBreaked_payload; - reg bridge_interruptCtrl_writeIntEnable; - reg bridge_interruptCtrl_readIntEnable; - wire bridge_interruptCtrl_readInt; - wire bridge_interruptCtrl_writeInt; - wire bridge_interruptCtrl_interrupt; - reg bridge_misc_readError; - reg when_BusSlaveFactory_l335; - wire when_BusSlaveFactory_l341; - reg bridge_misc_readOverflowError; - reg when_BusSlaveFactory_l335_1; - wire when_BusSlaveFactory_l341_1; - wire uartCtrl_1_io_read_isStall; - reg bridge_misc_breakDetected; - reg uartCtrl_1_io_readBreak_regNext; - wire when_UartCtrl_l155; - reg when_BusSlaveFactory_l335_2; - wire when_BusSlaveFactory_l341_2; - reg bridge_misc_doBreak; - reg when_BusSlaveFactory_l371; - wire when_BusSlaveFactory_l373; - reg when_BusSlaveFactory_l335_3; - wire when_BusSlaveFactory_l341_3; - wire [1:0] _zz_bridge_uartConfigReg_frame_parity; - wire [0:0] _zz_bridge_uartConfigReg_frame_stop; - wire when_BmbSlaveFactory_l71; - `ifndef SYNTHESIS - reg [23:0] bridge_uartConfigReg_frame_stop_string; - reg [31:0] bridge_uartConfigReg_frame_parity_string; - reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; - reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; - `endif - - - assign _zz_bridge_misc_readError = 1'b0; - assign _zz_bridge_misc_readOverflowError = 1'b0; - assign _zz_bridge_misc_breakDetected = 1'b0; - assign _zz_bridge_misc_doBreak = 1'b1; - assign _zz_bridge_misc_doBreak_1 = 1'b0; - assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); - assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; - assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; - UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1 ( - .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i - .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i - .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i - .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i - .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i - .io_write_ready (uartCtrl_1_io_write_ready ), //o - .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i - .io_read_valid (uartCtrl_1_io_read_valid ), //o - .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i - .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o - .io_uart_txd (uartCtrl_1_io_uart_txd ), //o - .io_uart_rxd (io_uart_rxd ), //i - .io_readError (uartCtrl_1_io_readError ), //o - .io_writeBreak (bridge_misc_doBreak ), //i - .io_readBreak (uartCtrl_1_io_readBreak ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b bridge_write_streamUnbuffered_queueWithOccupancy ( - .io_push_valid (bridge_write_streamUnbuffered_valid ), //i - .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i - .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_write_ready ), //i - .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1_io_read_queueWithOccupancy ( - .io_push_valid (uartCtrl_1_io_read_valid ), //i - .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i - .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(bridge_uartConfigReg_frame_stop) - UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; - default : bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(bridge_uartConfigReg_frame_parity) - UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; - default : bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_parity) - UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; - default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_stop) - UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; - default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - `endif - - assign io_uart_txd = uartCtrl_1_io_uart_txd; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_busCtrl_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_busCtrl_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign busCtrl_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; - end - 6'h04 : begin - busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; - end - 6'h10 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; - busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - always @(*) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doWrite) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; - assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; - assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - always @(*) begin - bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - if(uartCtrl_1_io_readBreak) begin - bridge_read_streamBreaked_valid = 1'b0; - end - end - - always @(*) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; - if(uartCtrl_1_io_readBreak) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; - end - end - - assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - always @(*) begin - bridge_read_streamBreaked_ready = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doRead) begin - bridge_read_streamBreaked_ready = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); - assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); - assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); - always @(*) begin - when_BusSlaveFactory_l335 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; - always @(*) begin - when_BusSlaveFactory_l335_1 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; - assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); - assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); - always @(*) begin - when_BusSlaveFactory_l335_2 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l371 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l371 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l335_3 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; - assign io_interrupt = bridge_interruptCtrl_interrupt; - assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; - assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - bridge_uartConfigReg_clockDivider <= 20'h0; - bridge_uartConfigReg_clockDivider <= 20'h00035; - bridge_uartConfigReg_frame_dataLength <= 3'b111; - bridge_uartConfigReg_frame_parity <= UartParityType_NONE; - bridge_uartConfigReg_frame_stop <= UartStopType_ONE; - bridge_interruptCtrl_writeIntEnable <= 1'b0; - bridge_interruptCtrl_readIntEnable <= 1'b0; - bridge_misc_readError <= 1'b0; - bridge_misc_readOverflowError <= 1'b0; - bridge_misc_breakDetected <= 1'b0; - bridge_misc_doBreak <= 1'b0; - end else begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); - end - if(when_BusSlaveFactory_l335) begin - if(when_BusSlaveFactory_l341) begin - bridge_misc_readError <= _zz_bridge_misc_readError[0]; - end - end - if(uartCtrl_1_io_readError) begin - bridge_misc_readError <= 1'b1; - end - if(when_BusSlaveFactory_l335_1) begin - if(when_BusSlaveFactory_l341_1) begin - bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; - end - end - if(uartCtrl_1_io_read_isStall) begin - bridge_misc_readOverflowError <= 1'b1; - end - if(when_UartCtrl_l155) begin - bridge_misc_breakDetected <= 1'b1; - end - if(when_BusSlaveFactory_l335_2) begin - if(when_BusSlaveFactory_l341_2) begin - bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; - end - end - if(when_BusSlaveFactory_l371) begin - if(when_BusSlaveFactory_l373) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; - end - end - if(when_BusSlaveFactory_l335_3) begin - if(when_BusSlaveFactory_l341_3) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; - end - end - case(io_bus_cmd_payload_fragment_address) - 6'h0c : begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; - bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; - bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; - end - end - 6'h04 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; - end - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; - end - end - end - end - - always @(posedge io_systemClk) begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; - end - - -endmodule - -module BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [15:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output [0:0] io_timerInterrupt, - output [0:0] io_softwareInterrupt, - output [63:0] io_time, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [31:0] _zz_logic_harts_0_cmp; - wire [31:0] _zz_logic_harts_0_cmp_1; - wire [31:0] _zz_logic_harts_0_cmp_2; - wire [31:0] _zz_logic_harts_0_cmp_3; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_bus_cmd_fire; - wire factory_doWrite; - wire io_bus_cmd_fire_1; - wire factory_doRead; - reg [63:0] logic_time; - reg [63:0] logic_harts_0_cmp; - reg logic_harts_0_timerInterrupt; - reg logic_harts_0_softwareInterrupt; - wire [63:0] _zz_factory_rsp_payload_fragment_data; - wire when_BmbSlaveFactory_l71; - wire when_BmbSlaveFactory_l71_1; - wire when_BmbSlaveFactory_l71_2; - wire when_BmbSlaveFactory_l71_3; - - assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; - assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; - end - if(when_BmbSlaveFactory_l71_1) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; - end - end - - assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - assign _zz_factory_rsp_payload_fragment_data = logic_time; - assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; - assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; - assign io_time = logic_time; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); - assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); - assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); - assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - logic_time <= 64'h0; - logic_harts_0_softwareInterrupt <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); - end - logic_time <= (logic_time + 64'h0000000000000001); - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - if(factory_doWrite) begin - logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); - if(when_BmbSlaveFactory_l71_2) begin - if(factory_doWrite) begin - logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; - end - end - if(when_BmbSlaveFactory_l71_3) begin - if(factory_doWrite) begin - logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; - end - end - end - - -endmodule - -module BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [23:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [3:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [3:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [23:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [3:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [3:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [23:0] io_outputs_1_cmd_payload_fragment_address, - output [1:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [3:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [3:0] io_outputs_1_rsp_payload_fragment_context, - output reg io_outputs_2_cmd_valid, - input io_outputs_2_cmd_ready, - output io_outputs_2_cmd_payload_last, - output [0:0] io_outputs_2_cmd_payload_fragment_opcode, - output [23:0] io_outputs_2_cmd_payload_fragment_address, - output [1:0] io_outputs_2_cmd_payload_fragment_length, - output [31:0] io_outputs_2_cmd_payload_fragment_data, - output [3:0] io_outputs_2_cmd_payload_fragment_mask, - output [3:0] io_outputs_2_cmd_payload_fragment_context, - input io_outputs_2_rsp_valid, - output io_outputs_2_rsp_ready, - input io_outputs_2_rsp_payload_last, - input [0:0] io_outputs_2_rsp_payload_fragment_opcode, - input [31:0] io_outputs_2_rsp_payload_fragment_data, - input [3:0] io_outputs_2_rsp_payload_fragment_context, - output reg io_outputs_3_cmd_valid, - input io_outputs_3_cmd_ready, - output io_outputs_3_cmd_payload_last, - output [0:0] io_outputs_3_cmd_payload_fragment_opcode, - output [23:0] io_outputs_3_cmd_payload_fragment_address, - output [1:0] io_outputs_3_cmd_payload_fragment_length, - output [31:0] io_outputs_3_cmd_payload_fragment_data, - output [3:0] io_outputs_3_cmd_payload_fragment_mask, - output [3:0] io_outputs_3_cmd_payload_fragment_context, - input io_outputs_3_rsp_valid, - output io_outputs_3_rsp_ready, - input io_outputs_3_rsp_payload_last, - input [0:0] io_outputs_3_rsp_payload_fragment_opcode, - input [31:0] io_outputs_3_rsp_payload_fragment_data, - input [3:0] io_outputs_3_rsp_payload_fragment_context, - output reg io_outputs_4_cmd_valid, - input io_outputs_4_cmd_ready, - output io_outputs_4_cmd_payload_last, - output [0:0] io_outputs_4_cmd_payload_fragment_opcode, - output [23:0] io_outputs_4_cmd_payload_fragment_address, - output [1:0] io_outputs_4_cmd_payload_fragment_length, - output [31:0] io_outputs_4_cmd_payload_fragment_data, - output [3:0] io_outputs_4_cmd_payload_fragment_mask, - output [3:0] io_outputs_4_cmd_payload_fragment_context, - input io_outputs_4_rsp_valid, - output io_outputs_4_rsp_ready, - input io_outputs_4_rsp_payload_last, - input [0:0] io_outputs_4_rsp_payload_fragment_opcode, - input [31:0] io_outputs_4_rsp_payload_fragment_data, - input [3:0] io_outputs_4_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_logic_rspPendingCounter; - wire [3:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [3:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_3; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [3:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [3:0] logic_input_payload_fragment_context; - reg io_input_cmd_rValid; - wire logic_input_fire; - reg io_input_cmd_rData_last; - reg [0:0] io_input_cmd_rData_fragment_opcode; - reg [23:0] io_input_cmd_rData_fragment_address; - reg [1:0] io_input_cmd_rData_fragment_length; - reg [31:0] io_input_cmd_rData_fragment_data; - reg [3:0] io_input_cmd_rData_fragment_mask; - reg [3:0] io_input_cmd_rData_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_hitsS0_2; - wire logic_hitsS0_3; - wire logic_hitsS0_4; - wire logic_noHitS0; - wire io_input_cmd_fire; - reg logic_hitsS1_0; - reg logic_hitsS1_1; - reg logic_hitsS1_2; - reg logic_hitsS1_3; - reg logic_hitsS1_4; - wire io_input_cmd_fire_1; - reg logic_noHitS1; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - wire _zz_io_outputs_2_cmd_payload_last; - wire _zz_io_outputs_3_cmd_payload_last; - wire _zz_io_outputs_4_cmd_payload_last; - reg [3:0] logic_rspPendingCounter; - wire logic_input_fire_1; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - reg logic_rspHits_2; - reg logic_rspHits_3; - reg logic_rspHits_4; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_2; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_3; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_4; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_context; - wire logic_input_fire_6; - wire _zz_io_input_rsp_payload_last; - wire _zz_io_input_rsp_payload_last_1; - wire [2:0] _zz_io_input_rsp_payload_last_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last_2) - 3'b000 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - 3'b001 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - 3'b010 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; - end - 3'b011 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_cmd_ready = (! io_input_cmd_rValid); - assign logic_input_valid = io_input_cmd_rValid; - assign logic_input_payload_last = io_input_cmd_rData_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); - assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); - assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); - always @(*) begin - io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); - if(logic_cmdWait) begin - io_outputs_2_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; - assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; - assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); - always @(*) begin - io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); - if(logic_cmdWait) begin - io_outputs_3_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; - assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; - assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); - always @(*) begin - io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); - if(logic_cmdWait) begin - io_outputs_4_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; - assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; - assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); - assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign io_outputs_2_rsp_ready = io_input_rsp_ready; - assign io_outputs_3_rsp_ready = io_input_rsp_ready; - assign io_outputs_4_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_input_cmd_rValid <= 1'b0; - logic_rspPendingCounter <= 4'b0000; - logic_rspNoHit_doIt <= 1'b0; - end else begin - if(io_input_cmd_valid) begin - io_input_cmd_rValid <= 1'b1; - end - if(logic_input_fire) begin - io_input_cmd_rValid <= 1'b0; - end - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(io_input_cmd_ready) begin - io_input_cmd_rData_last <= io_input_cmd_payload_last; - io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; - io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; - io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; - io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; - io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; - io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; - end - if(io_input_cmd_fire) begin - logic_hitsS1_0 <= logic_hitsS0_0; - logic_hitsS1_1 <= logic_hitsS0_1; - logic_hitsS1_2 <= logic_hitsS0_2; - logic_hitsS1_3 <= logic_hitsS0_3; - logic_hitsS1_4 <= logic_hitsS0_4; - end - if(io_input_cmd_fire_1) begin - logic_noHitS1 <= logic_noHitS0; - end - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS1_0; - logic_rspHits_1 <= logic_hitsS1_1; - logic_rspHits_2 <= logic_hitsS1_2; - logic_rspHits_3 <= logic_hitsS1_3; - logic_rspHits_4 <= logic_hitsS1_4; - end - if(logic_input_fire_3) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_5) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - end - - -endmodule - -//BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b replaced by BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b - -module BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output reg io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_source, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output reg io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output reg [0:0] io_output_cmd_payload_fragment_opcode, - output reg [31:0] io_output_cmd_payload_fragment_address, - output reg [1:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [3:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output reg io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [3:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_buffer_last; - wire [0:0] _zz_buffer_last_1; - wire [11:0] _zz_buffer_addressIncr; - wire [11:0] _zz_buffer_addressIncr_1; - wire [11:0] _zz_buffer_addressIncr_2; - wire doResult; - reg buffer_valid; - reg [0:0] buffer_opcode; - reg [0:0] buffer_source; - reg [31:0] buffer_address; - reg [0:0] buffer_context; - reg [3:0] buffer_beat; - wire buffer_last; - wire [31:0] buffer_addressIncr; - wire buffer_isWrite; - wire io_output_cmd_fire; - wire [3:0] cmdTransferBeatCount; - wire requireBuffer; - reg cmdContext_drop; - reg cmdContext_last; - reg [0:0] cmdContext_source; - reg [0:0] cmdContext_context; - wire io_output_cmd_fire_1; - wire rspContext_drop; - wire rspContext_last; - wire [0:0] rspContext_source; - wire [0:0] rspContext_context; - wire [3:0] _zz_rspContext_drop; - wire when_Stream_l434; - reg io_output_rsp_thrown_valid; - wire io_output_rsp_thrown_ready; - wire io_output_rsp_thrown_payload_last; - wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; - wire [31:0] io_output_rsp_thrown_payload_fragment_data; - wire [3:0] io_output_rsp_thrown_payload_fragment_context; - - assign _zz_buffer_last_1 = 1'b1; - assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; - assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); - assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; - assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; - assign buffer_last = (buffer_beat == _zz_buffer_last); - assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; - assign buffer_isWrite = (buffer_opcode == 1'b1); - assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); - assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; - assign requireBuffer = (cmdTransferBeatCount != 4'b0000); - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_last = 1'b1; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_address = buffer_addressIncr; - end else begin - io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - if(requireBuffer) begin - io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; - end - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_opcode = buffer_opcode; - end else begin - io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - if(requireBuffer) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; - end - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_context = buffer_context; - end else begin - cmdContext_context = io_input_cmd_payload_fragment_context; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_source = buffer_source; - end else begin - cmdContext_source = io_input_cmd_payload_fragment_source; - end - end - - always @(*) begin - io_input_cmd_ready = 1'b0; - if(buffer_valid) begin - io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); - end else begin - io_input_cmd_ready = io_output_cmd_ready; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); - end else begin - io_output_cmd_valid = io_input_cmd_valid; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_last = buffer_last; - end else begin - cmdContext_last = (! requireBuffer); - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_drop = buffer_isWrite; - end else begin - cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); - end - end - - assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); - assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; - assign rspContext_drop = _zz_rspContext_drop[0]; - assign rspContext_last = _zz_rspContext_drop[1]; - assign rspContext_source = _zz_rspContext_drop[2 : 2]; - assign rspContext_context = _zz_rspContext_drop[3 : 3]; - assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); - always @(*) begin - io_output_rsp_thrown_valid = io_output_rsp_valid; - if(when_Stream_l434) begin - io_output_rsp_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_output_rsp_ready = io_output_rsp_thrown_ready; - if(when_Stream_l434) begin - io_output_rsp_ready = 1'b1; - end - end - - assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; - assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_input_rsp_valid = io_output_rsp_thrown_valid; - assign io_output_rsp_thrown_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = rspContext_last; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = rspContext_context; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffer_valid <= 1'b0; - end else begin - if(io_output_cmd_fire) begin - if(buffer_last) begin - buffer_valid <= 1'b0; - end - end - if(!buffer_valid) begin - buffer_valid <= (requireBuffer && io_output_cmd_fire_1); - end - end - end - - always @(posedge io_systemClk) begin - if(io_output_cmd_fire) begin - buffer_beat <= (buffer_beat - 4'b0001); - buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; - end - if(!buffer_valid) begin - buffer_opcode <= io_input_cmd_payload_fragment_opcode; - buffer_source <= io_input_cmd_payload_fragment_source; - buffer_address <= io_input_cmd_payload_fragment_address; - buffer_context <= io_input_cmd_payload_fragment_context; - buffer_beat <= cmdTransferBeatCount; - end - end - - -endmodule - -module BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [14:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_mask, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_ram_port0; - wire io_bus_rsp_isStall; - reg io_bus_cmd_valid_regNextWhen; - reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; - wire [12:0] _zz_io_bus_rsp_payload_fragment_data; - wire io_bus_cmd_fire; - wire _zz_io_bus_rsp_payload_fragment_data_1; - wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; - reg [7:0] ram_symbol0 [0:8191]; - reg [7:0] ram_symbol1 [0:8191]; - reg [7:0] ram_symbol2 [0:8191]; - reg [7:0] ram_symbol3 [0:8191]; - reg [7:0] _zz_ramsymbol_read; - reg [7:0] _zz_ramsymbol_read_1; - reg [7:0] _zz_ramsymbol_read_2; - reg [7:0] _zz_ramsymbol_read_3; - - initial begin - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); - end - always @(*) begin - _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; - end - always @(posedge io_systemClk) begin - if(io_bus_cmd_fire) begin - _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; - end - if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; - end - if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; - end - if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; - end - end - - assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); - assign io_bus_cmd_ready = (! io_bus_rsp_isStall); - assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; - assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; - assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); - assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; - assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; - assign io_bus_rsp_payload_fragment_opcode = 1'b0; - assign io_bus_rsp_payload_last = 1'b1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_bus_cmd_valid_regNextWhen <= 1'b0; - end else begin - if(io_bus_cmd_ready) begin - io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; - end - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_ready) begin - io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; - end - end - - -endmodule - -module BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_source, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [0:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_source, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [0:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_source, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [0:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_source, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [31:0] io_outputs_1_cmd_payload_fragment_address, - output [5:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [0:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_source, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [0:0] io_outputs_1_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_1; - reg [0:0] _zz_io_input_rsp_payload_fragment_source; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [0:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_source; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [5:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [0:0] logic_input_payload_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - reg [0:0] logic_rspNoHit_source; - wire logic_input_fire_4; - reg [0:0] logic_rspNoHit_context; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_counter; - wire [0:0] _zz_io_input_rsp_payload_last; - wire when_BmbDecoder_l81; - wire io_input_rsp_fire_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last) - 1'b0 : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = logic_rspHits_1; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b0; - if(when_BmbDecoder_l81) begin - io_input_rsp_payload_last = 1'b1; - end - if(logic_rspNoHit_singleBeatRsp) begin - io_input_rsp_payload_last = 1'b1; - end - end - end - - always @(*) begin - io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_source = logic_rspNoHit_source; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); - assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - logic_rspHits_1 <= logic_hitsS0_1; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_3) begin - logic_rspNoHit_source <= logic_input_payload_fragment_source; - end - if(logic_input_fire_4) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - if(logic_input_fire_5) begin - logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; - end - if(logic_rspNoHit_doIt) begin - if(io_input_rsp_fire_2) begin - logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); - end - end - end - - -endmodule - -module BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_inputs_0_cmd_valid, - output io_inputs_0_cmd_ready, - input io_inputs_0_cmd_payload_last, - input [0:0] io_inputs_0_cmd_payload_fragment_opcode, - input [31:0] io_inputs_0_cmd_payload_fragment_address, - input [5:0] io_inputs_0_cmd_payload_fragment_length, - input [31:0] io_inputs_0_cmd_payload_fragment_data, - input [3:0] io_inputs_0_cmd_payload_fragment_mask, - input [0:0] io_inputs_0_cmd_payload_fragment_context, - output io_inputs_0_rsp_valid, - input io_inputs_0_rsp_ready, - output io_inputs_0_rsp_payload_last, - output [0:0] io_inputs_0_rsp_payload_fragment_opcode, - output [31:0] io_inputs_0_rsp_payload_fragment_data, - output [0:0] io_inputs_0_rsp_payload_fragment_context, - input io_inputs_1_cmd_valid, - output io_inputs_1_cmd_ready, - input io_inputs_1_cmd_payload_last, - input [0:0] io_inputs_1_cmd_payload_fragment_opcode, - input [31:0] io_inputs_1_cmd_payload_fragment_address, - input [5:0] io_inputs_1_cmd_payload_fragment_length, - input [31:0] io_inputs_1_cmd_payload_fragment_data, - input [3:0] io_inputs_1_cmd_payload_fragment_mask, - output io_inputs_1_rsp_valid, - input io_inputs_1_rsp_ready, - output io_inputs_1_rsp_payload_last, - output [0:0] io_inputs_1_rsp_payload_fragment_opcode, - output [31:0] io_inputs_1_rsp_payload_fragment_data, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_source, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_source, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire memory_arbiter_io_inputs_0_ready; - wire memory_arbiter_io_inputs_1_ready; - wire memory_arbiter_io_output_valid; - wire memory_arbiter_io_output_payload_last; - wire [0:0] memory_arbiter_io_output_payload_fragment_source; - wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; - wire [31:0] memory_arbiter_io_output_payload_fragment_address; - wire [5:0] memory_arbiter_io_output_payload_fragment_length; - wire [31:0] memory_arbiter_io_output_payload_fragment_data; - wire [3:0] memory_arbiter_io_output_payload_fragment_mask; - wire [0:0] memory_arbiter_io_output_payload_fragment_context; - wire [0:0] memory_arbiter_io_chosen; - wire [1:0] memory_arbiter_io_chosenOH; - wire [1:0] _zz_io_output_cmd_payload_fragment_source; - reg _zz_io_output_rsp_ready; - wire [0:0] memory_rspSel; - - assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; - StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b memory_arbiter ( - .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i - .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o - .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i - .io_inputs_0_payload_fragment_source (1'b0 ), //i - .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i - .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i - .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o - .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i - .io_inputs_1_payload_fragment_source (1'b0 ), //i - .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i - .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_1_payload_fragment_context (1'b0 ), //i - .io_output_valid (memory_arbiter_io_output_valid ), //o - .io_output_ready (io_output_cmd_ready ), //i - .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o - .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o - .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o - .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o - .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o - .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o - .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o - .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o - .io_chosen (memory_arbiter_io_chosen ), //o - .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(memory_rspSel) - 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; - default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; - endcase - end - - assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; - assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; - assign io_output_cmd_valid = memory_arbiter_io_output_valid; - assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; - assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; - assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; - assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; - assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); - assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); - assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_ready = _zz_io_output_rsp_ready; - -endmodule - -module BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data -); - - - assign io_outputs_0_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_outputs_0_cmd_ready; - assign io_input_rsp_valid = io_outputs_0_rsp_valid; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - -endmodule - -module BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context -); - - - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - -endmodule - -module BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire logic_hitsS0_0; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - wire logic_input_fire_4; - wire logic_input_fire_5; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - always @(*) begin - logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - end - - -endmodule - -module BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input system_cores_0_debugReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin - if(system_cores_0_debugReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_remote_cmd_valid, - output io_remote_cmd_ready, - input io_remote_cmd_payload_last, - input [0:0] io_remote_cmd_payload_fragment, - output io_remote_rsp_valid, - input io_remote_rsp_ready, - output io_remote_rsp_payload_error, - output [31:0] io_remote_rsp_payload_data, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output io_mem_cmd_payload_wr, - output [1:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload, - input io_systemClk, - input debugCd_logic_outputReset -); - - reg [66:0] dispatcher_dataShifter; - reg dispatcher_dataLoaded; - reg [7:0] dispatcher_headerShifter; - wire [7:0] dispatcher_header; - reg dispatcher_headerLoaded; - reg [2:0] dispatcher_counter; - wire when_Fragment_l346; - wire when_Fragment_l349; - wire [66:0] _zz_io_mem_cmd_payload_address; - wire io_mem_cmd_isStall; - wire when_Fragment_l372; - - assign dispatcher_header = dispatcher_headerShifter[7 : 0]; - assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); - assign when_Fragment_l349 = (dispatcher_counter == 3'b111); - assign io_remote_cmd_ready = (! dispatcher_dataLoaded); - assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; - assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; - assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; - assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; - assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; - assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); - assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); - assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); - assign io_remote_rsp_valid = io_mem_rsp_valid; - assign io_remote_rsp_payload_error = 1'b0; - assign io_remote_rsp_payload_data = io_mem_rsp_payload; - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - dispatcher_dataLoaded <= 1'b0; - dispatcher_headerLoaded <= 1'b0; - dispatcher_counter <= 3'b000; - end else begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_counter <= (dispatcher_counter + 3'b001); - if(when_Fragment_l349) begin - dispatcher_headerLoaded <= 1'b1; - end - end - if(io_remote_cmd_payload_last) begin - dispatcher_headerLoaded <= 1'b1; - dispatcher_dataLoaded <= 1'b1; - dispatcher_counter <= 3'b000; - end - end - if(when_Fragment_l372) begin - dispatcher_headerLoaded <= 1'b0; - dispatcher_dataLoaded <= 1'b0; - end - end - end - - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); - end else begin - dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); - end - end - end - - -endmodule - -module JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_ctrl_tdi, - input io_ctrl_enable, - input io_ctrl_capture, - input io_ctrl_shift, - input io_ctrl_update, - input io_ctrl_reset, - output io_ctrl_tdo, - output io_remote_cmd_valid, - input io_remote_cmd_ready, - output io_remote_cmd_payload_last, - output [0:0] io_remote_cmd_payload_fragment, - input io_remote_rsp_valid, - output io_remote_rsp_ready, - input io_remote_rsp_payload_error, - input [31:0] io_remote_rsp_payload_data, - input io_systemClk, - input debugCd_logic_outputReset, - input jtagCtrl_tck -); - - wire flowCCByToggle_1_io_output_valid; - wire flowCCByToggle_1_io_output_payload_last; - wire [0:0] flowCCByToggle_1_io_output_payload_fragment; - wire system_cmd_valid; - wire system_cmd_payload_last; - wire [0:0] system_cmd_payload_fragment; - wire system_cmd_toStream_valid; - wire system_cmd_toStream_ready; - wire system_cmd_toStream_payload_last; - wire [0:0] system_cmd_toStream_payload_fragment; - (* async_reg = "true" *) reg system_rsp_valid; - (* async_reg = "true" *) reg system_rsp_payload_error; - (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; - wire io_remote_rsp_fire; - wire jtag_wrapper_ctrl_tdi; - wire jtag_wrapper_ctrl_enable; - wire jtag_wrapper_ctrl_capture; - wire jtag_wrapper_ctrl_shift; - wire jtag_wrapper_ctrl_update; - wire jtag_wrapper_ctrl_reset; - reg jtag_wrapper_ctrl_tdo; - reg [1:0] jtag_wrapper_header; - wire [1:0] jtag_wrapper_headerNext; - reg [0:0] jtag_wrapper_counter; - reg jtag_wrapper_done; - reg jtag_wrapper_sendCapture; - reg jtag_wrapper_sendShift; - reg jtag_wrapper_sendUpdate; - wire when_JtagTapInstructions_l183; - wire when_JtagTapInstructions_l186; - wire jtag_writeArea_ctrl_tdi; - wire jtag_writeArea_ctrl_enable; - wire jtag_writeArea_ctrl_capture; - wire jtag_writeArea_ctrl_shift; - wire jtag_writeArea_ctrl_update; - wire jtag_writeArea_ctrl_reset; - wire jtag_writeArea_ctrl_tdo; - wire jtag_writeArea_source_valid; - wire jtag_writeArea_source_payload_last; - wire [0:0] jtag_writeArea_source_payload_fragment; - reg jtag_writeArea_valid; - reg jtag_writeArea_data; - wire when_JtagTapInstructions_l209; - wire jtag_readArea_ctrl_tdi; - wire jtag_readArea_ctrl_enable; - wire jtag_readArea_ctrl_capture; - wire jtag_readArea_ctrl_shift; - wire jtag_readArea_ctrl_update; - wire jtag_readArea_ctrl_reset; - wire jtag_readArea_ctrl_tdo; - reg [33:0] jtag_readArea_full_shifter; - wire when_JtagTapInstructions_l209_1; - - FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b flowCCByToggle_1 ( - .io_input_valid (jtag_writeArea_source_valid ), //i - .io_input_payload_last (jtag_writeArea_source_payload_last ), //i - .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i - .io_output_valid (flowCCByToggle_1_io_output_valid ), //o - .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o - .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o - .jtagCtrl_tck (jtagCtrl_tck ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - assign system_cmd_toStream_valid = system_cmd_valid; - assign system_cmd_toStream_payload_last = system_cmd_payload_last; - assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; - assign io_remote_cmd_valid = system_cmd_toStream_valid; - assign system_cmd_toStream_ready = io_remote_cmd_ready; - assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; - assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; - assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); - assign io_remote_rsp_ready = 1'b1; - assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); - always @(*) begin - jtag_wrapper_sendCapture = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_sendCapture = 1'b1; - end - end - end - end - end - - always @(*) begin - jtag_wrapper_sendShift = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(!when_JtagTapInstructions_l183) begin - jtag_wrapper_sendShift = 1'b1; - end - end - end - end - - always @(*) begin - jtag_wrapper_sendUpdate = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_update) begin - jtag_wrapper_sendUpdate = 1'b1; - end - end - end - - assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); - assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); - always @(*) begin - jtag_wrapper_ctrl_tdo = 1'b0; - if(when_JtagTapInstructions_l209) begin - jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; - end - if(when_JtagTapInstructions_l209_1) begin - jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; - end - end - - assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; - assign jtag_wrapper_ctrl_enable = io_ctrl_enable; - assign jtag_wrapper_ctrl_capture = io_ctrl_capture; - assign jtag_wrapper_ctrl_shift = io_ctrl_shift; - assign jtag_wrapper_ctrl_update = io_ctrl_update; - assign jtag_wrapper_ctrl_reset = io_ctrl_reset; - assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; - assign jtag_writeArea_source_valid = jtag_writeArea_valid; - assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); - assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; - assign system_cmd_valid = flowCCByToggle_1_io_output_valid; - assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; - assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; - assign jtag_writeArea_ctrl_tdo = 1'b0; - assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); - assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_writeArea_ctrl_enable = 1'b1; - assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); - assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); - assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); - assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; - assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; - assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); - assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_readArea_ctrl_enable = 1'b1; - assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); - assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); - assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); - assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - system_rsp_valid <= 1'b0; - end - if(io_remote_rsp_fire) begin - system_rsp_valid <= 1'b1; - system_rsp_payload_error <= io_remote_rsp_payload_error; - system_rsp_payload_data <= io_remote_rsp_payload_data; - end - end - - always @(posedge jtagCtrl_tck) begin - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_capture) begin - jtag_wrapper_done <= 1'b0; - jtag_wrapper_counter <= 1'b0; - end - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); - jtag_wrapper_header <= jtag_wrapper_headerNext; - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_done <= 1'b1; - end - end - end - end - jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); - jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; - if(jtag_readArea_ctrl_enable) begin - if(jtag_readArea_ctrl_capture) begin - jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; - end - if(jtag_readArea_ctrl_shift) begin - jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); - end - end - end - - -endmodule - -module VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b ( - output dBus_cmd_valid, - input dBus_cmd_ready, - output dBus_cmd_payload_wr, - output dBus_cmd_payload_uncached, - output [31:0] dBus_cmd_payload_address, - output [31:0] dBus_cmd_payload_data, - output [3:0] dBus_cmd_payload_mask, - output [2:0] dBus_cmd_payload_size, - output dBus_cmd_payload_last, - input dBus_rsp_valid, - input dBus_rsp_payload_last, - input [31:0] dBus_rsp_payload_data, - input dBus_rsp_payload_error, - input timerInterrupt, - input externalInterrupt, - input softwareInterrupt, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBus_cmd_valid, - input iBus_cmd_ready, - output reg [31:0] iBus_cmd_payload_address, - output [2:0] iBus_cmd_payload_size, - input iBus_rsp_valid, - input [31:0] iBus_rsp_payload_data, - input iBus_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset, - input debugCd_logic_outputReset -); - localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; - localparam ShiftCtrlEnum_SLL_1 = 2'd1; - localparam ShiftCtrlEnum_SRL_1 = 2'd2; - localparam ShiftCtrlEnum_SRA_1 = 2'd3; - localparam BranchCtrlEnum_INC = 2'd0; - localparam BranchCtrlEnum_B = 2'd1; - localparam BranchCtrlEnum_JAL = 2'd2; - localparam BranchCtrlEnum_JALR = 2'd3; - localparam EnvCtrlEnum_NONE = 2'd0; - localparam EnvCtrlEnum_XRET = 2'd1; - localparam EnvCtrlEnum_ECALL = 2'd2; - localparam EnvCtrlEnum_EBREAK = 2'd3; - localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; - localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; - localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; - localparam AluCtrlEnum_ADD_SUB = 2'd0; - localparam AluCtrlEnum_SLT_SLTU = 2'd1; - localparam AluCtrlEnum_BITWISE = 2'd2; - localparam Src2CtrlEnum_RS = 2'd0; - localparam Src2CtrlEnum_IMI = 2'd1; - localparam Src2CtrlEnum_IMS = 2'd2; - localparam Src2CtrlEnum_PC = 2'd3; - localparam Src1CtrlEnum_RS = 2'd0; - localparam Src1CtrlEnum_IMU = 2'd1; - localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; - localparam Src1CtrlEnum_URS1 = 2'd3; - - wire IBusCachedPlugin_cache_io_flush; - wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; - wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; - wire IBusCachedPlugin_cache_io_cpu_decode_isValid; - wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; - wire IBusCachedPlugin_cache_io_cpu_decode_isUser; - reg IBusCachedPlugin_cache_io_cpu_fill_valid; - wire dataCache_1_io_cpu_execute_isValid; - wire [31:0] dataCache_1_io_cpu_execute_address; - wire dataCache_1_io_cpu_memory_isValid; - reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; - reg dataCache_1_io_cpu_writeBack_isValid; - wire dataCache_1_io_cpu_writeBack_isUser; - wire [31:0] dataCache_1_io_cpu_writeBack_storeData; - wire [31:0] dataCache_1_io_cpu_writeBack_address; - wire dataCache_1_io_cpu_writeBack_fence_SW; - wire dataCache_1_io_cpu_writeBack_fence_SR; - wire dataCache_1_io_cpu_writeBack_fence_SO; - wire dataCache_1_io_cpu_writeBack_fence_SI; - wire dataCache_1_io_cpu_writeBack_fence_PW; - wire dataCache_1_io_cpu_writeBack_fence_PR; - wire dataCache_1_io_cpu_writeBack_fence_PO; - wire dataCache_1_io_cpu_writeBack_fence_PI; - wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; - wire dataCache_1_io_cpu_flush_valid; - wire dataCache_1_io_cpu_flush_payload_singleLine; - wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; - wire dataCache_1_io_mem_cmd_ready; - reg [31:0] _zz_RegFilePlugin_regFile_port0; - reg [31:0] _zz_RegFilePlugin_regFile_port1; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1_io_cpu_execute_haltIt; - wire dataCache_1_io_cpu_execute_refilling; - wire dataCache_1_io_cpu_memory_isWrite; - wire dataCache_1_io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1_io_cpu_writeBack_data; - wire dataCache_1_io_cpu_writeBack_mmuException; - wire dataCache_1_io_cpu_writeBack_unalignedAccess; - wire dataCache_1_io_cpu_writeBack_accessError; - wire dataCache_1_io_cpu_writeBack_isWrite; - wire dataCache_1_io_cpu_writeBack_keepMemRspData; - wire dataCache_1_io_cpu_writeBack_exclusiveOk; - wire dataCache_1_io_cpu_flush_ready; - wire dataCache_1_io_cpu_redo; - wire dataCache_1_io_mem_cmd_valid; - wire dataCache_1_io_mem_cmd_payload_wr; - wire dataCache_1_io_mem_cmd_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_size; - wire dataCache_1_io_mem_cmd_payload_last; - wire [51:0] _zz_memory_MUL_LOW; - wire [51:0] _zz_memory_MUL_LOW_1; - wire [51:0] _zz_memory_MUL_LOW_2; - wire [51:0] _zz_memory_MUL_LOW_3; - wire [32:0] _zz_memory_MUL_LOW_4; - wire [51:0] _zz_memory_MUL_LOW_5; - wire [49:0] _zz_memory_MUL_LOW_6; - wire [51:0] _zz_memory_MUL_LOW_7; - wire [49:0] _zz_memory_MUL_LOW_8; - wire [31:0] _zz_execute_SHIFT_RIGHT; - wire [32:0] _zz_execute_SHIFT_RIGHT_1; - wire [32:0] _zz_execute_SHIFT_RIGHT_2; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; - wire _zz_decode_LEGAL_INSTRUCTION_3; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; - wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; - wire _zz_decode_LEGAL_INSTRUCTION_9; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; - wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; - wire _zz_decode_LEGAL_INSTRUCTION_15; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; - wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; - wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; - reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; - wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; - wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; - wire [25:0] _zz_io_cpu_flush_payload_lineId; - wire [25:0] _zz_io_cpu_flush_payload_lineId_1; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; - wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; - wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; - wire _zz__zz_decode_BRANCH_CTRL_2_5; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; - wire _zz__zz_decode_BRANCH_CTRL_2_9; - wire _zz__zz_decode_BRANCH_CTRL_2_10; - wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; - wire _zz__zz_decode_BRANCH_CTRL_2_13; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; - wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; - wire _zz__zz_decode_BRANCH_CTRL_2_26; - wire _zz__zz_decode_BRANCH_CTRL_2_27; - wire _zz__zz_decode_BRANCH_CTRL_2_28; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; - wire _zz__zz_decode_BRANCH_CTRL_2_32; - wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; - wire _zz__zz_decode_BRANCH_CTRL_2_36; - wire _zz__zz_decode_BRANCH_CTRL_2_37; - wire _zz__zz_decode_BRANCH_CTRL_2_38; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; - wire _zz__zz_decode_BRANCH_CTRL_2_40; - wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; - wire _zz__zz_decode_BRANCH_CTRL_2_47; - wire _zz__zz_decode_BRANCH_CTRL_2_48; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; - wire _zz__zz_decode_BRANCH_CTRL_2_54; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; - wire _zz__zz_decode_BRANCH_CTRL_2_57; - wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; - wire _zz__zz_decode_BRANCH_CTRL_2_66; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; - wire _zz__zz_decode_BRANCH_CTRL_2_68; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; - wire _zz__zz_decode_BRANCH_CTRL_2_70; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; - wire _zz__zz_decode_BRANCH_CTRL_2_75; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; - wire _zz__zz_decode_BRANCH_CTRL_2_86; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; - wire _zz__zz_decode_BRANCH_CTRL_2_92; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; - wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; - wire _zz__zz_decode_BRANCH_CTRL_2_99; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; - wire _zz__zz_decode_BRANCH_CTRL_2_101; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; - wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; - wire _zz__zz_decode_BRANCH_CTRL_2_111; - wire _zz__zz_decode_BRANCH_CTRL_2_112; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; - wire _zz__zz_decode_BRANCH_CTRL_2_125; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; - wire _zz__zz_decode_BRANCH_CTRL_2_140; - wire _zz__zz_decode_BRANCH_CTRL_2_141; - wire _zz__zz_decode_BRANCH_CTRL_2_142; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; - wire _zz_RegFilePlugin_regFile_port; - wire _zz_decode_RegFilePlugin_rs1Data; - wire _zz_RegFilePlugin_regFile_port_1; - wire _zz_decode_RegFilePlugin_rs2Data; - wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; - wire [2:0] _zz__zz_decode_SRC1_1; - wire [4:0] _zz__zz_decode_SRC1_1_1; - wire [11:0] _zz__zz_decode_SRC2_4; - wire [31:0] _zz_execute_SrcPlugin_addSub; - wire [31:0] _zz_execute_SrcPlugin_addSub_1; - wire [31:0] _zz_execute_SrcPlugin_addSub_2; - wire [31:0] _zz_execute_SrcPlugin_addSub_3; - wire [31:0] _zz_execute_SrcPlugin_addSub_4; - wire [31:0] _zz_execute_SrcPlugin_addSub_5; - wire [31:0] _zz_execute_SrcPlugin_addSub_6; - wire [65:0] _zz_writeBack_MulPlugin_result; - wire [65:0] _zz_writeBack_MulPlugin_result_1; - wire [31:0] _zz__zz_decode_RS2_2; - wire [31:0] _zz__zz_decode_RS2_2_1; - wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; - wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; - wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; - wire _zz_when; - wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; - wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; - wire [51:0] memory_MUL_LOW; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire [33:0] execute_MUL_HL; - wire [33:0] execute_MUL_LH; - wire [31:0] execute_MUL_LL; - wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; - wire [31:0] memory_MEMORY_STORE_DATA_RF; - wire [31:0] execute_MEMORY_STORE_DATA_RF; - wire decode_DO_EBREAK; - wire decode_CSR_READ_OPCODE; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] decode_SRC2; - wire [31:0] decode_SRC1; - wire decode_SRC2_FORCE_ZERO; - wire [1:0] decode_BRANCH_CTRL; - wire [1:0] _zz_decode_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; - wire [1:0] _zz_execute_to_memory_ENV_CTRL; - wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; - wire [1:0] decode_ENV_CTRL; - wire [1:0] _zz_decode_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; - wire decode_IS_CSR; - wire decode_IS_RS2_SIGNED; - wire decode_IS_RS1_SIGNED; - wire decode_IS_DIV; - wire memory_IS_MUL; - wire decode_IS_MUL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; - wire [1:0] decode_SHIFT_CTRL; - wire [1:0] _zz_decode_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; - wire [1:0] decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_MANAGMENT; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [1:0] decode_ALU_CTRL; - wire [1:0] _zz_decode_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; - wire decode_MEMORY_FORCE_CONSTISTENCY; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [31:0] memory_PC; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] execute_PC; - wire [1:0] execute_BRANCH_CTRL; - wire [1:0] _zz_execute_BRANCH_CTRL; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire [1:0] memory_ENV_CTRL; - wire [1:0] _zz_memory_ENV_CTRL; - wire [1:0] execute_ENV_CTRL; - wire [1:0] _zz_execute_ENV_CTRL; - wire [1:0] writeBack_ENV_CTRL; - wire [1:0] _zz_writeBack_ENV_CTRL; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire execute_IS_MUL; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_decode_RS2; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_decode_RS2_1; - wire [1:0] memory_SHIFT_CTRL; - wire [1:0] _zz_memory_SHIFT_CTRL; - wire [1:0] execute_SHIFT_CTRL; - wire [1:0] _zz_execute_SHIFT_CTRL; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_decode_SRC2; - wire [31:0] _zz_decode_SRC2_1; - wire [1:0] decode_SRC2_CTRL; - wire [1:0] _zz_decode_SRC2_CTRL; - wire [31:0] _zz_decode_SRC1; - wire [1:0] decode_SRC1_CTRL; - wire [1:0] _zz_decode_SRC1_CTRL; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire [1:0] execute_ALU_CTRL; - wire [1:0] _zz_execute_ALU_CTRL; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire [1:0] execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_execute_ALU_BITWISE_CTRL; - wire [31:0] _zz_lastStageRegFileWrite_payload_address; - wire _zz_lastStageRegFileWrite_valid; - reg _zz_1; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire [1:0] _zz_decode_BRANCH_CTRL_1; - wire [1:0] _zz_decode_ENV_CTRL_1; - wire [1:0] _zz_decode_SHIFT_CTRL_1; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; - wire [1:0] _zz_decode_SRC2_CTRL_1; - wire [1:0] _zz_decode_ALU_CTRL_1; - wire [1:0] _zz_decode_SRC1_CTRL_1; - reg [31:0] _zz_decode_RS2_2; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_MEMORY_STORE_DATA_RF; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire memory_MEMORY_ENABLE; - wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; - wire execute_MEMORY_FORCE_CONSTISTENCY; - (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_MANAGMENT; - (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected_4; - reg IBusCachedPlugin_rsp_issueDetected_3; - reg IBusCachedPlugin_rsp_issueDetected_2; - reg IBusCachedPlugin_rsp_issueDetected_1; - reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; - wire [31:0] decode_PC; - wire [31:0] decode_INSTRUCTION; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - wire IBusCachedPlugin_forceNoDecodeCond; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_0_isValid; - wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_isPaging; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_0_isValid; - wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_isPaging; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_when_DBusCachedPlugin_l393; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire [31:0] CsrPlugin_csrMapping_readDataSignal; - wire [31:0] CsrPlugin_csrMapping_readDataInit; - wire [31:0] CsrPlugin_csrMapping_writeDataSignal; - wire CsrPlugin_csrMapping_allowCsrSignal; - wire CsrPlugin_csrMapping_hazardFree; - wire CsrPlugin_inWfi /* verilator public */ ; - reg CsrPlugin_thirdPartyWake; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg CsrPlugin_allowEbreakException; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg BranchPlugin_inDebugNoFetchFlag; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_externalFlush; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_correction; - reg IBusCachedPlugin_fetchPc_correctionReg; - wire IBusCachedPlugin_fetchPc_output_fire; - wire IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - wire when_Fetcher_l134; - wire IBusCachedPlugin_fetchPc_output_fire_1; - wire when_Fetcher_l134_1; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_fetchPc_redo_valid; - wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; - reg IBusCachedPlugin_fetchPc_flushed; - wire when_Fetcher_l161; - reg IBusCachedPlugin_iBusRsp_redoFetch; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_output_valid; - wire IBusCachedPlugin_iBusRsp_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; - wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; - wire when_Fetcher_l243; - wire IBusCachedPlugin_injector_decodeInput_valid; - wire IBusCachedPlugin_injector_decodeInput_ready; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; - wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_IBusCachedPlugin_injector_decodeInput_valid; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - wire when_Fetcher_l323; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - wire when_Fetcher_l332; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - wire when_Fetcher_l332_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - wire when_Fetcher_l332_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - wire when_Fetcher_l332_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire when_Fetcher_l332_4; - reg IBusCachedPlugin_injector_nextPcCalc_valids_5; - wire when_Fetcher_l332_5; - reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - wire IBusCachedPlugin_rsp_issueDetected; - reg IBusCachedPlugin_rsp_redoFetch; - wire when_IBusCachedPlugin_l239; - wire when_IBusCachedPlugin_l244; - wire when_IBusCachedPlugin_l250; - wire when_IBusCachedPlugin_l256; - wire when_IBusCachedPlugin_l267; - wire dataCache_1_io_mem_cmd_s2mPipe_valid; - reg dataCache_1_io_mem_cmd_s2mPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_rValid; - reg dataCache_1_io_mem_cmd_rData_wr; - reg dataCache_1_io_mem_cmd_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_rData_size; - reg dataCache_1_io_mem_cmd_rData_last; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; - wire when_Stream_l368; - reg dBus_rsp_regNext_valid; - reg dBus_rsp_regNext_payload_last; - reg [31:0] dBus_rsp_regNext_payload_data; - reg dBus_rsp_regNext_payload_error; - reg [31:0] DBusCachedPlugin_rspCounter; - wire when_DBusCachedPlugin_l308; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; - wire dataCache_1_io_cpu_flush_isStall; - wire when_DBusCachedPlugin_l350; - wire when_DBusCachedPlugin_l366; - wire when_DBusCachedPlugin_l393; - wire when_DBusCachedPlugin_l446; - wire when_DBusCachedPlugin_l466; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire [31:0] writeBack_DBusCachedPlugin_rspRf; - wire [1:0] switch_Misc_l210; - wire _zz_writeBack_DBusCachedPlugin_rspFormated; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; - wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire when_DBusCachedPlugin_l492; - wire [32:0] _zz_decode_BRANCH_CTRL_2; - wire _zz_decode_BRANCH_CTRL_3; - wire _zz_decode_BRANCH_CTRL_4; - wire _zz_decode_BRANCH_CTRL_5; - wire _zz_decode_BRANCH_CTRL_6; - wire _zz_decode_BRANCH_CTRL_7; - wire _zz_decode_BRANCH_CTRL_8; - wire [1:0] _zz_decode_SRC1_CTRL_2; - wire [1:0] _zz_decode_ALU_CTRL_2; - wire [1:0] _zz_decode_SRC2_CTRL_2; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; - wire [1:0] _zz_decode_SHIFT_CTRL_2; - wire [1:0] _zz_decode_ENV_CTRL_2; - wire [1:0] _zz_decode_BRANCH_CTRL_9; - wire when_RegFilePlugin_l63; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_2; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_execute_REGFILE_WRITE_DATA; - reg [31:0] _zz_decode_SRC1_1; - wire _zz_decode_SRC2_2; - reg [19:0] _zz_decode_SRC2_3; - wire _zz_decode_SRC2_4; - reg [19:0] _zz_decode_SRC2_5; - reg [31:0] _zz_decode_SRC2_6; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_decode_RS2_3; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire when_HazardSimplePlugin_l47; - wire when_HazardSimplePlugin_l48; - wire when_HazardSimplePlugin_l51; - wire when_HazardSimplePlugin_l45; - wire when_HazardSimplePlugin_l57; - wire when_HazardSimplePlugin_l58; - wire when_HazardSimplePlugin_l48_1; - wire when_HazardSimplePlugin_l51_1; - wire when_HazardSimplePlugin_l45_1; - wire when_HazardSimplePlugin_l57_1; - wire when_HazardSimplePlugin_l58_1; - wire when_HazardSimplePlugin_l48_2; - wire when_HazardSimplePlugin_l51_2; - wire when_HazardSimplePlugin_l45_2; - wire when_HazardSimplePlugin_l57_2; - wire when_HazardSimplePlugin_l58_2; - wire when_HazardSimplePlugin_l105; - wire when_HazardSimplePlugin_l108; - wire when_HazardSimplePlugin_l113; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - reg [0:0] execute_MulPlugin_delayLogic_counter; - wire when_MulPlugin_l65; - wire when_MulPlugin_l70; - wire [1:0] switch_MulPlugin_l87; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; - wire [65:0] writeBack_MulPlugin_result; - wire when_MulPlugin_l147; - wire [1:0] switch_MulPlugin_l148; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - wire when_MulDivIterativePlugin_l126; - wire when_MulDivIterativePlugin_l126_1; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l128; - wire when_MulDivIterativePlugin_l129; - wire when_MulDivIterativePlugin_l132; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire when_MulDivIterativePlugin_l151; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l162; - wire _zz_memory_MulDivIterativePlugin_rs2; - wire _zz_memory_MulDivIterativePlugin_rs1; - reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle; - reg [63:0] CsrPlugin_minstret; - wire _zz_when_CsrPlugin_l965; - wire _zz_when_CsrPlugin_l965_1; - wire _zz_when_CsrPlugin_l965_2; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; - wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire when_CsrPlugin_l922; - wire when_CsrPlugin_l922_1; - wire when_CsrPlugin_l922_2; - wire when_CsrPlugin_l922_3; - wire when_CsrPlugin_l935; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire when_CsrPlugin_l959; - wire when_CsrPlugin_l965; - wire when_CsrPlugin_l965_1; - wire when_CsrPlugin_l965_2; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_pcValids_0; - reg CsrPlugin_pipelineLiberator_pcValids_1; - reg CsrPlugin_pipelineLiberator_pcValids_2; - wire CsrPlugin_pipelineLiberator_active; - wire when_CsrPlugin_l993; - wire when_CsrPlugin_l993_1; - wire when_CsrPlugin_l993_2; - wire when_CsrPlugin_l998; - reg CsrPlugin_pipelineLiberator_done; - wire when_CsrPlugin_l1004; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException /* verilator public */ ; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire when_CsrPlugin_l1032; - wire when_CsrPlugin_l1077; - wire [1:0] switch_CsrPlugin_l1081; - reg execute_CsrPlugin_wfiWake; - wire when_CsrPlugin_l1129; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - wire when_CsrPlugin_l1142; - wire when_CsrPlugin_l1149; - wire when_CsrPlugin_l1150; - wire when_CsrPlugin_l1157; - wire when_CsrPlugin_l1167; - reg execute_CsrPlugin_writeInstruction; - reg execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - wire switch_Misc_l210_1; - reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; - wire when_CsrPlugin_l1189; - wire when_CsrPlugin_l1193; - wire [11:0] execute_CsrPlugin_csrAddress; - wire execute_BranchPlugin_eq; - wire [2:0] switch_Misc_l210_2; - reg _zz_execute_BRANCH_DO; - reg _zz_execute_BRANCH_DO_1; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_execute_BranchPlugin_branch_src2; - reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; - wire _zz_execute_BranchPlugin_branch_src2_2; - reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; - wire _zz_execute_BranchPlugin_branch_src2_4; - reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; - reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - wire when_DebugPlugin_l225; - reg DebugPlugin_haltedByBreak; - reg DebugPlugin_debugUsed /* verilator public */ ; - reg DebugPlugin_disableEbreak; - wire DebugPlugin_allowEBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_when_DebugPlugin_l244; - wire when_DebugPlugin_l244; - wire [5:0] switch_DebugPlugin_l267; - wire when_DebugPlugin_l271; - wire when_DebugPlugin_l271_1; - wire when_DebugPlugin_l272; - wire when_DebugPlugin_l272_1; - wire when_DebugPlugin_l273; - wire when_DebugPlugin_l274; - wire when_DebugPlugin_l275; - wire when_DebugPlugin_l275_1; - wire when_DebugPlugin_l295; - wire when_DebugPlugin_l298; - wire when_DebugPlugin_l311; - reg DebugPlugin_resetIt_regNext; - wire when_DebugPlugin_l331; - wire when_Pipeline_l124; - reg [31:0] decode_to_execute_PC; - wire when_Pipeline_l124_1; - reg [31:0] execute_to_memory_PC; - wire when_Pipeline_l124_2; - reg [31:0] memory_to_writeBack_PC; - wire when_Pipeline_l124_3; - reg [31:0] decode_to_execute_INSTRUCTION; - wire when_Pipeline_l124_4; - reg [31:0] execute_to_memory_INSTRUCTION; - wire when_Pipeline_l124_5; - reg [31:0] memory_to_writeBack_INSTRUCTION; - wire when_Pipeline_l124_6; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - wire when_Pipeline_l124_7; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - wire when_Pipeline_l124_8; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - wire when_Pipeline_l124_9; - reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - wire when_Pipeline_l124_10; - reg decode_to_execute_SRC_USE_SUB_LESS; - wire when_Pipeline_l124_11; - reg decode_to_execute_MEMORY_ENABLE; - wire when_Pipeline_l124_12; - reg execute_to_memory_MEMORY_ENABLE; - wire when_Pipeline_l124_13; - reg memory_to_writeBack_MEMORY_ENABLE; - wire when_Pipeline_l124_14; - reg [1:0] decode_to_execute_ALU_CTRL; - wire when_Pipeline_l124_15; - reg decode_to_execute_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_16; - reg execute_to_memory_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_17; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_18; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - wire when_Pipeline_l124_19; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_20; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_21; - reg decode_to_execute_MEMORY_WR; - wire when_Pipeline_l124_22; - reg execute_to_memory_MEMORY_WR; - wire when_Pipeline_l124_23; - reg memory_to_writeBack_MEMORY_WR; - wire when_Pipeline_l124_24; - reg decode_to_execute_MEMORY_MANAGMENT; - wire when_Pipeline_l124_25; - reg decode_to_execute_SRC_LESS_UNSIGNED; - wire when_Pipeline_l124_26; - reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; - wire when_Pipeline_l124_27; - reg [1:0] decode_to_execute_SHIFT_CTRL; - wire when_Pipeline_l124_28; - reg [1:0] execute_to_memory_SHIFT_CTRL; - wire when_Pipeline_l124_29; - reg decode_to_execute_IS_MUL; - wire when_Pipeline_l124_30; - reg execute_to_memory_IS_MUL; - wire when_Pipeline_l124_31; - reg memory_to_writeBack_IS_MUL; - wire when_Pipeline_l124_32; - reg decode_to_execute_IS_DIV; - wire when_Pipeline_l124_33; - reg execute_to_memory_IS_DIV; - wire when_Pipeline_l124_34; - reg decode_to_execute_IS_RS1_SIGNED; - wire when_Pipeline_l124_35; - reg decode_to_execute_IS_RS2_SIGNED; - wire when_Pipeline_l124_36; - reg decode_to_execute_IS_CSR; - wire when_Pipeline_l124_37; - reg [1:0] decode_to_execute_ENV_CTRL; - wire when_Pipeline_l124_38; - reg [1:0] execute_to_memory_ENV_CTRL; - wire when_Pipeline_l124_39; - reg [1:0] memory_to_writeBack_ENV_CTRL; - wire when_Pipeline_l124_40; - reg [1:0] decode_to_execute_BRANCH_CTRL; - wire when_Pipeline_l124_41; - reg [31:0] decode_to_execute_RS1; - wire when_Pipeline_l124_42; - reg [31:0] decode_to_execute_RS2; - wire when_Pipeline_l124_43; - reg decode_to_execute_SRC2_FORCE_ZERO; - wire when_Pipeline_l124_44; - reg [31:0] decode_to_execute_SRC1; - wire when_Pipeline_l124_45; - reg [31:0] decode_to_execute_SRC2; - wire when_Pipeline_l124_46; - reg decode_to_execute_CSR_WRITE_OPCODE; - wire when_Pipeline_l124_47; - reg decode_to_execute_CSR_READ_OPCODE; - wire when_Pipeline_l124_48; - reg decode_to_execute_DO_EBREAK; - wire when_Pipeline_l124_49; - reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_50; - reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_51; - (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; - wire when_Pipeline_l124_52; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_53; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_54; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - wire when_Pipeline_l124_55; - reg [31:0] execute_to_memory_MUL_LL; - wire when_Pipeline_l124_56; - reg [33:0] execute_to_memory_MUL_LH; - wire when_Pipeline_l124_57; - reg [33:0] execute_to_memory_MUL_HL; - wire when_Pipeline_l124_58; - reg [33:0] execute_to_memory_MUL_HH; - wire when_Pipeline_l124_59; - reg [33:0] memory_to_writeBack_MUL_HH; - wire when_Pipeline_l124_60; - reg execute_to_memory_BRANCH_DO; - wire when_Pipeline_l124_61; - reg [31:0] execute_to_memory_BRANCH_CALC; - wire when_Pipeline_l124_62; - reg [51:0] memory_to_writeBack_MUL_LOW; - wire when_Pipeline_l151; - wire when_Pipeline_l154; - wire when_Pipeline_l151_1; - wire when_Pipeline_l154_1; - wire when_Pipeline_l151_2; - wire when_Pipeline_l154_2; - reg [2:0] switch_Fetcher_l365; - wire when_Fetcher_l381; - wire when_Fetcher_l401; - wire when_CsrPlugin_l1277; - reg execute_CsrPlugin_csr_3860; - wire when_CsrPlugin_l1277_1; - reg execute_CsrPlugin_csr_769; - wire when_CsrPlugin_l1277_2; - reg execute_CsrPlugin_csr_768; - wire when_CsrPlugin_l1277_3; - reg execute_CsrPlugin_csr_836; - wire when_CsrPlugin_l1277_4; - reg execute_CsrPlugin_csr_772; - wire when_CsrPlugin_l1277_5; - reg execute_CsrPlugin_csr_773; - wire when_CsrPlugin_l1277_6; - reg execute_CsrPlugin_csr_833; - wire when_CsrPlugin_l1277_7; - reg execute_CsrPlugin_csr_832; - wire when_CsrPlugin_l1277_8; - reg execute_CsrPlugin_csr_834; - wire when_CsrPlugin_l1277_9; - reg execute_CsrPlugin_csr_835; - wire [1:0] switch_CsrPlugin_l723; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; - wire when_CsrPlugin_l1310; - wire when_CsrPlugin_l1315; - `ifndef SYNTHESIS - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; - reg [47:0] decode_ENV_CTRL_string; - reg [47:0] _zz_decode_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_decode_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_execute_BRANCH_CTRL_string; - reg [47:0] memory_ENV_CTRL_string; - reg [47:0] _zz_memory_ENV_CTRL_string; - reg [47:0] execute_ENV_CTRL_string; - reg [47:0] _zz_execute_ENV_CTRL_string; - reg [47:0] writeBack_ENV_CTRL_string; - reg [47:0] _zz_writeBack_ENV_CTRL_string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_memory_SHIFT_CTRL_string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_execute_SHIFT_CTRL_string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_decode_SRC2_CTRL_string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_decode_SRC1_CTRL_string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_execute_ALU_CTRL_string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_1_string; - reg [47:0] _zz_decode_ENV_CTRL_1_string; - reg [71:0] _zz_decode_SHIFT_CTRL_1_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; - reg [23:0] _zz_decode_SRC2_CTRL_1_string; - reg [63:0] _zz_decode_ALU_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_2_string; - reg [63:0] _zz_decode_ALU_CTRL_2_string; - reg [23:0] _zz_decode_SRC2_CTRL_2_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; - reg [71:0] _zz_decode_SHIFT_CTRL_2_string; - reg [47:0] _zz_decode_ENV_CTRL_2_string; - reg [31:0] _zz_decode_BRANCH_CTRL_9_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [47:0] decode_to_execute_ENV_CTRL_string; - reg [47:0] execute_to_memory_ENV_CTRL_string; - reg [47:0] memory_to_writeBack_ENV_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - `endif - - reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - - assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); - assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); - assign _zz_memory_MUL_LOW_2 = 52'h0; - assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; - assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; - assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; - assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; - assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; - assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); - assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; - assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; - assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; - assign _zz__zz_decode_SRC1_1 = 3'b100; - assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; - assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); - assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); - assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; - assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); - assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; - assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; - assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; - assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; - assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; - assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); - assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; - assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; - assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; - assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; - assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); - assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; - assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; - assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; - assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; - assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; - assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; - assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; - assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; - assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); - assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); - assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); - assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; - assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; - assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); - assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); - assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; - assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); - assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; - assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); - assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); - assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; - assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); - assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); - assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; - assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; - assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); - assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; - assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; - assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); - assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); - assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; - assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); - assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; - assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); - assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); - assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); - assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); - assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); - assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; - assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); - assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); - assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; - assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); - assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; - assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); - assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; - assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; - assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; - assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; - assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); - assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); - assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; - assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; - assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); - assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; - assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); - assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); - assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); - assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); - assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; - assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; - assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); - assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); - assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); - assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); - assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; - assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; - assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; - assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; - assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); - assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; - assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); - assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; - assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); - assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; - assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); - assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; - assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); - assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); - assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; - assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; - assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; - assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); - assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; - assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; - assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; - assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); - assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); - assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; - assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); - assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; - assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); - assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; - assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; - assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); - assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); - assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; - assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); - assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); - assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs1Data) begin - _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs2Data) begin - _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b IBusCachedPlugin_cache ( - .io_flush (IBusCachedPlugin_cache_io_flush ), //i - .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i - .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i - .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i - .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i - .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - DataCache_b62b14ffe6bb44e5a817b8d08e286c6b dataCache_1 ( - .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i - .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i - .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i - .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i - .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i - .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i - .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i - .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i - .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i - .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i - .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i - .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i - .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i - .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) - 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; - 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; - default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) - 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; - 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; - 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; - default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) - 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; - default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - `ifndef SYNTHESIS - always @(*) begin - case(decode_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; - default : decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; - default : memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; - default : execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; - default : writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; - default : _zz_decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_1) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; - default : _zz_decode_SRC2_CTRL_1_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_1) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_1_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_2) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_2_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_2) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_2_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_2) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; - default : _zz_decode_SRC2_CTRL_2_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_2) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_2) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_2) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_2_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_9) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_9_string = "????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - `endif - - assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; - assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; - assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; - assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; - assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; - assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; - assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; - assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; - assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); - assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); - assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); - assign decode_SRC2 = _zz_decode_SRC2_6; - assign decode_SRC1 = _zz_decode_SRC1_1; - assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; - assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; - assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; - assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; - assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; - assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; - assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; - assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; - assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; - assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; - assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; - assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; - assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; - assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; - assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; - assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign memory_PC = execute_to_memory_PC; - assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; - assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; - assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; - assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; - assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; - assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; - assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; - assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; - assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; - assign memory_MUL_HL = execute_to_memory_MUL_HL; - assign memory_MUL_LH = execute_to_memory_MUL_LH; - assign memory_MUL_LL = execute_to_memory_MUL_LL; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; - assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; - always @(*) begin - _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; - if(when_CsrPlugin_l1189) begin - _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; - end - end - - assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @(*) begin - decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr1Match) begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l51) begin - decode_RS2 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l51_1) begin - decode_RS2 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l51_2) begin - decode_RS2 = _zz_decode_RS2; - end - end - end - end - - always @(*) begin - decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr0Match) begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l48) begin - decode_RS1 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l48_1) begin - decode_RS1 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l48_2) begin - decode_RS1 = _zz_decode_RS2; - end - end - end - end - - assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @(*) begin - _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_SLL_1 : begin - _zz_decode_RS2_1 = _zz_decode_RS2_3; - end - ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin - _zz_decode_RS2_1 = memory_SHIFT_RIGHT; - end - default : begin - end - endcase - end - if(when_MulDivIterativePlugin_l128) begin - _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; - end - end - - assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; - assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; - assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; - assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; - assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_decode_SRC2 = decode_PC; - assign _zz_decode_SRC2_1 = decode_RS2; - assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; - assign _zz_decode_SRC1 = decode_RS1; - assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; - assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; - assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; - assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; - assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; - assign execute_SRC2 = decode_to_execute_SRC2; - assign execute_SRC1 = decode_to_execute_SRC1; - assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; - assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; - assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; - always @(*) begin - _zz_1 = 1'b0; - if(lastStageRegFileWrite_valid) begin - _zz_1 = 1'b1; - end - end - - assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); - always @(*) begin - decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; - if(when_RegFilePlugin_l63) begin - decode_REGFILE_WRITE_VALID = 1'b0; - end - end - - assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); - always @(*) begin - _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; - if(when_DBusCachedPlugin_l492) begin - _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; - end - if(when_MulPlugin_l147) begin - case(switch_MulPlugin_l148) - 2'b00 : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; - end - default : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; - end - endcase - end - end - - assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; - assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; - assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - assign execute_RS1 = decode_to_execute_RS1; - assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; - assign execute_RS2 = decode_to_execute_RS2; - assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = execute_SrcPlugin_addSub; - assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; - assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; - end - end - - always @(*) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; - end - end - - assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; - assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @(*) begin - decode_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l308) begin - decode_arbitration_haltItself = 1'b1; - end - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_haltItself = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - decode_arbitration_haltByOther = 1'b0; - if(when_HazardSimplePlugin_l113) begin - decode_arbitration_haltByOther = 1'b1; - end - if(CsrPlugin_pipelineLiberator_active) begin - decode_arbitration_haltByOther = 1'b1; - end - if(when_CsrPlugin_l1129) begin - decode_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - decode_arbitration_removeIt = 1'b0; - if(_zz_when) begin - decode_arbitration_removeIt = 1'b1; - end - if(decode_arbitration_isFlushed) begin - decode_arbitration_removeIt = 1'b1; - end - end - - assign decode_arbitration_flushIt = 1'b0; - always @(*) begin - decode_arbitration_flushNext = 1'b0; - if(_zz_when) begin - decode_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - execute_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l350) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_MulPlugin_l65) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_CsrPlugin_l1193) begin - if(execute_CsrPlugin_blockedBySideEffects) begin - execute_arbitration_haltItself = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_haltByOther = 1'b0; - if(when_DBusCachedPlugin_l366) begin - execute_arbitration_haltByOther = 1'b1; - end - if(when_DebugPlugin_l295) begin - execute_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_removeIt = 1'b1; - end - if(execute_arbitration_isFlushed) begin - execute_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - execute_arbitration_flushIt = 1'b0; - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushIt = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_flushNext = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushNext = 1'b1; - end - end - end - - always @(*) begin - memory_arbitration_haltItself = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l129) begin - memory_arbitration_haltItself = 1'b1; - end - end - end - - assign memory_arbitration_haltByOther = 1'b0; - always @(*) begin - memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed) begin - memory_arbitration_removeIt = 1'b1; - end - end - - assign memory_arbitration_flushIt = 1'b0; - always @(*) begin - memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid) begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l466) begin - writeBack_arbitration_haltItself = 1'b1; - end - end - - assign writeBack_arbitration_haltByOther = 1'b0; - always @(*) begin - writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_removeIt = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - writeBack_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1032) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1077) begin - writeBack_arbitration_flushNext = 1'b1; - end - end - - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @(*) begin - IBusCachedPlugin_fetcherHalt = 1'b0; - if(when_CsrPlugin_l935) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1032) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1077) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - if(DebugPlugin_haltIt) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l311) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - - assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; - always @(*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if(when_Fetcher_l243) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - end - - always @(*) begin - _zz_when_DBusCachedPlugin_l393 = 1'b0; - if(DebugPlugin_godmode) begin - _zz_when_DBusCachedPlugin_l393 = 1'b1; - end - end - - assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; - assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; - assign CsrPlugin_inWfi = 1'b0; - always @(*) begin - CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt) begin - CsrPlugin_thirdPartyWake = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_valid = 1'b0; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - if(when_CsrPlugin_l1077) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; - end - default : begin - end - endcase - end - end - - always @(*) begin - CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode) begin - CsrPlugin_forceMachineWire = 1'b1; - end - end - - always @(*) begin - CsrPlugin_allowInterrupts = 1'b1; - if(when_DebugPlugin_l331) begin - CsrPlugin_allowInterrupts = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode) begin - CsrPlugin_allowException = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowEbreakException = 1'b1; - if(DebugPlugin_allowEBreak) begin - CsrPlugin_allowEbreakException = 1'b0; - end - end - - always @(*) begin - BranchPlugin_inDebugNoFetchFlag = 1'b0; - if(DebugPlugin_godmode) begin - BranchPlugin_inDebugNoFetchFlag = 1'b1; - end - end - - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - always @(*) begin - IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - end - - assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @(*) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; - end - end - - assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); - assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); - always @(*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; - end - IBusCachedPlugin_fetchPc_pc[0] = 1'b0; - IBusCachedPlugin_fetchPc_pc[1] = 1'b0; - end - - always @(*) begin - IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - end - - assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); - assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); - assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @(*) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; - end - end - - assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; - assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if(when_IBusCachedPlugin_l267) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; - assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - if(when_Fetcher_l323) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - end - - assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); - assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); - assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); - assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); - assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); - assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); - assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); - assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); - assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; - assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; - assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; - assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - always @(*) begin - decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_isValid = 1'b1; - end - 3'b011 : begin - decode_arbitration_isValid = 1'b1; - end - default : begin - end - endcase - if(IBusCachedPlugin_forceNoDecodeCond) begin - decode_arbitration_isValid = 1'b0; - end - end - - assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @(*) begin - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - end - - assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; - assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; - assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); - assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; - assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @(*) begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; - assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); - assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; - assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; - assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); - always @(*) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; - assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); - assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; - always @(*) begin - case(execute_DBusCachedPlugin_size) - 2'b00 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; - end - 2'b01 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; - end - default : begin - _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; - end - endcase - end - - assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); - assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; - assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); - assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); - assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); - assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; - assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; - assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @(*) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if(when_DBusCachedPlugin_l393) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; - end - end - - assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); - always @(*) begin - dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - if(writeBack_arbitration_haltByOther) begin - dataCache_1_io_cpu_writeBack_isValid = 1'b0; - end - end - - assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); - assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; - assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; - always @(*) begin - DBusCachedPlugin_redoBranch_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_redoBranch_valid = 1'b1; - end - end - end - - assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @(*) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - end - end - end - - assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @(*) begin - DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; - end - end - end - - assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); - assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; - assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; - assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; - assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; - always @(*) begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; - writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; - writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; - writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; - end - - assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; - assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; - end - - assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; - end - - always @(*) begin - case(switch_Misc_l210) - 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; - end - 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; - end - default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; - end - endcase - end - - assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); - assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); - assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; - assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; - assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; - assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; - assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; - assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; - assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; - assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; - assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; - assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; - assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; - assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; - assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; - assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; - assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; - assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = 4'b0010; - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; - assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); - assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; - assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; - assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; - always @(*) begin - lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - if(_zz_2) begin - lastStageRegFileWrite_valid = 1'b1; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - if(_zz_2) begin - lastStageRegFileWrite_payload_address = 5'h0; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; - if(_zz_2) begin - lastStageRegFileWrite_payload_data = 32'h0; - end - end - - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_AND_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); - end - AluBitwiseCtrlEnum_OR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); - end - default : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); - end - endcase - end - - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_BITWISE : begin - _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; - end - AluCtrlEnum_SLT_SLTU : begin - _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; - end - default : begin - _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; - end - endcase - end - - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : begin - _zz_decode_SRC1_1 = _zz_decode_SRC1; - end - Src1CtrlEnum_PC_INCREMENT : begin - _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; - end - Src1CtrlEnum_IMU : begin - _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; - end - default : begin - _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; - end - endcase - end - - assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; - always @(*) begin - _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; - end - - assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; - always @(*) begin - _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; - end - - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2_1; - end - Src2CtrlEnum_IMI : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; - end - Src2CtrlEnum_IMS : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; - end - default : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2; - end - endcase - end - - always @(*) begin - execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; - if(execute_SRC2_FORCE_ZERO) begin - execute_SrcPlugin_addSub = execute_SRC1; - end - end - - assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @(*) begin - _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; - _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; - _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; - _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; - _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; - _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; - _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; - _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; - _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; - _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; - _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; - _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; - _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; - _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; - _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; - _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; - _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; - _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; - _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; - _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; - _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; - _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; - _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; - _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; - _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; - _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; - _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; - _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; - _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; - _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; - _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; - _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); - always @(*) begin - _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; - _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; - _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; - _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; - _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; - _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; - _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; - _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; - _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; - _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; - _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; - _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; - _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; - _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; - _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; - _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; - _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; - _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; - _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; - _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; - _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; - _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; - _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; - _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; - _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; - _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; - _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; - _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; - _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; - _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; - _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; - _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; - end - - always @(*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l48) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l48_1) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l48_2) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l105) begin - HazardSimplePlugin_src0Hazard = 1'b0; - end - end - - always @(*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l51) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l51_1) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l51_2) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l108) begin - HazardSimplePlugin_src1Hazard = 1'b0; - end - end - - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l47 = 1'b1; - assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); - assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); - assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); - assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); - assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); - assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); - assign execute_MulPlugin_a = execute_RS1; - assign execute_MulPlugin_b = execute_RS2; - assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_aSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_aSigned = 1'b1; - end - default : begin - execute_MulPlugin_aSigned = 1'b0; - end - endcase - end - - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_bSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_bSigned = 1'b0; - end - default : begin - execute_MulPlugin_bSigned = 1'b0; - end - endcase - end - - assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; - assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; - assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; - assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; - assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; - assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); - assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); - assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; - end - end - end - - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; - end - end - - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); - assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); - always @(*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); - end - if(memory_MulDivIterativePlugin_div_counter_willClear) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end - end - - assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); - assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); - assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); - assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; - assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); - assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @(*) begin - _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; - end - - always @(*) begin - CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire) begin - CsrPlugin_privilege = 2'b11; - end - end - - assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; - end - if(decode_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; - end - if(execute_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; - end - end - - assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); - assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); - assign CsrPlugin_lastStageWasWfi = 1'b0; - assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); - always @(*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(when_CsrPlugin_l1004) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - if(CsrPlugin_hadException) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - end - - assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); - assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @(*) begin - CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException) begin - CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - end - end - - always @(*) begin - CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException) begin - CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; - end - end - - always @(*) begin - CsrPlugin_xtvec_mode = 2'bxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; - end - default : begin - end - endcase - end - - always @(*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; - end - default : begin - end - endcase - end - - assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); - assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; - assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); - assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); - always @(*) begin - execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3860) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_769) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_768) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_836) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_772) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_773) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_833) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_832) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_834) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_835) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(CsrPlugin_csrMapping_allowCsrSignal) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_illegalAccess = 1'b1; - end - if(when_CsrPlugin_l1315) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_illegalInstruction = 1'b0; - if(when_CsrPlugin_l1149) begin - if(when_CsrPlugin_l1150) begin - execute_CsrPlugin_illegalInstruction = 1'b1; - end - end - end - - always @(*) begin - CsrPlugin_selfException_valid = 1'b0; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1157) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_selfException_payload_code = 4'bxxxx; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_payload_code = 4'b0010; - end - if(when_CsrPlugin_l1157) begin - case(CsrPlugin_privilege) - 2'b00 : begin - CsrPlugin_selfException_payload_code = 4'b1000; - end - default : begin - CsrPlugin_selfException_payload_code = 4'b1011; - end - endcase - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_payload_code = 4'b0011; - end - end - - assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); - assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); - assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); - assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); - always @(*) begin - execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_writeInstruction = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_readInstruction = 1'b0; - end - end - - assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); - assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; - assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; - always @(*) begin - case(switch_Misc_l210_1) - 1'b0 : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; - end - default : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); - end - endcase - end - - assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; - assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); - assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); - assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; - always @(*) begin - casez(switch_Misc_l210_2) - 3'b000 : begin - _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; - end - 3'b001 : begin - _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); - end - 3'b1?1 : begin - _zz_execute_BRANCH_DO = (! execute_SRC_LESS); - end - default : begin - _zz_execute_BRANCH_DO = execute_SRC_LESS; - end - endcase - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : begin - _zz_execute_BRANCH_DO_1 = 1'b0; - end - BranchCtrlEnum_JAL : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - default : begin - _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; - end - endcase - end - - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); - assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; - end - - assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; - end - - assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_JAL : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; - end - default : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - end - endcase - end - - assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); - assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); - always @(*) begin - debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; - end - end - default : begin - end - endcase - end - end - - always @(*) begin - debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if(when_DebugPlugin_l244) begin - debug_bus_rsp_data[0] = DebugPlugin_resetIt; - debug_bus_rsp_data[1] = DebugPlugin_haltIt; - debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; - debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; - debug_bus_rsp_data[4] = DebugPlugin_stepIt; - end - end - - assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); - always @(*) begin - IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - IBusCachedPlugin_injectionPort_valid = 1'b1; - end - end - default : begin - end - endcase - end - end - - assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; - assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; - assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; - assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; - assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; - assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; - assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); - assign when_Pipeline_l124 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); - assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); - assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; - assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; - assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; - assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; - assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; - assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; - assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; - assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; - assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; - assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; - assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); - assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; - assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); - assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; - assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; - assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; - assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; - assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; - assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); - assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; - assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); - assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; - assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); - assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; - assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; - assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); - assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; - assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); - assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); - assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); - assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - always @(*) begin - IBusCachedPlugin_injectionPort_ready = 1'b0; - case(switch_Fetcher_l365) - 3'b100 : begin - IBusCachedPlugin_injectionPort_ready = 1'b1; - end - default : begin - end - endcase - end - - assign when_Fetcher_l381 = (! decode_arbitration_isStuck); - assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); - assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); - assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; - if(execute_CsrPlugin_csr_768) begin - _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; - if(execute_CsrPlugin_csr_836) begin - _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; - if(execute_CsrPlugin_csr_772) begin - _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; - if(execute_CsrPlugin_csr_773) begin - _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; - _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; - if(execute_CsrPlugin_csr_833) begin - _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; - if(execute_CsrPlugin_csr_832) begin - _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; - if(execute_CsrPlugin_csr_834) begin - _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; - if(execute_CsrPlugin_csr_835) begin - _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; - end - end - - assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); - assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - IBusCachedPlugin_fetchPc_booted <= 1'b0; - IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - IBusCachedPlugin_rspCounter <= 32'h0; - dataCache_1_io_mem_cmd_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dBus_rsp_regNext_valid <= 1'b0; - DBusCachedPlugin_rspCounter <= 32'h0; - _zz_2 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; - memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - CsrPlugin_misa_base <= 2'b01; - CsrPlugin_misa_extensions <= 26'h0041101; - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= 2'b11; - CsrPlugin_mie_MEIE <= 1'b0; - CsrPlugin_mie_MTIE <= 1'b0; - CsrPlugin_mie_MSIE <= 1'b0; - CsrPlugin_mcycle <= 64'h0; - CsrPlugin_minstret <= 64'h0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - CsrPlugin_interrupt_valid <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - CsrPlugin_hadException <= 1'b0; - execute_CsrPlugin_wfiWake <= 1'b0; - execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - switch_Fetcher_l365 <= 3'b000; - end else begin - if(IBusCachedPlugin_fetchPc_correction) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_output_fire) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - end - IBusCachedPlugin_fetchPc_booted <= 1'b1; - if(when_Fetcher_l134) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_output_fire_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b1; - end - if(when_Fetcher_l134_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(when_Fetcher_l161) begin - IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - end - if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); - end - if(decode_arbitration_removeIt) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - end - if(when_Fetcher_l332) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(when_Fetcher_l332_1) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(when_Fetcher_l332_2) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(when_Fetcher_l332_3) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(when_Fetcher_l332_4) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(when_Fetcher_l332_5) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(iBus_rsp_valid) begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); - end - if(dataCache_1_io_mem_cmd_valid) begin - dataCache_1_io_mem_cmd_rValid <= 1'b1; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_rValid <= 1'b0; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; - end - dBus_rsp_regNext_valid <= dBus_rsp_valid; - if(dBus_rsp_valid) begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); - end - _zz_2 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; - memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring) begin - CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); - end - if(when_CsrPlugin_l922) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - end - if(when_CsrPlugin_l922_1) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if(when_CsrPlugin_l922_2) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if(when_CsrPlugin_l922_3) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - end - CsrPlugin_interrupt_valid <= 1'b0; - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - end - if(CsrPlugin_pipelineLiberator_active) begin - if(when_CsrPlugin_l993) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; - end - if(when_CsrPlugin_l993_1) begin - CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; - end - if(when_CsrPlugin_l993_2) begin - CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; - end - end - if(when_CsrPlugin_l998) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - end - if(CsrPlugin_interruptJump) begin - CsrPlugin_interrupt_valid <= 1'b0; - end - CsrPlugin_hadException <= CsrPlugin_exception; - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; - CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; - end - default : begin - end - endcase - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b00; - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; - end - default : begin - end - endcase - end - execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(when_Pipeline_l151) begin - execute_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154) begin - execute_arbitration_isValid <= decode_arbitration_isValid; - end - if(when_Pipeline_l151_1) begin - memory_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_1) begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(when_Pipeline_l151_2) begin - writeBack_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_2) begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(switch_Fetcher_l365) - 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid) begin - switch_Fetcher_l365 <= 3'b001; - end - end - 3'b001 : begin - switch_Fetcher_l365 <= 3'b010; - end - 3'b010 : begin - switch_Fetcher_l365 <= 3'b011; - end - 3'b011 : begin - if(when_Fetcher_l381) begin - switch_Fetcher_l365 <= 3'b100; - end - end - 3'b100 : begin - switch_Fetcher_l365 <= 3'b000; - end - default : begin - end - endcase - if(execute_CsrPlugin_csr_769) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; - CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; - end - end - if(execute_CsrPlugin_csr_768) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - case(switch_CsrPlugin_l723) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b11; - end - default : begin - end - endcase - end - end - if(execute_CsrPlugin_csr_772) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; - CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - end - end - - always @(posedge io_systemClk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; - end - if(IBusCachedPlugin_injector_decodeInput_ready) begin - IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; - end - if(dataCache_1_io_mem_cmd_ready) begin - dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; - dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; - dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; - dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; - execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); - if(when_MulPlugin_l70) begin - execute_MulPlugin_delayLogic_counter <= 1'b0; - end - execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - if(when_MulDivIterativePlugin_l126) begin - memory_MulDivIterativePlugin_div_done <= 1'b1; - end - if(when_MulDivIterativePlugin_l126_1) begin - memory_MulDivIterativePlugin_div_done <= 1'b0; - end - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if(when_MulDivIterativePlugin_l151) begin - memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; - end - end - end - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); - memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; - end - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_code <= 4'b0111; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_code <= 4'b0011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_code <= 4'b1011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - end - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException) begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase - end - if(when_Pipeline_l124) begin - decode_to_execute_PC <= _zz_decode_SRC2; - end - if(when_Pipeline_l124_1) begin - execute_to_memory_PC <= execute_PC; - end - if(when_Pipeline_l124_2) begin - memory_to_writeBack_PC <= memory_PC; - end - if(when_Pipeline_l124_3) begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; - end - if(when_Pipeline_l124_4) begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; - end - if(when_Pipeline_l124_5) begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if(when_Pipeline_l124_6) begin - decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_7) begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_8) begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_9) begin - decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; - end - if(when_Pipeline_l124_10) begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; - end - if(when_Pipeline_l124_11) begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; - end - if(when_Pipeline_l124_12) begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; - end - if(when_Pipeline_l124_13) begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if(when_Pipeline_l124_14) begin - decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; - end - if(when_Pipeline_l124_15) begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_16) begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_17) begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_18) begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; - end - if(when_Pipeline_l124_19) begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_20) begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_21) begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; - end - if(when_Pipeline_l124_22) begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; - end - if(when_Pipeline_l124_23) begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; - end - if(when_Pipeline_l124_24) begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; - end - if(when_Pipeline_l124_25) begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; - end - if(when_Pipeline_l124_26) begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; - end - if(when_Pipeline_l124_27) begin - decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; - end - if(when_Pipeline_l124_28) begin - execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; - end - if(when_Pipeline_l124_29) begin - decode_to_execute_IS_MUL <= decode_IS_MUL; - end - if(when_Pipeline_l124_30) begin - execute_to_memory_IS_MUL <= execute_IS_MUL; - end - if(when_Pipeline_l124_31) begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; - end - if(when_Pipeline_l124_32) begin - decode_to_execute_IS_DIV <= decode_IS_DIV; - end - if(when_Pipeline_l124_33) begin - execute_to_memory_IS_DIV <= execute_IS_DIV; - end - if(when_Pipeline_l124_34) begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; - end - if(when_Pipeline_l124_35) begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; - end - if(when_Pipeline_l124_36) begin - decode_to_execute_IS_CSR <= decode_IS_CSR; - end - if(when_Pipeline_l124_37) begin - decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; - end - if(when_Pipeline_l124_38) begin - execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; - end - if(when_Pipeline_l124_39) begin - memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; - end - if(when_Pipeline_l124_40) begin - decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; - end - if(when_Pipeline_l124_41) begin - decode_to_execute_RS1 <= _zz_decode_SRC1; - end - if(when_Pipeline_l124_42) begin - decode_to_execute_RS2 <= _zz_decode_SRC2_1; - end - if(when_Pipeline_l124_43) begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; - end - if(when_Pipeline_l124_44) begin - decode_to_execute_SRC1 <= decode_SRC1; - end - if(when_Pipeline_l124_45) begin - decode_to_execute_SRC2 <= decode_SRC2; - end - if(when_Pipeline_l124_46) begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; - end - if(when_Pipeline_l124_47) begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; - end - if(when_Pipeline_l124_48) begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; - end - if(when_Pipeline_l124_49) begin - execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_50) begin - memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_51) begin - execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; - end - if(when_Pipeline_l124_52) begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; - end - if(when_Pipeline_l124_53) begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; - end - if(when_Pipeline_l124_54) begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; - end - if(when_Pipeline_l124_55) begin - execute_to_memory_MUL_LL <= execute_MUL_LL; - end - if(when_Pipeline_l124_56) begin - execute_to_memory_MUL_LH <= execute_MUL_LH; - end - if(when_Pipeline_l124_57) begin - execute_to_memory_MUL_HL <= execute_MUL_HL; - end - if(when_Pipeline_l124_58) begin - execute_to_memory_MUL_HH <= execute_MUL_HH; - end - if(when_Pipeline_l124_59) begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; - end - if(when_Pipeline_l124_60) begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if(when_Pipeline_l124_61) begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end - if(when_Pipeline_l124_62) begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; - end - if(when_Fetcher_l401) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; - end - if(when_CsrPlugin_l1277) begin - execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); - end - if(when_CsrPlugin_l1277_1) begin - execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); - end - if(when_CsrPlugin_l1277_2) begin - execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); - end - if(when_CsrPlugin_l1277_3) begin - execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); - end - if(when_CsrPlugin_l1277_4) begin - execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); - end - if(when_CsrPlugin_l1277_5) begin - execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); - end - if(when_CsrPlugin_l1277_6) begin - execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); - end - if(when_CsrPlugin_l1277_7) begin - execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); - end - if(when_CsrPlugin_l1277_8) begin - execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); - end - if(when_CsrPlugin_l1277_9) begin - execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); - end - if(execute_CsrPlugin_csr_836) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - if(execute_CsrPlugin_csr_773) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; - CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; - end - end - if(execute_CsrPlugin_csr_833) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_832) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - end - - always @(posedge io_systemClk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready) begin - DebugPlugin_firstCycle <= 1'b1; - end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid) begin - DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; - end - _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; - if(when_DebugPlugin_l295) begin - DebugPlugin_busReadDataReg <= execute_PC; - end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - DebugPlugin_debugUsed <= 1'b0; - DebugPlugin_disableEbreak <= 1'b0; - end else begin - if(when_DebugPlugin_l225) begin - DebugPlugin_godmode <= 1'b1; - end - if(debug_bus_cmd_valid) begin - DebugPlugin_debugUsed <= 1'b1; - end - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h0 : begin - if(debug_bus_cmd_payload_wr) begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(when_DebugPlugin_l271) begin - DebugPlugin_resetIt <= 1'b1; - end - if(when_DebugPlugin_l271_1) begin - DebugPlugin_resetIt <= 1'b0; - end - if(when_DebugPlugin_l272) begin - DebugPlugin_haltIt <= 1'b1; - end - if(when_DebugPlugin_l272_1) begin - DebugPlugin_haltIt <= 1'b0; - end - if(when_DebugPlugin_l273) begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(when_DebugPlugin_l274) begin - DebugPlugin_godmode <= 1'b0; - end - if(when_DebugPlugin_l275) begin - DebugPlugin_disableEbreak <= 1'b1; - end - if(when_DebugPlugin_l275_1) begin - DebugPlugin_disableEbreak <= 1'b0; - end - end - end - default : begin - end - endcase - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end - end - if(when_DebugPlugin_l311) begin - if(decode_arbitration_isValid) begin - DebugPlugin_haltIt <= 1'b1; - end - end - end - end - - -endmodule - -module BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin - if(debugCd_logic_outputReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input io_asyncReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge io_asyncReset) begin - if(io_asyncReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload_data; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [7:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload_data = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload_data) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload_data; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_push_valid, - output io_push_ready, - input io_push_payload_kind, - input io_push_payload_read, - input io_push_payload_write, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output io_pop_payload_kind, - output io_pop_payload_read, - output io_pop_payload_write, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [10:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz__zz_io_pop_payload_kind; - wire [10:0] _zz_logic_ram_port_1; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [10:0] _zz_io_pop_payload_kind; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [10:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_kind = 1'b1; - assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; - always @(posedge io_systemClk) begin - if(_zz__zz_io_pop_payload_kind) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; - assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; - assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; - assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; - assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_config_kind_cpol, - input io_config_kind_cpha, - input [11:0] io_config_sclkToogle, - input [1:0] io_config_mod, - input [0:0] io_config_ss_activeHigh, - input [11:0] io_config_ss_setup, - input [11:0] io_config_ss_hold, - input [11:0] io_config_ss_disable, - input io_cmd_valid, - output reg io_cmd_ready, - input io_cmd_payload_kind, - input io_cmd_payload_read, - input io_cmd_payload_write, - input [7:0] io_cmd_payload_data, - output io_rsp_valid, - output [7:0] io_rsp_payload_data, - output [0:0] io_spi_sclk_write, - output reg io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output reg [0:0] io_spi_data_0_write, - output reg io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output reg [0:0] io_spi_data_1_write, - output reg io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output reg [0:0] io_spi_data_2_write, - output reg io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output reg [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [0:0] _zz_outputPhy_dataWrite_3; - wire [2:0] _zz_outputPhy_dataWrite_4; - wire [2:0] _zz_outputPhy_dataWrite_5; - reg [1:0] _zz_outputPhy_dataWrite_6; - wire [1:0] _zz_outputPhy_dataWrite_7; - wire [2:0] _zz_outputPhy_dataWrite_8; - reg [3:0] _zz_outputPhy_dataWrite_9; - wire [0:0] _zz_outputPhy_dataWrite_10; - wire [2:0] _zz_outputPhy_dataWrite_11; - wire [3:0] _zz_inputPhy_dataRead; - wire [3:0] _zz_inputPhy_dataRead_1; - wire [3:0] _zz_inputPhy_dataRead_2; - wire [3:0] _zz_inputPhy_dataRead_3; - wire [3:0] _zz_inputPhy_dataRead_4; - wire [3:0] _zz_inputPhy_dataRead_5; - wire [3:0] _zz_inputPhy_dataRead_6; - wire [8:0] _zz_inputPhy_bufferNext; - wire [10:0] _zz_inputPhy_bufferNext_1; - reg [11:0] timer_counter; - reg timer_reset; - wire timer_ss_setupHit; - wire timer_ss_holdHit; - wire timer_ss_disableHit; - wire timer_sclkToogleHit; - reg fsm_state; - reg [2:0] fsm_counter; - reg [2:0] _zz_fsm_counterPlus; - wire [2:0] fsm_counterPlus; - reg fsm_fastRate; - reg fsm_isDdr; - reg [2:0] fsm_counterMax; - reg fsm_lateSampling; - reg fsm_readFill; - reg fsm_readDone; - reg [0:0] fsm_ss; - wire when_SpiXdrMasterCtrl_l739; - wire when_SpiXdrMasterCtrl_l742; - wire when_SpiXdrMasterCtrl_l749; - wire when_SpiXdrMasterCtrl_l751; - wire when_SpiXdrMasterCtrl_l758; - wire when_SpiXdrMasterCtrl_l764; - wire when_SpiXdrMasterCtrl_l781; - reg [0:0] outputPhy_sclkWrite; - wire [0:0] _zz_io_spi_sclk_write; - wire when_SpiXdrMasterCtrl_l796; - reg [3:0] outputPhy_dataWrite; - reg [2:0] outputPhy_widthSel; - reg [2:0] outputPhy_offset; - wire [7:0] _zz_outputPhy_dataWrite; - wire [7:0] _zz_outputPhy_dataWrite_1; - wire [7:0] _zz_outputPhy_dataWrite_2; - wire when_SpiXdrMasterCtrl_l839; - wire when_SpiXdrMasterCtrl_l839_1; - reg [1:0] io_config_mod_delay_1; - reg [1:0] inputPhy_mod; - reg fsm_readFill_delay_1; - reg inputPhy_readFill; - reg fsm_readDone_delay_1; - reg inputPhy_readDone; - reg [6:0] inputPhy_buffer; - reg [7:0] inputPhy_bufferNext; - reg [2:0] inputPhy_widthSel; - wire [3:0] inputPhy_dataWrite; - reg [3:0] inputPhy_dataRead; - reg fsm_state_delay_1; - reg fsm_state_delay_2; - wire when_SpiXdrMasterCtrl_l861; - reg [3:0] inputPhy_dataReadBuffer; - - assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); - assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); - assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); - assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); - assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; - assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; - always @(*) begin - case(_zz_outputPhy_dataWrite_4) - 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; - 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; - 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; - 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; - 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; - 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; - 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; - default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_7) - 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; - 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; - 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; - default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_10) - 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; - default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; - endcase - end - - always @(*) begin - timer_reset = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - timer_reset = timer_sclkToogleHit; - end else begin - if(!when_SpiXdrMasterCtrl_l758) begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - timer_reset = 1'b1; - end - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - timer_reset = 1'b1; - end - end - - assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); - assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); - assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); - assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); - always @(*) begin - _zz_fsm_counterPlus = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - _zz_fsm_counterPlus = 3'b001; - end - 2'b01 : begin - _zz_fsm_counterPlus = 3'b010; - end - 2'b10 : begin - _zz_fsm_counterPlus = 3'b100; - end - default : begin - end - endcase - end - - assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); - always @(*) begin - fsm_fastRate = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_fastRate = 1'b0; - end - 2'b01 : begin - fsm_fastRate = 1'b0; - end - 2'b10 : begin - fsm_fastRate = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_isDdr = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_isDdr = 1'b0; - end - 2'b01 : begin - fsm_isDdr = 1'b0; - end - 2'b10 : begin - fsm_isDdr = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_counterMax = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - fsm_counterMax = 3'b111; - end - 2'b01 : begin - fsm_counterMax = 3'b110; - end - 2'b10 : begin - fsm_counterMax = 3'b100; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_lateSampling = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_lateSampling = 1'b1; - end - 2'b01 : begin - fsm_lateSampling = 1'b1; - end - 2'b10 : begin - fsm_lateSampling = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_readFill = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readFill = 1'b1; - end - end - end - end - - always @(*) begin - fsm_readDone = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); - end - end - end - end - - assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); - always @(*) begin - io_cmd_ready = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l749) begin - if(when_SpiXdrMasterCtrl_l751) begin - io_cmd_ready = 1'b1; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - if(timer_ss_setupHit) begin - io_cmd_ready = 1'b1; - end - end else begin - if(!when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_disableHit) begin - io_cmd_ready = 1'b1; - end - end - end - end - end - end - - assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); - assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); - assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; - assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); - assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); - always @(*) begin - outputPhy_sclkWrite = 1'b0; - if(when_SpiXdrMasterCtrl_l796) begin - case(io_config_mod) - 2'b00 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b01 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b10 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - default : begin - end - endcase - end - end - - assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; - assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); - assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); - always @(*) begin - outputPhy_widthSel = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_widthSel = 3'b000; - end - 2'b01 : begin - outputPhy_widthSel = 3'b001; - end - 2'b10 : begin - outputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_offset = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_offset = 3'b111; - end - 2'b01 : begin - outputPhy_offset = 3'b111; - end - 2'b10 : begin - outputPhy_offset = 3'b111; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_dataWrite = 4'bxxxx; - case(outputPhy_widthSel) - 3'b000 : begin - outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; - end - 3'b001 : begin - outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; - end - 3'b010 : begin - outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; - end - default : begin - end - endcase - end - - assign _zz_outputPhy_dataWrite = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; - always @(*) begin - io_spi_data_0_writeEnable = 1'b0; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_writeEnable = 1'b1; - end - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_writeEnable = 1'b0; - case(io_config_mod) - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_2_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_3_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_0_write = 1'bx; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); - end - 2'b01 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - 2'b10 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_write = 1'bx; - case(io_config_mod) - 2'b01 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - 2'b10 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_2_write[0] = outputPhy_dataWrite[2]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_3_write[0] = outputPhy_dataWrite[3]; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); - assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); - always @(*) begin - inputPhy_bufferNext = 8'bxxxxxxxx; - case(inputPhy_widthSel) - 3'b000 : begin - inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; - end - 3'b001 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; - end - 3'b010 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; - end - default : begin - end - endcase - end - - always @(*) begin - inputPhy_widthSel = 3'bxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_widthSel = 3'b000; - end - 2'b01 : begin - inputPhy_widthSel = 3'b001; - end - 2'b10 : begin - inputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); - always @(*) begin - inputPhy_dataRead = 4'bxxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; - end - 2'b01 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; - end - 2'b10 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; - inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; - inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; - end - default : begin - end - endcase - end - - assign io_rsp_valid = inputPhy_readDone; - assign io_rsp_payload_data = inputPhy_bufferNext; - always @(posedge io_systemClk) begin - timer_counter <= (timer_counter + 12'h001); - if(timer_reset) begin - timer_counter <= 12'h0; - end - io_config_mod_delay_1 <= io_config_mod; - inputPhy_mod <= io_config_mod_delay_1; - fsm_state_delay_1 <= fsm_state; - fsm_state_delay_2 <= fsm_state_delay_1; - if(when_SpiXdrMasterCtrl_l861) begin - inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - end - case(inputPhy_widthSel) - 3'b000 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b001 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b010 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - default : begin - end - endcase - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - fsm_ss <= 1'b0; - fsm_readFill_delay_1 <= 1'b0; - inputPhy_readFill <= 1'b0; - fsm_readDone_delay_1 <= 1'b0; - inputPhy_readDone <= 1'b0; - end else begin - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(timer_sclkToogleHit) begin - fsm_state <= (! fsm_state); - end - if(when_SpiXdrMasterCtrl_l749) begin - fsm_counter <= fsm_counterPlus; - if(when_SpiXdrMasterCtrl_l751) begin - fsm_state <= 1'b0; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - fsm_ss[0] <= 1'b1; - end else begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - fsm_state <= 1'b1; - end - end else begin - fsm_ss[0] <= 1'b0; - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - end - fsm_readFill_delay_1 <= fsm_readFill; - inputPhy_readFill <= fsm_readFill_delay_1; - fsm_readDone_delay_1 <= fsm_readDone; - inputPhy_readDone <= fsm_readDone_delay_1; - end - end - - -endmodule - -//StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b replaced by StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b - -module StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload, - input io_flush, - output [7:0] io_occupancy, - output [7:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [6:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [6:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload; - wire [6:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [6:0] logic_pushPtr_valueNext; - reg [6:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [6:0] logic_popPtr_valueNext; - reg [6:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [6:0] logic_ptrDif; - reg [7:0] logic_ram [0:127]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 7'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 7'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload = _zz_logic_ram_port0; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 7'h0; - logic_popPtr_value <= 7'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( - input [2:0] io_config_frame_dataLength, - input [0:0] io_config_frame_stop, - input [1:0] io_config_frame_parity, - input [19:0] io_config_clockDivider, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - output io_uart_txd, - input io_uart_rxd, - output io_readError, - input io_writeBreak, - output io_readBreak, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - wire tx_io_write_ready; - wire tx_io_txd; - wire rx_io_read_valid; - wire [7:0] rx_io_read_payload; - wire rx_io_rts; - wire rx_io_error; - wire rx_io_break; - reg [19:0] clockDivider_counter; - wire clockDivider_tick; - reg clockDivider_tickReg; - reg io_write_thrown_valid; - wire io_write_thrown_ready; - wire [7:0] io_write_thrown_payload; - `ifndef SYNTHESIS - reg [23:0] io_config_frame_stop_string; - reg [31:0] io_config_frame_parity_string; - `endif - - - UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b tx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_write_valid (io_write_thrown_valid ), //i - .io_write_ready (tx_io_write_ready ), //o - .io_write_payload (io_write_thrown_payload[7:0] ), //i - .io_cts (1'b0 ), //i - .io_txd (tx_io_txd ), //o - .io_break (io_writeBreak ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b rx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_read_valid (rx_io_read_valid ), //o - .io_read_ready (io_read_ready ), //i - .io_read_payload (rx_io_read_payload[7:0] ), //o - .io_rxd (io_uart_rxd ), //i - .io_rts (rx_io_rts ), //o - .io_error (rx_io_error ), //o - .io_break (rx_io_break ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_config_frame_stop) - UartStopType_ONE : io_config_frame_stop_string = "ONE"; - UartStopType_TWO : io_config_frame_stop_string = "TWO"; - default : io_config_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_config_frame_parity) - UartParityType_NONE : io_config_frame_parity_string = "NONE"; - UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; - UartParityType_ODD : io_config_frame_parity_string = "ODD "; - default : io_config_frame_parity_string = "????"; - endcase - end - `endif - - assign clockDivider_tick = (clockDivider_counter == 20'h0); - always @(*) begin - io_write_thrown_valid = io_write_valid; - if(rx_io_break) begin - io_write_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_write_ready = io_write_thrown_ready; - if(rx_io_break) begin - io_write_ready = 1'b1; - end - end - - assign io_write_thrown_payload = io_write_payload; - assign io_write_thrown_ready = tx_io_write_ready; - assign io_read_valid = rx_io_read_valid; - assign io_read_payload = rx_io_read_payload; - assign io_uart_txd = tx_io_txd; - assign io_readError = rx_io_error; - assign io_readBreak = rx_io_break; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter <= 20'h0; - clockDivider_tickReg <= 1'b0; - end else begin - clockDivider_tickReg <= clockDivider_tick; - clockDivider_counter <= (clockDivider_counter - 20'h00001); - if(clockDivider_tick) begin - clockDivider_counter <= io_config_clockDivider; - end - end - end - - -endmodule - -module StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_inputs_0_valid, - output io_inputs_0_ready, - input io_inputs_0_payload_last, - input [0:0] io_inputs_0_payload_fragment_source, - input [0:0] io_inputs_0_payload_fragment_opcode, - input [31:0] io_inputs_0_payload_fragment_address, - input [5:0] io_inputs_0_payload_fragment_length, - input [31:0] io_inputs_0_payload_fragment_data, - input [3:0] io_inputs_0_payload_fragment_mask, - input [0:0] io_inputs_0_payload_fragment_context, - input io_inputs_1_valid, - output io_inputs_1_ready, - input io_inputs_1_payload_last, - input [0:0] io_inputs_1_payload_fragment_source, - input [0:0] io_inputs_1_payload_fragment_opcode, - input [31:0] io_inputs_1_payload_fragment_address, - input [5:0] io_inputs_1_payload_fragment_length, - input [31:0] io_inputs_1_payload_fragment_data, - input [3:0] io_inputs_1_payload_fragment_mask, - input [0:0] io_inputs_1_payload_fragment_context, - output io_output_valid, - input io_output_ready, - output io_output_payload_last, - output [0:0] io_output_payload_fragment_source, - output [0:0] io_output_payload_fragment_opcode, - output [31:0] io_output_payload_fragment_address, - output [5:0] io_output_payload_fragment_length, - output [31:0] io_output_payload_fragment_data, - output [3:0] io_output_payload_fragment_mask, - output [0:0] io_output_payload_fragment_context, - output [0:0] io_chosen, - output [1:0] io_chosenOH, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l621; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l621 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); - assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l621) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_valid, - input io_input_payload_last, - input [0:0] io_input_payload_fragment, - output io_output_valid, - output io_output_payload_last, - output [0:0] io_output_payload_fragment, - input jtagCtrl_tck, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg inputArea_data_last; - reg [0:0] inputArea_data_fragment; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire outputArea_flow_payload_last; - wire [0:0] outputArea_flow_payload_fragment; - reg outputArea_flow_m2sPipe_valid; - reg outputArea_flow_m2sPipe_payload_last; - reg [0:0] outputArea_flow_m2sPipe_payload_fragment; - - BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - initial begin - `ifndef SYNTHESIS - inputArea_target = $urandom; - outputArea_hit = $urandom; - `endif - end - - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_last = inputArea_data_last; - assign outputArea_flow_payload_fragment = inputArea_data_fragment; - assign io_output_valid = outputArea_flow_m2sPipe_valid; - assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; - assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; - always @(posedge jtagCtrl_tck) begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - inputArea_data_last <= io_input_payload_last; - inputArea_data_fragment <= io_input_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - outputArea_hit <= outputArea_target; - if(outputArea_flow_valid) begin - outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; - outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - outputArea_flow_m2sPipe_valid <= 1'b0; - end else begin - outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; - end - end - - -endmodule - -module DataCache_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - output reg io_cpu_execute_haltIt, - input io_cpu_execute_args_wr, - input [1:0] io_cpu_execute_args_size, - input io_cpu_execute_args_totalyConsistent, - output io_cpu_execute_refilling, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - input [31:0] io_cpu_memory_mmuRsp_physicalAddress, - input io_cpu_memory_mmuRsp_isIoAccess, - input io_cpu_memory_mmuRsp_isPaging, - input io_cpu_memory_mmuRsp_allowRead, - input io_cpu_memory_mmuRsp_allowWrite, - input io_cpu_memory_mmuRsp_allowExecute, - input io_cpu_memory_mmuRsp_exception, - input io_cpu_memory_mmuRsp_refilling, - input io_cpu_memory_mmuRsp_bypassTranslation, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isFiring, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - input [31:0] io_cpu_writeBack_storeData, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output io_cpu_writeBack_keepMemRspData, - input io_cpu_writeBack_fence_SW, - input io_cpu_writeBack_fence_SR, - input io_cpu_writeBack_fence_SO, - input io_cpu_writeBack_fence_SI, - input io_cpu_writeBack_fence_PW, - input io_cpu_writeBack_fence_PR, - input io_cpu_writeBack_fence_PO, - input io_cpu_writeBack_fence_PI, - input [3:0] io_cpu_writeBack_fence_FM, - output io_cpu_writeBack_exclusiveOk, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output io_cpu_flush_ready, - input io_cpu_flush_payload_singleLine, - input [5:0] io_cpu_flush_payload_lineId, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output io_mem_cmd_payload_uncached, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_size, - output io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input io_mem_rsp_payload_last, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [21:0] _zz_ways_0_tags_port0; - reg [31:0] _zz_ways_0_data_port0; - wire [21:0] _zz_ways_0_tags_port; - wire [9:0] _zz_stage0_dataColisions; - wire [9:0] _zz__zz_stageA_dataColisions; - wire [0:0] _zz_when; - wire [3:0] _zz_loader_counter_valueNext; - wire [0:0] _zz_loader_counter_valueNext_1; - wire [1:0] _zz_loader_waysAllocator; - reg _zz_1; - reg _zz_2; - wire haltCpu; - reg tagsReadCmd_valid; - reg [5:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [5:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [5:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; - wire _zz_ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRsp; - wire when_DataCache_l642; - wire when_DataCache_l645; - wire when_DataCache_l664; - wire rspSync; - wire rspLast; - reg memCmdSent; - wire io_mem_cmd_fire; - wire when_DataCache_l686; - reg [3:0] _zz_stage0_mask; - wire [3:0] stage0_mask; - wire [0:0] stage0_dataColisions; - wire [0:0] stage0_wayInvalidate; - wire stage0_isAmo; - wire when_DataCache_l771; - reg stageA_request_wr; - reg [1:0] stageA_request_size; - reg stageA_request_totalyConsistent; - wire when_DataCache_l771_1; - reg [3:0] stageA_mask; - wire stageA_isAmo; - wire stageA_isLrsc; - wire [0:0] stageA_wayHits; - wire when_DataCache_l771_2; - reg [0:0] stageA_wayInvalidate; - wire when_DataCache_l771_3; - reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_stageA_dataColisions; - wire [0:0] stageA_dataColisions; - wire when_DataCache_l822; - reg stageB_request_wr; - reg [1:0] stageB_request_size; - reg stageB_request_totalyConsistent; - reg stageB_mmuRspFreeze; - wire when_DataCache_l824; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_isPaging; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_mmuRsp_bypassTranslation; - wire when_DataCache_l821; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - wire when_DataCache_l821_1; - reg [31:0] stageB_dataReadRsp_0; - wire when_DataCache_l820; - reg [0:0] stageB_wayInvalidate; - wire stageB_consistancyHazard; - wire when_DataCache_l820_1; - reg [0:0] stageB_dataColisions; - wire when_DataCache_l820_2; - reg stageB_unaligned; - wire when_DataCache_l820_3; - reg [0:0] stageB_waysHitsBeforeInvalidate; - wire [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - wire when_DataCache_l820_4; - reg [3:0] stageB_mask; - reg stageB_loaderValid; - wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_waitDone; - wire stageB_flusher_hold; - reg [6:0] stageB_flusher_counter; - wire when_DataCache_l850; - wire when_DataCache_l856; - reg stageB_flusher_start; - wire stageB_isAmo; - wire stageB_isAmoCached; - wire stageB_isExternalLsrc; - wire stageB_isExternalAmo; - wire [31:0] stageB_requestDataBypass; - reg stageB_cpuWriteToCache; - wire when_DataCache_l926; - wire stageB_badPermissions; - wire stageB_loadStoreFault; - wire stageB_bypassCache; - wire when_DataCache_l995; - wire when_DataCache_l1004; - wire when_DataCache_l1009; - wire when_DataCache_l1020; - wire when_DataCache_l1032; - wire when_DataCache_l991; - wire when_DataCache_l1066; - wire when_DataCache_l1075; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [3:0] loader_counter_valueNext; - reg [3:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - wire loader_kill; - reg loader_killReg; - wire when_DataCache_l1090; - wire loader_done; - wire when_DataCache_l1118; - reg loader_valid_regNext; - wire when_DataCache_l1122; - wire when_DataCache_l1125; - reg [21:0] ways_0_tags [0:63]; - reg [7:0] ways_0_data_symbol0 [0:1023]; - reg [7:0] ways_0_data_symbol1 [0:1023]; - reg [7:0] ways_0_data_symbol2 [0:1023]; - reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_ways_0_datasymbol_read; - reg [7:0] _zz_ways_0_datasymbol_read_1; - reg [7:0] _zz_ways_0_datasymbol_read_2; - reg [7:0] _zz_ways_0_datasymbol_read_3; - - assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_when = 1'b1; - assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; - assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; - assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_ways_0_tagsReadRsp_valid) begin - _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(*) begin - _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; - end - always @(posedge io_systemClk) begin - if(_zz_ways_0_dataReadRspMem) begin - _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(when_DataCache_l645) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(when_DataCache_l642) begin - _zz_2 = 1'b1; - end - end - - assign haltCpu = 1'b0; - assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; - assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; - assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; - assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; - assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; - assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); - assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); - always @(*) begin - tagsReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - tagsReadCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsReadCmd_payload = 6'bxxxxxx; - if(when_DataCache_l664) begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; - end - end - - always @(*) begin - dataReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - dataReadCmd_valid = 1'b1; - end - end - - always @(*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; - if(when_DataCache_l664) begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end - end - - always @(*) begin - tagsWriteCmd_valid = 1'b0; - if(when_DataCache_l850) begin - tagsWriteCmd_valid = 1'b1; - end - if(when_DataCache_l1066) begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsWriteCmd_payload_way = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_way = 1'b1; - end - if(loader_done) begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - tagsWriteCmd_payload_address = 6'bxxxxxx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; - end - if(loader_done) begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; - end - end - - always @(*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done) begin - tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; - if(loader_done) begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end - end - - always @(*) begin - dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache) begin - if(when_DataCache_l926) begin - dataWriteCmd_valid = 1'b1; - end - end - if(when_DataCache_l1066) begin - dataWriteCmd_valid = 1'b0; - end - if(when_DataCache_l1090) begin - dataWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_way = stageB_waysHits; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; - end - end - - always @(*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end - end - - always @(*) begin - dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_mask = 4'b0000; - if(_zz_when[0]) begin - dataWriteCmd_payload_mask[3 : 0] = stageB_mask; - end - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_mask = 4'b1111; - end - end - - assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - always @(*) begin - io_cpu_execute_haltIt = 1'b0; - if(when_DataCache_l850) begin - io_cpu_execute_haltIt = 1'b1; - end - end - - assign rspSync = 1'b1; - assign rspLast = 1'b1; - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); - always @(*) begin - _zz_stage0_mask = 4'bxxxx; - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_stage0_mask = 4'b0001; - end - 2'b01 : begin - _zz_stage0_mask = 4'b0011; - end - 2'b10 : begin - _zz_stage0_mask = 4'b1111; - end - default : begin - end - endcase - end - - assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stage0_wayInvalidate = 1'b0; - assign stage0_isAmo = 1'b0; - assign when_DataCache_l771 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_isAmo = 1'b0; - assign stageA_isLrsc = 1'b0; - assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); - assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); - assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_mmuRspFreeze = 1'b0; - if(when_DataCache_l1125) begin - stageB_mmuRspFreeze = 1'b1; - end - end - - assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); - assign stageB_consistancyHazard = 1'b0; - assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); - assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (|stageB_waysHits); - assign stageB_dataMux = stageB_dataReadRsp_0; - assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - if(io_mem_cmd_ready) begin - stageB_loaderValid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - stageB_loaderValid = 1'b0; - end - end - - assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @(*) begin - io_cpu_writeBack_haltIt = 1'b1; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - if(when_DataCache_l995) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1009) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - - assign stageB_flusher_hold = 1'b0; - assign when_DataCache_l850 = (! stageB_flusher_counter[6]); - assign when_DataCache_l856 = (! stageB_flusher_hold); - assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); - assign stageB_isAmo = 1'b0; - assign stageB_isAmoCached = 1'b0; - assign stageB_isExternalLsrc = 1'b0; - assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = io_cpu_writeBack_storeData; - always @(*) begin - stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - stageB_cpuWriteToCache = 1'b1; - end - end - end - end - end - - assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); - assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); - assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @(*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1020) begin - io_cpu_redo = 1'b1; - end - end - end - end - end - if(when_DataCache_l1075) begin - io_cpu_redo = 1'b1; - end - if(when_DataCache_l1122) begin - io_cpu_redo = 1'b1; - end - end - - always @(*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache) begin - io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); - end - end - - assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @(*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - io_mem_cmd_valid = (! memCmdSent); - end else begin - if(when_DataCache_l1004) begin - if(stageB_request_wr) begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if(when_DataCache_l1032) begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_mem_cmd_valid = 1'b0; - end - end - - always @(*) begin - io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_address[5 : 0] = 6'h0; - end - end - end - end - end - - assign io_mem_cmd_payload_last = 1'b1; - always @(*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; - always @(*) begin - io_mem_cmd_payload_size = {1'd0, stageB_request_size}; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_size = 3'b110; - end - end - end - end - end - - assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); - assign io_cpu_writeBack_keepMemRspData = 1'b0; - assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); - assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); - assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); - assign when_DataCache_l1032 = (! memCmdSent); - assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - always @(*) begin - if(stageB_bypassCache) begin - io_cpu_writeBack_data = stageB_ioMemRspMuxed; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); - always @(*) begin - loader_counter_willIncrement = 1'b0; - if(when_DataCache_l1090) begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @(*) begin - loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); - if(loader_counter_willClear) begin - loader_counter_valueNext = 4'b0000; - end - end - - assign loader_kill = 1'b0; - assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign loader_done = loader_counter_willOverflow; - assign when_DataCache_l1118 = (! loader_valid); - assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); - assign io_cpu_execute_refilling = loader_valid; - assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); - always @(posedge io_systemClk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if(when_DataCache_l771) begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_size <= io_cpu_execute_args_size; - stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; - end - if(when_DataCache_l771_1) begin - stageA_mask <= stage0_mask; - end - if(when_DataCache_l771_2) begin - stageA_wayInvalidate <= stage0_wayInvalidate; - end - if(when_DataCache_l771_3) begin - stage0_dataColisions_regNextWhen <= stage0_dataColisions; - end - if(when_DataCache_l822) begin - stageB_request_wr <= stageA_request_wr; - stageB_request_size <= stageA_request_size; - stageB_request_totalyConsistent <= stageA_request_totalyConsistent; - end - if(when_DataCache_l824) begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; - stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; - stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; - end - if(when_DataCache_l821) begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if(when_DataCache_l821_1) begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if(when_DataCache_l820) begin - stageB_wayInvalidate <= stageA_wayInvalidate; - end - if(when_DataCache_l820_1) begin - stageB_dataColisions <= stageA_dataColisions; - end - if(when_DataCache_l820_2) begin - stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); - end - if(when_DataCache_l820_3) begin - stageB_waysHitsBeforeInvalidate <= stageA_wayHits; - end - if(when_DataCache_l820_4) begin - stageB_mask <= stageA_mask; - end - loader_valid_regNext <= loader_valid; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - memCmdSent <= 1'b0; - stageB_flusher_waitDone <= 1'b0; - stageB_flusher_counter <= 7'h0; - stageB_flusher_start <= 1'b1; - loader_valid <= 1'b0; - loader_counter_value <= 4'b0000; - loader_waysAllocator <= 1'b1; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end else begin - if(io_mem_cmd_fire) begin - memCmdSent <= 1'b1; - end - if(when_DataCache_l686) begin - memCmdSent <= 1'b0; - end - if(io_cpu_flush_ready) begin - stageB_flusher_waitDone <= 1'b0; - end - if(when_DataCache_l850) begin - if(when_DataCache_l856) begin - stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter[6] <= 1'b1; - end - end - end - stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start) begin - stageB_flusher_waitDone <= 1'b1; - stageB_flusher_counter <= 7'h0; - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; - end - end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 - `else - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 - end - `endif - `endif - if(stageB_loaderValid) begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(loader_kill) begin - loader_killReg <= 1'b1; - end - if(when_DataCache_l1090) begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_done) begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end - if(when_DataCache_l1118) begin - loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; - end - end - end - - -endmodule - -module InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, - input io_cpu_fetch_mmuRsp_isIoAccess, - input io_cpu_fetch_mmuRsp_isPaging, - input io_cpu_fetch_mmuRsp_allowRead, - input io_cpu_fetch_mmuRsp_allowWrite, - input io_cpu_fetch_mmuRsp_allowExecute, - input io_cpu_fetch_mmuRsp_exception, - input io_cpu_fetch_mmuRsp_refilling, - input io_cpu_fetch_mmuRsp_bypassTranslation, - output [31:0] io_cpu_fetch_physicalAddress, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_banks_0_port1; - reg [21:0] _zz_ways_0_tags_port1; - wire [21:0] _zz_ways_0_tags_port; - reg _zz_1; - reg _zz_2; - reg lineLoader_fire; - reg lineLoader_valid; - (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; - wire when_InstructionCache_l338; - reg _zz_when_InstructionCache_l342; - wire when_InstructionCache_l342; - wire when_InstructionCache_l351; - reg lineLoader_cmdSent; - wire io_mem_cmd_fire; - wire when_Utils_l513; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; - wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire when_InstructionCache_l401; - wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; - wire _zz_fetchStage_read_banksValue_0_dataMem_1; - wire [31:0] fetchStage_read_banksValue_0_dataMem; - wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; - wire _zz_fetchStage_read_waysValues_0_tag_valid_1; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - wire when_InstructionCache_l435; - reg [31:0] io_cpu_fetch_data_regNextWhen; - wire when_InstructionCache_l459; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_isPaging; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_mmuRsp_bypassTranslation; - wire when_InstructionCache_l459_1; - reg decodeStage_hit_valid; - wire when_InstructionCache_l459_2; - reg decodeStage_hit_error; - reg [31:0] banks_0 [0:1023]; - reg [21:0] ways_0_tags [0:63]; - - assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_1) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin - _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin - _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid) begin - _zz_2 = 1'b1; - end - end - - always @(*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid) begin - if(when_InstructionCache_l401) begin - lineLoader_fire = 1'b1; - end - end - end - - always @(*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(when_InstructionCache_l338) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(when_InstructionCache_l342) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush) begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); - assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); - assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; - assign io_mem_cmd_payload_size = 3'b110; - assign when_Utils_l513 = (! lineLoader_valid); - always @(*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if(when_Utils_l513) begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end - end - - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; - assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); - assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; - assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; - assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; - assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); - assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; - assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; - assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; - assign fetchStage_hit_word = fetchStage_hit_data; - assign io_cpu_fetch_data = fetchStage_hit_word; - assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; - assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= 4'b0000; - end else begin - if(lineLoader_fire) begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire) begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid) begin - lineLoader_valid <= 1'b1; - end - if(io_flush) begin - lineLoader_flushPending <= 1'b1; - end - if(when_InstructionCache_l351) begin - lineLoader_flushPending <= 1'b0; - end - if(io_mem_cmd_fire) begin - lineLoader_cmdSent <= 1'b1; - end - if(lineLoader_fire) begin - lineLoader_cmdSent <= 1'b0; - end - if(io_mem_rsp_valid) begin - lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); - if(io_mem_rsp_payload_error) begin - lineLoader_hadError <= 1'b1; - end - end - end - end - - always @(posedge io_systemClk) begin - if(io_cpu_fill_valid) begin - lineLoader_address <= io_cpu_fill_payload; - end - if(when_InstructionCache_l338) begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); - end - _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; - if(when_InstructionCache_l351) begin - lineLoader_flushCounter <= 7'h0; - end - if(when_InstructionCache_l435) begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if(when_InstructionCache_l459) begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; - decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; - decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; - end - if(when_InstructionCache_l459_1) begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if(when_InstructionCache_l459_2) begin - decodeStage_hit_error <= fetchStage_hit_error; - end - end - - -endmodule - -module UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - input io_rxd, - output io_rts, - output reg io_error, - output io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlRxState_IDLE = 3'd0; - localparam UartCtrlRxState_START = 3'd1; - localparam UartCtrlRxState_DATA = 3'd2; - localparam UartCtrlRxState_PARITY = 3'd3; - localparam UartCtrlRxState_STOP = 3'd4; - - wire io_rxd_buffercc_io_dataOut; - wire _zz_sampler_value; - wire _zz_sampler_value_1; - wire _zz_sampler_value_2; - wire _zz_sampler_value_3; - wire _zz_sampler_value_4; - wire _zz_sampler_value_5; - wire _zz_sampler_value_6; - wire [2:0] _zz_when_UartCtrlRx_l139; - wire [0:0] _zz_when_UartCtrlRx_l139_1; - reg _zz_io_rts; - wire sampler_synchroniser; - wire sampler_samples_0; - reg sampler_samples_1; - reg sampler_samples_2; - reg sampler_samples_3; - reg sampler_samples_4; - reg sampler_value; - reg sampler_tick; - reg [2:0] bitTimer_counter; - reg bitTimer_tick; - wire when_UartCtrlRx_l43; - reg [2:0] bitCounter_value; - reg [6:0] break_counter; - wire break_valid; - wire when_UartCtrlRx_l69; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg [7:0] stateMachine_shifter; - reg stateMachine_validReg; - wire when_UartCtrlRx_l93; - wire when_UartCtrlRx_l103; - wire when_UartCtrlRx_l111; - wire when_UartCtrlRx_l113; - wire when_UartCtrlRx_l125; - wire when_UartCtrlRx_l136; - wire when_UartCtrlRx_l139; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; - assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); - assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); - assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); - assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); - assign _zz_sampler_value_6 = 1'b1; - assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); - assign _zz_sampler_value_2 = 1'b1; - BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b io_rxd_buffercc ( - .io_dataIn (io_rxd ), //i - .io_dataOut (io_rxd_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlRxState_START : stateMachine_state_string = "START "; - UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - io_error = 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - end - UartCtrlRxState_START : begin - end - UartCtrlRxState_DATA : begin - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(!when_UartCtrlRx_l125) begin - io_error = 1'b1; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - io_error = 1'b1; - end - end - end - endcase - end - - assign io_rts = _zz_io_rts; - assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; - assign sampler_samples_0 = sampler_synchroniser; - always @(*) begin - bitTimer_tick = 1'b0; - if(sampler_tick) begin - if(when_UartCtrlRx_l43) begin - bitTimer_tick = 1'b1; - end - end - end - - assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); - assign break_valid = (break_counter == 7'h68); - assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); - assign io_break = break_valid; - assign io_read_valid = stateMachine_validReg; - assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); - assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); - assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); - assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); - assign when_UartCtrlRx_l136 = (! sampler_value); - assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); - assign io_read_payload = stateMachine_shifter; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_rts <= 1'b0; - sampler_samples_1 <= 1'b1; - sampler_samples_2 <= 1'b1; - sampler_samples_3 <= 1'b1; - sampler_samples_4 <= 1'b1; - sampler_value <= 1'b1; - sampler_tick <= 1'b0; - break_counter <= 7'h0; - stateMachine_state <= UartCtrlRxState_IDLE; - stateMachine_validReg <= 1'b0; - end else begin - _zz_io_rts <= (! io_read_ready); - if(io_samplingTick) begin - sampler_samples_1 <= sampler_samples_0; - end - if(io_samplingTick) begin - sampler_samples_2 <= sampler_samples_1; - end - if(io_samplingTick) begin - sampler_samples_3 <= sampler_samples_2; - end - if(io_samplingTick) begin - sampler_samples_4 <= sampler_samples_3; - end - sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); - sampler_tick <= io_samplingTick; - if(sampler_value) begin - break_counter <= 7'h0; - end else begin - if(when_UartCtrlRx_l69) begin - break_counter <= (break_counter + 7'h01); - end - end - stateMachine_validReg <= 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - stateMachine_state <= UartCtrlRxState_START; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - stateMachine_state <= UartCtrlRxState_DATA; - if(when_UartCtrlRx_l103) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l111) begin - if(when_UartCtrlRx_l113) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_PARITY; - end - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l125) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end else begin - if(when_UartCtrlRx_l139) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(sampler_tick) begin - bitTimer_counter <= (bitTimer_counter - 3'b001); - end - if(bitTimer_tick) begin - bitCounter_value <= (bitCounter_value + 3'b001); - end - if(bitTimer_tick) begin - stateMachine_parity <= (stateMachine_parity ^ sampler_value); - end - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - bitTimer_counter <= 3'b010; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - stateMachine_shifter[bitCounter_value] <= sampler_value; - if(when_UartCtrlRx_l111) begin - bitCounter_value <= 3'b000; - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - input io_cts, - output io_txd, - input io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlTxState_IDLE = 3'd0; - localparam UartCtrlTxState_START = 3'd1; - localparam UartCtrlTxState_DATA = 3'd2; - localparam UartCtrlTxState_PARITY = 3'd3; - localparam UartCtrlTxState_STOP = 3'd4; - - wire [2:0] _zz_clockDivider_counter_valueNext; - wire [0:0] _zz_clockDivider_counter_valueNext_1; - wire [2:0] _zz_when_UartCtrlTx_l93; - wire [0:0] _zz_when_UartCtrlTx_l93_1; - reg clockDivider_counter_willIncrement; - wire clockDivider_counter_willClear; - reg [2:0] clockDivider_counter_valueNext; - reg [2:0] clockDivider_counter_value; - wire clockDivider_counter_willOverflowIfInc; - wire clockDivider_counter_willOverflow; - reg [2:0] tickCounter_value; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg stateMachine_txd; - wire when_UartCtrlTx_l58; - wire when_UartCtrlTx_l73; - wire when_UartCtrlTx_l76; - wire when_UartCtrlTx_l93; - reg _zz_io_txd; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; - assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; - assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlTxState_START : stateMachine_state_string = "START "; - UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - clockDivider_counter_willIncrement = 1'b0; - if(io_samplingTick) begin - clockDivider_counter_willIncrement = 1'b1; - end - end - - assign clockDivider_counter_willClear = 1'b0; - assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); - assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); - always @(*) begin - clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); - if(clockDivider_counter_willClear) begin - clockDivider_counter_valueNext = 3'b000; - end - end - - always @(*) begin - stateMachine_txd = 1'b1; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - stateMachine_txd = 1'b0; - end - UartCtrlTxState_DATA : begin - stateMachine_txd = io_write_payload[tickCounter_value]; - end - UartCtrlTxState_PARITY : begin - stateMachine_txd = stateMachine_parity; - end - default : begin - end - endcase - end - - always @(*) begin - io_write_ready = io_break; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - io_write_ready = 1'b1; - end - end - end - UartCtrlTxState_PARITY : begin - end - default : begin - end - endcase - end - - assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); - assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); - assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); - assign io_txd = _zz_io_txd; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter_value <= 3'b000; - stateMachine_state <= UartCtrlTxState_IDLE; - _zz_io_txd <= 1'b1; - end else begin - clockDivider_counter_value <= clockDivider_counter_valueNext; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - if(when_UartCtrlTx_l58) begin - stateMachine_state <= UartCtrlTxState_START; - end - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_DATA; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - if(when_UartCtrlTx_l76) begin - stateMachine_state <= UartCtrlTxState_STOP; - end else begin - stateMachine_state <= UartCtrlTxState_PARITY; - end - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_STOP; - end - end - default : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l93) begin - stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); - end - end - end - endcase - _zz_io_txd <= (stateMachine_txd && (! io_break)); - end - end - - always @(posedge io_systemClk) begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= (tickCounter_value + 3'b001); - end - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); - end - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - tickCounter_value <= 3'b000; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - tickCounter_value <= 3'b000; - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - initial begin - `ifndef SYNTHESIS - buffers_0 = $urandom; - buffers_1 = $urandom; - `endif - end - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - - -endmodule - -module BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input systemCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_define.vh b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_define.vh deleted file mode 100644 index c60c9f4..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_define.vh +++ /dev/null @@ -1,45 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2022.1.196 -// IP Version: 2.2 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.v b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.v deleted file mode 100644 index 4b3fc22..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.v +++ /dev/null @@ -1,76 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -sapphire u_sapphire( -.io_systemClk ( io_systemClk ), -.jtagCtrl_enable ( jtagCtrl_enable ), -.jtagCtrl_tdi ( jtagCtrl_tdi ), -.jtagCtrl_capture ( jtagCtrl_capture ), -.jtagCtrl_shift ( jtagCtrl_shift ), -.jtagCtrl_update ( jtagCtrl_update ), -.jtagCtrl_reset ( jtagCtrl_reset ), -.jtagCtrl_tdo ( jtagCtrl_tdo ), -.jtagCtrl_tck ( jtagCtrl_tck ), -.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), -.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), -.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), -.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), -.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), -.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), -.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), -.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), -.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), -.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), -.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), -.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), -.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), -.system_spi_0_io_ss ( system_spi_0_io_ss ), -.io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), -.io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), -.io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), -.io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), -.io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), -.io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), -.io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), -.io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), -.io_asyncReset ( io_asyncReset ), -.io_systemReset ( io_systemReset ), -.system_uart_0_io_txd ( system_uart_0_io_txd ), -.system_uart_0_io_rxd ( system_uart_0_io_rxd ) -); diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd deleted file mode 100644 index a8c601e..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd +++ /dev/null @@ -1,118 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// -------------- Begin Cut here for COMPONENT Declaration ------ -COMPONENT sapphire is -PORT ( -io_systemClk : in std_logic; -jtagCtrl_enable : in std_logic; -jtagCtrl_tdi : in std_logic; -jtagCtrl_capture : in std_logic; -jtagCtrl_shift : in std_logic; -jtagCtrl_update : in std_logic; -jtagCtrl_reset : in std_logic; -jtagCtrl_tdo : out std_logic; -jtagCtrl_tck : in std_logic; -system_spi_0_io_data_0_read : in std_logic; -system_spi_0_io_data_0_write : out std_logic; -system_spi_0_io_data_0_writeEnable : out std_logic; -system_spi_0_io_data_1_read : in std_logic; -system_spi_0_io_data_1_write : out std_logic; -system_spi_0_io_data_1_writeEnable : out std_logic; -system_spi_0_io_data_2_read : in std_logic; -system_spi_0_io_data_2_write : out std_logic; -system_spi_0_io_data_2_writeEnable : out std_logic; -system_spi_0_io_data_3_read : in std_logic; -system_spi_0_io_data_3_write : out std_logic; -system_spi_0_io_data_3_writeEnable : out std_logic; -system_spi_0_io_sclk_write : out std_logic; -system_spi_0_io_ss : out std_logic_vector(0 to 0); -io_apbSlave_0_PADDR : out std_logic_vector(15 downto 0); -io_apbSlave_0_PENABLE : out std_logic; -io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0); -io_apbSlave_0_PREADY : in std_logic; -io_apbSlave_0_PSEL : out std_logic; -io_apbSlave_0_PSLVERROR : in std_logic; -io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0); -io_apbSlave_0_PWRITE : out std_logic; -io_asyncReset : in std_logic; -io_systemReset : out std_logic; -system_uart_0_io_txd : out std_logic; -system_uart_0_io_rxd : in std_logic); -END COMPONENT; ----------------------- End COMPONENT Declaration ------------ - -------------- Begin Cut here for INSTANTIATION Template ----- -u_sapphire : sapphire -PORT MAP ( -io_systemClk => io_systemClk, -jtagCtrl_enable => jtagCtrl_enable, -jtagCtrl_tdi => jtagCtrl_tdi, -jtagCtrl_capture => jtagCtrl_capture, -jtagCtrl_shift => jtagCtrl_shift, -jtagCtrl_update => jtagCtrl_update, -jtagCtrl_reset => jtagCtrl_reset, -jtagCtrl_tdo => jtagCtrl_tdo, -jtagCtrl_tck => jtagCtrl_tck, -system_spi_0_io_data_0_read => system_spi_0_io_data_0_read, -system_spi_0_io_data_0_write => system_spi_0_io_data_0_write, -system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable, -system_spi_0_io_data_1_read => system_spi_0_io_data_1_read, -system_spi_0_io_data_1_write => system_spi_0_io_data_1_write, -system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable, -system_spi_0_io_data_2_read => system_spi_0_io_data_2_read, -system_spi_0_io_data_2_write => system_spi_0_io_data_2_write, -system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable, -system_spi_0_io_data_3_read => system_spi_0_io_data_3_read, -system_spi_0_io_data_3_write => system_spi_0_io_data_3_write, -system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable, -system_spi_0_io_sclk_write => system_spi_0_io_sclk_write, -system_spi_0_io_ss => system_spi_0_io_ss, -io_apbSlave_0_PADDR => io_apbSlave_0_PADDR, -io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE, -io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA, -io_apbSlave_0_PREADY => io_apbSlave_0_PREADY, -io_apbSlave_0_PSEL => io_apbSlave_0_PSEL, -io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR, -io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA, -io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE, -io_asyncReset => io_asyncReset, -io_systemReset => io_systemReset, -system_uart_0_io_txd => system_uart_0_io_txd, -system_uart_0_io_rxd => system_uart_0_io_rxd); ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/settings.json b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/settings.json deleted file mode 100644 index 594e31f..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/settings.json +++ /dev/null @@ -1,156 +0,0 @@ -{ - "args": [ - "-o", - "sapphire", - "--base_path", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip", - "--vlnv", - { - "vendor": "efinixinc.com", - "library": "soc", - "name": "efx_soc", - "version": "2.2" - } - ], - "conf": { - "HexFile_PathEnable": "0", - "HexFile_Path": "", - "APBSlave0_Size": "65536", - "DEVKIT_CUSTOM": "sapphireBoard_rev0", - "LDSize": "124", - "LDStackSize": "4", - "DEVKIT": "2", - "DEBUG": "1", - "SOFT_TAP": "0", - "TAP_COUNT": "0", - "TAP_SEL": "8", - "Frequency": "50", - "PeriFrequencyEnable": "0", - "PeriFrequency": "50", - "UART2_INT_ID": "3", - "TEST": "0", - "Base_M_AXIS": "3774873600", - "APBSlave0": "1", - "APBSlave2": "0", - "Base_M_IO": "4160749568", - "APBSlave1": "0", - "APBSlave3": "0", - "USER_1_INTR_ID": "17", - "USER_1_INTR": "0", - "USER_0_INTR_ID": "16", - "USER_0_INTR": "0", - "USER_2_INTR": "0", - "USER_2_INTR_ID": "22", - "USER_3_INTR": "0", - "USER_3_INTR_ID": "23", - "USER_4_INTR": "0", - "USER_4_INTR_ID": "24", - "USER_5_INTR": "0", - "USER_5_INTR_ID": "25", - "USER_6_INTR": "0", - "USER_6_INTR_ID": "26", - "USER_7_INTR": "0", - "USER_7_INTR_ID": "27", - "APBSlave4": "0", - "CustomInstruction": "0", - "ATMEXT": "0", - "CMREXT": "0", - "FPEXT": "1", - "FPU": "0", - "LINUX": "0", - "ICACHEWAY": "1", - "DCACHEWAY": "1", - "CpuCount": "1", - "ICacheSize": "4096", - "DCacheSize": "4096", - "Cache": "1", - "DDR": "0", - "DDR_AXI4": "0", - "DDRWidth": "128", - "DDRSize": "3758096384", - "OCRSize": "32768", - "AXISlave": "0", - "AXISlaveSize": "16777216", - "GPIO1_INT_ID1": "15", - "GPIO1_INT_ID0": "14", - "GPIO0_INT_ID1": "13", - "GPIO0_INT_ID0": "12", - "GPIO0": "0", - "GPIO0Width": "4", - "GPIO1Width": "8", - "GPIO1": "0", - "UART0_INT_ID": "1", - "IOSize": "4096", - "UART0_M_Addr": "4096", - "UART1_M_Addr": "8192", - "UART2_M_Addr": "12288", - "SPI0_M_Addr": "24576", - "SPI1_M_Addr": "16384", - "SPI2_M_Addr": "20480", - "I2C0_M_Addr": "40960", - "I2C1_M_Addr": "45056", - "I2C2_M_Addr": "49152", - "GPIO0_M_Addr": "53248", - "GPIO1_M_Addr": "57344", - "APBSlave0_M_Addr": "1048576", - "APBSlave1_M_Addr": "2097152", - "APBSlave2_M_Addr": "3145728", - "APBSlave3_M_Addr": "4194304", - "APBSlave4_M_Addr": "5242880", - "UART0": "1", - "UART2": "0", - "UART1_INT_ID": "2", - "UART1": "0", - "SPI2": "0", - "SPI2DW": "8", - "SPI2SS": "1", - "SPI1_INT_ID": "5", - "SPI1": "0", - "SPI1DW": "8", - "SPI1SS": "1", - "SPI0_INT_ID": "4", - "SPI0": "1", - "SPI0DW": "8", - "SPI0SS": "1", - "I2C2_INT_ID": "10", - "ADDR_Scheme": "0", - "I2C2": "0", - "I2C1": "0", - "SPI2_INT_ID": "6", - "I2C1_INT_ID": "9", - "I2C0_INT_ID": "8", - "I2C0": "0", - "AXIMasterWidth_1": "32", - "AXIMaster_1": "0", - "AXIMasterWidth": "32", - "AXIMaster": "1", - "USER_TIMER0": "0", - "USER_TIMER0_CNT_WIDTH": "12", - "USER_TIMER0_PS_WIDTH": "8", - "USER_TIMER0_INT_ID": "19", - "USER_TIMER0_M_Addr": "61440", - "USER_TIMER1": "0", - "USER_TIMER1_CNT_WIDTH": "12", - "USER_TIMER1_PS_WIDTH": "8", - "USER_TIMER1_INT_ID": "20", - "USER_TIMER1_M_Addr": "65536", - "USER_TIMER2": "0", - "USER_TIMER2_CNT_WIDTH": "12", - "USER_TIMER2_PS_WIDTH": "8", - "USER_TIMER2_INT_ID": "21", - "USER_TIMER2_M_Addr": "69632" - }, - "output": { - "external_generator": [], - "external_source": [ - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.v", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire.v", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_define.vh", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd" - ], - "external_script": [], - "external_embedded_sw": [] - }, - "sw_version": "2022.1.196", - "generated_date": "2022-08-08T02:57:54.948573" -} \ No newline at end of file diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v deleted file mode 100644 index d8f0f2f..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v +++ /dev/null @@ -1,14093 +0,0 @@ -// Generator : SpinalHDL v1.7.1-SNAPSHOT git head : 2aaf6e4d1af9719ce8d12a973793990e489d8055 -// Component : EfxSapphireSoc - -`timescale 1ns/1ps - -module EfxSapphireSoc ( - input io_systemClk, - input io_asyncReset, - input jtagCtrl_tck, - output reg io_systemReset, - input jtagCtrl_tdi, - input jtagCtrl_enable, - input jtagCtrl_capture, - input jtagCtrl_shift, - input jtagCtrl_update, - input jtagCtrl_reset, - output jtagCtrl_tdo, - output system_uart_0_io_txd, - input system_uart_0_io_rxd, - output [15:0] io_apbSlave_0_PADDR, - output [0:0] io_apbSlave_0_PSEL, - output io_apbSlave_0_PENABLE, - input io_apbSlave_0_PREADY, - output io_apbSlave_0_PWRITE, - output [31:0] io_apbSlave_0_PWDATA, - input [31:0] io_apbSlave_0_PRDATA, - input io_apbSlave_0_PSLVERROR, - output [0:0] system_spi_0_io_sclk_write, - output system_spi_0_io_data_0_writeEnable, - input [0:0] system_spi_0_io_data_0_read, - output [0:0] system_spi_0_io_data_0_write, - output system_spi_0_io_data_1_writeEnable, - input [0:0] system_spi_0_io_data_1_read, - output [0:0] system_spi_0_io_data_1_write, - output system_spi_0_io_data_2_writeEnable, - input [0:0] system_spi_0_io_data_2_read, - output [0:0] system_spi_0_io_data_2_write, - output system_spi_0_io_data_3_writeEnable, - input [0:0] system_spi_0_io_data_3_read, - output [0:0] system_spi_0_io_data_3_write, - output [0:0] system_spi_0_io_ss -); - - reg system_cores_0_logic_cpu_dBus_rsp_valid; - wire system_cores_0_logic_cpu_dBus_rsp_payload_error; - wire system_cores_0_logic_cpu_debug_bus_cmd_payload_wr; - wire system_cores_0_logic_cpu_iBus_rsp_payload_error; - wire bufferCC_5_io_dataOut; - wire bufferCC_6_io_dataOut; - wire system_cores_0_logic_cpu_dBus_cmd_valid; - wire system_cores_0_logic_cpu_dBus_cmd_payload_wr; - wire system_cores_0_logic_cpu_dBus_cmd_payload_uncached; - wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_address; - wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_data; - wire [3:0] system_cores_0_logic_cpu_dBus_cmd_payload_mask; - wire [2:0] system_cores_0_logic_cpu_dBus_cmd_payload_size; - wire system_cores_0_logic_cpu_dBus_cmd_payload_last; - wire system_cores_0_logic_cpu_debug_bus_cmd_ready; - wire [31:0] system_cores_0_logic_cpu_debug_bus_rsp_data; - wire system_cores_0_logic_cpu_debug_resetOut; - wire system_cores_0_logic_cpu_iBus_cmd_valid; - wire [31:0] system_cores_0_logic_cpu_iBus_cmd_payload_address; - wire [2:0] system_cores_0_logic_cpu_iBus_cmd_payload_size; - wire system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; - wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid; - wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last; - wire [0:0] system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment; - wire system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready; - wire system_hardJtag_debug_logic_debugger_io_remote_cmd_ready; - wire system_hardJtag_debug_logic_debugger_io_remote_rsp_valid; - wire system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error; - wire [31:0] system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data; - wire system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; - wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address; - wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; - wire system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr; - wire [1:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size; - wire bufferCC_7_io_dataOut; - wire bmbDecoder_4_io_input_cmd_ready; - wire bmbDecoder_4_io_input_rsp_valid; - wire bmbDecoder_4_io_input_rsp_payload_last; - wire [0:0] bmbDecoder_4_io_input_rsp_payload_fragment_opcode; - wire [31:0] bmbDecoder_4_io_input_rsp_payload_fragment_data; - wire bmbDecoder_4_io_outputs_0_cmd_valid; - wire bmbDecoder_4_io_outputs_0_cmd_payload_last; - wire [0:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; - wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address; - wire [1:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; - wire bmbDecoder_4_io_outputs_0_rsp_ready; - wire system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; - wire system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; - wire system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; - wire system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; - wire system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; - wire system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; - wire system_fabric_iBus_bmb_decoder_io_input_cmd_ready; - wire system_fabric_iBus_bmb_decoder_io_input_rsp_valid; - wire system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; - wire [0:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; - wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid; - wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - wire system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready; - wire system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; - wire system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; - wire system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; - wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; - wire system_bridge_bmb_arbiter_io_inputs_1_cmd_ready; - wire system_bridge_bmb_arbiter_io_inputs_1_rsp_valid; - wire system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last; - wire [0:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data; - wire system_bridge_bmb_arbiter_io_output_cmd_valid; - wire system_bridge_bmb_arbiter_io_output_cmd_payload_last; - wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; - wire system_bridge_bmb_arbiter_io_output_rsp_ready; - wire system_bridge_bmb_decoder_io_input_cmd_ready; - wire system_bridge_bmb_decoder_io_input_rsp_valid; - wire system_bridge_bmb_decoder_io_input_rsp_payload_last; - wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; - wire system_bridge_bmb_decoder_io_outputs_0_cmd_valid; - wire system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - wire system_bridge_bmb_decoder_io_outputs_0_rsp_ready; - wire system_bridge_bmb_decoder_io_outputs_1_cmd_valid; - wire system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last; - wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - wire system_bridge_bmb_decoder_io_outputs_1_rsp_ready; - wire system_ramA_logic_io_bus_cmd_ready; - wire system_ramA_logic_io_bus_rsp_valid; - wire system_ramA_logic_io_bus_rsp_payload_last; - wire [0:0] system_ramA_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_ramA_logic_io_bus_rsp_payload_fragment_data; - wire [3:0] system_ramA_logic_io_bus_rsp_payload_fragment_context; - wire system_bridge_bmb_unburstify_io_input_cmd_ready; - wire system_bridge_bmb_unburstify_io_input_rsp_valid; - wire system_bridge_bmb_unburstify_io_input_rsp_payload_last; - wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context; - wire system_bridge_bmb_unburstify_io_output_cmd_valid; - wire system_bridge_bmb_unburstify_io_output_cmd_payload_last; - wire [0:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address; - wire [1:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; - wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; - wire system_bridge_bmb_unburstify_io_output_rsp_ready; - wire system_bridge_bmb_unburstify_1_io_input_cmd_ready; - wire system_bridge_bmb_unburstify_1_io_input_rsp_valid; - wire system_bridge_bmb_unburstify_1_io_input_rsp_payload_last; - wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context; - wire system_bridge_bmb_unburstify_1_io_output_cmd_valid; - wire system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; - wire [0:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address; - wire [1:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; - wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; - wire system_bridge_bmb_unburstify_1_io_output_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; - wire system_bmbPeripheral_bmb_decoder_io_input_rsp_valid; - wire system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - wire system_clint_logic_io_bus_cmd_ready; - wire system_clint_logic_io_bus_rsp_valid; - wire system_clint_logic_io_bus_rsp_payload_last; - wire [0:0] system_clint_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_clint_logic_io_bus_rsp_payload_fragment_data; - wire [3:0] system_clint_logic_io_bus_rsp_payload_fragment_context; - wire [0:0] system_clint_logic_io_timerInterrupt; - wire [0:0] system_clint_logic_io_softwareInterrupt; - wire [63:0] system_clint_logic_io_time; - wire system_uart_0_io_logic_io_bus_cmd_ready; - wire system_uart_0_io_logic_io_bus_rsp_valid; - wire system_uart_0_io_logic_io_bus_rsp_payload_last; - wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - wire [3:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - wire system_uart_0_io_logic_io_uart_txd; - wire system_uart_0_io_logic_io_interrupt; - wire system_spi_0_io_logic_io_ctrl_cmd_ready; - wire system_spi_0_io_logic_io_ctrl_rsp_valid; - wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; - wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - wire [3:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; - wire [0:0] system_spi_0_io_logic_io_spi_ss; - wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; - wire system_spi_0_io_logic_io_spi_data_0_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; - wire system_spi_0_io_logic_io_spi_data_1_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; - wire system_spi_0_io_logic_io_spi_data_2_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; - wire system_spi_0_io_logic_io_spi_data_3_writeEnable; - wire system_spi_0_io_logic_io_interrupt; - wire io_apbSlave_0_logic_io_input_cmd_ready; - wire io_apbSlave_0_logic_io_input_rsp_valid; - wire io_apbSlave_0_logic_io_input_rsp_payload_last; - wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - wire [3:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - wire [15:0] io_apbSlave_0_logic_io_output_PADDR; - wire [0:0] io_apbSlave_0_logic_io_output_PSEL; - wire io_apbSlave_0_logic_io_output_PENABLE; - wire io_apbSlave_0_logic_io_output_PWRITE; - wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; - wire [29:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - wire [6:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1; - reg debugCd_logic_inputResetTrigger; - reg debugCd_logic_outputResetUnbuffered; - reg [11:0] debugCd_logic_holdingLogic_resetCounter; - wire when_ClockDomainGenerator_l77; - reg debugCd_logic_outputReset; - wire debugCd_logic_inputResetAdapter_stuff_syncTrigger; - reg systemCd_logic_inputResetTrigger; - reg systemCd_logic_outputResetUnbuffered; - reg [5:0] systemCd_logic_holdingLogic_resetCounter; - wire when_ClockDomainGenerator_l77_1; - reg systemCd_logic_outputReset; - wire system_cores_0_iBus_cmd_valid; - wire system_cores_0_iBus_cmd_ready; - wire system_cores_0_iBus_cmd_payload_last; - wire [0:0] system_cores_0_iBus_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_cmd_payload_fragment_address; - wire [5:0] system_cores_0_iBus_cmd_payload_fragment_length; - wire system_cores_0_iBus_rsp_valid; - wire system_cores_0_iBus_rsp_ready; - wire system_cores_0_iBus_rsp_payload_last; - wire [0:0] system_cores_0_iBus_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_rsp_payload_fragment_data; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; - reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; - wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; - wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context; - wire system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; - reg [5:0] _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - wire when_DataCache_l532; - reg system_cores_0_debugReset; - wire system_cores_0_iBus_connector_decoder_cmd_valid; - wire system_cores_0_iBus_connector_decoder_cmd_ready; - wire system_cores_0_iBus_connector_decoder_cmd_payload_last; - wire [0:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; - wire system_cores_0_iBus_connector_decoder_rsp_valid; - wire system_cores_0_iBus_connector_decoder_rsp_ready; - wire system_cores_0_iBus_connector_decoder_rsp_payload_last; - wire [0:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; - reg _zz_system_cores_0_iBus_connector_decoder_rsp_ready; - wire system_cores_0_iBus_cmd_combStage_valid; - wire system_cores_0_iBus_cmd_combStage_ready; - wire system_cores_0_iBus_cmd_combStage_payload_last; - wire [0:0] system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_cmd_combStage_payload_fragment_address; - wire [5:0] system_cores_0_iBus_cmd_combStage_payload_fragment_length; - wire _zz_system_cores_0_iBus_rsp_valid; - reg _zz_system_cores_0_iBus_rsp_valid_1; - reg _zz_system_cores_0_iBus_rsp_payload_last; - reg [0:0] _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_cores_0_iBus_rsp_payload_fragment_data; - wire when_Stream_l368; - wire system_cores_0_dBus_connector_decoder_cmd_valid; - wire system_cores_0_dBus_connector_decoder_cmd_ready; - wire system_cores_0_dBus_connector_decoder_cmd_payload_last; - wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; - wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; - wire system_cores_0_dBus_connector_decoder_rsp_valid; - wire system_cores_0_dBus_connector_decoder_rsp_ready; - wire system_cores_0_dBus_connector_decoder_rsp_payload_last; - wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; - wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; - wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; - wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; - reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; - reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; - reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; - reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; - reg [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; - reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; - reg [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; - reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; - wire when_Stream_l368_1; - wire system_hardJtag_debug_logic_mmMaster_cmd_valid; - wire system_hardJtag_debug_logic_mmMaster_cmd_ready; - wire system_hardJtag_debug_logic_mmMaster_cmd_payload_last; - wire [0:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - wire [1:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; - wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; - wire [3:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - wire system_hardJtag_debug_logic_mmMaster_rsp_valid; - wire system_hardJtag_debug_logic_mmMaster_rsp_ready; - wire system_hardJtag_debug_logic_mmMaster_rsp_payload_last; - wire [0:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data; - reg [3:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - wire system_hardJtag_debug_bmb_connector_decoder_cmd_valid; - wire system_hardJtag_debug_bmb_connector_decoder_cmd_ready; - wire system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last; - wire [0:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address; - wire [1:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask; - wire system_hardJtag_debug_bmb_connector_decoder_rsp_valid; - wire system_hardJtag_debug_bmb_connector_decoder_rsp_ready; - wire system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; - wire [0:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; - wire system_fabric_iBus_bmb_cmd_valid; - reg system_fabric_iBus_bmb_cmd_ready; - wire system_fabric_iBus_bmb_cmd_payload_last; - wire [0:0] system_fabric_iBus_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_cmd_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_cmd_payload_fragment_length; - wire system_fabric_iBus_bmb_rsp_valid; - wire system_fabric_iBus_bmb_rsp_ready; - wire system_fabric_iBus_bmb_rsp_payload_last; - wire [0:0] system_fabric_iBus_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_rsp_payload_fragment_data; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire system_cores_0_debugBmb_cmd_valid; - wire system_cores_0_debugBmb_cmd_ready; - wire system_cores_0_debugBmb_cmd_payload_last; - wire [0:0] system_cores_0_debugBmb_cmd_payload_fragment_opcode; - wire [7:0] system_cores_0_debugBmb_cmd_payload_fragment_address; - wire [1:0] system_cores_0_debugBmb_cmd_payload_fragment_length; - wire [31:0] system_cores_0_debugBmb_cmd_payload_fragment_data; - wire [3:0] system_cores_0_debugBmb_cmd_payload_fragment_mask; - wire system_cores_0_debugBmb_rsp_valid; - wire system_cores_0_debugBmb_rsp_ready; - wire system_cores_0_debugBmb_rsp_payload_last; - wire [0:0] system_cores_0_debugBmb_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_debugBmb_rsp_payload_fragment_data; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - reg _zz_io_input_rsp_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; - reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; - reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; - wire when_Stream_l368_2; - wire _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire when_Stream_l368_3; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [7:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire system_cores_0_logic_cpu_debug_bus_cmd_fire; - reg system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; - wire system_fabric_dBusCoherent_bmb_cmd_valid; - wire system_fabric_dBusCoherent_bmb_cmd_ready; - wire system_fabric_dBusCoherent_bmb_cmd_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_rsp_valid; - wire system_fabric_dBusCoherent_bmb_rsp_ready; - wire system_fabric_dBusCoherent_bmb_rsp_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; - wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; - wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; - wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; - wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; - wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; - wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready; - wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; - wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid; - wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; - wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context; - wire system_fabric_dBus_bmb_cmd_valid; - wire system_fabric_dBus_bmb_cmd_ready; - wire system_fabric_dBus_bmb_cmd_payload_last; - wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBus_bmb_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBus_bmb_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_context; - wire system_fabric_dBus_bmb_rsp_valid; - wire system_fabric_dBus_bmb_rsp_ready; - wire system_fabric_dBus_bmb_rsp_payload_last; - wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_context; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_fabric_iBus_bmb_cmd_m2sPipe_valid; - wire system_fabric_iBus_bmb_cmd_m2sPipe_ready; - wire system_fabric_iBus_bmb_cmd_m2sPipe_payload_last; - wire [0:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length; - reg system_fabric_iBus_bmb_cmd_rValid; - reg system_fabric_iBus_bmb_cmd_rData_last; - reg [0:0] system_fabric_iBus_bmb_cmd_rData_fragment_opcode; - reg [31:0] system_fabric_iBus_bmb_cmd_rData_fragment_address; - reg [5:0] system_fabric_iBus_bmb_cmd_rData_fragment_length; - wire when_Stream_l368_4; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - wire system_bridge_bmb_cmd_valid; - wire system_bridge_bmb_cmd_ready; - wire system_bridge_bmb_cmd_payload_last; - wire [0:0] system_bridge_bmb_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_cmd_payload_fragment_context; - wire system_bridge_bmb_rsp_valid; - wire system_bridge_bmb_rsp_ready; - wire system_bridge_bmb_rsp_payload_last; - wire [0:0] system_bridge_bmb_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_rsp_payload_fragment_context; - wire system_bridge_bmb_cmd_s2mPipe_valid; - reg system_bridge_bmb_cmd_s2mPipe_ready; - wire system_bridge_bmb_cmd_s2mPipe_payload_last; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; - wire [5:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; - wire [3:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; - reg system_bridge_bmb_cmd_rValid; - reg system_bridge_bmb_cmd_rData_last; - reg [0:0] system_bridge_bmb_cmd_rData_fragment_source; - reg [0:0] system_bridge_bmb_cmd_rData_fragment_opcode; - reg [31:0] system_bridge_bmb_cmd_rData_fragment_address; - reg [5:0] system_bridge_bmb_cmd_rData_fragment_length; - reg [31:0] system_bridge_bmb_cmd_rData_fragment_data; - reg [3:0] system_bridge_bmb_cmd_rData_fragment_mask; - reg [0:0] system_bridge_bmb_cmd_rData_fragment_context; - wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid; - wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; - wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address; - wire [5:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data; - wire [3:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context; - reg system_bridge_bmb_cmd_s2mPipe_rValid; - reg system_bridge_bmb_cmd_s2mPipe_rData_last; - reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; - reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; - reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; - reg [5:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; - reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; - reg [3:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; - reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; - wire when_Stream_l368_5; - wire system_bmbPeripheral_bmb_cmd_valid; - wire system_bmbPeripheral_bmb_cmd_ready; - wire system_bmbPeripheral_bmb_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_rsp_valid; - wire system_bmbPeripheral_bmb_rsp_ready; - wire system_bmbPeripheral_bmb_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - reg _zz_io_bus_rsp_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last; - wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode; - wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address; - wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length; - wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context; - wire _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - reg [0:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - reg [3:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire when_Stream_l368_6; - wire _zz_io_input_rsp_ready_1; - wire system_bmbPeripheral_bmb_cmd_combStage_valid; - wire system_bmbPeripheral_bmb_cmd_combStage_ready; - wire system_bmbPeripheral_bmb_cmd_combStage_payload_last; - wire [0:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context; - wire _zz_system_bmbPeripheral_bmb_rsp_valid; - reg _zz_system_bmbPeripheral_bmb_rsp_valid_1; - reg _zz_system_bmbPeripheral_bmb_rsp_payload_last; - reg [0:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; - reg [3:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [15:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - reg _zz_timerInterrupt; - reg _zz_softwareInterrupt; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_ready_1; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; - wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; - wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; - wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; - reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; - reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - reg [3:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire [1:0] system_uart_0_io_interrupt_plic_gateway_priority; - reg system_uart_0_io_interrupt_plic_gateway_ip; - reg system_uart_0_io_interrupt_plic_gateway_waitCompletion; - wire when_PlicGateway_l21; - wire [1:0] system_spi_0_io_interrupt_plic_gateway_priority; - reg system_spi_0_io_interrupt_plic_gateway_ip; - reg system_spi_0_io_interrupt_plic_gateway_waitCompletion; - wire when_PlicGateway_l21_1; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; - wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; - wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; - wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; - reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; - reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_1; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_1; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; - wire system_plic_logic_bmb_cmd_valid; - wire system_plic_logic_bmb_cmd_ready; - wire system_plic_logic_bmb_cmd_payload_last; - wire [0:0] system_plic_logic_bmb_cmd_payload_fragment_opcode; - wire [21:0] system_plic_logic_bmb_cmd_payload_fragment_address; - wire [1:0] system_plic_logic_bmb_cmd_payload_fragment_length; - wire [31:0] system_plic_logic_bmb_cmd_payload_fragment_data; - wire [3:0] system_plic_logic_bmb_cmd_payload_fragment_context; - wire system_plic_logic_bmb_rsp_valid; - wire system_plic_logic_bmb_rsp_ready; - wire system_plic_logic_bmb_rsp_payload_last; - wire [0:0] system_plic_logic_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_plic_logic_bmb_rsp_payload_fragment_data; - wire [3:0] system_plic_logic_bmb_rsp_payload_fragment_context; - reg system_plic_logic_bus_readHaltTrigger; - wire system_plic_logic_bus_writeHaltTrigger; - wire system_plic_logic_bus_rsp_valid; - wire system_plic_logic_bus_rsp_ready; - wire system_plic_logic_bus_rsp_payload_last; - wire [0:0] system_plic_logic_bus_rsp_payload_fragment_opcode; - reg [31:0] system_plic_logic_bus_rsp_payload_fragment_data; - wire [3:0] system_plic_logic_bus_rsp_payload_fragment_context; - wire _zz_system_plic_logic_bmb_rsp_valid; - reg _zz_system_plic_logic_bus_rsp_ready; - wire _zz_system_plic_logic_bmb_rsp_valid_1; - reg _zz_system_plic_logic_bmb_rsp_valid_2; - reg _zz_system_plic_logic_bmb_rsp_payload_last; - reg [0:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_data; - reg [3:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_context; - wire when_Stream_l368_7; - wire system_plic_logic_bus_askWrite; - wire system_plic_logic_bus_askRead; - wire system_plic_logic_bmb_cmd_fire; - wire system_plic_logic_bus_doWrite; - wire system_plic_logic_bmb_cmd_fire_1; - wire system_plic_logic_bus_doRead; - wire system_cores_0_externalInterrupt_plic_target_ie_0; - wire system_cores_0_externalInterrupt_plic_target_ie_1; - wire [1:0] system_cores_0_externalInterrupt_plic_target_threshold; - wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_0_priority; - wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_0_id; - wire system_cores_0_externalInterrupt_plic_target_requests_0_valid; - wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_1_priority; - wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_1_id; - wire system_cores_0_externalInterrupt_plic_target_requests_1_valid; - wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_2_priority; - wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_2_id; - wire system_cores_0_externalInterrupt_plic_target_requests_2_valid; - wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority; - wire [1:0] _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1; - wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2; - wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3; - reg [1:0] system_cores_0_externalInterrupt_plic_target_bestRequest_priority; - reg [2:0] system_cores_0_externalInterrupt_plic_target_bestRequest_id; - reg system_cores_0_externalInterrupt_plic_target_bestRequest_valid; - wire system_cores_0_externalInterrupt_plic_target_iep; - wire [2:0] system_cores_0_externalInterrupt_plic_target_claim; - reg [1:0] _zz_system_uart_0_io_interrupt_plic_gateway_priority; - reg [1:0] _zz_system_spi_0_io_interrupt_plic_gateway_priority; - reg system_plic_logic_bridge_claim_valid; - reg [2:0] system_plic_logic_bridge_claim_payload; - reg system_plic_logic_bridge_completion_valid; - reg [2:0] system_plic_logic_bridge_completion_payload; - reg system_plic_logic_bridge_coherencyStall_willIncrement; - wire system_plic_logic_bridge_coherencyStall_willClear; - reg [0:0] system_plic_logic_bridge_coherencyStall_valueNext; - reg [0:0] system_plic_logic_bridge_coherencyStall_value; - wire system_plic_logic_bridge_coherencyStall_willOverflowIfInc; - wire system_plic_logic_bridge_coherencyStall_willOverflow; - wire when_PlicMapper_l122; - reg [1:0] _zz_system_cores_0_externalInterrupt_plic_target_threshold; - reg system_plic_logic_bridge_targetMapping_0_targetCompletion_valid; - wire [2:0] system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; - reg _zz_system_cores_0_externalInterrupt_plic_target_ie_0; - reg _zz_system_cores_0_externalInterrupt_plic_target_ie_1; - reg system_cores_0_externalInterrupt_plic_target_iep_regNext; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_2; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_2; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_3; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_3; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [21:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_4; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_4; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; - wire when_BmbSlaveFactory_l71; - - assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address >>> 2); - assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); - BufferCC_2 bufferCC_5 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_5_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .io_asyncReset (io_asyncReset ) //i - ); - BufferCC_3 bufferCC_6 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_6_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset) //i - ); - VexRiscv system_cores_0_logic_cpu ( - .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o - .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i - .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o - .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o - .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o - .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o - .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o - .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o - .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o - .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i - .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i - .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i - .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i - .timerInterrupt (_zz_timerInterrupt ), //i - .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i - .softwareInterrupt (_zz_softwareInterrupt ), //i - .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i - .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o - .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i - .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i - .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i - .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o - .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o - .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o - .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i - .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o - .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o - .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i - .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i - .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - JtagBridgeNoTap system_hardJtag_debug_logic_jtagBridge ( - .io_ctrl_tdi (jtagCtrl_tdi ), //i - .io_ctrl_enable (jtagCtrl_enable ), //i - .io_ctrl_capture (jtagCtrl_capture ), //i - .io_ctrl_shift (jtagCtrl_shift ), //i - .io_ctrl_update (jtagCtrl_update ), //i - .io_ctrl_reset (jtagCtrl_reset ), //i - .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i - .jtagCtrl_tck (jtagCtrl_tck ) //i - ); - SystemDebugger system_hardJtag_debug_logic_debugger ( - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o - .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i - .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o - .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o - .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i - .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BufferCC_4 bufferCC_7 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_7_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .system_cores_0_debugReset (system_cores_0_debugReset) //i - ); - BmbDecoder bmbDecoder_4 ( - .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i - .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i - .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BmbExclusiveMonitor system_fabric_exclusiveMonitor_logic ( - .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i - .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i - .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i - .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i - ); - BmbDecoder_1 system_fabric_iBus_bmb_decoder ( - .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i - ); - BmbArbiter system_bridge_bmb_arbiter ( - .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i - .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o - .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i - .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i - .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o - .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i - .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o - .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o - .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o - .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o - .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o - .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i - .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i - .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o - .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o - .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o - .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o - .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i - .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_2 system_bridge_bmb_decoder ( - .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o - .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i - .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o - .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbOnChipRam system_ramA_logic ( - .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i - .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i - .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i - .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify system_bridge_bmb_unburstify ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify system_bridge_bmb_unburstify_1 ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_3 system_bmbPeripheral_bmb_decoder ( - .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i - .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i - .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i - .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i - .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i - .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i - .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i - .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o - .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i - .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o - .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o - .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o - .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i - .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o - .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i - .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i - .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i - .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i - .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o - .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i - .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o - .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o - .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o - .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i - .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o - .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i - .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i - .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i - .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i - .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o - .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i - .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o - .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o - .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o - .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i - .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o - .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i - .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i - .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i - .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbClint system_clint_logic ( - .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o - .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o - .io_time (system_clint_logic_io_time[63:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUartCtrl system_uart_0_io_logic ( - .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i - .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i - .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i - .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o - .io_uart_rxd (system_uart_0_io_rxd ), //i - .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbSpiXdrMasterCtrl system_spi_0_io_logic ( - .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o - .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i - .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i - .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o - .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o - .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o - .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o - .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o - .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i - .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i - .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i - .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i - .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o - .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o - .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbToApb3Bridge io_apbSlave_0_logic ( - .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o - .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o - .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o - .io_output_PREADY (io_apbSlave_0_PREADY ), //i - .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o - .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o - .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i - .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - initial begin - debugCd_logic_holdingLogic_resetCounter = 12'h0; - debugCd_logic_outputReset = 1'b1; - end - - always @(*) begin - debugCd_logic_inputResetTrigger = 1'b0; - if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin - debugCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - debugCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); - assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; - always @(*) begin - systemCd_logic_inputResetTrigger = 1'b0; - if(bufferCC_6_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - if(bufferCC_7_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - systemCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); - assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; - assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; - assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; - assign system_cores_0_iBus_cmd_payload_last = 1'b1; - assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_iBus_rsp_ready = 1'b1; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; - always @(*) begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; - case(system_cores_0_logic_cpu_dBus_cmd_payload_size) - 3'b000 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; - end - 3'b001 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; - end - 3'b010 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; - end - 3'b011 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; - end - 3'b100 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; - end - 3'b101 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; - end - 3'b110 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; - end - default : begin - end - endcase - end - - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; - always @(*) begin - system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; - if(when_DataCache_l532) begin - system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; - end - end - - assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; - assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; - assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; - assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; - assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; - always @(*) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; - if(when_Stream_l368) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); - assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; - assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; - assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; - assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; - assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; - assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; - always @(*) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; - if(when_Stream_l368_1) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; - assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; - assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; - assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; - always @(*) begin - case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) - 2'b00 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; - end - 2'b01 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; - end - default : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; - end - endcase - end - - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; - assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; - assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; - assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; - assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; - assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; - assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; - assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); - always @(*) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_2) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; - always @(*) begin - _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_3) begin - _zz_io_input_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; - assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; - assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); - assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; - assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; - assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; - assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; - assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; - assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; - assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; - assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; - assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; - assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; - assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; - assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; - if(when_Stream_l368_4) begin - system_fabric_iBus_bmb_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); - assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; - assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; - assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; - assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; - assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; - assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; - assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; - assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; - assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; - assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; - assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; - assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; - assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; - assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; - assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; - assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); - always @(*) begin - system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_5) begin - system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; - assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; - assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; - assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; - assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; - always @(*) begin - _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_6) begin - _zz_io_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; - assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; - assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); - assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; - assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; - assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; - assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; - assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; - assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; - assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; - assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); - assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); - assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); - assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; - assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; - assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; - assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; - assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; - assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; - assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; - assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; - assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; - assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_plic_logic_bus_readHaltTrigger = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bus_readHaltTrigger = 1'b1; - end - end - - assign system_plic_logic_bus_writeHaltTrigger = 1'b0; - assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); - assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); - always @(*) begin - _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; - if(when_Stream_l368_7) begin - _zz_system_plic_logic_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); - assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; - assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; - assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; - assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; - assign system_plic_logic_bus_rsp_payload_last = 1'b1; - assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; - end - 22'h001000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; - end - 22'h000010 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; - end - 22'h200000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; - end - 22'h200004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; - end - 22'h002000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; - end - default : begin - end - endcase - end - - assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; - assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; - assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; - assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; - assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; - assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); - assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; - assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); - assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); - assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); - assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; - assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; - always @(*) begin - system_plic_logic_bridge_claim_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_valid = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_claim_payload = 3'bxxx; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_completion_valid = 1'b0; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_valid = 1'b1; - end - end - - always @(*) begin - system_plic_logic_bridge_completion_payload = 3'bxxx; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; - end - end - - always @(*) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(when_BmbSlaveFactory_l71) begin - if(system_plic_logic_bus_askWrite) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(system_plic_logic_bus_askRead) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - end - end - - assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; - assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); - assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); - always @(*) begin - system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); - if(system_plic_logic_bridge_coherencyStall_willClear) begin - system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; - end - end - - assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); - assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; - always @(*) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doWrite) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; - assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; - assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; - assign when_BmbSlaveFactory_l71 = 1'b1; - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); - end - if(debugCd_logic_inputResetTrigger) begin - debugCd_logic_holdingLogic_resetCounter <= 12'h0; - end - debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); - end - if(systemCd_logic_inputResetTrigger) begin - systemCd_logic_holdingLogic_resetCounter <= 6'h0; - end - systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - io_systemReset <= systemCd_logic_outputReset; - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; - _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; - _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; - system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; - system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; - system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; - end - if(system_bridge_bmb_cmd_ready) begin - system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; - system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; - system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; - system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; - system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; - system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; - system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; - system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; - end - if(_zz_io_input_rsp_ready_1) begin - _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - end - _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; - _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready_1) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; - _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; - _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; - _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; - end - system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); - system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); - system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); - system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; - end - - always @(posedge io_systemClk) begin - system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_fabric_iBus_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; - system_plic_logic_bridge_coherencyStall_value <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; - end else begin - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; - end - if(system_bridge_bmb_cmd_valid) begin - system_bridge_bmb_cmd_rValid <= 1'b1; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_rValid <= 1'b0; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; - end - if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; - end - if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_uart_0_io_logic_io_bus_rsp_valid) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; - end - if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - end - if(when_PlicGateway_l21) begin - system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; - end - if(when_PlicGateway_l21_1) begin - system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); - end - if(system_plic_logic_bridge_claim_valid) begin - case(system_plic_logic_bridge_claim_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - default : begin - end - endcase - end - if(system_plic_logic_bridge_completion_valid) begin - case(system_plic_logic_bridge_completion_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - default : begin - end - endcase - end - system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h000010 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h200000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h002000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; - end else begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; - end - end - - -endmodule - -module BmbToApb3Bridge ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [15:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [3:0] io_input_rsp_payload_fragment_context, - output [15:0] io_output_PADDR, - output [0:0] io_output_PSEL, - output io_output_PENABLE, - input io_output_PREADY, - output io_output_PWRITE, - output [31:0] io_output_PWDATA, - input [31:0] io_output_PRDATA, - input io_output_PSLVERROR, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire bmbBuffer_cmd_valid; - reg bmbBuffer_cmd_ready; - wire bmbBuffer_cmd_payload_last; - wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; - wire [15:0] bmbBuffer_cmd_payload_fragment_address; - wire [1:0] bmbBuffer_cmd_payload_fragment_length; - wire [31:0] bmbBuffer_cmd_payload_fragment_data; - wire [3:0] bmbBuffer_cmd_payload_fragment_context; - reg bmbBuffer_rsp_valid; - reg bmbBuffer_rsp_ready; - wire bmbBuffer_rsp_payload_last; - reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_payload_fragment_context; - wire io_input_rsp_isStall; - wire _zz_io_input_cmd_ready; - wire bmbBuffer_rsp_m2sPipe_valid; - wire bmbBuffer_rsp_m2sPipe_ready; - wire bmbBuffer_rsp_m2sPipe_payload_last; - wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; - reg bmbBuffer_rsp_rValid; - reg bmbBuffer_rsp_rData_last; - reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; - reg [31:0] bmbBuffer_rsp_rData_fragment_data; - reg [3:0] bmbBuffer_rsp_rData_fragment_context; - wire when_Stream_l368; - reg state; - wire when_BmbToApb3Bridge_l46; - - assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); - assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); - assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; - assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - always @(*) begin - bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; - if(when_Stream_l368) begin - bmbBuffer_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); - assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; - assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; - assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; - assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; - assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; - always @(*) begin - bmbBuffer_cmd_ready = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_cmd_ready = 1'b1; - end - end - end - - assign io_output_PSEL[0] = bmbBuffer_cmd_valid; - assign io_output_PENABLE = state; - assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); - assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; - assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; - always @(*) begin - bmbBuffer_rsp_valid = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_rsp_valid = 1'b1; - end - end - end - - assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; - assign when_BmbToApb3Bridge_l46 = (! state); - assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign bmbBuffer_rsp_payload_last = 1'b1; - always @(*) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b0; - if(io_output_PSLVERROR) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b1; - end - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - bmbBuffer_rsp_rValid <= 1'b0; - state <= 1'b0; - end else begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; - end - if(when_BmbToApb3Bridge_l46) begin - state <= bmbBuffer_cmd_valid; - end else begin - if(io_output_PREADY) begin - state <= 1'b0; - end - end - end - end - - always @(posedge io_systemClk) begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; - bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; - bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; - bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; - end - end - - -endmodule - -module BmbSpiXdrMasterCtrl ( - input io_ctrl_cmd_valid, - output io_ctrl_cmd_ready, - input io_ctrl_cmd_payload_last, - input [0:0] io_ctrl_cmd_payload_fragment_opcode, - input [11:0] io_ctrl_cmd_payload_fragment_address, - input [1:0] io_ctrl_cmd_payload_fragment_length, - input [31:0] io_ctrl_cmd_payload_fragment_data, - input [3:0] io_ctrl_cmd_payload_fragment_context, - output io_ctrl_rsp_valid, - input io_ctrl_rsp_ready, - output io_ctrl_rsp_payload_last, - output [0:0] io_ctrl_rsp_payload_fragment_opcode, - output [31:0] io_ctrl_rsp_payload_fragment_data, - output [3:0] io_ctrl_rsp_payload_fragment_context, - output [0:0] io_spi_sclk_write, - output io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output [0:0] io_spi_data_0_write, - output io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output [0:0] io_spi_data_1_write, - output io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output [0:0] io_spi_data_2_write, - output io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; - wire ctrl_io_cmd_ready; - wire ctrl_io_rsp_valid; - wire [7:0] ctrl_io_rsp_payload_data; - wire [0:0] ctrl_io_spi_sclk_write; - wire [0:0] ctrl_io_spi_ss; - wire [0:0] ctrl_io_spi_data_0_write; - wire ctrl_io_spi_data_0_writeEnable; - wire [0:0] ctrl_io_spi_data_1_write; - wire ctrl_io_spi_data_1_writeEnable; - wire [0:0] ctrl_io_spi_data_2_write; - wire ctrl_io_spi_data_2_writeEnable; - wire [0:0] ctrl_io_spi_data_3_write; - wire ctrl_io_spi_data_3_writeEnable; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; - wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_ctrl_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_ctrl_rsp_valid_1; - reg _zz_io_ctrl_rsp_valid_2; - reg _zz_io_ctrl_rsp_payload_last; - reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; - reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_ctrl_cmd_fire; - wire factory_doWrite; - wire io_ctrl_cmd_fire_1; - wire factory_doRead; - wire [31:0] mapping_cmdLogic_writeData; - reg mapping_cmdLogic_doRegular; - reg mapping_cmdLogic_doWriteLarge; - reg mapping_cmdLogic_doReadWriteLarge; - wire mapping_cmdLogic_streamUnbuffered_valid; - wire mapping_cmdLogic_streamUnbuffered_ready; - wire mapping_cmdLogic_streamUnbuffered_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_payload_read; - wire mapping_cmdLogic_streamUnbuffered_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - wire when_Stream_l368_1; - wire ctrl_io_rsp_toStream_valid; - wire ctrl_io_rsp_toStream_ready; - wire [7:0] ctrl_io_rsp_toStream_payload_data; - reg _zz_io_pop_ready; - reg _zz_io_pop_ready_1; - reg mapping_interruptCtrl_cmdIntEnable; - reg mapping_interruptCtrl_rspIntEnable; - wire mapping_interruptCtrl_cmdInt; - wire mapping_interruptCtrl_rspInt; - wire mapping_interruptCtrl_interrupt; - reg _zz_io_config_kind_cpol; - reg _zz_io_config_kind_cpha; - reg [1:0] _zz_io_config_mod; - reg [11:0] _zz_io_config_sclkToogle; - reg [11:0] _zz_io_config_ss_setup; - reg [11:0] _zz_io_config_ss_hold; - reg [11:0] _zz_io_config_ss_disable; - reg [0:0] _zz_io_config_ss_activeHigh; - wire [1:0] _zz_io_config_kind_cpol_1; - - TopLevel ctrl ( - .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i - .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i - .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i - .io_config_mod (_zz_io_config_mod[1:0] ), //i - .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i - .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i - .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i - .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i - .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i - .io_cmd_ready (ctrl_io_cmd_ready ), //o - .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i - .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i - .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i - .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i - .io_rsp_valid (ctrl_io_rsp_valid ), //o - .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o - .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (io_spi_data_0_read ), //i - .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (io_spi_data_1_read ), //i - .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (io_spi_data_2_read ), //i - .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (io_spi_data_3_read ), //i - .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o - .io_spi_ss (ctrl_io_spi_ss ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_2 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( - .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i - .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o - .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i - .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i - .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i - .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i - .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o - .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i - .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o - .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o - .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o - .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o - .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_3 ctrl_io_rsp_queueWithOccupancy ( - .io_push_valid (ctrl_io_rsp_toStream_valid ), //i - .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o - .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i - .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o - .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_ctrl_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); - assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - 12'h004 : begin - factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; - end - 12'h00c : begin - factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; - factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; - factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; - factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; - end - 12'h058 : begin - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - default : begin - end - endcase - end - - assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - always @(*) begin - mapping_cmdLogic_doRegular = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doRegular = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h050 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doReadWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h054 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doReadWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); - assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; - assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); - always @(*) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_1) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; - assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; - assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; - assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; - always @(*) begin - _zz_io_pop_ready = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doRead) begin - _zz_io_pop_ready = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - _zz_io_pop_ready_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h058 : begin - if(factory_doRead) begin - _zz_io_pop_ready_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); - assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); - assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); - assign io_spi_sclk_write = ctrl_io_spi_sclk_write; - assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; - assign io_spi_data_0_write = ctrl_io_spi_data_0_write; - assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; - assign io_spi_data_1_write = ctrl_io_spi_data_1_write; - assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; - assign io_spi_data_2_write = ctrl_io_spi_data_2_write; - assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; - assign io_spi_data_3_write = ctrl_io_spi_data_3_write; - assign io_spi_ss = ctrl_io_spi_ss; - assign io_interrupt = mapping_interruptCtrl_interrupt; - assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; - assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_ctrl_rsp_valid_2 <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; - mapping_interruptCtrl_cmdIntEnable <= 1'b0; - mapping_interruptCtrl_rspIntEnable <= 1'b0; - _zz_io_config_ss_activeHigh <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h00c : begin - if(factory_doWrite) begin - mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; - mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; - end - end - 12'h030 : begin - if(factory_doWrite) begin - _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h008 : begin - if(factory_doWrite) begin - _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; - _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; - _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; - end - end - 12'h020 : begin - if(factory_doWrite) begin - _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h024 : begin - if(factory_doWrite) begin - _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h028 : begin - if(factory_doWrite) begin - _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h02c : begin - if(factory_doWrite) begin - _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - default : begin - end - endcase - end - - -endmodule - -module BmbUartCtrl ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [5:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output io_uart_txd, - input io_uart_rxd, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; - wire uartCtrl_1_io_write_ready; - wire uartCtrl_1_io_read_valid; - wire [7:0] uartCtrl_1_io_read_payload; - wire uartCtrl_1_io_uart_txd; - wire uartCtrl_1_io_readError; - wire uartCtrl_1_io_readBreak; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; - wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; - wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; - wire [0:0] _zz_bridge_misc_readError; - wire [0:0] _zz_bridge_misc_readOverflowError; - wire [0:0] _zz_bridge_misc_breakDetected; - wire [0:0] _zz_bridge_misc_doBreak; - wire [0:0] _zz_bridge_misc_doBreak_1; - wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - wire [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [3:0] busCtrl_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_busCtrl_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_bus_cmd_fire; - wire busCtrl_doWrite; - wire io_bus_cmd_fire_1; - wire busCtrl_doRead; - reg [2:0] bridge_uartConfigReg_frame_dataLength; - reg [0:0] bridge_uartConfigReg_frame_stop; - reg [1:0] bridge_uartConfigReg_frame_parity; - reg [19:0] bridge_uartConfigReg_clockDivider; - reg _zz_bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_ready; - wire [7:0] bridge_write_streamUnbuffered_payload; - reg bridge_read_streamBreaked_valid; - reg bridge_read_streamBreaked_ready; - wire [7:0] bridge_read_streamBreaked_payload; - reg bridge_interruptCtrl_writeIntEnable; - reg bridge_interruptCtrl_readIntEnable; - wire bridge_interruptCtrl_readInt; - wire bridge_interruptCtrl_writeInt; - wire bridge_interruptCtrl_interrupt; - reg bridge_misc_readError; - reg when_BusSlaveFactory_l335; - wire when_BusSlaveFactory_l341; - reg bridge_misc_readOverflowError; - reg when_BusSlaveFactory_l335_1; - wire when_BusSlaveFactory_l341_1; - wire uartCtrl_1_io_read_isStall; - reg bridge_misc_breakDetected; - reg uartCtrl_1_io_readBreak_regNext; - wire when_UartCtrl_l155; - reg when_BusSlaveFactory_l335_2; - wire when_BusSlaveFactory_l341_2; - reg bridge_misc_doBreak; - reg when_BusSlaveFactory_l371; - wire when_BusSlaveFactory_l373; - reg when_BusSlaveFactory_l335_3; - wire when_BusSlaveFactory_l341_3; - wire [1:0] _zz_bridge_uartConfigReg_frame_parity; - wire [0:0] _zz_bridge_uartConfigReg_frame_stop; - wire when_BmbSlaveFactory_l71; - `ifndef SYNTHESIS - reg [23:0] bridge_uartConfigReg_frame_stop_string; - reg [31:0] bridge_uartConfigReg_frame_parity_string; - reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; - reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; - `endif - - - assign _zz_bridge_misc_readError = 1'b0; - assign _zz_bridge_misc_readOverflowError = 1'b0; - assign _zz_bridge_misc_breakDetected = 1'b0; - assign _zz_bridge_misc_doBreak = 1'b1; - assign _zz_bridge_misc_doBreak_1 = 1'b0; - assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); - assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; - assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; - UartCtrl uartCtrl_1 ( - .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i - .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i - .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i - .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i - .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i - .io_write_ready (uartCtrl_1_io_write_ready ), //o - .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i - .io_read_valid (uartCtrl_1_io_read_valid ), //o - .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i - .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o - .io_uart_txd (uartCtrl_1_io_uart_txd ), //o - .io_uart_rxd (io_uart_rxd ), //i - .io_readError (uartCtrl_1_io_readError ), //o - .io_writeBreak (bridge_misc_doBreak ), //i - .io_readBreak (uartCtrl_1_io_readBreak ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( - .io_push_valid (bridge_write_streamUnbuffered_valid ), //i - .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i - .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_write_ready ), //i - .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo uartCtrl_1_io_read_queueWithOccupancy ( - .io_push_valid (uartCtrl_1_io_read_valid ), //i - .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i - .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(bridge_uartConfigReg_frame_stop) - UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; - default : bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(bridge_uartConfigReg_frame_parity) - UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; - default : bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_parity) - UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; - default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_stop) - UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; - default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - `endif - - assign io_uart_txd = uartCtrl_1_io_uart_txd; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_busCtrl_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_busCtrl_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign busCtrl_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; - end - 6'h04 : begin - busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; - end - 6'h10 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; - busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - always @(*) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doWrite) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; - assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; - assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - always @(*) begin - bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - if(uartCtrl_1_io_readBreak) begin - bridge_read_streamBreaked_valid = 1'b0; - end - end - - always @(*) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; - if(uartCtrl_1_io_readBreak) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; - end - end - - assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - always @(*) begin - bridge_read_streamBreaked_ready = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doRead) begin - bridge_read_streamBreaked_ready = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); - assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); - assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); - always @(*) begin - when_BusSlaveFactory_l335 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; - always @(*) begin - when_BusSlaveFactory_l335_1 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; - assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); - assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); - always @(*) begin - when_BusSlaveFactory_l335_2 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l371 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l371 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l335_3 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; - assign io_interrupt = bridge_interruptCtrl_interrupt; - assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; - assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - bridge_uartConfigReg_clockDivider <= 20'h0; - bridge_uartConfigReg_clockDivider <= 20'h00035; - bridge_uartConfigReg_frame_dataLength <= 3'b111; - bridge_uartConfigReg_frame_parity <= UartParityType_NONE; - bridge_uartConfigReg_frame_stop <= UartStopType_ONE; - bridge_interruptCtrl_writeIntEnable <= 1'b0; - bridge_interruptCtrl_readIntEnable <= 1'b0; - bridge_misc_readError <= 1'b0; - bridge_misc_readOverflowError <= 1'b0; - bridge_misc_breakDetected <= 1'b0; - bridge_misc_doBreak <= 1'b0; - end else begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); - end - if(when_BusSlaveFactory_l335) begin - if(when_BusSlaveFactory_l341) begin - bridge_misc_readError <= _zz_bridge_misc_readError[0]; - end - end - if(uartCtrl_1_io_readError) begin - bridge_misc_readError <= 1'b1; - end - if(when_BusSlaveFactory_l335_1) begin - if(when_BusSlaveFactory_l341_1) begin - bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; - end - end - if(uartCtrl_1_io_read_isStall) begin - bridge_misc_readOverflowError <= 1'b1; - end - if(when_UartCtrl_l155) begin - bridge_misc_breakDetected <= 1'b1; - end - if(when_BusSlaveFactory_l335_2) begin - if(when_BusSlaveFactory_l341_2) begin - bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; - end - end - if(when_BusSlaveFactory_l371) begin - if(when_BusSlaveFactory_l373) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; - end - end - if(when_BusSlaveFactory_l335_3) begin - if(when_BusSlaveFactory_l341_3) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; - end - end - case(io_bus_cmd_payload_fragment_address) - 6'h0c : begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; - bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; - bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; - end - end - 6'h04 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; - end - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; - end - end - end - end - - always @(posedge io_systemClk) begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; - end - - -endmodule - -module BmbClint ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [15:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output [0:0] io_timerInterrupt, - output [0:0] io_softwareInterrupt, - output [63:0] io_time, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [31:0] _zz_logic_harts_0_cmp; - wire [31:0] _zz_logic_harts_0_cmp_1; - wire [31:0] _zz_logic_harts_0_cmp_2; - wire [31:0] _zz_logic_harts_0_cmp_3; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_bus_cmd_fire; - wire factory_doWrite; - wire io_bus_cmd_fire_1; - wire factory_doRead; - reg [63:0] logic_time; - reg [63:0] logic_harts_0_cmp; - reg logic_harts_0_timerInterrupt; - reg logic_harts_0_softwareInterrupt; - wire [63:0] _zz_factory_rsp_payload_fragment_data; - wire when_BmbSlaveFactory_l71; - wire when_BmbSlaveFactory_l71_1; - wire when_BmbSlaveFactory_l71_2; - wire when_BmbSlaveFactory_l71_3; - - assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; - assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; - end - if(when_BmbSlaveFactory_l71_1) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; - end - end - - assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - assign _zz_factory_rsp_payload_fragment_data = logic_time; - assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; - assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; - assign io_time = logic_time; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); - assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); - assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); - assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - logic_time <= 64'h0; - logic_harts_0_softwareInterrupt <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); - end - logic_time <= (logic_time + 64'h0000000000000001); - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - if(factory_doWrite) begin - logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); - if(when_BmbSlaveFactory_l71_2) begin - if(factory_doWrite) begin - logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; - end - end - if(when_BmbSlaveFactory_l71_3) begin - if(factory_doWrite) begin - logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; - end - end - end - - -endmodule - -module BmbDecoder_3 ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [23:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [3:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [3:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [23:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [3:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [3:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [23:0] io_outputs_1_cmd_payload_fragment_address, - output [1:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [3:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [3:0] io_outputs_1_rsp_payload_fragment_context, - output reg io_outputs_2_cmd_valid, - input io_outputs_2_cmd_ready, - output io_outputs_2_cmd_payload_last, - output [0:0] io_outputs_2_cmd_payload_fragment_opcode, - output [23:0] io_outputs_2_cmd_payload_fragment_address, - output [1:0] io_outputs_2_cmd_payload_fragment_length, - output [31:0] io_outputs_2_cmd_payload_fragment_data, - output [3:0] io_outputs_2_cmd_payload_fragment_mask, - output [3:0] io_outputs_2_cmd_payload_fragment_context, - input io_outputs_2_rsp_valid, - output io_outputs_2_rsp_ready, - input io_outputs_2_rsp_payload_last, - input [0:0] io_outputs_2_rsp_payload_fragment_opcode, - input [31:0] io_outputs_2_rsp_payload_fragment_data, - input [3:0] io_outputs_2_rsp_payload_fragment_context, - output reg io_outputs_3_cmd_valid, - input io_outputs_3_cmd_ready, - output io_outputs_3_cmd_payload_last, - output [0:0] io_outputs_3_cmd_payload_fragment_opcode, - output [23:0] io_outputs_3_cmd_payload_fragment_address, - output [1:0] io_outputs_3_cmd_payload_fragment_length, - output [31:0] io_outputs_3_cmd_payload_fragment_data, - output [3:0] io_outputs_3_cmd_payload_fragment_mask, - output [3:0] io_outputs_3_cmd_payload_fragment_context, - input io_outputs_3_rsp_valid, - output io_outputs_3_rsp_ready, - input io_outputs_3_rsp_payload_last, - input [0:0] io_outputs_3_rsp_payload_fragment_opcode, - input [31:0] io_outputs_3_rsp_payload_fragment_data, - input [3:0] io_outputs_3_rsp_payload_fragment_context, - output reg io_outputs_4_cmd_valid, - input io_outputs_4_cmd_ready, - output io_outputs_4_cmd_payload_last, - output [0:0] io_outputs_4_cmd_payload_fragment_opcode, - output [23:0] io_outputs_4_cmd_payload_fragment_address, - output [1:0] io_outputs_4_cmd_payload_fragment_length, - output [31:0] io_outputs_4_cmd_payload_fragment_data, - output [3:0] io_outputs_4_cmd_payload_fragment_mask, - output [3:0] io_outputs_4_cmd_payload_fragment_context, - input io_outputs_4_rsp_valid, - output io_outputs_4_rsp_ready, - input io_outputs_4_rsp_payload_last, - input [0:0] io_outputs_4_rsp_payload_fragment_opcode, - input [31:0] io_outputs_4_rsp_payload_fragment_data, - input [3:0] io_outputs_4_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_logic_rspPendingCounter; - wire [3:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [3:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_3; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [3:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [3:0] logic_input_payload_fragment_context; - reg io_input_cmd_rValid; - wire logic_input_fire; - reg io_input_cmd_rData_last; - reg [0:0] io_input_cmd_rData_fragment_opcode; - reg [23:0] io_input_cmd_rData_fragment_address; - reg [1:0] io_input_cmd_rData_fragment_length; - reg [31:0] io_input_cmd_rData_fragment_data; - reg [3:0] io_input_cmd_rData_fragment_mask; - reg [3:0] io_input_cmd_rData_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_hitsS0_2; - wire logic_hitsS0_3; - wire logic_hitsS0_4; - wire logic_noHitS0; - wire io_input_cmd_fire; - reg logic_hitsS1_0; - reg logic_hitsS1_1; - reg logic_hitsS1_2; - reg logic_hitsS1_3; - reg logic_hitsS1_4; - wire io_input_cmd_fire_1; - reg logic_noHitS1; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - wire _zz_io_outputs_2_cmd_payload_last; - wire _zz_io_outputs_3_cmd_payload_last; - wire _zz_io_outputs_4_cmd_payload_last; - reg [3:0] logic_rspPendingCounter; - wire logic_input_fire_1; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - reg logic_rspHits_2; - reg logic_rspHits_3; - reg logic_rspHits_4; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_2; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_3; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_4; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_context; - wire logic_input_fire_6; - wire _zz_io_input_rsp_payload_last; - wire _zz_io_input_rsp_payload_last_1; - wire [2:0] _zz_io_input_rsp_payload_last_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last_2) - 3'b000 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - 3'b001 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - 3'b010 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; - end - 3'b011 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_cmd_ready = (! io_input_cmd_rValid); - assign logic_input_valid = io_input_cmd_rValid; - assign logic_input_payload_last = io_input_cmd_rData_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); - assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); - assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); - always @(*) begin - io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); - if(logic_cmdWait) begin - io_outputs_2_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; - assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; - assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); - always @(*) begin - io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); - if(logic_cmdWait) begin - io_outputs_3_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; - assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; - assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); - always @(*) begin - io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); - if(logic_cmdWait) begin - io_outputs_4_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; - assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; - assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); - assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign io_outputs_2_rsp_ready = io_input_rsp_ready; - assign io_outputs_3_rsp_ready = io_input_rsp_ready; - assign io_outputs_4_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_input_cmd_rValid <= 1'b0; - logic_rspPendingCounter <= 4'b0000; - logic_rspNoHit_doIt <= 1'b0; - end else begin - if(io_input_cmd_valid) begin - io_input_cmd_rValid <= 1'b1; - end - if(logic_input_fire) begin - io_input_cmd_rValid <= 1'b0; - end - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(io_input_cmd_ready) begin - io_input_cmd_rData_last <= io_input_cmd_payload_last; - io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; - io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; - io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; - io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; - io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; - io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; - end - if(io_input_cmd_fire) begin - logic_hitsS1_0 <= logic_hitsS0_0; - logic_hitsS1_1 <= logic_hitsS0_1; - logic_hitsS1_2 <= logic_hitsS0_2; - logic_hitsS1_3 <= logic_hitsS0_3; - logic_hitsS1_4 <= logic_hitsS0_4; - end - if(io_input_cmd_fire_1) begin - logic_noHitS1 <= logic_noHitS0; - end - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS1_0; - logic_rspHits_1 <= logic_hitsS1_1; - logic_rspHits_2 <= logic_hitsS1_2; - logic_rspHits_3 <= logic_hitsS1_3; - logic_rspHits_4 <= logic_hitsS1_4; - end - if(logic_input_fire_3) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_5) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - end - - -endmodule - -//BmbUnburstify replaced by BmbUnburstify - -module BmbUnburstify ( - input io_input_cmd_valid, - output reg io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_source, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output reg io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output reg [0:0] io_output_cmd_payload_fragment_opcode, - output reg [31:0] io_output_cmd_payload_fragment_address, - output reg [1:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [3:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output reg io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [3:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_buffer_last; - wire [0:0] _zz_buffer_last_1; - wire [11:0] _zz_buffer_addressIncr; - wire [11:0] _zz_buffer_addressIncr_1; - wire [11:0] _zz_buffer_addressIncr_2; - wire doResult; - reg buffer_valid; - reg [0:0] buffer_opcode; - reg [0:0] buffer_source; - reg [31:0] buffer_address; - reg [0:0] buffer_context; - reg [3:0] buffer_beat; - wire buffer_last; - wire [31:0] buffer_addressIncr; - wire buffer_isWrite; - wire io_output_cmd_fire; - wire [3:0] cmdTransferBeatCount; - wire requireBuffer; - reg cmdContext_drop; - reg cmdContext_last; - reg [0:0] cmdContext_source; - reg [0:0] cmdContext_context; - wire io_output_cmd_fire_1; - wire rspContext_drop; - wire rspContext_last; - wire [0:0] rspContext_source; - wire [0:0] rspContext_context; - wire [3:0] _zz_rspContext_drop; - wire when_Stream_l434; - reg io_output_rsp_thrown_valid; - wire io_output_rsp_thrown_ready; - wire io_output_rsp_thrown_payload_last; - wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; - wire [31:0] io_output_rsp_thrown_payload_fragment_data; - wire [3:0] io_output_rsp_thrown_payload_fragment_context; - - assign _zz_buffer_last_1 = 1'b1; - assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; - assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); - assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; - assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; - assign buffer_last = (buffer_beat == _zz_buffer_last); - assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; - assign buffer_isWrite = (buffer_opcode == 1'b1); - assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); - assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; - assign requireBuffer = (cmdTransferBeatCount != 4'b0000); - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_last = 1'b1; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_address = buffer_addressIncr; - end else begin - io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - if(requireBuffer) begin - io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; - end - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_opcode = buffer_opcode; - end else begin - io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - if(requireBuffer) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; - end - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_context = buffer_context; - end else begin - cmdContext_context = io_input_cmd_payload_fragment_context; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_source = buffer_source; - end else begin - cmdContext_source = io_input_cmd_payload_fragment_source; - end - end - - always @(*) begin - io_input_cmd_ready = 1'b0; - if(buffer_valid) begin - io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); - end else begin - io_input_cmd_ready = io_output_cmd_ready; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); - end else begin - io_output_cmd_valid = io_input_cmd_valid; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_last = buffer_last; - end else begin - cmdContext_last = (! requireBuffer); - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_drop = buffer_isWrite; - end else begin - cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); - end - end - - assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); - assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; - assign rspContext_drop = _zz_rspContext_drop[0]; - assign rspContext_last = _zz_rspContext_drop[1]; - assign rspContext_source = _zz_rspContext_drop[2 : 2]; - assign rspContext_context = _zz_rspContext_drop[3 : 3]; - assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); - always @(*) begin - io_output_rsp_thrown_valid = io_output_rsp_valid; - if(when_Stream_l434) begin - io_output_rsp_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_output_rsp_ready = io_output_rsp_thrown_ready; - if(when_Stream_l434) begin - io_output_rsp_ready = 1'b1; - end - end - - assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; - assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_input_rsp_valid = io_output_rsp_thrown_valid; - assign io_output_rsp_thrown_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = rspContext_last; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = rspContext_context; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffer_valid <= 1'b0; - end else begin - if(io_output_cmd_fire) begin - if(buffer_last) begin - buffer_valid <= 1'b0; - end - end - if(!buffer_valid) begin - buffer_valid <= (requireBuffer && io_output_cmd_fire_1); - end - end - end - - always @(posedge io_systemClk) begin - if(io_output_cmd_fire) begin - buffer_beat <= (buffer_beat - 4'b0001); - buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; - end - if(!buffer_valid) begin - buffer_opcode <= io_input_cmd_payload_fragment_opcode; - buffer_source <= io_input_cmd_payload_fragment_source; - buffer_address <= io_input_cmd_payload_fragment_address; - buffer_context <= io_input_cmd_payload_fragment_context; - buffer_beat <= cmdTransferBeatCount; - end - end - - -endmodule - -module BmbOnChipRam ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [14:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_mask, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_ram_port0; - wire io_bus_rsp_isStall; - reg io_bus_cmd_valid_regNextWhen; - reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; - wire [12:0] _zz_io_bus_rsp_payload_fragment_data; - wire io_bus_cmd_fire; - wire _zz_io_bus_rsp_payload_fragment_data_1; - wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; - reg [7:0] ram_symbol0 [0:8191]; - reg [7:0] ram_symbol1 [0:8191]; - reg [7:0] ram_symbol2 [0:8191]; - reg [7:0] ram_symbol3 [0:8191]; - reg [7:0] _zz_ramsymbol_read; - reg [7:0] _zz_ramsymbol_read_1; - reg [7:0] _zz_ramsymbol_read_2; - reg [7:0] _zz_ramsymbol_read_3; - - initial begin - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); - end - always @(*) begin - _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; - end - always @(posedge io_systemClk) begin - if(io_bus_cmd_fire) begin - _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; - end - if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; - end - if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; - end - if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; - end - end - - assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); - assign io_bus_cmd_ready = (! io_bus_rsp_isStall); - assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; - assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; - assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); - assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; - assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; - assign io_bus_rsp_payload_fragment_opcode = 1'b0; - assign io_bus_rsp_payload_last = 1'b1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_bus_cmd_valid_regNextWhen <= 1'b0; - end else begin - if(io_bus_cmd_ready) begin - io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; - end - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_ready) begin - io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; - end - end - - -endmodule - -module BmbDecoder_2 ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_source, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [0:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_source, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [0:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_source, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [0:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_source, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [31:0] io_outputs_1_cmd_payload_fragment_address, - output [5:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [0:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_source, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [0:0] io_outputs_1_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_1; - reg [0:0] _zz_io_input_rsp_payload_fragment_source; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [0:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_source; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [5:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [0:0] logic_input_payload_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - reg [0:0] logic_rspNoHit_source; - wire logic_input_fire_4; - reg [0:0] logic_rspNoHit_context; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_counter; - wire [0:0] _zz_io_input_rsp_payload_last; - wire when_BmbDecoder_l81; - wire io_input_rsp_fire_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last) - 1'b0 : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = logic_rspHits_1; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b0; - if(when_BmbDecoder_l81) begin - io_input_rsp_payload_last = 1'b1; - end - if(logic_rspNoHit_singleBeatRsp) begin - io_input_rsp_payload_last = 1'b1; - end - end - end - - always @(*) begin - io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_source = logic_rspNoHit_source; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); - assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - logic_rspHits_1 <= logic_hitsS0_1; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_3) begin - logic_rspNoHit_source <= logic_input_payload_fragment_source; - end - if(logic_input_fire_4) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - if(logic_input_fire_5) begin - logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; - end - if(logic_rspNoHit_doIt) begin - if(io_input_rsp_fire_2) begin - logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); - end - end - end - - -endmodule - -module BmbArbiter ( - input io_inputs_0_cmd_valid, - output io_inputs_0_cmd_ready, - input io_inputs_0_cmd_payload_last, - input [0:0] io_inputs_0_cmd_payload_fragment_opcode, - input [31:0] io_inputs_0_cmd_payload_fragment_address, - input [5:0] io_inputs_0_cmd_payload_fragment_length, - input [31:0] io_inputs_0_cmd_payload_fragment_data, - input [3:0] io_inputs_0_cmd_payload_fragment_mask, - input [0:0] io_inputs_0_cmd_payload_fragment_context, - output io_inputs_0_rsp_valid, - input io_inputs_0_rsp_ready, - output io_inputs_0_rsp_payload_last, - output [0:0] io_inputs_0_rsp_payload_fragment_opcode, - output [31:0] io_inputs_0_rsp_payload_fragment_data, - output [0:0] io_inputs_0_rsp_payload_fragment_context, - input io_inputs_1_cmd_valid, - output io_inputs_1_cmd_ready, - input io_inputs_1_cmd_payload_last, - input [0:0] io_inputs_1_cmd_payload_fragment_opcode, - input [31:0] io_inputs_1_cmd_payload_fragment_address, - input [5:0] io_inputs_1_cmd_payload_fragment_length, - input [31:0] io_inputs_1_cmd_payload_fragment_data, - input [3:0] io_inputs_1_cmd_payload_fragment_mask, - output io_inputs_1_rsp_valid, - input io_inputs_1_rsp_ready, - output io_inputs_1_rsp_payload_last, - output [0:0] io_inputs_1_rsp_payload_fragment_opcode, - output [31:0] io_inputs_1_rsp_payload_fragment_data, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_source, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_source, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire memory_arbiter_io_inputs_0_ready; - wire memory_arbiter_io_inputs_1_ready; - wire memory_arbiter_io_output_valid; - wire memory_arbiter_io_output_payload_last; - wire [0:0] memory_arbiter_io_output_payload_fragment_source; - wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; - wire [31:0] memory_arbiter_io_output_payload_fragment_address; - wire [5:0] memory_arbiter_io_output_payload_fragment_length; - wire [31:0] memory_arbiter_io_output_payload_fragment_data; - wire [3:0] memory_arbiter_io_output_payload_fragment_mask; - wire [0:0] memory_arbiter_io_output_payload_fragment_context; - wire [0:0] memory_arbiter_io_chosen; - wire [1:0] memory_arbiter_io_chosenOH; - wire [1:0] _zz_io_output_cmd_payload_fragment_source; - reg _zz_io_output_rsp_ready; - wire [0:0] memory_rspSel; - - assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; - StreamArbiter memory_arbiter ( - .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i - .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o - .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i - .io_inputs_0_payload_fragment_source (1'b0 ), //i - .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i - .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i - .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o - .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i - .io_inputs_1_payload_fragment_source (1'b0 ), //i - .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i - .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_1_payload_fragment_context (1'b0 ), //i - .io_output_valid (memory_arbiter_io_output_valid ), //o - .io_output_ready (io_output_cmd_ready ), //i - .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o - .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o - .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o - .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o - .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o - .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o - .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o - .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o - .io_chosen (memory_arbiter_io_chosen ), //o - .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(memory_rspSel) - 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; - default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; - endcase - end - - assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; - assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; - assign io_output_cmd_valid = memory_arbiter_io_output_valid; - assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; - assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; - assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; - assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; - assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); - assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); - assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_ready = _zz_io_output_rsp_ready; - -endmodule - -module BmbDecoder_1 ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data -); - - - assign io_outputs_0_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_outputs_0_cmd_ready; - assign io_input_rsp_valid = io_outputs_0_rsp_valid; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - -endmodule - -module BmbExclusiveMonitor ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context -); - - - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - -endmodule - -module BmbDecoder ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire logic_hitsS0_0; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - wire logic_input_fire_4; - wire logic_input_fire_5; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - always @(*) begin - logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - end - - -endmodule - -module BufferCC_4 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input system_cores_0_debugReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin - if(system_cores_0_debugReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module SystemDebugger ( - input io_remote_cmd_valid, - output io_remote_cmd_ready, - input io_remote_cmd_payload_last, - input [0:0] io_remote_cmd_payload_fragment, - output io_remote_rsp_valid, - input io_remote_rsp_ready, - output io_remote_rsp_payload_error, - output [31:0] io_remote_rsp_payload_data, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output io_mem_cmd_payload_wr, - output [1:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload, - input io_systemClk, - input debugCd_logic_outputReset -); - - reg [66:0] dispatcher_dataShifter; - reg dispatcher_dataLoaded; - reg [7:0] dispatcher_headerShifter; - wire [7:0] dispatcher_header; - reg dispatcher_headerLoaded; - reg [2:0] dispatcher_counter; - wire when_Fragment_l346; - wire when_Fragment_l349; - wire [66:0] _zz_io_mem_cmd_payload_address; - wire io_mem_cmd_isStall; - wire when_Fragment_l372; - - assign dispatcher_header = dispatcher_headerShifter[7 : 0]; - assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); - assign when_Fragment_l349 = (dispatcher_counter == 3'b111); - assign io_remote_cmd_ready = (! dispatcher_dataLoaded); - assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; - assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; - assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; - assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; - assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; - assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); - assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); - assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); - assign io_remote_rsp_valid = io_mem_rsp_valid; - assign io_remote_rsp_payload_error = 1'b0; - assign io_remote_rsp_payload_data = io_mem_rsp_payload; - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - dispatcher_dataLoaded <= 1'b0; - dispatcher_headerLoaded <= 1'b0; - dispatcher_counter <= 3'b000; - end else begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_counter <= (dispatcher_counter + 3'b001); - if(when_Fragment_l349) begin - dispatcher_headerLoaded <= 1'b1; - end - end - if(io_remote_cmd_payload_last) begin - dispatcher_headerLoaded <= 1'b1; - dispatcher_dataLoaded <= 1'b1; - dispatcher_counter <= 3'b000; - end - end - if(when_Fragment_l372) begin - dispatcher_headerLoaded <= 1'b0; - dispatcher_dataLoaded <= 1'b0; - end - end - end - - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); - end else begin - dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); - end - end - end - - -endmodule - -module JtagBridgeNoTap ( - input io_ctrl_tdi, - input io_ctrl_enable, - input io_ctrl_capture, - input io_ctrl_shift, - input io_ctrl_update, - input io_ctrl_reset, - output io_ctrl_tdo, - output io_remote_cmd_valid, - input io_remote_cmd_ready, - output io_remote_cmd_payload_last, - output [0:0] io_remote_cmd_payload_fragment, - input io_remote_rsp_valid, - output io_remote_rsp_ready, - input io_remote_rsp_payload_error, - input [31:0] io_remote_rsp_payload_data, - input io_systemClk, - input debugCd_logic_outputReset, - input jtagCtrl_tck -); - - wire flowCCByToggle_1_io_output_valid; - wire flowCCByToggle_1_io_output_payload_last; - wire [0:0] flowCCByToggle_1_io_output_payload_fragment; - wire system_cmd_valid; - wire system_cmd_payload_last; - wire [0:0] system_cmd_payload_fragment; - wire system_cmd_toStream_valid; - wire system_cmd_toStream_ready; - wire system_cmd_toStream_payload_last; - wire [0:0] system_cmd_toStream_payload_fragment; - (* async_reg = "true" *) reg system_rsp_valid; - (* async_reg = "true" *) reg system_rsp_payload_error; - (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; - wire io_remote_rsp_fire; - wire jtag_wrapper_ctrl_tdi; - wire jtag_wrapper_ctrl_enable; - wire jtag_wrapper_ctrl_capture; - wire jtag_wrapper_ctrl_shift; - wire jtag_wrapper_ctrl_update; - wire jtag_wrapper_ctrl_reset; - reg jtag_wrapper_ctrl_tdo; - reg [1:0] jtag_wrapper_header; - wire [1:0] jtag_wrapper_headerNext; - reg [0:0] jtag_wrapper_counter; - reg jtag_wrapper_done; - reg jtag_wrapper_sendCapture; - reg jtag_wrapper_sendShift; - reg jtag_wrapper_sendUpdate; - wire when_JtagTapInstructions_l183; - wire when_JtagTapInstructions_l186; - wire jtag_writeArea_ctrl_tdi; - wire jtag_writeArea_ctrl_enable; - wire jtag_writeArea_ctrl_capture; - wire jtag_writeArea_ctrl_shift; - wire jtag_writeArea_ctrl_update; - wire jtag_writeArea_ctrl_reset; - wire jtag_writeArea_ctrl_tdo; - wire jtag_writeArea_source_valid; - wire jtag_writeArea_source_payload_last; - wire [0:0] jtag_writeArea_source_payload_fragment; - reg jtag_writeArea_valid; - reg jtag_writeArea_data; - wire when_JtagTapInstructions_l209; - wire jtag_readArea_ctrl_tdi; - wire jtag_readArea_ctrl_enable; - wire jtag_readArea_ctrl_capture; - wire jtag_readArea_ctrl_shift; - wire jtag_readArea_ctrl_update; - wire jtag_readArea_ctrl_reset; - wire jtag_readArea_ctrl_tdo; - reg [33:0] jtag_readArea_full_shifter; - wire when_JtagTapInstructions_l209_1; - - FlowCCByToggle flowCCByToggle_1 ( - .io_input_valid (jtag_writeArea_source_valid ), //i - .io_input_payload_last (jtag_writeArea_source_payload_last ), //i - .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i - .io_output_valid (flowCCByToggle_1_io_output_valid ), //o - .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o - .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o - .jtagCtrl_tck (jtagCtrl_tck ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - assign system_cmd_toStream_valid = system_cmd_valid; - assign system_cmd_toStream_payload_last = system_cmd_payload_last; - assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; - assign io_remote_cmd_valid = system_cmd_toStream_valid; - assign system_cmd_toStream_ready = io_remote_cmd_ready; - assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; - assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; - assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); - assign io_remote_rsp_ready = 1'b1; - assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); - always @(*) begin - jtag_wrapper_sendCapture = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_sendCapture = 1'b1; - end - end - end - end - end - - always @(*) begin - jtag_wrapper_sendShift = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(!when_JtagTapInstructions_l183) begin - jtag_wrapper_sendShift = 1'b1; - end - end - end - end - - always @(*) begin - jtag_wrapper_sendUpdate = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_update) begin - jtag_wrapper_sendUpdate = 1'b1; - end - end - end - - assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); - assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); - always @(*) begin - jtag_wrapper_ctrl_tdo = 1'b0; - if(when_JtagTapInstructions_l209) begin - jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; - end - if(when_JtagTapInstructions_l209_1) begin - jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; - end - end - - assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; - assign jtag_wrapper_ctrl_enable = io_ctrl_enable; - assign jtag_wrapper_ctrl_capture = io_ctrl_capture; - assign jtag_wrapper_ctrl_shift = io_ctrl_shift; - assign jtag_wrapper_ctrl_update = io_ctrl_update; - assign jtag_wrapper_ctrl_reset = io_ctrl_reset; - assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; - assign jtag_writeArea_source_valid = jtag_writeArea_valid; - assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); - assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; - assign system_cmd_valid = flowCCByToggle_1_io_output_valid; - assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; - assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; - assign jtag_writeArea_ctrl_tdo = 1'b0; - assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); - assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_writeArea_ctrl_enable = 1'b1; - assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); - assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); - assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); - assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; - assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; - assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); - assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_readArea_ctrl_enable = 1'b1; - assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); - assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); - assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); - assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - system_rsp_valid <= 1'b0; - end - if(io_remote_rsp_fire) begin - system_rsp_valid <= 1'b1; - system_rsp_payload_error <= io_remote_rsp_payload_error; - system_rsp_payload_data <= io_remote_rsp_payload_data; - end - end - - always @(posedge jtagCtrl_tck) begin - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_capture) begin - jtag_wrapper_done <= 1'b0; - jtag_wrapper_counter <= 1'b0; - end - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); - jtag_wrapper_header <= jtag_wrapper_headerNext; - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_done <= 1'b1; - end - end - end - end - jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); - jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; - if(jtag_readArea_ctrl_enable) begin - if(jtag_readArea_ctrl_capture) begin - jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; - end - if(jtag_readArea_ctrl_shift) begin - jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); - end - end - end - - -endmodule - -module VexRiscv ( - output dBus_cmd_valid, - input dBus_cmd_ready, - output dBus_cmd_payload_wr, - output dBus_cmd_payload_uncached, - output [31:0] dBus_cmd_payload_address, - output [31:0] dBus_cmd_payload_data, - output [3:0] dBus_cmd_payload_mask, - output [2:0] dBus_cmd_payload_size, - output dBus_cmd_payload_last, - input dBus_rsp_valid, - input dBus_rsp_payload_last, - input [31:0] dBus_rsp_payload_data, - input dBus_rsp_payload_error, - input timerInterrupt, - input externalInterrupt, - input softwareInterrupt, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBus_cmd_valid, - input iBus_cmd_ready, - output reg [31:0] iBus_cmd_payload_address, - output [2:0] iBus_cmd_payload_size, - input iBus_rsp_valid, - input [31:0] iBus_rsp_payload_data, - input iBus_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset, - input debugCd_logic_outputReset -); - localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; - localparam ShiftCtrlEnum_SLL_1 = 2'd1; - localparam ShiftCtrlEnum_SRL_1 = 2'd2; - localparam ShiftCtrlEnum_SRA_1 = 2'd3; - localparam BranchCtrlEnum_INC = 2'd0; - localparam BranchCtrlEnum_B = 2'd1; - localparam BranchCtrlEnum_JAL = 2'd2; - localparam BranchCtrlEnum_JALR = 2'd3; - localparam EnvCtrlEnum_NONE = 2'd0; - localparam EnvCtrlEnum_XRET = 2'd1; - localparam EnvCtrlEnum_ECALL = 2'd2; - localparam EnvCtrlEnum_EBREAK = 2'd3; - localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; - localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; - localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; - localparam AluCtrlEnum_ADD_SUB = 2'd0; - localparam AluCtrlEnum_SLT_SLTU = 2'd1; - localparam AluCtrlEnum_BITWISE = 2'd2; - localparam Src2CtrlEnum_RS = 2'd0; - localparam Src2CtrlEnum_IMI = 2'd1; - localparam Src2CtrlEnum_IMS = 2'd2; - localparam Src2CtrlEnum_PC = 2'd3; - localparam Src1CtrlEnum_RS = 2'd0; - localparam Src1CtrlEnum_IMU = 2'd1; - localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; - localparam Src1CtrlEnum_URS1 = 2'd3; - - wire IBusCachedPlugin_cache_io_flush; - wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; - wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; - wire IBusCachedPlugin_cache_io_cpu_decode_isValid; - wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; - wire IBusCachedPlugin_cache_io_cpu_decode_isUser; - reg IBusCachedPlugin_cache_io_cpu_fill_valid; - wire dataCache_1_io_cpu_execute_isValid; - wire [31:0] dataCache_1_io_cpu_execute_address; - wire dataCache_1_io_cpu_memory_isValid; - reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; - reg dataCache_1_io_cpu_writeBack_isValid; - wire dataCache_1_io_cpu_writeBack_isUser; - wire [31:0] dataCache_1_io_cpu_writeBack_storeData; - wire [31:0] dataCache_1_io_cpu_writeBack_address; - wire dataCache_1_io_cpu_writeBack_fence_SW; - wire dataCache_1_io_cpu_writeBack_fence_SR; - wire dataCache_1_io_cpu_writeBack_fence_SO; - wire dataCache_1_io_cpu_writeBack_fence_SI; - wire dataCache_1_io_cpu_writeBack_fence_PW; - wire dataCache_1_io_cpu_writeBack_fence_PR; - wire dataCache_1_io_cpu_writeBack_fence_PO; - wire dataCache_1_io_cpu_writeBack_fence_PI; - wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; - wire dataCache_1_io_cpu_flush_valid; - wire dataCache_1_io_cpu_flush_payload_singleLine; - wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; - wire dataCache_1_io_mem_cmd_ready; - reg [31:0] _zz_RegFilePlugin_regFile_port0; - reg [31:0] _zz_RegFilePlugin_regFile_port1; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1_io_cpu_execute_haltIt; - wire dataCache_1_io_cpu_execute_refilling; - wire dataCache_1_io_cpu_memory_isWrite; - wire dataCache_1_io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1_io_cpu_writeBack_data; - wire dataCache_1_io_cpu_writeBack_mmuException; - wire dataCache_1_io_cpu_writeBack_unalignedAccess; - wire dataCache_1_io_cpu_writeBack_accessError; - wire dataCache_1_io_cpu_writeBack_isWrite; - wire dataCache_1_io_cpu_writeBack_keepMemRspData; - wire dataCache_1_io_cpu_writeBack_exclusiveOk; - wire dataCache_1_io_cpu_flush_ready; - wire dataCache_1_io_cpu_redo; - wire dataCache_1_io_mem_cmd_valid; - wire dataCache_1_io_mem_cmd_payload_wr; - wire dataCache_1_io_mem_cmd_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_size; - wire dataCache_1_io_mem_cmd_payload_last; - wire [51:0] _zz_memory_MUL_LOW; - wire [51:0] _zz_memory_MUL_LOW_1; - wire [51:0] _zz_memory_MUL_LOW_2; - wire [51:0] _zz_memory_MUL_LOW_3; - wire [32:0] _zz_memory_MUL_LOW_4; - wire [51:0] _zz_memory_MUL_LOW_5; - wire [49:0] _zz_memory_MUL_LOW_6; - wire [51:0] _zz_memory_MUL_LOW_7; - wire [49:0] _zz_memory_MUL_LOW_8; - wire [31:0] _zz_execute_SHIFT_RIGHT; - wire [32:0] _zz_execute_SHIFT_RIGHT_1; - wire [32:0] _zz_execute_SHIFT_RIGHT_2; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; - wire _zz_decode_LEGAL_INSTRUCTION_3; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; - wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; - wire _zz_decode_LEGAL_INSTRUCTION_9; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; - wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; - wire _zz_decode_LEGAL_INSTRUCTION_15; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; - wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; - wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; - reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; - wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; - wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; - wire [25:0] _zz_io_cpu_flush_payload_lineId; - wire [25:0] _zz_io_cpu_flush_payload_lineId_1; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; - wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; - wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; - wire _zz__zz_decode_BRANCH_CTRL_2_5; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; - wire _zz__zz_decode_BRANCH_CTRL_2_9; - wire _zz__zz_decode_BRANCH_CTRL_2_10; - wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; - wire _zz__zz_decode_BRANCH_CTRL_2_13; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; - wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; - wire _zz__zz_decode_BRANCH_CTRL_2_26; - wire _zz__zz_decode_BRANCH_CTRL_2_27; - wire _zz__zz_decode_BRANCH_CTRL_2_28; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; - wire _zz__zz_decode_BRANCH_CTRL_2_32; - wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; - wire _zz__zz_decode_BRANCH_CTRL_2_36; - wire _zz__zz_decode_BRANCH_CTRL_2_37; - wire _zz__zz_decode_BRANCH_CTRL_2_38; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; - wire _zz__zz_decode_BRANCH_CTRL_2_40; - wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; - wire _zz__zz_decode_BRANCH_CTRL_2_47; - wire _zz__zz_decode_BRANCH_CTRL_2_48; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; - wire _zz__zz_decode_BRANCH_CTRL_2_54; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; - wire _zz__zz_decode_BRANCH_CTRL_2_57; - wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; - wire _zz__zz_decode_BRANCH_CTRL_2_66; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; - wire _zz__zz_decode_BRANCH_CTRL_2_68; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; - wire _zz__zz_decode_BRANCH_CTRL_2_70; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; - wire _zz__zz_decode_BRANCH_CTRL_2_75; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; - wire _zz__zz_decode_BRANCH_CTRL_2_86; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; - wire _zz__zz_decode_BRANCH_CTRL_2_92; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; - wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; - wire _zz__zz_decode_BRANCH_CTRL_2_99; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; - wire _zz__zz_decode_BRANCH_CTRL_2_101; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; - wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; - wire _zz__zz_decode_BRANCH_CTRL_2_111; - wire _zz__zz_decode_BRANCH_CTRL_2_112; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; - wire _zz__zz_decode_BRANCH_CTRL_2_125; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; - wire _zz__zz_decode_BRANCH_CTRL_2_140; - wire _zz__zz_decode_BRANCH_CTRL_2_141; - wire _zz__zz_decode_BRANCH_CTRL_2_142; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; - wire _zz_RegFilePlugin_regFile_port; - wire _zz_decode_RegFilePlugin_rs1Data; - wire _zz_RegFilePlugin_regFile_port_1; - wire _zz_decode_RegFilePlugin_rs2Data; - wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; - wire [2:0] _zz__zz_decode_SRC1_1; - wire [4:0] _zz__zz_decode_SRC1_1_1; - wire [11:0] _zz__zz_decode_SRC2_4; - wire [31:0] _zz_execute_SrcPlugin_addSub; - wire [31:0] _zz_execute_SrcPlugin_addSub_1; - wire [31:0] _zz_execute_SrcPlugin_addSub_2; - wire [31:0] _zz_execute_SrcPlugin_addSub_3; - wire [31:0] _zz_execute_SrcPlugin_addSub_4; - wire [31:0] _zz_execute_SrcPlugin_addSub_5; - wire [31:0] _zz_execute_SrcPlugin_addSub_6; - wire [65:0] _zz_writeBack_MulPlugin_result; - wire [65:0] _zz_writeBack_MulPlugin_result_1; - wire [31:0] _zz__zz_decode_RS2_2; - wire [31:0] _zz__zz_decode_RS2_2_1; - wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; - wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; - wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; - wire _zz_when; - wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; - wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; - wire [51:0] memory_MUL_LOW; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire [33:0] execute_MUL_HL; - wire [33:0] execute_MUL_LH; - wire [31:0] execute_MUL_LL; - wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; - wire [31:0] memory_MEMORY_STORE_DATA_RF; - wire [31:0] execute_MEMORY_STORE_DATA_RF; - wire decode_DO_EBREAK; - wire decode_CSR_READ_OPCODE; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] decode_SRC2; - wire [31:0] decode_SRC1; - wire decode_SRC2_FORCE_ZERO; - wire [1:0] decode_BRANCH_CTRL; - wire [1:0] _zz_decode_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; - wire [1:0] _zz_execute_to_memory_ENV_CTRL; - wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; - wire [1:0] decode_ENV_CTRL; - wire [1:0] _zz_decode_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; - wire decode_IS_CSR; - wire decode_IS_RS2_SIGNED; - wire decode_IS_RS1_SIGNED; - wire decode_IS_DIV; - wire memory_IS_MUL; - wire decode_IS_MUL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; - wire [1:0] decode_SHIFT_CTRL; - wire [1:0] _zz_decode_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; - wire [1:0] decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_MANAGMENT; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [1:0] decode_ALU_CTRL; - wire [1:0] _zz_decode_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; - wire decode_MEMORY_FORCE_CONSTISTENCY; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [31:0] memory_PC; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] execute_PC; - wire [1:0] execute_BRANCH_CTRL; - wire [1:0] _zz_execute_BRANCH_CTRL; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire [1:0] memory_ENV_CTRL; - wire [1:0] _zz_memory_ENV_CTRL; - wire [1:0] execute_ENV_CTRL; - wire [1:0] _zz_execute_ENV_CTRL; - wire [1:0] writeBack_ENV_CTRL; - wire [1:0] _zz_writeBack_ENV_CTRL; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire execute_IS_MUL; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_decode_RS2; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_decode_RS2_1; - wire [1:0] memory_SHIFT_CTRL; - wire [1:0] _zz_memory_SHIFT_CTRL; - wire [1:0] execute_SHIFT_CTRL; - wire [1:0] _zz_execute_SHIFT_CTRL; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_decode_SRC2; - wire [31:0] _zz_decode_SRC2_1; - wire [1:0] decode_SRC2_CTRL; - wire [1:0] _zz_decode_SRC2_CTRL; - wire [31:0] _zz_decode_SRC1; - wire [1:0] decode_SRC1_CTRL; - wire [1:0] _zz_decode_SRC1_CTRL; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire [1:0] execute_ALU_CTRL; - wire [1:0] _zz_execute_ALU_CTRL; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire [1:0] execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_execute_ALU_BITWISE_CTRL; - wire [31:0] _zz_lastStageRegFileWrite_payload_address; - wire _zz_lastStageRegFileWrite_valid; - reg _zz_1; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire [1:0] _zz_decode_BRANCH_CTRL_1; - wire [1:0] _zz_decode_ENV_CTRL_1; - wire [1:0] _zz_decode_SHIFT_CTRL_1; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; - wire [1:0] _zz_decode_SRC2_CTRL_1; - wire [1:0] _zz_decode_ALU_CTRL_1; - wire [1:0] _zz_decode_SRC1_CTRL_1; - reg [31:0] _zz_decode_RS2_2; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_MEMORY_STORE_DATA_RF; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire memory_MEMORY_ENABLE; - wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; - wire execute_MEMORY_FORCE_CONSTISTENCY; - (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_MANAGMENT; - (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected_4; - reg IBusCachedPlugin_rsp_issueDetected_3; - reg IBusCachedPlugin_rsp_issueDetected_2; - reg IBusCachedPlugin_rsp_issueDetected_1; - reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; - wire [31:0] decode_PC; - wire [31:0] decode_INSTRUCTION; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - wire IBusCachedPlugin_forceNoDecodeCond; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_0_isValid; - wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_isPaging; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_0_isValid; - wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_isPaging; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_when_DBusCachedPlugin_l393; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire [31:0] CsrPlugin_csrMapping_readDataSignal; - wire [31:0] CsrPlugin_csrMapping_readDataInit; - wire [31:0] CsrPlugin_csrMapping_writeDataSignal; - wire CsrPlugin_csrMapping_allowCsrSignal; - wire CsrPlugin_csrMapping_hazardFree; - wire CsrPlugin_inWfi /* verilator public */ ; - reg CsrPlugin_thirdPartyWake; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg CsrPlugin_allowEbreakException; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg BranchPlugin_inDebugNoFetchFlag; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_externalFlush; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_correction; - reg IBusCachedPlugin_fetchPc_correctionReg; - wire IBusCachedPlugin_fetchPc_output_fire; - wire IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - wire when_Fetcher_l134; - wire IBusCachedPlugin_fetchPc_output_fire_1; - wire when_Fetcher_l134_1; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_fetchPc_redo_valid; - wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; - reg IBusCachedPlugin_fetchPc_flushed; - wire when_Fetcher_l161; - reg IBusCachedPlugin_iBusRsp_redoFetch; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_output_valid; - wire IBusCachedPlugin_iBusRsp_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; - wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; - wire when_Fetcher_l243; - wire IBusCachedPlugin_injector_decodeInput_valid; - wire IBusCachedPlugin_injector_decodeInput_ready; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; - wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_IBusCachedPlugin_injector_decodeInput_valid; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - wire when_Fetcher_l323; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - wire when_Fetcher_l332; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - wire when_Fetcher_l332_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - wire when_Fetcher_l332_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - wire when_Fetcher_l332_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire when_Fetcher_l332_4; - reg IBusCachedPlugin_injector_nextPcCalc_valids_5; - wire when_Fetcher_l332_5; - reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - wire IBusCachedPlugin_rsp_issueDetected; - reg IBusCachedPlugin_rsp_redoFetch; - wire when_IBusCachedPlugin_l239; - wire when_IBusCachedPlugin_l244; - wire when_IBusCachedPlugin_l250; - wire when_IBusCachedPlugin_l256; - wire when_IBusCachedPlugin_l267; - wire dataCache_1_io_mem_cmd_s2mPipe_valid; - reg dataCache_1_io_mem_cmd_s2mPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_rValid; - reg dataCache_1_io_mem_cmd_rData_wr; - reg dataCache_1_io_mem_cmd_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_rData_size; - reg dataCache_1_io_mem_cmd_rData_last; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; - wire when_Stream_l368; - reg dBus_rsp_regNext_valid; - reg dBus_rsp_regNext_payload_last; - reg [31:0] dBus_rsp_regNext_payload_data; - reg dBus_rsp_regNext_payload_error; - reg [31:0] DBusCachedPlugin_rspCounter; - wire when_DBusCachedPlugin_l308; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; - wire dataCache_1_io_cpu_flush_isStall; - wire when_DBusCachedPlugin_l350; - wire when_DBusCachedPlugin_l366; - wire when_DBusCachedPlugin_l393; - wire when_DBusCachedPlugin_l446; - wire when_DBusCachedPlugin_l466; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire [31:0] writeBack_DBusCachedPlugin_rspRf; - wire [1:0] switch_Misc_l210; - wire _zz_writeBack_DBusCachedPlugin_rspFormated; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; - wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire when_DBusCachedPlugin_l492; - wire [32:0] _zz_decode_BRANCH_CTRL_2; - wire _zz_decode_BRANCH_CTRL_3; - wire _zz_decode_BRANCH_CTRL_4; - wire _zz_decode_BRANCH_CTRL_5; - wire _zz_decode_BRANCH_CTRL_6; - wire _zz_decode_BRANCH_CTRL_7; - wire _zz_decode_BRANCH_CTRL_8; - wire [1:0] _zz_decode_SRC1_CTRL_2; - wire [1:0] _zz_decode_ALU_CTRL_2; - wire [1:0] _zz_decode_SRC2_CTRL_2; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; - wire [1:0] _zz_decode_SHIFT_CTRL_2; - wire [1:0] _zz_decode_ENV_CTRL_2; - wire [1:0] _zz_decode_BRANCH_CTRL_9; - wire when_RegFilePlugin_l63; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_2; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_execute_REGFILE_WRITE_DATA; - reg [31:0] _zz_decode_SRC1_1; - wire _zz_decode_SRC2_2; - reg [19:0] _zz_decode_SRC2_3; - wire _zz_decode_SRC2_4; - reg [19:0] _zz_decode_SRC2_5; - reg [31:0] _zz_decode_SRC2_6; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_decode_RS2_3; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire when_HazardSimplePlugin_l47; - wire when_HazardSimplePlugin_l48; - wire when_HazardSimplePlugin_l51; - wire when_HazardSimplePlugin_l45; - wire when_HazardSimplePlugin_l57; - wire when_HazardSimplePlugin_l58; - wire when_HazardSimplePlugin_l48_1; - wire when_HazardSimplePlugin_l51_1; - wire when_HazardSimplePlugin_l45_1; - wire when_HazardSimplePlugin_l57_1; - wire when_HazardSimplePlugin_l58_1; - wire when_HazardSimplePlugin_l48_2; - wire when_HazardSimplePlugin_l51_2; - wire when_HazardSimplePlugin_l45_2; - wire when_HazardSimplePlugin_l57_2; - wire when_HazardSimplePlugin_l58_2; - wire when_HazardSimplePlugin_l105; - wire when_HazardSimplePlugin_l108; - wire when_HazardSimplePlugin_l113; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - reg [0:0] execute_MulPlugin_delayLogic_counter; - wire when_MulPlugin_l65; - wire when_MulPlugin_l70; - wire [1:0] switch_MulPlugin_l87; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; - wire [65:0] writeBack_MulPlugin_result; - wire when_MulPlugin_l147; - wire [1:0] switch_MulPlugin_l148; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - wire when_MulDivIterativePlugin_l126; - wire when_MulDivIterativePlugin_l126_1; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l128; - wire when_MulDivIterativePlugin_l129; - wire when_MulDivIterativePlugin_l132; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire when_MulDivIterativePlugin_l151; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l162; - wire _zz_memory_MulDivIterativePlugin_rs2; - wire _zz_memory_MulDivIterativePlugin_rs1; - reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle; - reg [63:0] CsrPlugin_minstret; - wire _zz_when_CsrPlugin_l965; - wire _zz_when_CsrPlugin_l965_1; - wire _zz_when_CsrPlugin_l965_2; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; - wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire when_CsrPlugin_l922; - wire when_CsrPlugin_l922_1; - wire when_CsrPlugin_l922_2; - wire when_CsrPlugin_l922_3; - wire when_CsrPlugin_l935; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire when_CsrPlugin_l959; - wire when_CsrPlugin_l965; - wire when_CsrPlugin_l965_1; - wire when_CsrPlugin_l965_2; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_pcValids_0; - reg CsrPlugin_pipelineLiberator_pcValids_1; - reg CsrPlugin_pipelineLiberator_pcValids_2; - wire CsrPlugin_pipelineLiberator_active; - wire when_CsrPlugin_l993; - wire when_CsrPlugin_l993_1; - wire when_CsrPlugin_l993_2; - wire when_CsrPlugin_l998; - reg CsrPlugin_pipelineLiberator_done; - wire when_CsrPlugin_l1004; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException /* verilator public */ ; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire when_CsrPlugin_l1032; - wire when_CsrPlugin_l1077; - wire [1:0] switch_CsrPlugin_l1081; - reg execute_CsrPlugin_wfiWake; - wire when_CsrPlugin_l1129; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - wire when_CsrPlugin_l1142; - wire when_CsrPlugin_l1149; - wire when_CsrPlugin_l1150; - wire when_CsrPlugin_l1157; - wire when_CsrPlugin_l1167; - reg execute_CsrPlugin_writeInstruction; - reg execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - wire switch_Misc_l210_1; - reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; - wire when_CsrPlugin_l1189; - wire when_CsrPlugin_l1193; - wire [11:0] execute_CsrPlugin_csrAddress; - wire execute_BranchPlugin_eq; - wire [2:0] switch_Misc_l210_2; - reg _zz_execute_BRANCH_DO; - reg _zz_execute_BRANCH_DO_1; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_execute_BranchPlugin_branch_src2; - reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; - wire _zz_execute_BranchPlugin_branch_src2_2; - reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; - wire _zz_execute_BranchPlugin_branch_src2_4; - reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; - reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - wire when_DebugPlugin_l225; - reg DebugPlugin_haltedByBreak; - reg DebugPlugin_debugUsed /* verilator public */ ; - reg DebugPlugin_disableEbreak; - wire DebugPlugin_allowEBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_when_DebugPlugin_l244; - wire when_DebugPlugin_l244; - wire [5:0] switch_DebugPlugin_l267; - wire when_DebugPlugin_l271; - wire when_DebugPlugin_l271_1; - wire when_DebugPlugin_l272; - wire when_DebugPlugin_l272_1; - wire when_DebugPlugin_l273; - wire when_DebugPlugin_l274; - wire when_DebugPlugin_l275; - wire when_DebugPlugin_l275_1; - wire when_DebugPlugin_l295; - wire when_DebugPlugin_l298; - wire when_DebugPlugin_l311; - reg DebugPlugin_resetIt_regNext; - wire when_DebugPlugin_l331; - wire when_Pipeline_l124; - reg [31:0] decode_to_execute_PC; - wire when_Pipeline_l124_1; - reg [31:0] execute_to_memory_PC; - wire when_Pipeline_l124_2; - reg [31:0] memory_to_writeBack_PC; - wire when_Pipeline_l124_3; - reg [31:0] decode_to_execute_INSTRUCTION; - wire when_Pipeline_l124_4; - reg [31:0] execute_to_memory_INSTRUCTION; - wire when_Pipeline_l124_5; - reg [31:0] memory_to_writeBack_INSTRUCTION; - wire when_Pipeline_l124_6; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - wire when_Pipeline_l124_7; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - wire when_Pipeline_l124_8; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - wire when_Pipeline_l124_9; - reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - wire when_Pipeline_l124_10; - reg decode_to_execute_SRC_USE_SUB_LESS; - wire when_Pipeline_l124_11; - reg decode_to_execute_MEMORY_ENABLE; - wire when_Pipeline_l124_12; - reg execute_to_memory_MEMORY_ENABLE; - wire when_Pipeline_l124_13; - reg memory_to_writeBack_MEMORY_ENABLE; - wire when_Pipeline_l124_14; - reg [1:0] decode_to_execute_ALU_CTRL; - wire when_Pipeline_l124_15; - reg decode_to_execute_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_16; - reg execute_to_memory_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_17; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_18; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - wire when_Pipeline_l124_19; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_20; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_21; - reg decode_to_execute_MEMORY_WR; - wire when_Pipeline_l124_22; - reg execute_to_memory_MEMORY_WR; - wire when_Pipeline_l124_23; - reg memory_to_writeBack_MEMORY_WR; - wire when_Pipeline_l124_24; - reg decode_to_execute_MEMORY_MANAGMENT; - wire when_Pipeline_l124_25; - reg decode_to_execute_SRC_LESS_UNSIGNED; - wire when_Pipeline_l124_26; - reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; - wire when_Pipeline_l124_27; - reg [1:0] decode_to_execute_SHIFT_CTRL; - wire when_Pipeline_l124_28; - reg [1:0] execute_to_memory_SHIFT_CTRL; - wire when_Pipeline_l124_29; - reg decode_to_execute_IS_MUL; - wire when_Pipeline_l124_30; - reg execute_to_memory_IS_MUL; - wire when_Pipeline_l124_31; - reg memory_to_writeBack_IS_MUL; - wire when_Pipeline_l124_32; - reg decode_to_execute_IS_DIV; - wire when_Pipeline_l124_33; - reg execute_to_memory_IS_DIV; - wire when_Pipeline_l124_34; - reg decode_to_execute_IS_RS1_SIGNED; - wire when_Pipeline_l124_35; - reg decode_to_execute_IS_RS2_SIGNED; - wire when_Pipeline_l124_36; - reg decode_to_execute_IS_CSR; - wire when_Pipeline_l124_37; - reg [1:0] decode_to_execute_ENV_CTRL; - wire when_Pipeline_l124_38; - reg [1:0] execute_to_memory_ENV_CTRL; - wire when_Pipeline_l124_39; - reg [1:0] memory_to_writeBack_ENV_CTRL; - wire when_Pipeline_l124_40; - reg [1:0] decode_to_execute_BRANCH_CTRL; - wire when_Pipeline_l124_41; - reg [31:0] decode_to_execute_RS1; - wire when_Pipeline_l124_42; - reg [31:0] decode_to_execute_RS2; - wire when_Pipeline_l124_43; - reg decode_to_execute_SRC2_FORCE_ZERO; - wire when_Pipeline_l124_44; - reg [31:0] decode_to_execute_SRC1; - wire when_Pipeline_l124_45; - reg [31:0] decode_to_execute_SRC2; - wire when_Pipeline_l124_46; - reg decode_to_execute_CSR_WRITE_OPCODE; - wire when_Pipeline_l124_47; - reg decode_to_execute_CSR_READ_OPCODE; - wire when_Pipeline_l124_48; - reg decode_to_execute_DO_EBREAK; - wire when_Pipeline_l124_49; - reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_50; - reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_51; - (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; - wire when_Pipeline_l124_52; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_53; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_54; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - wire when_Pipeline_l124_55; - reg [31:0] execute_to_memory_MUL_LL; - wire when_Pipeline_l124_56; - reg [33:0] execute_to_memory_MUL_LH; - wire when_Pipeline_l124_57; - reg [33:0] execute_to_memory_MUL_HL; - wire when_Pipeline_l124_58; - reg [33:0] execute_to_memory_MUL_HH; - wire when_Pipeline_l124_59; - reg [33:0] memory_to_writeBack_MUL_HH; - wire when_Pipeline_l124_60; - reg execute_to_memory_BRANCH_DO; - wire when_Pipeline_l124_61; - reg [31:0] execute_to_memory_BRANCH_CALC; - wire when_Pipeline_l124_62; - reg [51:0] memory_to_writeBack_MUL_LOW; - wire when_Pipeline_l151; - wire when_Pipeline_l154; - wire when_Pipeline_l151_1; - wire when_Pipeline_l154_1; - wire when_Pipeline_l151_2; - wire when_Pipeline_l154_2; - reg [2:0] switch_Fetcher_l365; - wire when_Fetcher_l381; - wire when_Fetcher_l401; - wire when_CsrPlugin_l1277; - reg execute_CsrPlugin_csr_3860; - wire when_CsrPlugin_l1277_1; - reg execute_CsrPlugin_csr_769; - wire when_CsrPlugin_l1277_2; - reg execute_CsrPlugin_csr_768; - wire when_CsrPlugin_l1277_3; - reg execute_CsrPlugin_csr_836; - wire when_CsrPlugin_l1277_4; - reg execute_CsrPlugin_csr_772; - wire when_CsrPlugin_l1277_5; - reg execute_CsrPlugin_csr_773; - wire when_CsrPlugin_l1277_6; - reg execute_CsrPlugin_csr_833; - wire when_CsrPlugin_l1277_7; - reg execute_CsrPlugin_csr_832; - wire when_CsrPlugin_l1277_8; - reg execute_CsrPlugin_csr_834; - wire when_CsrPlugin_l1277_9; - reg execute_CsrPlugin_csr_835; - wire [1:0] switch_CsrPlugin_l723; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; - wire when_CsrPlugin_l1310; - wire when_CsrPlugin_l1315; - `ifndef SYNTHESIS - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; - reg [47:0] decode_ENV_CTRL_string; - reg [47:0] _zz_decode_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_decode_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_execute_BRANCH_CTRL_string; - reg [47:0] memory_ENV_CTRL_string; - reg [47:0] _zz_memory_ENV_CTRL_string; - reg [47:0] execute_ENV_CTRL_string; - reg [47:0] _zz_execute_ENV_CTRL_string; - reg [47:0] writeBack_ENV_CTRL_string; - reg [47:0] _zz_writeBack_ENV_CTRL_string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_memory_SHIFT_CTRL_string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_execute_SHIFT_CTRL_string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_decode_SRC2_CTRL_string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_decode_SRC1_CTRL_string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_execute_ALU_CTRL_string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_1_string; - reg [47:0] _zz_decode_ENV_CTRL_1_string; - reg [71:0] _zz_decode_SHIFT_CTRL_1_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; - reg [23:0] _zz_decode_SRC2_CTRL_1_string; - reg [63:0] _zz_decode_ALU_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_2_string; - reg [63:0] _zz_decode_ALU_CTRL_2_string; - reg [23:0] _zz_decode_SRC2_CTRL_2_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; - reg [71:0] _zz_decode_SHIFT_CTRL_2_string; - reg [47:0] _zz_decode_ENV_CTRL_2_string; - reg [31:0] _zz_decode_BRANCH_CTRL_9_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [47:0] decode_to_execute_ENV_CTRL_string; - reg [47:0] execute_to_memory_ENV_CTRL_string; - reg [47:0] memory_to_writeBack_ENV_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - `endif - - reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - - assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); - assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); - assign _zz_memory_MUL_LOW_2 = 52'h0; - assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; - assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; - assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; - assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; - assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; - assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); - assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; - assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; - assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; - assign _zz__zz_decode_SRC1_1 = 3'b100; - assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; - assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); - assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); - assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; - assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); - assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; - assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; - assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; - assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; - assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; - assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); - assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; - assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; - assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; - assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; - assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); - assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; - assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; - assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; - assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; - assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; - assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; - assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; - assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; - assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); - assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); - assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); - assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; - assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; - assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); - assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); - assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; - assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); - assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; - assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); - assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); - assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; - assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); - assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); - assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; - assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; - assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); - assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; - assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; - assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); - assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); - assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; - assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); - assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; - assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); - assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); - assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); - assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); - assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); - assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; - assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); - assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); - assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; - assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); - assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; - assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); - assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; - assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; - assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; - assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; - assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); - assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); - assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; - assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; - assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); - assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; - assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); - assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); - assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); - assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); - assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; - assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; - assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); - assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); - assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); - assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); - assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; - assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; - assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; - assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; - assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); - assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; - assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); - assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; - assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); - assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; - assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); - assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; - assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); - assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); - assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; - assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; - assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; - assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); - assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; - assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; - assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; - assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); - assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); - assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; - assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); - assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; - assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); - assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; - assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; - assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); - assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); - assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; - assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); - assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); - assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs1Data) begin - _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs2Data) begin - _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush (IBusCachedPlugin_cache_io_flush ), //i - .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i - .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i - .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i - .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i - .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - DataCache dataCache_1 ( - .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i - .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i - .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i - .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i - .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i - .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i - .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i - .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i - .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i - .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i - .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i - .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i - .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i - .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) - 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; - 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; - default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) - 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; - 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; - 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; - default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) - 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; - default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - `ifndef SYNTHESIS - always @(*) begin - case(decode_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; - default : decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; - default : memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; - default : execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; - default : writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; - default : _zz_decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_1) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; - default : _zz_decode_SRC2_CTRL_1_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_1) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_1_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_2) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_2_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_2) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_2_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_2) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; - default : _zz_decode_SRC2_CTRL_2_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_2) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_2) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_2) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_2_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_9) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_9_string = "????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - `endif - - assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; - assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; - assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; - assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; - assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; - assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; - assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; - assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; - assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); - assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); - assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); - assign decode_SRC2 = _zz_decode_SRC2_6; - assign decode_SRC1 = _zz_decode_SRC1_1; - assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; - assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; - assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; - assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; - assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; - assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; - assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; - assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; - assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; - assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; - assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; - assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; - assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; - assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; - assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; - assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign memory_PC = execute_to_memory_PC; - assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; - assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; - assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; - assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; - assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; - assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; - assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; - assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; - assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; - assign memory_MUL_HL = execute_to_memory_MUL_HL; - assign memory_MUL_LH = execute_to_memory_MUL_LH; - assign memory_MUL_LL = execute_to_memory_MUL_LL; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; - assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; - always @(*) begin - _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; - if(when_CsrPlugin_l1189) begin - _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; - end - end - - assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @(*) begin - decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr1Match) begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l51) begin - decode_RS2 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l51_1) begin - decode_RS2 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l51_2) begin - decode_RS2 = _zz_decode_RS2; - end - end - end - end - - always @(*) begin - decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr0Match) begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l48) begin - decode_RS1 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l48_1) begin - decode_RS1 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l48_2) begin - decode_RS1 = _zz_decode_RS2; - end - end - end - end - - assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @(*) begin - _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_SLL_1 : begin - _zz_decode_RS2_1 = _zz_decode_RS2_3; - end - ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin - _zz_decode_RS2_1 = memory_SHIFT_RIGHT; - end - default : begin - end - endcase - end - if(when_MulDivIterativePlugin_l128) begin - _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; - end - end - - assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; - assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; - assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; - assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; - assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_decode_SRC2 = decode_PC; - assign _zz_decode_SRC2_1 = decode_RS2; - assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; - assign _zz_decode_SRC1 = decode_RS1; - assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; - assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; - assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; - assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; - assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; - assign execute_SRC2 = decode_to_execute_SRC2; - assign execute_SRC1 = decode_to_execute_SRC1; - assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; - assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; - assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; - always @(*) begin - _zz_1 = 1'b0; - if(lastStageRegFileWrite_valid) begin - _zz_1 = 1'b1; - end - end - - assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); - always @(*) begin - decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; - if(when_RegFilePlugin_l63) begin - decode_REGFILE_WRITE_VALID = 1'b0; - end - end - - assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); - always @(*) begin - _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; - if(when_DBusCachedPlugin_l492) begin - _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; - end - if(when_MulPlugin_l147) begin - case(switch_MulPlugin_l148) - 2'b00 : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; - end - default : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; - end - endcase - end - end - - assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; - assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; - assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - assign execute_RS1 = decode_to_execute_RS1; - assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; - assign execute_RS2 = decode_to_execute_RS2; - assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = execute_SrcPlugin_addSub; - assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; - assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; - end - end - - always @(*) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; - end - end - - assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; - assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @(*) begin - decode_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l308) begin - decode_arbitration_haltItself = 1'b1; - end - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_haltItself = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - decode_arbitration_haltByOther = 1'b0; - if(when_HazardSimplePlugin_l113) begin - decode_arbitration_haltByOther = 1'b1; - end - if(CsrPlugin_pipelineLiberator_active) begin - decode_arbitration_haltByOther = 1'b1; - end - if(when_CsrPlugin_l1129) begin - decode_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - decode_arbitration_removeIt = 1'b0; - if(_zz_when) begin - decode_arbitration_removeIt = 1'b1; - end - if(decode_arbitration_isFlushed) begin - decode_arbitration_removeIt = 1'b1; - end - end - - assign decode_arbitration_flushIt = 1'b0; - always @(*) begin - decode_arbitration_flushNext = 1'b0; - if(_zz_when) begin - decode_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - execute_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l350) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_MulPlugin_l65) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_CsrPlugin_l1193) begin - if(execute_CsrPlugin_blockedBySideEffects) begin - execute_arbitration_haltItself = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_haltByOther = 1'b0; - if(when_DBusCachedPlugin_l366) begin - execute_arbitration_haltByOther = 1'b1; - end - if(when_DebugPlugin_l295) begin - execute_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_removeIt = 1'b1; - end - if(execute_arbitration_isFlushed) begin - execute_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - execute_arbitration_flushIt = 1'b0; - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushIt = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_flushNext = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushNext = 1'b1; - end - end - end - - always @(*) begin - memory_arbitration_haltItself = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l129) begin - memory_arbitration_haltItself = 1'b1; - end - end - end - - assign memory_arbitration_haltByOther = 1'b0; - always @(*) begin - memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed) begin - memory_arbitration_removeIt = 1'b1; - end - end - - assign memory_arbitration_flushIt = 1'b0; - always @(*) begin - memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid) begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l466) begin - writeBack_arbitration_haltItself = 1'b1; - end - end - - assign writeBack_arbitration_haltByOther = 1'b0; - always @(*) begin - writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_removeIt = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - writeBack_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1032) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1077) begin - writeBack_arbitration_flushNext = 1'b1; - end - end - - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @(*) begin - IBusCachedPlugin_fetcherHalt = 1'b0; - if(when_CsrPlugin_l935) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1032) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1077) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - if(DebugPlugin_haltIt) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l311) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - - assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; - always @(*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if(when_Fetcher_l243) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - end - - always @(*) begin - _zz_when_DBusCachedPlugin_l393 = 1'b0; - if(DebugPlugin_godmode) begin - _zz_when_DBusCachedPlugin_l393 = 1'b1; - end - end - - assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; - assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; - assign CsrPlugin_inWfi = 1'b0; - always @(*) begin - CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt) begin - CsrPlugin_thirdPartyWake = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_valid = 1'b0; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - if(when_CsrPlugin_l1077) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; - end - default : begin - end - endcase - end - end - - always @(*) begin - CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode) begin - CsrPlugin_forceMachineWire = 1'b1; - end - end - - always @(*) begin - CsrPlugin_allowInterrupts = 1'b1; - if(when_DebugPlugin_l331) begin - CsrPlugin_allowInterrupts = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode) begin - CsrPlugin_allowException = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowEbreakException = 1'b1; - if(DebugPlugin_allowEBreak) begin - CsrPlugin_allowEbreakException = 1'b0; - end - end - - always @(*) begin - BranchPlugin_inDebugNoFetchFlag = 1'b0; - if(DebugPlugin_godmode) begin - BranchPlugin_inDebugNoFetchFlag = 1'b1; - end - end - - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - always @(*) begin - IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - end - - assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @(*) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; - end - end - - assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); - assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); - always @(*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; - end - IBusCachedPlugin_fetchPc_pc[0] = 1'b0; - IBusCachedPlugin_fetchPc_pc[1] = 1'b0; - end - - always @(*) begin - IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - end - - assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); - assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); - assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @(*) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; - end - end - - assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; - assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if(when_IBusCachedPlugin_l267) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; - assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - if(when_Fetcher_l323) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - end - - assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); - assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); - assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); - assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); - assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); - assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); - assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); - assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); - assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; - assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; - assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; - assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - always @(*) begin - decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_isValid = 1'b1; - end - 3'b011 : begin - decode_arbitration_isValid = 1'b1; - end - default : begin - end - endcase - if(IBusCachedPlugin_forceNoDecodeCond) begin - decode_arbitration_isValid = 1'b0; - end - end - - assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @(*) begin - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - end - - assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; - assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; - assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); - assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; - assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @(*) begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; - assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); - assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; - assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; - assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); - always @(*) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; - assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); - assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; - always @(*) begin - case(execute_DBusCachedPlugin_size) - 2'b00 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; - end - 2'b01 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; - end - default : begin - _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; - end - endcase - end - - assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); - assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; - assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); - assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); - assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); - assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; - assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; - assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @(*) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if(when_DBusCachedPlugin_l393) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; - end - end - - assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); - always @(*) begin - dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - if(writeBack_arbitration_haltByOther) begin - dataCache_1_io_cpu_writeBack_isValid = 1'b0; - end - end - - assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); - assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; - assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; - always @(*) begin - DBusCachedPlugin_redoBranch_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_redoBranch_valid = 1'b1; - end - end - end - - assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @(*) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - end - end - end - - assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @(*) begin - DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; - end - end - end - - assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); - assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; - assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; - assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; - assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; - always @(*) begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; - writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; - writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; - writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; - end - - assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; - assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; - end - - assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; - end - - always @(*) begin - case(switch_Misc_l210) - 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; - end - 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; - end - default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; - end - endcase - end - - assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); - assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); - assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; - assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; - assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; - assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; - assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; - assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; - assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; - assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; - assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; - assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; - assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; - assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; - assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; - assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; - assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; - assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = 4'b0010; - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; - assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); - assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; - assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; - assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; - always @(*) begin - lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - if(_zz_2) begin - lastStageRegFileWrite_valid = 1'b1; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - if(_zz_2) begin - lastStageRegFileWrite_payload_address = 5'h0; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; - if(_zz_2) begin - lastStageRegFileWrite_payload_data = 32'h0; - end - end - - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_AND_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); - end - AluBitwiseCtrlEnum_OR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); - end - default : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); - end - endcase - end - - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_BITWISE : begin - _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; - end - AluCtrlEnum_SLT_SLTU : begin - _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; - end - default : begin - _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; - end - endcase - end - - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : begin - _zz_decode_SRC1_1 = _zz_decode_SRC1; - end - Src1CtrlEnum_PC_INCREMENT : begin - _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; - end - Src1CtrlEnum_IMU : begin - _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; - end - default : begin - _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; - end - endcase - end - - assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; - always @(*) begin - _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; - end - - assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; - always @(*) begin - _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; - end - - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2_1; - end - Src2CtrlEnum_IMI : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; - end - Src2CtrlEnum_IMS : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; - end - default : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2; - end - endcase - end - - always @(*) begin - execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; - if(execute_SRC2_FORCE_ZERO) begin - execute_SrcPlugin_addSub = execute_SRC1; - end - end - - assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @(*) begin - _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; - _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; - _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; - _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; - _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; - _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; - _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; - _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; - _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; - _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; - _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; - _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; - _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; - _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; - _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; - _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; - _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; - _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; - _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; - _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; - _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; - _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; - _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; - _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; - _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; - _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; - _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; - _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; - _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; - _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; - _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; - _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); - always @(*) begin - _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; - _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; - _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; - _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; - _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; - _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; - _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; - _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; - _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; - _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; - _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; - _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; - _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; - _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; - _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; - _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; - _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; - _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; - _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; - _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; - _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; - _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; - _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; - _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; - _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; - _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; - _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; - _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; - _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; - _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; - _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; - _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; - end - - always @(*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l48) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l48_1) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l48_2) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l105) begin - HazardSimplePlugin_src0Hazard = 1'b0; - end - end - - always @(*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l51) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l51_1) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l51_2) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l108) begin - HazardSimplePlugin_src1Hazard = 1'b0; - end - end - - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l47 = 1'b1; - assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); - assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); - assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); - assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); - assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); - assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); - assign execute_MulPlugin_a = execute_RS1; - assign execute_MulPlugin_b = execute_RS2; - assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_aSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_aSigned = 1'b1; - end - default : begin - execute_MulPlugin_aSigned = 1'b0; - end - endcase - end - - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_bSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_bSigned = 1'b0; - end - default : begin - execute_MulPlugin_bSigned = 1'b0; - end - endcase - end - - assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; - assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; - assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; - assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; - assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; - assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); - assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); - assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; - end - end - end - - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; - end - end - - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); - assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); - always @(*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); - end - if(memory_MulDivIterativePlugin_div_counter_willClear) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end - end - - assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); - assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); - assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); - assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; - assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); - assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @(*) begin - _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; - end - - always @(*) begin - CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire) begin - CsrPlugin_privilege = 2'b11; - end - end - - assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; - end - if(decode_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; - end - if(execute_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; - end - end - - assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); - assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); - assign CsrPlugin_lastStageWasWfi = 1'b0; - assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); - always @(*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(when_CsrPlugin_l1004) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - if(CsrPlugin_hadException) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - end - - assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); - assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @(*) begin - CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException) begin - CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - end - end - - always @(*) begin - CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException) begin - CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; - end - end - - always @(*) begin - CsrPlugin_xtvec_mode = 2'bxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; - end - default : begin - end - endcase - end - - always @(*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; - end - default : begin - end - endcase - end - - assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); - assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; - assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); - assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); - always @(*) begin - execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3860) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_769) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_768) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_836) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_772) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_773) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_833) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_832) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_834) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_835) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(CsrPlugin_csrMapping_allowCsrSignal) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_illegalAccess = 1'b1; - end - if(when_CsrPlugin_l1315) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_illegalInstruction = 1'b0; - if(when_CsrPlugin_l1149) begin - if(when_CsrPlugin_l1150) begin - execute_CsrPlugin_illegalInstruction = 1'b1; - end - end - end - - always @(*) begin - CsrPlugin_selfException_valid = 1'b0; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1157) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_selfException_payload_code = 4'bxxxx; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_payload_code = 4'b0010; - end - if(when_CsrPlugin_l1157) begin - case(CsrPlugin_privilege) - 2'b00 : begin - CsrPlugin_selfException_payload_code = 4'b1000; - end - default : begin - CsrPlugin_selfException_payload_code = 4'b1011; - end - endcase - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_payload_code = 4'b0011; - end - end - - assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); - assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); - assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); - assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); - always @(*) begin - execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_writeInstruction = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_readInstruction = 1'b0; - end - end - - assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); - assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; - assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; - always @(*) begin - case(switch_Misc_l210_1) - 1'b0 : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; - end - default : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); - end - endcase - end - - assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; - assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); - assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); - assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; - always @(*) begin - casez(switch_Misc_l210_2) - 3'b000 : begin - _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; - end - 3'b001 : begin - _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); - end - 3'b1?1 : begin - _zz_execute_BRANCH_DO = (! execute_SRC_LESS); - end - default : begin - _zz_execute_BRANCH_DO = execute_SRC_LESS; - end - endcase - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : begin - _zz_execute_BRANCH_DO_1 = 1'b0; - end - BranchCtrlEnum_JAL : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - default : begin - _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; - end - endcase - end - - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); - assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; - end - - assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; - end - - assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_JAL : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; - end - default : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - end - endcase - end - - assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); - assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); - always @(*) begin - debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; - end - end - default : begin - end - endcase - end - end - - always @(*) begin - debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if(when_DebugPlugin_l244) begin - debug_bus_rsp_data[0] = DebugPlugin_resetIt; - debug_bus_rsp_data[1] = DebugPlugin_haltIt; - debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; - debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; - debug_bus_rsp_data[4] = DebugPlugin_stepIt; - end - end - - assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); - always @(*) begin - IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - IBusCachedPlugin_injectionPort_valid = 1'b1; - end - end - default : begin - end - endcase - end - end - - assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; - assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; - assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; - assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; - assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; - assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; - assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); - assign when_Pipeline_l124 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); - assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); - assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; - assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; - assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; - assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; - assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; - assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; - assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; - assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; - assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; - assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; - assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); - assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; - assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); - assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; - assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; - assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; - assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; - assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; - assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); - assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; - assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); - assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; - assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); - assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; - assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; - assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); - assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; - assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); - assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); - assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); - assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - always @(*) begin - IBusCachedPlugin_injectionPort_ready = 1'b0; - case(switch_Fetcher_l365) - 3'b100 : begin - IBusCachedPlugin_injectionPort_ready = 1'b1; - end - default : begin - end - endcase - end - - assign when_Fetcher_l381 = (! decode_arbitration_isStuck); - assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); - assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); - assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; - if(execute_CsrPlugin_csr_768) begin - _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; - if(execute_CsrPlugin_csr_836) begin - _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; - if(execute_CsrPlugin_csr_772) begin - _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; - if(execute_CsrPlugin_csr_773) begin - _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; - _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; - if(execute_CsrPlugin_csr_833) begin - _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; - if(execute_CsrPlugin_csr_832) begin - _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; - if(execute_CsrPlugin_csr_834) begin - _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; - if(execute_CsrPlugin_csr_835) begin - _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; - end - end - - assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); - assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - IBusCachedPlugin_fetchPc_booted <= 1'b0; - IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - IBusCachedPlugin_rspCounter <= 32'h0; - dataCache_1_io_mem_cmd_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dBus_rsp_regNext_valid <= 1'b0; - DBusCachedPlugin_rspCounter <= 32'h0; - _zz_2 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; - memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - CsrPlugin_misa_base <= 2'b01; - CsrPlugin_misa_extensions <= 26'h0041101; - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= 2'b11; - CsrPlugin_mie_MEIE <= 1'b0; - CsrPlugin_mie_MTIE <= 1'b0; - CsrPlugin_mie_MSIE <= 1'b0; - CsrPlugin_mcycle <= 64'h0; - CsrPlugin_minstret <= 64'h0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - CsrPlugin_interrupt_valid <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - CsrPlugin_hadException <= 1'b0; - execute_CsrPlugin_wfiWake <= 1'b0; - execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - switch_Fetcher_l365 <= 3'b000; - end else begin - if(IBusCachedPlugin_fetchPc_correction) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_output_fire) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - end - IBusCachedPlugin_fetchPc_booted <= 1'b1; - if(when_Fetcher_l134) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_output_fire_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b1; - end - if(when_Fetcher_l134_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(when_Fetcher_l161) begin - IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - end - if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); - end - if(decode_arbitration_removeIt) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - end - if(when_Fetcher_l332) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(when_Fetcher_l332_1) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(when_Fetcher_l332_2) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(when_Fetcher_l332_3) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(when_Fetcher_l332_4) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(when_Fetcher_l332_5) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(iBus_rsp_valid) begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); - end - if(dataCache_1_io_mem_cmd_valid) begin - dataCache_1_io_mem_cmd_rValid <= 1'b1; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_rValid <= 1'b0; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; - end - dBus_rsp_regNext_valid <= dBus_rsp_valid; - if(dBus_rsp_valid) begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); - end - _zz_2 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; - memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring) begin - CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); - end - if(when_CsrPlugin_l922) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - end - if(when_CsrPlugin_l922_1) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if(when_CsrPlugin_l922_2) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if(when_CsrPlugin_l922_3) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - end - CsrPlugin_interrupt_valid <= 1'b0; - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - end - if(CsrPlugin_pipelineLiberator_active) begin - if(when_CsrPlugin_l993) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; - end - if(when_CsrPlugin_l993_1) begin - CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; - end - if(when_CsrPlugin_l993_2) begin - CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; - end - end - if(when_CsrPlugin_l998) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - end - if(CsrPlugin_interruptJump) begin - CsrPlugin_interrupt_valid <= 1'b0; - end - CsrPlugin_hadException <= CsrPlugin_exception; - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; - CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; - end - default : begin - end - endcase - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b00; - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; - end - default : begin - end - endcase - end - execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(when_Pipeline_l151) begin - execute_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154) begin - execute_arbitration_isValid <= decode_arbitration_isValid; - end - if(when_Pipeline_l151_1) begin - memory_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_1) begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(when_Pipeline_l151_2) begin - writeBack_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_2) begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(switch_Fetcher_l365) - 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid) begin - switch_Fetcher_l365 <= 3'b001; - end - end - 3'b001 : begin - switch_Fetcher_l365 <= 3'b010; - end - 3'b010 : begin - switch_Fetcher_l365 <= 3'b011; - end - 3'b011 : begin - if(when_Fetcher_l381) begin - switch_Fetcher_l365 <= 3'b100; - end - end - 3'b100 : begin - switch_Fetcher_l365 <= 3'b000; - end - default : begin - end - endcase - if(execute_CsrPlugin_csr_769) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; - CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; - end - end - if(execute_CsrPlugin_csr_768) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - case(switch_CsrPlugin_l723) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b11; - end - default : begin - end - endcase - end - end - if(execute_CsrPlugin_csr_772) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; - CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - end - end - - always @(posedge io_systemClk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; - end - if(IBusCachedPlugin_injector_decodeInput_ready) begin - IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; - end - if(dataCache_1_io_mem_cmd_ready) begin - dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; - dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; - dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; - dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; - execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); - if(when_MulPlugin_l70) begin - execute_MulPlugin_delayLogic_counter <= 1'b0; - end - execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - if(when_MulDivIterativePlugin_l126) begin - memory_MulDivIterativePlugin_div_done <= 1'b1; - end - if(when_MulDivIterativePlugin_l126_1) begin - memory_MulDivIterativePlugin_div_done <= 1'b0; - end - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if(when_MulDivIterativePlugin_l151) begin - memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; - end - end - end - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); - memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; - end - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_code <= 4'b0111; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_code <= 4'b0011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_code <= 4'b1011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - end - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException) begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase - end - if(when_Pipeline_l124) begin - decode_to_execute_PC <= _zz_decode_SRC2; - end - if(when_Pipeline_l124_1) begin - execute_to_memory_PC <= execute_PC; - end - if(when_Pipeline_l124_2) begin - memory_to_writeBack_PC <= memory_PC; - end - if(when_Pipeline_l124_3) begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; - end - if(when_Pipeline_l124_4) begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; - end - if(when_Pipeline_l124_5) begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if(when_Pipeline_l124_6) begin - decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_7) begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_8) begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_9) begin - decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; - end - if(when_Pipeline_l124_10) begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; - end - if(when_Pipeline_l124_11) begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; - end - if(when_Pipeline_l124_12) begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; - end - if(when_Pipeline_l124_13) begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if(when_Pipeline_l124_14) begin - decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; - end - if(when_Pipeline_l124_15) begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_16) begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_17) begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_18) begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; - end - if(when_Pipeline_l124_19) begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_20) begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_21) begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; - end - if(when_Pipeline_l124_22) begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; - end - if(when_Pipeline_l124_23) begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; - end - if(when_Pipeline_l124_24) begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; - end - if(when_Pipeline_l124_25) begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; - end - if(when_Pipeline_l124_26) begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; - end - if(when_Pipeline_l124_27) begin - decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; - end - if(when_Pipeline_l124_28) begin - execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; - end - if(when_Pipeline_l124_29) begin - decode_to_execute_IS_MUL <= decode_IS_MUL; - end - if(when_Pipeline_l124_30) begin - execute_to_memory_IS_MUL <= execute_IS_MUL; - end - if(when_Pipeline_l124_31) begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; - end - if(when_Pipeline_l124_32) begin - decode_to_execute_IS_DIV <= decode_IS_DIV; - end - if(when_Pipeline_l124_33) begin - execute_to_memory_IS_DIV <= execute_IS_DIV; - end - if(when_Pipeline_l124_34) begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; - end - if(when_Pipeline_l124_35) begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; - end - if(when_Pipeline_l124_36) begin - decode_to_execute_IS_CSR <= decode_IS_CSR; - end - if(when_Pipeline_l124_37) begin - decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; - end - if(when_Pipeline_l124_38) begin - execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; - end - if(when_Pipeline_l124_39) begin - memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; - end - if(when_Pipeline_l124_40) begin - decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; - end - if(when_Pipeline_l124_41) begin - decode_to_execute_RS1 <= _zz_decode_SRC1; - end - if(when_Pipeline_l124_42) begin - decode_to_execute_RS2 <= _zz_decode_SRC2_1; - end - if(when_Pipeline_l124_43) begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; - end - if(when_Pipeline_l124_44) begin - decode_to_execute_SRC1 <= decode_SRC1; - end - if(when_Pipeline_l124_45) begin - decode_to_execute_SRC2 <= decode_SRC2; - end - if(when_Pipeline_l124_46) begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; - end - if(when_Pipeline_l124_47) begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; - end - if(when_Pipeline_l124_48) begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; - end - if(when_Pipeline_l124_49) begin - execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_50) begin - memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_51) begin - execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; - end - if(when_Pipeline_l124_52) begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; - end - if(when_Pipeline_l124_53) begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; - end - if(when_Pipeline_l124_54) begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; - end - if(when_Pipeline_l124_55) begin - execute_to_memory_MUL_LL <= execute_MUL_LL; - end - if(when_Pipeline_l124_56) begin - execute_to_memory_MUL_LH <= execute_MUL_LH; - end - if(when_Pipeline_l124_57) begin - execute_to_memory_MUL_HL <= execute_MUL_HL; - end - if(when_Pipeline_l124_58) begin - execute_to_memory_MUL_HH <= execute_MUL_HH; - end - if(when_Pipeline_l124_59) begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; - end - if(when_Pipeline_l124_60) begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if(when_Pipeline_l124_61) begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end - if(when_Pipeline_l124_62) begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; - end - if(when_Fetcher_l401) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; - end - if(when_CsrPlugin_l1277) begin - execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); - end - if(when_CsrPlugin_l1277_1) begin - execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); - end - if(when_CsrPlugin_l1277_2) begin - execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); - end - if(when_CsrPlugin_l1277_3) begin - execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); - end - if(when_CsrPlugin_l1277_4) begin - execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); - end - if(when_CsrPlugin_l1277_5) begin - execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); - end - if(when_CsrPlugin_l1277_6) begin - execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); - end - if(when_CsrPlugin_l1277_7) begin - execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); - end - if(when_CsrPlugin_l1277_8) begin - execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); - end - if(when_CsrPlugin_l1277_9) begin - execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); - end - if(execute_CsrPlugin_csr_836) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - if(execute_CsrPlugin_csr_773) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; - CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; - end - end - if(execute_CsrPlugin_csr_833) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_832) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - end - - always @(posedge io_systemClk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready) begin - DebugPlugin_firstCycle <= 1'b1; - end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid) begin - DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; - end - _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; - if(when_DebugPlugin_l295) begin - DebugPlugin_busReadDataReg <= execute_PC; - end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - DebugPlugin_debugUsed <= 1'b0; - DebugPlugin_disableEbreak <= 1'b0; - end else begin - if(when_DebugPlugin_l225) begin - DebugPlugin_godmode <= 1'b1; - end - if(debug_bus_cmd_valid) begin - DebugPlugin_debugUsed <= 1'b1; - end - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h0 : begin - if(debug_bus_cmd_payload_wr) begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(when_DebugPlugin_l271) begin - DebugPlugin_resetIt <= 1'b1; - end - if(when_DebugPlugin_l271_1) begin - DebugPlugin_resetIt <= 1'b0; - end - if(when_DebugPlugin_l272) begin - DebugPlugin_haltIt <= 1'b1; - end - if(when_DebugPlugin_l272_1) begin - DebugPlugin_haltIt <= 1'b0; - end - if(when_DebugPlugin_l273) begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(when_DebugPlugin_l274) begin - DebugPlugin_godmode <= 1'b0; - end - if(when_DebugPlugin_l275) begin - DebugPlugin_disableEbreak <= 1'b1; - end - if(when_DebugPlugin_l275_1) begin - DebugPlugin_disableEbreak <= 1'b0; - end - end - end - default : begin - end - endcase - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end - end - if(when_DebugPlugin_l311) begin - if(decode_arbitration_isValid) begin - DebugPlugin_haltIt <= 1'b1; - end - end - end - end - - -endmodule - -module BufferCC_3 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin - if(debugCd_logic_outputReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module BufferCC_2 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input io_asyncReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge io_asyncReset) begin - if(io_asyncReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module StreamFifo_3 ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload_data; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [7:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload_data = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload_data) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload_data; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module StreamFifo_2 ( - input io_push_valid, - output io_push_ready, - input io_push_payload_kind, - input io_push_payload_read, - input io_push_payload_write, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output io_pop_payload_kind, - output io_pop_payload_read, - output io_pop_payload_write, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [10:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz__zz_io_pop_payload_kind; - wire [10:0] _zz_logic_ram_port_1; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [10:0] _zz_io_pop_payload_kind; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [10:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_kind = 1'b1; - assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; - always @(posedge io_systemClk) begin - if(_zz__zz_io_pop_payload_kind) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; - assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; - assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; - assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; - assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module TopLevel ( - input io_config_kind_cpol, - input io_config_kind_cpha, - input [11:0] io_config_sclkToogle, - input [1:0] io_config_mod, - input [0:0] io_config_ss_activeHigh, - input [11:0] io_config_ss_setup, - input [11:0] io_config_ss_hold, - input [11:0] io_config_ss_disable, - input io_cmd_valid, - output reg io_cmd_ready, - input io_cmd_payload_kind, - input io_cmd_payload_read, - input io_cmd_payload_write, - input [7:0] io_cmd_payload_data, - output io_rsp_valid, - output [7:0] io_rsp_payload_data, - output [0:0] io_spi_sclk_write, - output reg io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output reg [0:0] io_spi_data_0_write, - output reg io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output reg [0:0] io_spi_data_1_write, - output reg io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output reg [0:0] io_spi_data_2_write, - output reg io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output reg [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [0:0] _zz_outputPhy_dataWrite_3; - wire [2:0] _zz_outputPhy_dataWrite_4; - wire [2:0] _zz_outputPhy_dataWrite_5; - reg [1:0] _zz_outputPhy_dataWrite_6; - wire [1:0] _zz_outputPhy_dataWrite_7; - wire [2:0] _zz_outputPhy_dataWrite_8; - reg [3:0] _zz_outputPhy_dataWrite_9; - wire [0:0] _zz_outputPhy_dataWrite_10; - wire [2:0] _zz_outputPhy_dataWrite_11; - wire [3:0] _zz_inputPhy_dataRead; - wire [3:0] _zz_inputPhy_dataRead_1; - wire [3:0] _zz_inputPhy_dataRead_2; - wire [3:0] _zz_inputPhy_dataRead_3; - wire [3:0] _zz_inputPhy_dataRead_4; - wire [3:0] _zz_inputPhy_dataRead_5; - wire [3:0] _zz_inputPhy_dataRead_6; - wire [8:0] _zz_inputPhy_bufferNext; - wire [10:0] _zz_inputPhy_bufferNext_1; - reg [11:0] timer_counter; - reg timer_reset; - wire timer_ss_setupHit; - wire timer_ss_holdHit; - wire timer_ss_disableHit; - wire timer_sclkToogleHit; - reg fsm_state; - reg [2:0] fsm_counter; - reg [2:0] _zz_fsm_counterPlus; - wire [2:0] fsm_counterPlus; - reg fsm_fastRate; - reg fsm_isDdr; - reg [2:0] fsm_counterMax; - reg fsm_lateSampling; - reg fsm_readFill; - reg fsm_readDone; - reg [0:0] fsm_ss; - wire when_SpiXdrMasterCtrl_l739; - wire when_SpiXdrMasterCtrl_l742; - wire when_SpiXdrMasterCtrl_l749; - wire when_SpiXdrMasterCtrl_l751; - wire when_SpiXdrMasterCtrl_l758; - wire when_SpiXdrMasterCtrl_l764; - wire when_SpiXdrMasterCtrl_l781; - reg [0:0] outputPhy_sclkWrite; - wire [0:0] _zz_io_spi_sclk_write; - wire when_SpiXdrMasterCtrl_l796; - reg [3:0] outputPhy_dataWrite; - reg [2:0] outputPhy_widthSel; - reg [2:0] outputPhy_offset; - wire [7:0] _zz_outputPhy_dataWrite; - wire [7:0] _zz_outputPhy_dataWrite_1; - wire [7:0] _zz_outputPhy_dataWrite_2; - wire when_SpiXdrMasterCtrl_l839; - wire when_SpiXdrMasterCtrl_l839_1; - reg [1:0] io_config_mod_delay_1; - reg [1:0] inputPhy_mod; - reg fsm_readFill_delay_1; - reg inputPhy_readFill; - reg fsm_readDone_delay_1; - reg inputPhy_readDone; - reg [6:0] inputPhy_buffer; - reg [7:0] inputPhy_bufferNext; - reg [2:0] inputPhy_widthSel; - wire [3:0] inputPhy_dataWrite; - reg [3:0] inputPhy_dataRead; - reg fsm_state_delay_1; - reg fsm_state_delay_2; - wire when_SpiXdrMasterCtrl_l861; - reg [3:0] inputPhy_dataReadBuffer; - - assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); - assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); - assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); - assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); - assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; - assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; - always @(*) begin - case(_zz_outputPhy_dataWrite_4) - 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; - 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; - 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; - 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; - 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; - 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; - 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; - default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_7) - 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; - 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; - 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; - default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_10) - 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; - default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; - endcase - end - - always @(*) begin - timer_reset = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - timer_reset = timer_sclkToogleHit; - end else begin - if(!when_SpiXdrMasterCtrl_l758) begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - timer_reset = 1'b1; - end - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - timer_reset = 1'b1; - end - end - - assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); - assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); - assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); - assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); - always @(*) begin - _zz_fsm_counterPlus = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - _zz_fsm_counterPlus = 3'b001; - end - 2'b01 : begin - _zz_fsm_counterPlus = 3'b010; - end - 2'b10 : begin - _zz_fsm_counterPlus = 3'b100; - end - default : begin - end - endcase - end - - assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); - always @(*) begin - fsm_fastRate = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_fastRate = 1'b0; - end - 2'b01 : begin - fsm_fastRate = 1'b0; - end - 2'b10 : begin - fsm_fastRate = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_isDdr = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_isDdr = 1'b0; - end - 2'b01 : begin - fsm_isDdr = 1'b0; - end - 2'b10 : begin - fsm_isDdr = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_counterMax = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - fsm_counterMax = 3'b111; - end - 2'b01 : begin - fsm_counterMax = 3'b110; - end - 2'b10 : begin - fsm_counterMax = 3'b100; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_lateSampling = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_lateSampling = 1'b1; - end - 2'b01 : begin - fsm_lateSampling = 1'b1; - end - 2'b10 : begin - fsm_lateSampling = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_readFill = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readFill = 1'b1; - end - end - end - end - - always @(*) begin - fsm_readDone = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); - end - end - end - end - - assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); - always @(*) begin - io_cmd_ready = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l749) begin - if(when_SpiXdrMasterCtrl_l751) begin - io_cmd_ready = 1'b1; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - if(timer_ss_setupHit) begin - io_cmd_ready = 1'b1; - end - end else begin - if(!when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_disableHit) begin - io_cmd_ready = 1'b1; - end - end - end - end - end - end - - assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); - assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); - assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; - assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); - assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); - always @(*) begin - outputPhy_sclkWrite = 1'b0; - if(when_SpiXdrMasterCtrl_l796) begin - case(io_config_mod) - 2'b00 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b01 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b10 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - default : begin - end - endcase - end - end - - assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; - assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); - assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); - always @(*) begin - outputPhy_widthSel = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_widthSel = 3'b000; - end - 2'b01 : begin - outputPhy_widthSel = 3'b001; - end - 2'b10 : begin - outputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_offset = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_offset = 3'b111; - end - 2'b01 : begin - outputPhy_offset = 3'b111; - end - 2'b10 : begin - outputPhy_offset = 3'b111; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_dataWrite = 4'bxxxx; - case(outputPhy_widthSel) - 3'b000 : begin - outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; - end - 3'b001 : begin - outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; - end - 3'b010 : begin - outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; - end - default : begin - end - endcase - end - - assign _zz_outputPhy_dataWrite = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; - always @(*) begin - io_spi_data_0_writeEnable = 1'b0; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_writeEnable = 1'b1; - end - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_writeEnable = 1'b0; - case(io_config_mod) - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_2_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_3_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_0_write = 1'bx; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); - end - 2'b01 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - 2'b10 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_write = 1'bx; - case(io_config_mod) - 2'b01 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - 2'b10 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_2_write[0] = outputPhy_dataWrite[2]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_3_write[0] = outputPhy_dataWrite[3]; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); - assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); - always @(*) begin - inputPhy_bufferNext = 8'bxxxxxxxx; - case(inputPhy_widthSel) - 3'b000 : begin - inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; - end - 3'b001 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; - end - 3'b010 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; - end - default : begin - end - endcase - end - - always @(*) begin - inputPhy_widthSel = 3'bxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_widthSel = 3'b000; - end - 2'b01 : begin - inputPhy_widthSel = 3'b001; - end - 2'b10 : begin - inputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); - always @(*) begin - inputPhy_dataRead = 4'bxxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; - end - 2'b01 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; - end - 2'b10 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; - inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; - inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; - end - default : begin - end - endcase - end - - assign io_rsp_valid = inputPhy_readDone; - assign io_rsp_payload_data = inputPhy_bufferNext; - always @(posedge io_systemClk) begin - timer_counter <= (timer_counter + 12'h001); - if(timer_reset) begin - timer_counter <= 12'h0; - end - io_config_mod_delay_1 <= io_config_mod; - inputPhy_mod <= io_config_mod_delay_1; - fsm_state_delay_1 <= fsm_state; - fsm_state_delay_2 <= fsm_state_delay_1; - if(when_SpiXdrMasterCtrl_l861) begin - inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - end - case(inputPhy_widthSel) - 3'b000 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b001 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b010 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - default : begin - end - endcase - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - fsm_ss <= 1'b0; - fsm_readFill_delay_1 <= 1'b0; - inputPhy_readFill <= 1'b0; - fsm_readDone_delay_1 <= 1'b0; - inputPhy_readDone <= 1'b0; - end else begin - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(timer_sclkToogleHit) begin - fsm_state <= (! fsm_state); - end - if(when_SpiXdrMasterCtrl_l749) begin - fsm_counter <= fsm_counterPlus; - if(when_SpiXdrMasterCtrl_l751) begin - fsm_state <= 1'b0; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - fsm_ss[0] <= 1'b1; - end else begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - fsm_state <= 1'b1; - end - end else begin - fsm_ss[0] <= 1'b0; - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - end - fsm_readFill_delay_1 <= fsm_readFill; - inputPhy_readFill <= fsm_readFill_delay_1; - fsm_readDone_delay_1 <= fsm_readDone; - inputPhy_readDone <= fsm_readDone_delay_1; - end - end - - -endmodule - -//StreamFifo replaced by StreamFifo - -module StreamFifo ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload, - input io_flush, - output [7:0] io_occupancy, - output [7:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [6:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [6:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload; - wire [6:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [6:0] logic_pushPtr_valueNext; - reg [6:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [6:0] logic_popPtr_valueNext; - reg [6:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [6:0] logic_ptrDif; - reg [7:0] logic_ram [0:127]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 7'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 7'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload = _zz_logic_ram_port0; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 7'h0; - logic_popPtr_value <= 7'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module UartCtrl ( - input [2:0] io_config_frame_dataLength, - input [0:0] io_config_frame_stop, - input [1:0] io_config_frame_parity, - input [19:0] io_config_clockDivider, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - output io_uart_txd, - input io_uart_rxd, - output io_readError, - input io_writeBreak, - output io_readBreak, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - wire tx_io_write_ready; - wire tx_io_txd; - wire rx_io_read_valid; - wire [7:0] rx_io_read_payload; - wire rx_io_rts; - wire rx_io_error; - wire rx_io_break; - reg [19:0] clockDivider_counter; - wire clockDivider_tick; - reg clockDivider_tickReg; - reg io_write_thrown_valid; - wire io_write_thrown_ready; - wire [7:0] io_write_thrown_payload; - `ifndef SYNTHESIS - reg [23:0] io_config_frame_stop_string; - reg [31:0] io_config_frame_parity_string; - `endif - - - UartCtrlTx tx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_write_valid (io_write_thrown_valid ), //i - .io_write_ready (tx_io_write_ready ), //o - .io_write_payload (io_write_thrown_payload[7:0] ), //i - .io_cts (1'b0 ), //i - .io_txd (tx_io_txd ), //o - .io_break (io_writeBreak ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - UartCtrlRx rx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_read_valid (rx_io_read_valid ), //o - .io_read_ready (io_read_ready ), //i - .io_read_payload (rx_io_read_payload[7:0] ), //o - .io_rxd (io_uart_rxd ), //i - .io_rts (rx_io_rts ), //o - .io_error (rx_io_error ), //o - .io_break (rx_io_break ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_config_frame_stop) - UartStopType_ONE : io_config_frame_stop_string = "ONE"; - UartStopType_TWO : io_config_frame_stop_string = "TWO"; - default : io_config_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_config_frame_parity) - UartParityType_NONE : io_config_frame_parity_string = "NONE"; - UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; - UartParityType_ODD : io_config_frame_parity_string = "ODD "; - default : io_config_frame_parity_string = "????"; - endcase - end - `endif - - assign clockDivider_tick = (clockDivider_counter == 20'h0); - always @(*) begin - io_write_thrown_valid = io_write_valid; - if(rx_io_break) begin - io_write_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_write_ready = io_write_thrown_ready; - if(rx_io_break) begin - io_write_ready = 1'b1; - end - end - - assign io_write_thrown_payload = io_write_payload; - assign io_write_thrown_ready = tx_io_write_ready; - assign io_read_valid = rx_io_read_valid; - assign io_read_payload = rx_io_read_payload; - assign io_uart_txd = tx_io_txd; - assign io_readError = rx_io_error; - assign io_readBreak = rx_io_break; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter <= 20'h0; - clockDivider_tickReg <= 1'b0; - end else begin - clockDivider_tickReg <= clockDivider_tick; - clockDivider_counter <= (clockDivider_counter - 20'h00001); - if(clockDivider_tick) begin - clockDivider_counter <= io_config_clockDivider; - end - end - end - - -endmodule - -module StreamArbiter ( - input io_inputs_0_valid, - output io_inputs_0_ready, - input io_inputs_0_payload_last, - input [0:0] io_inputs_0_payload_fragment_source, - input [0:0] io_inputs_0_payload_fragment_opcode, - input [31:0] io_inputs_0_payload_fragment_address, - input [5:0] io_inputs_0_payload_fragment_length, - input [31:0] io_inputs_0_payload_fragment_data, - input [3:0] io_inputs_0_payload_fragment_mask, - input [0:0] io_inputs_0_payload_fragment_context, - input io_inputs_1_valid, - output io_inputs_1_ready, - input io_inputs_1_payload_last, - input [0:0] io_inputs_1_payload_fragment_source, - input [0:0] io_inputs_1_payload_fragment_opcode, - input [31:0] io_inputs_1_payload_fragment_address, - input [5:0] io_inputs_1_payload_fragment_length, - input [31:0] io_inputs_1_payload_fragment_data, - input [3:0] io_inputs_1_payload_fragment_mask, - input [0:0] io_inputs_1_payload_fragment_context, - output io_output_valid, - input io_output_ready, - output io_output_payload_last, - output [0:0] io_output_payload_fragment_source, - output [0:0] io_output_payload_fragment_opcode, - output [31:0] io_output_payload_fragment_address, - output [5:0] io_output_payload_fragment_length, - output [31:0] io_output_payload_fragment_data, - output [3:0] io_output_payload_fragment_mask, - output [0:0] io_output_payload_fragment_context, - output [0:0] io_chosen, - output [1:0] io_chosenOH, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l621; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l621 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); - assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l621) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module FlowCCByToggle ( - input io_input_valid, - input io_input_payload_last, - input [0:0] io_input_payload_fragment, - output io_output_valid, - output io_output_payload_last, - output [0:0] io_output_payload_fragment, - input jtagCtrl_tck, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg inputArea_data_last; - reg [0:0] inputArea_data_fragment; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire outputArea_flow_payload_last; - wire [0:0] outputArea_flow_payload_fragment; - reg outputArea_flow_m2sPipe_valid; - reg outputArea_flow_m2sPipe_payload_last; - reg [0:0] outputArea_flow_m2sPipe_payload_fragment; - - BufferCC_1 inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - initial begin - `ifndef SYNTHESIS - inputArea_target = $urandom; - outputArea_hit = $urandom; - `endif - end - - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_last = inputArea_data_last; - assign outputArea_flow_payload_fragment = inputArea_data_fragment; - assign io_output_valid = outputArea_flow_m2sPipe_valid; - assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; - assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; - always @(posedge jtagCtrl_tck) begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - inputArea_data_last <= io_input_payload_last; - inputArea_data_fragment <= io_input_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - outputArea_hit <= outputArea_target; - if(outputArea_flow_valid) begin - outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; - outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - outputArea_flow_m2sPipe_valid <= 1'b0; - end else begin - outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; - end - end - - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - output reg io_cpu_execute_haltIt, - input io_cpu_execute_args_wr, - input [1:0] io_cpu_execute_args_size, - input io_cpu_execute_args_totalyConsistent, - output io_cpu_execute_refilling, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - input [31:0] io_cpu_memory_mmuRsp_physicalAddress, - input io_cpu_memory_mmuRsp_isIoAccess, - input io_cpu_memory_mmuRsp_isPaging, - input io_cpu_memory_mmuRsp_allowRead, - input io_cpu_memory_mmuRsp_allowWrite, - input io_cpu_memory_mmuRsp_allowExecute, - input io_cpu_memory_mmuRsp_exception, - input io_cpu_memory_mmuRsp_refilling, - input io_cpu_memory_mmuRsp_bypassTranslation, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isFiring, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - input [31:0] io_cpu_writeBack_storeData, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output io_cpu_writeBack_keepMemRspData, - input io_cpu_writeBack_fence_SW, - input io_cpu_writeBack_fence_SR, - input io_cpu_writeBack_fence_SO, - input io_cpu_writeBack_fence_SI, - input io_cpu_writeBack_fence_PW, - input io_cpu_writeBack_fence_PR, - input io_cpu_writeBack_fence_PO, - input io_cpu_writeBack_fence_PI, - input [3:0] io_cpu_writeBack_fence_FM, - output io_cpu_writeBack_exclusiveOk, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output io_cpu_flush_ready, - input io_cpu_flush_payload_singleLine, - input [5:0] io_cpu_flush_payload_lineId, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output io_mem_cmd_payload_uncached, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_size, - output io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input io_mem_rsp_payload_last, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [21:0] _zz_ways_0_tags_port0; - reg [31:0] _zz_ways_0_data_port0; - wire [21:0] _zz_ways_0_tags_port; - wire [9:0] _zz_stage0_dataColisions; - wire [9:0] _zz__zz_stageA_dataColisions; - wire [0:0] _zz_when; - wire [3:0] _zz_loader_counter_valueNext; - wire [0:0] _zz_loader_counter_valueNext_1; - wire [1:0] _zz_loader_waysAllocator; - reg _zz_1; - reg _zz_2; - wire haltCpu; - reg tagsReadCmd_valid; - reg [5:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [5:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [5:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; - wire _zz_ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRsp; - wire when_DataCache_l642; - wire when_DataCache_l645; - wire when_DataCache_l664; - wire rspSync; - wire rspLast; - reg memCmdSent; - wire io_mem_cmd_fire; - wire when_DataCache_l686; - reg [3:0] _zz_stage0_mask; - wire [3:0] stage0_mask; - wire [0:0] stage0_dataColisions; - wire [0:0] stage0_wayInvalidate; - wire stage0_isAmo; - wire when_DataCache_l771; - reg stageA_request_wr; - reg [1:0] stageA_request_size; - reg stageA_request_totalyConsistent; - wire when_DataCache_l771_1; - reg [3:0] stageA_mask; - wire stageA_isAmo; - wire stageA_isLrsc; - wire [0:0] stageA_wayHits; - wire when_DataCache_l771_2; - reg [0:0] stageA_wayInvalidate; - wire when_DataCache_l771_3; - reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_stageA_dataColisions; - wire [0:0] stageA_dataColisions; - wire when_DataCache_l822; - reg stageB_request_wr; - reg [1:0] stageB_request_size; - reg stageB_request_totalyConsistent; - reg stageB_mmuRspFreeze; - wire when_DataCache_l824; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_isPaging; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_mmuRsp_bypassTranslation; - wire when_DataCache_l821; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - wire when_DataCache_l821_1; - reg [31:0] stageB_dataReadRsp_0; - wire when_DataCache_l820; - reg [0:0] stageB_wayInvalidate; - wire stageB_consistancyHazard; - wire when_DataCache_l820_1; - reg [0:0] stageB_dataColisions; - wire when_DataCache_l820_2; - reg stageB_unaligned; - wire when_DataCache_l820_3; - reg [0:0] stageB_waysHitsBeforeInvalidate; - wire [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - wire when_DataCache_l820_4; - reg [3:0] stageB_mask; - reg stageB_loaderValid; - wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_waitDone; - wire stageB_flusher_hold; - reg [6:0] stageB_flusher_counter; - wire when_DataCache_l850; - wire when_DataCache_l856; - reg stageB_flusher_start; - wire stageB_isAmo; - wire stageB_isAmoCached; - wire stageB_isExternalLsrc; - wire stageB_isExternalAmo; - wire [31:0] stageB_requestDataBypass; - reg stageB_cpuWriteToCache; - wire when_DataCache_l926; - wire stageB_badPermissions; - wire stageB_loadStoreFault; - wire stageB_bypassCache; - wire when_DataCache_l995; - wire when_DataCache_l1004; - wire when_DataCache_l1009; - wire when_DataCache_l1020; - wire when_DataCache_l1032; - wire when_DataCache_l991; - wire when_DataCache_l1066; - wire when_DataCache_l1075; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [3:0] loader_counter_valueNext; - reg [3:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - wire loader_kill; - reg loader_killReg; - wire when_DataCache_l1090; - wire loader_done; - wire when_DataCache_l1118; - reg loader_valid_regNext; - wire when_DataCache_l1122; - wire when_DataCache_l1125; - reg [21:0] ways_0_tags [0:63]; - reg [7:0] ways_0_data_symbol0 [0:1023]; - reg [7:0] ways_0_data_symbol1 [0:1023]; - reg [7:0] ways_0_data_symbol2 [0:1023]; - reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_ways_0_datasymbol_read; - reg [7:0] _zz_ways_0_datasymbol_read_1; - reg [7:0] _zz_ways_0_datasymbol_read_2; - reg [7:0] _zz_ways_0_datasymbol_read_3; - - assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_when = 1'b1; - assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; - assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; - assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_ways_0_tagsReadRsp_valid) begin - _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(*) begin - _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; - end - always @(posedge io_systemClk) begin - if(_zz_ways_0_dataReadRspMem) begin - _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(when_DataCache_l645) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(when_DataCache_l642) begin - _zz_2 = 1'b1; - end - end - - assign haltCpu = 1'b0; - assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; - assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; - assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; - assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; - assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; - assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); - assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); - always @(*) begin - tagsReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - tagsReadCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsReadCmd_payload = 6'bxxxxxx; - if(when_DataCache_l664) begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; - end - end - - always @(*) begin - dataReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - dataReadCmd_valid = 1'b1; - end - end - - always @(*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; - if(when_DataCache_l664) begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end - end - - always @(*) begin - tagsWriteCmd_valid = 1'b0; - if(when_DataCache_l850) begin - tagsWriteCmd_valid = 1'b1; - end - if(when_DataCache_l1066) begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsWriteCmd_payload_way = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_way = 1'b1; - end - if(loader_done) begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - tagsWriteCmd_payload_address = 6'bxxxxxx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; - end - if(loader_done) begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; - end - end - - always @(*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done) begin - tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; - if(loader_done) begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end - end - - always @(*) begin - dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache) begin - if(when_DataCache_l926) begin - dataWriteCmd_valid = 1'b1; - end - end - if(when_DataCache_l1066) begin - dataWriteCmd_valid = 1'b0; - end - if(when_DataCache_l1090) begin - dataWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_way = stageB_waysHits; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; - end - end - - always @(*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end - end - - always @(*) begin - dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_mask = 4'b0000; - if(_zz_when[0]) begin - dataWriteCmd_payload_mask[3 : 0] = stageB_mask; - end - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_mask = 4'b1111; - end - end - - assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - always @(*) begin - io_cpu_execute_haltIt = 1'b0; - if(when_DataCache_l850) begin - io_cpu_execute_haltIt = 1'b1; - end - end - - assign rspSync = 1'b1; - assign rspLast = 1'b1; - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); - always @(*) begin - _zz_stage0_mask = 4'bxxxx; - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_stage0_mask = 4'b0001; - end - 2'b01 : begin - _zz_stage0_mask = 4'b0011; - end - 2'b10 : begin - _zz_stage0_mask = 4'b1111; - end - default : begin - end - endcase - end - - assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stage0_wayInvalidate = 1'b0; - assign stage0_isAmo = 1'b0; - assign when_DataCache_l771 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_isAmo = 1'b0; - assign stageA_isLrsc = 1'b0; - assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); - assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); - assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_mmuRspFreeze = 1'b0; - if(when_DataCache_l1125) begin - stageB_mmuRspFreeze = 1'b1; - end - end - - assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); - assign stageB_consistancyHazard = 1'b0; - assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); - assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (|stageB_waysHits); - assign stageB_dataMux = stageB_dataReadRsp_0; - assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - if(io_mem_cmd_ready) begin - stageB_loaderValid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - stageB_loaderValid = 1'b0; - end - end - - assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @(*) begin - io_cpu_writeBack_haltIt = 1'b1; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - if(when_DataCache_l995) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1009) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - - assign stageB_flusher_hold = 1'b0; - assign when_DataCache_l850 = (! stageB_flusher_counter[6]); - assign when_DataCache_l856 = (! stageB_flusher_hold); - assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); - assign stageB_isAmo = 1'b0; - assign stageB_isAmoCached = 1'b0; - assign stageB_isExternalLsrc = 1'b0; - assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = io_cpu_writeBack_storeData; - always @(*) begin - stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - stageB_cpuWriteToCache = 1'b1; - end - end - end - end - end - - assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); - assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); - assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @(*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1020) begin - io_cpu_redo = 1'b1; - end - end - end - end - end - if(when_DataCache_l1075) begin - io_cpu_redo = 1'b1; - end - if(when_DataCache_l1122) begin - io_cpu_redo = 1'b1; - end - end - - always @(*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache) begin - io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); - end - end - - assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @(*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - io_mem_cmd_valid = (! memCmdSent); - end else begin - if(when_DataCache_l1004) begin - if(stageB_request_wr) begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if(when_DataCache_l1032) begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_mem_cmd_valid = 1'b0; - end - end - - always @(*) begin - io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_address[5 : 0] = 6'h0; - end - end - end - end - end - - assign io_mem_cmd_payload_last = 1'b1; - always @(*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; - always @(*) begin - io_mem_cmd_payload_size = {1'd0, stageB_request_size}; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_size = 3'b110; - end - end - end - end - end - - assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); - assign io_cpu_writeBack_keepMemRspData = 1'b0; - assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); - assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); - assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); - assign when_DataCache_l1032 = (! memCmdSent); - assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - always @(*) begin - if(stageB_bypassCache) begin - io_cpu_writeBack_data = stageB_ioMemRspMuxed; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); - always @(*) begin - loader_counter_willIncrement = 1'b0; - if(when_DataCache_l1090) begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @(*) begin - loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); - if(loader_counter_willClear) begin - loader_counter_valueNext = 4'b0000; - end - end - - assign loader_kill = 1'b0; - assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign loader_done = loader_counter_willOverflow; - assign when_DataCache_l1118 = (! loader_valid); - assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); - assign io_cpu_execute_refilling = loader_valid; - assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); - always @(posedge io_systemClk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if(when_DataCache_l771) begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_size <= io_cpu_execute_args_size; - stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; - end - if(when_DataCache_l771_1) begin - stageA_mask <= stage0_mask; - end - if(when_DataCache_l771_2) begin - stageA_wayInvalidate <= stage0_wayInvalidate; - end - if(when_DataCache_l771_3) begin - stage0_dataColisions_regNextWhen <= stage0_dataColisions; - end - if(when_DataCache_l822) begin - stageB_request_wr <= stageA_request_wr; - stageB_request_size <= stageA_request_size; - stageB_request_totalyConsistent <= stageA_request_totalyConsistent; - end - if(when_DataCache_l824) begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; - stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; - stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; - end - if(when_DataCache_l821) begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if(when_DataCache_l821_1) begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if(when_DataCache_l820) begin - stageB_wayInvalidate <= stageA_wayInvalidate; - end - if(when_DataCache_l820_1) begin - stageB_dataColisions <= stageA_dataColisions; - end - if(when_DataCache_l820_2) begin - stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); - end - if(when_DataCache_l820_3) begin - stageB_waysHitsBeforeInvalidate <= stageA_wayHits; - end - if(when_DataCache_l820_4) begin - stageB_mask <= stageA_mask; - end - loader_valid_regNext <= loader_valid; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - memCmdSent <= 1'b0; - stageB_flusher_waitDone <= 1'b0; - stageB_flusher_counter <= 7'h0; - stageB_flusher_start <= 1'b1; - loader_valid <= 1'b0; - loader_counter_value <= 4'b0000; - loader_waysAllocator <= 1'b1; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end else begin - if(io_mem_cmd_fire) begin - memCmdSent <= 1'b1; - end - if(when_DataCache_l686) begin - memCmdSent <= 1'b0; - end - if(io_cpu_flush_ready) begin - stageB_flusher_waitDone <= 1'b0; - end - if(when_DataCache_l850) begin - if(when_DataCache_l856) begin - stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter[6] <= 1'b1; - end - end - end - stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start) begin - stageB_flusher_waitDone <= 1'b1; - stageB_flusher_counter <= 7'h0; - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; - end - end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache.scala:L1077 - `else - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache.scala:L1077 - end - `endif - `endif - if(stageB_loaderValid) begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(loader_kill) begin - loader_killReg <= 1'b1; - end - if(when_DataCache_l1090) begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_done) begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end - if(when_DataCache_l1118) begin - loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; - end - end - end - - -endmodule - -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, - input io_cpu_fetch_mmuRsp_isIoAccess, - input io_cpu_fetch_mmuRsp_isPaging, - input io_cpu_fetch_mmuRsp_allowRead, - input io_cpu_fetch_mmuRsp_allowWrite, - input io_cpu_fetch_mmuRsp_allowExecute, - input io_cpu_fetch_mmuRsp_exception, - input io_cpu_fetch_mmuRsp_refilling, - input io_cpu_fetch_mmuRsp_bypassTranslation, - output [31:0] io_cpu_fetch_physicalAddress, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_banks_0_port1; - reg [21:0] _zz_ways_0_tags_port1; - wire [21:0] _zz_ways_0_tags_port; - reg _zz_1; - reg _zz_2; - reg lineLoader_fire; - reg lineLoader_valid; - (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; - wire when_InstructionCache_l338; - reg _zz_when_InstructionCache_l342; - wire when_InstructionCache_l342; - wire when_InstructionCache_l351; - reg lineLoader_cmdSent; - wire io_mem_cmd_fire; - wire when_Utils_l513; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; - wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire when_InstructionCache_l401; - wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; - wire _zz_fetchStage_read_banksValue_0_dataMem_1; - wire [31:0] fetchStage_read_banksValue_0_dataMem; - wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; - wire _zz_fetchStage_read_waysValues_0_tag_valid_1; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - wire when_InstructionCache_l435; - reg [31:0] io_cpu_fetch_data_regNextWhen; - wire when_InstructionCache_l459; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_isPaging; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_mmuRsp_bypassTranslation; - wire when_InstructionCache_l459_1; - reg decodeStage_hit_valid; - wire when_InstructionCache_l459_2; - reg decodeStage_hit_error; - reg [31:0] banks_0 [0:1023]; - reg [21:0] ways_0_tags [0:63]; - - assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_1) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin - _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin - _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid) begin - _zz_2 = 1'b1; - end - end - - always @(*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid) begin - if(when_InstructionCache_l401) begin - lineLoader_fire = 1'b1; - end - end - end - - always @(*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(when_InstructionCache_l338) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(when_InstructionCache_l342) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush) begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); - assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); - assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; - assign io_mem_cmd_payload_size = 3'b110; - assign when_Utils_l513 = (! lineLoader_valid); - always @(*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if(when_Utils_l513) begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end - end - - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; - assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); - assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; - assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; - assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; - assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); - assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; - assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; - assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; - assign fetchStage_hit_word = fetchStage_hit_data; - assign io_cpu_fetch_data = fetchStage_hit_word; - assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; - assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= 4'b0000; - end else begin - if(lineLoader_fire) begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire) begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid) begin - lineLoader_valid <= 1'b1; - end - if(io_flush) begin - lineLoader_flushPending <= 1'b1; - end - if(when_InstructionCache_l351) begin - lineLoader_flushPending <= 1'b0; - end - if(io_mem_cmd_fire) begin - lineLoader_cmdSent <= 1'b1; - end - if(lineLoader_fire) begin - lineLoader_cmdSent <= 1'b0; - end - if(io_mem_rsp_valid) begin - lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); - if(io_mem_rsp_payload_error) begin - lineLoader_hadError <= 1'b1; - end - end - end - end - - always @(posedge io_systemClk) begin - if(io_cpu_fill_valid) begin - lineLoader_address <= io_cpu_fill_payload; - end - if(when_InstructionCache_l338) begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); - end - _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; - if(when_InstructionCache_l351) begin - lineLoader_flushCounter <= 7'h0; - end - if(when_InstructionCache_l435) begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if(when_InstructionCache_l459) begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; - decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; - decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; - end - if(when_InstructionCache_l459_1) begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if(when_InstructionCache_l459_2) begin - decodeStage_hit_error <= fetchStage_hit_error; - end - end - - -endmodule - -module UartCtrlRx ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - input io_rxd, - output io_rts, - output reg io_error, - output io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlRxState_IDLE = 3'd0; - localparam UartCtrlRxState_START = 3'd1; - localparam UartCtrlRxState_DATA = 3'd2; - localparam UartCtrlRxState_PARITY = 3'd3; - localparam UartCtrlRxState_STOP = 3'd4; - - wire io_rxd_buffercc_io_dataOut; - wire _zz_sampler_value; - wire _zz_sampler_value_1; - wire _zz_sampler_value_2; - wire _zz_sampler_value_3; - wire _zz_sampler_value_4; - wire _zz_sampler_value_5; - wire _zz_sampler_value_6; - wire [2:0] _zz_when_UartCtrlRx_l139; - wire [0:0] _zz_when_UartCtrlRx_l139_1; - reg _zz_io_rts; - wire sampler_synchroniser; - wire sampler_samples_0; - reg sampler_samples_1; - reg sampler_samples_2; - reg sampler_samples_3; - reg sampler_samples_4; - reg sampler_value; - reg sampler_tick; - reg [2:0] bitTimer_counter; - reg bitTimer_tick; - wire when_UartCtrlRx_l43; - reg [2:0] bitCounter_value; - reg [6:0] break_counter; - wire break_valid; - wire when_UartCtrlRx_l69; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg [7:0] stateMachine_shifter; - reg stateMachine_validReg; - wire when_UartCtrlRx_l93; - wire when_UartCtrlRx_l103; - wire when_UartCtrlRx_l111; - wire when_UartCtrlRx_l113; - wire when_UartCtrlRx_l125; - wire when_UartCtrlRx_l136; - wire when_UartCtrlRx_l139; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; - assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); - assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); - assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); - assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); - assign _zz_sampler_value_6 = 1'b1; - assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); - assign _zz_sampler_value_2 = 1'b1; - BufferCC io_rxd_buffercc ( - .io_dataIn (io_rxd ), //i - .io_dataOut (io_rxd_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlRxState_START : stateMachine_state_string = "START "; - UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - io_error = 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - end - UartCtrlRxState_START : begin - end - UartCtrlRxState_DATA : begin - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(!when_UartCtrlRx_l125) begin - io_error = 1'b1; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - io_error = 1'b1; - end - end - end - endcase - end - - assign io_rts = _zz_io_rts; - assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; - assign sampler_samples_0 = sampler_synchroniser; - always @(*) begin - bitTimer_tick = 1'b0; - if(sampler_tick) begin - if(when_UartCtrlRx_l43) begin - bitTimer_tick = 1'b1; - end - end - end - - assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); - assign break_valid = (break_counter == 7'h68); - assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); - assign io_break = break_valid; - assign io_read_valid = stateMachine_validReg; - assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); - assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); - assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); - assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); - assign when_UartCtrlRx_l136 = (! sampler_value); - assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); - assign io_read_payload = stateMachine_shifter; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_rts <= 1'b0; - sampler_samples_1 <= 1'b1; - sampler_samples_2 <= 1'b1; - sampler_samples_3 <= 1'b1; - sampler_samples_4 <= 1'b1; - sampler_value <= 1'b1; - sampler_tick <= 1'b0; - break_counter <= 7'h0; - stateMachine_state <= UartCtrlRxState_IDLE; - stateMachine_validReg <= 1'b0; - end else begin - _zz_io_rts <= (! io_read_ready); - if(io_samplingTick) begin - sampler_samples_1 <= sampler_samples_0; - end - if(io_samplingTick) begin - sampler_samples_2 <= sampler_samples_1; - end - if(io_samplingTick) begin - sampler_samples_3 <= sampler_samples_2; - end - if(io_samplingTick) begin - sampler_samples_4 <= sampler_samples_3; - end - sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); - sampler_tick <= io_samplingTick; - if(sampler_value) begin - break_counter <= 7'h0; - end else begin - if(when_UartCtrlRx_l69) begin - break_counter <= (break_counter + 7'h01); - end - end - stateMachine_validReg <= 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - stateMachine_state <= UartCtrlRxState_START; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - stateMachine_state <= UartCtrlRxState_DATA; - if(when_UartCtrlRx_l103) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l111) begin - if(when_UartCtrlRx_l113) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_PARITY; - end - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l125) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end else begin - if(when_UartCtrlRx_l139) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(sampler_tick) begin - bitTimer_counter <= (bitTimer_counter - 3'b001); - end - if(bitTimer_tick) begin - bitCounter_value <= (bitCounter_value + 3'b001); - end - if(bitTimer_tick) begin - stateMachine_parity <= (stateMachine_parity ^ sampler_value); - end - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - bitTimer_counter <= 3'b010; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - stateMachine_shifter[bitCounter_value] <= sampler_value; - if(when_UartCtrlRx_l111) begin - bitCounter_value <= 3'b000; - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module UartCtrlTx ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - input io_cts, - output io_txd, - input io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlTxState_IDLE = 3'd0; - localparam UartCtrlTxState_START = 3'd1; - localparam UartCtrlTxState_DATA = 3'd2; - localparam UartCtrlTxState_PARITY = 3'd3; - localparam UartCtrlTxState_STOP = 3'd4; - - wire [2:0] _zz_clockDivider_counter_valueNext; - wire [0:0] _zz_clockDivider_counter_valueNext_1; - wire [2:0] _zz_when_UartCtrlTx_l93; - wire [0:0] _zz_when_UartCtrlTx_l93_1; - reg clockDivider_counter_willIncrement; - wire clockDivider_counter_willClear; - reg [2:0] clockDivider_counter_valueNext; - reg [2:0] clockDivider_counter_value; - wire clockDivider_counter_willOverflowIfInc; - wire clockDivider_counter_willOverflow; - reg [2:0] tickCounter_value; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg stateMachine_txd; - wire when_UartCtrlTx_l58; - wire when_UartCtrlTx_l73; - wire when_UartCtrlTx_l76; - wire when_UartCtrlTx_l93; - reg _zz_io_txd; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; - assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; - assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlTxState_START : stateMachine_state_string = "START "; - UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - clockDivider_counter_willIncrement = 1'b0; - if(io_samplingTick) begin - clockDivider_counter_willIncrement = 1'b1; - end - end - - assign clockDivider_counter_willClear = 1'b0; - assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); - assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); - always @(*) begin - clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); - if(clockDivider_counter_willClear) begin - clockDivider_counter_valueNext = 3'b000; - end - end - - always @(*) begin - stateMachine_txd = 1'b1; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - stateMachine_txd = 1'b0; - end - UartCtrlTxState_DATA : begin - stateMachine_txd = io_write_payload[tickCounter_value]; - end - UartCtrlTxState_PARITY : begin - stateMachine_txd = stateMachine_parity; - end - default : begin - end - endcase - end - - always @(*) begin - io_write_ready = io_break; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - io_write_ready = 1'b1; - end - end - end - UartCtrlTxState_PARITY : begin - end - default : begin - end - endcase - end - - assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); - assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); - assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); - assign io_txd = _zz_io_txd; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter_value <= 3'b000; - stateMachine_state <= UartCtrlTxState_IDLE; - _zz_io_txd <= 1'b1; - end else begin - clockDivider_counter_value <= clockDivider_counter_valueNext; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - if(when_UartCtrlTx_l58) begin - stateMachine_state <= UartCtrlTxState_START; - end - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_DATA; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - if(when_UartCtrlTx_l76) begin - stateMachine_state <= UartCtrlTxState_STOP; - end else begin - stateMachine_state <= UartCtrlTxState_PARITY; - end - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_STOP; - end - end - default : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l93) begin - stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); - end - end - end - endcase - _zz_io_txd <= (stateMachine_txd && (! io_break)); - end - end - - always @(posedge io_systemClk) begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= (tickCounter_value + 3'b001); - end - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); - end - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - tickCounter_value <= 3'b000; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - tickCounter_value <= 3'b000; - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module BufferCC_1 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - initial begin - `ifndef SYNTHESIS - buffers_0 = $urandom; - buffers_1 = $urandom; - `endif - end - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - - -endmodule - -module BufferCC ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input systemCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin deleted file mode 100644 index c68d3c6..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin +++ /dev/null @@ -1,8192 +0,0 @@ -10010111 -10010011 -00010011 -00010011 -10010011 -00010011 -01100011 -10000011 -00100011 -00010011 -10010011 -11100011 -00010011 -10010011 -01100011 -00100011 -00010011 -11100011 -11101111 -11101111 -01101111 -01100111 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 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"/projects/SSE/kmlau/install/efinity/2022.1/ipm/ip/efx_soc/efx_soc/generator/bootloader/bootloader_32K.hex" ---cpuCount 1 ---spi name=system_spi_0_io,address=0x014000,interruptId=4,width=8,ssCount=1 ---Fpu false ---uart name=system_uart_0_io,address=0x010000,interruptId=1 ---L1I true ---dCacheSize 4096 ---axiAEnable false ---onChipRamSize 0x8000 ---iCacheWays 1 ---apbSlave name=io_apbSlave_0,address=0x100000,size=65536 ---ddrAEnable false ---iCacheSize 4096 ---onChipRamAddress 0xf9000000 ---Atomic false ---PeripheralClock false ---softTap false ---customInstruction false ---apbBridgeAddress 0xf8000000 ---L1D true ---Linux false ---dCacheWays 1 ---systemFrequency 50000000 diff --git a/fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v b/fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v deleted file mode 100644 index 64c5fed..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v +++ /dev/null @@ -1,241 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module mac_pat_gen -( -//Globle Signals -input clk, -input rstn, -//Control Interface -input pat_gen_en, -input [15:0] pat_gen_num,//When value is 0, it's infinite mode -input [15:0] pat_gen_ipg, -//MAC Protocol Signals -input [47:0] dst_mac, -input [47:0] src_mac, -input [15:0] mac_dlen, -//AXI4-Stream Interface -input rclk, -input rrstn, -input [7:0] rdata, -input rvalid, -input rlast, - -output reg [7:0] tdata, -output reg tvalid, -output reg tlast, -input tready -); - -// Parameter Define -localparam IDLE = 2'h0; -localparam PAT_IPG = 2'h1; -localparam PAT_GEN = 2'h2; - -// Register Define -reg pat_gen_en_dl1; -reg pat_gen_en_dl2; -reg [1:0] cur_state; -reg [1:0] next_state; -reg pat_en; -reg infinite_en; -reg [15:0] num_cnt; -reg [15:0] ipg_cnt; -reg [15:0] pat_cnt; - -reg [15:0] pat_gen_num_r; -reg [15:0] pat_gen_ipg_r; -reg [47:0] dst_mac_r; -reg [47:0] src_mac_r; -reg [15:0] mac_dlen_r; - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) begin - pat_gen_num_r <= 16'h0; - pat_gen_ipg_r <= 16'h0; - dst_mac_r <= 48'h0; - src_mac_r <= 48'h0; - mac_dlen_r <= 16'h0; - end - else begin - pat_gen_num_r <= pat_gen_num; - pat_gen_ipg_r <= pat_gen_ipg; - dst_mac_r <= dst_mac; - src_mac_r <= src_mac; - mac_dlen_r <= mac_dlen; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - pat_gen_en_dl1 <= 1'h0; - pat_gen_en_dl2 <= 1'h0; - end - else - begin - pat_gen_en_dl1 <= pat_gen_en; - pat_gen_en_dl2 <= pat_gen_en_dl1; - end -end - -/*----------------------- FSM Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - cur_state <= IDLE; - else - cur_state <= next_state; -end - -always @(*) - begin - case(cur_state) - IDLE : - if(pat_en == 1'b1) - next_state = PAT_GEN; - else - next_state = IDLE; - - PAT_IPG : - if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) - next_state = IDLE; - else if(ipg_cnt == pat_gen_ipg_r) - next_state = PAT_GEN; - else - next_state = PAT_IPG; - - PAT_GEN : - if((tlast == 1'b1) && (tready == 1'b1)) - next_state = PAT_IPG; - else - next_state = PAT_GEN; - - default : - next_state = IDLE; - endcase - end - -/*----------------------- Generator Control Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - pat_en <= 1'h1; - else if((cur_state == IDLE) && (pat_en == 1'b1)) - pat_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - infinite_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) - infinite_en <= 1'h1; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - infinite_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - num_cnt <= 16'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - num_cnt <= pat_gen_num_r; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) - num_cnt <= num_cnt - 1'b1; -end - -/*----------------------- Pattern Counter Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ipg_cnt <= 16'h0; - else if(cur_state == PAT_IPG) - ipg_cnt <= ipg_cnt + 1'b1; - else - ipg_cnt <= 8'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_cnt <= 16'h0; - else if(cur_state != PAT_GEN) - pat_cnt <= 16'h0; - else if(tready == 1'b1) - pat_cnt <= pat_cnt + 1'b1; -end - -/*----------------------- Pattern Generator Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tvalid <= 1'b0; - else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) - tvalid <= 1'b1; - else if((tready == 1'b1) && (tlast == 1'b1)) - tvalid <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tdata <= 8'h0; - else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd14)) - case(pat_cnt[3:0]) - 4'd0 : tdata <= dst_mac_r[5*8 +: 8]; - 4'd1 : tdata <= dst_mac_r[4*8 +: 8]; - 4'd2 : tdata <= dst_mac_r[3*8 +: 8]; - 4'd3 : tdata <= dst_mac_r[2*8 +: 8]; - 4'd4 : tdata <= dst_mac_r[1*8 +: 8]; - 4'd5 : tdata <= dst_mac_r[0*8 +: 8]; - 4'd6 : tdata <= src_mac_r[5*8 +: 8]; - 4'd7 : tdata <= src_mac_r[4*8 +: 8]; - 4'd8 : tdata <= src_mac_r[3*8 +: 8]; - 4'd9 : tdata <= src_mac_r[2*8 +: 8]; - 4'd10 : tdata <= src_mac_r[1*8 +: 8]; - 4'd11 : tdata <= src_mac_r[0*8 +: 8]; - 4'd12 : tdata <= mac_dlen_r[15:8]; - 4'd13 : tdata <= mac_dlen_r[7:0]; - 4'd14 : tdata <= 8'h0;//MAC First Data - default : tdata <= tdata + 1'b1; - endcase - else if((cur_state == PAT_GEN) && (tready == 1'b1)) - tdata <= tdata + 1'b1; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tlast <= 1'b0; - else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == mac_dlen_r+16'd13)) - tlast <= 1'b1; - else if(tready == 1'b1) - tlast <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v b/fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v deleted file mode 100644 index 14508a7..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v +++ /dev/null @@ -1,139 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module mac_rx2tx -( -//Globle Signals -// -//Receive AXI4-Stream Interface -input rx_axis_clk, -input rx_axis_rstn, -input [7:0] rx_axis_mac_tdata, -input rx_axis_mac_tvalid, -input rx_axis_mac_tlast, -input rx_axis_mac_tuser, -output reg rx_axis_mac_tready, -//Transmit AXI4-Stream Interface -input tx_axis_clk, -input tx_axis_rstn, -output reg [7:0] tx_axis_mac_tdata, -output reg tx_axis_mac_tvalid, -output reg tx_axis_mac_tlast, -output reg tx_axis_mac_tuser, -input tx_axis_mac_tready -); -// Parameter Define - -// Register Define - -// Wire Define -wire [9:0] u1_data; -wire u1_wrreq; -wire u1_rdreq; -wire [9:0] u1_q; -wire u1_empty; -wire u1_almfull; -wire [10:0] u1_wrcnt; - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ - -/*----------------------- Rx Clock Region ----------------------------*/ -assign u1_almfull = (u1_wrcnt >= 2045); - -always @(posedge rx_axis_clk or negedge rx_axis_rstn) -begin - if(rx_axis_rstn == 1'b0) - rx_axis_mac_tready <= 1'b0; - else if(u1_almfull == 1'b1) - rx_axis_mac_tready <= 1'b0; - else - rx_axis_mac_tready <= 1'b1; -end - -/*----------------------- Fifo 1 Region ----------------------------*/ -DC_FIFO #( - .FIFO_MODE ("ShowAhead" ), - .DATA_WIDTH (10 ), - .FIFO_DEPTH (2048 ) -) -u1 -( - //System Signal - .Reset (!rx_axis_rstn ), - //Write Signal - .WrClk (rx_axis_clk ), - .WrEn (u1_wrreq ), - .WrDNum (u1_wrcnt ), - .WrFull ( ), - .WrData (u1_data ), - //Read Signal - .RdClk (tx_axis_clk ), - .RdEn (u1_rdreq ), - .RdDNum ( ), - .RdEmpty (u1_empty ), - .RdData (u1_q ) -); - -assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata}; -assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1); -assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1)); - -/*----------------------- Tx Clock Region ----------------------------*/ - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tvalid <= 1'b0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tvalid <= 1'b1; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tvalid <= 1'b0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tdata <= 8'h0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tdata <= u1_q[7:0]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tdata <= 8'h0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tlast <= 1'b0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tlast <= u1_q[8]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tlast <= 1'b0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tuser <= 1'b0; - else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1)) - tx_axis_mac_tuser <= u1_q[9]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tuser <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/reg_apb3.v b/fpga/ip/gTSE/T120F324_devkit/reg_apb3.v deleted file mode 100644 index 3447897..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/reg_apb3.v +++ /dev/null @@ -1,333 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module reg_apb3#( - parameter ADDR_WTH = 10 -) -( -//Globle Signals -// -//APB3 Slave Interface -input s_apb3_clk, -input s_apb3_rstn, -input [ADDR_WTH-1:0] s_apb3_paddr, -input s_apb3_psel, -input s_apb3_penable, -output reg s_apb3_pready, -input s_apb3_pwrite,//0:rd; 1:wr; -input [31:0] s_apb3_pwdata, -output reg [31:0] s_apb3_prdata, -output wire s_apb3_pslverror, -//Cfg Space Registers -//--Example Registers Field -output reg mac_sw_rst, -output reg axi4_st_mux_select, -output reg pat_mux_select, -output reg udp_pat_gen_en, -output reg mac_pat_gen_en, -output reg [15:0] pat_gen_num, -output reg [15:0] pat_gen_ipg, -output reg [47:0] pat_dst_mac, -output reg [47:0] pat_src_mac, -output reg [15:0] pat_mac_dlen, -output reg [31:0] pat_src_ip, -output reg [31:0] pat_dst_ip, -output reg [15:0] pat_src_port, -output reg [15:0] pat_dst_port, -output reg [15:0] pat_udp_dlen, -output reg [1:0] clkmux_sel -); -// Parameter Define - -// Register Define -reg [ADDR_WTH-3:0] loc_addr; -reg loc_wr_vld; -reg loc_rd_vld; - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -//apb3 interface -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - loc_addr <= {ADDR_WTH-2{1'b0}}; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) - loc_addr <= s_apb3_paddr[2+:ADDR_WTH-2]; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - loc_wr_vld <= 1'b0; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - loc_wr_vld <= 1'b1; - else - loc_wr_vld <= 1'b0; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - loc_rd_vld <= 1'b0; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) - loc_rd_vld <= 1'b1; - else - loc_rd_vld <= 1'b0; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - s_apb3_pready <= 1'b0; - else if((loc_wr_vld == 1'b1) || (loc_rd_vld == 1'b1)) - s_apb3_pready <= 1'b1; - else - s_apb3_pready <= 1'b0; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - s_apb3_prdata <= 32'h0; - else if(loc_rd_vld == 1'b1) - begin - case(loc_addr) - //Example Registers Field - 'h080 : s_apb3_prdata <= {31'h0,mac_sw_rst}; - 'h081 : s_apb3_prdata <= {30'h0,pat_mux_select,axi4_st_mux_select}; - 'h082 : s_apb3_prdata <= {30'h0,mac_pat_gen_en,udp_pat_gen_en}; - 'h083 : s_apb3_prdata <= {pat_gen_ipg,pat_gen_num}; - 'h084 : s_apb3_prdata <= pat_dst_mac[31:0]; - 'h085 : s_apb3_prdata <= {16'h0,pat_dst_mac[47:32]}; - 'h086 : s_apb3_prdata <= pat_src_mac[31:0]; - 'h087 : s_apb3_prdata <= {16'h0,pat_src_mac[47:32]}; - 'h088 : s_apb3_prdata <= {16'h0,pat_mac_dlen}; - 'h089 : s_apb3_prdata <= pat_src_ip; - 'h08a : s_apb3_prdata <= pat_dst_ip; - 'h08b : s_apb3_prdata <= {pat_dst_port,pat_src_port}; - 'h08c : s_apb3_prdata <= {16'h0,pat_udp_dlen}; - 'h08d : s_apb3_prdata <= {30'h0,clkmux_sel}; - endcase - end -end - -assign s_apb3_pslverror = 1'b0; - -/*----------------------------------------------------------------------------------*\ - Register Space -- Example Registers Field -\*----------------------------------------------------------------------------------*/ -//loc_addr = 0x080; axi_addr = 0x200; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - mac_sw_rst <= 1'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h080)) - begin - mac_sw_rst <= s_apb3_pwdata[0]; - end -end - -//loc_addr = 0x081; axi_addr = 0x204; RW; -//[axi4_st_mux_select] 0:pat tx mode; 1:rx2tx loopback mode; -//[pat_mux_select] 0:udp pat; 1:mac pat; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - axi4_st_mux_select <= 1'h0; - pat_mux_select <= 1'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h081)) - begin - axi4_st_mux_select <= s_apb3_pwdata[0]; - pat_mux_select <= s_apb3_pwdata[1]; - end -end - -//loc_addr = 0x082; axi_addr = 0x208; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - udp_pat_gen_en <= 1'h0; - mac_pat_gen_en <= 1'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h082)) - begin - udp_pat_gen_en <= s_apb3_pwdata[0]; - mac_pat_gen_en <= s_apb3_pwdata[1]; - end -end - -//loc_addr = 0x083; axi_addr = 0x20c; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_gen_num <= 16'h0; - pat_gen_ipg <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h083)) - begin - pat_gen_num <= s_apb3_pwdata[15:0]; - pat_gen_ipg <= s_apb3_pwdata[31:16]; - end -end - -//loc_addr = 0x084; axi_addr = 0x210; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_dst_mac[31:0] <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h084)) - begin - pat_dst_mac[31:0] <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x085; axi_addr = 0x214; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_dst_mac[47:32] <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h085)) - begin - pat_dst_mac[47:32] <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x086; axi_addr = 0x218; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_mac[31:0] <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h086)) - begin - pat_src_mac[31:0] <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x087; axi_addr = 0x21c; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_mac[47:32] <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h087)) - begin - pat_src_mac[47:32] <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x088; axi_addr = 0x220; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_mac_dlen <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h088)) - begin - pat_mac_dlen <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x089; axi_addr = 0x224; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_ip <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h089)) - begin - pat_src_ip <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x08a; axi_addr = 0x228; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_dst_ip <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08a)) - begin - pat_dst_ip <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x08b; axi_addr = 0x22c; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_port <= 16'h0; - pat_dst_port <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08b)) - begin - pat_src_port <= s_apb3_pwdata[15:0]; - pat_dst_port <= s_apb3_pwdata[31:16]; - end -end - -//loc_addr = 0x08c; axi_addr = 0x230; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_udp_dlen <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08c)) - begin - pat_udp_dlen <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x08d; axi_addr = 0x234; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - clkmux_sel <= 2'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08d)) - begin - clkmux_sel <= s_apb3_pwdata[1:0]; - end -end - - -/*----------------------------------------------------------------------------------*\ - Register Space -- The End -\*----------------------------------------------------------------------------------*/ - -endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v b/fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v deleted file mode 100644 index e7a1f19..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v +++ /dev/null @@ -1,206 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`timescale 1 ns / 1 ns -module rgmii_2_rmii ( - input clk_50m, //50Mhz refclock - input rst_n, - //conduit - input [2:0] eth_speed, - //rgmii interface - input [3:0] rgmii_txd, - input rgmii_tx_ctl, - output wire [3:0] rgmii_rxd, - output wire rgmii_rx_ctl, - output reg rgmii_rxc, - //rmii interface - output wire rmii_clk, - output reg [1:0] rmii_txd, - output reg rmii_txen, - input [1:0] rmii_rxd, - input rmii_crsdv -); - -wire [3:0] rxd_c; -wire rx_ctl_c; -reg [3:0] rxd_r; -reg rx_ctl_r; -reg rmii_crsdv_r, shift_en; -reg [4:0] txd_cnt, rxd_cnt; -reg [3:0] rxd_shiftreg; -reg [1:0] shift2; -reg [19:0] shift20; -reg [1:0] rx_ctl_p2; -reg [19:0] rx_ctl_p20; - -assign rmii_clk = ~clk_50m; //create 180deg phaseshift - -/*--------------- TX path ---------------------*/ -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - txd_cnt <= 5'd0; - end - else if (rgmii_tx_ctl) begin - if (((eth_speed == 3'h2) && txd_cnt == 5'd1) || - ((eth_speed == 3'h1) && txd_cnt == 5'd19)) begin - txd_cnt <= 5'd0; - end - else begin - txd_cnt <= txd_cnt + 5'd1; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rmii_txen <= 1'b0; - end - else begin - rmii_txen <= rgmii_tx_ctl; - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rmii_txd <= 2'b00; - end - else begin - if ((eth_speed == 3'h2) && txd_cnt == 5'd0) begin - rmii_txd <= rgmii_txd[1:0]; - end - else if ((eth_speed == 3'h2) && txd_cnt == 5'd1) begin - rmii_txd <= rgmii_txd[3:2]; - end - - if ((eth_speed == 3'h1) && txd_cnt == 5'd0) begin - rmii_txd <= rgmii_txd[1:0]; - end - else if ((eth_speed == 3'h1) && txd_cnt == 5'd10) begin - rmii_txd <= rgmii_txd[3:2]; - end - end -end -/*------------------ end of TX path ------------------------*/ - -/*------------ RX path ------------------*/ -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rxd_cnt <= 5'd0; - end - else if (rmii_crsdv) begin - if (((eth_speed == 3'h2) && rxd_cnt == 5'd1) || ((eth_speed == 3'h1) && rxd_cnt == 5'd19)) begin - rxd_cnt <= 5'd0; - end - else begin - rxd_cnt <= rxd_cnt + 5'd1; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rxd_shiftreg <= 4'd0; - end - else if (rmii_crsdv) begin - if (eth_speed == 3'h2 || ((eth_speed == 3'h1) && (rxd_cnt == 5'd0 || rxd_cnt == 5'd10))) begin - rxd_shiftreg <= {rmii_rxd, rxd_shiftreg[3:2]}; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - shift2 <= 2'b1; - shift20 <= 20'b1; - end - else begin - shift2 <= {shift2[0],shift2[1]}; - shift20 <= {shift20[18:0],shift20[19]}; - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rgmii_rxc <= 1'b0; - end - else begin - if ((eth_speed == 3'h2 && shift2[1]) || (eth_speed == 3'h1 && (shift20[10]))) begin - rgmii_rxc <= 1'b1; - end - else if ((eth_speed == 3'h2 && shift2[0]) || (eth_speed == 3'h1 && (shift20[0]))) begin - rgmii_rxc <= 1'b0; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rx_ctl_p2 <= 2'd0; - rx_ctl_p20 <= 20'd0; - end - else begin - rx_ctl_p2 <= {rmii_crsdv , rx_ctl_p2[1]}; - rx_ctl_p20 <= {rmii_crsdv, rx_ctl_p20[19:1]}; - end -end - -/*---- shift rxd & rx_ctl so that they are not edge align with rgmii_rxc ----*/ -assign rxd_c = (rxd_cnt == 5'd0) ? rxd_shiftreg : rxd_r; -assign rx_ctl_c = (eth_speed == 3'h2) ? rx_ctl_p2[0] : rx_ctl_p20[0]; - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rxd_r <= 4'd0; - rx_ctl_r <= 1'd0; - rmii_crsdv_r <= 1'd0; - end - else begin - rxd_r <= rxd_c; - rx_ctl_r <= rx_ctl_c; - rmii_crsdv_r <= rmii_crsdv; - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - shift_en <= 1'd0; - end // to detect if rmii_crsdv assert at the posedge of rgmii_rxc, delay rgmii_rxd & rgmii_rx_ctl if they are aligned with rgmii_rxc - else if (rmii_crsdv && ~rmii_crsdv_r) begin - if (((eth_speed == 3'h2) && shift2[0]) || ((eth_speed == 3'h1) && shift20[11])) begin - shift_en <= 1'd1; - end - else begin - shift_en <= 1'd0; - end - end -end - -assign rgmii_rxd = shift_en ? rxd_r : rxd_c; -assign rgmii_rx_ctl = shift_en ? rx_ctl_r : rx_ctl_c; -/*--------------------------------------------------------*/ -/*------------------ end of RX path ------------------------*/ -endmodule \ No newline at end of file diff --git a/fpga/ip/gTSE/T120F324_devkit/temac_ex.peri.xml b/fpga/ip/gTSE/T120F324_devkit/temac_ex.peri.xml deleted file mode 100644 index bbc0cdc..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/temac_ex.peri.xml +++ /dev/null @@ -1,131 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/ip/gTSE/T120F324_devkit/temac_ex.v b/fpga/ip/gTSE/T120F324_devkit/temac_ex.v deleted file mode 100644 index 15d4a24..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/temac_ex.v +++ /dev/null @@ -1,563 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -//`include "header.v" // use JTAG hard block -module temac_ex -( -//Globle Signals -//----pll_0 -input clk, -input clk_125m, -input pll_0_locked, -input sw6, -output wire pll_rstn, - -//TEMAC PHY RGMII Interface -output wire [3:0] rgmii_txd_HI, -output wire [3:0] rgmii_txd_LO, -output wire rgmii_txc_HI, -output wire rgmii_txc_LO, -input [3:0] rgmii_rxd_HI, -input [3:0] rgmii_rxd_LO, -`ifdef TITANIUM - output wire rgmii_tx_ctl_HI, - output wire rgmii_tx_ctl_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input mux_clk, - output [1:0] mux_clk_sw, -`else - input rgmii_rxc, - output wire rgmii_tx_ctl, - input rgmii_rx_ctl, -`endif -//TEMAC PHY Ctr Interface -output wire phy_rstn, -//hardware Jtag Interface -`ifndef SIM_MODE -`ifndef SOFT_TAP -input jtag_inst1_TCK, -input jtag_inst1_TDI, -output wire jtag_inst1_TDO, -input jtag_inst1_SEL, -input jtag_inst1_CAPTURE, -input jtag_inst1_SHIFT, -input jtag_inst1_UPDATE, -input jtag_inst1_RESET, -`else -//software Jtag Interface -input io_jtag_tms, -input io_jtag_tdi, -output wire io_jtag_tdo, -input io_jtag_tck, -`endif - -//Debug Signals -//output wire [1:0] debug_led -output wire system_uart_0_io_txd, -input system_uart_0_io_rxd, -`endif - -output system_spi_0_io_sclk_write, -output system_spi_0_io_data_0_writeEnable, -input system_spi_0_io_data_0_read, -output system_spi_0_io_data_0_write, -output system_spi_0_io_data_1_writeEnable, -input system_spi_0_io_data_1_read, -output system_spi_0_io_data_1_write, -output system_spi_0_io_ss, - -//TEMAC PHY MDIO Interface -input phy_mdi, -output wire phy_mdo, -output wire phy_mdo_en, -output wire phy_mdc -); -// Parameter Define -`include "gTSE_define.svh" - -// Register Define - -// Wire Define -wire clk_50m; -wire clk_50m_rstn; -wire mac_reset; -wire proto_reset; -wire mac_rstn; -//AXI4-Stream Interface -wire rx_axis_clk; -wire [7:0] rx_axis_mac_tdata; -wire rx_axis_mac_tvalid; -wire rx_axis_mac_tlast; -wire rx_axis_mac_tuser; -wire rx_axis_mac_tready; -wire tx_axis_clk; -wire [7:0] tx_axis_mac_tdata; -wire tx_axis_mac_tvalid; -wire tx_axis_mac_tlast; -wire tx_axis_mac_tuser; -wire tx_axis_mac_tready; -wire [7:0] udp_tx_axis_mac_tdata; -wire udp_tx_axis_mac_tvalid; -wire udp_tx_axis_mac_tlast; -wire udp_tx_axis_mac_tready; -wire [7:0] mac_tx_axis_mac_tdata; -wire mac_tx_axis_mac_tvalid; -wire mac_tx_axis_mac_tlast; -wire mac_tx_axis_mac_tready; -wire [7:0] pat_tx_axis_mac_tdata; -wire pat_tx_axis_mac_tvalid; -wire pat_tx_axis_mac_tlast; -wire pat_tx_axis_mac_tuser; -wire pat_tx_axis_mac_tready; -wire [7:0] loop_tx_axis_mac_tdata; -wire loop_tx_axis_mac_tvalid; -wire loop_tx_axis_mac_tlast; -wire loop_tx_axis_mac_tuser; -wire loop_tx_axis_mac_tready; -//RiscV APB3 Interface -wire [15:0] apb3_paddr; -wire apb3_psel; -wire apb3_penable; -wire apb3_pready; -wire apb3_pwrite; -wire [31:0] apb3_pwdata; -wire [31:0] apb3_prdata; -wire apb3_pslverror; -//Mac APB3 Interface -wire [9:0] mac_apb3_paddr; -wire mac_apb3_psel; -wire mac_apb3_penable; -wire mac_apb3_pready; -wire mac_apb3_pwrite; -wire [31:0] mac_apb3_pwdata; -wire [31:0] mac_apb3_prdata; -wire mac_apb3_pslverror; -//Ex APB3 Interface -wire [9:0] ex_apb3_paddr; -wire ex_apb3_psel; -wire ex_apb3_penable; -wire ex_apb3_pready; -wire ex_apb3_pwrite; -wire [31:0] ex_apb3_pwdata; -wire [31:0] ex_apb3_prdata; -wire ex_apb3_pslverror; -//AXI4-Lite Interface -wire [9:0] axi_awaddr; -wire axi_awvalid; -wire axi_awready; -wire [31:0] axi_wdata; -wire axi_wvalid; -wire axi_wready; -wire [1:0] axi_bresp; -wire axi_bvalid; -wire axi_bready; -wire [9:0] axi_araddr; -wire axi_arvalid; -wire axi_arready; -wire [1:0] axi_rresp; -wire [31:0] axi_rdata; -wire axi_rvalid; -wire axi_rready; -//Cfg Space Registers -wire mac_sw_rst; -wire axi4_st_mux_select; -wire pat_mux_select; -wire udp_pat_gen_en; -wire mac_pat_gen_en; -wire [15:0] pat_gen_num; -wire [15:0] pat_gen_ipg; -wire [47:0] pat_dst_mac; -wire [47:0] pat_src_mac; -wire [15:0] pat_mac_dlen; -wire [31:0] pat_src_ip; -wire [31:0] pat_dst_ip; -wire [15:0] pat_src_port; -wire [15:0] pat_dst_port; -wire [15:0] pat_udp_dlen; - -//TSE DDIO -`ifdef TITANIUM - wire rgmii_rxc; - - assign rgmii_rxc = mux_clk; -`else - wire rgmii_rx_ctl_LO; - wire rgmii_rx_ctl_HI; - wire rgmii_tx_ctl_LO; - wire rgmii_tx_ctl_HI; - - assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ; - assign rgmii_rx_ctl_HI = rgmii_rx_ctl ; - assign rgmii_rx_ctl_LO = rgmii_rx_ctl ; -`endif -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -assign pll_rstn = 1; -/*----------------------- Clock Region -----------------------*/ -//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above. -//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has -//high combi logic and couldn't meet timing at 125Mhz. -assign rx_axis_clk = clk;//clk_125m; -assign tx_axis_clk = clk;//clk_125m; - - -/*----------------------- Reset Region -----------------------*/ -//assign pll_0_reset = 1'b0; -assign clk_50m = clk; -assign phy_rstn = sw6; -assign clk_50m_rstn = pll_0_locked; -assign mac_reset = ~pll_0_locked; -assign proto_reset = mac_sw_rst; -assign mac_rstn = ~(mac_reset || proto_reset); - -/*----------------------- MCU Module ----------------------------*/ -`ifndef SIM_MODE -sapphire u_mcu -( -//user custom ports - //SOC - .io_systemClk (clk_50m ), - .io_asyncReset (1'b0 ), - .system_uart_0_io_txd (system_uart_0_io_txd ), - .system_uart_0_io_rxd (system_uart_0_io_rxd ), - .system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ), - .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ), - .system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ), - .system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ), - .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ), - .system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ), - .system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ), - .system_spi_0_io_ss (system_spi_0_io_ss ), - .jtagCtrl_tck (jtag_inst1_TCK ), - .jtagCtrl_tdi (jtag_inst1_TDI ), - .jtagCtrl_tdo (jtag_inst1_TDO ), - .jtagCtrl_enable (jtag_inst1_SEL ), - .jtagCtrl_capture (jtag_inst1_CAPTURE ), - .jtagCtrl_shift (jtag_inst1_SHIFT ), - .jtagCtrl_update (jtag_inst1_UPDATE ), - .jtagCtrl_reset (jtag_inst1_RESET ), -//APB3 Master Interface - .io_apbSlave_0_PADDR (apb3_paddr ), - .io_apbSlave_0_PSEL (apb3_psel ), - .io_apbSlave_0_PENABLE (apb3_penable ), - .io_apbSlave_0_PREADY (apb3_pready ), - .io_apbSlave_0_PWRITE (apb3_pwrite ), - .io_apbSlave_0_PWDATA (apb3_pwdata ), - .io_apbSlave_0_PRDATA (apb3_prdata ), - .io_apbSlave_0_PSLVERROR (apb3_pslverror ) -); -`endif - -assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready; -assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata; -assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror; - -assign mac_apb3_paddr = apb3_paddr[9:0]; -assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0; -assign mac_apb3_penable = apb3_penable; -assign mac_apb3_pwrite = apb3_pwrite; -assign mac_apb3_pwdata = apb3_pwdata; - -assign ex_apb3_paddr = apb3_paddr[9:0]; -assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0; -assign ex_apb3_penable = apb3_penable; -assign ex_apb3_pwrite = apb3_pwrite; -assign ex_apb3_pwdata = apb3_pwdata; - -apb3_2_axi4_lite#( - .ADDR_WTH (10 ) -) -u_apb3_2_axi4_lite -( -//Globle Signals - .clk (clk_50m ), - .rstn (clk_50m_rstn ), -//APB3 Slave Interface - .s_apb3_paddr (mac_apb3_paddr ), - .s_apb3_psel (mac_apb3_psel ), - .s_apb3_penable (mac_apb3_penable ), - .s_apb3_pready (mac_apb3_pready ), - .s_apb3_pwrite (mac_apb3_pwrite ), - .s_apb3_pwdata (mac_apb3_pwdata ), - .s_apb3_prdata (mac_apb3_prdata ), - .s_apb3_pslverror (mac_apb3_pslverror ), -//AXI4-Lite Master Interface - .m_axi_awaddr (axi_awaddr ), - .m_axi_awvalid (axi_awvalid ), - .m_axi_awready (axi_awready ), - .m_axi_wdata (axi_wdata ), - .m_axi_wvalid (axi_wvalid ), - .m_axi_wready (axi_wready ), - .m_axi_bresp (axi_bresp ), - .m_axi_bvalid (axi_bvalid ), - .m_axi_bready (axi_bready ), - .m_axi_araddr (axi_araddr ), - .m_axi_arvalid (axi_arvalid ), - .m_axi_arready (axi_arready ), - .m_axi_rresp (axi_rresp ), - .m_axi_rdata (axi_rdata ), - .m_axi_rvalid (axi_rvalid ), - .m_axi_rready (axi_rready ) -); - -reg_apb3#( - .ADDR_WTH (10 ) -) -u_reg_apb3 -( -//Globle Signals -// -//APB3 Slave Interface - .s_apb3_clk (clk_50m ), - .s_apb3_rstn (clk_50m_rstn ), - .s_apb3_paddr (ex_apb3_paddr ), - .s_apb3_psel (ex_apb3_psel ), - .s_apb3_penable (ex_apb3_penable ), - .s_apb3_pready (ex_apb3_pready ), - .s_apb3_pwrite (ex_apb3_pwrite ), - .s_apb3_pwdata (ex_apb3_pwdata ), - .s_apb3_prdata (ex_apb3_prdata ), - .s_apb3_pslverror (ex_apb3_pslverror ), -//Cfg Space Registers -//--Example Registers Field - .mac_sw_rst (mac_sw_rst ), - .axi4_st_mux_select (axi4_st_mux_select ), - .pat_mux_select (pat_mux_select ), - .udp_pat_gen_en (udp_pat_gen_en ), - .mac_pat_gen_en (mac_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), - .pat_dst_mac (pat_dst_mac ), - .pat_src_mac (pat_src_mac ), - .pat_mac_dlen (pat_mac_dlen ), - .pat_src_ip (pat_src_ip ), - .pat_dst_ip (pat_dst_ip ), - .pat_src_port (pat_src_port ), - .pat_dst_port (pat_dst_port ), - .pat_udp_dlen (pat_udp_dlen ), - .clkmux_sel (mux_clk_sw ) -); - -//generate if (PATTERN_TYPE == 0) begin //UDP -// -//assign mac_tx_axis_mac_tdata = 8'h0; -//assign mac_tx_axis_mac_tvalid = 1'b0; -//assign mac_tx_axis_mac_tlast = 1'b0; - -/*----------------------- The Ethernet Pattern Module -----------------------*/ -udp_pat_gen u_udp_pat_gen -( -//Globle Signals - .clk (tx_axis_clk ), - .rstn (mac_rstn ), -//Control Interface - .pat_gen_en (udp_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), -//MAC Protocol Signals - .dst_mac (pat_dst_mac ), - .src_mac (pat_src_mac ), -//IP Protocol Signals - .src_ip (pat_src_ip ), - .dst_ip (pat_dst_ip ), -//UDP Protocol Signals - .src_port (pat_src_port ), - .dst_port (pat_dst_port ), - .udp_dlen (pat_udp_dlen ), -//AXI4-Stream Interface - .rclk (rx_axis_clk ), - .rrstn (mac_rstn ), - .rdata (rx_axis_mac_tdata ), - .rvalid (rx_axis_mac_tvalid ), - .rlast (rx_axis_mac_tlast ), - .tdata (udp_tx_axis_mac_tdata ), - .tvalid (udp_tx_axis_mac_tvalid ), - .tlast (udp_tx_axis_mac_tlast ), - .tready (udp_tx_axis_mac_tready ) -); -//end -//else begin //MAC -// -//assign udp_tx_axis_mac_tdata = 8'h0; -//assign udp_tx_axis_mac_tvalid = 1'b0; -//assign udp_tx_axis_mac_tlast = 1'b0; - -mac_pat_gen u_mac_pat_gen -( -//Globle Signals - .clk (tx_axis_clk ), - .rstn (mac_rstn ), -//Control Interface - .pat_gen_en (mac_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), -//MAC Protocol Signals - .dst_mac (pat_dst_mac ), - .src_mac (pat_src_mac ), - .mac_dlen (pat_mac_dlen ), -//AXI4-Stream Interface - .rclk (rx_axis_clk ), - .rrstn (mac_rstn ), - .rdata (rx_axis_mac_tdata ), - .rvalid (rx_axis_mac_tvalid ), - .rlast (rx_axis_mac_tlast ), - .tdata (mac_tx_axis_mac_tdata ), - .tvalid (mac_tx_axis_mac_tvalid ), - .tlast (mac_tx_axis_mac_tlast ), - .tready (mac_tx_axis_mac_tready ) -); -//end -//endgenerate - -axi4_st_mux u_pat_mux -( -//Globle Signals - .mux_select (pat_mux_select ),//0:udp pat; 1:mac pat; -//Mux In 0 Interface - .tdata0 (udp_tx_axis_mac_tdata ), - .tvalid0 (udp_tx_axis_mac_tvalid ), - .tlast0 (udp_tx_axis_mac_tlast ), - .tuser0 (1'b0 ), - .tready0 (udp_tx_axis_mac_tready ), -//Mux In 1 Interface - .tdata1 (mac_tx_axis_mac_tdata ), - .tvalid1 (mac_tx_axis_mac_tvalid ), - .tlast1 (mac_tx_axis_mac_tlast ), - .tuser1 (1'b0 ), - .tready1 (mac_tx_axis_mac_tready ), -//Mux Out Interface - .tdata (pat_tx_axis_mac_tdata ), - .tvalid (pat_tx_axis_mac_tvalid ), - .tlast (pat_tx_axis_mac_tlast ), - .tuser (pat_tx_axis_mac_tuser ), - .tready (pat_tx_axis_mac_tready ) -); - -/*----------------------- The Tx AXI4 St Mux Module -----------------------*/ -axi4_st_mux u_tx_axi4st_mux -( -//Globle Signals - .mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback; -//Mux In 0 Interface - .tdata0 (pat_tx_axis_mac_tdata ), - .tvalid0 (pat_tx_axis_mac_tvalid ), - .tlast0 (pat_tx_axis_mac_tlast ), - .tuser0 (pat_tx_axis_mac_tuser ), - .tready0 (pat_tx_axis_mac_tready ), -//Mux In 1 Interface - .tdata1 (loop_tx_axis_mac_tdata ), - .tvalid1 (loop_tx_axis_mac_tvalid ), - .tlast1 (loop_tx_axis_mac_tlast ), - .tuser1 (loop_tx_axis_mac_tuser ), - .tready1 (loop_tx_axis_mac_tready ), -//Mux Out Interface - .tdata (tx_axis_mac_tdata ), - .tvalid (tx_axis_mac_tvalid ), - .tlast (tx_axis_mac_tlast ), - .tuser (tx_axis_mac_tuser ), - .tready (tx_axis_mac_tready ) -); - -/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/ -gTSE u_tsemac -( -//Globle Signals - .mac_reset (mac_reset ), - .proto_reset (proto_reset ), - .tx_mac_aclk (clk_125m ), - .rx_mac_aclk ( ), - .eth_speed ( ), -//Receive AXI4-Stream Interface - .rx_axis_clk (rx_axis_clk ), - .rx_axis_mac_tdata (rx_axis_mac_tdata ), - .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), - .rx_axis_mac_tlast (rx_axis_mac_tlast ), - .rx_axis_mac_tstrb (), - .rx_axis_mac_tuser (rx_axis_mac_tuser ), - .rx_axis_mac_tready (rx_axis_mac_tready ), -//Transmit AXI4-Stream Interface - .tx_axis_clk (tx_axis_clk ), - .tx_axis_mac_tdata (tx_axis_mac_tdata ), - .tx_axis_mac_tvalid (tx_axis_mac_tvalid ), - .tx_axis_mac_tlast (tx_axis_mac_tlast ), - .tx_axis_mac_tstrb (1'b1 ), - .tx_axis_mac_tuser (tx_axis_mac_tuser ), - .tx_axis_mac_tready (tx_axis_mac_tready ), - //--RGMII Interface - .rgmii_txd_HI (rgmii_txd_HI ), - .rgmii_txd_LO (rgmii_txd_LO ), - .rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ), - .rgmii_txc_HI (rgmii_txc_HI ), - .rgmii_txc_LO (rgmii_txc_LO ), - .rgmii_rxd_HI (rgmii_rxd_HI ), - .rgmii_rxd_LO (rgmii_rxd_LO ), - .rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ), - .rgmii_rxc (rgmii_rxc ), - //AXI4-Lite Interface - .s_axi_aclk (clk_50m ), - .s_axi_awaddr (axi_awaddr ), - .s_axi_awvalid (axi_awvalid ), - .s_axi_awready (axi_awready ), - .s_axi_wdata (axi_wdata ), - .s_axi_wvalid (axi_wvalid ), - .s_axi_wready (axi_wready ), - .s_axi_bresp (axi_bresp ), - .s_axi_bvalid (axi_bvalid ), - .s_axi_bready (axi_bready ), - .s_axi_araddr (axi_araddr ), - .s_axi_arvalid (axi_arvalid ), - .s_axi_arready (axi_arready ), - .s_axi_rresp (axi_rresp ), - .s_axi_rdata (axi_rdata ), - .s_axi_rvalid (axi_rvalid ), - .s_axi_rready (axi_rready ), - //MDIO Interface - .Mdo (phy_mdo ), - .MdoEn (phy_mdo_en ), - .Mdi (phy_mdi ), - .Mdc (phy_mdc ) -); - -/*----------------------- User Interface Loopback Module ----------------------------*/ -mac_rx2tx u_mac_rx2tx -( -//Globle Signals -// -//Receive AXI4-Stream Interface - .rx_axis_clk (rx_axis_clk ), - .rx_axis_rstn (mac_rstn ), - .rx_axis_mac_tdata (rx_axis_mac_tdata ), - .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), - .rx_axis_mac_tlast (rx_axis_mac_tlast ), - .rx_axis_mac_tuser (rx_axis_mac_tuser ), - .rx_axis_mac_tready (rx_axis_mac_tready ), -//Transmit AXI4-Stream Interface - .tx_axis_clk (tx_axis_clk ), - .tx_axis_rstn (mac_rstn ), - .tx_axis_mac_tdata (loop_tx_axis_mac_tdata ), - .tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ), - .tx_axis_mac_tlast (loop_tx_axis_mac_tlast ), - .tx_axis_mac_tuser (loop_tx_axis_mac_tuser ), - .tx_axis_mac_tready (loop_tx_axis_mac_tready ) -); - -endmodule - diff --git a/fpga/ip/gTSE/T120F324_devkit/temac_ex.xml b/fpga/ip/gTSE/T120F324_devkit/temac_ex.xml deleted file mode 100644 index e56c1a9..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/temac_ex.xml +++ /dev/null @@ -1,92 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/ip/gTSE/T120F324_devkit/timing.sdc b/fpga/ip/gTSE/T120F324_devkit/timing.sdc deleted file mode 100644 index f4e30be..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/timing.sdc +++ /dev/null @@ -1,53 +0,0 @@ -################################## Clock Constraints ########################## -create_clock -period 20.00 clk -create_clock -period 8.00 clk_125m -create_clock -waveform {2.00 6.00} -period 8.00 clk_125m_90deg -create_clock -period 8.00 rgmii_rxc -create_clock -period 100.00 [get_ports {jtag_inst1_TCK}] - -#################################################################################################################################### -# Timing Mode Constrains -#################################################################################################################################### -set_clock_groups -exclusive -group {clk} -group {clk_125m} -group {clk_125m_90deg} -group {rgmii_rxc} -group {jtag_inst1_TCK} - -# GPIO Constraints -#################### -set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] -set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] -set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] -set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] -set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] -set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] -set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] -set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] -set_output_delay -clock_fall -clock clk_125m_90deg -max -4.700 [get_ports {rgmii_txc_LO rgmii_txc_HI}] -set_output_delay -clock_fall -clock clk_125m_90deg -min -2.571 [get_ports {rgmii_txc_LO rgmii_txc_HI}] -set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] -set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] -set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] -set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] -set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] -set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] -set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] -set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] - -# LVDS RX GPIO Constraints -############################ -set_input_delay -clock rgmii_rxc -max 6.100 [get_ports {rgmii_rx_ctl}] -set_input_delay -clock rgmii_rxc -min 3.050 [get_ports {rgmii_rx_ctl}] -set_output_delay -clock clk_125m -max -5.210 [get_ports {rgmii_tx_ctl}] -set_output_delay -clock clk_125m -min -2.480 [get_ports {rgmii_tx_ctl}] - -# LVDS Rx Constraints -#################### - -# JTAG Constraints -#################### -set_output_delay -clock jtag_inst1_TCK -max 0.111 [get_ports {jtag_inst1_TDO}] -set_output_delay -clock jtag_inst1_TCK -min 0.053 [get_ports {jtag_inst1_TDO}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.267 [get_ports {jtag_inst1_CAPTURE}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.134 [get_ports {jtag_inst1_CAPTURE}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.231 [get_ports {jtag_inst1_SEL}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.116 [get_ports {jtag_inst1_SEL}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.321 [get_ports {jtag_inst1_SHIFT}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.161 [get_ports {jtag_inst1_SHIFT}] diff --git a/fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v b/fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v deleted file mode 100644 index e5626c3..0000000 --- a/fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v +++ /dev/null @@ -1,497 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module udp_pat_gen -( -//Globle Signals -input clk, -input rstn, -//Control Interface -input pat_gen_en, -input [15:0] pat_gen_num,//When value is 0, it's infinite mode -input [15:0] pat_gen_ipg, -//MAC Protocol Signals -input [47:0] dst_mac, -input [47:0] src_mac, -//IP Protocol Signals -input [31:0] src_ip, -input [31:0] dst_ip, -//UDP Protocol Signals -input [15:0] udp_dlen, -input [15:0] src_port, -input [15:0] dst_port, -//AXI4-Stream Interface -input rclk, -input rrstn, -input [7:0] rdata, -input rvalid, -input rlast, - -output reg [7:0] tdata, -output reg tvalid, -output reg tlast, -input tready -); - -// Parameter Define -localparam VER = 4'h4;//IPv4 -localparam IHL = 4'h5;//Internet Header Length -localparam TOS = 8'h0;//Type Of Service -localparam FLG = 3'h0;//Flags -localparam TTL = 8'h40;//Time To Live -localparam PTC = 8'h11;//UDP Protocol - -localparam IDLE = 3'h0; -localparam UDP_CHKSUM = 3'h1; -localparam IP_CHKSUM = 3'h2; -localparam PAT_IPG = 3'h3; -localparam PAT_GEN = 3'h4; - -// Register Define -reg [2:0] cur_state; -reg [2:0] next_state; -reg pat_gen_en_dl1; -reg pat_gen_en_dl2; -reg [31:0] src_ip_r; -reg [31:0] dst_ip_r; -reg [15:0] src_port_r; -reg [15:0] dst_port_r; -reg pat_en; -reg infinite_en; -reg [15:0] num_cnt; -reg [15:0] udp_chksum_cnt; -reg [3:0] ip_chksum_cnt; -reg [15:0] ipg_cnt; -reg [15:0] pat_cnt; -reg [15:0] udp_len; -reg [15:0] udp_chksum_num; -reg [7:0] udp_data_h; -reg [7:0] udp_data_l; -reg [16:0] udp_chksum_r; -reg [15:0] udp_chksum; -reg [15:0] ip_len; -reg [15:0] ip_id; -reg [12:0] ip_ofs; -reg [16:0] ip_chksum_r; -reg [15:0] ip_chksum; - -reg [15:0] pat_gen_num_r; -reg [15:0] pat_gen_ipg_r; -reg [47:0] dst_mac_r; -reg [47:0] src_mac_r; -reg [15:0] udp_dlen_r; - -// Wire Define -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) begin - pat_gen_num_r <= 16'h0; - pat_gen_ipg_r <= 16'h0; - dst_mac_r <= 48'h0; - src_mac_r <= 48'h0; - udp_dlen_r <= 16'h0; - end - else begin - pat_gen_num_r <= pat_gen_num; - pat_gen_ipg_r <= pat_gen_ipg; - dst_mac_r <= dst_mac; - src_mac_r <= src_mac; - udp_dlen_r <= udp_dlen; - end -end - -/*----------------------- FSM Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - cur_state <= IDLE; - else - cur_state <= next_state; -end - -always @(*) - begin - case(cur_state) - IDLE : - if(pat_en == 1'b1) - next_state = UDP_CHKSUM; - else - next_state = IDLE; - - UDP_CHKSUM : - if(udp_chksum_cnt == udp_chksum_num) - next_state = IP_CHKSUM; - else - next_state = UDP_CHKSUM; - - IP_CHKSUM : - if(ip_chksum_cnt == 4'd9) - next_state = PAT_GEN; - else - next_state = IP_CHKSUM; - - PAT_IPG : - if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) - next_state = IDLE; - else if(ipg_cnt == pat_gen_ipg_r) - next_state = IP_CHKSUM; - else - next_state = PAT_IPG; - - PAT_GEN : - if((tlast == 1'b1) && (tready == 1'b1)) - next_state = PAT_IPG; - else - next_state = PAT_GEN; - - default : - next_state = IDLE; - endcase - end - -/*----------------------- Generator Control Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - pat_gen_en_dl1 <= 1'h0; - pat_gen_en_dl2 <= 1'h0; - end - else - begin - pat_gen_en_dl1 <= pat_gen_en; - pat_gen_en_dl2 <= pat_gen_en_dl1; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - src_ip_r <= 32'h0; - dst_ip_r <= 32'h0; - src_port_r <= 16'h0; - dst_port_r <= 16'h0; - end - else - begin - src_ip_r <= src_ip; - dst_ip_r <= dst_ip; - src_port_r <= src_port; - dst_port_r <= dst_port; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - pat_en <= 1'h1; - else if((cur_state == IDLE) && (pat_en == 1'b1)) - pat_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - infinite_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) - infinite_en <= 1'h1; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - infinite_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - num_cnt <= 16'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - num_cnt <= pat_gen_num_r; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) - num_cnt <= num_cnt - 1'b1; -end - -/*----------------------- UDP Protocol Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_len <= 16'h0; - else - udp_len <= udp_dlen_r + 16'd8; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_num <= 16'h0; - else if(udp_dlen_r[0] == 1'b1) - udp_chksum_num <= udp_dlen_r[15:1] + 16'd10; - else - udp_chksum_num <= udp_dlen_r[15:1] + 16'd9; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - udp_data_h <= 8'h0; - udp_data_l <= 8'h0; - end - else if(cur_state == IDLE) - begin - udp_data_h <= 8'h0; - udp_data_l <= 8'h1; - end - else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9)) - begin - udp_data_h <= udp_data_h + 8'h2; - udp_data_l <= udp_data_l + 8'h2; - end -end - -//udp checksum calculate -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_r <= 17'h0; - else if(cur_state == IDLE) - udp_chksum_r <= 17'h0; - else if(cur_state == UDP_CHKSUM) begin - if (udp_chksum_cnt <= 16'd8) begin - case(udp_chksum_cnt[3:0]) - 4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16]; - 4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16]; - 4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16]; - 4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16]; - 4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16]; - 4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; - 4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16]; - 4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16]; - 4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; - default : udp_chksum_r <= 17'h0; - endcase - end - else begin - if(udp_chksum_cnt == udp_chksum_num) - udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16]; - else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1)) - udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16]; - else - udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16]; - end - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum <= 16'h0; - else - udp_chksum <= ~udp_chksum_r[15:0]; -end - -/*----------------------- IP Protocol Region ----------------------------*/ -//IP Frame Total Length -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_len <= 16'h0; - else - ip_len <= udp_len + 16'd20; -end - -//IP Frame Identification -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_id <= 16'h0; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1)) - ip_id <= ip_id + 1'b1; -end - -//IP Frame Fragment Offset -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum <= 16'h0; - else - ip_chksum <= ~ip_chksum_r[15:0]; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_ofs <= 13'h0; -end - -//ip checksum calculate -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum_r <= 16'h0; - else if(cur_state == IDLE) - ip_chksum_r <= 16'h0; - else if(cur_state == IP_CHKSUM) begin - case(ip_chksum_cnt) - 4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16]; - 4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16]; - 4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16]; - 4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16]; - 4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16]; - 4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16]; - 4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16]; - 4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16]; - 4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16]; - 4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16]; - endcase - end - else if(cur_state == PAT_IPG) - ip_chksum_r <= 16'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum <= 16'h0; - else - ip_chksum <= ~ip_chksum_r[15:0]; -end - -/*----------------------- Pattern Counter Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_cnt <= 16'h0; - else if(cur_state == UDP_CHKSUM) - udp_chksum_cnt <= udp_chksum_cnt + 1'b1; - else - udp_chksum_cnt <= 16'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum_cnt <= 4'h0; - else if(cur_state == IP_CHKSUM) - ip_chksum_cnt <= ip_chksum_cnt + 1'b1; - else - ip_chksum_cnt <= 4'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ipg_cnt <= 16'h0; - else if(cur_state == PAT_IPG) - ipg_cnt <= ipg_cnt + 1'b1; - else - ipg_cnt <= 8'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_cnt <= 16'h0; - else if(cur_state != PAT_GEN) - pat_cnt <= 16'h0; - else if(tready == 1'b1) - pat_cnt <= pat_cnt + 1'b1; -end - -/*----------------------- Pattern Generator Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tvalid <= 1'b0; - else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) - tvalid <= 1'b1; - else if((tready == 1'b1) && (tlast == 1'b1)) - tvalid <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tdata <= 8'h0; - else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42)) - case(pat_cnt[5:0]) - 6'd0 : tdata <= dst_mac_r[5*8 +: 8]; - 6'd1 : tdata <= dst_mac_r[4*8 +: 8]; - 6'd2 : tdata <= dst_mac_r[3*8 +: 8]; - 6'd3 : tdata <= dst_mac_r[2*8 +: 8]; - 6'd4 : tdata <= dst_mac_r[1*8 +: 8]; - 6'd5 : tdata <= dst_mac_r[0*8 +: 8]; - 6'd6 : tdata <= src_mac_r[5*8 +: 8]; - 6'd7 : tdata <= src_mac_r[4*8 +: 8]; - 6'd8 : tdata <= src_mac_r[3*8 +: 8]; - 6'd9 : tdata <= src_mac_r[2*8 +: 8]; - 6'd10 : tdata <= src_mac_r[1*8 +: 8]; - 6'd11 : tdata <= src_mac_r[0*8 +: 8]; - 6'd12 : tdata <= 8'h08; - 6'd13 : tdata <= 8'h00; - 6'd14 : tdata <= {VER,IHL}; - 6'd15 : tdata <= TOS; - 6'd16 : tdata <= ip_len[15:8]; - 6'd17 : tdata <= ip_len[7:0]; - 6'd18 : tdata <= ip_id[15:8]; - 6'd19 : tdata <= ip_id[7:0]; - 6'd20 : tdata <= {FLG,ip_ofs[12:8]}; - 6'd21 : tdata <= ip_ofs[7:0]; - 6'd22 : tdata <= TTL; - 6'd23 : tdata <= PTC; - 6'd24 : tdata <= ip_chksum[15:8]; - 6'd25 : tdata <= ip_chksum[7:0]; - 6'd26 : tdata <= src_ip_r[3*8 +: 8]; - 6'd27 : tdata <= src_ip_r[2*8 +: 8]; - 6'd28 : tdata <= src_ip_r[1*8 +: 8]; - 6'd29 : tdata <= src_ip_r[0*8 +: 8]; - 6'd30 : tdata <= dst_ip_r[3*8 +: 8]; - 6'd31 : tdata <= dst_ip_r[2*8 +: 8]; - 6'd32 : tdata <= dst_ip_r[1*8 +: 8]; - 6'd33 : tdata <= dst_ip_r[0*8 +: 8]; - 6'd34 : tdata <= src_port_r[15:8]; - 6'd35 : tdata <= src_port_r[7:0]; - 6'd36 : tdata <= dst_port_r[15:8]; - 6'd37 : tdata <= dst_port_r[7:0]; - 6'd38 : tdata <= udp_len[15:8]; - 6'd39 : tdata <= udp_len[7:0]; - 6'd40 : tdata <= udp_chksum[15:8]; - 6'd41 : tdata <= udp_chksum[7:0]; - 6'd42 : tdata <= 8'h0;//UDP First Data - default : tdata <= tdata + 1'b1; - endcase - else if((cur_state == PAT_GEN) && (tready == 1'b1)) - tdata <= tdata + 1'b1; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tlast <= 1'b0; - else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13)) - tlast <= 1'b1; - else if(tready == 1'b1) - tlast <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/Testbench/DaulClkFifo.v b/fpga/ip/gTSE/Testbench/DaulClkFifo.v deleted file mode 100644 index 7d34961..0000000 --- a/fpga/ip/gTSE/Testbench/DaulClkFifo.v +++ /dev/null @@ -1,498 +0,0 @@ - -`timescale 1ns/100ps - -module DC_FIFO -# ( - parameter FIFO_MODE = "Normal" , //"Normal"; //"ShowAhead" - parameter DATA_WIDTH = 8 , - parameter FIFO_DEPTH = 512 , - - parameter AW_C = $clog2(FIFO_DEPTH), - parameter DW_C = DATA_WIDTH , - parameter DD_C = 2**AW_C - ) -( - //System Signal - input Reset , //System Reset - //Write Signal - input WrClk , //(I)Wirte Clock - input WrEn , //(I)Write Enable - output [AW_C-1:0] WrDNum , //(O)Write Data Number In Fifo - output WrFull , //(I)Write Full - input [DW_C -1:0] WrData , //(I)Write Data - //Read Signal - input RdClk , //(I)Read Clock - input RdEn , //(I)Read Enable - output [AW_C-1:0] RdDNum , //(O)Radd Data Number In Fifo - output RdEmpty , //(O)Read FifoEmpty - output [DW_C-1 :0] RdData //(O)Read Data -); - -//Define Parameter -/////////////////////////////////////////////////////////////// - localparam TCo_C = 0 ; - - reg [1:0] WrClkRstGen = 2'h3; - reg [1:0] RdClkRstGen = 2'h3; - - always @( posedge WrClk or posedge Reset) - begin - if (Reset) WrClkRstGen <= # TCo_C 2'h3; - else - begin - WrClkRstGen[0] <= # TCo_C 1'h0; - WrClkRstGen[1] <= # TCo_C (&RdClkRstGen); - end - end - - wire WrClkRst = WrClkRstGen[1]; - - /////////////////////////////////////////////////// - always @( posedge RdClk or posedge Reset) - begin - if (Reset) RdClkRstGen <= # TCo_C 2'h3; - else - begin - RdClkRstGen[0] <= # TCo_C 1'h0; - RdClkRstGen[1] <= # TCo_C (&WrClkRstGen); - end - end - - wire RdClkRst = RdClkRstGen[1]; - - /////////////////////////////////////////////////// - wire FifoWrEn = WrEn; - wire [AW_C :0] WrAddrCnt ; - wire [AW_C :0] FifoWrAddr ; - wire FifoWrFull ; - - FifoAddrCnt # ( .CounterWidth_C (AW_C)) - U1_WrAddrCnt - ( - //System Signal - .Reset ( WrClkRst ) , //System Reset - .SysClk ( WrClk ) , //System Clock - //Counter Signal - .ClkEn ( FifoWrEn ) , //(I)Clock Enable - .FifoFlag ( FifoWrFull ) , //(I)Fifo Flag - .AddrCnt ( WrAddrCnt ) , //(O)Address Counter - .Addess ( FifoWrAddr ) //(O)Address Output - ); - - /////////////////////////////////////////////////// - reg [DW_C-1:0] FifoBuff [DD_C-1:0]; - - always @( posedge WrClk) - begin - if (WrEn & (~WrFull)) - begin - FifoBuff[FifoWrAddr[AW_C-1:0]] <= # TCo_C WrData; - end - end - - /////////////////////////////////////////////////// - - /////////////////////////////////////////////////// - wire FifoEmpty ; - wire FifoRdEn ; - - wire [AW_C :0] RdAddrCnt ; - wire [AW_C :0] FifoRdAddr ; - - FifoAddrCnt #( .CounterWidth_C (AW_C)) - U2_RdAddrCnt - ( - //System Signal - .Reset ( RdClkRst ) , //System Reset - .SysClk ( RdClk ) , //System Clock - //Counter Signal - .ClkEn ( FifoRdEn ) , //(I)Clock Enable - .FifoFlag ( FifoEmpty ) , //(I)Fifo Flag - .AddrCnt ( RdAddrCnt ) , //(O)Address Counter - .Addess ( FifoRdAddr ) //(O)Address Output - ); - - /////////////////////////////////////////////////// - reg [DW_C-1 :0] FifoRdData ; - - always @( posedge RdClk) - begin - if (FifoRdEn) FifoRdData <= # TCo_C FifoBuff[FifoRdAddr[AW_C-1:0]]; - end - - /////////////////////////////////////////////////// - assign RdData = FifoRdData ; //(O)Read Data - - reg [AW_C:0] WrRdAddr = {AW_C+1{1'h0}}; - - always @( posedge WrClk) - begin - if (WrClkRst) WrRdAddr <= # TCo_C {AW_C+1{1'h0}} ; - else WrRdAddr <= # TCo_C FifoRdAddr [AW_C:0] ; - end - - /////////////////////////////////////////////////////////// - wire [AW_C-1:0] WrRdAHex; - wire [AW_C-1:0] WrWrAHex; - - GrayDecode #(AW_C) WRAGray2Hex (WrRdAddr [AW_C-1:0] , WrRdAHex[AW_C-1:0]); - GrayDecode #(AW_C) WWAGray2Hex (FifoWrAddr [AW_C-1:0] , WrWrAHex[AW_C-1:0]); - - /////////////////////////////////////////////////////////// - reg [AW_C-1:0] WrAddrDiff; - - always @( posedge WrClk) - begin - if (WrFull) WrAddrDiff <= # TCo_C {AW_C{1'h1}} ; - else WrAddrDiff <= # TCo_C (WrWrAHex - WrRdAHex) ; - end - - /////////////////////////////////////////////////////////// - assign WrDNum = WrAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo - - reg [AW_C:0] WrRdAddrReg = {AW_C+1{1'h0}}; - - always @( posedge WrClk) - begin - if ( WrClkRst) WrRdAddrReg <= # TCo_C {AW_C+1{1'h0}} ; - else WrRdAddrReg <= # TCo_C WrRdAddr[AW_C : 0] ; - end - - /////////////////////////////////////////////////////////// - reg RdAddrChg = 1'h0; - reg WrFullClr = 1'h0; - - always @( posedge WrClk) - begin - if ( WrClkRst) RdAddrChg <= # TCo_C 1'h0 ; - else RdAddrChg <= # TCo_C (FifoWrFull & (WrRdAddr[AW_C-1:0] != WrRdAddrReg[AW_C-1:0])); - end - - always @( posedge WrClk) - begin - if ( WrClkRst) WrFullClr <= # TCo_C 1'h0 ; - else WrFullClr <= # TCo_C (FifoWrFull & RdAddrChg); - end - - /////////////////////////////////////////////////////////// - reg RdAHighNext = 1'h0; - - wire RdAHighRise = (~WrRdAddrReg[AW_C-1]) & WrRdAddr[AW_C-1]; - - always @( posedge WrClk) - begin - if (WrClkRst ) RdAHighNext <= # TCo_C 1'h0 ; - else if (RdAHighRise) RdAHighNext <= # TCo_C (~WrRdAddr[AW_C]) ; - end - - /////////////////////////////////////////////////// - wire FullCalc = (WrAddrCnt[AW_C-1:0] == WrRdAddr[AW_C-1:0]) - && (WrAddrCnt[AW_C ] != (WrRdAddr[AW_C-1] ? WrRdAddrReg[AW_C] : RdAHighNext) ); - - /////////////////////////////////////////////////// - reg FullFlag = 1'h0; - - always @( posedge WrClk) - begin - if (WrClkRst) FullFlag <= # TCo_C 1'h0; - else if (FullFlag) FullFlag <= # TCo_C (~WrFullClr); - else if (FifoWrEn) FullFlag <= # TCo_C FullCalc; - end - - assign FifoWrFull = FullFlag; - - /////////////////////////////////////////////////// - assign WrFull = FifoWrFull ; //(I)Write Full - - reg [AW_C :0] RdWrAddr = {AW_C+1{1'h0}}; - - always @( posedge RdClk) - begin - if (RdClkRst ) RdWrAddr <= # TCo_C {AW_C+1{1'h0}} ; - else RdWrAddr <= # TCo_C FifoWrAddr [AW_C:0] ; - end - - /////////////////////////////////////////////////////////// - wire [AW_C-1:0] RdWrAHex; - wire [AW_C-1:0] RdRdAHex; - - GrayDecode # (AW_C) RWAGray2Hex (RdWrAddr [AW_C-1:0] , RdWrAHex[AW_C-1:0] ); - GrayDecode # (AW_C) RRAGray2Hex (FifoRdAddr [AW_C-1:0] , RdRdAHex[AW_C-1:0] ); - - /////////////////////////////////////////////////////////// - reg [AW_C-1:0] RdAddrDiff; - - always @( posedge RdClk) - begin - if (RdEmpty ) RdAddrDiff <= # TCo_C {AW_C{1'h0}} ; - else RdAddrDiff <= # TCo_C (RdWrAHex - RdRdAHex) ; - end - - /////////////////////////////////////////////////////////// - assign RdDNum = RdAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo - - reg [AW_C:0] RdWrAddrReg = {AW_C+1{1'h0}}; - - always @( posedge RdClk) - begin - if (RdClkRst) RdWrAddrReg <= # TCo_C {AW_C+1{1'h0}} ; - else RdWrAddrReg <= # TCo_C RdWrAddr [AW_C:0] ; - end - - /////////////////////////////////////////////////////////// - reg WrAddrChg = 1'h0; - reg EmptyClr = 1'h0; - - always @( posedge RdClk) - begin - if (RdClkRst) WrAddrChg <= # TCo_C 1'h0 ; - else WrAddrChg <= # TCo_C FifoEmpty & (RdWrAddr[AW_C-1:0] != RdWrAddrReg[AW_C-1:0]); - end - always @( posedge RdClk) - begin - if (RdClkRst) EmptyClr <= # TCo_C 1'h0; - else EmptyClr <= # TCo_C (FifoEmpty & WrAddrChg); - end - - /////////////////////////////////////////////////////////// - reg WrAHighNext = 1'h0; - - wire WrAHighRise = (~RdWrAddrReg[AW_C-1]) & RdWrAddr[AW_C-1]; - - always @( posedge RdClk) - begin - if (RdClkRst) WrAHighNext <= # TCo_C 1'h0 ; - else if (WrAHighRise) WrAHighNext <= # TCo_C (~RdWrAddr[AW_C]); - end - - /////////////////////////////////////////////////////////// - wire EmptyCalc = (RdAddrCnt[AW_C-1:0] == RdWrAddr[AW_C-1:0]) - && (RdAddrCnt[AW_C ] == (RdWrAddr[AW_C-1] ? RdWrAddrReg[AW_C] : WrAHighNext)); - - /////////////////////////////////////////////////////////// - reg EmptyFlag = 1'h1; - - always @( posedge RdClk) - begin - if (RdClkRst) EmptyFlag <= # TCo_C 1'h1; - else if (EmptyFlag) EmptyFlag <= # TCo_C (~EmptyClr); - else if (FifoRdEn) EmptyFlag <= # TCo_C EmptyCalc; - end - - assign FifoEmpty = EmptyFlag; - - /////////////////////////////////////////////////////////// - reg EmptyReg = 1'h0; - - always @( posedge RdClk ) - begin - if (RdClkRst) EmptyReg <= # TCo_C 1'h1; - else if (FifoRdEn) EmptyReg <= # TCo_C FifoEmpty; - end - - /////////////////////////////////////////////////////////// - assign RdEmpty = (FIFO_MODE == "ShowAhead") ? EmptyReg : FifoEmpty; //(O)Read FifoEmpty - - reg RdFirst = 1'h0; - - always @( posedge RdClk) - begin - if (FIFO_MODE == "ShowAhead") - begin - if (RdClkRst) RdFirst <= # TCo_C 1'h0 ; - else if (RdFirst) RdFirst <= # TCo_C 1'h0 ; - else if (EmptyClr) RdFirst <= # TCo_C RdEmpty ; - end - else RdFirst <= # TCo_C 1'h0 ; - end - - /////////////////////////////////////////////////////////// - assign FifoRdEn = RdEn || RdFirst ; - - /////////////////////////////////////////////////////////// - -//666666666666666666666666666666666666666666666666666666666 - -endmodule - -//////////////// DaulClkFifo ////////////////////////////// - -///////////////// FifoAddrCnt ///////////////////////////// - -module FifoAddrCnt -# ( - parameter CounterWidth_C = 9 , - parameter CW_C = CounterWidth_C - ) -( - //System Signal - input Reset , //System Reset - input SysClk , //System Clock - //Counter Signal - input ClkEn , //(I)Clock Enable - input FifoFlag , //(I)Fifo Flag - output [CW_C:0] AddrCnt , //(O)Address Counter - output [CW_C:0] Addess //(O)Address Output -); - -//Define Parameter -/////////////////////////////////////////////////////////// -localparam TCo_C = 1; - - wire [CW_C-1:0] GrayAddrCnt; - wire CarryOut; - - GrayCnt #(.CounterWidth_C (CW_C)) - U1_AddrCnt - ( - //System Signal - .Reset ( Reset ), //System Reset - .SysClk ( SysClk ), //System Clock - //Counter Signal - .SyncClr ( 1'h0 ), //(I)Sync Clear - .ClkEn ( ClkEn ), //(I)Clock Enable - .CarryIn ( ~FifoFlag ), //(I)Carry input - .CarryOut ( CarryOut ), //(O)Carry output - .Count ( GrayAddrCnt ) //(O)Counter Value Output - ); - -/////////////////////////////////////////////////////////// - reg CntHighBit; - - always @( posedge SysClk ) - begin - if (Reset) CntHighBit <= # TCo_C 1'h0; - else if (ClkEn) CntHighBit <= # TCo_C CntHighBit + CarryOut; - end - -/////////////////////////////////////////////////////////// - reg [CW_C:0] AddrOut; //(O)Address Output - - always @(posedge SysClk) - begin - if (Reset) AddrOut <= # TCo_C {CW_C{1'h0}}; - else if (ClkEn) AddrOut <= # TCo_C FifoFlag ? AddrOut : AddrCnt; - end - -/////////////////////////////////////////////////////////// - assign AddrCnt = {CntHighBit , GrayAddrCnt} ; //(O)Address Counter - assign Addess = AddrOut ; //(O)Address Output - -//111111111111111111111111111111111111111111111111111111111 - -endmodule - -/////////////////// FifoAddrCnt ////////////////////////// - -module GrayCnt -# ( - parameter CounterWidth_C = 9 , - parameter CW_C = CounterWidth_C - ) -( - //System Signal - input Reset , //System Reset - input SysClk , //System Clock - //Counter Signal - input SyncClr , //(I)Sync Clear - input ClkEn , //(I)Clock Enable - input CarryIn , //(I)Carry input - output CarryOut , //(O)Carry output - output [CW_C-1:0] Count //(O)Counter Value Output -); - -//Define Parameter -/////////////////////////////////////////////////////////// -localparam TCo_C = 1; - - wire [CW_C:0 ] CryIn ; - wire [CW_C-1:0] CryOut ; - - reg [CW_C-1:0] GrayCnt; - - assign CryIn[0] = CarryIn; - - genvar i; - generate - for(i=0;i1) ? 1'h0: 1'h1 ; - else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ; - else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i]; - end - - ////////////// - if (i==0) - begin - assign CryOut[0] = GrayCnt[0] && CarryIn; - assign CryIn [1] = ~GrayCnt[0] && CarryIn; - end - else - begin - assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]); - assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ; - end - end - - endgenerate - - wire GrayCarry = CryOut[CW_C-2]; - -/////////////////////////////////////////////////////////// - reg CntHigh = 1'h0; - - always @( posedge SysClk) - begin - if (Reset) CntHigh <= # TCo_C 1'h0; - else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry); - end - -/////////////////////////////////////////////////////////// - assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output - assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output - -/////////////////////////////////////////////////////////// - -//111111111111111111111111111111111111111111111111111111111 - -endmodule - -////////////////////// GrayCnt //////////////////////////// - -module GrayDecode -# ( - parameter DataWidht_C = 8 - ) -( - input [DataWidht_C-1:0] GrayIn, - output [DataWidht_C-1:0] HexOut -); - - //Define Parameter - /////////////////////////////////////////////////////////////// - parameter TCo_C = 1; - - localparam DW_C = DataWidht_C; - - /////////////////////////////////////////////////////////////// - reg [DW_C-1:0] Hex; - - integer i; - - always @ (GrayIn) - begin - Hex[DW_C-1]=GrayIn[DW_C-1]; - for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i]; - end - - assign HexOut = Hex; - - /////////////////////////////////////////////////////////////// - -endmodule - - - diff --git a/fpga/ip/gTSE/Testbench/ODDR.v b/fpga/ip/gTSE/Testbench/ODDR.v deleted file mode 100644 index d78b0da..0000000 --- a/fpga/ip/gTSE/Testbench/ODDR.v +++ /dev/null @@ -1,159 +0,0 @@ -`timescale 1 ps / 1 ps - -`celldefine - -module ODDR (Q, C, CE, D1, D2, R, S); - - output Q; - - input C; - input CE; - input D1; - input D2; - input R; - input S; - - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - - parameter SRTYPE = "SYNC"; - parameter ROC_WIDTH = 100000; - - localparam MODULE_NAME = "ODDR"; - - pulldown P1 (R); - pulldown P2 (S); - - reg GSR; - reg q_out = INIT, qd2_posedge_int; - - wire c_in,delay_c; - wire ce_in,delay_ce; - wire d1_in,delay_d1; - wire d2_in,delay_d2; - wire gsr_in; - wire r_in,delay_r; - wire s_in,delay_s; - - assign gsr_in = GSR; - assign Q = q_out; - - initial begin - GSR = 1'b1; - #(ROC_WIDTH) - GSR = 1'b0; - end - - initial begin - - if ((INIT != 0) && (INIT != 1)) begin - $display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, INIT); - #1 $finish; - end - - if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin - $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", MODULE_NAME, DDR_CLK_EDGE); - #1 $finish; - end - - if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin - $display("Attribute Syntax Error : The attribute SRTYPE on %s instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", MODULE_NAME, SRTYPE); - #1 $finish; - end - - end // initial begin - - - always @(gsr_in or r_in or s_in) begin - if (gsr_in == 1'b1) begin - assign q_out = INIT; - assign qd2_posedge_int = INIT; - end - else if (gsr_in == 1'b0) begin - if (r_in == 1'b1 && SRTYPE == "ASYNC") begin - assign q_out = 1'b0; - assign qd2_posedge_int = 1'b0; - end - else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin - assign q_out = 1'b1; - assign qd2_posedge_int = 1'b1; - end - else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin - deassign q_out; - deassign qd2_posedge_int; - end - else if (r_in == 1'b0 && s_in == 1'b0) begin - deassign q_out; - deassign qd2_posedge_int; - end - end // if (gsr_in == 1'b0) - end // always @ (gsr_in or r_in or s_in) - - - always @(posedge c_in) begin - if (r_in == 1'b1) begin - q_out <= 1'b0; - qd2_posedge_int <= 1'b0; - end - else if (r_in == 1'b0 && s_in == 1'b1) begin - q_out <= 1'b1; - qd2_posedge_int <= 1'b1; - end - else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin - q_out <= d1_in; - qd2_posedge_int <= d2_in; - end -// CR 527698 - else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin - qd2_posedge_int <= q_out; - end - end // always @ (posedge c_in) - - - always @(negedge c_in) begin - if (r_in == 1'b1) - q_out <= 1'b0; - else if (r_in == 1'b0 && s_in == 1'b1) - q_out <= 1'b1; - else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin - if (DDR_CLK_EDGE == "SAME_EDGE") - q_out <= qd2_posedge_int; - else if (DDR_CLK_EDGE == "OPPOSITE_EDGE") - q_out <= d2_in; - end - end // always @ (negedge c_in) - - assign delay_c = C; - assign delay_ce = CE; - assign delay_d1 = D1; - assign delay_d2 = D2; - assign delay_r = R; - assign delay_s = S; - - assign c_in = IS_C_INVERTED ^ delay_c; - assign ce_in = delay_ce; - assign d1_in = IS_D1_INVERTED ^ delay_d1; - assign d2_in = IS_D2_INVERTED ^ delay_d2; - assign r_in = delay_r; - assign s_in = delay_s; - - -//*** Timing Checks Start here - - specify - - (C => Q) = (100:100:100, 100:100:100); - (posedge R => (Q +: 0)) = (0:0:0, 0:0:0); - (posedge S => (Q +: 0)) = (0:0:0, 0:0:0); - - specparam PATHPULSE$ = 0; - - endspecify - -endmodule // ODDR - -`endcelldefine - diff --git a/fpga/ip/gTSE/Testbench/aldec/gTSE.sv b/fpga/ip/gTSE/Testbench/aldec/gTSE.sv deleted file mode 100644 index 69de231..0000000 --- a/fpga/ip/gTSE/Testbench/aldec/gTSE.sv +++ /dev/null @@ -1,9845 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.288.2.10 -// IP Version: 7.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _4c19f37180ff465ca20760e199a0613f -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gTSE -( - input mac_reset, - input proto_reset, - output rx_mac_aclk, - input tx_mac_aclk, - output [2:0] eth_speed, - input rx_axis_clk, - output rx_axis_mac_tuser, - output rx_axis_mac_tlast, - output rx_axis_mac_tvalid, - input rx_axis_mac_tready, - input tx_axis_clk, - input tx_axis_mac_tvalid, - input tx_axis_mac_tlast, - input tx_axis_mac_tuser, - output tx_axis_mac_tready, - output [3:0] rgmii_txd_HI, - output [3:0] rgmii_txd_LO, - output rgmii_tx_ctl_HI, - output rgmii_tx_ctl_LO, - output rgmii_txc_HI, - output rgmii_txc_LO, - input [3:0] rgmii_rxd_HI, - input [3:0] rgmii_rxd_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input rgmii_rxc, - input s_axi_aclk, - output [7:0] rx_axis_mac_tdata, - input [7:0] tx_axis_mac_tdata, - input [0:0] tx_axis_mac_tstrb, - output [0:0] rx_axis_mac_tstrb, - output MdoEn, - output Mdo, - input Mdi, - output Mdc, - input [9:0] s_axi_araddr, - output s_axi_arready, - input s_axi_arvalid, - input [9:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_awvalid, - input s_axi_bready, - output [1:0] s_axi_bresp, - output s_axi_bvalid, - output [31:0] s_axi_rdata, - input s_axi_rready, - output [1:0] s_axi_rresp, - output s_axi_rvalid, - input [31:0] s_axi_wdata, - output s_axi_wready, - input s_axi_wvalid -); -`IP_MODULE_NAME(efx_mac1gbe) -#( - .VERSION (16), - .TXFIFO_EN (1'b1), - .RXFIFO_EN (1'b1), - .TXFIFO_DTH (4096), - .RXFIFO_DTH (4096), - .PHY_INTF_MODE (0), - .AXIS_DW (8), - .RGMII_RXC_EDGE (1'b1), - .RGMII_TXC_DLY (1'b1), - .INTER_PACKET_GAP (6'd12), - .MTU_FRAME_LENGTH (16'd1518), - .MAC_SOURCE_ADDRESS (48'd0), - .ENABLE_BROADCAST_FILTERING (1'b1), - .LOOPBACK_EN (1'b1), - .APBIF (1'b0), - .FAMILY ("TITANIUM") -) -u_efx_mac1gbe -( - .mac_reset ( mac_reset ), - .proto_reset ( proto_reset ), - .rx_mac_aclk ( rx_mac_aclk ), - .tx_mac_aclk ( tx_mac_aclk ), - .eth_speed ( eth_speed ), - .rx_axis_clk ( rx_axis_clk ), - .rx_axis_mac_tuser ( rx_axis_mac_tuser ), - .rx_axis_mac_tlast ( rx_axis_mac_tlast ), - .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), - .rx_axis_mac_tready ( rx_axis_mac_tready ), - .tx_axis_clk ( tx_axis_clk ), - .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), - .tx_axis_mac_tlast ( tx_axis_mac_tlast ), - .tx_axis_mac_tuser ( tx_axis_mac_tuser ), - .tx_axis_mac_tready ( tx_axis_mac_tready ), - .rgmii_txd_HI ( rgmii_txd_HI ), - .rgmii_txd_LO ( rgmii_txd_LO ), - .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), - .rgmii_txc_HI ( rgmii_txc_HI ), - .rgmii_txc_LO ( rgmii_txc_LO ), - .rgmii_rxd_HI ( rgmii_rxd_HI ), - .rgmii_rxd_LO ( rgmii_rxd_LO ), - .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), - .rgmii_rxc ( rgmii_rxc ), - .s_axi_aclk ( s_axi_aclk ), - .rx_axis_mac_tdata ( rx_axis_mac_tdata ), - .tx_axis_mac_tdata ( tx_axis_mac_tdata ), - .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), - .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), - .MdoEn ( MdoEn ), - .Mdo ( Mdo ), - .Mdi ( Mdi ), - .Mdc ( Mdc ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rready ( s_axi_rready ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ) -); -endmodule - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -MKHWLtljMm7kaIKwqUK8B5EM2QxPAoxLfX2cJIpcD8uU6akTM8tOaCCq3fMfRLOr -SMgTjMO8gkEDhuWpeeY3zc0UfPumTQ7/0MePhALxq2YkHeE6xpzjoV214ddWs2SZ -ngn3y/T3JwvOLSP8v3chWxTaLfsv781pmyiWaW2ANcnxLKss63esqdwxjuAKGa1E -t4Pkivr+Y4WTlOFhRJLNNWs96MemiTmFKpo0yfpF8JoeM118sL8OZxdN3uFAYRGY -JjRQnM2MKtMN/trj8aMlCDTmFBKh76B5x+WVJ6FpZzMTtC43cHm6IFdKP5cbozNi -q6qjblAU3CRV8RZn8/HoCg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8512 ) -`pragma protect data_block -98jMY7pxEJ1JvjZ+eQeniKqSLGmDGbOWaPlk/M955KVX5c7n52LdyGStmuY7dCab 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-Khu2y8YBJrPFbpy7rSV76IDo9Vjj6qADWaMl4d+OjfEzKdYRCAa5eRBsXB50FkBX -J39jwFVYNfkCYUz+Fdx0Sdzp6L7kwAzoJfRuCeL21BvsQ6nG/M5oda8EQRhMHt6T -nwe6BB5HDWsrh7DF8L7lBucO9b0cSuQAYfhkIQKrt8jk0c5TO+DBfoPfCWQb6yV+ -JbOyJvs24rZYjBF2OFEjozoQMZ3CLgAUgHt/v1+jubiFajhsOrR305CAuxVd7ERy -m1WGaSJ0mqyE2Rwx3CUNrnKmo5L07pPf5kX0Pf61ScaTjWFDaKsyDvho1gVicQ5a -0LuaYBMjLhlHu+xj8S1N1nHpymCtmz+a45bZwtzcnmkyxW9SKYQtDJR8yOBoo2Gp -AfrXhRATe0Wmg6H/G3E9MCAUWK9rW75NolqWai1QnNfOqHDAaQz8r5v8oZCCRkCc -dMmLnW6ttLglqF6+36OZDMPVrMkZrwuLk0EzbyDtd7Odm1j/2AmMJQ+yVm06Oo9W -iRb+1DrsNpguHldCnlR4Fz1pWdve8UCvm9c7N/Sv3vMMUI3YpfbA+sb1xwIq5+JU -syQRisTt45frrF4nMTfMPALrschVgYy2Xk9E82Y4chTfD5K3f4BK7PANhiwXPOH/ -W8R4Dcpc00nZ3eJni48Wu+/n6KYQud8ic4l+R/9AY+Y3qRw341aurSthTsP3k8vE -AfbQU6sQP92LzN7TQ2uqNn/i+GGrk9/xLWGks57GWsyVPfMJmjohPa7sUd+J79lz -O/yBgYOZLMPE5HtqBVOAcWZ3qpIK4qPYYCV2LOtGyfuUXR3R9yDsc55RcL51OX3d -YVxv2C2qrf+xNnlhz0JImOYaugUOYTgHC+FPetGAqTVdGpag3I+xcijTd/ZktA35 -qsNeGlUEWpPCSBg6MCm2UKUHpeOCke5ZpL4Q3oEvwaK4U6STOthGM0scT06Ien8F -skVLyBa/4JE6gfWT+nKQ2GGqmMcd4yFEpj7yx/5NajrXhORzjfLKK46GhkmXzAE2 -5dMLH5oBmH7cSYs9jExINMAUHgjpKcB0qj90FBILm2EVsEfAL+GUwT2oBSAiA9Aw -nownDjLWMDRuDtGHN5UuqYQIQyzkIP2W2LxASIdlCHFuiQ7WVBdDTtc0Mh3QUZpc -7cnP/CqXMQAtxyjdMiUtyaby4qfujfUOUSMhPy4yExvU61ej+sbQ2T1YaW0AJtVy -NbtoCtawUApzkx8UhEuF8Xkbx5g+lUCguc59xjG3ycG5Nolt4zlFWtKnTCL6auS1 -8GcoP4NIbsmg5X0zRPw0Dq+UnxIM5mxgZCuIq3srwveSvo92iyCOyf8wPKQAe5YY -DKGqm7NqKz+CNRkmShDR5Oog4l3weQZleKMFUZ2xxvBcxqvjPgNpALEtBuotq7yG -vQFjwJYj1Xxc1bi57CyZkWFrTInFxc11dASiPfDd3N99CWC3jX7/vEzKvL8WwDUT -nc880Ln57vPhJ+yGlnibIWkvFfeU+xRB+QZ5/ISkoQFG4YOYwjHmuW0xRkpXL+3y -DPiwzNWTsh088RvIfl7ka96SCft3cPSW4Xj4dnKGqlfFpILbxL7tCUc+cNZ1vl59 -fmWowf6r++oQzdGNCwC3PHYSSYPp/nLLPQ8bdOD7znW3h0/lxpLXdzevANxDt6Fe -efI5V6Qput3fH857O6KfcA== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -sJoun9hXsaBjoXd5vq4p0WrRiBOmYRz7dLZcqHre9vcVYQPlTOAqH0akQ6/PLAvo -b9EUQM/9bTYotLNHFDMfXIxqXF7xhnq3mOzPkpjLwLd10+G18u3FajkaV7bI0IAW -oAt4VExdspy9hXF3QLCwQvl+uXjg6B9tfkQ9lRE9Lt8c2s17Xx07Kvbp1zl7vyZg -jIzh1M8YJu5XWmIzLuCFgslf9Kr91eatrzMfWF2L1/8ZSvGiwK0dx68laecFUI5B -EnV0j0+orVdTEn15qN5+MomveXhwUi6euoryiKOhEuwxQPwJgWJdLJFjc2PGdHKK -NsgFLAx5GqkU+UrV2n2SXQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 448 ) -`pragma protect data_block -VQEpSYyrqyMy0d6e5MIzq762bzEojUES6yynx1aA5YDeKe6T5+dbMqPYRoy2ZpgY -1pDSzeqP4kI9eLLRgGkBdiK45om6VD11yNVwjrQMTGqbPqFazzhwUBUoSB7JwcAD -uC1FXbWkLYXBlKP+jolNB7dno1fTrg9L/nOmBI1I8OVyjmP4bvnXN45GNXRtvVMX -y0zkEfl9r7gQWPbQ4ywNu1WiReEE9uKWaSlhmunbfKrHkR+WQoexuhfV8DZ0hZyQ -MVmGaG4hL0IiKUoIKKwz/5nkAFBSQg9XQgwniu/4pwNJbvB2ps4oRE+CkkabddOd -REXQ3xbluJgS/j9unThBmb1sg08axrYBcQT5C9BQTNxLnKH3jAJtkhB32EUR7K8Y -VFSV9qT4ZiPutIB+jlDZKcQXzDvwTKs2/UovSgdwdL0fDYh8N6iTXamqVKfKR41O -IrzRJLOlQ7Zb4WUDyft5RB/ZA77Gaeeo8xXAfHgbLIe4KM8m05Mx3dOixwdPKOf4 -Iivkxru9/M6xHtIkk7Sb3gYK6gcWfW5av9qpewcpb9BqBDlFGVg8BqlxkhxKymHd -rzVfVgBqmYYmXoH399QOsQ== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -h07AONsTLlxUVOuPlT8XRZHZulcIPjI5IlCVE57voQcoylYjcYlec6S5UHg4gef0 -KagslBKEtX4SBcosPVrVrw3xKbkRoW2OrahVzxsru597XKu7PRdb8MZ96PsJavzN -tdgLf54Xf5Ya8oqvlMrbmHSj+vVnFC+AqKvIp7XrFpYla22SC4RENMPZltjegEZu -vLTTClkxA4XzNVJjS+RNXjMnUscfzBmMKXRWZ9QFgA4yEJ5BZidIbatzYW3aLyXs -+jIeuJjAO35ZhJozFu/FkqDptxBpy8zvkLY3GpiwNCnetBHMPm5/Yyc5c1525c/g -ako3dDZN6Kobgs5dVRe0xQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6192 ) -`pragma protect data_block -yd2FI2Caiow0cA4NVeMtmNji6mCZ2DlqmPPmHPTwsBJo74MHmwyaSsyNBlIJjNam -ZjzFUH+NJiCMsSXTNDwZEH2DYBfHPwDl0oJC4sQqQLvtwogCii5PUuVNLTjyjepV -fbgcxwhRRjJMATFd/bxevj4hmAjLXAdS2gz4roHKI28y2+oTivT4sgyWcp3rTJK4 -B7QBbnslto4/rAMSb42yAHRdB2dczjEnG1m7UQ0Zw0FxyIQAr6OslFbG+zQU16zb -dDA8+OovMqzJfxmb58Y8q2kraIScEWYdvRyxsZQVYgd8cAn+heR5G9GZ1+kWD2+y -YdjDUsGSmgjuAwRXdsPvOy68BjDnBDvgdtluLdGU6EheeoYQl74ghaLXGdkWPmRX -xS8VQzx4ZuPDdf9Fokl12gflQjACt/P19jSLW6oJIxhvsQ4snMVNXxB8Z4AR4P3Y -ZXQ9BHl3oDTdP7n3PXBtAx7+HhIpWyL20QSechD8qImEMPoRpkuYz5TjDc3brNpf -SHhhfut5AoKAg1J+Ob1jQ/d8kv6iggfVPC+Ej/zp3d9J352UPytNw4PwDkec4Ey8 -BcP78D+iGNepH/E4KBP1Do7iMixyb/w8vD4l4SiYBBufbTwz4VrgOsnuF8kzFG/Z -/JofsNpWECXLkrMremvtlkZdxEk9p3wd4Kuf7iT7xrwFQz2KrIGBro0SGGa9NxJs -5ElS2oUvXIR+J9VXHfEhD5FVH8/Z7GJLOWVIGY/K96z/i0etunV848fQleVK/Ezb -omCurOi2Qx0jW+febzCtMiUUhbpI0kWnN4leE3OBEprQmlUspoq2TyysHqBEKFJQ -rSleCMSHfyNkWyJB9YPTrRmu/ayPwjZ/zxTzgnZt5z5BzL/ztakmQZoCU8MhyBpi -BhEKppuqu+xLgcoU3tUz9bxV1+vx3nicWUOVROVk0T6L6odzeXZ5YQPD525edSgO -IwFhLU1Sw9XOBiPZ7yA7PmzBb73pqaRzHtRMRMkTpBQqGsg7FUcG6kKV389M8Fwo -QQ8KyEiM+MSHlGPe0MVONS+5/lVHmsXx3RqGztwMC3eG0kWtccP6cOAMHLS481yM -xTwot7erY7oHGnvfKVA3VZUd615ZlPYd65SZ4KIYKDW2QcvpEjrhcntsIJIzDdq7 -ChsQ9qV2hSxJ2nQxrr0HyF3sU2wL9wOQqrbCkyGgNk742bbDQh22qvtzY7yPgPG6 -XkwS6a2g+Vlr/Gb0p0CPrVRUimHNAdwxCgzj0Imi0ddmQINJWQyG6lDixGmkiib+ -cecH6lR2YNIsxLE56Umnonlp6g/Zq13x04yIm5F6TEXweFZE9EYD/cLwfAviWgka -1cL92gENSy+CFZ+VZb7h8nESYSFKrGeUFIHlh0Shhc/D6RAXiBmjpWqNnuRPhhig -Ce1VFqqTslB0joqBP1IlOT8ZdQhSzzyGdHvHdO17MS/b5BpbFB1ocnW+Q6cHUH6Y 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-jyuPJTV3R7X6Ep8bjpeKIWVIuJd8jb7YVa3yJw4OyOWVGirrjATtWvaBNsExmfHP -at9v22Kw5i36PplcNFpO8qPqbc+Xlepq4Hh6NKL49TMyZWE3tt95YEVLwHZcsFgo -daZRmfI87Z8ixt5M2DDTqoKvVJQ+I/atKfbGytImDT1r5y3SZ96hCZApmpx+LBwh -Re/MZ7Ums7sj66B3NkR3NQHhewAUdCk0ExE9Q2XlrDPGlTQ4KBlxp/SiQgkuydp7 -4ByoelqcB2OoGwub4N4rH/geQufxBITKrTPWRxerNrNN/ruNoJOzVxL++54C/1eF -42arGQOJuxPBucNs2rtTJ8RN/KXoBGAn+hbP0mo7avYFskpwTCYoCvqzSOgFlHRT -HLH6eNHMNt2b5rh1MgbNwxIgJdaUwYWoXtqMuexyt7jg3cNONWKecCg/pB8iGfWw -bnk/jfYEUNA+gkYO3mVYkpowFOe4aTww79PcelDiBC9ImKYkpc5x56GXT7ZdNyzE -19VcPv3o+zmyHFGvYpZ1dqhahfpx0Iy8WIygUmwRiI4SaIogrFmVOJ0KrMEKT/ro -FIuiP3pJa9bxGzqJK6J1I3ZLb0W69Z7mux16Txve15EeJAQAFWJHMSPGx5mCabDF -jDbfRI8+N806DhQInT9kVB0nIpioXUQ1CEmfJUQPp4sUP9P8G8Tti6BjAAdd4254 -TTcj5zacai07NV2ZKkcMVkhDc4udjZtR6dZKnZRwpW4y4yQbiJkOPlefIPL2USat -hPT7ivxbRSbwWvaIKowdtyHCOsvPbi1YjH/4qtBEfmIvyNDZ4i+Q4OZ38lzv3A9l -9MIjgseW0BicKT/kYcFsnlqCXj3/brHXpyxSRtnCfZH3K88IbJqzPeWGB7PmfacL -5Dsoz7KIRan9HGk/7n7Ra8it6G0QY7TR4Zwdaf0MKikmVNQm05yqaBh3Za4SWw/f -JvyCjQC3ZOJmB/E87c8Zj8u+4kcOqmiu72l/Q7ByGOy9YTL0sPy5o9tSfBeo0Guy -KaXzCqQ7EGnuLiweWpvTu1T/+xO8WxaGtXGrBdmHHPoVp/ywS1dZojFqjS/4cR/k -R4P2JpBEtFSmIgE75tqNUtqkNt9YB1wL+beaLbuTHaVAJ1f1JpvSwb8kZqeX0VVz -P88QxG9bxvbINS1nih4/An8pvVY2Dzh0zLoGiT34OhcRQJN4dljpp7jWugPBgoge -TWXRFJls12fTzD+LPujkvT9w0GdygT7mQgKeCSgdWVMQNoTyujDtdgbqoTj8fiPq -sfHrvQ6gzvMmatSH4JLTAJwdiWPTzOFhbVRAm6Ld24aE/69BI6vYQw4XwjdZXU5q -lFwrhgE0HutDyxN9VyzpD1Yp+Q0oDSxFVh3oeaC8ctCZG/rPQts80ZTPa7ed5qIp -gbDdU4d5/FnLjTx/b8653kWA2Y8737HDsSzldoQJJLVQpZxS+VaBxs69zeea85KF -rV9wzk/KdTDVtezT4c90rtLVAwVIwx1AZoaVxAlKuwCMscuLUPdAIojmj7dy8Zgd -t+9T0d1u4QTBIB6yveNxHxsUzQCWWxV+kdL98sjySruydTFQxOe8itZJpfSlGmjm -XxaoLdHgkgesr5NNfkvSulOC1O7UUiABBs80jmgSm0WEXZf3NPUM0/t79GFf80mB -DrEMzVp5MEW9JNFPz62cqg/dZeuqkhu1tlDxt5FXVENWpsGkFFKDqotrTtvKLWpi -xwYocWFwlbeiOxhQIBWtf+zybdUne2eArKuabD+Z6pLXOhlGdOYxr19Vn1TkY892 -CJyQEhCjhBKx+n0p1/OFU84A1oLRKh3mXTM5lFqmnRtVlFQVyY7Bf61gLIvQarol -0+egWv/oaHFSjkLpkTCNswC1HGgrMSu4jIJtkYmadfts3m4WKf9uk2UQcjQSiT1v -qCTsslHzAQzSFb62OkA61cWbbjFAscy85+7gNBackN9bSl4K+r9rZUXCZDZSUKB6 -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -SF6jRX5MbN1KbFm1wuYk5J3Ovoq4vxkJqESI6Lrz2iEvnMS6GgkGXQXWjHgiisJ7 -yeAGiWNDQuLR6MWZCgtUohyFVU5eVKvERRAf9nVBSJBjfh09WftAIdSadBWiV5fx -fxFuUL6SPamPNpCdkO2W2FOSvEEMSqyOalaIk65mCV4mOJyRYzm96tMhjOizDFlt -4AxCGA0kys+jln4Q5Dpo2Zsu5AbVIIDlHF6kqtCRkH4DLpbo2ByxXzHHXZvTdpbT -X92OXbfcUawSFeXO6LqrcEOuVN+X8nzaArA+w+nL5rWhNDZN/nCqvwPNE7I5nukd -Ei2KoM+M5Wo95QuqKU74Aw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1152 ) -`pragma protect data_block -FVnbUs5RJWbO4aJIvIqCuSa9rRE3WgP2KsRWQvunl5MVjQ6us8TfajzoDBQQlXOr -UrzPRf8jcH5Ge3JHkIIQFf7+TuupWW/oi338I4wB5u+kxkF7Cv2BQf3+5J5xF3xj -ZKlAxC2BLIojcgSliK+kpNl/TFnhg2A4dVB2uq+Me1YS11Py8fPTSxEAOgl05QoB -cjIH5OJO9lr25DDpttC0lhvM8AKmBiGT23mG63iyQfhgEfIrL06z4zjw2unfA5sJ -kkj0TbaZy78ZtXVm6yTZdfRPbph+eEJUOCZLMR11MSTTJlGV1VfOpIPYD7sRCt3T -7HmUapmMGJ8KEc+0cYi0o3COUuk1HFyfsVdExdwY5UVCGQUpFPQFLoqvQLHwvJ/7 -m1enhwlroWnEsCvBs49VNb9BaWwvIaH3E1jT4HcKS+xuhD5/B5PJWvJBZP41ssmu -d/ysmQfO5QYWX3rZMek2SJxdriT5qSY9I8N6CPS88wOMes6VkC+yVXr8XkvKZRxB -/y56JNCZbpGUEFF7gp0IC9BaP8qdM5XNdkuwARFNnvwp4bij1bErdk1EoWE/bmFY -8ZjiuSDr7rqiAwCr07Ydj7nwbOiUpudG6qqkKLbvu777qKFmOhq/jOJWwo1ja2CO -VUQERDaqwiEbJPVWPEBC1mrYPhQWC2jdYXPCeVc/dSTlFqsCxBgWlu8fy1Hk0Jm4 -l0CBQXF2Lckg00cNysHM8LLCSmlKNqn6wXqjeBKwUr71m9lVtusx+vsDg9hE0iRv -xles3Nl7I87JpNocis56zGYEwJSXj5GWfDLdAFx32OArPZHZgZa9F8vMQO4VyUV9 -JyJRXBdmNVZKghOrrlUksPSlSEs2ZIuSqTd3yxrC16AujHfCBQgCyI0KHJL43h5M -R3l19pU/NAxT76ypQ0jmrwIMVDpDOTZEZMOQDrERzDpOHSQ80GJsWE42RazSfYai -1NbWS1yphkXvCsEdpm939DfRxArZ/wIjvuigZinHajDfEFgM0WFNRW6dVpTuLcOf -r46q7tg30WFEVPivojMOjto2Eb/nd/GRC4bcVR3If+dvU+hHufAcpRPMShC/zwwL -IUPXp+dKFRiOQ8kTitir2lfE9M9a37ioZZK8hzHuFjueugspI0P2Fs0d4vxxlPmH -61TVmLcYmDQpsXnTGHSQNTm6qF6s13pFUcZw3aY1lNNN+sn38RxrD3bGjcxyvJ40 -qobwiHhATqS8/j7JM1kdFqOPnNX29xTA0kYMvYie1TLmzKqeFM5R1xB9TqlIPzyz -aCGNEN1fDnvVQkrM0ZP8tmG8q7iPXXvrvh6clLe8f/aYdo2T5TSww/hSnb6325pM -j2FRgBYVrchFb9aBCmGGoDvc1A/7Nc6+wNRpps/wDvGcUN41TPyZIRmEAoluwwpn -MvcESNGKGoB+gFwd1SdsreIwTo6uPiT4QlgdbbQ6RwYYeSZIWOZBo9NkhK6ebLSU -il0NYDxK8g2uEMRnQefBxfshN9xuIiy1eKgef0JCKvvnWdU50dLd3y2HcMzCcfUl -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -aolNkchrHQdmf62Vo9Z1dgP0MtOYoRaBWW72TEEQ6JVJYPWBBRjaO8khH/Z8oasr -nAt/W+xy88PFXSJezzJXyWx65EvvU8/+aXYHwr5KugLXmFdBQoWoFUb+DwN8muhK -Ikytq2rL9li9q4mNyW32tSsKIPcqi0v4Zf9+wgrklH/XUtBmycjvls+noGdRVa+G -t06I+WZ4Rmdx6Bl74XCV29VQUj8i1xc4Q6zBymcQrCQOhc9uP0gYGbk4pyEHO7OJ -FBfq42AexS2wgmTmdEX64M3Tw0ILbqaLd3YHTgwKlUyDsmfaEbaK1UqBS9/f3XWP -pRjsuHm1RjnY5XhVBsZyFQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8208 ) -`pragma protect data_block -a6jx+jJhdxnW3Rpu82IhCtDN4rDxnSi+pHcMIhINP07QeDUC9DUcLE6W0WFxSABB -5XUGcvygT/fw2CJ9AEHWJboQgJeDHPw8crtL1RYsVuZ9Rj8dgjyEnDtosOOr7OSw -I+vfCDj2VS9cKPQi5kKVmD3tWASnyoFQ+JqHYXUG1I+DjYe/uNkcqCkuMTWuK7IT -8uGwvjOudEeChmB5fZTnGzsTQOIc5O2ItC70qi/nqsckaaC4RZs6L2Tkio/RCAyz -lKVfc/qt3bWdLS2xX26JYhTA8xU+eivyiLCC/L6Z56sCxYsy6K7IiqpbzPvEUxW7 -djKHx+uHS5uI7KNfyz65sCTM52fgslMIW8DfWCnOtm7Lz1Gea9KSmWicTa2Dm3nE -L93ECevgSqtJ2adeZvDpT5FM+zvxJ+7R4JqNm4wJIdiWQh21RjDGmMqD8w4CXIOR -dHfRD8VzkvgwL4/klUhx1KJyNwdXvpDlBXVMQSOV28soe5vKgyDlQ8I1FWRrhSKy -4VMl95/IGIaiTEG7pSDXraBL7fmRCsc+uMwJ23FpshTRl+gXiaVbenOUbw1wNi6k -00c7OnimqNpdWV1N7sOII/ASqr/ssrA2o9iD6DohPe/tJRaSQhfMIgWYODfi5pli -63nGU7QkmjwgSMGJgDz1eqpIeFkeQkc/DJuUUVoSl0jKbAsHnhi0zkggd4zSluXv -/dAi7owo0O3jY0o9oHXcC5+czZMTDuhe+Ll8/kDCSAgpPAbzgCBvKIM0ScIa5Nsa -IZ73XXmMYy4pjy0UCLxb+PEbTxv+9bq7PqjwCrc7K3GvhQBfU4Hp2pOQ480d+NI0 -xGxuI47HyO7g9MfK1LYk4zIQdhxQvpSHRuT7sBkavw4vR1AmsDWDc0Wyu80rIDEk -jJhtoRQ3ffVVd1XH35TzoautGcjQnG0rADBIUQ/G4oYJ9cOQtr13aW8AhaMeGTji -xhefzJrKmytE11iuqRW0UdbW0EtN65ZcR1yPiVFAx9g/ub+myXAtWoJk5Z7AwORV -bGaenqvG+hhzwSYWuRSgW0GL/eGaEQVk1reL2CEoudQSsdFJOrAnhB0Vhi/5ORZF -rWVIA8JKZi6s1/Exv3xAY0vbqv+U8TLdikMzLNKXJyKZkdE4l+xv6L+rRcdWrikL -e+hwjtTXtAwdPXLqKY9Jx0IumoCc5Xif+nzZUicPCAC7mT8e3ZTmFU+CCzW5TU/J -Wk9wkXx9GTrErRaNHiittI56u6JAbiXfiaMQsnFeBpvNwm6c51PLBloBw5FKnzwf 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-DI35c/Q+Iflj+2U/lWNrpuoVPe1g0QQUAXHIeWfwH+ryLGf9m1v2ZHJE1Pu2n2gt -rMADDZ0oSi3DW4EWXfSJgUNccgfi9wn2nN4/3aAeEu6nHYwgdsGVZeD0T8bxj/gW -wU02M+EZWJCAbynAVePl7ABTGR4kX/7QxPIIBg/Eg66zGtKGRlsUxv2GggmgGsEm -BFMPobdHXNM6Nu1P7OzFHAeemLsjf2rNL9J7eWoTYMYV1vZZvkw+aVHz4IC2X59V -lbhWFnzfr4aUrEOWjK42Ib/PBvjGf81UZ35wUhEpKFmT0iW3MaZSe4vB6tjnrM73 -FPXfJ7SIJfY+oJ1C+uArKonWLfmi75SbmKkiU1SxpCuFtaaR8W3lrUzG246gGm/Y -wYbp/8Q9rW/OgrmmYs+NrH5tjWNihwcmMdNMH7V4JH0Ew8bnouHgCblM6VA4O0RL -cQuT7erRvJg21qVx7gPcigWhqTXfWSNYFWBvhHbU3s+yw7bbAQt+BH6ONYXasuXx -cBQ0z1TeHNoKOJL2a4vD1gA7I7+iqo+UnhwjZpgeQPoALPMeMiT+9H1GqqZ5zcgv -FE14VeSZ00mLzfbJAiptLIAAN8PWI+Xi2Imd8QwqU7/70GeolJiJ75scbX7neK5V -Ua+CCWMbHVL+QifcTfRBeRfPcBfqTb0GU4yl185qD+muZkLfOMkkiFwUgDQGRy7T -0OZoLnOS5HcEp6sL9+t6/LmbI32Y+rCcPnP3V66Y+fKmeiZYukPohYZf23ev3ng7 -sU/dN8NLa1SNLPiwFyx/wUtPS6mHIOfnC3GJ8fvPIKYjwR8JCbRIyXro9DsJyPhJ -ociZuLucV9J5zmlmQMbWQPFM80OmRh/LSkJXrqxidrcv2WRcaXM39UUnoM5AwLmY -EuCcyTjH1+Z3nV+8rjkcPIsckCtrmh58oloKEDMZAGF/zxkgOdn8ViRIfEeLZFSd -eVu/yXyF7xae7dkFp4D2RHIwpVHawEzfW6Mb/YQL9cUf+zdl/ph78I+HppX9E7rJ -17IoDUr3lCnygxxRFdAHY2A9L3+NiGbgiMQKvrXSLbl8CDFwQefz9OJoaLRlRHxT -RGEoaK/+yM0rwU44tMjPCSHglYeZXldEPxQ1JGFNg/SRkOQuHIDLoplNF34znC7H -6sicUemRTww62jV+gdwkVNbuTuZNi6rBkXaAVqdMsnBVGaw4HPdyJmenQxg0JyBc -9bLgrHIpGyJ0J7Y7kD6R/5NtgBobe7N21ayaSz2n8VTimJ6xsco7L6m/PzmDfMqt -ibQC1GicEDgAB2dtcO6tzd3Opd0GzAP0qs/Gc41NfI98w7q7FppUjNoEL0pULmwF -qwu55tMvonW0gwo2gsz8+KJcVpa3Yh77NIcbeFh2/V2Ki5pFeH65B1LjRfLqUEp9 -+kBtmwZgmKksLJ2i/62zh9t46FJJXN1q/w5vNioQqRl3RsvMNsYRnZ9/6wsLpCv9 -Gp6OAMo3eDYh/bKhk+QsFU+thyW5bZXwMuAyty7gIR0+BBP5VtoXyCDUrQHlJDzO -6nkxycNWS58NrxJHAa+5Wsa70UKUceINtt/1obdRiS6qeaN733jsrSksYMT83xaN -ehWrgFHhhfThQbqZ5tm4uJO1S/aCzUhRaitKYN3uWKu446IhR/daKY/esqJvi484 -GnNizsuAHdvOywMyLoTsp32dos4PrFaSqF5D5V0thx3CV0cTxckLXYJ+7XOnOAi7 -dOXs2PFfhFy5CTGX2Y08KxaXG3y6HU1/jMLbB5MwaSqRHZI4VXfCyzmlwKmaL/cS -2jthwLm3M3R/QpoTjHPVeO0aH0KzWmjltZLy9Ezt7r4UfuelHVt/09Rctj6D53Yp -95nSelSGZnXddi3uGY4cV1/XQipyCVlPf9I+eY8b6xvZV9m68alW8W6lL6rl3dAe -6C9TejbmMaMGEUO5jhjMZjUareb4YXa2NoiLv28VRKhdKlhkiLeLn1WtJy9m3BP2 -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YE2kAOrL4lpJYzbOGvwVsCIUVQOUtbCEDF8bhBb6qm5AayzRmcPL25FFvnq7UAQ1 -uB3C658d0USynAoyfE1U4QQb1oURV6Hntl4FB7UVcquRD04cnlV2TxvDYdS0JbcR -7vCuwcLQ4Qte69nkRwXoGW47I8lU9Xm4LMbqKbIO/H3kwcGjabId4a9VWNoR9NUd -PqnLp9omCj724zHA/CeFacgIJ5WhxXKQvnlZsQiVyvLnVMe4kfyh3xvKd6+yFOFv -VarMWNpp0pgGSfBec1WQY1kFJu4x4xVdGdW+rciXNMqIap22sQQ5VR6o674a1ze9 -ohiUaQrLxx8AEBjSHL5u5Q== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1680 ) -`pragma protect data_block -26ATNUwJBh0ERNEcYuEZLNE2VR9F6dwubFMZn6V94RpIq6yn+q6LS2FXjj2KJGzD -JS3I3g/f2ZRWtySljkRc1KscNbsRLollG3vzaxGk3AU9rhiwcR59Tlek/gi1zf+a -vnB5tGGsg/c4cWAMVJbV8PKUWDGiLi3FajdMtoeQ2/2ujxLHGwEFdRxz09sXoYCg -hiNsoVdheY4BAOvOLN7agW1NGEwfKvGK6YnR7MfJjD8SCKZtfWK96BiVdMe4jEBk -IxiAIvyt7SZzIWNyt7jgB9BTja5HfYz5PATIZLxTsR1vzC7haJVEB65PkGjQUR3/ -U2Zldx0O/LqWBkWZ2dgAqOiWXE5Lmg5pDcEXj6SMQhqLHFr4O22HhF+qZY9TzKAD -k+/2hq55JUUgaFg2fLL9gsLQ79QxMYZXBOV4PJvxozL/ZyOUNyJKljT/cAnQjuAx -/A/wFPZS2U7hr1eV7gSw2UkOJS8B2bKGEWjoSCXP+t/3q70eNQOsyHFoqe3yFYas -omQFQ26FhNOR4U+bTsWem4PMJtaCxNoeTmQdA+0xt2conseTJQvKJvIe/TC8Fwjv -GrJaqE9OJt3DgLbraKI7YuWqCKQeCFgX9xxu53qHShYH4o4/yz8YQwQ8aAes+i04 -vrOggaK7jZeVqvXF/w/DU1qKW3fLOFsJNx6Yk7RWzUws4XbXcMe1wgxYdqOVXWtf -n11gKa8wpuCFSUYxEmiTaT7pHuZ0MYr1b1a5jHnG1PceUccgnfn0vtBd776DMiCt -aiXDaRumupAAtZA45drytSlVrDzAdNskqYDJZOBjgtlSSEkCYZb9vjUwYSArd7vD -ruA+q9Zgw7s/e7XW3JDxCmHBnfTaJ1u94W6SVn8boaaAQUVUzNWy1oFPt4VvpPlE -QH1DWGZFprytzSFxtrJ6+8fluY/fjnrwwCzgebzG62tjURpzaFzE+6a7198k7pzW -9FF3/oVJqgOi9It4NOpB3cT8MIJtUitQFZwPQjdWkjWYhG65WeqFRXw4v6YTpeTe -x80pzs95SQWA6B8wr+PNJrAa0uBmEoZKqlmS4peMdo0Z1dDJUYgeRlEoYoIckddP -8y/RcBXYdX4jVjwBDd88c4H0p9ml8x/rnBp1xLSGMgQor3wPC766aRrAN7+obXap -4s7wiIeUAAYwfVan+3J7FTGhoct175a1AasCDArorcMzLB/T8grYUtm7fr/Aas+D -qRwPmJAiqHN6NTTzMo8J+fmoKdlT4/+nbQTEWP0sjfqcTMnmbjuEq0+xsmj43PL4 -Cbk77wZQhunlfwkkeb0TVO9ALPiITttoWxL7wDugGVyngguDNqpownLQCRHkwVEO -KZstlkOj8+H/tssBIUD8QiYYnQ8PiDBZ7GAQREeQMnwaYoBu9uVYKYiR7A3CzUZu -e1msPU/w8OUKAHEWTUNMBR5gqF+bJb2SzJKiHGrwrK7Q/soDyE5GTCCgoDrFSIub -hslvLTZAa8psCYs3QGtoK3fqZcJwbhl+Vt0lwWnm8lDoYXMJU/xIaH9L2cizDmIu -FstjphugMNLC2waVJbewafS9D9lUrcC2I6AOD163dpnphIxSeVyFhAlQZKEzPOQm -FQZLdhNJFxXszxpUDs9WZbDwPs8V7yTQPslW/EEyiYswri6B4miUpNZVoSzjasFY -963palnwgAb63ENM3qlsYc+61aEOxshrurZ1PaPUAJfyiESBXemDcZ4t3gIDkBiN -Wi8zKUSGnOCjh7by4pX5U++lr0bTU7OcqAuxYEJvjxFdCiDfOAL8bzK8EdvVuOHQ -s6X0dURl2g9zx0HrmCMTy9Gp0zPr0ncz0quyrmLLa5mGXZz603vwg5kMLoTE1zgT -d/bO2AZTchrwVIw7IU26KSxopJ5NEk9fl28c6yqemCaohURa0mpF9m+lFna2l0PO -VszF83++mGHZxD/B3SpAMEnYv0d6uV560E5j32UdE5d5VkUEpMUNtSZJNgyq6RN0 -5vNg8srxsy2rG3nDhpc8Ir4nYm73n6rl0rUBkUwQGb/s3D5QzE3lTpnbzznjA9oW -vm7qHy3ZV79Ty/hn4UBNC7xRiJeHarTxe3aQX7KeZhZKGXdCo4TBFGWZ/iKI4lUx -ofx1MCriuWy7ZKVAPqU5qIrbn3GMC1aiY3tsUIsv6dK4NkiZrovlOdhPIT01B52H -YULlKeHm04FtXfb3Z96XBsyV46X+1rCkv30JpKquKlNnp6c6hfpXKK0WWVeiczzo -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -Clh2+96y2UaAIMsOT1iQd0b4LgP6cUyq8ikdSaopI2xdvmHpy4MCZw5eH+3bsiRS -sIEJcXd7mTNOXDmXhErDaFesKLkcq6yObhPVwNralwLNFz2QMabsWP3pK2FVtkYI -fj4egCCAY9GcswHvNDiOf7clwh4nxs+SsNQqWgn4+e03w80+KoCR7ntVbJvNn7Ru -R4Awd91Y3QAh4vNgZAPy9FhwFh529f3cC1dTuK4Ub0ZWgGquypgjleCIisw4zCvg -FHeGKwJ0ypkTUqj3xiglECEaa4kDPmUqRioVyK8ierOu3UdHSjUZ9hAN96tvKAZs -H0Frv1cvk6PU6a5SMhm8lQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1872 ) -`pragma protect data_block -+FF2ryBPFKhElPRjRPlL94Ht1qyO12X9daQ9C99SM0WbaOTEIqV0p/mmSwo7XdNq -gPyOyDn2mYFJ5Ilb72QyTCdI0y5pnAVoN2wYyhlvtVZhEDTMkVvgmFCmkgSwP7cM -yzGP5HP9OuOS40nO2pFs5iKDvfcKXWtExe42+mtlYGf48INkKp2bHVRIts9uGh+G -nnqPIZuE3py6Ju23I2d35DdwqO/3AV2MOkjFqiWii4B4uT/uInhNTufGLrA8+P0N -WeYJFyIjPX5JPjpYxIAZw+aVuR6pfD0QqPCCxm2jr49DAKsaZtMnBAbQIz38PHaZ -jEToXCuCiAtkLBHcn9PN5PS8HsplbfguTJ0CY/sOvBS6VqCbdoT8Y4lrQpcWvohd -+BhXiJFEMCQ98F1KgLzrdUNmfroOuVwUuzzkkA0bIuJHqUx1f3+vw42RSNBr4zAS -ASwtMbvKbyIN3n4QQeB+rppOS3yrp8NrNcK2xyOSxnsGX+GKsphHbn+8Tz5XKgrJ -WLMi/AmfYiXmv2NXchFp8ELBERHtEo2/4z389iThqwkcqUVrDUlSH4GkhovsGylj -3heghHehw9Ibfys9ZUMpakpZla7LyLbzekJxuXRGAODLu+qiebcZa/idcTV0tcOq -AdE798kou3CdCIdfyeiY9oC35S0rfA07uOA/zvVceoCNZw8oR+iJLBM4zj1LR/qH -0p/7vd81jwDlBOxKYNt2+hmSGzqwgZGkd+49sthGCZtUt5RXR2KPuj1vIwfq32TF -55ow2akOzG5ObW4f6YNNC3f8poq1/O3Vo0SqAx3ccwarGTJ+dZiiM0ucl6YxEtSz -ND9Ez9tWI3BHdSQmjlgOEnsEsoD1B1Jirh/BIClIyB2osigAPCvyqp1xD0IahWeg -cAOWdCrj2WKZpsd7CdZuDie87OWnWiXGR5zfZWVXpqT3qW8M244zcoOZAggHGuXh -ffjFd71jo44drv7OOZ95yMXltL2IXNfkpt6Sv/vP80P5wOv3A4q8bj7KYD7MG47w -dN+U/ZnchN0AeoY5yWeY1HVyiDBIPWJC8B50hId/N5nbSf07wSUoRcLY0JwbheWx -ibGRQCjP/NDX3wtrqQMo1cRIVjPd0HcqYeFrQy72UARUI8RUYUQwlfKi3Aw0CaT5 -ywRd/Y2dpURZriBkvgGVDglhUBD7rNAhUpUtY5U23CuuhLhY764CLxphgdFs5bkv -MONDF2xps/zvh8GA26WixN4tHD4NPeth5fxqcx3sTuYa5mH3q2QQvEfFyxUt9uRS -3V2/sZtXu9paziifAaEVy8fd50ipIXiUG0fUHlVkrpchpXF4x3KpxyN/aNLtgxyx -IvAxMHnI81iyb/pnCWyBVer+kDuGYkqs/wXwT5Z6Pl/y7w76ITS7WUSXGUecFuV4 -IjtJHaHF3TLEZpl9vzsC9LbpKPiMBAGEIiewV98VXLIs/3iActQJ8K9g8ZgJmElR -ZIvPTHQKTyPn+zyuD+9XZeDtx9/h93O661F8Rt8cxk6CrYHwFIfu9SDh4g5iP/4/ -u0FPT3ozRoBwjjMpKT1K20NOe0ybSxJqsJnk5TFjSZVGLcrQxSvSKupi31zDr8sg -Upfc7mWpYzg21J9oVrXXHFc1lRzZRzMMxZAX+Pk5PvM7Hhe5+bumLWIuS9kvq8jS -cuanW36GhbTIy52itg5NiY27riMFfxfPSdi7nqQ8kuPffSc+KkiNiTshklNa6k2b -MHUH1ejbbNwKGyrr6hgt/3nPFa708KECEcQ9AGrXJaPWQ+cwuw0264ruAl2FzgJE -B9En2+GAGXrxsAJ00v3KNt7D5YJ1DIksGkzBh9XWclt5rtD7AgKS2gXBYlrwvh0K -QokmIku0nRTuIoc/WluYMLZKqCWrRL2jm7r9duhGOepYI8FlVbj2zHjNniwC5PLN -9Cvy58hmG1Z6gj2O0v7eFudoLH4MgKywUF8eP9hhqv3m/5qu2ftfDd/ipyodZFiP -ijNPQZyxplBubafG0W7FLPir7d4nRTl0MpUfQKjAcEJ1qsnTp9iiFp5lCY4ZtESu -DS1I4s1QbFmNd1IHT7MPuu9KHPJHRpPBcVQBLE2VW2YY8eZ/aVWwv6uMWf9BbNMl -NcMjxnEBx9RgP5ZXCq2sa+EG/z0GxkpS0jBulYgz1Rq8G5PlaPHIUuUElokeamHV -wI2lJwG7FA91UrGxOUEE76PabAZEBdtbFBmWGnYtzTAsKFHmtr6Jg+yq5A05rEru -OXxmJVsUJyWuzeSwtLtjeYcYIi5HrYHdzhojcj6inmmxk8UdKEQqr+o/93+YDEH9 -ac1c7TvoyANVJBmnsyGUJ94zoCf1z9YPBf0sZF24QetIjrNIaI4skW5CN8jVZrzP -ca6D6QlzaU7MR6KZavqsEOX1M/D0wbA+CxtkhRtcEMc4hkwcpFL3AyUgu2c9YIp3 -PbijWvq+kgGNPaahydqMP7PhZeaOIyKzogXmzbLXaUhJ/G+gczS6YdqBMqHXYlmt -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -LE2+LFfgwm6au8Qed7luh0VjcDc+B3kA1Ir8num5KBRVTiIzuKhCP9/7nz6ao596 -bhXmMC4XEva1VPhmJ8sO5e6zRy0FI9xAkDssejY7vLm8R5tJ7VZpvpLFCSx/5wKw -3wWXcxoZR1+PJk4dJ+QV4eKQ7AyeGiwI8DtallapnaG3wjj6w0efefqk8LCOmJI8 -behEHZOLQ/5Qpbyxwm0fdcGc0iZ6RspvMpZvEAL+ao2MBxITzF6OuflDziN9nI+3 -y4ixJYyFEAT5NSelcIU7gXzJ+0KaGrTGh1cAqPoimqI4gIC3zaVWjwCU16v7PFTz -rz/Vvf25iwmBk7v5U7qx1g== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2656 ) -`pragma protect data_block -QhqXslTzgnkGEgHGFjDLyiolpnRzI2jYjYsmFe9KtqCxwFExOiG1NIxTknOXbUvh -aXAKMit6YPaEPHPG7Rieul9mKjgDdkKlbNG6mqDFpZO8VNumtGG2vp/ScoiRunwn -fTCn74+AfGiWYVTOKxtHC27HLiWs4FVv8zoPZzRTOtDls2ImQST+nQl+4CNxj99C -PORt251BwFl8yZcElj3JERD3se9TkKcbnn7u5ZhIOBnlNpf0quHLEAhvH30C/yz7 -v3pl+J6nFV7nurpjDFeTdeM52wefSsd+pwVgTCY7nJPbgUKeqves2ngkkrNk0Qkq -KoxNhA6PvCxDEqbEKEM0OMPX5n2OqcnoGpKxMy8tAyF/TwCtA3s+ODJTqiKu+tUg -OMmmDMi5JDiAb9J8H+R0utEcHORkCpYiSrVwHE9li6epCfDNedmhNJq7uRaOmdaW -46RcBGOQnQXRwlWsUTC8RbnQkvTHROYLgXjpZ7qNwwNjeVE/aLjPkip5CZltn6hI -2MwIhRUpsXlKjbx8mvPmFR7GucSJlRsJfYDL6lVl9EQYvxbJSe0WJzXRUmn2dtdw -M3BK5cpe3Ji/MrVKULHAq8Ny5iseGF7JSj4TvzSwI117X49rnZKNGyaw69jqRUB5 -AuEcMRPHy8aUdiU1KSFCj/Yw5dgwa5gLIHowmVm+HnY0QpXxVOWosQ9oJedyrXWD -NNEfKSXhnyh+J5bt8Xd5cGiCsDF2bCgqzTkrpavZ+bp6ICva5P0JNJuWShhVidfV -HyXF7r+xlkovrV9YmVe5MQioyRJPaeYhH4VFeQxl3uVND1HYoo1iwnmQUG/O89Ct -R8YBPnRkdsdxkUiT8V9OXKBiS/DbBgyip1KZyIrQXHWiG8YbCAuzy70PqUHmVspm -YlAiN6EcJfB6y6YLhIaQS4oYJuAOz2XEVGaWtwT24EUOiMi1VtCJ9zmckyq3fNI2 -DHMzD/diYUI9TfskUYjfUrv583zodnBiHAvO53k7/aIuClinrklXA0TNk9lZJtoV -6/O/S0F/DUxjh6lCewdxvGgY6QDyiY8F0amvvVpJSo3wWW2PbrMUrFjoHglW5ipa -iLDG+c0huDn06ZEet9nC+9Md/Z4EdGB9qn/hA1HZqC2lpPMH7aZnbPGda9j644AZ -b8MPRcT/jut7NxcY3kbhTsq6SIv+W+xhwafcE3WMPWhK81PygCOT9fQW2ZzJ0bEm -zELUpVr/YVvwr/yh4Sgo7ezoOr4Lu7tPc67L6aRdNmzZdE95pC7PyYHVrEWpqtkj -Mq4AwChzrxP+Hn2K0/h9CuVf7Mh4WYXq93B8IHcvF3ZYxgwKH1Q/FfX8ewXQJXeZ -oPsmmZ24D7L3vkV6lMudscL9+4YFdBvBwy8cyAb0D5Y1/krMwR5d9XeNpwIX/lwj -fJTwJPVDzjlVscd2IeQbolRoOwCJFhUrPiYRfrsK20oFaB5p+UPVsyGMjbfEvw9h -Nj+su/UJZlFWLrSIpfNI0G/U0AMYv7IQgnipJQN8rUzm2kPJvhH/Nx1tB1443mU0 -svTZjQXXY16vUu2p4BC0fWtVeREL1yQT53cOoi6Cu8dPArHuxp1JpIUx3daUnJCl -JkJ8R7zJwKnVmCHmyFAvszSral4aFBgj8gZgLgCUBJAsvIfIs/5280xggGG7y1vN -c1u2LGwYO7opOJVSjjHLv0g0KfEvtFyCws1aZRoevUTDtkSHuvxYxebyeAtB/x7k -69tU0a6hfMC1C+39F/zhfIZW5YDUKR2Ml1MgYWn3grPZUsw6H1yu9BXT02vhhntF -TfXNNcfNTJNZqwverllUZ8oV0GAJjVE6s+u2OozQeSALOSMHT79ZgGetp7GhVOgV -R0tyS+LBt9DUTMPaWYe6fwbL1vS+/qONocrfeOJU1C2rk7JbZIjCWjbyLniYG0MC -u7wdSila2z0vtWPGSsCtWm4pTYH7Xh4RmgF5fdfXr5ugZcqOvFkx2xZ43j0WDFyo -JKI+4T8ynYpSywiwjfutUcT+Z8uvDmwy83VT9J72eCUFmieg5Ey4J4EJYpcfVb40 -ydUPSO0lvXCPLbG1gKxKAmcW/6uWR8EwCpQgXghEQ5knbZsqyCBHRvq1t8qTOBAP -0ec9wz5Qz/JCFFuFnqtea356X8kIQHhYiOyPQiiWhxHseqkfFzc2bFgxB1cu28lD -OJrckJx2wuEvQehZAOQ8H1nGgxLdTXnzW0PkSr4balxwT2/dSYO5ZI77iwuSbMpY -xRsrxzGqwva8EZCfZ7nA3dBmhm/3pUyiV57qQKGMSfAfzOgiGTCg7Ijdc/Ly5OjN -iGAXc76Tm+E4ZNXRb3tmHTmps/kCwu2iYAbE2mwIvz8nUZcZGRCuJqcLtNC/xt19 -rfn7gGpu1IKNIci/ZhkkpJg6J/cUxb3xFDyc5VsmPJaPkrQ90zw+XbgDEQGBJuNG -kmbdp54gVYyXnHfi8rZsX1zApPcSrvtNUnJiEVWl5Y2z4+rV96HO0KRWCcV1sgNG -Z6hUCoiyD/fijkxgGVduGol1LWjNb/LsVqh70fuL/CTZgb0OJrfGgNvvQoG3p1f8 -6pH4qh/S9EFueAl4qHCQfQ7ikDRyqJo/chRYbuIDqwjMAoGk/C/vBaQS6JjnjpQm -i5WVQKXgMfocednye3yu2smD3G+qd9c2RVJNUAov0mPK7cScYj51c4PDcwzSSGbn -9kSIuwlc/t4I8FZ9kf68BM9u00J8vgrRjHAuaO5QIJnzjnwzsSLqfQtm3lsSVHod -Ui0wLGTkeAaiEnMNBM9nwRJyzSn9gszDCeaclidsptxyOHMPq6014IAzUdIsHEUV -XqQ8+G7cwmUXuKwk8dcxfRA332QEU34Sj9YWGnuyF/QcRVWoVFEZDN0lnWKCxYLQ -2IC2giagOaWwuOkTybJTp7HnDJ/QMtYocOjoIG7aVOHjaKiBbKYQYgIleEJqiewI -7vkL/7JBydeKuU7IIcDXJWneljzbOD+YOn11jAyYb3h1suSYOYCLKwU2VpibLAFJ -fe9x0TyUDqhXepAtkMX+/ch2Ihn1zwPkOBVx2pIzviF+oGkkbq22RgP0P1SKe+C1 -K+ylwfE0TcKPKOzDLeqpxfkylcOzn8nXb+kkjOD8q1vcN4H2w9IRNTUH6jA8X/Ua -xR2aYfZsGUs2P31w8s2IMjiolr396FI9uisk54tQOEjSa1MZRubiHhA1b83nQtn4 -u54EmCw/DLG/SdAnEMK6/jQ1F8BM7OWjpNHu3hv7SZPrBAaLXd6JiuE+9+qxl7hW -eereg8KEx/wKv529cnv+i+nzsjSBg0eym/O9ZnkIA5a1xooIdJe8izoEig1leAst -Ao8zJqa0mHX2GXOEad62TSzzDkiqjr7AkFpMLxRqmrp411FDoUfLqqYXWgLNHsEJ -T2M8fB3gDH7WFYjT8S5qJQi55K+AxI07KOW6zZxH1EeWgfuWx1P6qMXD93EQEpPN -qUH4WLO59a5T4QVO3/3l1M4o4v08iF9pcPJlrBX2IT03wgeyFOko+k00CHq+r3Px -xRFznbHeMXrJzICpc1qpNg== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -a9hy4rxBrnfw+wxP50p3JnUR+YJ9+SQjya3L9r3erHPvT0IB1/j6iUYV2UN0bWvo -slhWQdYOx1GoBstYG2navdEMBM1ksTWHFLFWZPJ8ttxrSSiPvCG+xsAf4fHUEoxf -FnAG65tM4DRbdjUOKOcqR+OZW/S1VHDt11jO4HIVRc25PAbPViCji5Os5GNVet3J -G7F8KtMTbVJHqamQ0NPuY6ndxvsW8w9g3nuLQjWI+H7MLiJKtUnjJArfK0/wKAY4 -nFsxLy0eSD+CLtVbao9QAWtOqZlWzD0FwO4PqQDtVYngsrhjYpzk6mTCzIwBlMZT -fr+ElYHlgyghsDTuN+QRtg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16720 ) -`pragma protect data_block -8upiWK6lq8vrvGkMb1XU7RyY+I2bQE3fPjKYsfaAtIlIcixj7CcX+r/nx19SUjOR -5EmweJL/IHojH0EAd1jMpdBD1kXJcA/wiy2b/HazXnORDvyMwCsNkx63/cv3Ghba -1hNmT1Yq0DnOpXRNQbvsUPpuzQ1AFL42A2KXginlkEoy59/m0B7sIse8FPijpVNZ -IWce/IwOiWGLPa3Ivm8k5NZtDs7bOkC1+bTut8Jfp+h6x1LHMW81mU74u6TjsB5H -jVZvf2peUwkp7CoLQ7iPpN5Cyr7kbj6hhp5CZNUKdK0zAzFEejbqEnN6/CHKMuI3 -W8fWWVtsGNA0vYGaMUqBm0Wp5/ER57Y5ZHYm/VL/VuE1sM6+5BUcx/t0Sqs/yExu -eYc5Y9qXpFgJYnaypT5v3xXj5/xfc5OV3x6GiGiokz6ZnWDyxnEHdjRqpOo+8gRr -hT9REnDojW+sVwX2PA7bUmxkavCpKIPo8zgCdAsU7SDO4hWw4xSwY4ejTQv1Idmw -3SACUWoIK3n+agdmQPxn7hCDGsrSSY3zaNE5kOZ9AgfRVMcLcTbysDDguzrEFNJc -r1iBhnwinqDNAuh3ytpN/NMr5bx3MiaN4ttfRdJ9H7mpDJATEDjkYOtnYrw+pYj+ -z90hOLkgJ7GjcyfYwZ8315RoGpoKGvIb/oz3SkfNi7q//di0d2S8+9M2h7OkNsNC -RN6NJki7P/hq1I4px4ZRGJkQdAa/iZipCyT3XtXlFPlFzFbgUWUrWnZLjMzaMEXo -GSpu+httr+e/ZyY9f2mcV4n+NivwIcpQ6Pn1DHgT9cZr0x2hs/cI6z40WtMbbeYH -UW2zEKX5grGSf3xu04d/htqQrSD8OP4WfyJNP/0myBnJdGn0v8YldONYi/tLlnx3 -HuT4fHLwqoJgXsPRqjakE2WTKNdXNqbnggZoURhC+qC7ulWGa5L8PFDCjuWddBna -1otEBuWEzpd2qIuzYnQqb5EaX49Iwr019pPElgeyl4qcF2J+nNDf8CGLLQLnGz6/ -1k7EyF2YWW5Pz4XYUwfsRQUJx3oKrTOopyt5ilarf2rFDmQeFte/NWD9GICbpDXa -kG4Y+Rto5aHvQpIdg2Y0/XTbqeGLwlWYOB02U17EGtLG05mokTR9BoR6lOVWGvcg -EE0EjvcsgruDxaDNMP5qO2mIv52lfA9UCmV2e238j8XFCEGTGJYd+FthXOAqabhF -d6O+OVwuR2rxobEPGdwrj8HKP7ZFh/XGNL7c18bcTIwqzYmKLR3P9109xhiozyHN -hQu4cj3Js+EJ99y/J5IEncdXu2jhR3MYi0PJJKd3Hn7qgsV1AsgR/4Mamg+fUYJu -Cup28IrNkS9uf2rXthL4tW18wUum/OuFuUR1E293ffKavnEJSfS+jJuh1P6vkTrj -t7DYBGbmHddirDfw7lLUjNC7YjtR42ZMS7Wz+QQ8OBgmf8tqzxcQxW8V/SwBm8X9 -B/+dELKL3EcemEVrZFskLNsArubjKKMt4W/1Y0RaR9SaA0/MB4ts3V4im3I4s2bb -W8zXwcqivdkAeGjmDakh+G3bAwCKmiuV0wmOjnpkuWhBwJihSipgjJxZJmF+LVa6 -TECjJKIZ1mICoiTzV2ywelCZJwQ2Bnp5B2w7GWQTYJ6aW2TsuUQdK7VcQ8tPE1Cg -x2p1U+AKfklQ7tjw1bUhspnScnjs86evSySFL135NSXKtDg7sGUaTeiIqUYcPZvp -TclcewTGKjrCXynwPjguEvtN9JoDfJT3Bf0kl7n+2m1mTDmcGtRwSerkw5qmQHFB -LMqwTpqdPBzL4GjY/fqnsawxKA0UN+nET55/5qE5K2qRMZyaBIE5Z8Bu5YfXyXfA -wT2JENXWq98/CLoMd8/tRmsUb8P3Ht8zooxvjamDHOXGAH9nhLalPuX5+73XGSav -5nO77HG7hVLhYwjrDNXUfdyuFQUd/DyL2TcGa1QmD/oCYF1bKF5j1J6gibdV2GnI -aQgZ0zuq7Y5TGA1HMhH9rgEd4WRV3rij0h2S0Q9NYlMCSFX0glxoaUquiD874jsl -lRcd/6E6Ywr7YhxBPbNW9pgt1cNWr9821P/JBQgsmOMk/FkXnSQBVjEV2U9gLpFh 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-Pk+CU9d4Pl3z24mJTJ8TpA== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -n9rncH1gli54i44OkRckXrPS5/bYes/awIWcV3RmnEBDP3AcPLSKHOEOZge8ZOyN -wVltadJ2zhaR1pxa1g+6VALvUtvzm+YTBZ3pwQi49ZgPt5/wPep+O/POaCQYq+Ah -x7LGg4e/LzfBv0lRKkcuaea6bHM6A7u0nmr63ytA86LQEL7lABH27sO8NaE0/M5j -DqKGhEYFJSP2Yxpfcc1/3ht3x4Fqhlo+joo6gt+mQm+VUsy5T+U2YN+NQtNZ5J1K -XlAJoqKUJUxgRRd9KJhaVDOBzstJxb66ts5wP2FMr84GZrdw/QQJb8Z+K7VB/H7q -o/xuf13FxxHZIa1S404mhg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 19056 ) -`pragma protect data_block -mcGX/XrhhAetb2qiw8MmgWavoO4JPBy0CYURSItQTnxNSH1+dcurY1/Y/CgUT5og -yW+fx/M3tBmbrC0uCbS+7av3vxOPRXz487IuX0gNlCA7EratTXAr/vo2Sq0Sv3y3 -zXzacFO3Vf5mWRdbpCqje+bzLRpNFEiIwVeDMgBrIBxuP76VwIXxc2zjjqKOyVkd -FRpIfRbiwqK//vHW/qo7wiA53vo7VUVOpXeLgpO0FGRlXWVF3WLp3WAo/mapEQh5 -h7wkf7GxHfgLeLUgPdGyB/XnoBbNM9iXYAF4jT7ZAxQ2FH354gviOh/bwKjCRPS4 -HQu5n7ByQ4NOp1X+GrC20ltEyK46B04+BddIISK1ZlM5pjE1B76E4ztKVjOzLx/w -74F77rT+ImAwR14RmuYh6IBtDl86cY7e+UVXTyKgHtP2HkC5pds+S82N+xQx8mbg -iyvRu/MtkUufYkmh0uMu8dRNN9BGP5qk/KOYHvW9cSrfQh5Qke6MLiOdyyP+W30L -RRW1mhLBoR/ZSzFy73e9xrizrBj3ek9VWP0WVyacHpmjZ4+Y4bKpC2jxXYJNh3Ni -VSWIOu/burQSiCiQu6GKcSDNpvTWCAM5EhbRwrB0MiNAAWfmZtRZ5OGG4Oy+mOhD -LaKYJpYXfZfVZU2aXC62wWmAc3zRUCd2eFIP/NpoyUxdTGrmVL3FN25yzpkp92p9 -vLsjB/9QdmscfmZ90rtBoCZn1gxi9RSZ9m75uPELtoTzJ5objT0ZapOgPnv1a7Qf -WMT+A0Im1F6zBeeBZdgX3XzYn9f2gFV5Gq+vtVIQPAWqkG4mSsUuWKB2ikQCB5Mg -lkTYW5CLyhdWrnTJmmcAii5I1Q//peA9gYuUTbAyf8eJZMCn580n2fcM6XttOpdB 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-bDDbuisH9/DxGO3CByaYN1fUPqPXy0cCvcB8mh0nKJwDNPlC09S+CC+ksplKH42p -FYKCQzl2vm2JEeFkWHJaTq4USJBzwqFefY+t3cxoP7cWRGZKC3PFzHHOlcfFvrw4 -SIWZLpEbsiG5k+mMGGSbwTrWuKAHLXMxUwKZnYCzXW8PdLCj+hnqfdJgkfhDc8no -ZaeGp6DLJogCg2TlubDzds9GnxkFBze5kp61hUFK8ixmkvkE+f/P8jfjdftBkuAZ -CLxJ4pAfZ3K9Uo7KtOtj7GSO/betZsTuSzhUbveWrXAViMMV60CApshkDS+uxG3+ -oXueZ16aiCz70mmTTMxpSODAeuJjKlXPUQY8iG3+x8weEPRvqu5VHJ+K6WZa9van -iRTIDRIeXkpssPw3akpmwDf8y/5XtWw/0RAININVFFxLaQCbLpBJgmEJFdYWT1lM -cg43yzG38geUadEbGLym3V5VPs6X+olTD3rTGUmzf2b4bk4RjDk9pTIw+0IsFMRE -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -J7BOv0C5jXIeRnLfMOyapOQhyKpFxofs/IUotfm22gu2bHDwrkOZuNyLq83WUu2r -xh4uVd6vqtCoovwzd7WfItOCJ+X3O/rPN+iOMyUD4wUX35A1JlV+R91hVXXEJeJK -O80EKuSi1cjkL94t77Y+BP7umEmcNvaWc2GsIw/yQc6S7Haa3qdT5InDmDim3BIS -8ianCpIbGR5tK2EK3Dd1jXhcsqg63wXWm9ytRW/sXcbLdFEA4q4bAwtsavM1I4gY -2p9fZ2Lqm2N2rOQGPJV4YFUkwXWXjQGKOsaBYkwTWJIkJC4XggjFYhfOPFQhinMU -JpYvRNjOSlo9yPiIiUT90Q== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 36512 ) -`pragma protect data_block -1KZxstNKe1X3FW8BvRwLlLOIM3zSdhwPG2BEO5RT2Hx+LcIC4hTVWuBJOTR0W+xU -TimN+/zw3ZQ3TUuhBIf+5cViOaiE3T/00dPwc8zzP1bq56Ah2eFb8umxSnuypg5J -wPG/gtAZ9EGXsfJZO95JJW2NdlGZ5vQMoAC3BujdiXh/OLyj7utM24A0GPxZOk9i -Lldfu4LlJZUeXlVmUGFLNP8qnfGJjj3OjzIslsxWdrQfIUEIt+C16arwlvRHgDPm -jEo5gfYJ0fmU/HIf9JKMWqMu2TihPgKrAYbRwLn2sUETfjV0QhlZFIA9MRkVAi/0 -biDlTTzVB6K8ZiEvk6/CpT7d8d9ry0R4XNvOz77mTEHCSegPJ6ty/FYjrlUcT696 -W8YmdAR4AUb3Xzj9GH7yiqqoTUuU83WIAcd+YKrvNpGimbjNDjvus3Hsy2AXLEmz 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-0OLxyI8iRkfInAb9kwwhkVAp3eEpKZlseKhziSVQ4IFN6yajbw+j5KVOmMhb2/gQ -rXzQeq+kPKFODLnH4O5JH/scGCfzhvAyzltl31OXC6w+7HD3TtyFT3RMlnqV1EDL -zKgnVViRyD2O02xrW0R5m8MlZImza74JFq/VRMJfIUpuDhxhYJfy00cF9K/FHR2P -pFJX+dGybQJg3GER4k3t+GvAaYSX/CAIDixMGHLN6tk= -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -KOhIlvaBdXECsKrbEVJUzh/U26bIKVYacE93lWLn0xKG9BPuUScZRg86anjHyYc3 -BakNe+PgnuJEVToYQFkSSg7dilv1sC1y3A1esk/m/agSm1sZPAp9NXn71CeNtLyq -eXW4+sYrPhCz9ARfu35HctyMw0hohs0d9BUvwOVui0XQVxf6T5Lo83B5XREJlGet -fRnVqNWfzxTOM12vqIQowKKuvxhX1eIWMAY5THDVP0MYXaPzVt/tPmSCOAoMK+x3 -fVIwwzPHHpF0DPmvj8JSmJmlaTew2n5hkYU31ogV1dVyjnJqPSvggbb2bB4YHnWr -Ej/zH846G4MmCJDO+yZDLw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6832 ) -`pragma protect data_block -+Z6uDxWxa1wZTJu8JY0TOi0egG8tzyyv0sjD0EG87Bcp2nM7oduZcHHRJ1oDveP2 -RW9+KmUvkvqdDjOvmYDaD61UT3NntqmZ+s85cV3fobe34onhe24Fp0ZsM6+2EU/P -2FRL8FdGE3PtEpSkCfcrb6Pe5nlr/FzeLll97Cm0E5ePUrLFBetyS3AU/cLzcZay -4h5s0RlvECzY6AjfWNKCPDVC31f/w77E7R6tWgnSPohEO32oFywC1EfnUwGWiTqT -3fM7iqZye9S/LbaOvgXeDwXGY/ck2oLU+xOIKyja4vioUJgrwohYF2FJOUYooupQ -YzCEETEp6KomFEeP3tB6VNAO83V3TRCSvY8TbnA/pjBYU6BixrUQGVXCl/OFIStp -UF7C5Wcu8FiVbfTQPg/R+buRms6R5kyIVKjI+unvmpgk65710peaBHKRmHuO/1oR -GdMdA+oTTkHtw5J0Pfl/oeYuL6C4EV4gd7VsCoA9646uDmaz5aDWSHvY7To5QUMn -Ytz0OqN0hpYqDkSFgOhJzYujm6vylYst/nGeon9jFCbEXeD3Ubc7MaDPDx+A2jm5 -LnWFUNQ6PDvkiLdyKc/2mr1jNybCvgFVTx+SzWbIAMHyS7yQ/IWLmGGqNiB2Ola/ -JMXCY8qDO4zRD79o+Y8ZYNSKfqzG8axxUrqtQ+hh2hFozVZedHtLwXtVOREj0FpN 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-eZHN2IMVVm44+aE7Oaycv4nYtqhlSf3ySoWGnDMIJLiL/aaQD32XcC6GmpgP5LTA -jeDHk7LwOr0lzd5dpvPpm9qxRl9Xn6gmwDhU6ErNjldLt1EENgiSE+tdFjTMzQ0r -yyM+NDX5nHKGVCHQl7DD6JsYquqc27fahSFKnjOUlKIMusNi9LEVFD7E5hcLLjk8 -YCodEc1RQ+5XRjZ44l8hpBEeh2POPSklz5ytk4AS58ah4YTqTWSJW7uVcMfR5jDo -mZ0xHq0LOLYUQf/vS/5uMJdRFx2H9/7E0F/OZpzgCJdSXYiTPYnKOVKrACgbFV4Y -54WhmiqPSd4rHPAh63pVpqsK4HxMp2kFrkzdBQdjsX0g3wBmE2F4+97xSYAEDODt -X4pvxaVhzVbkBi1q+ifxDAoD0LWkwQN8aPXqyfIe3zWWMgJ9AiazxqdqK8EAv3g/ -cyZugRbtF/jqi5ceeUlmoJLNq6x6jXGB+lLjbD83zWcPP438hGReL62/N2EWIFrn -zgViEpcU+aThU0rtX7xXtuo7NMZRtvR5EV60q1JlEartQ8eGTA1UyWKa8XckB3O+ -tH8lY/ZsUHsb/Lb+EoTD4ZiNV5MWEbwKMzxXZ3DBiTdlZGtIm+m66tL8YhSJhF7v -VpBQLB0aC52wSccllNxvIdARpOn3IqtXjTK09szIaMfLJGxEa1s1VXtY1RKd3qcy -hSop+iugpeLj8cyBhVf+qQ== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -EeWN16FcGe9oBJ5oEU+ohgRhhPUxTnyYnwj6pG7yWCXXIFJ/c/Z2IFC6YMj5VV6P -BLyZALNjwaoSRWibW3QAq5qvNT7j0LDbK5BiD3kYMK2NM1ttc5RJe8nvvjIGZf/4 -QOgUPzxqMONvaitGcZqFkFRF4F2r32UTAF83wa/GXK2EVl27GpYipuMHfblqQc1T -0P1I+cdkyrOYVdn1Qa81Iz3uywJPy936keWhYnoBKnsgr368YKmcgYSRTKkT/tBw -MxLMmX96CeZt3TRFQHv4gfRxBPY8acA1UBgUTmeIGRMIn6vrYpV8wxIugIJFqVcC -hrVjUIFq33bxM4i1U0TwRQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 29968 ) -`pragma protect data_block -YhKy5e/Okr/GJ/vg9eBL0014mggpRjiJvYYOMd4xhuzrh41ain74Svo2q+UD8cs/ -Mgo4yRLBR27zxN0hMpPvEvXU1NBuBn6CvfUvQsiF1ETmF6vIlRHIJN/fz1SU4nPK -CEt8qslpdwoYcLUhTEmEGSH7UV6AnX4Beex90z4Wt8QTKeSbED0/+Kfkp8OSM6pB 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-zbDX2VEKz4roUsRvhoKxScM7fO6dkPtNUayTsGFt7GXlJS2s/vVO8fsD9Ciec9x3 -ggJUgqK/yoLBjY9gZ4kiRJLVf+s4q8XbNIbnpJw1gbBJ0x+4FkUnKCnNOAS7BiG1 -CmIG0COajvJ6XpRXo0KpkZoxCaKhwC7dJawtLfr1ZvH/qwpPL/T22pbSaJWIOf1A -x5T8ARhJwoGA0MtMSqhQDNSneuRmy3GG6d5gjvjIliu/Wfdab6/YZ1y2Fbc62DJW -vRQnjb9i3K6OwuyM/WSLtMHKvBBb4UXhPhi0EcmJVRvrxEm8/1B3IYJvKGKuobZU -ZOoR4FMT2HlcKf/Ya0Q+jnuzHED7CNM0clsZoSFGI7QGJgZE/SPJtvuWBI8uvOT+ -YEGEJPC3s9MpByV9Pt6KFA== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -jKKARVQzpBjsnhGaDRXS2of402Denlp/BDQ9Ty1CjdBDB11vyj07ShZzg/yf0s46 -4i5BSgiNZFP60ULPBKuj9srpwLgZ+4wnvjoUZO7miHerzd4i2Se96DGrDU1ASNJ1 -2zoboipgmNHRUSy6NhrrTjto32IJYxYYdkc+zABhsGGglKjcw3DhZbYM0P21JD9N -6bHb47pm6JAl2t0zF7TNEzG2xZO30CBLIrxT3iqWtJ+UMI7oP+zOgzEa2Hz9dQfu -T/OoYZ+a8/GBNciE6fy3/VsrK3sm4wMF9rlkKl9YLLHSilEdRHKlmFypuvhVMvfB -eHN3u9By19hM6nPHSv0Rfw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 50592 ) -`pragma protect data_block -4m24W//DII3zKN+0WX7EsAbd2xWEk0dIIOQUygyMQ0Nxgsn9lQUFYqtTqYuJG17v -u02W5k269HUkmsBRurnFPolpAz4iyfTxiBhELJZ+Q1DDU3H/s+DAjrMbnzUDxntW -h7jLk6TnUa2ApvNA2RJPym4fM8On128cWrjeRPx4wIycJb7Dn9xUZp3PhBhgihEf -Km837CEaIgHbbFj3k5v5Ig380L8U3jTnCd8oP3/KjIfb1FA27il+jZ7IbQyWA19l -yIGBzTvoQCUDuHhuD7a/B7bXCsxWlknapRwx+2m/0XPZHVs/ipV7RNge+OzK2825 -nFVpuXASx09tX7xOt0/oMcO3EW6wmNeFKQJE07Ipf5o5G3Pv05wlDs4Yly7eiaL8 -V+hoJEsnCSTzm4Bmu9ntP6B7QNH84ZUO6u6Scmq8cQDnypzoa6NpituwCTFjANLQ -MQmZQ88BTtm6czXEpNZZyrv8C1F6MtwB3c18vtOs9Watgp42sJsIqFGXynHfbsfS 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-U1DgXj34kRQAk5DoS3hA9fknNHsQvvPduJpU9oT847K1BnCB+TTm8LrBEI6NL1o8 -8Pc+4472ZwRXDiguFsTkouVHXfKf0uOFNc7stKrrhqVeFkAnBSGod8/2VfvVNoVX -Ev40NWVEy/izcNbhNs84bgwbKrkUjMSHVydxBlILyO9xqzymen0JbQIeaOKBwdQZ -48s4VckJwYUtf9FWYGYDoVAC50+3le/US2rYhu5fY76PrVDXc0cw1MpcKFuMRIR5 -ql1/WIRsWcKguOAIBfZeBfbVzorOWaH26xcncdIDdSJHQjQ9rPh2pSFar7wFrGgt -sQCCXUGEDH06Fg4Nq3/l85mLNvkEGMjtBaV8xhE1vOuG9Ep7tSrR+wwQzfk6SRCW -/3ZaWwfw3e3vEIwUlDzZS8ZX9CWr5ix9awlRbKsW/KawkZR84oEnUZ+RzEmc5llC -ipr2pbhLHyw9kjKnYNEix518faz0OzAeXR7y3cRYgGWLvEuqAeOxIJHeAItYlMTv -9zjg3TEjt0XUbO7vlKXdrHzjUYhK0MLjnXPDD81mcDu9LKu9C+NsDGwhdi9jgoYs -1ChuAoHRrI17TjThcZyancR5QYWpK+zqDz+qNTEOQ4K1gTEgti7RxOlbfBAbWK97 -SIX4hM7OmnmsDOgSY4nWwBo35ud8CtQNnVaFubkYQQZ3+ngWoFOXV4h4VjrazAsV -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IzMcge2JRDduYI2DRh0KHkEJU4gz02MPgjc2RDBL8iz3Dq4D9psMK+fMS6s9Hjoj -5ZInOPXpv4JtjohyVclxBgY+dsuotOPanGH2Cb+sLKLPGTEeosYSIfKzGmKBYmx9 -vQe21qVnWRRwWBudqVwVSVSAWLxLEV0O50OxgYF/kieN+2hl6xZ49mh2t6tcpr/9 -crcndWhYLWAyZdPl/f4agVcbX/g1TN2rDAAgR9DVuOJEC/u2OdTqvN85DqlD100O -ftD/3iDyjNM0Xn17m0UW4rxBJ1qzAt6uQ9Ccpl+HXf3Yhc4vxe8A7xtgM/PFZpmN -+MHciuZ8iljRLcc9QByyCg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5088 ) -`pragma protect data_block -zC/xYWcf8zZCLGdo8fvzvA4Cfmo5QeWLxffNdB3fNO+IYm8qkyUydAEswNf++htr -w8/pcgKNTGwNYiX2SMp5GoncPUNcJDchplQdQex/7/4J4jcYDjuh4wLgma7S8CZz -63E5aC67hWhvcwipW3G2YMDOiquspOg3a2LTeAoOeqYo7+VClRWJWxATAeD4GJMA -pOnXzDjQkhiS9f17weNENLKUJfv9vy/gT2k7UtRbZgxST8Cn1BrUhvAp0G0YrVky -HOZiIitmuFff9/ElSy6EQ81iKfmcsIJCEHziYq1MIddOtZ9fod/ZrdRGfDVEZ/KE -wAg9EsdOjvktPzTIoYpm//kjBveL4CnbEW5H6dcKjBcx1GO3MdmOy/380CYKNq4e -dGBQJaQfVZeDHpib1Qpu5k02ZYYJtOV9ZQY1Wb8yTCc22/WvFYUE39kUZWAsF5Rj -hlXyfmYy9h4X68zy7DMn44DwS93kgpVqo8plYlri3y0v1EdMvurRfoXX0at7hGXe -Eq1mXTnP5tpZ6vPRTeWlwDqUpPZh0NVNLqhpItjHImnCQIjk3sEBdMVb474JNfvN -R41ap+Sn0s9hkPRElX7aM87ME9ugdQc8y3a4f/SrdTqjOl5nSoSwMWhAJABLfQrz -gLvyMP6pCvQcWslCHTfXzt90FoKGW76+c3yGZtK/OBbz727KeqzIH8/V5TjfmbJl -+oqgtpIzUPNFGAKapbiJ0TyAUNmJGGn43tSvbhd0FKrrT7suSF2EVMIlFtZCoX3c -P8Bxs/D2KJzHOHmYi8VVOoQ6DP59YZe6ptr2uggvwGUWlD1rEvZXeZ3vOzm/O/2W -UEm9cOomQR05sX9WcADVSvkokZnXH7yHtmA57iVB7UphRxi3leme4q5PQZRf2APJ -iZG3+04Akd/M+GUkp3h970osRywFUN+2M0eLaZghSAMocMa6XyZT8O5ufaP/c0vS -6gOctr8czd9ILH1xFv5QIBfYvbVuEj6NcQyObkQ7gGRl8nQ2XN30qkgRrZRlwhwc -79pE94LOptDN0melwE4z6f56wU33/eBm0NQcO9LOud7HXP4fEw3u2YocoChHa5JC -p9Wc6DIti6ej+4NaQ4wxh3vlC0CW9Qpqgv18MHTAH0S6zQxkvkX/V5ihqN3FdCMh -Z41Wp4BPYTZ9fj8Nh5OrJpbQdin0Ze0xghUNCv+HtKhoWsTi9ctfbvsxa9gQ7J4j -Ma5H0ZrzuvWrS+9IKoLqiaD/g0pE+lWmCm+dAA1Kzf1SzxQ6YYHufPjwYXURVuS+ -iQOGD78/c6ErsTF+wb+9q8k0Ef+7V1CMFtI2JQo8oAvJjw6XfN9y+gMBVFaSSNzY -VVxXyd7r654nF6EFecTG8o3s/gtKyzgq1Za5rOqb2Ze4NW1kWAdOEdKWL1AJbNM4 -rQiQkmJRC70aVnVJtwE+lvo3BeAGOXOR4KrXEUtKjYtuSVEQvot9W3P8TjFKxmaB -Gy7sBMQJUntX5WakRe9dTQ4zMSSEESbs71si+u/KkjLeMxNRrnWC5MgbZK/xpoVT -ZBEtR4bbFQUKWFf+wfB23h8BX2DwWyRan/tS6yljsvH7i41r7xJ2/wgHH/nRA547 -ibW1GGSLWBmvyrMQzkbpd4LpmFEJZyoybUNxwj1Orf3t45Lrgeh5jgoHGPWu16JY -gXdF9wNd5DzR/NRjqKj6zcjc7eEYTKIxMm2ndgnZz8AYQhbhZW8CpMfp7eSM5a6H -JmrhlpwqxIEUOHUZRyANREGZfXxFUvJu30WCOZqqe1/TjgqYtNJEfl3X32y5iJAz -xbVGLjgYatfvE6/Uskl/NxzQYUm6JMbg0v2B7WuAPlzJuOUzkOsw9BcpivBLpBaf -Bl5C/dlK8d19s4pooB1gsr15bhprNR8LqeDwCw3e4ItlzCNJu4kiMBXZNg05r0XV -pMahF4VgFKbMa0MFSdQaCsRxNOY3fpScFRdPaKf69xZ3ahq/N6SpKRGVkwy+KfdX -Sf3H+Nq2iOj1PQmkug/dK1iKTps110AFUn/mC/ROHKdbmqlpLW/gM5a/2zxj3XJC -Jp/3XzvuSeoUl29NH5GK374FERJ6vdOsGnBi1R7Uk2i3JixeylUzJ8lZGt7yhWX4 -117lZq1d3gIodecR+Cv3XFwmOkaePp5RCqOSkQhpeDyESXmfnG7rFtrNBEFYz+6Z -B13x6L/qG7LeIsVA9QFJNfpFFf83k2TwG1zE4vaJTwab7N/2UvRRpJSBKiYb+omH -lOMuwRM27NLIZb3LI5pe6T8a+6mfqlVFGLHX5V+4kma8CqX1E3EPbu1jfduYz/QE -4dvg8RW+5VEVy8YdX7awN/iUVVDXJBb6miWVLWlvapa9vWILp13rQU4D3Sdzn77e -oxieY6vPCtocbT0AzaqHap1iQwHvPX84GgvFN80Ejuvq/rJ6+YHZ+XwunX8/hThy -gImPZXCa4Oq6hwil72vQI+SmlgUZoXe/KRS5Kb7veg30sC+61vHwwmwbmpL9xpy1 -a33pvU1qJl8hX47U1LoFG5AOaS0bGdtJUtx/eqRKEHzxw3Da54/vk8adDQ2/Il5V -Ptk2kaGYMIFadkjP47LIpqfXVOR3OyCL0J3kYH54D81rqCkSpAEBOx8NI9izReec -zXut12B7IquWIe8GPrMp4kQv4EEMvBcsYT1e1VBnbui85mNU2PAXHbAfLm2LeZXb -rBdXQL5cfgYlkgJD3YYOOAogH6bzjDeERAIUvzjo1ZaJToqa/5+otymhx0+V7ZEb -6eAfvsatx0/6H+LlOnAE1R/QmOvekqoF4uTjpOCrWXmZG1u1QBwvu2k8uc3hfBAV -09KhryYDm01DAoJybu2aRmPnUfr789bAyVNfh3U7b1OW8/OV28tAzmy7UMOa4WZp -k2+C392MZ+T/IyJ5/NbV+pRE2i5mBNH/idtwpZjw6GKbUH1z8YVtcnBYxrFofb4q -sbnQjtre6o21ojIk6US/k16ssIy8fZh/NqLB5ygXSLEGOj/ksNcxPtjDOGL26f/+ -UBPCWJlIPvKYQzQG1NUyAVfXC9oO8CLvNx+MXAjvnWO0BsgOeHrejoMu4Qg/ZTEo -s8UE+3fzjrxm+qdFIci737IBpZhukLPYU3RgvaIxnJpNzqFA0HSecqcMb9b/spVG -kcmHG2XN296QApxiKTVy6o54NlDDRRZt5G/Hj/sMTKqfeg6hUhyYU4hSy7+me5ig -7av2iSsO67wfiyi2BTLgu6gVYCesRiq6fn6qEUqrPeQLAr+6mxqry7IuaJ6dJSo2 -nXPvH9RofaqLShdDoMueMyZ0bZxDDbD8jzMVBhvEDB9H0t1bxmLBlfRyq6SZejKV -XethtgRO1bA31FC9mPig/RgSMKsrHvCAz7DA7aqhBIAyhA0H7Ox+Xt6gf8lIxA70 -wHOci4fs1m2/MiIrXY/MB7dpoK7o2eyPJuxDXp3U2jQhHamklfzlu4fobQ88tHcq -h5h9htUwqXGYVplPMDFv8TSCwazSSFg9OBykImgEU5HQvWzAVhXV12oTvLZt4FIh -RDeBeB13dThmW+hrEhKg/AxCXFsBjXArpHLAtqsByUS/mv9E+FiHr4/gZEpOX6Ou -M2jQX3bwTBe9OKFhz0uFjauWgA49tC9nPGlSonxaSG40G4m76PE6tDOxNKfrxe9u -XWU5TUArWGVrKwi/b2WRFk6uB5ePix4VBcXKCyWcO/ieSaGk85wFOlKGdgatmOI9 -xURrf9uTqaK5Ml1X4WWXG2k6CEoYpAyzNS56ytcCQsALNU8TBa1tQkYcKuNxSJwX -2ZsC2PlGHm5atDHQmpvGolTH56g3RoOXrhpMsS4w9ZvkK9ScCmWXx2akd+qBvYti -i7EsnTlhPJ0WhFwZPePxgbDU5dd/ixOM0ml+qPj1xt6A/4i/9jbkGQ+AkQaNY+4H -/hEManBUCdJv2f3YOUxwXwlmhhcq7RbdD+wRrgBo8ek2R/FGTCMPzKPgIJD+7cm0 -USs/kYMDwCc70I+unagGbPWIAypZM8Zbd/lRqZxCAnm7/Aux2Fm1vwWNODPK5jAh -i0qEqymbUDP2ewUT13mzxzDshba5jzfs8mQlQRl3eDkB+nOOHu66hUrWe/FiO09r -x8nIVtSHZ28yxRav2jil7kUl9afSXrmMs6iUE1ZwG/JmxcL2MjOvMhUxjkLTy8ee -bNefgGUiSCoMm153BBf2KF8Xh5+F+jGTg2XaLfJ0ehryjwE1a4IwZUDIXur1xOKr -55qCR8czixRsNDtziAxmX++d3Jmt9XrrcWOFAxto9SL6jdCXCjZGoar9be2QSe14 -36Yw6q3pwSx2uJxDzysKYfaBsOVEMuGuwm+KpelTzaH/QuJc7VQ8TEsD34Sw8awP -L/Zj+mGoeZ5HtmyQVFIXUVDPd8ZQlH2sleiUYQD1GwMIvkIBNA1ujdARJVT6fW/C -o7cswuu8qxARojABI01AZUfZhHhrni+xMr9LTxBD3BMMdsbeqgMCe/DLqf/kjqQk -NxahT0dYXIRCs5bvk5SMbZXBNdH8GhnZ5vZkO0YSkjRhco+lBx9ncu75H6IcGCxH -dEpc6kbCAOPW9YPVvtvrGhdnjc0V6dAzbmOSjOoDH1V18uq9mNV422eAIQ5kbENK -zyAl8te/voKW2Mi8ENgoe+6cDLyEa09xQNiRijhLO9fUwd/8oRpLEuYLMFcCc4Pl -gnhiAxF26UhkH+8Rq4SjiAF6sWk5pwW+48JTVXTbz5QARsfc4kdQH7Y31rkN8HLL -vQTVQqgJbquNJhoweAcN4dB1hrOnk6qodd0yZZizi3zGNBP8wRp4n6K0rM2qwBzf -cwcNFJRwA9LsqbrM8lEhlfuz6T54W/ar+OPYw7ZTM4mz2yYk59Zt7UFSzoquUPRd -Xd1ErXaxVqgNfjB4z9AhrTE147Y0RP5wZNmoU5XamH7npuGTLRw3L1BpKO2M3wT1 -J6Pwtb/eG14gGVrgVB7DJpHYfDpg5QSPUjkkFMBOxxbe1+jXUlMRmhbcK94m+BeW -Fy1GQ+bEJGXVtQ+EteKZam/xUj0cdJ6CzOSLqpfM6zf+/zdYT0mECoIPYio8MNZB -mtX+QVh+/pp/FM/u4H/LTrqPraGZaMQEfqh87wRsXhDAynlkeW2ShIi/GmaRYP+H -NJH3h6Je598+wSG+o/KFX6/m2OfU3ZYakRrIYI+UBT6+qI82zwctqeZzL2nZvNX6 -3uLUAP7aHNBjddxOVg+9fG46+VHpqt0kMeCKDXXyykeE/wT/tqDzoiXHgNbPo6rq -yOh9nzfyklim0Y/mVBHcV+wsrdeTEOJGO7sjs7hr1HQQbPMuKZamzbbLBa31jE5f -dXK1OufQbyYcnEHVuyDMt6wFMqpCtjdZydJYgW4lv3aAm1wpzhvYTvfJatjHcxzo -nbhqAkqCvTfz1w8sCNyYy6Te2wWXPhYfj0IIJxhjzKJWD6GSxBnpvXYgPtOV+5xV -HHdHX0d0PS+ECPBtkooHM9vSyNmIV0BOnTZPmqLYs5t9jJHDjEaRswEv+2Pew8SS -LcpFL5Yq9009tkPm8EFiW6UElEcXwNmI77GoQgNj01R/q6H2a61+8K0oX+8kOJ89 -NuAn6iONzSbCYdy4OCnRDvfVFSIhC9ij4f2UxApAUVW+F0K+GoiZN1rGUcNp3pwn -ZlNbwZKM+agp0fnZavSG4rPMQNo9S9s4YEtqpUzgUlE0RIw41P+w6FFTK74k19cz -lIDSkMB0dILeooXzRm39a7dp0yT6M6X+YeePqRh97BE5hdg5PchDVRauZrhU6q0d -265GeDJsyCPmDqcrbmQcM2Ho4WtCELCkXmX+AGLxZFOYvZ8g5IiEq5Tec5xGDgK5 -kLuTw3jXZwz5oVjRkgJtz3bzhHkSrBr3wAAAjtnBftYOJvpMtjNeqoc/aOE58h49 -b/nlxDNmQL5pjm3N/deLApaIFusruWsP6rVGz8UnCMJfMVP6PLpCrjkNs7fcO4fW -aCDyvHs+/rYZpaNwnowx8gcduXeFcROyV0YqVX18Ul9pFPa/bZ8Fh/Lc/j+s3/3J -ABTvD0LwxDjZVbP5ZqAAgxsxqQOIhsLEqy6sw5sYM8kYOyqLk8tW0S2Vpetz0y2y -xujsOQ9I6Oyt9CroQsNJAxAErHtOmdUvsv3DxbhP2gwmb30iUHpYE/95IS9oZzO1 -2LOdoAMT4f435yXesIUuMIwYXuuJ86qtGRI/S4TL6ufDb2V7torh4CTzO3sGS2hY -Hz3bP3Ysn9jO5AKR9M7V/VRRKvt8iDfltZHif9Qeb4Clrw/r+ops1X27+DdnLY+l -NEU/KsVtRxAVBd3zzUK3mKAu019ODAZc5Zk3js2T29lWKTFwVtgFtPyUQHLVygYy -l0hfIjYQL+D9JGsU3J+zqjWeLkvFYHc1NxbtItInwkqdjBUCZ1oqSOvSf0eAoPNR -yFmb7f1HUauvqm5IPhCtle9WhKWsEjmMwt/Y0N6hY76TdO+MMmGz5hm1OrFVRx0K -qeZoEyB/a0HM1e17CobGXHUMGd3Q7mPBY8xTpZLaXgTdRXrJxHL42S72sVYDX9sA -k7oBG3ZpGjZgAeHCnSAg5Jj6K6cE+QLuiN86LgN8VeU4rl2WRXf9vBZupNCKyQft -RIh89JYJw+GADB3mqqvVa3VfqyHGX7EJhfZQZnTZmi/Xh8zlPO06paKUuMMxW1sC -3fgJspJeiOpR18mX5ZaEl4YbUshQuezlZoq+xYKQcDNzDLp2kkdhYpzFFWCKujTl -Dh2SoorAIdX7uQOrctqIukPHX1VQuH0NjaIQXcE2DQhK1xjf7HNJ1X62MuwTl3jK -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -dOPtwFtLMcPenaEyGyZsI+s2xj0m2PnKI0HIO0J37nXu9s/URaK6vVkiRIlFAGEc -jCfFmEwDYWhHhdcMMJEeZ4UbEKbS5VAoryHReu51Guj5uwrM85BA53UcCyiAZeLI -EdS3yjfRYJaaq8xYdFrHJ1KpIomCt44AcjX5LRkSbA5prRgzbc/21AHDJHFTEfKd -39Ax/IAlqD3WzO6qUtrvrSaM6Hg+cHV63JSv0MOKYpKgTCPKKoIOvv4+PRaqitlV -FIMIGL5XFDxZWTuv+pweh4TnT7/cGMYXUnBczH1SdsfG1UB9U2S01SifaQbG1Q2v -OupVr/2wpDbCfxGqLmdxhw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5664 ) -`pragma protect data_block -w+3Ys/3cYEzxgh6mGd74Nv8Nbh4d+haY0IAO2kthrTsBC3lR7Y0ILXIGhJsCndbu -gyy4q5s3MHerBwrCkrGfGh91QNuyQX8nns1gNNdnp92ZQyVuAPOUh8lqelgvZMPx -LhNafsi6AC/pv5HB96G9z4qTfKzTgeDy9o6ouTA2xC3equpsYNOzNvzj1DrZuA6e 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-JsnR/eluEJW9cCNe239FP+sVb09Lb7zQ/SyPuSAiE3nFuN6cY8mQ57K4M5mD2BuP -cc7YwPIQ5otEyTjH1j8F7B5UlNk0prTHrwp4NHwbhlDKKAw+AsgDO4wDdYTWsppZ -XVU4jI1veAF7+obTiD7sGw3b5tEi7R0n6GnO4GBEc+tdYEtMHmxza6oNhZT23541 -hCO3EWoTZfUZUpVCGv1O5wCF63roWIokx2EgMUDmwMs3lQV0Uv5sDrVYb0KL2/F+ -vAe7xiacrrSYQTzhc6G1ZmsimtYfnIt2urO1mSb5FuPuy4JcGzOrWmOSqVrAuZT2 -xXZcDkqY9is4wmnzDQY6QBoTtlecrGRuLUDvmdA23yTSqwYr36XZkAAoonro9SAv -PqlLP3pUnIPHocFVo9Ud0CjW4m1nXdMpIWApDUZd/Ic082VIouTvr1tewFXMor6L -qaNUDn4H1OdphUzx8IwqOZAK3rSGwNyWPES4aIxxr2bcYsSnLT7xwW7NEQ/mbHYe -Pwl48lfAWM/525m3HPsYu45ch76Qf6OsMuZrmVIqUh5stjAjvKjBC5Y0wlb7HXIj -M/kmPOg3del7Bl8wclajmR9BAiH4f2pVNvj6MeGEZ4xjjUPiovs6IcYuAoDtyP82 -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -0EdYk8u9EcHvk5jqhjgohDTjVAeJT375Ef59f7yUuToa5zLARg+3ZhYxjn+3f2+f -GHrkhwUVyhyqbT8WjkrsEkbFOY+QQi4ZdA1Xj4Z//wG+fcEvjjatYv48Sz3YtuOH -QUP817ART1osb2GtW/StscEKBvMutLk+Snqv3QkHb4ev4y2y3KJtwzYaBBCh4HP3 -fctt1g52yiTQCFtcd+8R7WACRO21cZs0IoR+ctw1Kbk6yZBnnIAQYsMlvYYUNJFr -csfS25mNE9ui/mTPN9AcyuaJ2FfdK4erHR1Fdbr+BAa0sKHxg93I8QWo9O3iRy+5 -kVk8iGT9nN7Mv+IhhkiGAg== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3504 ) -`pragma protect data_block -EpUzHnZQ6MFzwaYdo8W13JVbZIgyghggaxTmb1JmEjhNwkKWhkMMC2Ks++6VLFEk -wYduO2xhSsY68DNAiD9BSCQO14ss6qzU2Qfp8bhG3qdWn4urrh/UgiT3LtrttRvB -WaDtTLoU08YRIi8SpN50pbk80kg6Q+u5OiJrUypY8/MCOE+A7R/CCyUX/sE1N2Vz -MYYc5oxFcnxfEvrLE48IdwDnImaeGHM6yJLyszgX7jq9rd+oo+eDcscHX9kbfoRM -NlBdtPyFUfkBHHI7+FRP7Bw1sqf1Sbs10VmMF/dS5Xtr/OlI1xfOJYckdOoRTino -ADlKD4tOg72Obe0RIXKIrVf2ogd8yZNkzcKqLX6Q8W0HBW7Sa3UL/QVw3W425BQq -uZYwmiNeyU8U1VP4rHQO3bl7D12IvkxV+AQPqmIOeYg299UEXWIFb2iELLLHaLg1 -+2c0X1N1Gmbs1aMtp/2WxxS3/AdsDbi8rsgAWMftd626UWTv6xblk4fmaTewH0EI -3+LYLrgcBVO0hMXXA9AEtUhgm0MO8idEPDCZUtmJEn67VoPNCo9zfXCfwNHICIZk -UMSs+J0ZkeV8MGKV+GSsZ1hGRNWculxlh3ck1jbvnTRwaohoG05VnH5Y+U8fpRHv -+qVOSV15H+e1OaGVVCOzjU9CxwglwoT8gzJ6aZ5Ed8rhvqgEXXUhB0fkrl+chVjq -j0YrFvEpTS2f0SolxVXc3YkIeiW03j+xQdTPsZUQqQ3L25fxZUaKMX4zlnRoOg6E -Pdnck/34hCYTlmLzpBC6lZQ4vnConKLioSwDyBX3q1zji5lmV/v2N+1NISVRkOHg -lk7Lp3ELDDtTSimEVwQsXlXiH/w+pzq1RH8gD4G/DgrRqt5Xg68SwiP5sFnqLKo3 -YJY80LnvRacrgYqxdGcM20XZTgAbEW5QIlmQK5CCI2UhaLpdcxedeHJViIOjtt2q -UcjLFONvXvgvxfaYTn/hGHwTllTc9F1LtNhGq7Bjk0BNtxABSCkAwzTobNufbDiL -VhEPF4Jl5vwoALSxrMwwjXk7T+ZHZ1mXixw5LK3NIgguPjGR4ucHnVKQHKYO+jZT -xhov7ZiDB/i5oAOMs9mkvw2sK4HtdxZRAkUwfDguhpLog2KY1TUk2J26H5QTUZiM -Z4pgvD94KYyVpGTuSFVVbKFAqtF4D3meT5lZiUD3KLFhZQP5bcc2V1FWpwoqiglx -H1hiFELCOV3eCjKBKIr6zxeExCxZStp9Lc4d/8//fKYCsaniUFCvVNcWPviou0F0 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-Lp1CAP0z3s8cPDpa4fqbIy3Stzkc1HY8aW2G3BiWU0Vf2A4RX5X2Pp2s1Co0B4q1 -ve8UtMMZXRwXYfZGIvq1RoAe/3/uotb/KbM1SvvMMY8tVPIg25Dqn616jyFJ3qIC -TJIrLaPjSF6YumUrirCkv0pPp7Um2mH2r3GOFdReM+TFv8kosTQJa6Jk1A57sVpF -zPCrN5Npx0B7omOSu3Z5NK1SVE8Wn9FUvqAoy/0waleuDR/35asisYFl/u4eOYO4 -Uq+54IxvLydKUrOggJfyO7vM/opnx8FG3KljOJZW2GArClk7ZlbsMa/iW9jGgrgD -pdASHRe8yF2LxbsJBkV0Y3irZgxRLP0ioUDnmcMYsI2NZBCsMpFT0ixuIw2aZvWI -e+atlpwrMq89SKertbVwncbLrUmcHUm3VRSjGj7l9oAiZHJinROODBx6qEVO2lvJ -perN0+ZYYJC5v+qyWIxbK1NFDEHA4gGtkmy+AcBOhxaHkChxp6Vr/dVoDCggfCLn -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -M8byHsCbrDGyP62CFo8IvTM3Ae5RZL5oFDkkznIjOqNMKx3MfffncMeFuVCbvra+ -Kz6I+7iwc1Fcj6DtkGGvxA4S/1nZs7iGAAvORqAF7HrKRZSfaVC5VZcuRSJzAH0i -Aewvp5YeFpmGEMBrIU4gGOOXU3vOpMTgE7Dg5mf6LqRWI784AXRaAJUNUlNSUHeI -IVbnj9YkS60Jui0wZjzP8PZtP4/xXmKdwe+gXbB/RrDoDgMx04/CnJYEJI/w+bEw -++9yzzLQxLrmwBIQWs2Zht7Nsmy21fpn0sEMQ1KcT+8EVhINv9qF4JLHeDQESCHJ -gODTw8hroSy9hCWlIflMfw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 31840 ) -`pragma protect data_block -5thCRcC0Ri4TQe7AWgUIP4KfBITUsWYD6kXfm/H/v583HctLMad7k5VlJiSTNFJs -I3SDS4IKr6jhB0mmMEd8mZdT5q2wIKrzYjLgIOPB1BnudVGS3efcTZyhDkY/jTLt -Xj/bs+iL5Kwnv4Q5SwAo44LWb8eo0VlSKEKRi8bz1E441x/XSEXl6u8zoNHsbHIE -nwTEgTZf/qA+GMwsbIm8wkywnuouG3R/RWz8eFe+qn1dsnKA/ELMWjmoxPtfvS22 -SvgcmNhTGhPszoLnENkuvQ9jX42/yo1TwH0/VhxFZdkPTkh/UbinSkQqTAyOivAd -mvKUzqJeVnAOsBrXW/SPKaKXXufPJSG+58DHq/tz+YwJBFca3LXxM9Q7ViQnwU2c -wOwgamYFaJevCuVnFeqRfMxJ0i8g7iEV/YZqzd9tTwNOo8ZZAhJz4joDNIOUs8Na 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_top) # ( - parameter FAMILY = "TRION", // New Param - parameter SYNC_CLK = 0, - parameter BYPASS_RESET_SYNC = 0, // New Param - parameter SYNC_STAGE = 2, // New Param - parameter MODE = "STANDARD", - parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) - parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) - parameter PIPELINE_REG = 1, // Reverted (By default is ON) - parameter OPTIONAL_FLAGS = 1, // Reverted - parameter OUTPUT_REG = 0, - parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_FULL_ASSERT = 27, - parameter PROG_FULL_NEGATE = 23, - parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_EMPTY_ASSERT = 5, - parameter PROG_EMPTY_NEGATE = 7, - parameter ALMOST_FLAG = OPTIONAL_FLAGS, - parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, - parameter ASYM_WIDTH_RATIO = 4, - parameter WADDR_WIDTH = depth2width(DEPTH), - parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), - parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), - parameter RADDR_WIDTH = depth2width(RD_DEPTH), - parameter ENDIANESS = 0, - parameter OVERFLOW_PROTECT = 1, - parameter UNDERFLOW_PROTECT = 1, - parameter RAM_STYLE = "block_ram" - -)( - input wire a_rst_i, - input wire a_wr_rst_i, - input wire a_rd_rst_i, - input wire clk_i, - input wire wr_clk_i, - input wire rd_clk_i, - input wire wr_en_i, - input wire rd_en_i, - input wire [DATA_WIDTH-1:0] wdata, - output wire almost_full_o, - output wire prog_full_o, - output wire full_o, - output wire overflow_o, - output wire wr_ack_o, - output wire [WADDR_WIDTH :0] datacount_o, - output wire [WADDR_WIDTH :0] wr_datacount_o, - output wire empty_o, - output wire almost_empty_o, - output wire prog_empty_o, - output wire underflow_o, - output wire rd_valid_o, - output wire [RDATA_WIDTH-1:0] rdata, - output wire [RADDR_WIDTH :0] rd_datacount_o, - output wire rst_busy -); - -localparam WR_DEPTH = DEPTH; -localparam WDATA_WIDTH = DATA_WIDTH; -localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; - -wire wr_rst_int; -wire rd_rst_int; -wire wr_en_int; -wire rd_en_int; -wire [WADDR_WIDTH-1:0] waddr; -wire [RADDR_WIDTH-1:0] raddr; -wire wr_clk_int; -wire rd_clk_int; -wire [WADDR_WIDTH :0] wr_datacount_int; -wire [RADDR_WIDTH :0] rd_datacount_int; - -generate - if (ASYM_WIDTH_RATIO == 4) begin - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - assign datacount_o = wr_datacount_int; - assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - end - end - else begin - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - end - end - - if (!SYNC_CLK) begin - //(* async_reg = "true" *) reg [1:0] wr_rst; - //(* async_reg = "true" *) reg [1:0] rd_rst; - // - //always @ (posedge wr_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // wr_rst <= 2'b11; - // else - // wr_rst <= {wr_rst[0],1'b0}; - //end - // - //always @ (posedge rd_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // rd_rst <= 2'b11; - // else - // rd_rst <= {rd_rst[0],1'b0}; - //end - - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_wr_rst_i; - assign rd_rst_int = a_rd_rst_i; - assign rst_busy = 1'b0; - end - else begin - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_wr_rst ( - .clk (wr_clk_int), - .reset (a_rst_i), - .d_o (wr_rst_int) - ); - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_rd_rst ( - .clk (rd_clk_int), - .reset (a_rst_i), - .d_o (rd_rst_int) - ); - assign rst_busy = wr_rst_int | rd_rst_int; - end - - end - else begin - //(* async_reg = "true" *) reg [1:0] a_rst; - // - //always @ (posedge clk_i or posedge a_rst_i) begin - // if (a_rst_i) - // a_rst <= 2'b11; - // else - // a_rst <= {a_rst[0],1'b0}; - //end - wire a_rst; - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_a_rst ( - .clk (clk_i), - .reset (a_rst_i), - .d_o (a_rst) - ); - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_rst_i; - assign rd_rst_int = a_rst_i; - assign rst_busy = 1'b0; - end - else begin - assign wr_rst_int = a_rst; - assign rd_rst_int = a_rst; - assign rst_busy = wr_rst_int | rd_rst_int; - end - end -endgenerate - -`IP_MODULE_NAME(efx_fifo_ram) # ( - .FAMILY (FAMILY), - .WR_DEPTH (WR_DEPTH), - .RD_DEPTH (RD_DEPTH), - .WDATA_WIDTH (WDATA_WIDTH), - .RDATA_WIDTH (RDATA_WIDTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .OUTPUT_REG (OUTPUT_REG), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .ENDIANESS (ENDIANESS), - .RAM_STYLE (RAM_STYLE) -) xefx_fifo_ram ( - .wdata (wdata), - .waddr (waddr), - .raddr (raddr), - .we (wr_en_int), - .re (rd_en_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .rdata (rdata) -); - -`IP_MODULE_NAME(efx_fifo_ctl) # ( - .SYNC_CLK (SYNC_CLK), - .SYNC_STAGE (SYNC_STAGE), - .MODE (MODE), - .WR_DEPTH (WR_DEPTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .PIPELINE_REG (PIPELINE_REG), - .ALMOST_FLAG (ALMOST_FLAG), - .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), - .PROG_FULL_ASSERT (PROG_FULL_ASSERT), - .PROG_FULL_NEGATE (PROG_FULL_NEGATE), - .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), - .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), - .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), - .OUTPUT_REG (OUTPUT_REG), - .HANDSHAKE_FLAG (HANDSHAKE_FLAG), - .OVERFLOW_PROTECT (OVERFLOW_PROTECT), - .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) -) xefx_fifo_ctl ( - .wr_rst (wr_rst_int), - .rd_rst (rd_rst_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .we (wr_en_i), - .re (rd_en_i), - .wr_full (full_o), - .wr_ack (wr_ack_o), - .rd_empty (empty_o), - .wr_almost_full (almost_full_o), - .rd_almost_empty (almost_empty_o), - .wr_prog_full (prog_full_o), - .rd_prog_empty (prog_empty_o), - .wr_en_int (wr_en_int), - .rd_en_int (rd_en_int), - .waddr (waddr), - .raddr (raddr), - .wr_datacount (wr_datacount_int), - .rd_datacount (rd_datacount_int), - .rd_vld (rd_valid_o), - .wr_overflow (overflow_o), - .rd_underflow (underflow_o) -); - -function integer depth2width; -input [31:0] depth; -begin : fnDepth2Width - if (depth > 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p -yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU -De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF -GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh -0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r -mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q -z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p -yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU -De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF -GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh -0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r -mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q -z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx= 2045); - -always @(posedge rx_axis_clk or negedge rx_axis_rstn) -begin - if(rx_axis_rstn == 1'b0) - rx_axis_mac_tready <= 1'b0; - else if(u1_almfull == 1'b1) - rx_axis_mac_tready <= 1'b0; - else - rx_axis_mac_tready <= 1'b1; -end - -/*----------------------- Fifo 1 Region ----------------------------*/ -DC_FIFO #( - .FIFO_MODE ("ShowAhead" ), - .DATA_WIDTH (10 ), - .FIFO_DEPTH (2048 ) -) -u1 -( - //System Signal - .Reset (!rx_axis_rstn ), - //Write Signal - .WrClk (rx_axis_clk ), - .WrEn (u1_wrreq ), - .WrDNum (u1_wrcnt ), - .WrFull ( ), - .WrData (u1_data ), - //Read Signal - .RdClk (tx_axis_clk ), - .RdEn (u1_rdreq ), - .RdDNum ( ), - .RdEmpty (u1_empty ), - .RdData (u1_q ) -); - -assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata}; -assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1); -assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1)); - -/*----------------------- Tx Clock Region ----------------------------*/ - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tvalid <= 1'b0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tvalid <= 1'b1; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tvalid <= 1'b0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tdata <= 8'h0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tdata <= u1_q[7:0]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tdata <= 8'h0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tlast <= 1'b0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tlast <= u1_q[8]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tlast <= 1'b0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tuser <= 1'b0; - else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1)) - tx_axis_mac_tuser <= u1_q[9]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tuser <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/Testbench/modelsim.do b/fpga/ip/gTSE/Testbench/modelsim.do deleted file mode 100644 index ccfb639..0000000 --- a/fpga/ip/gTSE/Testbench/modelsim.do +++ /dev/null @@ -1,6 +0,0 @@ -onerror {quit -f} -vlib work -vlog -sv -timescale 1ns/1ps +define+SIM+SIM_MODE+EFX_SIM -sv ./temac_ex.v ./apb3_2_axi4_lite.v ./axi4_st_mux.v ./mac_pat_gen.v ./mac_rx2tx.v ./reg_apb3.v ./udp_pat_gen.v ./tb_header.v ./tb_top.v ./ODDR.v ./glbl.v ./DaulClkFifo.v ./modelsim/gTSE.sv -vsim -t ns work.tb_top -gui -voptargs="+acc" -log -r /* -run -all diff --git a/fpga/ip/gTSE/Testbench/modelsim/gTSE.sv b/fpga/ip/gTSE/Testbench/modelsim/gTSE.sv deleted file mode 100644 index b042cf4..0000000 --- a/fpga/ip/gTSE/Testbench/modelsim/gTSE.sv +++ /dev/null @@ -1,4617 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.288.2.10 -// IP Version: 7.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _4c19f37180ff465ca20760e199a0613f -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gTSE -( - input mac_reset, - input proto_reset, - output rx_mac_aclk, - input tx_mac_aclk, - output [2:0] eth_speed, - input rx_axis_clk, - output rx_axis_mac_tuser, - output rx_axis_mac_tlast, - output rx_axis_mac_tvalid, - input rx_axis_mac_tready, - input tx_axis_clk, - input tx_axis_mac_tvalid, - input tx_axis_mac_tlast, - input tx_axis_mac_tuser, - output tx_axis_mac_tready, - output [3:0] rgmii_txd_HI, - output [3:0] rgmii_txd_LO, - output rgmii_tx_ctl_HI, - output rgmii_tx_ctl_LO, - output rgmii_txc_HI, - output rgmii_txc_LO, - input [3:0] rgmii_rxd_HI, - input [3:0] rgmii_rxd_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input rgmii_rxc, - input s_axi_aclk, - output [7:0] rx_axis_mac_tdata, - input [7:0] tx_axis_mac_tdata, - input [0:0] tx_axis_mac_tstrb, - output [0:0] rx_axis_mac_tstrb, - output MdoEn, - output Mdo, - input Mdi, - output Mdc, - input [9:0] s_axi_araddr, - output s_axi_arready, - input s_axi_arvalid, - input [9:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_awvalid, - input s_axi_bready, - output [1:0] s_axi_bresp, - output s_axi_bvalid, - output [31:0] s_axi_rdata, - input s_axi_rready, - output [1:0] s_axi_rresp, - output s_axi_rvalid, - input [31:0] s_axi_wdata, - output s_axi_wready, - input s_axi_wvalid -); -`IP_MODULE_NAME(efx_mac1gbe) -#( - .VERSION (16), - .TXFIFO_EN (1'b1), - .RXFIFO_EN (1'b1), - .TXFIFO_DTH (4096), - .RXFIFO_DTH (4096), - .PHY_INTF_MODE (0), - .AXIS_DW (8), - .RGMII_RXC_EDGE (1'b1), - .RGMII_TXC_DLY (1'b1), - .INTER_PACKET_GAP (6'd12), - .MTU_FRAME_LENGTH (16'd1518), - .MAC_SOURCE_ADDRESS (48'd0), - .ENABLE_BROADCAST_FILTERING (1'b1), - .LOOPBACK_EN (1'b1), - .APBIF (1'b0), - .FAMILY ("TITANIUM") -) -u_efx_mac1gbe -( - .mac_reset ( mac_reset ), - .proto_reset ( proto_reset ), - .rx_mac_aclk ( rx_mac_aclk ), - .tx_mac_aclk ( tx_mac_aclk ), - .eth_speed ( eth_speed ), - .rx_axis_clk ( rx_axis_clk ), - .rx_axis_mac_tuser ( rx_axis_mac_tuser ), - .rx_axis_mac_tlast ( rx_axis_mac_tlast ), - .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), - .rx_axis_mac_tready ( rx_axis_mac_tready ), - .tx_axis_clk ( tx_axis_clk ), - .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), - .tx_axis_mac_tlast ( tx_axis_mac_tlast ), - .tx_axis_mac_tuser ( tx_axis_mac_tuser ), - .tx_axis_mac_tready ( tx_axis_mac_tready ), - .rgmii_txd_HI ( rgmii_txd_HI ), - .rgmii_txd_LO ( rgmii_txd_LO ), - .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), - .rgmii_txc_HI ( rgmii_txc_HI ), - .rgmii_txc_LO ( rgmii_txc_LO ), - .rgmii_rxd_HI ( rgmii_rxd_HI ), - .rgmii_rxd_LO ( rgmii_rxd_LO ), - .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), - .rgmii_rxc ( rgmii_rxc ), - .s_axi_aclk ( s_axi_aclk ), - .rx_axis_mac_tdata ( rx_axis_mac_tdata ), - .tx_axis_mac_tdata ( tx_axis_mac_tdata ), - .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), - .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), - .MdoEn ( MdoEn ), - .Mdo ( Mdo ), - .Mdi ( Mdi ), - .Mdc ( Mdc ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rready ( s_axi_rready ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ) -); -endmodule - -//pragma protect -//pragma protect begin -`protected - - MTI!#e;@xIi7[-HGzLj~uK$ABr$Zn-[=27Ae'i}@{^NE;{e6lAK?nvVnanL_/'ua3cAXKuv?3BaD - V;$uMGZ,%lwJ#*+[[o_n=['CW!Ul$HUl_T{3A=O#}Ev@;7IVvZX$s#;\VpE[%H'vCO]}}q/ovC!l,oQ$?;'vGBX1nmXY~Kj*j{pzRA]n - V!wX^7Z_$2+bff}dCJuu~\uOs;>jln,es?E>K,'BmaC5ICU5x{5;mG\}Rnzs$eJ+BnzV-sAz1?G7iA5KCa'VoPO#OQCi3k^;3u#saCXAeuE - TOu'G-'-UA5#YE'*,+\T,#7>}D=VuWO_$*r'\TkY$}<\wlGbn15[$Q3u~C^$xYn~$VvDNI!URHG{ - JkT{szJ[?~{UB;Y-@[;ZR~{ulXEX[6a[#7QR_+f7m1RNCMOUxTMETI#}I}WkC$U~C>G?VCn#l2#d - FqOwj{HRU<{-X~]3zn']e=1Il~,[}7veO>#r*H[JZe5a=2Vl?sYA]*),gjlBZQp*TIlwG1ruYxoA - HD^GIY;Vzn>3[r[5\O=,3#+{vSm$!*U>erKI\^*?rom1W['Y+Dv+R,VAv?=+mzKj,_kw\X=u5;XY - amx,Z7az#=CU]'*iTU|$'e#mxn=kpBv\m5ir[n~4%N_a,=}2l$us_777oK)_n_!;\vu*~lXROEj~CiU - [$'#q7+WsACCv}$wUX5VX@pe}YeUZ9[R\wDA_u;s?>HD!>#H_'zwVHs$,prY<\dpk~JYAjzZ]e]+ - lGs\Hew'1?<]x>vaG_eA-[pC+K}7x#C>*=]F{H*!JrOVizi'<};U-*O5?GZJ0opwmI[5^Ua\O~}] - KK1![G3sQz{u!]9mz!JKRzJz!uvxIaXEa3pETQV^IYlXE[w.^@~A7m=Ze#-3@epk,Ie@+Gi^|%~+ - ~u&3^ICv#snHwIi\!'YH^I;]CG!7[7RVaK5BlU<)kA-J~CvHvW1=#U-_OpmlP2{o~*,_jzCOm3\n - ;9)A]VDRzA*?7<]O^l}Bs7'wQ{=iXAJ5pj5]luYJns{}!xrkCtR$a>[wG@C!7+G;3UkvYY=ww,w1 - v**J>kvYjYyr'Z*3N{e]\Gr'_}p@~-nTlfXCul:\U7lL2_zpPs71ie>Qp$>,v5jBm9s?T7Vu*>]B - hWAYQyX$E^CQOxsXlujE#;TT<<(rT$Q?aCIO=aU:bOioaDQ+T(U5]^l\=uY!zKoYIBy^I_~sEk1i - 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3|GY1H'[s+_}Y>Rm@*e;rl#'z_oTEpsV3+>CICeIoi*]X@ZXD[>'!UrT_mk],l@[7Y=m5-RUU*I$ - zosse_O-JoAo?leJmWNw-\eRi\k,EC^mQ'Yv3+sJv3nj - C5CKIUmIBK^I'wRUNR+jkQKp#Rlp5&c(HBmWG}j+-VY*C}A^o}$W={HgxWg;QwEJR><2l+5 - ^O+og:V{=j7m\r@UVi1?>X*AlpznAQo>XkwIOjC@;+e57\D+nH]*pepCX^ZG~!ZvWR2]C$Ye]]$p - ]3r;-@pw~1RuRC5V~zv>VXZ}OZAn>$3[sY5IY@7D^nUz,WCRCZvk[azl1{3xexJC,1oEI=Wx]\1= - v'"paaTH5;uzbjK1EGwpEm7 -`endprotected -//pragma protect end - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_top) # ( - parameter FAMILY = "TRION", // New Param - parameter SYNC_CLK = 0, - parameter BYPASS_RESET_SYNC = 0, // New Param - parameter SYNC_STAGE = 2, // New Param - parameter MODE = "STANDARD", - parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) - parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) - parameter PIPELINE_REG = 1, // Reverted (By default is ON) - parameter OPTIONAL_FLAGS = 1, // Reverted - parameter OUTPUT_REG = 0, - parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_FULL_ASSERT = 27, - parameter PROG_FULL_NEGATE = 23, - parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_EMPTY_ASSERT = 5, - parameter PROG_EMPTY_NEGATE = 7, - parameter ALMOST_FLAG = OPTIONAL_FLAGS, - parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, - parameter ASYM_WIDTH_RATIO = 4, - parameter WADDR_WIDTH = depth2width(DEPTH), - parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), - parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), - parameter RADDR_WIDTH = depth2width(RD_DEPTH), - parameter ENDIANESS = 0, - parameter OVERFLOW_PROTECT = 1, - parameter UNDERFLOW_PROTECT = 1, - parameter RAM_STYLE = "block_ram" - -)( - input wire a_rst_i, - input wire a_wr_rst_i, - input wire a_rd_rst_i, - input wire clk_i, - input wire wr_clk_i, - input wire rd_clk_i, - input wire wr_en_i, - input wire rd_en_i, - input wire [DATA_WIDTH-1:0] wdata, - output wire almost_full_o, - output wire prog_full_o, - output wire full_o, - output wire overflow_o, - output wire wr_ack_o, - output wire [WADDR_WIDTH :0] datacount_o, - output wire [WADDR_WIDTH :0] wr_datacount_o, - output wire empty_o, - output wire almost_empty_o, - output wire prog_empty_o, - output wire underflow_o, - output wire rd_valid_o, - output wire [RDATA_WIDTH-1:0] rdata, - output wire [RADDR_WIDTH :0] rd_datacount_o, - output wire rst_busy -); - -localparam WR_DEPTH = DEPTH; -localparam WDATA_WIDTH = DATA_WIDTH; -localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; - -wire wr_rst_int; -wire rd_rst_int; -wire wr_en_int; -wire rd_en_int; -wire [WADDR_WIDTH-1:0] waddr; -wire [RADDR_WIDTH-1:0] raddr; -wire wr_clk_int; -wire rd_clk_int; -wire [WADDR_WIDTH :0] wr_datacount_int; -wire [RADDR_WIDTH :0] rd_datacount_int; - -generate - if (ASYM_WIDTH_RATIO == 4) begin - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - assign datacount_o = wr_datacount_int; - assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - end - end - else begin - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - end - end - - if (!SYNC_CLK) begin - //(* async_reg = "true" *) reg [1:0] wr_rst; - //(* async_reg = "true" *) reg [1:0] rd_rst; - // - //always @ (posedge wr_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // wr_rst <= 2'b11; - // else - // wr_rst <= {wr_rst[0],1'b0}; - //end - // - //always @ (posedge rd_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // rd_rst <= 2'b11; - // else - // rd_rst <= {rd_rst[0],1'b0}; - //end - - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_wr_rst_i; - assign rd_rst_int = a_rd_rst_i; - assign rst_busy = 1'b0; - end - else begin - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_wr_rst ( - .clk (wr_clk_int), - .reset (a_rst_i), - .d_o (wr_rst_int) - ); - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_rd_rst ( - .clk (rd_clk_int), - .reset (a_rst_i), - .d_o (rd_rst_int) - ); - assign rst_busy = wr_rst_int | rd_rst_int; - end - - end - else begin - //(* async_reg = "true" *) reg [1:0] a_rst; - // - //always @ (posedge clk_i or posedge a_rst_i) begin - // if (a_rst_i) - // a_rst <= 2'b11; - // else - // a_rst <= {a_rst[0],1'b0}; - //end - wire a_rst; - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_a_rst ( - .clk (clk_i), - .reset (a_rst_i), - .d_o (a_rst) - ); - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_rst_i; - assign rd_rst_int = a_rst_i; - assign rst_busy = 1'b0; - end - else begin - assign wr_rst_int = a_rst; - assign rd_rst_int = a_rst; - assign rst_busy = wr_rst_int | rd_rst_int; - end - end -endgenerate - -`IP_MODULE_NAME(efx_fifo_ram) # ( - .FAMILY (FAMILY), - .WR_DEPTH (WR_DEPTH), - .RD_DEPTH (RD_DEPTH), - .WDATA_WIDTH (WDATA_WIDTH), - .RDATA_WIDTH (RDATA_WIDTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .OUTPUT_REG (OUTPUT_REG), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .ENDIANESS (ENDIANESS), - .RAM_STYLE (RAM_STYLE) -) xefx_fifo_ram ( - .wdata (wdata), - .waddr (waddr), - .raddr (raddr), - .we (wr_en_int), - .re (rd_en_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .rdata (rdata) -); - -`IP_MODULE_NAME(efx_fifo_ctl) # ( - .SYNC_CLK (SYNC_CLK), - .SYNC_STAGE (SYNC_STAGE), - .MODE (MODE), - .WR_DEPTH (WR_DEPTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .PIPELINE_REG (PIPELINE_REG), - .ALMOST_FLAG (ALMOST_FLAG), - .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), - .PROG_FULL_ASSERT (PROG_FULL_ASSERT), - .PROG_FULL_NEGATE (PROG_FULL_NEGATE), - .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), - .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), - .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), - .OUTPUT_REG (OUTPUT_REG), - .HANDSHAKE_FLAG (HANDSHAKE_FLAG), - .OVERFLOW_PROTECT (OVERFLOW_PROTECT), - .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) -) xefx_fifo_ctl ( - .wr_rst (wr_rst_int), - .rd_rst (rd_rst_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .we (wr_en_i), - .re (rd_en_i), - .wr_full (full_o), - .wr_ack (wr_ack_o), - .rd_empty (empty_o), - .wr_almost_full (almost_full_o), - .rd_almost_empty (almost_empty_o), - .wr_prog_full (prog_full_o), - .rd_prog_empty (prog_empty_o), - .wr_en_int (wr_en_int), - .rd_en_int (rd_en_int), - .waddr (waddr), - .raddr (raddr), - .wr_datacount (wr_datacount_int), - .rd_datacount (rd_datacount_int), - .rd_vld (rd_valid_o), - .wr_overflow (overflow_o), - .rd_underflow (underflow_o) -); - -function integer depth2width; -input [31:0] depth; -begin : fnDepth2Width - if (depth > 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p -yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU -De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF -GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh -0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r -mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q -z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO 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-7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM -DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI -8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 -JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD -UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 -g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY -XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 -eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ -PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r -uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ -OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx -X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI -bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe -/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV -Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL -qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ -4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa -XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc -Ei7EaFpheCmlTJyxUg8TdA== -`pragma protect end_protected - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idxUU*[oU1[5}Vus#!'AOTp_DVG;x=a - aIEzoCUHJG,X!B{}'Q>UjIGoQ7pp\vi1V3BR{djoH@BIC_~wK2}?H_&OZ+Y72BVoG!WU5*?G@_#XK=TGr\$iujV{mZ]_Zw+>A'Jo;oR!ao==Y>s?{AW]J$a$E]B#~7V - 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YOZY-XZs!~%'eD*V+m[L{IC4U=Yn&GYk2,i+@o7n#<{}rO@$\-{pJ^!+}rvajQ>EpH$#eA'2,EQw - ~uUwxpjKZms>Ds@;QQY>we#Rjj{m}s]j~l?!Y7eB2-v'~c}k]!$^7]{nQ,~R;xj-^,z\zAu#wI<-F;{7;l$mHmT!1I@Ge))Hw=H}3AwoD#rHCX[DQ]#axO@$l~!\Cp7G*2>^+'\]K2Q - 1Zo[i]r#lQ^+="+C@C]Cj5vaXTO?!W.}k!OD8pow[@jsoMk^T@'@=uh{E7T - .=-5V=ZoEopW3sv6eZ\2@RKY?]kX3wQojpU^3n*BO-~7ouV@@>4[Ip=s2u=OilV - =Tpv7?*?0hmVsuqB#Ue=@Gm?1?z]rA[Ge1'aDKG?'XZXIWW];B@oA{;G>nT+<]p}*nW_5YC]yv1e - {Ik\,K=#l]m7$wDn;;o1[$awk_]n3Ws$T|'IjXma~sE{Xow-}!mX${!TK*O7Hu7E-]C7I~O>\1JY*YWl-{kOwKu6l]O7,A;*BTEja5;g!s-IP+B![BGjAHaWChYKK,<+3vuoAX,^ - >X5G!}{s3BK'sZw#E*l_ZwxYH~{v?}6*tpa1p7moQD1+syl,1wT[ei1#eJ5'G;XOwox25m71'm7u,n$.KQx$R\ - }~X^xZK+!C*?~\,a-$C;!o,D#T\^7Uown-/H^Qezr$RIOZxzxoG@='lvA*;+RJ3[B?sb>^KYCKee - 'Kmn7vJUHlZ[.^1sKe[) -`endprotected -//pragma protect end - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE/Testbench/ncsim/gTSE.sv b/fpga/ip/gTSE/Testbench/ncsim/gTSE.sv deleted file mode 100644 index a4ca54d..0000000 --- a/fpga/ip/gTSE/Testbench/ncsim/gTSE.sv +++ /dev/null @@ -1,9954 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.288.2.10 -// IP Version: 7.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _4c19f37180ff465ca20760e199a0613f -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gTSE -( - input mac_reset, - input proto_reset, - output rx_mac_aclk, - input tx_mac_aclk, - output [2:0] eth_speed, - input rx_axis_clk, - output rx_axis_mac_tuser, - output rx_axis_mac_tlast, - output rx_axis_mac_tvalid, - input rx_axis_mac_tready, - input tx_axis_clk, - input tx_axis_mac_tvalid, - input tx_axis_mac_tlast, - input tx_axis_mac_tuser, - output tx_axis_mac_tready, - output [3:0] rgmii_txd_HI, - output [3:0] rgmii_txd_LO, - output rgmii_tx_ctl_HI, - output rgmii_tx_ctl_LO, - output rgmii_txc_HI, - output rgmii_txc_LO, - input [3:0] rgmii_rxd_HI, - input [3:0] rgmii_rxd_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input rgmii_rxc, - input s_axi_aclk, - output [7:0] rx_axis_mac_tdata, - input [7:0] tx_axis_mac_tdata, - input [0:0] tx_axis_mac_tstrb, - output [0:0] rx_axis_mac_tstrb, - output MdoEn, - output Mdo, - input Mdi, - output Mdc, - input [9:0] s_axi_araddr, - output s_axi_arready, - input s_axi_arvalid, - input [9:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_awvalid, - input s_axi_bready, - output [1:0] s_axi_bresp, - output s_axi_bvalid, - output [31:0] s_axi_rdata, - input s_axi_rready, - output [1:0] s_axi_rresp, - output s_axi_rvalid, - input [31:0] s_axi_wdata, - output s_axi_wready, - input s_axi_wvalid -); -`IP_MODULE_NAME(efx_mac1gbe) -#( - .VERSION (16), - .TXFIFO_EN (1'b1), - .RXFIFO_EN (1'b1), - .TXFIFO_DTH (4096), - .RXFIFO_DTH (4096), - .PHY_INTF_MODE (0), - .AXIS_DW (8), - .RGMII_RXC_EDGE (1'b1), - .RGMII_TXC_DLY (1'b1), - .INTER_PACKET_GAP (6'd12), - .MTU_FRAME_LENGTH (16'd1518), - .MAC_SOURCE_ADDRESS (48'd0), - .ENABLE_BROADCAST_FILTERING (1'b1), - .LOOPBACK_EN (1'b1), - .APBIF (1'b0), - .FAMILY ("TITANIUM") -) -u_efx_mac1gbe -( - .mac_reset ( mac_reset ), - .proto_reset ( proto_reset ), - .rx_mac_aclk ( rx_mac_aclk ), - .tx_mac_aclk ( tx_mac_aclk ), - .eth_speed ( eth_speed ), - .rx_axis_clk ( rx_axis_clk ), - .rx_axis_mac_tuser ( rx_axis_mac_tuser ), - .rx_axis_mac_tlast ( rx_axis_mac_tlast ), - .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), - .rx_axis_mac_tready ( rx_axis_mac_tready ), - .tx_axis_clk ( tx_axis_clk ), - .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), - .tx_axis_mac_tlast ( tx_axis_mac_tlast ), - .tx_axis_mac_tuser ( tx_axis_mac_tuser ), - .tx_axis_mac_tready ( tx_axis_mac_tready ), - .rgmii_txd_HI ( rgmii_txd_HI ), - .rgmii_txd_LO ( rgmii_txd_LO ), - .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), - .rgmii_txc_HI ( rgmii_txc_HI ), - .rgmii_txc_LO ( rgmii_txc_LO ), - .rgmii_rxd_HI ( rgmii_rxd_HI ), - .rgmii_rxd_LO ( rgmii_rxd_LO ), - .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), - .rgmii_rxc ( rgmii_rxc ), - .s_axi_aclk ( s_axi_aclk ), - .rx_axis_mac_tdata ( rx_axis_mac_tdata ), - .tx_axis_mac_tdata ( tx_axis_mac_tdata ), - .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), - .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), - .MdoEn ( MdoEn ), - .Mdo ( Mdo ), - .Mdi ( Mdi ), - .Mdc ( Mdc ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rready ( s_axi_rready ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ) -); -endmodule - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AnxLCEXIwWGNUbKODuvDDj9z3+IsvyasQalysUi/itDT2wwInQ3bBdLVigviyZBs -KfNqHVcHh1PkyYw6Tc63TbVvrM0JlKHeRk9d4Ni755Frdl+e0Yeh82+Cu7JAI77V -toSbtXAPtD6vOVPzzed5ozvhLM0NSdRFehAG9pksl3iYjKFZP6TayMWce09NBstN -j+KnL6lB7cNlu0ejMJXS7VgJ8dx8NGBDtFHQEZ5XfZo3IKXu2RTPmQkW3pU8QhlH -F8qGcX2EikZvcV+7xxJnVc8CjsdqEa+f2tIVEtB7gpGdCQYhsfE4ScprrVpuFhH+ -2Rn6AkA5iTdD385b26iafw== -//pragma protect end_key_block -//pragma protect digest_block -45gGFciNrCTJZXxwMOIqQD36VKE= -//pragma protect end_digest_block -//pragma protect data_block -/fAtlRv3M2ytzKM0VXXGACIycHPm8M1coZKa23W5ckG5VSaPQWRKFrb6mgu8TO0l -bsYYbh10DRf4e0UeK3eUMlW2Nv7PK5r0WlNsZ9MnO0NK/lbgmAILp5iX5xNmPGF7 -gjcW59pKt2Qrn7vnwhWQ63Z39ta8HP6ePI71JfesQqoYcpBSA8AmFzMf1qI1uHz2 -7ErMZ/087JXzS1/EfWz+HieVw9qNIkgQ+VC0HOg62kSOuyGGx0OlFaSSRqrkQBa2 -l5wr1Q5Xfy1pQTbh/5tHAygoyKtL/Xnlgi1THjm3FM9dv+TuX+phlOCiGL4to09Z -Qo7SWTIezt44KA9UucO1/gadJ70aQGrwfgvSO+G8xE5x+lcGeo+7NzoXvFsi0s+j -9eTGqKPEnw71QadHcPTSkKxTN0NE7Xwx076L8bPZ9m8ANfnfKX3m3i8tMSfSW+6F -PSqPF5XddstKumMgnP1oWtr8G7Zn+VyShR7G3E9tmtfgVzQsrLUHluUZogE/ESfw -AeYeJjEoRkzLwRFCKzy0R6BEzeZvZfZ0xv+s38XgmKvEpE/bVplAqDpmFaWpNcWF -Ru8sYhk8Cdyodw8M7YzSE+sqGI4OKHHoZdV75dQof86i87NiQiesruNAVRwbXW7x -fMohhn/h/mhmuE8nKssOyKahZuFxL1ich1gkQPdFZHvvwynRBdS/e5i/6AaaBIBP -bR8p9b8hk3ni1xPjf3lHM+s8LvIwWOC9hoOSzaeJh0K6n39T0LnH9uegg/eGrSg9 -hYUOhRon3mkfbIm3pswVQL/fxjjfwRy1u5yT+1Sxg7JfShqilW/BxEVRr9Vxd+rO -5Cflt4nrXlSTPZrTQSnGiwNKHhSFBEe0RzV+8w1yfbi2NXVWG0US1iKg4p+Op354 -0kJQhKlWcJRODiobUArS4ggIcIR5w/GB1xjpY/MmP7Ow6X8ZkybvsDzXK3bP5UME -hPRFCZKfj2muvkYTY4dNgUhNzvPf3WsIbbgif6UKDDNPoTTUK/GXMfbPqAwF6Zwo -mAkIN054CU5DC8H6Emh5/7fLohI0Z6HQGUV2LETHFcO72lREtIo8QySjIPWGXQt3 -tifo6++SzquMqk7Rekps+tUpor8nVcp1ZDq73IthGNtLY3WhuvNoaC80cno0mcjn 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protect end_data_block -//pragma protect digest_block -ccHJ1CIvmCRS+nbWgLQWKS78CiY= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -ARIzM20qvQsOhlemikp1MkhOGVvOqdCptklMFViFENgrk/BZmZ/vFkAL+ZtNt+Rt -gKaoV3CumDZiaq6j1xjRczEEuHtJJdWTPTpDnzJNsuHqOJA15YIcT7YAiS+pDPrH -ba6+VIqZO/0yjRlkoCPVqy9LkQ/xrWMKVbYMlmy0Id69u06KGbU1p5j4cb76uOMu -4bWZZrwVWlKStkTuJxrQaxY4reE/4p1IFspfvCOMNbfhGS5T9NLNuz4Ar+fLhiG4 -h0eIDLgy4gRmRu5lYBBfFDJkzEwoXKCyIu4bc2aTEbIes/iyxQmnggy0jAde8A39 -TdTlABcW1iLl/z9STeHQ+Q== -//pragma protect end_key_block -//pragma protect digest_block -n10L4UZBiziO4pZGJcyPwOagmTY= -//pragma protect end_digest_block -//pragma protect data_block -ks92l8Pg0utWHydDDfUWK9bco9hKy99Ce8wQI89GnW51fDBoSkKipLRroDYR4L4Q -KMxBd6gEhA6tCEBZ5pXXPbMQVWfaTgWvgmvmgJM+Q87n4H2sIERbqjFxtVA4jsAQ -GKjqpvPoUxomiwwwnkEhSBcn4Ln/INnrnN5uwLCndauYhelZ6qq5wwVTsXZ18oiF -muvBDozzgaFd6dsWb6tMSgKGByOe2tbPQ3Ze64+pl6wB+UsLu8Nqrx1MybBEYqhd -XpM9Z2OoRtbv3goP0Q9FMC0F63Q0/M9t4ZMaR788I5ZOhgXiPyeovcj0cB6JgEV5 -fufSyfhl3czHHTjcBqoqKlwcS23nyyugFwexhqMTa9oF7U2q8qancROWTSHDIBzL -IAy4xMe/+jC6iDSpG6X3Av7yKHUlT0gErKDciaW5NxJl6yoTx3Y8wF00QiOHTSjT -7IULO5VkuSn1wXa5uSOzKaRV+7uLVS70BtKW8IqacaGerzIohmYqxrtCa5A8tKSP -epAJld5IzBrNY430eue5o45udqkxEu9fcm+AYLm/w7lErz4Q5JDtoyDFBlRVJMXb -8PyqE3cavcbcj52fiqDfpO2upZkj5HXjknZV5vWg3ed8CC4ftVuMQjYJnDrkMtVL -a31AaGyx1vjrolR18SJn4AL46lDUF57Vfx5qPmX6/yczhMV0n5CvtwonTEtHdsRL -ceUWg+UakzBg9U+v9SOxF5G4q1dK08XqqeIWp3n/B8uy86/eAcsSZfMqGoiQ9t3k -qZF5bmYZU4a/brz5QmvqEPpEO9H1c6H4D0Y01gxeVhIT7kMyaUsLXoLx8Ou4Fcsz -YZ+jQGqXlXkMwjKdh/NTbPjZzkrwJF0JsBGFY12Sked5opcpjQca3MjF4WB4lGSB -PokbR4TTMd8r/YYSFm5C77f4HqTUUzvcUQIRUblxO4P6GD65frrIcK922fuEYvaz -//pragma protect end_data_block -//pragma protect digest_block -6Z3kBITlGBQ1queo/RSCimERKpE= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -Atz8tucueABxi6tE+6GDTFGVUzFguCPXX4a1GvHwgkopw6puuI6B/bguieeIeHkL -tgEqfHMU6A0PrYo8SKDzwI5DlGQY/DNWJhbkmWmo/igpJ24aMcFurAskETQkgSIw -IvhTjwwxL0DMnTN0Nn82TOAVMnrBgcDSPDk3+xiL00APePbf79ybpd7wV8gc5FE2 -VkXmLpxK6HxOdbeNRXpD0EwIwh0rz9cRbRNhKklPnAhKLokzOFTALpd6HxvLxg+u -PXAhC0TBY0AfXEfxX9EkGMTXSRFuL4e/Z4hvMY2GFC92HLrzm+zpmFYIIXpSdqmm -mJ1+NJbHvwYN0VTqmYim+w== -//pragma protect end_key_block -//pragma protect digest_block -Hr63lrg3B3IJZh8a3CEdfiqq8kk= -//pragma protect end_digest_block -//pragma protect data_block -9qfofxU8gWlHm8zNLCS+VqBoZEIOR5k63yp7QPGH/vDHxQwY3utVDj0WWvYVxXsb -apzYXBOoIkJ1b5kSMf3n8GB0qqwrHuozP8xAyOAqOUQHDBSxXonyBPNC1hdd948x -g/wYLzsI/bPCJKLrMFzJRVGJh9wRtwfR6BQJvR3z1PqfqEDeBa1datzmoNoI2Kjo -XFSOh167i4WdW8/i90vpxoy3MM1+blEWNW8NJTvOsVMCaK/ZFuiHfYb28uzzXiRF -vI1fW4d5SGJB1cL7oGe+0RDzOM1jqOPnQelxD2fO4mAB8d8+R/yLZkrp8BljLw6A -TbLTI6l8DC45G6LfUTEkpC5x8Cio0jJXRvG8i6FGlZ/zIh6kh0eBm/JMoDqXCEf5 -F2SWDK/ZBl0FX2d8VOCKDx9x60oPjmi7E4rmijTXF8N1kJaDY4jtDxoFaVBaNsEO -6IkXHJqrzO5LDa30WxStDljF1y+CYlHCyPJJdDoMooounxcWFZDgO6HMmMwg3KMM -YN/UggiY+eqqQ0Dc+rDkYrKFjvWWyqCIP65/IPee8tM0WLaOiY7njKWhwlU7duY4 -yu29Twsqtw+9f1ZA9N8TARtkKOIN1kcoGA27eeGTH5wIu9U8YjdpxBtTCowMj5e+ -iRAolrHCF7RAoXtpe/qe45sJ0NegAWwmq0CH5uxvo9HDkpOU+XACgSBKkH8yPlbr -t9GnQtsncgQNJX9rVE0YDqtyIY+dqC+sVlBQ2QlAckiP5xtIgyvMMpaEaDEQvq/I -TmkCuNy8ZMLbwyK+wU8YErCSWjAqpW4DBlZun6B7MzqCUufawlj+vINZrmxIRsVC -ExUEGENIZ1EIGqUJ7keGU1iKLr4pgGGgL3DS66YTaWbQ7/mdddPsj9NKVNM86sGn -DRt71wH8JBVc8WkcfGl+zxvSPaFnmbDUwArG/rzDjqWCsHwThmhA7A5kd53y/gtO -pBIWf+FghpzCZylZE9flPeIucuA96JyW7gzoGjRYA2wBNlDc9RFyPC6ttWsNQ1OI -U8LFcU9BNOR5VYsff1nxQmsSIXANIsiXN817XK/ZKXP+RXN6a4LPfcM4m9QDehsm -F6Fmrsev1bzkyPWLHD3X8e4rt/KybPN660YNtgQNwP6BJEw4zDgoO3o5R9rdDlF+ -nqmEWoEuf8TnKO0/LtzxtG4NWPrzeUw0rq/zC3lfxobuirUXc+c851nqaE4f7I7Z -N44lhZ5sm83hYT01X4jj5P3mHT/Hnf6YyDtLqwoNLOs+zldRJjURKyGYfVEuNQ84 -O71crQOhiMeYnQPehkTIgo9R462BhUst6Alga2CEAqrOuy0o7JWv1e8AGoHdx0/y -d2R7VdMYJb3oBdeQRFdDpJ0LSh7uh454J5vsmosuv691Xh2w2RvyvgfO328qPWM2 -UHcRH40W++a8D+BA3Oc6gJaPoaRn4k3PqNDzWozpW3+RU7sW3CYp9dWbzVuSOzqr -za3rr/fwlF4rJMQsDcsTObQCEMoWe1msqA+qo7M2MwXnetPXC8xSdMXyMPVyQKHX -E1fztXqcsqMaGfFOsa/rauZz8BUilQ1+ZpUjYRHixJgK5y5jdBH/fuiQ0u0ultsR -ILPiS/FBdEssnJzoLJVN2JbQSI9B87tTNDLK6MI6BkHwZ/e+su2mzyjOtTadhvQw -xsLpV8qxFe7ZsG+E2zyQ5lJckwEi3JF0Xp3dG+Y/rMNds827rHLWobzc5B7U93Yr -Ca9Xq7bXU4qmh9GP8ZQlBhNXNckt94QUtnUz7TGRUCNvviCZ9965NMg3gl+sX4er -iQ4Wqa3teBJ7vHdCiVrE0YnTWnYgsFVT6MXpV1nxrzyuob+gtZ0YMwJHnsiCB/pt -FxYg9gizyTfB7GdfmzKFGKRKhQp+tt9IImBQcLT1dqpCxXlyh74B2Np1fvRZJzRh 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-Jg50L8hq8TERElkU49A3/sDalCAZSEbgntzr7lK1fPWA8ExCh8AKB0atTHJnek2P -AZXDpQIrGrd1lJVgRYiHgrp3yIujBPRD61Gd9DW/L+225nxizLFVaL8sMBIHCSLo -/x0uIXxcemcqa/2H1HtKU6I6RKVGR6I0Ea2lA34DUZpwTv2tD7LGnvAsBC66achv -XHD4Um3v/SupNKbBIpIntamqCmhKqHE24tLBic/Bg342v6k1O7sJfcKcu0aA5d/9 -l0tMYFNWxITDk3P61f3Axq6RKoScTOGOpCrdMCNa9c6hLJCP1QSgmMGtoOXQzRCh -MtuaURsuVfwLDPIE17B7WY8kJ1lxcimJHY7w3B9P3zZjAB4uonCHzCfZCazQMIEE -C2/VLA7A4iYrHbcI8/YLKH0H99MI1sF5/kiGK0zs/TOTTKeLJJ9QwuY4I7h8P8KG -FN+kzKUNlIKknMNfrgGAI0ra2duOW+WMN4xSguCSYUI7qia1aE2ZlUnFU58qfoO4 -vwHRk198UmhUFCfspAws9eNn8qCpbkVOPRvKDiNovdRBhWRPw6U+LSEhh42s8wAl -eeCJoDY92MrXPorD7Ae6mXZGXOFjmMIeU76NppWpQu9WZtMfgprk25U11v3fvJbD -y+ohavLx1+lqVPTFEmK0zjo9eUfiUwuxtnbS+2FAgph/EgPGMYT5Lvn0CWsbTF6T -vBzn89iZaUDBVgZ0rhxRCc02t/PSbNgVd5Wv91l5nWU5rl98r3bh/MBKyVwq6bOq -foVjDI2z6/E8qR0KNuGyflvVabFjeGmHYxUHLm3GH8P3sHjD6AC7kFDjdmbzbWJU -hO2OQQIXSfjeJ5w1/fb357eKOmlOGorkjhAwbxbZauF/5ZFyfB0rfi61umUR2IMd -03C5K7JVYrUFOwdlx2QIpz1ROPpzcFdW73gRiZy/7Xa6yM42LBrKx3K2krYPinQW -SzHVSQENpIp9p4NF8IdpJyi+Ak4+B/w8bceQJ79sdtomZWjrtiotAdk9l5geyIBS -aiARZZhAOGeb1tlBuisE0D9WSf+hfbx9m4Va8XmMa2awQ8c4aysAwipfFcDSokqe -0J0+yjz8IhGvC0k1MlsS3nF1xSckBFtEQBqQ85d9zWBdDMBsQkUuvDXQ/PKSMecR -yKLLBNWEVLe4S/iTzc79SEax3Ik6HKFozawETA+OZqcVtGAhM8YoxFctxPYg+uXD -bWUzV/Ja54HXPNEv71aGMXmtC9Jzg50ObzU7njHdy8Q5cl+4h96sX3iC/8fgKxcV -GxAsVqirR7VXVxne0efzFNtQFcIOh9vPs9qHN5BCoYu4bXvSdijjCQqjD+8P/Wl6 -K+Qu9l6ESXl4mb5i6xb4F4fjZk+C7uKt8rM/bK1fOaxx2QMzf2f4GAZjfK2NoLKm -vDKNU5ihfZai9xIJqQ5FVUHoQzSQboee/ojE3neMGeVPRQgsBnf9v9E2c6TdK+Yd -fuQWTePp4XW9/zE9qWsKaYHLxj7oxKyPitOMktjgTaFDoXeX6DZxe4Od2r4fHKmV -rrtXLjB6FIwaByaXWefvP3McRSxMZARdgIc4NePBrPWDr3iKJtsHuVaXNYHsPcsn -xyyq2KT6isALcOYG1eAgyPtGBhaR+UCpAi7VZtjJD9tRZF2vwkjaDi5ryJ8L+oCn -b/7J52bKD7OwKJQ9m6Y7q8+KVhpkSUPcSDnvBOKosIX+lEN9SnKm1Zjw1xYPPDZT -b469Q5d11Q6yIYhLat+5d5x1MXe0CnM6qDTqj7odIgN82HfiWakPiijx4FVOpwhE -nU0HPm8huYJ6tKVHXcr0w27BViaPS4liZIWKe/zyOUI0sOXIQ8ycX55jXS1X9JQK -EcH41tzIcqRMZZrUqZMgihUivPdTtXZRaKnaRozuPyo= -//pragma protect end_data_block -//pragma protect digest_block -NoNN/+HOL/6XnNdLy3d9uw2O3HQ= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AbCzhd0qNN1a3YD2COxnxD9tA4+Q8AthzDbzjUhGr06Te3TXX9nYsgo3lUXkiQvh -TCqgcIyaHSmj7N4taHx2OHQM65fqZ9Kxlkmcs4uwd5L5keLAE/xHBK+oOX+mAu0n -wi9qZnDk2POmSmxaLIinPJJLXmbOu1tKcNUqryv6jGSZqxHFGYNuIrCWEPHGhH8z -ScFwZj1MH7MLTBso3FGbgqoMfAGglrHtPPIRqQToZJ5UyrJ5OnliZvjjHUct4lAt -oxuezsQeVftgh7ARe0q/34Uw5IB+tFu0T648sWtQrbOuK2lirrsT70RyQVaFNJOB -afEEkSjZUwZJ8Gim6nx7fA== -//pragma protect end_key_block -//pragma protect digest_block -ANmuh8+Z/fi0NpDa8f8OOgJt3vE= -//pragma protect end_digest_block -//pragma protect data_block -W6sMrQihbaMdI2RPKLIUTNwA3Gc4uUMkomlzSKCIsSnwjupA8mz6SVNbXWxoov96 -Wq6a1C1N/Dm3topALugkZTReuwtDwAKkfPoY/lqmvwI/ZbudZA8SPZ7O5w7UAHMe -sOgMxf79xE5rvAq4xKQnAM0VLBqegLEUtz66mw4srVKttRDNIhNDpaJ47ApsJxY0 -SQs98wsAI8U9feEarxvg8T1zgq5eiO9dPIa8j8lwI9bOmA1ZkuwQZ9L1UPTfDf1A -c15Aqge5ZRwClqgCuP4LrrtlPbdba15wIXIM4SrZmkT8Ymb3H6prJJvzW+LFOfTt -7JuJ4TTuwrO0F81xm25CnwSiYvzR4UeaGwMfhjU0wBKcBOD0B4XYxUVOVpqw8CnX -w7Pf4LLrSwmUMgRCHfTe2wSRUlT8/W5lGXCCKzTIeFc7e66Tv5F0dVQoTezOretn -IdrxIs+FluvZltCHWNK7wTsCYe5ZF+E1BYE6+PPZrnsEJXa9SeeWq0cssknmR14T -miF2IVo5HoRSlCrEwRGMa+oK8DVIE0ohMX/7YORCTp3m8Hco5S8vFq26NBv/w2m/ -asV+1/y7N6Suk/PnG2VEwnjlliJf0CZTkY1Cgovfm6yzc1diAXGMxKdb0HTlPcKH -U+4yv2lrROslwGbgT99x7R0pecjwY5Z8v8jUn2xowXnuH5mtNAUIsWsT63+/l2wY -hzujAJnunUhPzEpiSPMlgxcCnQnZy33MXUf1ZtkooAtEfZt98i26L7QcAjDZx0/F -hQW3sMRyKlPh04dpEHWKW+lsYwXVPVIou0TbEVwnQ1rdhJH3aq9pHXc2TVBpLjjy -zZQg6ett6jU87uoffZXg0TRVVGGMH1KprdoGZR3XRg/L30ED5H5nBQ7l4Yuf/7eS -bXYec6xDUGxLDKG87iSacHYFC4hsTd2HRDggVPwAwItZCP2hsO5nrYWIgod/3ZnY -OY0gaLqbF4/fZNKr6KQUVDTP1VP1iaiFVYLNDHZ3Jw1taicnfUkIgpuOcieXHL19 -1FQi7ljYZDHDLBdg/UpR50JWsGPSXrFFCyBAZdqu+Gl+doYXRD2QWqCbrHr4YFce -v0DtSjB9EUvQXQaUfj0zBpFBnmQ3alpUu3TttlGuRRwfNtnf71DclD1tqwPVF6Ii -Y+ovFZTAl6984V5t6Q9ioZWc/Ru9tB2K+Cl5/pkSCq54UMVJnYVM+aa6P3Ssb7dx -45lGpqjNKrfQ89TN9eqo63jDAKCwGFiuPQoUxDunlJpXonbZVy/UhbdtMqIW5ESI -33D0BeXiqgHE+KCNft8aBJFM3tQ8/ZoN4MzD6ZCHOuurrxsGUz0aS1SongSJFfQX -0GBsRwhzaoEgkVqAhNEkLJHG45LSLUlklYLeD5c4KWZKSYtggqLk5g+TlK72akQV -eZe/gvQQJsNIVq0A5fQoOWXoRXmKYtBSfd9VlXxbImc+Mm6OAHDk2LsYG0qNJ6hp -hPM/c2+wML7iK0uLJX6T28Gyw4dvKYEJT2pJn/RlVlggOV4vcO4VDaRLu2VPO6DY -1ne5XtWtqEEmQo6qcjo+hNHKPaLmZeuiHLLfSi0p9BKd1E5PwRejhCDp2Tl/ohut -pGAxleOWkKh3F1p5lB5/oRievr0g3KiIskFHL2CxJvG2olL3OBmeL4x/QxELGj8N -m+1cKH3PsPsIbCPjDFFVLC6dEYQQ4bnY24/o5IBwxJDUm+gaiMRVX+JaSE54DqM4 -VkEMQ8d+RTEcVlORJOYYRs7bNdH6s4bIz3rtH9cZHHRIBQAQzhe5nTtWWMr01dXw -neNWPmRn4tTkXzQYmqazhY0JBUBQyyIUNoR09Wg/kkXaKaNPCxzzpoa4c5swx3Ct -WbWpkOf8uqehUOTyZ5jnccJItbhFwhV2SnbVK5RMEn0= -//pragma protect end_data_block -//pragma protect digest_block -d1Onj9prOJmn4JcwcCCC8cvvcYw= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AsnvdlQQG2G/k9b5qztkkW7Dv+FAZiPWR6QAUQ+DxyO86/iCpkBlRR6oSVI7Og+p -9CtGpeXkbt4RrFe90nWZGjqvKgB7RxmhXppMUa7bi5yTGg6r1eOI3gAVzAd0YjMy -25rpc2ixPCo14GQPh++XOQ9s40V4LBII16ArZidT3TUwXSob65RLazB/eIV/sUNy -5eBEKR7/xyx/F+evqlp6SnUvcfFe0SuOopPUCAACMa/w2N6o2t6qUgzpnKjvfpyy -aL6wquWnMYxt1ZWghTs3ESImUnkDXkLHeOrJnpqOt4oal8yNil8aDRGPYogUCq9v -nwUaPfDpVSeVWP85S9g4tg== -//pragma protect end_key_block -//pragma protect digest_block -I+eFsI6owEDO8y+cCD4HefhLDZ4= -//pragma protect end_digest_block -//pragma protect data_block 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-07mY83sEn8MJQ2MLPA51TqtF8Qa2WAW85uU9TzEb27BcHBqVmy0IIagRYFvaYALZ -OUS32h7eNSdz/JL4YcfJHnZLFPey/gmE4FZxp/rp5m7cH6EomSSMlCDsa9jScPNu -lBNpniQJEPVCI5Hn0Jd+/VtWI/hmvLWT666cn2qcbrQFVBQM+/GadWrcuWS5t01F -yJkoi4ca90KnhiB0t7aYxgEP+oa9HLvBI/EDhDuuG9/IuQwepv1Dv/JR5B14fQkx -adMkZa+ZyaHu7nnfmntOInxAbhAjJVph+vrIAL4jUjwh2bSHv9TRasmQmf7aGmzM -XUs4qRgQEmiqdfqZKn1vfsN17SbMKj3OWyS91LGY5o3P/MKI0NvriJUjC8iSjf68 -Uq5vfQIin8TvpIvRlF1pqPNvsTm+fCwZdUdLNbGOJNekcI8hTuRVzObHhqL+exYJ -XODGB/KZNdfnuDynK8WBJZdjj5g+DEBK8R2Lek1WhMiTT761Huz/UY7DZrd8CJ8e -7kqagJ7fHHGZA7m3+uGKCKxN1TM7hFxduZGwfmZikT6GaXdB3zbiLyG3dqpSEEbz -Ru8JPMPEBfAFft/sJFb1956DCpwbuMprRu3Puw69b7sRqOBIwYsCz4OQYVbVdzzX -J6kZYd+yoGQ/7Avxfc28dymd9PC25v7l5+oQHJMTvv8cjncI4mYBXuD6yPn4u0AL -Jln3muh6n766T6bMjhuhm7QBJeFlziBT4B8zvPSS7ms= -//pragma protect end_data_block -//pragma protect digest_block -D7e/03/mF2BL9YuHkWwHU2Ux1m4= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -Abb/aU6vd4NK5iXNnimYoWO7UYIoJonmB0a4Z6SFd+HXx2lY6uqbs9SGpllvwPAM -Wb5IV0DhyUtyh2WTfgW93UdYA6et2F4f4KFsV1HrIgx6YyTvefxkddDkXJ2Hdt0i -DVY7dOwl8pi5G0G/iVLsg++KpwuRAqFdKMIQM5kdDn7yvb9J4fwdXXBHtykep1+4 -RrEaIf+oTgqDzfalR4V1G1WlQz+6HOac8ohOpYDiASBMMrbEZBkNnw4F58YLsweu -ZFwlILhLIQ0p8ZXVNlvdC4j03Ir8B5UguySAxZby07M2EMi0wFLqi4PD493fVPKz -iiVHouTBWJlaPEyX51xzQA== -//pragma protect end_key_block -//pragma protect digest_block -pWD285A16E48GpWKY9w7PswvVQg= -//pragma protect end_digest_block -//pragma protect data_block -tbC5phADw5ibrgILsA6yzkwnDfSWH7zOwDaZ6EJLfQPfvj6SJKAsCZsnB8f+/eYy -BwY6m/LYrNnACYKG6hTiObSY7+2IbqvbKrMZEv/NTlurYmDf6wV4btaadDLl2Wku -DjsdRKs81nn+P+CBiZVD4F8xIQkNUrTc2xI1d5L4zU9Cnu7I+rjGFEpouCpYtGmX -jJ0uopKZuO0ExRMmp2vxEcIGZVNNyMaImeQLr2JnwndvCBc0kdw9ypFJJYm0aYRw -Y3z7cuiWTggHwEWRujz0SXODHjOKLkczh2lqilWtfhOGyrlFOHU18uwQmvRL8ahn -8RaOiaPf5AJcvUHsJGt95vw7srGMaALs2qDqHGIZA6Cehv5J1pLFZQXAjt9E5yCC -xipoPwtYKbHTxaw7zbLW6HIisW2pA36/TFQ4L0H7Br5dUtOryXWYAE0dzzBANUKe -r/RzjWLmwWAkWuZVt14lDDPAMROxEP0aRpBK/LXQX1VnoEkXqHe4jswYkN3ncgOP -51pYAY71krd12pCBs2aDChpu431mMgzGUjot3JuJ97sBXuOFl+OidSBb6iEqRvmq -xY73FBBZh4WWkm+nbmTmLuIjVpcQbUYHq5FOD108SZz/YLNSCDHPdoRIqp0ZQxJh -pJFOotWNf6alEPIRX3bJxEnjALGM3NtDQBVCiy39JQe4GPdYkxSB45ekPx8+VhFa -7uB3qovPPyhvkqsDBHCzRwtbir3KmH+ph1su951iTPRaos7Ge4zkEtoX030q1a30 -FEiX/MwWjeUxzmNPmsArzKTA/doH5NXOLigVq1odhmSjCiDbitQTAikvGJ5PLXjj -LtSzeZVF9mtAGP3Epny8gEShJuQUruPLOtDqzW9B5EElhu4ltE2cG9SsZ5gc0XTV -8H/46JhLYNxJXluUPa995tvqstk3BHCQiPkro4zbJZJPIEB/pioEBL7IR+hnVkFa -Wf0zI7LYVMK8n66wM54iLK9ve0MGLx5LUat2xkM4WfnsO+vxrL0o8Xy5H8jsDmuu -Ev/D3mFU1pjpnBNEMRu4FUXhHmCh5dXykeBG48H2n8V8hD5hGdPNKANVZqgL7Nm2 -lWgEekSBB4bDfkycUge9xBvyHeI6OK45jYKf552/wdMIZuCiYS8+laUi+IrCgfVp -gLoY6Jq8BInh0sQaPFHASxdXuR6vwBdrQ793lTBGHIsP5d75zTOYvoVmUjowoTX4 -pX9+5A+vcIIHAmq7Y0sKjZGs9f+YhI4xxID7iH+tect9C32aY3rsOuiPIsIF9cwq -/hcRBENALP6VK0QRLI/L13yLiFfYP5GzwW0w5m0BX4/pBReCyfW0B8BtU8H+ki3h -AXxANnbC2F5eJbRFWe3QF0uqn3Y8HfD+3/OUy0XVARPn2QlCNQBQnLT2dHeMoHe3 -zfs+X0YJhaefWi0UXSXmzjdhn5uvQR2t4tpDviDgOMaFVIX7lFkij/p9JBuswcf7 -JJPHyDSOmRAci+FPHX3rw0liWnJic3SFyx27saxlTMlDjxuXz6RUsxgmykgwXS2q -XFj4Y2qmKi1HjNu+sr23zKFzu9C7qPcxpt3EdjI6BnG2Ks2guYXv0Gwqr+mpQ5E1 -RgU45UCjhWK/9Zo3CeoXJjHyG0/5SufH155/hmltrpf/eInxz0oQ1ghwwgrvjTqZ -5as7CqOk+T6BTdOiBn3NzcQQHF/TuhOXs1b9OdVUritY6nA56Dh5UuG90Nc65Gef -/B4vwieJ4p0Uor8JrUVt8TBeILazBlM5NzzQDIXV1Mmuiz8Wbhg24RM+P7hlxqNx -irbPIimPdX1PuX9dirAkq6SRbdNScE6mDvzvIQWIfxaPvwH2f2nhI4YuFsNROpoY -PBZAbdyAyBVwthKpmLDcY4OkiehCDWrxPlH7vq8PdqAYcmLUtgijiGvssqDog5db -gIsMuzTnV93QKwuGrFXn+zV9EOc11MMBEIcm57sqylRCYxY7ytpjP7p0hp9FVXdD -zGWiihTEdQQVKICmGUezqF0zVzAxNYqdaGkO0hXYGAt1Fx4EilEI233Tk9XUG/PL -Id3vdrlXCfiq4SGMYR6er30QbQANt/VMjMcz+QO4rf8K1P0lCVe7PGun8/z4o7YP -m+oSy5M+46ZGvsILKRXhQXsFkZtTB33r0MoGjXsj9BWG9YrTDyEy45XqS+iSfie3 -KQmvIe+/XPLLyXAhxhxQxluCM8wr9hi/tWQF2N59lRkx/C15Ys3acNvcYHfrgTQB -WdKVG6Bn+o07TQaYEInbJ3MEonMG7mbn1MAVLdsaYuLrwtjc7gFqIGsto2CqXZkG -qmlooCBVplz3ZwCY6gTzGRNKu07UtAClI6P7Dm6Ctdk9G4AfJP05aAx4va1C2jVv -ua+Klymxl/Mws++p7tsE5wNBLg8/9hKw+SVprSFgwHLR5wKwjVVm3A+QyfsOEwDr -q92mjPKmbNTHIeqlsV28oZtZClh0uexmXprF0vOw8euL4FSjxd6nTpBSxJmK7C7t -bNiFNYTd5YMPQxYRgQ4uoaTmr7JMSgnbfqLAYF7Sl9OmW9pB5ieexe0HWyWI+c50 -QLvSKkbMbxPjq5/TDNvSAAfrxnSMwcQTyX7MJeJvRUQ= -//pragma protect end_data_block -//pragma protect digest_block -q8FQ8IPkH9SC749Sk1McZpJf12E= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AuMoHPX8Pd3mqbQO1GA1lDwNRW4jVDSCCnolu3a6qpNdY5kHzBOGmD+lMc+C6ham -DMiMRT9V4xdB/+OwhRUdvnDdS8ZdNEzgQ16Gp2C+bb8C8fxGtMhNxkoUVWf587Kn -BgG/gBlTbJeO63zuzFdgGYvAyJ2VnKYt5wWMlOEkPu9ltYfcrLIG3R13kjyTD1Ci -XIHkBgGaddrqRpVONdrM+FKVtXZ57ZAqBgLbG6DP1TCMKkiChSMPG8h480WRmgKc -dQ0b22rh00a8vsr/qVARmzjRyOJSx4rgZOEhGRcQ8evgL7SOZxu3JXy3m0oErgqT -QVYOONJeCKkvOy9Jgs+EaQ== -//pragma protect end_key_block -//pragma protect digest_block -8qSCHJneLBb6XVLZi9bJi6+NcUw= -//pragma protect end_digest_block -//pragma protect data_block -mjUZOoJM2MxBaXTtENbAKMWZ9cufVZblhfcbSkDa7OaUetrwGVOBa+POnkO7nBlb -t4K/wQkA+RF7Rhk2fuAx5SfklhKO9JKLYqP6gq+X8LkxlcTF7uuL0jeQWJF0OCyp -Zjh+SCwSUz33Y9NeU8tYfOVaNE6eJIWcV2gdFIkISSQzLem3h+G3LL/IXZZ85/HS -dBsLSIqz3Xj5h4+aAzn60yoeeTXLFw5cpcYHXeOjazyGPRwBFvMXntIwwgyZtUf2 -TgtGZUKJicZOcgx+INVrAWh7UykCu8GgEhP3gHz2FFWDaykgozYa+BdWlHYVZRnd -u4HttmarkcM1hDmIrDkN0xeI0R3B3cOYK93O+SfFZRjgPgWSgfe0Dniw4rFvSb/6 -xfLwV2p8Tb6WjH43i5+zp5RLfqwh4GhPqUKiWdj/NRP+2jZI6DfnXdKpUtPqCD4Y -ie+t/1dmyPeAnHThwKsqhOjxXY3ektJOkC8tEfQQ+xQGqS6V2Yw98zDIGCBqR5tm -ykkfpn2EOiqZAF21pDpQNWKAbKFV4COTE244UTVwVRP8PvLm7MigAvstvPfogjle -pgwyeO54yhhf/t+I+dh7Ol2PbPIIKq6queTfDFK7iFP94L12lgHAdUAl+HE5fzlP -wFK0iM7gVC5Rpg4rP+y0e9vCX5DU3W7w5J0QRMnwnWPg+KQ8YczK3/W/spBaHZOB -kN4ZVGB0LvCTPyaJzGr5LoFnA+cYlUsazBidM8Xy3/br/sI2BprOeT0Bbq0pgZ+7 -ZozDzNd7LZtVNGBHU0z30YjaArVNIbrxjGvrM1rMBiXMKMkBKnAK6OPDz/Cv81Bu -sr4T3WjutY+QUyn6JJb4WBh0C52rGPWkmApEmDrViAoBfIikmr6NOZWjoX7lTUBX -ktMH4cCtEGL7kpJrtSal2lBI75l7dQugTNXInwxuckce7Xe+OEzvP2MmloJy0O6M -BdQew09sZNR7qH+pATwkTgOxzR8WD2uFJ4xRG2JXMCeQmOJ8GqVLNtWCRBTZu/w7 -Ei4QQiFUDii1+M0vuTqWGWd0nI1+TjsqB02FbH4wfCUh3GJEtaAnXJsLa0bsSqPG -F91Q0P7JKG94GRUCaZzWaY4l5rmgTOHdsKIDkMrO8ZomgqxIW8/PyrdVufecyuhS -tagF7wdMRFl4N0wj9U7nvS1ap9/Y0druycAD0giFMZqvPMj2TdOcei4WJsgBt97T -qGgspa5rTqVlzARrLSgFLTUyF633pj+0Bb12EWQPX7oDj5k5kS/SzW0ZKNpLV8ty -Hox7DDoQu006ZqZZdY26fxlSh7aRj2b2bF1aToC7GjcA1lbdsOtyQqz1zTn8Idvk -Y423RWAAXMfO+FUTbExd30pDrp2EVJL0xSS/Od0v4F0yjNS3nd9e8JMxF6bZyrwp -lPmapxq0TNxCxs5DcQje6xpbdGTE9tGTevyk7YhE2jmVBQoBNS8ollR1cChJnMX2 -A3wgJSwc1/R7mArGuO4d6V4WyrVjy1ay3Dn587sRxBoIEyYfQtbvw4Hp57EGMTmB -z3Wedc32RaQ/gYdi8W5ALb7e3ZugnCImvKAO9Zys41rR80jfZgDibRRE7R7eWBpx -Dca/tfPT/nm0kmLMrr+QLFj6NG+W46M/9s+RUPVjXmRQWYWn3DoL/urWcc4dA5ED -ZSW7QYb19DJ6uG9QHoeMzbPTheO3qpk3upfbp54jnvKXkTiEN8i2NN6WpJcByXVT -eYWrCmNsPKij4RylgCrk9+TnrF+SmUV1Qdg4qRveSj3oRXo9hVjlyJWbHhwdDhWh -aEdl+0aCT2cjFTiR8yeqW+vuoKioYN9qh8TLLuAdGLgmZtq9WxsyGkPKOtspDUMq -EWydQ0p+4RzUAulPvbwIKb0sGggpPGngkt6TyLp83Cs516Y40mH6DSaTl71MfUPN -6hVNGmJHFYj3tTvj0TQ5Yn6LDKZIFMYthZGHop+ROh+IEXUubzHm7a3cDCtqkTyE -b03LsJC6CbMnKI4XGecMXYfQw9IYR+L/5ks46VSRiptymUrTtRogrHb4JM3vMykV -eiowloo3C+iXYPHohrH0mtLiiPc6R58vOFVfL8nYoib2JO6D8+6Xy2g7xxq3mJAV -yqdbRTu0VObw/j4oDm3QhDtedNtGn5zFi6EsNsnD8Mo610kERxQ5JWUQ9pFn+Q8C -z25QzeOUO0xcG5p73pWvx/iYAmLe1udtKsweXltd/jqfrnxSd82xNUv+VYdzwn84 -OelM0vLrTklkXPc4+OoI/t0vlN9HTKz71v9vN46rliiLEjWEK4q1O2f4rlqbyB5j -y2+8e26HbD3xg3kmwDYHKnBdp6BHGoal9KnDxzTz/eu9LNHlwf5zjck8iA3+97jz -HHwOnEGLRkzAUM3vr5Rh9YHCl4LPYSLVC1p3wLPAjbS6kIN2SxaHQmW2+qkCyeBK -ayJOmojJZvd2ytxxil979lOGyGnqssMnSOVD5y/xarNrTxcWneOD5zLaidEWVIeN -hcQwoNqbl9ou6rUMlFYsbbC1Sodw7eSpKhoIcISyqvzudaCOPOvydwvaKECE2AO8 -kcNmqRNarkBd6EztjGGGjpo/VKwuSjjKmTTVG6UosMIu98rT8GMpN0XPDQLZcGUM -SZhPY7MvdYR+5IytmxaxPpwNtw2pXjPzyu+txd6Hc3qgeJJi+7qWWOwTGPbxgu2j -5gKuah3rKsqgRqDyspNjnaf4Jur338xZJSy4ei+FfF4Bzn4NEO1x/+SarhFS+Qi8 -8oci+qlUaAtPSUXwZ4W5uUVK6B4XAOf3Q8jfxQHQXZS3FBSTUCAe9TzAE1mv+gdq -DBDftqQtX/oHWfAmeZhmRBuj7LdF4fVNcnOSlb9RYYo= -//pragma protect end_data_block -//pragma protect digest_block -fISjrQLVTMznoejKTXLxneEH1rM= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -Alh+zpnsJ6NtMNwzGSTrfbMl+vFsUFiQe7E8ZGxfpOO4gXH+R8hi3eZ5VwT90lvV -JhwMoeTUKOhlOXbWgCgWxu2KaM6oRZagJxI/qLkZbLXOlM24Altu2z3sJT7Ymbi7 -SifwsoPrd55gSeSnwTmdwAU/3m/+fyVWBK9zo5tri2VJTLDpm2DCcT+5aerLXXPg -ScpwP3go0xQ69IrJdZ9wx9Z2Qb+mbafejlACthfrI/qHqz0+KfF7JU3xnktro9EK -H7agWTVWTyfwEes3oAnLjcgrxQtygl2JcZ384L7W2ohbVxq0M6xNdZ4dc5E1Jd/8 -wWwZ5PjU8hN3vfbePgjZkA== -//pragma protect end_key_block -//pragma protect digest_block -TtmbDmxdMg1zJG/PERb8Ra+Pms8= -//pragma protect end_digest_block -//pragma protect data_block -k+n69WuR4H8EJmfWtnuPsWo8FraZu4DfWYL2PY5YqjsXpkNVPDjqEZdDsG3SqNTN -2S1NZ870LhHCGvBBARLdJA1VLkqWryMAuNBirOylR5IF0321LM6vzQn3Wi9TWmfc -bFEeI3OJeikRfzPkLvH1aLGNjqWEAnQ0M4hS1oMTed7NQFZDLfd7E2MjGMUZPShr -UBv40r3fj+D8GVgPsHkbOLPmp/3nKpGql0CUOocKPoyICPDj7IGwrwNd7oeuDA7v -zQCcZm5LS0THPD2SIa2ass1gWjm7tCNlrh2k4IYRm32YFovPvXQFRgfOvgTxg6JQ -77hKZwhD2x19eRMm0+HXZxjrBXEMKB8rFJNVPC9dWtETwHUJab3lzrXCr4Fgwzgk -jFcwTSIvH0RVVw3fj/cJvUCBX6hCjRqrch6UmteqvuJ6IFGi7aekfL+T8v3Ws2iu -aCQwxfCXMtw30H3obauMB9I/w4hjSFGSCD4u5FH2F1Mqpn0uC6Kk+iRMRPCWbiTm -dxJoJvLlTTUkT1iZj/gOhjRowBboxZlGAEh2is5t9ed8icK6cJuniTKdCndoSnri -9MBhURyF1lipG+3/530Hc5udwnTKXQFlaVzeuPme6+yy3PFkD5Sx2Xjf9qjF8kDx -pwz7GB8IUaRwNK0rkoIk6Jtcx2/xrtxmzsRVkFIsd044rIKyMHdc2YV+1qAzjaVK -miG89UzKseUjt/58f6GBRjHUTbNzeMYrJvqbI++ridb1nwEPo+Yh/0GLq7ykgk5o -x3NpQqxg2FOEIT2wQKDCyJrS9SyYNcDqLSnzTxewDbm77l2WlUE+X7xKaa5RMs06 -dcXJR8GLKF1fDzMdBOj/mUmJBOEtkUSWWhBL7yuGja4BgSdDzMxXvQf9UW+j6ERe -JIPco270nVyQCHrhCkINoj0OPa3rbtmMZxjN3UnloY0wXt6F+vxKcaveXUKsu20R -xzJ9Fk7NiL4xws9qG9B1dJShV9stkYdqRjRM1q4Mjx6zO4dE3IXEovLi3EZTGfH9 -m/PQwWGTXz/14BXn78imWB7C5/rjP3eG3Az4YF8CkB/oYO1bmoG7JOYGT44nuhG0 -hHDN0ZLDnY9cXqdENEuqvfe1SJn1yNIa2QBiIfPwWZ/mpjlMinq04ZS/QWv+F4YP -GADlxVl3fEa/D7UV9PZ733h2MGvM813eA+6dP+7nQ6izER+aqnxXVSR6108m9Fhh -Qlw5p2O5H2uzgB5FMAIflWj7J8eZKu2W28EllU+YNwvoN3mlYNmxBToH2cj1XgQp -btS2r6Xj/F0UXqGwkjO23ySxQ05FwmWPmPRe17S0vfb/tX/q7BagnZH70jjtvKtC -sfF7mVTEWER3JP0QX5QNBej4MsNBRjBd7mkxhuvV28p00rLc/I8rs84VgVPtRRRN -nLJqPgqXxWdZqA1cGh5PjX1oqI2/mfHaePtCCQ/wAXOmnkUCOu0APDCIpVtHvZkI -b9TzbKp2iL3FyLl+enDkH8LoIIBxlF3M8IiKNj2HvTjMGZFYqenhTYoSv36LdtvF -ltyEQMfmJDDgb/QEn0tc+FY2rl04em2Nq/cCjuFc0lgO0zCObt6PnIAPas7Pgfn/ -2+Sk3ypPrp6C8vesKbDAUydYzSN/6veQ43B2srBEX0KyPDHX+1Zh7xxHiY1XdXQv -luUl3pbLoq8CDzpIqLs/KnLFWDqpN732dEXe0gnrx3ZPgalnL4o0y+8kUpj0XRMp -tVxHQqGwuU0K+aqMcZHWORJwolnNtwyjmmFi6HGcbq7WlMaryZxJgSVGqG2dfn/W -CRazQU8VPjZao0tcu3PWMKwVZo9lkCvv3gXksbWFoR2Ql1GTv+ZPTmw/xypk6dhG -kOeDd6N04JrlfkPnM4yh3INLmxUDLAeJepsZdYLCskwLqW0VUtpenQ6kObflHJSH -8zJZNOkiiYrYhxOATiRMxxYJR/tjenOebx7jvKJ3SZ0VwRobUsXbaB5JtVeSLR7A -GOXHVR+DRtrcevCsezaYMmA8lajykBiIvbyU5Oqw+MsmaUxGfacjBcYVtM8P5502 -HWRl1s6zySX0awWWKtAG0cJ/vw/8fJyqOrTXAxPLqG0gKhjjLiAzewbmehoygDXE -mfMm24jUzVvRPm3QpQXRdhUaZdNvwYaLhX+Wm+Onbo3Aq7okNDq8zfBIsuCMN4Mw -1ZshNtS9QWHvWdJoUUEbOPo5YyU0drWX/mS8vkq8uTYfyu/fIWw+rnEfT48iv7p3 -imY1H+2cuaqwEHqslEkhKv2Z3dLI1hO1YJtJFGLYpP8ddFU7CPRu5U9t0MHD1WAf -Gq22GHJFJXt1YXWxgAnZiTLKNgIB1NEtzR1JC6YOMi8Z3rQuasl5FtVGxQ7mjpWi -ZqniCdVTIFgRAU4U2C8YLbW3q1UtBXgzPDsaAYl2lfVpy0DkxyUt2MKuQXcIOsL8 -BWUIHVG8ElfLBQWKzx7sly9V+O3ud0WcgnmXbt2AihDescA3xeGYtFiLLLRMv3j0 -2ya3EGX2R0hDeN9THnTLBGoBvc66vCnwM/PEFJsEsUDYLHBBFRP+KWfJxVtk6nSk -GWa0XA85vqK/MohEtiDg9c6G3uHVWwk5EtN8XBnQJt7l3Wn01FPeonDnz+v4jB4A -sPAL/UUV5RC3g1v3kvjYNEB6vMoTy1/ngzvRpeO0KxeoUshPExPLcp7m8hakQP/2 -ZaMZ2EfnqXVTw9RVTa0VYvY501PDLvJX9HGF/IeDpo3zgloNBBlYazbKsBPdGY+t -iumUOdyMEEWizwEslLqNp2K9GKkZpR2sukxCRUdAQwG/y3SebZVwDU0CBwnJSOmx -DXle5Z+JwkuORjN8rlC+SOowLJM3SWAb6/UlQbj77DMdbv/uCN7QnipP7khrcTKk -fa7CiQIaz60uq27MECrP8AhwO6tfecCloHvmz4L5ys5W+Y5RDQVYOd74J/Jm9pTH -97fEhrJS8s/thV8H95E26kcNUTq0mdRrpG8XN3yIzkWgmD3Nhl8LsqRCvxf2xqYM -pcam8WaqfVSaDZh4uRdj0q6no7WnGAz3J64NcGAqKJKlIA1RK03GBLH4wnS7Msy/ -Xw9eQUc3V5cqL/qv4naKd80+m8GLxlvzh+NUJYzNETs6f99BaWGsoIaWX5fJzG2k -igEdeEMCOivBYJei6tsn39IvHGzU3u9me6I2/Qxnk8cwiIUrdLVnrcKSgagUSfRc -hFOgMejL1W4G2vfgvQ3E6jJ1Gw7/GpUM9BTQwgOS+xgLicT5e9qZjwyDmBtARtDu -YXy9CBo1iVhlcW4U9C67bbBLJkY87ruw4vtIpDCnnVguGP8hfD7CQIMzY/x/3BiT -noB5VtC5pCS3sc9Kw+KjrhOKirM5rgqra8zQG2uXJOpqLWJb928CrkMBmSqvpAmP -HXwztnlmJ1j24kGYS4eMQqq7H8Y2mTB9UInwMwkLgUUvJNeEFIiQoIh7DGnm0WUf -yehkk1ElESPD7idNa0WYSM14QEBhnsSIlYRDx7WLkPJdhiXR0/pPftNS1d8M8sm+ -sk7FazVQEW2aJovwsGYvxEvifNXdLZOPIwTWeMMVRoewTnOmfFGup2RRdifqo3BF -B1My3eFaaTpYg8j54SPjUrbhwQH7SWpKHPUSBb7t8zUplKEKXDOBCuC4mXCC+5Qv -GwJl8wljjwbCdNHrAvQTerZYmjlLuDND3uaU8xqbqKBT0zkWlx7zMApJYisgL9a5 -gvr3wqZj7IbSdZL49oLWQtawz6y9+vPchronN9xhEhgf6oo4N9CXE00eylTzdqFW -hZ4UsVFT9Qbm1/aUmSsHuRHq7NQCP8O44kdDGvCoXO4HhX0qMcRBJ1RdSdfL2GDV -DQR66hnhj5sr3fniKtsFFcXsW/wQ0McEfMPzmbaayvk869DgAGM/HhqN1lCpUdkz -//pragma protect end_data_block -//pragma protect digest_block -Dp33pnOzrjzNeFbe/SSVyHl2kAc= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -ADDkpHBcv1QLYI/vnbFUVBLH/vblpSm2j60Iblf8+01HHOD98Yh22bALNGILAwKs -9gQVwKC2DPK94E95kFvX/0oIAboT2fXoRjUne3mjg9Bgg6srz/UjPaq9my7Gxlp3 -mZIJKplYwCFZQ/vV7OFM4LSihaRrcdzBCKY0fkk37axv3XVjuxXw08yClc1SWhob -1iNAzAl1o5YyjeSrMGjox8D3NalxWvLqTkgGJuZ/oRxlAi+t/rk9+Nec8ZCp8IrH -6lbK/r2RCMcJ0tI9SuPpOoahoEYRf7IdN6CLyP7Hoi4pDgDXpmj98vs8cRlUhfr4 -46L2gqFzbwedeQRHmEcDRA== -//pragma protect end_key_block -//pragma protect digest_block -XyTDHV4JZRt+wfV76/WwR7YhVcs= -//pragma protect end_digest_block -//pragma protect data_block -DIQpi5vonwJyBJ2D80G4WZHECvG9vVq/YknlVDO8yLOu/v7EJwCXVnV4CEJbRkoB -G7S7Y436+diYcvbpp5NUVgk59k5vS6NOImBWwi4fMek6uCj6JTlUKCGDP5RNNHNS -qPONRBmo+Bx2tputtqQfkO7Q5xca7SMR3I5WlRRonRrViYfnSG2r7rniJNV/aBdg -N2GulZPlIvJBQt1lXjb5WZzqfiZrnc4yIUGXAGaguf02UjuDF7/TV/RRnJA5fm0+ -3HYsjIuBo7Uv8pTHyFUu6+8LHxlfAR3k9o1dYX3XTEydMb0oz6zOvRbMdcn7NvOJ -TyLV6VXSi+GcjGsJXUUXJ8Io/Y6h0AXGV+t/6ozhr7c5PVsZzsvt/w0HF5pBZZOj -k88mhEgsyspl5UmgMl00+KUbOVIC5kZdilv9zYH/9iQmMv5mN5qR8WTWSlEtm7AZ -pNCYtsV1VVVuzqMAZ+eF8WwoW/dI+6F5Drs/8Lnl1Ap6LLmyWPQ5HO637iZvUjKb -oKpdb8RW+BjQx7mnzacRZhFKMCIoLaTTslxBgOfIX6GT62uidjK4vxxPKwryagFJ -OoWabemNWjoZw7UPheLqy1s5505fXN8ELI0n0jYzi4CfgKFlu5UtdAQrY6X0YgAQ -khyA3SeGhS64IfJw3f+nPzOihEaD9ho8VlYOTS8WjdB9esCQonaeaoGOnKt6ICUG -UMX70VlZVDpgunO64cnXSqiiYkCIwnUsBc9btS8cUfoBr+YvVvzHgXz6FEqll+bW -31SzQ1Cdh9WOkQpnSNy/N8yw/s1obp+NcrTzhVm12aqIWPCrBSpR8Wxh8H8FXSEa -yIlYGziTTrfJnhqXQ4YNQzvKHFny86swxUONRWzRrYweU8NOdIZANgYsM7dpoepA -MhV9Y7DiwAgl1CpUOYdtHfTYPMCiwoIXkpWPDoNF+DREKxnnd0Rm2K1JR4S70z80 -mGQJdZMeXz2GIUzlKuqlWQSwYMAN7ONM+R6/7BlxP47NScyDixqzivQ/+vSJevWL -/r4860aUrhzuX2GWqR8/FuPT24B/GshIEDAyg4FGRrJ0GXoe4uG00zvspJkUyeWy -U6e8nI8iBiKKXQnaBkPUYlRN6MDGQynAHDiKJgJ5/3/KjhWFuXus+om76XxMNBxL -PSIoLtZWtED5ID/TgpMytsL9Ry8a5E1wQ2J/GDcUlC5raiK29pfyIQKc8kUQAvqj -ROz+4xOJiUcQW2CYBSat/dv09S7TZd0eqxEU0CaJ0T7DL2lGOdi+YCi5BfmQuQmj -hFuH7InOfEDXuuxoEMvOmkpOmpaf0sHRkh1LSgfLNG0Vj80Z8fjKoRXp7FBUvjeM -NgvgkNj9PHFSSiq7mdmdvoUjL6gFnLCiCQApj1a+jCU+NPgDsnwj8O5ZAd7+/W54 -vmwM5MpUNVitjM7zqnj+dJtSe8+rK2XYc1ZXZ2263C+ZCj7N7bz7Gd7VdO4jK2zJ -m5S95wFIS+utX2gXg/+gNiivqmm2eyw1Dl27Ho0fZxV2MssnELDVKhIn5YfkhhQT -0YiI20ECjpDcxWTXEknWGHiQl/1+3SbLagjJIvUFnOaVKJ0FwQYSTB++4oGe7sNy -AAJX/Y5TPQZH4jBvU+FaEtCeqq7HjTqLDkyWvWnCIwJQUtnINmv4joaJz8Xv2RvD -srwjuX5kFBEudB/UakugDgGnH2ytO5uHk9wBMVc9Flfae0NlGgwGCI0fU6X42bZB -fGvgicAI5tmzmKKg8yYAeFAB732+KNN7seerVksH55JVXSZr0iumRCktdyavoX1o -WJjiGcGwIuS/8e3gdhsET0mDuHSHOfLHATu6p7ZtOofIp0wPQf3t3KFoABD/f1Cf -hzsz5nyRUXQCEeyptNpnqjmqoLlvjBhLjxxxUIkDj0l8ACwY+rG7BTw6JyOQ3d0B -aAs0iERvaOMLvW8jFGQtiELGcpzZ4hz/7soQ/gVJkN5DjrNaDLN2ofv7q3bDJOvX -nvlDqA1Q5JV6QGYtNf4k/9kWzXfpXsClqhiIbkn1bhOu6sGyL6a7e/LUlpUNBYz2 -QEC0n1cfuJEQ9nvqLJ+niTKAyFuciwScQKxzN4DsQq8zhElXCSL0T0rp/MYWDNOy -Ui8SFwXUAMqidS67LSRU5n8onASYtv4HMPNkbUB0SMj+yz4RruryFmhbBMzmbxch -hUgU0ppfeNOX9V6rxJFiXoBoBs5+BM9vmMc1UM9ncDmjtyUlc4ZxJsXQBqcWTO5q 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-i7ZKK4UFASlHrl82GQfg7lbnPmaUOrXrqpqUEbrhn7WYl5yHnPtGZ33w7ojFg6JH -QDtVTxSpf0pPbjemUfWi5T/msZlwJVT9Mx+kjgFajyG1ztS3GEoLPdQqo5vMLNjF -6yL22MItzoRUxPRucNbImPJAl2p9NKnSP3y7iNe9nDO+i4+wKD1KlM8LcwYuJ9lP -bOo6QvArwAMunxkgWO64uM2mqoL5+2qqWIoX/kOIKSyhESp+emu738SYtaszE9av -//pragma protect end_data_block -//pragma protect digest_block -nWrq3EPDMtEXfKvYGGpSQArDy4k= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AXMNUgx+35APeT+Uh1zoekyaEw7FKPAaxxyAa6Q8Epve4926p5t6aOUqjm31poWm -YkzJXrFJDf+MY5a65f9vjXEYavFbWfqstM5gzpnVEYrCosK5VL4V5haz6/0zm4W8 -3KFU071+dSKb0Ufe4/PRgxBz5L6UD2Q6qbk8pFHXdHqOsuoYxm4jLa0FBY4eoMeF -B3X4RqxbqpDnTDp4VR0rxrbeVE6WR8yH7k/V/F98ngoo+vTi+QAfgYdJqZxlP6nx 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-6Qb78DapxqOnBiyee8IdUiXu75UCoHv1VA8UWeLE8XpKud8A0BnxCvEzNN9OR5SL -DkI6OIB4wLtGR9WkCKTLuiS/GkMh/DAyPb3qmReWIREDXfVLBEdfagHlRTv+JMUg -Ky/X1Kvzay2GckEyNAt6+HHcStlUy+nbgiOkTS4U64gpW84vGovRmvuvNAbbKclu -Qka+daUPQVSltDxDoBb66C9QWYYhibW+H/CbuYPOPfX0/DWBAT8Db8xWGosGYAoo -mWCHZaV44NTrS1n+hhTgh3ctqe7T7VlqtjixXHXOS/9s0ok+Mk9AhtSga2DyDUkn -Qyy7Z2pCM5IbWzrIWxQ83ss7RmQlutGYWTy+K42Bojt1+pGL7J2CyY2mSbiQOdYb -BaQfKs6UM6XkZ3nHCuxToO5jfKy922OglLCrkmVnb4dE20oKwCn46lJwpStCLHSC -4Skt0+43e7SKyKJhszpgoNeDcVhBTZpJzAK3K1YOxfhJzdfdoELhCEr/u/uPGJrm -jJusPpfXT6yVtsAFpQ0VhmcLlaDmw1in+ooUsmlsjbKZXs8TWwljY1dbiKxySsYn -6SrN7vcZggtIFepsmRrAVECFcy80UewjTFvDjbbxF8syu4GJwhbDxtXie8HwCUTR -HUwpcPljEejr7edJbeamG/998vPJmnM6TgChNdz2cfsty1WILfT47T0uzzAaq0XO -gqevW/EVRD1lJhI3hQSsTwoxkiBsZ5FuezcX0xRkHx2OXtFtfeVWatTpu4y8yM+T -j+R0HASbTGEvi6n0MGDrY2PH3xu4dXwqpu+8NtrE7EJbc7qKS2SbeIMx2hQGnshQ -E0NpGrmjiELLFuxOqai7s/WQcUpTL24tz026zKaZCB654jz2wQl0UIG7kVq76HgQ -LBvoCH+Eo4DrSAZwRCocPY5+0Lt9eUzcZZC+MGEggGGRU/7TE8jigl7PgX/S/Tpo -StqxBlsZ6IEdEaXvlxpopVsJu6rvPoVIFFkmEDZUPGsqKYhv1FSawKXKnZkEWVPv -pk3UdkKNbsLzov4AEjKvUv6kwv4vMI6tKjPTyra0CWpgvoUSN4vooGVanBS+GXuF -//pragma protect end_data_block -//pragma protect digest_block -U9YB8/0V+ciChAhgBpR+Mjh1AqA= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AdFY3ddNMI5ObsRGTGZotARFS3CJ+vRLMss+z4M2RCmeWnJYSwbOVqDZT//3v1XS -eZCzvuRSef58imif0HkcVPAPNYx88rZ5R5Wx/QsXAvOU+xzC7nw4m79rzsNreJKW -TECIEiIMrfMnM8TuBS4RJ8ixg2QUxCNyypIpEwob+xA9sLT53CWnVC7PL+RGHtbm -dMfCpH7nsJAzmsF5GPYyCnYnSLmABwHoG3M+7cd1fRbjm1u0yGMCX/Vsir61hSWL -MRns9UFy1BN9D0IV7AmqeDx1lY2NfQm/6bM2X90oIAQ4R15r3rNgs/KRoFmNhAfo -l9LZHRSmPOz3WQkMiwp+vA== -//pragma protect end_key_block -//pragma protect digest_block -LMsSFqJZAXHDtTSKQpoQfkCpEXM= -//pragma protect end_digest_block -//pragma protect data_block -7ffQoyizsb0QzXTZB9aeQhlsi162E8F+lDclxV6tQubQVmIF5M6Atpj0EXivf+Rr -uN1sD1vbrdZ31AE4o2o/eNtFyecQnbWEzvmSwipUU6wbpQAWMtosJyZy1FzIiiJs -peAko7meqrTDG3dKFNVp1R4pyk/zxoz9j7UntuaKB6hneenjRexfZWPdzHpjL5lq -Q6Gq/56DOI8x/Vsya5VFd8sx/F9yPeTHwaCrJcF2UNxtNjs+rAgR8J7UWpIvagtI -R1EHdTo694RVmscvNWjhHG+BWUkJ1AD0fjvDkLh3zfY1v8F8aY8ciQmwOsTNP+v4 -LDTUL9KLXvLJzCD8f7ql4Rdd7KEyvZ9jl52HQipJg2kLi3GeEBUuoPae9ZQ8QexG -kAGJTA9wdjTATzO+XeT7INolWKv8rGl77X0csofJnaZ7FwbZ3PRLP8dNiuV/4nKj -hvjCh76+ufm4QoWzFUFkE8hUUa8Ny09X9SeEypMzVYD/4OsmW1Tlw7pACQKlZKwT -TNv/snOfwT8AizSjfXektkq0rRetCAYTD4fN3+VG6TOK7vhyaHcnZxfuleUi42uA -APv/4OnBCIrQptda1yWzAfH9WGTnySl2cAz7oCqA89FaQ+WRMoZYcl23greBDMRQ -YRG1CKII0heGRGRmBFAIVAvhiWwS8lJ/c5woTWIQNRe4MFyglIAwle2Ry6JDQ2Kr -/p1BXvbMYhvIHJEAwlyxiGSpzIjEShmPXTMcVAd2jgqWjRhoY33qoAe9iR3L9+2w -lZnipSUZA/a3SdYXjW/Khpg0dM9g1xfZYI8+UZcEcp5MwCirr0vs+Sn+bbhwUyMD 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-K57kWq1R4DY6LoeBMSHbKUuEucqtJQwFKO5niNr44oYdKIPk2aje6Y5ziBDJ0oPq -CIvT9FDYMujmRAVYhWDOhBwgMRbiIjQul7e7UK8iWT3+ncEuzTNaMmVl500Q5c2Q -C3DQS7LWVwtAbO5spBCyONAwyY5kAFoFq/1MTOXgo5q32PAVtsycii+BcHW81VlB -QlVOyLz3qNshjbld8wsPsg== -//pragma protect end_data_block -//pragma protect digest_block -Yac1UeXsmBvviCciB/hrnaEqr10= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AbhYTtNJq/FK+w1fFKm+6xLsSwJOb+mq9T3w8qXIOEgIUR34Njn53155UJnoKrVk -evQKf3BDVcJFLDEZFnCWmDCVW7pjhfevjP3nsAWwNYyEp75//Bba7WgJNlMzpJfT -SrvHXafsyhaZR0ZyxMM7Z2XXjvjBnjZK8vYLfi0J1br/pcztvahh/83ZQLzzfd5S -lqNwBQNiIIxS758t26qAl9x+srdZXs1gKnQgWogadySoK5ww7L7eG2yYNBXrIgnR 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-ejie+Z2krm5BJf37oyZzKVZupG0851MQ33SP1ZB7vT2xDTKraW40OpDYHi/aJXdB -je74G147+EUpbaqyJtN9Khh3Bm1JLm9PKQRnTQY6KOdBOWRjZ/n6IueswGtII1GE -1+H4QjqP2Yh/8Ao8RaakcXBetdZ7ijZ+XdzUiUx5Qmc7pIZkuuU1IpUd+Af8aMbz -KHqBcVAg+mbEI++iTtsS4rH68KU3WMp7cGNM+ZAcEVuL84amHwJW0XowW8/VlpoF -0szNkuVrPYcCMeU1YP4LTngfg7XrhEwit1xNIqSRcOPjR+Prdh8CV/aqhHiZxLBf -A+Do4Tc5XiBFE1byyP+aXItbFtVmja/eSIdFPgD3netgV2Ufys4ySvAjaomfpZ3e -JYckMrAVbRc06s437kYbJh59GYnCE/MVL7LbdgoinrVAnM8y2xSqqhi2ViXxcami -t03WpONtKtJYMzjLqd0NE0YnxCnO18Att2WiHZc9pfDjwcAPERG1AWiYkAaxdBcE -pDm/jhHtpf0tflOjCnRbm3JWO3q0g3kSB8If4UKevqtgYVjqarWtumh3xSLaaQki -ZkU9VXfxb97TsJZBygr2h4ACs+7uFjzozqkn4Hy2726A667VrqRnjvMAjeF3TCPJ -l6uwYrysGtT6HTsF5zY4FBn/zHin2GocmvCnK7hv2wdCH7yodzaIyhn0Z+/0TO4X -0f4S6RMehtoihNHaY07fHwnhAe0FVgygDcDYtF1cbVgk5lB2rDOKubc9uqlg49Xm -BNZIVmTf/82HJPPDM+t8wKwagc/hLocq3ZC1hlUb7T4KjsKi8w6lz5nCSft6/ItE -53zsaRZRAJkbZELWS/b3WcL51wINach2iVTtqXMHkD2/v3F8qfawL8Q9eL3BfHfa -Nf8KIYUXcQGO1+hwmdhAq2LUGxfnstFk/5QraGzydDlhef8+V24qopHSsOQq2SS2 -SQbd86EfZRWmhY1Zk/ROUfeKlC5s/gcKT6dxqIHmeZ8QSKV13Aw6l3y7tIMD5z24 -oaT7bD11fVOPd4OaeLZvYI5gDJWmR03zH4QLklWP2tvtIFwWoeW8p8Q7wBmpddq7 -//pragma protect end_data_block -//pragma protect digest_block -B3TkFI+3N0Wc2L+4rgj86RNP7kM= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -ANaeKJ7tSaIxxZfCymrxd1tPx/DBPXQg9P7ADT/kL709RAii9I85IereWkupiW6X -fY7mD+I0mTNaDYB55jD6uk/Tb/bYwk98jdHLh13Oiftml/rqOBjYa5s8RCFlCzqi -zH9uP6y6Poj227jCJTzfWZJaJIsGUpHvR3s+DzzFkDJQfleeW+f4VtylG3SgJckZ -b2s8xuNsNfcm1Drn1nYh8yX3AdzGbZ2UWhHYzDdqdLGLa1v8P0CGufu5lLcq1K2G -hjyMxuyqZ+cExm67cN7Y7GUi8gv/mX2r3ESjEZrKTWk9q9qQv1DcL+WaNoBn3I3T -nxFVy3bqck4R+XXscCf5qQ== -//pragma protect end_key_block -//pragma protect digest_block -qtP42qWnCaGHeHrx5eafulg95k4= -//pragma protect end_digest_block -//pragma protect data_block -loQKr+1WLUX7sLtHLOl2Sjgs3mXgrTbgd9xeSqHYlaBd1KrdhlYujcVXtr6WJdxY -o3zPy+a1ST8IZUbL/QYPlv8/SjwE7xXtcch29IaQ82xkVRK24NKTuXfafCFuMRrx -uRaAZirRXN4UEPtZs1aG/BSAvk/Ico+Vs7O0cdomS2SA+4mcMLdLap7vgFLVW1Jc -ZMVA7UZqNbm3tpIiW0SpSQx4fyIJ96yQJ/Fgby/g7tjGKqAhidkuS409iasvjzUR -cViQtPsnUed/UFbJJug5jcvd05U71Rf7xPlxq1oPAasVs5u8iFrwJ0t/xZ1FP7GX -Ql6GjLzue5RoyRzuArd+H0kbNjJkz9W69sI/2IkJAUVcwAfBSm+z6L6x0/xmP+jJ -3OXM7+X9+jWWOuqvwePuHqrtuVm8W7q4ZGm+rlaypiirpgMuD1bNQetdVo/BK17q -NedzcGNeCKqMPaE6e5RzfUhkqREnsilsEz+uqtjPvLf3AHNybjyntgDpNOxersZA -RKh9dpGDFaiGtAF7vxQHdNifzbjYa8EsUrB9WJs1gyF2ycpCHpSiGheUsJiyTi7V -fnZPKTwIxennbEXnTORQGcyagB3xyPTTRGPTiyHaCXZ/8lTNHcaGE4iLrYF3Mntw -xrHcvhGC1O5S6qCgRUiwbvOdrIVT5ImVz0nPoJfRol+C1u+sghO4Rns2r1o5QjLL -i0DNpDhP9W4OQhNu2ztYaCBVdRVl12WE24diSVgM6WSohAzZJMH8foxxNRKMLD33 -UE6QjTju1Hp9o8v7/pO5eahPQqyn0h/a6NcX0W8fDwL/gkNViCKa3KAQTPE5W5hP -EbVf/yEDMLihmICiWq2waqUwHCC408VB2E/QXrWLljtRKo984kN0zJwpHJdyUdPq -UaYfxVccbiDCAktoq1znf7ky6NWR5JXodW7l82x5sLjPoD8A/Wu/gRfeyRdqO7Kf -778gOAqzQDFrORy2R1XWfp3lY5MQkwHbH1pYHHifKvi5Sneh6gz6FXbJtQQtV2xO -yo0Xpbfo0JdRfFGQu9GYE78b42AeefL6vyLiChHr8/tsZBr8PFjmVBZoOeWxDrW/ -Igwt2nAvKma8SEtbeV0GFzsOvzPvlNy3tXUZg1//z0s7aaZKu1pOs9JrdalCyq7Z -EUeb9TEIep+br22PvI92EcYrFSpyz130wm74FLht21G760Qu3MqGrtw/NitItUeg -m16erFbwtjMQSalQ7da6eB6tmNCdCkF0ZagC/qo9kGD1Kr26Z/VVSsXztq+Cf/HJ -cNJbCjFiDDg9l/JwROk6LzZWHPi9x6sUkPPKEhrrLMhEO4zlvT5960bcd1ictT8l -esf+21BoPCS7Fb2GKFH4bCBNBrOThj3AoaGfw6frJCdz4ZeIBg2zHxvaGxz47Xb2 -u5vDpYmPBFdTreJrCWpqVfgi8RnXshTEaYxdZdHHXGiqr3N3Lx57FP+4kvHBn0X+ -oXtndv51PZLYt1J/3KTEoXrxfAaupr9gk7ycxjeiEk6zBH8hArn532OrTUMEOWf7 -zTh1cRH0kyLsWm6Vnpf0t+zZihNqOiauFET/Bti8pG9rkDqLoi6ioJMjyrRYQ8OJ -aS/dNi8J61OGWtsWjP0Z0DGP+v+sTahLXehwJT22Uq6Suw/JGNno2L5Kbgs9o1JN -e8sZ1HA8xw9jroT3jHMCNjU1YcKD09Ai+6eoH6cuqSgYdxIkyJ/4bczAHVsBgKL2 -0YxrNICXgzmYPa0N0l0l44cN706W2695Y1AFcD2sY+3W9tSvjnGsI7Z2/pBjlByi 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-0hmtuw9Gy+ujruqWjQck4EbIIUm8n8kwW8HsBMqeJwkWImaSMmJLZPDhmZIELo+l -X+yG25XCZBT3cl2WmSa+Mm0eyIGVZrccAucunnwGl0PsIbsIfb0ZD7lDpMDPOaKU -//pragma protect end_data_block -//pragma protect digest_block -6N9u26hVMpcbyyfmRwuCf6Az/lU= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AT1EB0I/npWqScdRvpJcRO4gQZmZ32n55aokvX66dpBReWYyfJe+e8xu3FsuL0hj -xFTYzPqCsokjEbxWJcQ7AqcTcNtY92dNwmIFk+9mtQL11nDQuEcAz+9qG+DzKQE0 -wEFxB1EFOwxq3BFrmHDuIOBCt4mqLXAlzSTZW5xJI34SVmPvvsg9ljtOu5ovC1fo -qrj4xbbiOv9JlswWSL87kY3/EAlJB93cTi8uIzDi7mLeylEdcn2Jw5H8S/Vwyafw -pM9YxN44/wv1Sm/j6jj5BDCKjFZ+0zxNMHtlB96vfvM2pNIgnswgk6ZCMT8kyGMR -eLKSDiJKdiLlAm3AiIYAxg== -//pragma protect end_key_block -//pragma protect digest_block -IjTle94Bs2ph1I75fY7zPvZwn7c= -//pragma protect end_digest_block -//pragma protect data_block -jEwb8aPdGcJbG/78ZebWTFTU/Ib2DeT61bEMW5W56vJUleaukGL7KoJzTTwLEw1b -OEtglXQIcCsUJz6B8MlcA9fLKPpPgtYkHxcWnNSSxxW22BTpVXM6iIhckb3QMaKh -rFK39UnLYiuZpCKu2NFFlVECv84Q2hV/W9wxA/bfyL2H+n425Wf7e0A8YN9Mji+8 -eYZjcLX+ey1yvjENqI79uEUREvBee+aZJMgYudNyXTXB9MpRXNXcFnOIku2t9OKb -Id/DdAaMM5O1rixCR2QyOJLd2NVVmoXEYBEGPnjk9y6Yg9XxJfSRwv3YMgHMq8db -eN2QfvW+l5vrTTRc41ub7AYB2r2nhVpY9KHMMIt7VJkZ4Bosn4b4ebLNq9C8cefm -hP3TK4N5O+sSaRi91PXj9LRKCjNwrVrkvW3RgDzxUe4Fir+q5IOc8czPoTjUxhcU -y7NVBi1dprTq6vbg11irFbW9sykx8NJH7AWFPKEbpVk25y1Hre9UX396KY7RmSLx -Lp7i9sY5k4rs8QIEzydEmtlyfP8bX61HccrJaAokH9bcroIxhF3L0TDxGxllH/mK -hOtHROnvelqID3Ac3+h8puXvs6vb98TydQKCrlXhwKl7UiVZVGeeRDSX2DULVzwt -EGQGUW4qiUuE2+vVoZeHCHmg3oByct9xMid6+7e1YbpNSnuTisFbGdECbEKtz/Xj -jYDe7qL34CsW3zgcmb1rFhUr+4TWEjWrlUWG7jPYRs3ArkDtF9i3ifVL+juwukNR -AshO83H9aIjiDsg9A7uGaCFzkKb/9dqHdSuhFPws0jvXKscy7pxDnZx2TU5D+rKK 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-IkUM9adHTbxFflbkSctkL4KsqjndNg1OjGDchMYrxF7MFmR47TcnJvxOkgFBa8hA -KBEzxfse3zj+Q0WwRzZzPWg7nMmBGSAaa5+8w+GosH4p2acXgEQzzEmSVOHp8fmA -Uk0eaxc5ppJMdQdqxCgd5od/D9TZjZ25b4IqTtEVavo2rGWZvl927v1q6FvloqkA -MSYZjFmJX/vUq+1ohL9v5LxdoDYy1EXLk7KJ/DMXBe/aetwf2pGL8AEpnPcVxk8g -GIWKZwohsrZ6M4AruTeRyNAqE/11DOyGR+mXHRsXFNvfrITUGA8kCOFgKA5mpw7/ -dlwCejg2oayitROSurMw5sPLmzTcPoUPnYSffSRXbsnwXBVgG2gar/Ph+4pal0W9 -qvcoTup5B6FuDGnEV0Q4GYKX3Usx0QzvhXDxOxRX5a36CyobXZBFhirg/de4zSpk -2PLB9fy0KcSTmevSunSBNguijiND07+0JJxiDxtRhVYqmC/0ZASjPohs+9RIM3qa -+TShF3j9qT2hZyuecOpepDm/PV8H2ZFjvAAQJaXkXZfRFJfhbvSaLfgBiWoE0D9G -Ia2Q3QTFTuextDGwucjC4K4EbHTpVKqZ42HYjbU3Vu+JzFDw4mVodrC+CNc8fgCy -9AH0wJDj7orYnd7LZh/d3S5CQOH1e4uYO+EheyrRisCDuA+wMvULGZYiFSf6FWKD -knQYNzLuo/0bvSCkEVcmFb8ZOGNyNhMNm5QrNt1OEBA= -//pragma protect end_data_block -//pragma protect digest_block -oVKojFyDpw5GaFjaBy/xgPtTTkw= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -ALEP0YMKgY2hG6kMs04J3ytNSCr7F/iMNJKtSVcQNf2nURIh8tgmUuQpfKedON+G -spusQvansFOzVgoi8JYjVQQzMHgqtriLVUNC6Goo7dbuaEy3NYy5IyBYJ5iwOYdL -X7cIbkKxnAFeMusuwsWRkdfDLft/pCqr0wo+76mQW9Jwx+DD5JzOtHwRCqoHT21n -nrg9qzdGO7eKZEqtQ/fvFHYJr01/zn85jGx+JlaDX6ZILJP68eAUjBLbaCxb8rVM -Yi0+qmto+QZkkuAI0Lul2JJkTYGpQ6a3MMsia70DpLOnt4TBdRCMwsdmtCG4sLmS -MXuDTBs8Hpzg7J0glGHLRA== -//pragma protect end_key_block -//pragma protect digest_block -H0bopUu32ivTFDA3K9T8J8SS43U= -//pragma protect end_digest_block -//pragma protect data_block -xSiDBU3P55Z9nPhPcRJoLNdiEV18n/eqw4MStefAh2Ht+DRhQl+v927uY8KQbqfw -nwpIZW5JcvK+vwBSoCmQ3izGMoCW/UruHGprihkMr0VreOxFWJlrPD1u0UqjiDTH -k/yjgH7S3JvGOQdJvynT4m3j/vywf95vdesePZaReQhCVdx5dOXLC87yka398Ugg -vWrVRpJeU4kTi9BbdHEYPKNLMI3dF25nm+8Y+YsUsuJqujkdHUAhJSgOIK0ci5ox -n5boIolqTuoHq85xf+o+PPMwHeykh6Uz5Q/Gq2KjT0PKn9avSRilfMPNnC6fIATM -1foGRuuz2UiwAn4QKEU/vjNeY1mlfLY0e7cwV+Z2udW2GH0igdPzn2nvHeRtN8lq -zuft3kHvWFmSH5Sg8w1dlL18v+XbJnNtqCvuBPQ9pjouZV40kehzawEzsawKmODE -IQy9NEnFZ5DoUGm59rb0mzcoRUBuf6u46K546Tvs/NrBXPW3EBWjWwksK4fG4QHN -j/tGpttczSqXZLFMsniYk49MoPvaeS2Vw4DBl88reyTiyjq770U6nKX54tTGG326 -149y4ZamqD6r2bknCwDJF0rHoM7++MfrL87UwB7NW1cVuLTdhN23yAVrVazVvsu1 -suwepSGaJ30eYtCQmpJ8AYxmU7e00Nf8fqwh93DIZjYs3Vv4gvhuZczGBMKPn8mQ -7c0PuNNcs8lCn/v2f66Au0pIXdsNmtf5Igb6TFHycqrhPTZz+owjdb/s7rsZ3lXT -9TwgljYVP84wDZqvmUMlp3//aNZhTqHf0YY/ft8uhGrq3UCQRLVBgbXmtal6gdbU -sta/TkTZ9YmWj34P1zyUlgHFDk0mrxiLqhCcCr/D9c/8P+agWBxjJDs5sbATiXim -WjqKCbdr+VIgVV+BSiBmR3mXB47L9yyrF09Vw688wT2nxepsGW5mCqa+ecNhTc7I -VxekweOkBEQNDm5XluDn8OXr500TWc2cq/MGEMPezzCBlnmmdpGkSgtZHpGaVrt6 -ztuGb/1OS1t/+RDHmu5S272YtACfD1qyI5sJiEddr6qMarG8lCAU/xGROqMbpfc5 -wb17QtLRE01AGyh7q6KdskeuEbFbDSHgcbxibivQ9FL1z2FfG8Sm9vnGzPPGfO7N -Y0KKULp0/zqBJ8RVhzsmZo/BQkxKvNTm15dvoyIaGO+L3v9F0xU+tpKVwAwrYE47 -tJXoFchyEIW0QEZUU5A4vXu/0dyQsiaHWe0ZVTAYvI3AoilUzXs/CR3BfI2t3gGd -g6ft2mqweO3xtTYyvWQ16xtDqax58L2bUdXCHtOQWOuHql5BXWe1m0O3VfFhlgW2 -V/Tpq/ee1DH57rovVwAHHYm4yh+HPvZuzW+Xqvtb4vjWKQ55rMUnrLPkIs1AWZW4 -qtiSPInZiE+UlKWTFPwmEpzOMeyEEHPDzq/+gtBtNKDrnN/RkjqZlVbmhUGusgpN -MTW1mGkLhldfm2PhgRF4yl7K/ZReVI8GuktRmK3H5fy36eyD0yP7oTQCqZ2q5+Wn -K97i33FUKT0z/3lRMj+nOz0iL9CNqFMn6JpmrktS+UJl9wcZqBDGU5NWivx4ZN64 -r5dYBqUOkb6gtCrQQguKW1LB6lM/bH53OQ9OoeVQzXwOZkvdiBWmJGqoA3PoO+Jt -sxD5dMcKEU1qfOvWq764QS2WJsYDaBcKUrsZRtQWOnhAJLOibmS0zH1CFi9p+phs -w7lQRD6L5oe1q+iX/k65VDEmh3tgnpsPYDFVoz2QTwwdcxceq2TscQmD+vPcg2tB -+Xu6YyVHPHWqOopDe07uUqvHGNyK4FqSccjAIHzLoLJBhqn7sW2wzB8+7gv0QW/Y -Q4DRP/aU89/SzUbUmXMy2M2k3jsU12+yMY426APDgjTnI3eXIXkM3Q2uF9JT9yt9 -r7C1GnK6DbVh7E47BW8Ogt4C7es8orlN7vh6EIwV1oPK7RUroJ2XDt9iVJJqW5dY -B6rarGbxqspOyTbvClRHgXg5Pcb3RfUIoptIe2lm4B8tKJuG6XV8A/s5KNLm7IZV -ZFYsxMLywDnByltIyYE3lqVMjlmK85Q048KeU+uuSOSRLPdgEQYxTFn98vnKUx1l -k8mVZ1QWD9ZI9tSMGvptftHnmgKbapeu79JFerNvbfqfyNkTURvRfvMMdzWFbsVK -bNcP/SEcIS+aqmLY6lDiKYs7q4Y6ELDFSsueVGyG93fs5BmqKm2Dd5uBdRdnV9VH -tqGfNkhfqfV3EGZg5IbmNqkRZgjMwrWJWPYPMOXN/74ZUN/o101XqIyqo0PuAE8x -8SpssK/IrbIcB5WnQgFMk8nHseDgunesmPjMErskxxXAjIDdHP1uWR5mAk8oabMn -S1F9y2L+K3YpYk6U9WDvqtQ2lMxKmX7D53qNK464280g9kte7PsgKXW46+Vo3FuI -Dh5yIs60Gq66x95KENnYM9hrPmaYoFojPI1XeI1vQ4bIz2LfonAbWYzJpbppBpjA -L89n63glPedbdK5ORaFogR9Wx+M/7TbJ8A/fr7h4zJGZgzl3Px7zH384w+kvsKdd -FUvI+EQrst3no+ODS+Av9akSkdlfgSEIveS/q6zMdJ7TTABxvyimhvYO08LQOuc8 -IgiBL3Bi/AlmkKMOVKwKigngMFk5NEbHbAQpGk/j9H3BNpB/I1nG4M2/TnHjJEL6 -5h89QNj1AGjeZ2ipOcJO7HKhwIUJk1nHfXr/jVlFv5y1cTQcT64Z8aF/LvNiwT/b -swBhWw+mBjgwI5cl36ZEt5llEZ17RZu04zW4G7WpacqomP3TRdQHToKmCaX22q18 -VMHuJRbIdFKSw2nypM6Kn8vkzhspLM5pwwmx3/WVqt14LM70o4hZdwjRj6CYLFZI -58yEcFNpbDWR5Lyth9346k+lTqATZ9Ed9wFzkMtizT5R/ulm/pB6fXyoH5ufMUz/ -+kkqxjkCC27gksQYX4PU73l40jzXwKPKDe5Imk7p5zapC879G36ErxI2PfDZNgR/ -ekz+YQo21IgpqisNB/v6rJATLhM7ywb15JQ3qu/w8OGZOvqLfWjETHkhhhID2Cp3 -2v4BUeIuSWZ7HiknHICshfDeL1ymuK+P9ETDDFe3+ry/6ipUCaAZo6x7rNUyYBfv -gxTNeegmbxElQ+7RPD2bjLsJXXDzuQJBSDD5AoiH6EEI5VJ3n8k8apifeLtot0pC -fI+6fLZtFwZr8R0H/2Qc6oLUW0XStUkQvlrTiIITCzcPcOO6oxZXABITO9oUbE3j -4+TKcT3ndOAbi8VUz0ZPrqA3mOyjhUNbA9YRuc5sWGUnjtW0V6wfiHQpfnj8GA1D -xHfjM8VLW8GWBJICuq7kZJQkaLv3g5VLvzsHEZw0Hy90sLR2txPRVaGb8lBPSD6S -T713wecx0hW7F6rXpQscZ9tukk2oT4H/G5x1TBqFk3OIJaEB/S+xrmmiA21ZtLZg -bwxTs+XUkofxRHjkMTs0XnRdvlFAA4dvPesP7Xcvjoz5Q7A/o+jpTcsMPrFKPy1m -PZnJj9sJLeT5IqbbKwSQioJzFhpOwApUYqGjwrYcTABAyoo0LmxPLOMSiF3zjkSh -8fkE7rBUj4g8B6cjKxMajcB2scmwYg/lvHT2+7xHD3BYvBtlLl/XABCxSNVgis0G -TOlf6Jao3sEZxl3MRY7ybg699a+AXndPuGPH+omD7w4NNEBk68zEyih63nJT4Rjv -ChU97nOiGTaY/QxWT5dlWPM+CdJkYV2zc1Q5zmrGeOtoDMbpxCu4d0/trtgu8fI3 -Eqq8ekiSvmiZFinzFR5Xurs/E9N3JpUI0jsGn87/G5L9Sv5XlZGz79R3KVeP9Nly -ZJzlB/2tDidVK5xGC8ChtdsoFQAie4GFfhHvQFyuMBT+ZhOJRvPyMO8oq2VxgFxK -dffQH+ZzbDuFgbRe9L4GS/pzDNUybsVYML1Wv2ann3Ux2o4Kdq7WgqJ40xTnJKDJ -EJjlyif6HK91PovJd9u/RJ1Wx32EZNIEimtuc9QMKl2DgWutpU5GqmhDW8ghpLnX -+obbOY/vliJBqaKB5ZBOl9a8woJA0HN9WfwZZGhFPzAavpwnxvo1ZXWkL8EY+Ed2 -gbjCBkFgmYZ2nQbH83TINl4QJcQuqVWRZxuO9L0eZFIeni7Xi4lWt2aNPIK159QA -uQN0tX8jJkGTw85rdBS7MWv181aPQ/1wBvd24PfMsOPK8zD5PvkT/Mbc7SMiHtEx -fg4IeYz8Xf3c+SBQBAx2pavDPRnhGb8nop3/QlNw4Dy6wsV843aZnD9vUJhune8a -yZPE+qL+W+CwNWq4DRfInjzQncqiIzoN6OYHczXH8FVDX9/hATazPVTB7PuWm62G -1J2UcFWxcow6b0c1GztvYAKjfe9AIzFmi2ABjMvpwztSlEIvqdwU3wCyaR/PCOdC -OgEA90/UfEXtTaO7hhGQ/CaZZYdIg+15nrXqYJydgYfcZb9K0Vbt+MmMvEiFTQXq -aqLFtR6Qg58q7sPjkkMKpQUZ0ZTgtg5Bn4WW76L9xGjkhGRqHtqLdLxtB3oTIgsp -lGrC+HD0ynFYTh8gxh/Y4S0jMl2JBLJHEYlRcGefIbJWg1lmW3FhiEumjnvARGhh -LTAaTaf4XUVgh5hfHcbDEVqexhxwzVPndmkfY/4HHJ3UFMEbZb7BttdXZXcgTnkf -nkE3LxELdIiiPN4BLsc8+pU4i1jQSQyZWjrUfKdGYEUswkxBqqS/S6oJ3Bwh7qI+ -ASBbNeQNaq+S7najqTvvw/ybnVv1vMOkAAajU4ooFarcmhX30l6dOojaoC6k/q4Z -xSoYnZboqAZ46xV/rbtHIqIhSmALbsIu/KNNhWzAWqS++/0Mmt1u3TCWS3mRY2il -CnfRSr+sY9smcSXcqMO5+rCR7NGHlzGyZmmzg1mpqcMK46e/RXTwr7Kp5TCTytDX -4onS3i4SkWOTPuwkk+ZZ+8jYtf96QCo8Jjh6NxhpkhI0UjgFqNTfpEXkxBANNOlB -5BFU5sXzDNPpepPTvuFkIylk89n9lcNODhcT9nC0AeC18OAQZyRk2aAo2f+W8ax0 -ipcedQgQUMTdSYBV5lIM1D9bZ8X2ypjr4NvE215pb6WmoI2rA2YmVBFDTSZ8OO0z -uPhBpY02cenYl5ChIp4KO4BK9T2CALs9v5ZOui5g1fSK8NzrQH0x1FYHAxP2VFPX -PsATv+SFMVI5ira5n0uA6hlWl2BxXltf8+zucpZzFJ3Hy71mUgQwetYSdwV2d3nE -EG8eW3zGvBBdXzEQyz5T2COcLAmHaG85Kk5f1Dyey/YMEuJTXY/FPBAHJW4qFbG5 -B/VYZx1kxwdYGd+dNjtjL2cz9Cdv16WZGmdHMHbAq7XzMsffM8BVrlBN0EVoUyUw -DBJuD9ERh5bqSs732BBoIwI+IfQMfkQ/PTmp0rjSCJSjmOeHpzFOvFubi7VcYuUu -GEp0d/T2vvyq4qRAYhYklOQi70+msgXjFp4G+DcFYI+mO/Sal0QeCf3MyDV9HSUM -YGbBrsN+XXcOq5KRxP3myGUZPIEGv/SzvJ3QXP31ruBwtDSxV1S/cZJzCplVX6Xk -MCwCMLogDoWTHWsDEhWR0ib8ryMtOnZwa0Yqdl1RAzvXlBzqajpojliJyr069Y9i -Rme2JIlQNriCxNyhwSYYOEvzehn/eV2DyhZ6Z0OTjHNp1Kaqy72Th3qG8NELJkmh -2M/Iaok2KmIiY96qEj6Xwwp1iPQcfPNwRuwoBtN1PJuQFVKpEYWla1oQM1rwXUxB -3A93+vgJWCs5Q0EjijGhdJLWz3jLeC714arYYf6rSgXvdoPnJIUfXOG6Z4Zwtqq/ -JtiE6Be/LYMWbmWtZiRlvDfYJtHU+oJJIpK8im3ZLP63sUr8I2vR2Lkuky991UJg -bJdQZAEn7bl0HT+B2eQpVjVJeHb8XU6u1jv0Fw1oBa0E/YVpEOzNZciUEYnn9pJr -nYLxJHfEQSn9j0wu1Xc1LMiZPyT5+zddc7keoBk998QeouwuXKDl5Fu1h41EMOu5 -dsrGu5kuaPQQx9JI+wqt7dnJHujs3SNx9d/yOwx69BE8tUdz5ftKmGrL6dR4Wz3v -X0HqpxqnP7VU+/fNNXu4OIZMAkFWQ+L9F6JG5yFgtWOSIKJ6xN8BQHskUTa0UfH3 -AvTmJEqs1b0fbCqFeRYXhd8amSzhwyF/BfJ898IQum9g9VdNuwoIYmEC++sJDRV7 -nq2oFsw61+MnW0f8eh/jSRgbpmMCt+cXxUR3K0lZiU9CUh3F/+wYxGtrOhINd7ji -BuTCaxBO7sla00f6VoZOdRN+295B3GW7oQsqrPaylbntpx5pMTC/WGsJt9RMrHeh -ANkhnVKchQhAmSPF4gaz/Up1RcClzPslGOxWn/PH/FLPALns/aY9tLBB0c8RpaqN -0KLkJn4R6nwXAgVxxuukldB60MK5ZU+OiKYcAboTaaW0KvgMXx+E9brnehdkQPBG -GtF0YvGNM5o9SkUPQe3dsazkM9epBweFjYgmrIRH2kQLX3ujWlFnVUTeBzVzfIYw -j9HRrR9hpfInKLa1bQvWswWaqm9glHMreXmfPbsWITgi2A3mfzoOXPCKCVTse0Ax -3egy5UnVr8lVbXDOUugt85aaRzQSyIwOVFGLJYjox/IL9Sszy+v6dDSEoZ+HcBJA -4Q5BLLsdKPeongJwe+/JSknVLsawUvo1JM/w18jeHllduTq19e2p+UdjLGBHunSN -XYjDcgUDIiLjO8Dqho6v0rkhGxtkPrUS9u1Spp5S0PqAE5LMuMjwU51RhiCTBu7E -abmHwp0PJgOHErP0Ai1NhuXOlUELPhgLXHEt+c73ifIjqZByVdOEYPFzWJTOP0En -WYolXUFdhhy0PcmAK+qmqv+kIvicUIlCjBzHDYXt1KG9hriTLpJYzdlLQ+rrmxnb -9a+mSvsW1aWLxZlIFXS+gn8y4iyDCOL8cawQcIuBgl3MRtYit4YrWzP9di0XVWNz -pW0NCAOOhqTFzoP2CTjRJmnQseJFBIJEF/K2TqAO++L26LGmm1LxlRmYHXOSiZ5B -0jy9R23pZ1ObZUpLpjp1jbQXi5SfAxKBK/w53UpvJDgX3A4BAuXgls2+FI3srTdE -mWeiKaLpTPGDMCLExxB59sIZN8ESJwvTleBjAXJg2Lk= -//pragma protect end_data_block -//pragma protect digest_block -1Okcq3Bx+b3XH43kFoKz4zxqo5g= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -AQeRdzVOqJ4iwDoe99zvboXiU5lXFKDvlhNtq/WoiJqz4LI8dneGqViS0qW8E5cW -dFrNY74BxRuU1zUyWX2q7ND72HLZ7b43cP7d8Tx0UViZ4YnpFDbDdItwoawze53j -e7dyCusjEq4t/mD6olfwd9QnMg1orJWxZ8cPJ5j5xikDWP7ePgP4c277SWzoxnac -zaPxeAhOFGBJeIchq5UPEmXGUYcv58Xb5AlMc9yeTKOd+qgNHT2a7+6pvw0nC/Xu -X53tQILJGS8ZfJDFjSphdOcpjwpyF/M3/LJvhukvC3FT+TWVdtiq9wFcgfuQvGgP -b2syN15Zt9silhfUS78i/Q== -//pragma protect end_key_block -//pragma protect digest_block -ITI7TKpnea8mGeIScDpwDiMkohE= -//pragma protect end_digest_block -//pragma protect data_block -tN84ozPtJgItVKSJa+JX3LCw5hsWc3/koaW74ODjnIcLsx0UhMpwntPtDiCxsC3w -zfCJ03MvTDAjpYybyzHUV06rZnOGF08tZzDnRhRlBHJqvuKGfXzOkR/jJLCojJ6e -qO2NZ0ZT0I1aQAN6RL/NsKYmA52bRdOP9F+kPbq/1pVTsK68pbO8WXEZqjcO2sCt -HTrkxMnP9pGuYivwzG7IcUGpdktkCPa3VDhQw9RYaDVCyVZX9x+OJKHU7i7xp96i -WtSdlWNRE+lO4BBRvXWOLaGTnCuvNJTeYcGsbj629X04Lpg4YxmOB7u49VNxFSI3 -xydQZMGQ0MrlmCGNiHYlocJLKoXc0JCFMbUPJQREK7FJslx378FNifLH8XQq4Oqe -WDD1bVzDYJRILpCNRnvbXGSdJOk11tGY4c1R/IdJca2a0qgG5xPOOPI9jxltbtlz -lBlpV88yL6EjJBF6SPXu3t04Hhz0nAh/5Y2U09q9nVybwdG+qxuiv6gtF+D5MnCF -14u9y6KaDa2+CszIkaRDudrhzE1PJj2P1zHrqqI3JWFZ1Z+t1hKxogOIhhZVl17S -l7j9mgjVTnZn6PTGpheW+rDfm98F9XAQ4UBROzhNZ7IHDJH3dsZ+Rz9+1mmAWll6 -DBYVxO3t6ctWale79Nmvharu5zN7A+wF5OLWvOXlcVtvHdq2WAbQSJFpIxX6avXM -9zBCsTjLYXepGS5klnvN7LAFIzkrEt5NcUpZYvMDCYHjDGsffS2SkkQDriJpqbiC -mLRs7mQbEveM+aFm7ENerH+pm+GeY8OhLupoxl67hJP3qyLI1iqIF8fJeaLiwoJW -wYQZ7g02ROZtVMNseFvxkyapzyoTfi9vdZLiglRZPvdpBmMAmhwSYfsT1kIrIo9t -KlQr+N58nrYhiPrv+5Ty65MQfoDTYkoODlH9MEN/AzNsR9Wx9BeEU2M9krv62Jsq -gf1vXputWAH6UQHCZyO3irucoGmGz6cDzjpM1io0pM3LRyE8qWjc6SMAOuAsII2P -/LTCsd1RVUtRAhOub11pSYYR2PCeJgZ0IvHlVr8C/KkKooIKE/0LtkTu6/yQBdsZ -vNAdQV0b+F617CfbwYODymEj4W4TWDZ8pp0Y1zgeJDeMWIPgGlF6A4Ln1/BRbvWZ -EU1heC8rCKGDCDAanXv+K+Xdl+ooaYmDY1NxDzwkOkWMMBnUX4lHd+P+uxaBypaa -LVWayzvBrjum/uB8yFAkMSCk8qx0ebLFl3ioQnZR5bdIbe6ht1UXZRRXJQt+tY0N -Exr5Mr7NNMkl3NoLrdKV5NkP+TtHmiEDJpErVF8Le3UC77H0rs9dLtRKLOLkdR4G -eijzsSdksvDqxixbgkMaRjEOjyBnxWKqE/hKWqDbSaQW1Kcpn5zd90y2rHCOJEAL -P67iCOigD49dJaMAdMIXa7eUE1zXqstWzj66Ya5TUjBddXooVljnncFnFwcSqoKH -OK6l0MRjAfjg5lyrVkAzn6dFQBAbobwRCfj7mvcVcVp6gkHbCzujnImd+eHngS4e -uayNLDNdUjvRfntRTcTYgkc2ai6CMPGfFpwbjLDNa8Zi+SymrjANhRNfIr7lDLwT -G8VD3KdEWOKAvxKxtK5Q9xmohB7Cnb4hrayjbXYHGm/7rm9pBGDcjxUx73Ay+3ae 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-XucfI0wWXM5gZtwbbrKrpImEILJgKdqH+YB1jS3ZOLtwO2pCX27TTmpF2LVrbZcq -ocOuKPeioqmaA/iCnPnPhYmhIJyxRtoZp63uUHLorce2LIxGg15yKJ5k9hRW0JdY -30RWPI/Y4PWbDVhjBY+6GwXVspyFTj6zSTEHjuh9XxZI8/U5zLtViYFFy1Qpt112 -NcggD7mWv9jHJ9/dy0g2g0bdSNV4L0YQwmunsiPZdpX9nBjM04etGVLPi/eNNrQN -UW3y1t31iGBoR8/KkTrjaHykl9T6ubW8bSPTXHjT9TrWDpb0t4j2I/bERe6Mx/jf -FVVzeFvuAMjc5no6WuaUdSJebLcQ8JRygdVh7IPiRTIAWte6i5JHfNa3gMrm3uCq -MHpEnH9RgzAgSnuc2oCJrApNB7N93b6zuj+eYy7G2wmMLWQik1uluJgXdA/2kK6N -L6ncjAHyYLoh3V/OnfD6EQ5QCQSX5Mf1I9bRlfv7CIgw50QKAdPcyhazbT4OxmEm -o8raZ9CgnKUxc2dK7OuOZOkX5xxh46TjxEBVV2YpDG19q5PO+BwLw4egsAUf5zSA -N/iVJaca1ZVEKvNz/ISVKOYLXpfdrv9/wLy2RDvVCXG4Ftjah3orTycn5FsroVnc -dMyDD8WcunSJI/AGhtPfRgR3+CkcID5cEtcLtpOgllKDS1cyDncZxXa/va30on6M -qBzpmhpYYNUNApndAGF8Svu6O9DuRuN3B9uiXWPxA0PlJ0EbHAVzBa6CWaGoLnPH -tMFm2HQ678DBSyUzwz2fS9GwvwqOxlhpvqbJ9yjlVAu6A2DgWF3a9m9tDwL2Yqzs -okwu+Dxw3l33rweCtsXCy9R7l9M1YZ0I3CY33RP3lXaGjMmJ8a+JTFmlNqrdyS8W -VoYH+hEV6GA14pUP4fnPwvFpBHuGJqJUJqy+mJ5PLwv9493UP+qxHJkollXQkVVS -irdsePkx2wQyjaxOjKzhyqMKU0aDVmzsyHtLrPPLrcg3BRxz0QSJPRPGkh078xrK -gfv2F1AmPszqlzd/bA5d8WzBM2nNcapQytH/1sjmv1BtFdL/9jeKdKCDJHXpyzPG -EQZrUkGIctdFcb8mYCHgAky6UFnb6DSjcybAdtIrCSL4nXVZWrRaZEqEj2oAYhaw -9hDvyvItzluj1U7tzFoYYmLwuQ6rfcr5oBp3Fk1p3gManBmInkIKda1H9CUru8Yd -nL76vUDAWfU14zrkuKYS2iTNHxPfqM84R+ca8Ma8BWTsI38lqTg1sQ4opnWucpHb -HNIuyZyTzhBu3AArKfn46GjNRbdzA3VPp1hTTbcaob4DIbZKF06PYblahzILL3uv -4igVoxzjgxgVljBDLZYJRRBxWlUqoP2Yf1Xui+ngM+XXU5um3N9qMs+YSDWtMFal -/718ybd7xL98JHb9Rgt3HlrXep12Tj+MZjLh+vZDuP8N/xr76odkCJuBU3Wc7XJf -8W43sCFD7LPmh8821iwLhsqT/2sldj3qhlpMrWRaWlyFgSsMQkUNfll/aGOaLk5b -hXdH9iyPJgqMtgjmpiCyHxeNgZ+rs/zXF+Sj6iGEmskTVJMcWYUpmeRHuJZBu4jT -2w7KoiVLY4wO1rMyxLS0kas0ZbQc2hwhGiCm1RmSdGcwvyjqnj0RKA6Sm8jSg8Fm -5ZeQ2zG2Kh3zhYbRn64GFMTbg7tPHP/wF2L2yah02tsFix7Q+4N2Y8w/0nSIxWvn -98LEtHkP9ra3tKYg8XWnUkczx3g4ffkWayqLu+6RuE7LDLWGWHsIDjKLSXykCaYG -TH4hMMf5l9t5r6JKK8mRDVy0U9JFjme6yR6RSZ94P6nWk4YOmFaERZID7dG7PoZV -z/kKN2gouyVkiFcPsuvti5s4N7zSlx4/XA9GPNXAjSr7mzTcA8HHcZw2xOTaj2XF -Pd+6XQkMh8/gudBQ92C3CT5W3PEqtrhipsERxoNCNoDbGFylslMqzVRlt3diuf48 -MwUvJo9s3QodnX18DNOMPQeV82KXViLROm+dFTvXBepDxsi+4IMPGVREM1e9ln4f -W/3NIA1sGIfX6AfWUloSfp2UMpAAN0PNEqCVL5BOvMyVTd/nm6C0tfKRf2kMMoKi -wMj3J3GhQDCTEvNb9ZHVD8truQYrB+1lltgjusIAYBH1s+JivG1ubxyY8e7+rJ4T -HReXAJ6TvOpjY/4JcWkL8yQLJSNomagv8LxgLPSshTvyycR5UHYc4lSWrG19t0u3 -RK9uRf3mWr1mnzUjviQKIW7I+vo+llvg6bp1h6m3ZQQPquQV3uftcoZM/LKHNZv4 -CD477OOO6dSiFAv0NhsOOCE7ONXRjzJ7X7golNuO+wzRnDvGKHCCF3k/MdZlrUvW -6+D4xx5eqORujSoYZgilZLFVpzvhJuBi1clrTv8gs85SRJJkhtAQBe6OhoIhbfOm -//pragma protect end_data_block -//pragma protect digest_block -GB4TclGiedNPwOlCGOg+lt+8X2M= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -Ansv9YAwGh1QaXL1XvJIO4maHH0snzDgp0De9+9uCOGT7CK9+Roc9kV8pfYNuPlx -wSpH0ULhTI6FHPRKT6sQFmLuiJ6xFw7VzoVhPmHhpZSF57Tnwzae65R/Q1wuBFsS -VF8eDk0UtJJQ46qXepGqz24I13aL9v3MvqCcL5GprH5TkwDCgArozzr2Iwg5KsYG -fwuEPi78tJuSZd8J+iQ1mJhN1xRT4EEGZq7Q0SEJk74s8r5DQYoVZLfrqtInkP9i -gBebjMdYOLNlwGBFQJxa7r6QuNiRihf9E/lxc9CsNGzgLcfF4KFl36kNJJcMORRP -yKmksiA1VTS/ApNZ0EH+uw== -//pragma protect end_key_block -//pragma protect digest_block -0tRm4qYvLsm4+VVCglvfy7MBywQ= -//pragma protect end_digest_block -//pragma protect data_block -9NWSUs3T6JqlmsubqWEDqL68Gzk6byUddFxu60jMO58UwMsEKSx+xGNyVH6GtgIT -gvk3MxLAUvKyLPY9Hlor/Ux3oaY3XYay89Gs/r9JTdz+eYvoSRmmTKfFq61MSOxv -lI4GTgYJrRk8tpjkAFiWNghVyjR+68GB4ITTxWnrKEq3dBKKNlwzJILw1mH/odyF -LCvpXu4+bvViiJjz/h6av9ECRe/MJEUQ74SFna5k1ahPmRcJT5bo6ebKz5UdpwkS -ZLsVYGTuDceOTKYkqs3hM/DRalfrb0DZshkFK6iDUV2J9URjFO5KZLQNijCjVCNs -kEHoKLOysIvn0KHNuvJ00ke7FU6V31TR7UyurCQBlU52+JnPdxlAZHLSaHiHuTsy -SFZDrTJk1IY3UuXhCnvUQA1GMwSyIoDB41cGOLquARJqXxGZ5wNoy5jsTIyZCZpk -ZMLip6nBXttmXSIJpDuxC1honfbdFXPrDTYC7lF+CW81FmbPRjv2d+VKjYeEVsev -nkTGSnbXdhKk4Q4gFVISK0W64QuYgzi2cTEAo0088TkX2MI0ndlyccbVXKp9Nm28 -/ZhLfE7ssUzDSi7rsuMPSLt/jy4smvTd7QXI2LizKBXrBLGxvbcnII7/zoG0KqIW -oFvWE/tXcgpwnyga4eu4i7/tGxaZW4UanfVqlgTKP1EX8OszabWe0N+Kjdo+KslT -jSadkgAE2Npm0ZxJsHQhaBjNAkFQM0uH6FS6SPPbbumsjJedssMp0Q4qhDwLXl2I -grUwgaW0FMP+oDDaTx+gp0H0Y2slAjROk5a7N2Kgok4PBa7XG52chWoqbLDGwiDA -Cw8jvpKVVeTyVpsWVMGURcOdkIaJk1aPwUqocMDYQY/G1HAm3MU3HbCm9iUZAo63 -rVBpl1h8o7oCSTI5UxjWEoooZlwl1pxCC3JzT3qCceaGSFKtymxP8oKz8ALdX6sQ -w55eDoJLE5BInO4j3lppUgXfsmYirbl4bgZOE4X9o4gdDVQ5baQrAvcBUpUeleBB -zsXr5vVaV9te7bsHW9eQFxBBfzINNeadH/0CRfPj20HvwYnIaeY6tKhiuzUuGHzs -VqTPFnAI1hItn3X5DX2/IuiYKOX36A+7WrMAVtflljOf/eg6wL9ahzYw4BdKdwqX -K1trXc5yJeUEQn64C20zSAWQj8etl0DKQwjvHFfJKI6BkmONs2ppEK+ptqglpy+t -QMkuRAdgn5U4XaXwWdgIwIJqhE8ER48kydWNbicjJJgcaVBu9NwfCXi/LopVHLqp -xTdnl2us6nOOxgVtvBF7m/6THG+1F/msxs5Vg45oLceCM8FaOascPbYfVPQLPPjK -n1VxrseqfNprPnbRxFoLb2T8an8649QjqVsLZzJpMVbi31KDKs3XGMi0F+qYCED5 -5XUjIZAkD5SNUGwIDG29JOfwehVB5w26qGRXx/QJ/5gJpJU17MDowZf3FdDpGiJh -KojC77GGjCjIDkDCYuiRgLda4Oa/vRoF+XO0Vw1dHJioerJTSX7p19NGryfIDCAs -X37RVc94+NctN3ySw1HyA6wzFjD+T7GN0ghkk2qv85BEnDTm7d0gIzXDTdLknelm -/zuGongbnEBA3HnLhvMkdnNMS4DoltPDgA4ucdLbV2y9/v4z5OCXattvTpVvgUGL -MhvJeOB+0qqIwAFmsIvh0FSZ4WzvmIKeoOEjRMMP0zPBIUzAMhpHwlbcyfa5o8xP -DwAPWKPUgJM8QU8mx8/1tP5pClV/WeDGHDV72/1wlk3cbalwVW05N6PseS7xxgT/ -LMHD2q+tgHA1WSx4M9dUSC54l6ZH23kflsFZ4ltTCxS2z5kWdCeh/TjqMSCpnbL/ -k6oY0vaYRBkssaHZfzHoa14jmno9SRsms8lkCoSYbQA0zfbZTYOOzN1ie4tdcYMO -UHbIUPGU5y9wj8mLdwHu8U0A9RnwzUl/3H8s/pYWigMWUDbDeu9TOB8QVFU2fM+j -ShquQc4E5CdtvOOGkBM4mOdRIrcfBbS/dfb6uyC/s8uMtIhk6cz1Vs9JM77bCxpN -YQN4Y2K79msgrxH9kLtg9TtFOZkDzacXzlKWKL4EJyCPC6dSOgz3M6egFHsdMk5K -xPQmA74i06KrxetqszF36ZRzUb2PaXr9saHZbJQSUrDtZT0C3lhiRL60hZPpzO+M -ShiDak4gAcqzhmr67JT2kqTiQBZsBcIHj4IP5Dgpa6U+id2w6P+CT9AyPL3OU1UH -iDHF0PWsd0mXvRdi267k5nA4lDACaqyiIui0FBEZQuWyRIJ58xqsT3YRAlpk1Bn4 -5TlqZgciCXKTfCekp6iDr02Wwk+CZZ6timjx2S2pjRk1ifjoDLlyAxJKczwAE4Vz -h3vzPoiRpQW1kB52NH16kacZCn75ujjLBzoXAAAwjgHpDIPsp+/50Z1xNpWVEMTZ -2bXXMJkRARMHq6O0EFARL0HlyIQwY+kFd5DdLQA3E9DTdlLFnDJmnTTzUujZq4ke -1b0St+TR9wyZkbqFw6rRssc0DcPJugIFuaNBTLNQ8nFinnQu8okJIsyfF5+EmXfE -07IE8l3DQgAor2x0n9bc+KxShsexg1o6DWcyxNhZ6dIAiyLUsCHA2mCsXwPo3+KM -LXpaL7ZJvkTy2T2TevmvBUirBpzCXJEDNPDZ2S/1aXm6hFdNDXnjNzTKQ+wq3oAE -LSvRMfHsb+3Wf5S8VdE8nxWJf21H02DpbNWv+jjDVsxlH9I8H8w81iQcoKXecc+/ -s7H2cVj6pBvd+3pj2t5duH32W5BZTH7htf+lXJ40VPEzDDojTstktTq9fO4b3Tqp -t2iaToU5qwZ0X2bTEsJL0rOTx/IvWe/zpRsneQ9vUkDMxjbsZbfhQ6hx2LSsvB9z -+vpUAQcXHEmM4D9SIuKbFzoAiRY0ZztIA8DcFKwJOSBBEOOGRI3nandbSyiXrnG8 -f3AQvX3vVkoyVR2/KdcS7PH0zHTi9dWDo//PmZ5EROdx4oNfM0uHs9HBLo44MMzy -irMbyYaSHLUEuUWPMjy94MRdqSs7HsqwZPQbXfkgccnKllSzLlqiwVk+EN2Q0rmM -ZycFWw2Y1ZwEmlFkbBaZqmS7Y2Tm87XJvuJDbKOUAGg2ppOCBwL74iVEx0E1Tj+Z -LmgaR0xZcsoPhjy+2+TShEN0Qhcuod4wrFScCMnR6QjulLPZaw1ogC50rj3yXuSc -ZDRih4bQ0U9BdIptJ2g3v/Ks5/+Yl5CHoVYhSmqz7toBPZmjS4Q6so6vnVp7D8uu -KTJg0DH2iY8cV6n0JzO0c857HY+f7MtnyCMh/2lPDq7U3Nvvxb2B2MgVxPK4tYb9 -upAtk6R6BQvYRwogWvso+0lMU7gVAlk+hAmHdMHErcmbzjHW4Y5QkHPI9mxg6WiG -sWhd78YZ9+REZZaO8aI1A2p0YL5rrdQzWuj0wVHdnWLvyK9XcEi6suv41BO1S6J3 -R2cMYqmOEYYwibxRbEURGYEJdBccLpCyk/rQ/0tIgvOnzOx51pfcoBvBjdiv0JpZ -nsJ+iaOceJRsHtcrDZXyA2qDnoPGTWFlygMWMKSL+fLXu4f6TpQrlM316w4vRhEv -OPWnxAFuuX7AfeYM/qBWSb05G2o9aXWqdPAgbrxs3/1+gAyWN51/Oe1yK8a47V0q -LYWJqZmYzSnFMvtSRWXHmmzxn3B6egMOZl+SFqtJnlPqn3keF6iXc3Epg2q7se3U -MmNJ1oRuONsG4MmGLM51CpI2Y64zWpeXA3IQj7lHTZbSEX2D0hYACdzLchHpTYEO -F/N2KN9wBeWKLrLsyqF6ZVCD3dHBQaNYRfVBFkJzUk4TsEYz1u3EqJJ9sqkOwgp2 -GeHKJy802wE9cI/zdyaIkRK0Ir1msGoea7WvUfh5QR6NpBPQWizn6krkRlCxACTm -EJCTNu71e9tJCMGAj04y7yBdob02T+n85suG79i4E6rRZC1t53FHLFtVf4FZvTZw -TUknMzLJO8Z76Y5bZu9YrdmgTRzJvDyeIxPEWa3lnEcPP59lXffnpDXxwWo09T76 -IY6obnH+X3Ft8ny8mq2AOOYJpu/5/dDH6Mp4bmcFO3XUC6fvkgTMx+Oygtxjke5U -1qcTFyhncwUUkkedfPGpqKspMSrfwXT8TQEgzXXC6mVmxCSx0s82q09TLXlCvlUZ -2uavraV1L1vOyi8t/kznmBSAcvxSLtgfa8RuxPue0gjQatRoUvTRkL2PFyBAJgew -KumA3hH++av5OgvHvmk4EG+WcS5xKgsKWmPyhVKlVUFpAv7bNu7WBM62Asl3Prv3 -08mVo8lMkK+Smnx2N2Ya2M+QsA1b7wPlEO2w3MHYaNsI1uGPJg1ldxECGpukIWyn -aJ2A+gvC2hAydh/SOJWcRVHC/U9pxoAPjPnSKC+6liwQlR7AnZBHX31N7VR7/u/R -5MYdkgwHY1VlZwHBGlpfQR9gy7ALb7ndfIxxM2JzvQ6+MZT8xmte+QbLTAwZt2R2 -/0nbpB1AxLGnHD6uqVov8pgpCUQ2bKbUuJbOyGU73ecfYLj3onC8Igl5ksG/VgRC -8c5TqtBElkN5LVsCuoGhhBk1gstYxz8AlMEvknpr5qMp7qcNj0rJkFDUJKkJjWSa -rOPbrUo8tZ/aixj3E0nqS09dwEMbS2ZiOv04jwUad4ZdhpCN0EcIe6kQIORP8rhh -K4Dad19SXkN1dq+5C5CaQjuOs+CfQ5jIN6TimLA1LGgcwWfxS+EbGT5RY1xFRBVu -Ekv0qCyghdCY4GZen0568tDshlGO8+k2sSsEU3yQo2lPWeSFUc3Nhe0p8KWUa5K2 -KYk0yQJOYaWY1ttkyiZ5AWEE8FnpW5kLJWDDb61ZO9GYCU/6eVeWCmrzJhO+TsCL -0C8WEFKNIPHa423WWDaghNG3KomR0CtF7uKCUTf+mK9eAfxxrSn1q0/fIrcc1XMj -iffaAM1McTLkkUWjmgJHdKYMK5jRl05+15KG0N4mCYv3itsFyJCsHs8OF3Hh2aSU -P2AOvclZP5+DvLIqnfK8wOtD8kvDQOzj+nEvuWR4rgY= -//pragma protect end_data_block -//pragma protect digest_block -QmYdJtuhCo0aZM4+JP1v/m9eIME= -//pragma protect end_digest_block -//pragma protect end_protected - - -//pragma protect begin_protected -//pragma protect encrypt_agent="NCPROTECT" -//pragma protect encrypt_agent_info="Encrypted using API" -//pragma protect key_keyowner=Cadence Design Systems. -//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) -//pragma protect key_method=RSA -//pragma protect key_block -Amajp3mby2UDUQLdpbYiAw9tFvXWC0k0x3RvEBRx1c7yL98M0GQX9AuQAM7ZWGKJ -cFuoIgVye3DoC/kXHvDRAzLJVaNEIXzaL9LtEBb0LITuFKpVhVAiUouMtvCcp0gm -C3y/rHeZEZelkSb4CpYPOF3H6YmH1phTaLaahAXTntOJAvxxNABVVs68XwhFaOe+ -KEuopJkLi3hkRYWeaEyhj9kqC9IBrmXHUJYQ4qcIGIAl4tgHZPBv+0C35Cyg1Kqc -iW4Iczy8v7iNdsFAB/MxgW9Q/RNowBYIpnf61pXBeMFbwIsKxe8bTS1xu6R3+/19 -3kwGS0I922iDeQiFN3Ir/w== -//pragma protect end_key_block -//pragma protect digest_block -6EuaYA9k9pp62W1ll3O8D6cdfeE= -//pragma protect end_digest_block -//pragma protect data_block -2P1SP5SmTOE7mtxtJo7zszroKRkk1HUMcgSUCN9R9oRHJ1cWYMYtBi7Xj+IeI+j+ -rm41BpMtdSTMHzOQg7el4FoK32q1TPwHrqUyWfnbsozT+29fKWwaL7u+Xul0ks7C -AurHssgNXOb8BXqEVSPTL8By2mFKK07pTIf1tA+2hWYJR62nCP84hT0wueFva4U8 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_top) # ( - parameter FAMILY = "TRION", // New Param - parameter SYNC_CLK = 0, - parameter BYPASS_RESET_SYNC = 0, // New Param - parameter SYNC_STAGE = 2, // New Param - parameter MODE = "STANDARD", - parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) - parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) - parameter PIPELINE_REG = 1, // Reverted (By default is ON) - parameter OPTIONAL_FLAGS = 1, // Reverted - parameter OUTPUT_REG = 0, - parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_FULL_ASSERT = 27, - parameter PROG_FULL_NEGATE = 23, - parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_EMPTY_ASSERT = 5, - parameter PROG_EMPTY_NEGATE = 7, - parameter ALMOST_FLAG = OPTIONAL_FLAGS, - parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, - parameter ASYM_WIDTH_RATIO = 4, - parameter WADDR_WIDTH = depth2width(DEPTH), - parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), - parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), - parameter RADDR_WIDTH = depth2width(RD_DEPTH), - parameter ENDIANESS = 0, - parameter OVERFLOW_PROTECT = 1, - parameter UNDERFLOW_PROTECT = 1, - parameter RAM_STYLE = "block_ram" - -)( - input wire a_rst_i, - input wire a_wr_rst_i, - input wire a_rd_rst_i, - input wire clk_i, - input wire wr_clk_i, - input wire rd_clk_i, - input wire wr_en_i, - input wire rd_en_i, - input wire [DATA_WIDTH-1:0] wdata, - output wire almost_full_o, - output wire prog_full_o, - output wire full_o, - output wire overflow_o, - output wire wr_ack_o, - output wire [WADDR_WIDTH :0] datacount_o, - output wire [WADDR_WIDTH :0] wr_datacount_o, - output wire empty_o, - output wire almost_empty_o, - output wire prog_empty_o, - output wire underflow_o, - output wire rd_valid_o, - output wire [RDATA_WIDTH-1:0] rdata, - output wire [RADDR_WIDTH :0] rd_datacount_o, - output wire rst_busy -); - -localparam WR_DEPTH = DEPTH; -localparam WDATA_WIDTH = DATA_WIDTH; -localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; - -wire wr_rst_int; -wire rd_rst_int; -wire wr_en_int; -wire rd_en_int; -wire [WADDR_WIDTH-1:0] waddr; -wire [RADDR_WIDTH-1:0] raddr; -wire wr_clk_int; -wire rd_clk_int; -wire [WADDR_WIDTH :0] wr_datacount_int; -wire [RADDR_WIDTH :0] rd_datacount_int; - -generate - if (ASYM_WIDTH_RATIO == 4) begin - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - assign datacount_o = wr_datacount_int; - assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - end - end - else begin - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - end - end - - if (!SYNC_CLK) begin - //(* async_reg = "true" *) reg [1:0] wr_rst; - //(* async_reg = "true" *) reg [1:0] rd_rst; - // - //always @ (posedge wr_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // wr_rst <= 2'b11; - // else - // wr_rst <= {wr_rst[0],1'b0}; - //end - // - //always @ (posedge rd_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // rd_rst <= 2'b11; - // else - // rd_rst <= {rd_rst[0],1'b0}; - //end - - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_wr_rst_i; - assign rd_rst_int = a_rd_rst_i; - assign rst_busy = 1'b0; - end - else begin - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_wr_rst ( - .clk (wr_clk_int), - .reset (a_rst_i), - .d_o (wr_rst_int) - ); - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_rd_rst ( - .clk (rd_clk_int), - .reset (a_rst_i), - .d_o (rd_rst_int) - ); - assign rst_busy = wr_rst_int | rd_rst_int; - end - - end - else begin - //(* async_reg = "true" *) reg [1:0] a_rst; - // - //always @ (posedge clk_i or posedge a_rst_i) begin - // if (a_rst_i) - // a_rst <= 2'b11; - // else - // a_rst <= {a_rst[0],1'b0}; - //end - wire a_rst; - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_a_rst ( - .clk (clk_i), - .reset (a_rst_i), - .d_o (a_rst) - ); - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_rst_i; - assign rd_rst_int = a_rst_i; - assign rst_busy = 1'b0; - end - else begin - assign wr_rst_int = a_rst; - assign rd_rst_int = a_rst; - assign rst_busy = wr_rst_int | rd_rst_int; - end - end -endgenerate - -`IP_MODULE_NAME(efx_fifo_ram) # ( - .FAMILY (FAMILY), - .WR_DEPTH (WR_DEPTH), - .RD_DEPTH (RD_DEPTH), - .WDATA_WIDTH (WDATA_WIDTH), - .RDATA_WIDTH (RDATA_WIDTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .OUTPUT_REG (OUTPUT_REG), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .ENDIANESS (ENDIANESS), - .RAM_STYLE (RAM_STYLE) -) xefx_fifo_ram ( - .wdata (wdata), - .waddr (waddr), - .raddr (raddr), - .we (wr_en_int), - .re (rd_en_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .rdata (rdata) -); - -`IP_MODULE_NAME(efx_fifo_ctl) # ( - .SYNC_CLK (SYNC_CLK), - .SYNC_STAGE (SYNC_STAGE), - .MODE (MODE), - .WR_DEPTH (WR_DEPTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .PIPELINE_REG (PIPELINE_REG), - .ALMOST_FLAG (ALMOST_FLAG), - .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), - .PROG_FULL_ASSERT (PROG_FULL_ASSERT), - .PROG_FULL_NEGATE (PROG_FULL_NEGATE), - .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), - .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), - .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), - .OUTPUT_REG (OUTPUT_REG), - .HANDSHAKE_FLAG (HANDSHAKE_FLAG), - .OVERFLOW_PROTECT (OVERFLOW_PROTECT), - .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) -) xefx_fifo_ctl ( - .wr_rst (wr_rst_int), - .rd_rst (rd_rst_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .we (wr_en_i), - .re (rd_en_i), - .wr_full (full_o), - .wr_ack (wr_ack_o), - .rd_empty (empty_o), - .wr_almost_full (almost_full_o), - .rd_almost_empty (almost_empty_o), - .wr_prog_full (prog_full_o), - .rd_prog_empty (prog_empty_o), - .wr_en_int (wr_en_int), - .rd_en_int (rd_en_int), - .waddr (waddr), - .raddr (raddr), - .wr_datacount (wr_datacount_int), - .rd_datacount (rd_datacount_int), - .rd_vld (rd_valid_o), - .wr_overflow (overflow_o), - .rd_underflow (underflow_o) -); - -function integer depth2width; -input [31:0] depth; -begin : fnDepth2Width - if (depth > 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p -yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU -De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF -GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh -0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r -mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q -z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idxP#I5B-:M0GLUND=:[=ba))NYXA03V1Rb -ZO[aCWeS/Eb3_)O27cd-WCe?DS?_FOb_fN?3-[Y^O&/I1.d.4OYe&=+Z53@0W@dG@\\<;59&LV -XWfHKXeDH^db,c(UUL;RFf<+7I=5Z^>-4K)dQ:a]S3YNM/ZRaYA3\Uc@.:g9cF9. -012@V,QDaEE2>HN#ROZ^B(7KeZ&B3A7>14Z&QXG4cg)GKEDa2N1\bK9gQA=gX1SIe6ace84TF>8U -B(TR:9E8cH=CLUc&L_R.7OLDOBAEI@bf/#:3;GBS:R]6ZTX -ME)YS7=)-?)db#7(DOPML4N;?2&_f=N+VZO1OC\L133dGN]ZS77#d[FaI_bUcA6e -fEZ0ZJF;cf5SDF[Ea[,Q?-Tf^(JdJT8[/]J(f/;]A>@9.Qc+a99F\4\4db\4W]E@@O[)-&\P0HLKY+#3>OdGeZ5Q\eDe/@) -5_F?OQEeB(3ILabGc&[EeS(2P[2c#9>NOWV&[a9@DVDBA<-fgSUA#]=eX)6d7<(, -[5E-17#bQ\&?M1a\A;T\HcSXgTF&[B;V7d#1OC_1CE^47g)MN)U04-OgSC9P/B09 -JSaFb-De;fXf:+7?R[P2X4+_WNYOVgQdLT\7@(C?UNWYb&O0]ec^-P=-6N+ZV]5e?1XcNMa6H=[e/fM:&ZR+/a2O3HDaaa5#;4ZCR(>WE=M&I(KE@O863-4Y_6B3^^b4 -V:P#I9,6ROS1@/ -4Q/91.bGSA@BJQ,07HRR&^D^8.M7^E@4HC?JW#JWf?Y#6 -0HOCZ6\WZ/B7K4Rgf+34>O#,QJM-a/Sgb&6VBH,G&,GU-VH[01?9GS^[J_BC4Nbf -^\f;J7Oa=0?B#=FY304L+3d4K?5O45F^-4O@g#UcYH03OHW4C:>H(W,_:01B8d]D -Y1X_Z\+G4LMYE\/]P3Zf0gg+NIA@UJTZTa;g3&;R7 -Y[/Y#PGUE;.0B<&((eDb+CM8LbWN;I-JN+K:4I9W?g_X7,6C8M3_BJfFc-LVPQWA -:HPIP.KUc[WLcO7(VG<2MI?ICcPa#d77a<;PUE^P>L__&?0AIAMTOK9Ze&,e0+;;eK.f:1:]/bK3L6J7#F,,@\:(\UIdDG6>[A]X+>GK&O<-]S/]?4^WaQ[-N@F&,=C(C;\9_4e(IVdb03;fQKEI)DJaCRc74\NGS_#1cTO)?C^eC->B:?AI63(gNb -e<^PAQW:/a>N(#5fE,N>gVI/fZLA\G&aUQR/G_UNVTA?aa,A/AJ8SS1<[Q77a6J\)Y,S^XJ-N@M4ZJ6 -&4Y-Ad6Fg];)Ne-g,[O03>.RL[&fGS@OSTFNFB<6>Jca4Zf#;8M&NQ-CBZMM<&&CKKBT(gPPg\CO_^NOM[FS=4A5/PMAT -CDN(4=4851G;HYA?2? -)ZPF04,5QF35J9JC&\A93,C;fg5O>SV_MT?_ZNeK,,aZZ0VG3We<#22)O,FeM5K3 -U#:&S7Xc<^T]ac7@RgO<-W67]T[TYb)PK6.I^;/(HS.;P+Vd(W0:Db0NJ\VbD]1] -Z0E4/+)&+4F&8=R?>A8H4ICZ3cca>dT0Z##VWI^bg9,e_2ARQ4cESBD:^#X8&4EF -^)(+6O#1BVAT4F1I4Q7S/)1KURg-U]@DU3,+.bC_Y<&RUOVYGa]^QS2-#/[@DA/N -U#Gb=Qg?OaP0Y8[-U.G00VE.ISMfeX;M#/&@F7JE+dZFZK,P^\L= 8'd42) begin - if ((rx_data_cnt - u_temac_ex.rx_axis_mac_tdata) != 8'd42) - rdata_mismatch <= 1'b1; - end -end - -//-----------------------------------------------------------------------------------// -// THE DUT RX -//-----------------------------------------------------------------------------------// -temac_ex u_temac_ex -( -//Globle Signals -//----pll_0 -//output wire pll_0_reset, - .clk (clk_50m ), - .clk_125m (clk_125m ), - .pll_0_locked (!Reset ), - .sw6 (), -//TEMAC PHY RGMII Interface - .rgmii_txd_HI (rgmii_txd_HI ), - .rgmii_txd_LO (rgmii_txd_LO ), - .rgmii_tx_ctl (rgmii_tx_ctl ), - .rgmii_txc_HI (rgmii_txc_HI ), - .rgmii_txc_LO (rgmii_txc_LO ), - .rgmii_rxd_HI (rgmii_rxd_HI ), - .rgmii_rxd_LO (rgmii_rxd_LO ), - .rgmii_rx_ctl (rgmii_rx_ctl ), - .rgmii_rxc (rgmii_rxc ), -//TEMAC PHY MDIO Interface - .phy_mdi (1'b0 ), - .phy_mdo ( ), - .phy_mdo_en ( ), - .phy_mdc ( ) -); - -/*----------------------- ODDR Region ----------------------------*/ -//rgmii_txc -ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE" )// "OPPOSITE_EDGE" or "SAME_EDGE" -) rgmii_txc_ddr ( - .Q (rgmii_txc ),// 1-bit DDR output - .C (clk_125m ),// 1-bit clock input - .CE (1'b1 ),// 1-bit clock enable input - .D1 (rgmii_txc_HI ),// 1-bit data input (positive edge) - .D2 (rgmii_txc_LO ),// 1-bit data input (negative edge) - .R (1'b0 ),// 1-bit reset - .S (1'b0 )// 1-bit set -); - -//-----------------------------------------------------------------------------------// -// THE Base Task -//-----------------------------------------------------------------------------------// - -//apb3 bus wr task -task apb3_wr; - input [9:0] awaddr; - input [31:0] wdata; - - begin - @(posedge clk_50m); - m_apb3_paddr <= awaddr; - m_apb3_pwrite <= 1'b1; - m_apb3_psel <= 1'b1; - m_apb3_pwdata <= wdata; - @(posedge clk_50m); - m_apb3_penable <= 1; - wait(m_apb3_pready); - @(posedge clk_50m); - m_apb3_paddr <= 0; - m_apb3_pwrite <= 0; - m_apb3_psel <= 0; - m_apb3_pwdata <= 1'b0; - m_apb3_penable <= 0; - @(posedge clk_50m); - end -endtask - -//apb3 bus rd task -task apb3_rd; - input [9:0] araddr; - - begin - @(posedge clk_50m); - m_apb3_paddr <= araddr; - m_apb3_pwrite <= 1'b0; - m_apb3_psel <= 1'b1; - @(posedge clk_50m); - m_apb3_penable <= 1; - wait(m_apb3_pready); - @(posedge clk_50m); - m_apb3_paddr <= 0; - m_apb3_pwrite <= 0; - m_apb3_psel <= 0; - m_apb3_penable <= 0; - @(posedge clk_50m); - end -endtask - -//initial task -task init_task; - begin - //initial mac_reg - tx_ena <= 1'h1; - rx_ena <= 1'h1; - xon_gen <= 1'h0; - promis_en <= 1'h0; - pad_en <= 1'h0; - crc_fwd <= 1'h0; - pause_ignore <= 1'h0; - tx_addr_ins <= 1'h0; - sw_reset <= 1'h0; - loop_ena <= 1'h0; - eth_speed[2:0] <= MAC_SPEED; - xoff_gen <= 1'h0; - cnt_reset <= 1'h0; - @(posedge clk_50m); - $display("---- Configure TSE MAC IP register setting ----"); - apb3_wr('h2*4,mac_command_config);//mac_reg command_config - - //initial ex_reg - apb3_wr('h84*4,DST_MAC_L);//ex_reg pat_dst_mac[31:0] - apb3_wr('h85*4,DST_MAC_H);//ex_reg pat_dst_mac[47:32] - apb3_wr('h86*4,SRC_MAC_L);//ex_reg pat_src_mac[31:0] - apb3_wr('h87*4,SRC_MAC_H);//ex_reg pat_src_mac[47:32] - apb3_wr('h89*4,SRC_IP);//ex_reg pat_src_ip - apb3_wr('h8a*4,DST_IP);//ex_reg pat_dst_ip - apb3_wr('h8b*4,{DST_PORT,SRC_PORT});//ex_reg pat_dst_port & pat_src_port - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select - end - else - begin - apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select - end - end -endtask - -//pause frame generator task -task pause_gen_task; - input [15:0] pause_quant; - - begin - apb3_wr('h6*4,pause_quant);//mac_reg pause_quant - - xoff_gen <= 1'h1; - @(posedge clk_50m); - apb3_wr('h2*4,mac_command_config);//mac_reg command_config - wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.u_tsemac.u_tx_engine.u_tx_ctr.cur_state == 4'd4); - xoff_gen <= 1'h0; - @(posedge clk_50m); - apb3_wr('h2*4,mac_command_config);//mac_reg command_config - end -endtask - -task check_rdata_task; - input integer i; - input [1:0] check_error_bit; - begin - - while (rx_data_rlast == 0) @(posedge clk_125m); - - if (check_error_bit == 2'b01) begin - apb3_rd('h22*4); // read ifInErrors - if (|m_apb3_prdata == 0) begin - $display("%t - Error: Expecting MAC packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata); - $fatal("FAIL: simulation fail"); - end - else begin - $display("%t - Correct MAC packet %d, received", $time, i); - end - end - else if (check_error_bit == 2'b10) begin - if (rx_data_ruser == 0) begin - $display("%t - Error: Expecting MAC packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser); - $fatal("FAIL: simulation fail"); - end - else begin - $display("%t - MAC packet %d is filtered", $time, i); - end - end - else begin - apb3_rd('h22*4); // read ifInErrors - if (rdata_mismatch != 0) begin - $display("%t - Error: Received data mismatch", $time); - $fatal("FAIL: simulation fail"); - end - - if (|m_apb3_prdata != 0) begin - $display("%t - Error: There is an Error in the MAC received packet, ifInErrors = %h", $time, m_apb3_prdata); - $fatal("FAIL: simulation fail"); - end - else begin - $display("%t - Correct MAC packet %d, received", $time, i); - end - end - end -endtask - -task check_udp_rdata_task; - input integer i; - input [1:0] check_error_bit; - begin - - while (rx_data_rlast == 0) @(posedge clk_125m); - - if (check_error_bit == 2'b01) begin - apb3_rd('h22*4); // read ifInErrors - if (|m_apb3_prdata == 0) begin - $display("%t - Error: Expecting UDP packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata); - $fatal("FAIL: simulation fail"); - end - else begin - $display("%t - Correct UDP packet %d, received", $time, i); - end - end - else if (check_error_bit == 2'b10) begin - if (rx_data_ruser == 0) begin - $display("%t - Error: Expecting UDP packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser); - $fatal("FAIL: simulation fail"); - end - else begin - $display("%t - UDP packet %d is filtered", $time, i); - end - end - else begin - apb3_rd('h22*4); // read ifInErrors - if (rdata_mismatch != 0) begin - $display("%t - Error: Received data mismatch", $time); - $fatal("FAIL: simulation fail"); - end - - if (|m_apb3_prdata != 0) begin - $display("%t - Error: There is an Error in the UDP received packet, ifInErrors = %h", $time, m_apb3_prdata); - $fatal("FAIL: simulation fail"); - end - else begin - $display("%t - Correct UDP packet %d, received", $time, i); - end - end - end -endtask - -//-----------------------------------------------------------------------------------// -// THE Test Case Task -//-----------------------------------------------------------------------------------// -task test_case_1_task; - begin - apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select - apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen - apb3_wr('h83*4,{16'h10,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - for (i=0; i<16'h3E8; i = i + 1) begin - check_rdata_task(i, 2'b00); - end - end -endtask - -task test_case_2_task; - begin - apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select - apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen - apb3_wr('h83*4,{16'hff,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - for (i=0; i<16'h3E8; i = i + 1) begin - check_udp_rdata_task(i, 2'b00); - end - end -endtask - -task test_case_3_task; -begin - begin // to transmit tx packet after rx pause frame finished processed - apb3_wr('h88*4,16'd100);//ex_reg pat_mac_dlen - apb3_wr('h8c*4,16'd100);//ex_reg pat_udp_dlen - apb3_wr('h83*4,{16'hf,16'h2});//ex_reg pat_gen_ipg & pat_gen_num - - //Send 2 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(0, 2'b00); - check_udp_rdata_task(1, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(0, 2'b00); - check_rdata_task(1, 2'b00); - end - - //send 1 pause frames - pause_gen_task(16'd8); - - while (rx_data_rlast == 0) @(posedge clk_125m); - - #1000 // to have some buffer to make sure the core process rx pause frame entirely - - //Send 2 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(2, 2'b00); - check_udp_rdata_task(3, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(2, 2'b00); - check_rdata_task(3, 2'b00); - end - end - - begin - //Send 2 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(4, 2'b00); - check_udp_rdata_task(5, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(4, 2'b00); - check_rdata_task(5, 2'b00); - end - - //send 1 pause frames - pause_gen_task(16'd8); - - //Send 2 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - // check to make sure entire pause frame is received - while (rx_data_rlast == 0) @(posedge clk_125m); - repeat(1) @(posedge clk_125m); - - check_udp_rdata_task(6, 2'b00); - check_udp_rdata_task(7, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - // check to make sure entire pause frame is received - while (rx_data_rlast == 0) @(posedge clk_125m); - repeat(1) @(posedge clk_125m); - - check_rdata_task(8, 2'b00); - check_rdata_task(9, 2'b00); - end - end -end -endtask - -task test_case_4_task; - begin - apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h5*4,16'd9000+46);//mac_reg frm_length - apb3_wr('h8c*4,16'd9000);//ex_reg pat_udp_dlen - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(0, 2'b00); - end - else - begin - apb3_wr('h5*4,16'd9000+18);//mac_reg frm_length - apb3_wr('h88*4,16'd9000);//ex_reg pat_mac_dlen - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(0, 2'b00); - end - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h8c*4,16'd9001);//ex_reg pat_udp_dlen - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(1, 2'b01); - end - else - begin - apb3_wr('h88*4,16'd9001);//ex_reg pat_mac_dlen - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(1, 2'b01); - end - end -endtask - -task test_case_5_task; - begin - apb3_wr('h83*4,{16'hf,16'd20});//ex_reg pat_gen_ipg & pat_gen_num - - for (i=0; i<20; i = i + 1) begin - apb3_wr('h88*4,i);//ex_reg pat_mac_dlen - apb3_wr('h8c*4,i);//ex_reg pat_udp_dlen - - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(i, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(i, 2'b00); - end - end - end -endtask - -task test_case_6_task; - begin - apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen - apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen - apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(0, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(0, 2'b00); - end - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(1, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(1, 2'b00); - end - - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h8c*4,16'd200);//ex_reg pat_udp_dlen - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - $display("%t Wait for rgmii_rx_ctl to go high", $time); - wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1); - repeat(20) @(posedge rgmii_rxc); - - err_ins <= 1'b1; - $display("%t - insert error", $time); - repeat(4) @(posedge rgmii_rxc); - err_ins <= 1'b0; - $display("%t - deassert error", $time); - - check_udp_rdata_task(2, 2'b01); - end - else - begin - apb3_wr('h88*4,16'd200);//ex_reg pat_mac_dlen - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - $display("%t Wait for rgmii_rx_ctl to go high", $time); - wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1); - repeat(20) @(posedge rgmii_rxc); - - err_ins <= 1'b1; - $display("%t - insert error", $time); - repeat(4) @(posedge rgmii_rxc); - err_ins <= 1'b0; - $display("%t - deassert error", $time); - - check_rdata_task(2, 2'b01); - end - end -endtask - -task test_case_7_task; - begin - apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen - apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen - apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(0, 2'b00); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(0, 2'b00); - end - apb3_wr('h51*4,32'hffffffff);//mac_reg mac_addr_mask[31:0] - apb3_wr('h52*4,16'hffff);//mac_reg mac_addr_mask[47:32] - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(1, 2'b10); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(1, 2'b10); - end - apb3_wr('h84*4,32'hffffffff);//ex_reg pat_dst_mac[31:0] - apb3_wr('h85*4,16'hffff);//ex_reg pat_dst_mac[47:32] - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(2, 2'b01); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(2, 2'b01); - end - apb3_wr('h50*4,32'h1);//mac_reg broadcast_filter_en - //Send 1 mac frames - if(PAT_TYPE == 1'b0) - begin - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_udp_rdata_task(3, 2'b10); - end - else - begin - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - check_rdata_task(3, 2'b10); - end - end -endtask - -task test_case_8_task; // small packet length & small inter-gap - begin - apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select - apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen - apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num - apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - for (i=0; i<16'd100; i = i + 1) begin - check_rdata_task(i, 2'b00); - end - end -endtask - -task test_case_9_task; // small packet length & small inter-gap - begin - apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select - apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen - apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num - apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en - apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en - - for (i=0; i<16'd100; i = i + 1) begin - check_udp_rdata_task(i, 2'b00); - end - end -endtask - -endmodule diff --git a/fpga/ip/gTSE/Testbench/temac_ex.v b/fpga/ip/gTSE/Testbench/temac_ex.v deleted file mode 100644 index 15d4a24..0000000 --- a/fpga/ip/gTSE/Testbench/temac_ex.v +++ /dev/null @@ -1,563 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -//`include "header.v" // use JTAG hard block -module temac_ex -( -//Globle Signals -//----pll_0 -input clk, -input clk_125m, -input pll_0_locked, -input sw6, -output wire pll_rstn, - -//TEMAC PHY RGMII Interface -output wire [3:0] rgmii_txd_HI, -output wire [3:0] rgmii_txd_LO, -output wire rgmii_txc_HI, -output wire rgmii_txc_LO, -input [3:0] rgmii_rxd_HI, -input [3:0] rgmii_rxd_LO, -`ifdef TITANIUM - output wire rgmii_tx_ctl_HI, - output wire rgmii_tx_ctl_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input mux_clk, - output [1:0] mux_clk_sw, -`else - input rgmii_rxc, - output wire rgmii_tx_ctl, - input rgmii_rx_ctl, -`endif -//TEMAC PHY Ctr Interface -output wire phy_rstn, -//hardware Jtag Interface -`ifndef SIM_MODE -`ifndef SOFT_TAP -input jtag_inst1_TCK, -input jtag_inst1_TDI, -output wire jtag_inst1_TDO, -input jtag_inst1_SEL, -input jtag_inst1_CAPTURE, -input jtag_inst1_SHIFT, -input jtag_inst1_UPDATE, -input jtag_inst1_RESET, -`else -//software Jtag Interface -input io_jtag_tms, -input io_jtag_tdi, -output wire io_jtag_tdo, -input io_jtag_tck, -`endif - -//Debug Signals -//output wire [1:0] debug_led -output wire system_uart_0_io_txd, -input system_uart_0_io_rxd, -`endif - -output system_spi_0_io_sclk_write, -output system_spi_0_io_data_0_writeEnable, -input system_spi_0_io_data_0_read, -output system_spi_0_io_data_0_write, -output system_spi_0_io_data_1_writeEnable, -input system_spi_0_io_data_1_read, -output system_spi_0_io_data_1_write, -output system_spi_0_io_ss, - -//TEMAC PHY MDIO Interface -input phy_mdi, -output wire phy_mdo, -output wire phy_mdo_en, -output wire phy_mdc -); -// Parameter Define -`include "gTSE_define.svh" - -// Register Define - -// Wire Define -wire clk_50m; -wire clk_50m_rstn; -wire mac_reset; -wire proto_reset; -wire mac_rstn; -//AXI4-Stream Interface -wire rx_axis_clk; -wire [7:0] rx_axis_mac_tdata; -wire rx_axis_mac_tvalid; -wire rx_axis_mac_tlast; -wire rx_axis_mac_tuser; -wire rx_axis_mac_tready; -wire tx_axis_clk; -wire [7:0] tx_axis_mac_tdata; -wire tx_axis_mac_tvalid; -wire tx_axis_mac_tlast; -wire tx_axis_mac_tuser; -wire tx_axis_mac_tready; -wire [7:0] udp_tx_axis_mac_tdata; -wire udp_tx_axis_mac_tvalid; -wire udp_tx_axis_mac_tlast; -wire udp_tx_axis_mac_tready; -wire [7:0] mac_tx_axis_mac_tdata; -wire mac_tx_axis_mac_tvalid; -wire mac_tx_axis_mac_tlast; -wire mac_tx_axis_mac_tready; -wire [7:0] pat_tx_axis_mac_tdata; -wire pat_tx_axis_mac_tvalid; -wire pat_tx_axis_mac_tlast; -wire pat_tx_axis_mac_tuser; -wire pat_tx_axis_mac_tready; -wire [7:0] loop_tx_axis_mac_tdata; -wire loop_tx_axis_mac_tvalid; -wire loop_tx_axis_mac_tlast; -wire loop_tx_axis_mac_tuser; -wire loop_tx_axis_mac_tready; -//RiscV APB3 Interface -wire [15:0] apb3_paddr; -wire apb3_psel; -wire apb3_penable; -wire apb3_pready; -wire apb3_pwrite; -wire [31:0] apb3_pwdata; -wire [31:0] apb3_prdata; -wire apb3_pslverror; -//Mac APB3 Interface -wire [9:0] mac_apb3_paddr; -wire mac_apb3_psel; -wire mac_apb3_penable; -wire mac_apb3_pready; -wire mac_apb3_pwrite; -wire [31:0] mac_apb3_pwdata; -wire [31:0] mac_apb3_prdata; -wire mac_apb3_pslverror; -//Ex APB3 Interface -wire [9:0] ex_apb3_paddr; -wire ex_apb3_psel; -wire ex_apb3_penable; -wire ex_apb3_pready; -wire ex_apb3_pwrite; -wire [31:0] ex_apb3_pwdata; -wire [31:0] ex_apb3_prdata; -wire ex_apb3_pslverror; -//AXI4-Lite Interface -wire [9:0] axi_awaddr; -wire axi_awvalid; -wire axi_awready; -wire [31:0] axi_wdata; -wire axi_wvalid; -wire axi_wready; -wire [1:0] axi_bresp; -wire axi_bvalid; -wire axi_bready; -wire [9:0] axi_araddr; -wire axi_arvalid; -wire axi_arready; -wire [1:0] axi_rresp; -wire [31:0] axi_rdata; -wire axi_rvalid; -wire axi_rready; -//Cfg Space Registers -wire mac_sw_rst; -wire axi4_st_mux_select; -wire pat_mux_select; -wire udp_pat_gen_en; -wire mac_pat_gen_en; -wire [15:0] pat_gen_num; -wire [15:0] pat_gen_ipg; -wire [47:0] pat_dst_mac; -wire [47:0] pat_src_mac; -wire [15:0] pat_mac_dlen; -wire [31:0] pat_src_ip; -wire [31:0] pat_dst_ip; -wire [15:0] pat_src_port; -wire [15:0] pat_dst_port; -wire [15:0] pat_udp_dlen; - -//TSE DDIO -`ifdef TITANIUM - wire rgmii_rxc; - - assign rgmii_rxc = mux_clk; -`else - wire rgmii_rx_ctl_LO; - wire rgmii_rx_ctl_HI; - wire rgmii_tx_ctl_LO; - wire rgmii_tx_ctl_HI; - - assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ; - assign rgmii_rx_ctl_HI = rgmii_rx_ctl ; - assign rgmii_rx_ctl_LO = rgmii_rx_ctl ; -`endif -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -assign pll_rstn = 1; -/*----------------------- Clock Region -----------------------*/ -//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above. -//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has -//high combi logic and couldn't meet timing at 125Mhz. -assign rx_axis_clk = clk;//clk_125m; -assign tx_axis_clk = clk;//clk_125m; - - -/*----------------------- Reset Region -----------------------*/ -//assign pll_0_reset = 1'b0; -assign clk_50m = clk; -assign phy_rstn = sw6; -assign clk_50m_rstn = pll_0_locked; -assign mac_reset = ~pll_0_locked; -assign proto_reset = mac_sw_rst; -assign mac_rstn = ~(mac_reset || proto_reset); - -/*----------------------- MCU Module ----------------------------*/ -`ifndef SIM_MODE -sapphire u_mcu -( -//user custom ports - //SOC - .io_systemClk (clk_50m ), - .io_asyncReset (1'b0 ), - .system_uart_0_io_txd (system_uart_0_io_txd ), - .system_uart_0_io_rxd (system_uart_0_io_rxd ), - .system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ), - .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ), - .system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ), - .system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ), - .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ), - .system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ), - .system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ), - .system_spi_0_io_ss (system_spi_0_io_ss ), - .jtagCtrl_tck (jtag_inst1_TCK ), - .jtagCtrl_tdi (jtag_inst1_TDI ), - .jtagCtrl_tdo (jtag_inst1_TDO ), - .jtagCtrl_enable (jtag_inst1_SEL ), - .jtagCtrl_capture (jtag_inst1_CAPTURE ), - .jtagCtrl_shift (jtag_inst1_SHIFT ), - .jtagCtrl_update (jtag_inst1_UPDATE ), - .jtagCtrl_reset (jtag_inst1_RESET ), -//APB3 Master Interface - .io_apbSlave_0_PADDR (apb3_paddr ), - .io_apbSlave_0_PSEL (apb3_psel ), - .io_apbSlave_0_PENABLE (apb3_penable ), - .io_apbSlave_0_PREADY (apb3_pready ), - .io_apbSlave_0_PWRITE (apb3_pwrite ), - .io_apbSlave_0_PWDATA (apb3_pwdata ), - .io_apbSlave_0_PRDATA (apb3_prdata ), - .io_apbSlave_0_PSLVERROR (apb3_pslverror ) -); -`endif - -assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready; -assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata; -assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror; - -assign mac_apb3_paddr = apb3_paddr[9:0]; -assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0; -assign mac_apb3_penable = apb3_penable; -assign mac_apb3_pwrite = apb3_pwrite; -assign mac_apb3_pwdata = apb3_pwdata; - -assign ex_apb3_paddr = apb3_paddr[9:0]; -assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0; -assign ex_apb3_penable = apb3_penable; -assign ex_apb3_pwrite = apb3_pwrite; -assign ex_apb3_pwdata = apb3_pwdata; - -apb3_2_axi4_lite#( - .ADDR_WTH (10 ) -) -u_apb3_2_axi4_lite -( -//Globle Signals - .clk (clk_50m ), - .rstn (clk_50m_rstn ), -//APB3 Slave Interface - .s_apb3_paddr (mac_apb3_paddr ), - .s_apb3_psel (mac_apb3_psel ), - .s_apb3_penable (mac_apb3_penable ), - .s_apb3_pready (mac_apb3_pready ), - .s_apb3_pwrite (mac_apb3_pwrite ), - .s_apb3_pwdata (mac_apb3_pwdata ), - .s_apb3_prdata (mac_apb3_prdata ), - .s_apb3_pslverror (mac_apb3_pslverror ), -//AXI4-Lite Master Interface - .m_axi_awaddr (axi_awaddr ), - .m_axi_awvalid (axi_awvalid ), - .m_axi_awready (axi_awready ), - .m_axi_wdata (axi_wdata ), - .m_axi_wvalid (axi_wvalid ), - .m_axi_wready (axi_wready ), - .m_axi_bresp (axi_bresp ), - .m_axi_bvalid (axi_bvalid ), - .m_axi_bready (axi_bready ), - .m_axi_araddr (axi_araddr ), - .m_axi_arvalid (axi_arvalid ), - .m_axi_arready (axi_arready ), - .m_axi_rresp (axi_rresp ), - .m_axi_rdata (axi_rdata ), - .m_axi_rvalid (axi_rvalid ), - .m_axi_rready (axi_rready ) -); - -reg_apb3#( - .ADDR_WTH (10 ) -) -u_reg_apb3 -( -//Globle Signals -// -//APB3 Slave Interface - .s_apb3_clk (clk_50m ), - .s_apb3_rstn (clk_50m_rstn ), - .s_apb3_paddr (ex_apb3_paddr ), - .s_apb3_psel (ex_apb3_psel ), - .s_apb3_penable (ex_apb3_penable ), - .s_apb3_pready (ex_apb3_pready ), - .s_apb3_pwrite (ex_apb3_pwrite ), - .s_apb3_pwdata (ex_apb3_pwdata ), - .s_apb3_prdata (ex_apb3_prdata ), - .s_apb3_pslverror (ex_apb3_pslverror ), -//Cfg Space Registers -//--Example Registers Field - .mac_sw_rst (mac_sw_rst ), - .axi4_st_mux_select (axi4_st_mux_select ), - .pat_mux_select (pat_mux_select ), - .udp_pat_gen_en (udp_pat_gen_en ), - .mac_pat_gen_en (mac_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), - .pat_dst_mac (pat_dst_mac ), - .pat_src_mac (pat_src_mac ), - .pat_mac_dlen (pat_mac_dlen ), - .pat_src_ip (pat_src_ip ), - .pat_dst_ip (pat_dst_ip ), - .pat_src_port (pat_src_port ), - .pat_dst_port (pat_dst_port ), - .pat_udp_dlen (pat_udp_dlen ), - .clkmux_sel (mux_clk_sw ) -); - -//generate if (PATTERN_TYPE == 0) begin //UDP -// -//assign mac_tx_axis_mac_tdata = 8'h0; -//assign mac_tx_axis_mac_tvalid = 1'b0; -//assign mac_tx_axis_mac_tlast = 1'b0; - -/*----------------------- The Ethernet Pattern Module -----------------------*/ -udp_pat_gen u_udp_pat_gen -( -//Globle Signals - .clk (tx_axis_clk ), - .rstn (mac_rstn ), -//Control Interface - .pat_gen_en (udp_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), -//MAC Protocol Signals - .dst_mac (pat_dst_mac ), - .src_mac (pat_src_mac ), -//IP Protocol Signals - .src_ip (pat_src_ip ), - .dst_ip (pat_dst_ip ), -//UDP Protocol Signals - .src_port (pat_src_port ), - .dst_port (pat_dst_port ), - .udp_dlen (pat_udp_dlen ), -//AXI4-Stream Interface - .rclk (rx_axis_clk ), - .rrstn (mac_rstn ), - .rdata (rx_axis_mac_tdata ), - .rvalid (rx_axis_mac_tvalid ), - .rlast (rx_axis_mac_tlast ), - .tdata (udp_tx_axis_mac_tdata ), - .tvalid (udp_tx_axis_mac_tvalid ), - .tlast (udp_tx_axis_mac_tlast ), - .tready (udp_tx_axis_mac_tready ) -); -//end -//else begin //MAC -// -//assign udp_tx_axis_mac_tdata = 8'h0; -//assign udp_tx_axis_mac_tvalid = 1'b0; -//assign udp_tx_axis_mac_tlast = 1'b0; - -mac_pat_gen u_mac_pat_gen -( -//Globle Signals - .clk (tx_axis_clk ), - .rstn (mac_rstn ), -//Control Interface - .pat_gen_en (mac_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), -//MAC Protocol Signals - .dst_mac (pat_dst_mac ), - .src_mac (pat_src_mac ), - .mac_dlen (pat_mac_dlen ), -//AXI4-Stream Interface - .rclk (rx_axis_clk ), - .rrstn (mac_rstn ), - .rdata (rx_axis_mac_tdata ), - .rvalid (rx_axis_mac_tvalid ), - .rlast (rx_axis_mac_tlast ), - .tdata (mac_tx_axis_mac_tdata ), - .tvalid (mac_tx_axis_mac_tvalid ), - .tlast (mac_tx_axis_mac_tlast ), - .tready (mac_tx_axis_mac_tready ) -); -//end -//endgenerate - -axi4_st_mux u_pat_mux -( -//Globle Signals - .mux_select (pat_mux_select ),//0:udp pat; 1:mac pat; -//Mux In 0 Interface - .tdata0 (udp_tx_axis_mac_tdata ), - .tvalid0 (udp_tx_axis_mac_tvalid ), - .tlast0 (udp_tx_axis_mac_tlast ), - .tuser0 (1'b0 ), - .tready0 (udp_tx_axis_mac_tready ), -//Mux In 1 Interface - .tdata1 (mac_tx_axis_mac_tdata ), - .tvalid1 (mac_tx_axis_mac_tvalid ), - .tlast1 (mac_tx_axis_mac_tlast ), - .tuser1 (1'b0 ), - .tready1 (mac_tx_axis_mac_tready ), -//Mux Out Interface - .tdata (pat_tx_axis_mac_tdata ), - .tvalid (pat_tx_axis_mac_tvalid ), - .tlast (pat_tx_axis_mac_tlast ), - .tuser (pat_tx_axis_mac_tuser ), - .tready (pat_tx_axis_mac_tready ) -); - -/*----------------------- The Tx AXI4 St Mux Module -----------------------*/ -axi4_st_mux u_tx_axi4st_mux -( -//Globle Signals - .mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback; -//Mux In 0 Interface - .tdata0 (pat_tx_axis_mac_tdata ), - .tvalid0 (pat_tx_axis_mac_tvalid ), - .tlast0 (pat_tx_axis_mac_tlast ), - .tuser0 (pat_tx_axis_mac_tuser ), - .tready0 (pat_tx_axis_mac_tready ), -//Mux In 1 Interface - .tdata1 (loop_tx_axis_mac_tdata ), - .tvalid1 (loop_tx_axis_mac_tvalid ), - .tlast1 (loop_tx_axis_mac_tlast ), - .tuser1 (loop_tx_axis_mac_tuser ), - .tready1 (loop_tx_axis_mac_tready ), -//Mux Out Interface - .tdata (tx_axis_mac_tdata ), - .tvalid (tx_axis_mac_tvalid ), - .tlast (tx_axis_mac_tlast ), - .tuser (tx_axis_mac_tuser ), - .tready (tx_axis_mac_tready ) -); - -/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/ -gTSE u_tsemac -( -//Globle Signals - .mac_reset (mac_reset ), - .proto_reset (proto_reset ), - .tx_mac_aclk (clk_125m ), - .rx_mac_aclk ( ), - .eth_speed ( ), -//Receive AXI4-Stream Interface - .rx_axis_clk (rx_axis_clk ), - .rx_axis_mac_tdata (rx_axis_mac_tdata ), - .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), - .rx_axis_mac_tlast (rx_axis_mac_tlast ), - .rx_axis_mac_tstrb (), - .rx_axis_mac_tuser (rx_axis_mac_tuser ), - .rx_axis_mac_tready (rx_axis_mac_tready ), -//Transmit AXI4-Stream Interface - .tx_axis_clk (tx_axis_clk ), - .tx_axis_mac_tdata (tx_axis_mac_tdata ), - .tx_axis_mac_tvalid (tx_axis_mac_tvalid ), - .tx_axis_mac_tlast (tx_axis_mac_tlast ), - .tx_axis_mac_tstrb (1'b1 ), - .tx_axis_mac_tuser (tx_axis_mac_tuser ), - .tx_axis_mac_tready (tx_axis_mac_tready ), - //--RGMII Interface - .rgmii_txd_HI (rgmii_txd_HI ), - .rgmii_txd_LO (rgmii_txd_LO ), - .rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ), - .rgmii_txc_HI (rgmii_txc_HI ), - .rgmii_txc_LO (rgmii_txc_LO ), - .rgmii_rxd_HI (rgmii_rxd_HI ), - .rgmii_rxd_LO (rgmii_rxd_LO ), - .rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ), - .rgmii_rxc (rgmii_rxc ), - //AXI4-Lite Interface - .s_axi_aclk (clk_50m ), - .s_axi_awaddr (axi_awaddr ), - .s_axi_awvalid (axi_awvalid ), - .s_axi_awready (axi_awready ), - .s_axi_wdata (axi_wdata ), - .s_axi_wvalid (axi_wvalid ), - .s_axi_wready (axi_wready ), - .s_axi_bresp (axi_bresp ), - .s_axi_bvalid (axi_bvalid ), - .s_axi_bready (axi_bready ), - .s_axi_araddr (axi_araddr ), - .s_axi_arvalid (axi_arvalid ), - .s_axi_arready (axi_arready ), - .s_axi_rresp (axi_rresp ), - .s_axi_rdata (axi_rdata ), - .s_axi_rvalid (axi_rvalid ), - .s_axi_rready (axi_rready ), - //MDIO Interface - .Mdo (phy_mdo ), - .MdoEn (phy_mdo_en ), - .Mdi (phy_mdi ), - .Mdc (phy_mdc ) -); - -/*----------------------- User Interface Loopback Module ----------------------------*/ -mac_rx2tx u_mac_rx2tx -( -//Globle Signals -// -//Receive AXI4-Stream Interface - .rx_axis_clk (rx_axis_clk ), - .rx_axis_rstn (mac_rstn ), - .rx_axis_mac_tdata (rx_axis_mac_tdata ), - .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), - .rx_axis_mac_tlast (rx_axis_mac_tlast ), - .rx_axis_mac_tuser (rx_axis_mac_tuser ), - .rx_axis_mac_tready (rx_axis_mac_tready ), -//Transmit AXI4-Stream Interface - .tx_axis_clk (tx_axis_clk ), - .tx_axis_rstn (mac_rstn ), - .tx_axis_mac_tdata (loop_tx_axis_mac_tdata ), - .tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ), - .tx_axis_mac_tlast (loop_tx_axis_mac_tlast ), - .tx_axis_mac_tuser (loop_tx_axis_mac_tuser ), - .tx_axis_mac_tready (loop_tx_axis_mac_tready ) -); - -endmodule - diff --git a/fpga/ip/gTSE/Testbench/udp_pat_gen.v b/fpga/ip/gTSE/Testbench/udp_pat_gen.v deleted file mode 100644 index e5626c3..0000000 --- a/fpga/ip/gTSE/Testbench/udp_pat_gen.v +++ /dev/null @@ -1,497 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module udp_pat_gen -( -//Globle Signals -input clk, -input rstn, -//Control Interface -input pat_gen_en, -input [15:0] pat_gen_num,//When value is 0, it's infinite mode -input [15:0] pat_gen_ipg, -//MAC Protocol Signals -input [47:0] dst_mac, -input [47:0] src_mac, -//IP Protocol Signals -input [31:0] src_ip, -input [31:0] dst_ip, -//UDP Protocol Signals -input [15:0] udp_dlen, -input [15:0] src_port, -input [15:0] dst_port, -//AXI4-Stream Interface -input rclk, -input rrstn, -input [7:0] rdata, -input rvalid, -input rlast, - -output reg [7:0] tdata, -output reg tvalid, -output reg tlast, -input tready -); - -// Parameter Define -localparam VER = 4'h4;//IPv4 -localparam IHL = 4'h5;//Internet Header Length -localparam TOS = 8'h0;//Type Of Service -localparam FLG = 3'h0;//Flags -localparam TTL = 8'h40;//Time To Live -localparam PTC = 8'h11;//UDP Protocol - -localparam IDLE = 3'h0; -localparam UDP_CHKSUM = 3'h1; -localparam IP_CHKSUM = 3'h2; -localparam PAT_IPG = 3'h3; -localparam PAT_GEN = 3'h4; - -// Register Define -reg [2:0] cur_state; -reg [2:0] next_state; -reg pat_gen_en_dl1; -reg pat_gen_en_dl2; -reg [31:0] src_ip_r; -reg [31:0] dst_ip_r; -reg [15:0] src_port_r; -reg [15:0] dst_port_r; -reg pat_en; -reg infinite_en; -reg [15:0] num_cnt; -reg [15:0] udp_chksum_cnt; -reg [3:0] ip_chksum_cnt; -reg [15:0] ipg_cnt; -reg [15:0] pat_cnt; -reg [15:0] udp_len; -reg [15:0] udp_chksum_num; -reg [7:0] udp_data_h; -reg [7:0] udp_data_l; -reg [16:0] udp_chksum_r; -reg [15:0] udp_chksum; -reg [15:0] ip_len; -reg [15:0] ip_id; -reg [12:0] ip_ofs; -reg [16:0] ip_chksum_r; -reg [15:0] ip_chksum; - -reg [15:0] pat_gen_num_r; -reg [15:0] pat_gen_ipg_r; -reg [47:0] dst_mac_r; -reg [47:0] src_mac_r; -reg [15:0] udp_dlen_r; - -// Wire Define -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) begin - pat_gen_num_r <= 16'h0; - pat_gen_ipg_r <= 16'h0; - dst_mac_r <= 48'h0; - src_mac_r <= 48'h0; - udp_dlen_r <= 16'h0; - end - else begin - pat_gen_num_r <= pat_gen_num; - pat_gen_ipg_r <= pat_gen_ipg; - dst_mac_r <= dst_mac; - src_mac_r <= src_mac; - udp_dlen_r <= udp_dlen; - end -end - -/*----------------------- FSM Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - cur_state <= IDLE; - else - cur_state <= next_state; -end - -always @(*) - begin - case(cur_state) - IDLE : - if(pat_en == 1'b1) - next_state = UDP_CHKSUM; - else - next_state = IDLE; - - UDP_CHKSUM : - if(udp_chksum_cnt == udp_chksum_num) - next_state = IP_CHKSUM; - else - next_state = UDP_CHKSUM; - - IP_CHKSUM : - if(ip_chksum_cnt == 4'd9) - next_state = PAT_GEN; - else - next_state = IP_CHKSUM; - - PAT_IPG : - if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) - next_state = IDLE; - else if(ipg_cnt == pat_gen_ipg_r) - next_state = IP_CHKSUM; - else - next_state = PAT_IPG; - - PAT_GEN : - if((tlast == 1'b1) && (tready == 1'b1)) - next_state = PAT_IPG; - else - next_state = PAT_GEN; - - default : - next_state = IDLE; - endcase - end - -/*----------------------- Generator Control Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - pat_gen_en_dl1 <= 1'h0; - pat_gen_en_dl2 <= 1'h0; - end - else - begin - pat_gen_en_dl1 <= pat_gen_en; - pat_gen_en_dl2 <= pat_gen_en_dl1; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - src_ip_r <= 32'h0; - dst_ip_r <= 32'h0; - src_port_r <= 16'h0; - dst_port_r <= 16'h0; - end - else - begin - src_ip_r <= src_ip; - dst_ip_r <= dst_ip; - src_port_r <= src_port; - dst_port_r <= dst_port; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - pat_en <= 1'h1; - else if((cur_state == IDLE) && (pat_en == 1'b1)) - pat_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - infinite_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) - infinite_en <= 1'h1; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - infinite_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - num_cnt <= 16'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - num_cnt <= pat_gen_num_r; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) - num_cnt <= num_cnt - 1'b1; -end - -/*----------------------- UDP Protocol Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_len <= 16'h0; - else - udp_len <= udp_dlen_r + 16'd8; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_num <= 16'h0; - else if(udp_dlen_r[0] == 1'b1) - udp_chksum_num <= udp_dlen_r[15:1] + 16'd10; - else - udp_chksum_num <= udp_dlen_r[15:1] + 16'd9; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - udp_data_h <= 8'h0; - udp_data_l <= 8'h0; - end - else if(cur_state == IDLE) - begin - udp_data_h <= 8'h0; - udp_data_l <= 8'h1; - end - else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9)) - begin - udp_data_h <= udp_data_h + 8'h2; - udp_data_l <= udp_data_l + 8'h2; - end -end - -//udp checksum calculate -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_r <= 17'h0; - else if(cur_state == IDLE) - udp_chksum_r <= 17'h0; - else if(cur_state == UDP_CHKSUM) begin - if (udp_chksum_cnt <= 16'd8) begin - case(udp_chksum_cnt[3:0]) - 4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16]; - 4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16]; - 4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16]; - 4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16]; - 4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16]; - 4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; - 4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16]; - 4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16]; - 4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; - default : udp_chksum_r <= 17'h0; - endcase - end - else begin - if(udp_chksum_cnt == udp_chksum_num) - udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16]; - else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1)) - udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16]; - else - udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16]; - end - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum <= 16'h0; - else - udp_chksum <= ~udp_chksum_r[15:0]; -end - -/*----------------------- IP Protocol Region ----------------------------*/ -//IP Frame Total Length -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_len <= 16'h0; - else - ip_len <= udp_len + 16'd20; -end - -//IP Frame Identification -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_id <= 16'h0; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1)) - ip_id <= ip_id + 1'b1; -end - -//IP Frame Fragment Offset -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum <= 16'h0; - else - ip_chksum <= ~ip_chksum_r[15:0]; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_ofs <= 13'h0; -end - -//ip checksum calculate -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum_r <= 16'h0; - else if(cur_state == IDLE) - ip_chksum_r <= 16'h0; - else if(cur_state == IP_CHKSUM) begin - case(ip_chksum_cnt) - 4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16]; - 4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16]; - 4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16]; - 4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16]; - 4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16]; - 4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16]; - 4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16]; - 4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16]; - 4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16]; - 4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16]; - endcase - end - else if(cur_state == PAT_IPG) - ip_chksum_r <= 16'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum <= 16'h0; - else - ip_chksum <= ~ip_chksum_r[15:0]; -end - -/*----------------------- Pattern Counter Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_cnt <= 16'h0; - else if(cur_state == UDP_CHKSUM) - udp_chksum_cnt <= udp_chksum_cnt + 1'b1; - else - udp_chksum_cnt <= 16'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum_cnt <= 4'h0; - else if(cur_state == IP_CHKSUM) - ip_chksum_cnt <= ip_chksum_cnt + 1'b1; - else - ip_chksum_cnt <= 4'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ipg_cnt <= 16'h0; - else if(cur_state == PAT_IPG) - ipg_cnt <= ipg_cnt + 1'b1; - else - ipg_cnt <= 8'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_cnt <= 16'h0; - else if(cur_state != PAT_GEN) - pat_cnt <= 16'h0; - else if(tready == 1'b1) - pat_cnt <= pat_cnt + 1'b1; -end - -/*----------------------- Pattern Generator Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tvalid <= 1'b0; - else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) - tvalid <= 1'b1; - else if((tready == 1'b1) && (tlast == 1'b1)) - tvalid <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tdata <= 8'h0; - else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42)) - case(pat_cnt[5:0]) - 6'd0 : tdata <= dst_mac_r[5*8 +: 8]; - 6'd1 : tdata <= dst_mac_r[4*8 +: 8]; - 6'd2 : tdata <= dst_mac_r[3*8 +: 8]; - 6'd3 : tdata <= dst_mac_r[2*8 +: 8]; - 6'd4 : tdata <= dst_mac_r[1*8 +: 8]; - 6'd5 : tdata <= dst_mac_r[0*8 +: 8]; - 6'd6 : tdata <= src_mac_r[5*8 +: 8]; - 6'd7 : tdata <= src_mac_r[4*8 +: 8]; - 6'd8 : tdata <= src_mac_r[3*8 +: 8]; - 6'd9 : tdata <= src_mac_r[2*8 +: 8]; - 6'd10 : tdata <= src_mac_r[1*8 +: 8]; - 6'd11 : tdata <= src_mac_r[0*8 +: 8]; - 6'd12 : tdata <= 8'h08; - 6'd13 : tdata <= 8'h00; - 6'd14 : tdata <= {VER,IHL}; - 6'd15 : tdata <= TOS; - 6'd16 : tdata <= ip_len[15:8]; - 6'd17 : tdata <= ip_len[7:0]; - 6'd18 : tdata <= ip_id[15:8]; - 6'd19 : tdata <= ip_id[7:0]; - 6'd20 : tdata <= {FLG,ip_ofs[12:8]}; - 6'd21 : tdata <= ip_ofs[7:0]; - 6'd22 : tdata <= TTL; - 6'd23 : tdata <= PTC; - 6'd24 : tdata <= ip_chksum[15:8]; - 6'd25 : tdata <= ip_chksum[7:0]; - 6'd26 : tdata <= src_ip_r[3*8 +: 8]; - 6'd27 : tdata <= src_ip_r[2*8 +: 8]; - 6'd28 : tdata <= src_ip_r[1*8 +: 8]; - 6'd29 : tdata <= src_ip_r[0*8 +: 8]; - 6'd30 : tdata <= dst_ip_r[3*8 +: 8]; - 6'd31 : tdata <= dst_ip_r[2*8 +: 8]; - 6'd32 : tdata <= dst_ip_r[1*8 +: 8]; - 6'd33 : tdata <= dst_ip_r[0*8 +: 8]; - 6'd34 : tdata <= src_port_r[15:8]; - 6'd35 : tdata <= src_port_r[7:0]; - 6'd36 : tdata <= dst_port_r[15:8]; - 6'd37 : tdata <= dst_port_r[7:0]; - 6'd38 : tdata <= udp_len[15:8]; - 6'd39 : tdata <= udp_len[7:0]; - 6'd40 : tdata <= udp_chksum[15:8]; - 6'd41 : tdata <= udp_chksum[7:0]; - 6'd42 : tdata <= 8'h0;//UDP First Data - default : tdata <= tdata + 1'b1; - endcase - else if((cur_state == PAT_GEN) && (tready == 1'b1)) - tdata <= tdata + 1'b1; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tlast <= 1'b0; - else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13)) - tlast <= 1'b1; - else if(tready == 1'b1) - tlast <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/DaulClkFifo.v b/fpga/ip/gTSE/Ti60F225_devkit/DaulClkFifo.v deleted file mode 100644 index 7d34961..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/DaulClkFifo.v +++ /dev/null @@ -1,498 +0,0 @@ - -`timescale 1ns/100ps - -module DC_FIFO -# ( - parameter FIFO_MODE = "Normal" , //"Normal"; //"ShowAhead" - parameter DATA_WIDTH = 8 , - parameter FIFO_DEPTH = 512 , - - parameter AW_C = $clog2(FIFO_DEPTH), - parameter DW_C = DATA_WIDTH , - parameter DD_C = 2**AW_C - ) -( - //System Signal - input Reset , //System Reset - //Write Signal - input WrClk , //(I)Wirte Clock - input WrEn , //(I)Write Enable - output [AW_C-1:0] WrDNum , //(O)Write Data Number In Fifo - output WrFull , //(I)Write Full - input [DW_C -1:0] WrData , //(I)Write Data - //Read Signal - input RdClk , //(I)Read Clock - input RdEn , //(I)Read Enable - output [AW_C-1:0] RdDNum , //(O)Radd Data Number In Fifo - output RdEmpty , //(O)Read FifoEmpty - output [DW_C-1 :0] RdData //(O)Read Data -); - -//Define Parameter -/////////////////////////////////////////////////////////////// - localparam TCo_C = 0 ; - - reg [1:0] WrClkRstGen = 2'h3; - reg [1:0] RdClkRstGen = 2'h3; - - always @( posedge WrClk or posedge Reset) - begin - if (Reset) WrClkRstGen <= # TCo_C 2'h3; - else - begin - WrClkRstGen[0] <= # TCo_C 1'h0; - WrClkRstGen[1] <= # TCo_C (&RdClkRstGen); - end - end - - wire WrClkRst = WrClkRstGen[1]; - - /////////////////////////////////////////////////// - always @( posedge RdClk or posedge Reset) - begin - if (Reset) RdClkRstGen <= # TCo_C 2'h3; - else - begin - RdClkRstGen[0] <= # TCo_C 1'h0; - RdClkRstGen[1] <= # TCo_C (&WrClkRstGen); - end - end - - wire RdClkRst = RdClkRstGen[1]; - - /////////////////////////////////////////////////// - wire FifoWrEn = WrEn; - wire [AW_C :0] WrAddrCnt ; - wire [AW_C :0] FifoWrAddr ; - wire FifoWrFull ; - - FifoAddrCnt # ( .CounterWidth_C (AW_C)) - U1_WrAddrCnt - ( - //System Signal - .Reset ( WrClkRst ) , //System Reset - .SysClk ( WrClk ) , //System Clock - //Counter Signal - .ClkEn ( FifoWrEn ) , //(I)Clock Enable - .FifoFlag ( FifoWrFull ) , //(I)Fifo Flag - .AddrCnt ( WrAddrCnt ) , //(O)Address Counter - .Addess ( FifoWrAddr ) //(O)Address Output - ); - - /////////////////////////////////////////////////// - reg [DW_C-1:0] FifoBuff [DD_C-1:0]; - - always @( posedge WrClk) - begin - if (WrEn & (~WrFull)) - begin - FifoBuff[FifoWrAddr[AW_C-1:0]] <= # TCo_C WrData; - end - end - - /////////////////////////////////////////////////// - - /////////////////////////////////////////////////// - wire FifoEmpty ; - wire FifoRdEn ; - - wire [AW_C :0] RdAddrCnt ; - wire [AW_C :0] FifoRdAddr ; - - FifoAddrCnt #( .CounterWidth_C (AW_C)) - U2_RdAddrCnt - ( - //System Signal - .Reset ( RdClkRst ) , //System Reset - .SysClk ( RdClk ) , //System Clock - //Counter Signal - .ClkEn ( FifoRdEn ) , //(I)Clock Enable - .FifoFlag ( FifoEmpty ) , //(I)Fifo Flag - .AddrCnt ( RdAddrCnt ) , //(O)Address Counter - .Addess ( FifoRdAddr ) //(O)Address Output - ); - - /////////////////////////////////////////////////// - reg [DW_C-1 :0] FifoRdData ; - - always @( posedge RdClk) - begin - if (FifoRdEn) FifoRdData <= # TCo_C FifoBuff[FifoRdAddr[AW_C-1:0]]; - end - - /////////////////////////////////////////////////// - assign RdData = FifoRdData ; //(O)Read Data - - reg [AW_C:0] WrRdAddr = {AW_C+1{1'h0}}; - - always @( posedge WrClk) - begin - if (WrClkRst) WrRdAddr <= # TCo_C {AW_C+1{1'h0}} ; - else WrRdAddr <= # TCo_C FifoRdAddr [AW_C:0] ; - end - - /////////////////////////////////////////////////////////// - wire [AW_C-1:0] WrRdAHex; - wire [AW_C-1:0] WrWrAHex; - - GrayDecode #(AW_C) WRAGray2Hex (WrRdAddr [AW_C-1:0] , WrRdAHex[AW_C-1:0]); - GrayDecode #(AW_C) WWAGray2Hex (FifoWrAddr [AW_C-1:0] , WrWrAHex[AW_C-1:0]); - - /////////////////////////////////////////////////////////// - reg [AW_C-1:0] WrAddrDiff; - - always @( posedge WrClk) - begin - if (WrFull) WrAddrDiff <= # TCo_C {AW_C{1'h1}} ; - else WrAddrDiff <= # TCo_C (WrWrAHex - WrRdAHex) ; - end - - /////////////////////////////////////////////////////////// - assign WrDNum = WrAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo - - reg [AW_C:0] WrRdAddrReg = {AW_C+1{1'h0}}; - - always @( posedge WrClk) - begin - if ( WrClkRst) WrRdAddrReg <= # TCo_C {AW_C+1{1'h0}} ; - else WrRdAddrReg <= # TCo_C WrRdAddr[AW_C : 0] ; - end - - /////////////////////////////////////////////////////////// - reg RdAddrChg = 1'h0; - reg WrFullClr = 1'h0; - - always @( posedge WrClk) - begin - if ( WrClkRst) RdAddrChg <= # TCo_C 1'h0 ; - else RdAddrChg <= # TCo_C (FifoWrFull & (WrRdAddr[AW_C-1:0] != WrRdAddrReg[AW_C-1:0])); - end - - always @( posedge WrClk) - begin - if ( WrClkRst) WrFullClr <= # TCo_C 1'h0 ; - else WrFullClr <= # TCo_C (FifoWrFull & RdAddrChg); - end - - /////////////////////////////////////////////////////////// - reg RdAHighNext = 1'h0; - - wire RdAHighRise = (~WrRdAddrReg[AW_C-1]) & WrRdAddr[AW_C-1]; - - always @( posedge WrClk) - begin - if (WrClkRst ) RdAHighNext <= # TCo_C 1'h0 ; - else if (RdAHighRise) RdAHighNext <= # TCo_C (~WrRdAddr[AW_C]) ; - end - - /////////////////////////////////////////////////// - wire FullCalc = (WrAddrCnt[AW_C-1:0] == WrRdAddr[AW_C-1:0]) - && (WrAddrCnt[AW_C ] != (WrRdAddr[AW_C-1] ? WrRdAddrReg[AW_C] : RdAHighNext) ); - - /////////////////////////////////////////////////// - reg FullFlag = 1'h0; - - always @( posedge WrClk) - begin - if (WrClkRst) FullFlag <= # TCo_C 1'h0; - else if (FullFlag) FullFlag <= # TCo_C (~WrFullClr); - else if (FifoWrEn) FullFlag <= # TCo_C FullCalc; - end - - assign FifoWrFull = FullFlag; - - /////////////////////////////////////////////////// - assign WrFull = FifoWrFull ; //(I)Write Full - - reg [AW_C :0] RdWrAddr = {AW_C+1{1'h0}}; - - always @( posedge RdClk) - begin - if (RdClkRst ) RdWrAddr <= # TCo_C {AW_C+1{1'h0}} ; - else RdWrAddr <= # TCo_C FifoWrAddr [AW_C:0] ; - end - - /////////////////////////////////////////////////////////// - wire [AW_C-1:0] RdWrAHex; - wire [AW_C-1:0] RdRdAHex; - - GrayDecode # (AW_C) RWAGray2Hex (RdWrAddr [AW_C-1:0] , RdWrAHex[AW_C-1:0] ); - GrayDecode # (AW_C) RRAGray2Hex (FifoRdAddr [AW_C-1:0] , RdRdAHex[AW_C-1:0] ); - - /////////////////////////////////////////////////////////// - reg [AW_C-1:0] RdAddrDiff; - - always @( posedge RdClk) - begin - if (RdEmpty ) RdAddrDiff <= # TCo_C {AW_C{1'h0}} ; - else RdAddrDiff <= # TCo_C (RdWrAHex - RdRdAHex) ; - end - - /////////////////////////////////////////////////////////// - assign RdDNum = RdAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo - - reg [AW_C:0] RdWrAddrReg = {AW_C+1{1'h0}}; - - always @( posedge RdClk) - begin - if (RdClkRst) RdWrAddrReg <= # TCo_C {AW_C+1{1'h0}} ; - else RdWrAddrReg <= # TCo_C RdWrAddr [AW_C:0] ; - end - - /////////////////////////////////////////////////////////// - reg WrAddrChg = 1'h0; - reg EmptyClr = 1'h0; - - always @( posedge RdClk) - begin - if (RdClkRst) WrAddrChg <= # TCo_C 1'h0 ; - else WrAddrChg <= # TCo_C FifoEmpty & (RdWrAddr[AW_C-1:0] != RdWrAddrReg[AW_C-1:0]); - end - always @( posedge RdClk) - begin - if (RdClkRst) EmptyClr <= # TCo_C 1'h0; - else EmptyClr <= # TCo_C (FifoEmpty & WrAddrChg); - end - - /////////////////////////////////////////////////////////// - reg WrAHighNext = 1'h0; - - wire WrAHighRise = (~RdWrAddrReg[AW_C-1]) & RdWrAddr[AW_C-1]; - - always @( posedge RdClk) - begin - if (RdClkRst) WrAHighNext <= # TCo_C 1'h0 ; - else if (WrAHighRise) WrAHighNext <= # TCo_C (~RdWrAddr[AW_C]); - end - - /////////////////////////////////////////////////////////// - wire EmptyCalc = (RdAddrCnt[AW_C-1:0] == RdWrAddr[AW_C-1:0]) - && (RdAddrCnt[AW_C ] == (RdWrAddr[AW_C-1] ? RdWrAddrReg[AW_C] : WrAHighNext)); - - /////////////////////////////////////////////////////////// - reg EmptyFlag = 1'h1; - - always @( posedge RdClk) - begin - if (RdClkRst) EmptyFlag <= # TCo_C 1'h1; - else if (EmptyFlag) EmptyFlag <= # TCo_C (~EmptyClr); - else if (FifoRdEn) EmptyFlag <= # TCo_C EmptyCalc; - end - - assign FifoEmpty = EmptyFlag; - - /////////////////////////////////////////////////////////// - reg EmptyReg = 1'h0; - - always @( posedge RdClk ) - begin - if (RdClkRst) EmptyReg <= # TCo_C 1'h1; - else if (FifoRdEn) EmptyReg <= # TCo_C FifoEmpty; - end - - /////////////////////////////////////////////////////////// - assign RdEmpty = (FIFO_MODE == "ShowAhead") ? EmptyReg : FifoEmpty; //(O)Read FifoEmpty - - reg RdFirst = 1'h0; - - always @( posedge RdClk) - begin - if (FIFO_MODE == "ShowAhead") - begin - if (RdClkRst) RdFirst <= # TCo_C 1'h0 ; - else if (RdFirst) RdFirst <= # TCo_C 1'h0 ; - else if (EmptyClr) RdFirst <= # TCo_C RdEmpty ; - end - else RdFirst <= # TCo_C 1'h0 ; - end - - /////////////////////////////////////////////////////////// - assign FifoRdEn = RdEn || RdFirst ; - - /////////////////////////////////////////////////////////// - -//666666666666666666666666666666666666666666666666666666666 - -endmodule - -//////////////// DaulClkFifo ////////////////////////////// - -///////////////// FifoAddrCnt ///////////////////////////// - -module FifoAddrCnt -# ( - parameter CounterWidth_C = 9 , - parameter CW_C = CounterWidth_C - ) -( - //System Signal - input Reset , //System Reset - input SysClk , //System Clock - //Counter Signal - input ClkEn , //(I)Clock Enable - input FifoFlag , //(I)Fifo Flag - output [CW_C:0] AddrCnt , //(O)Address Counter - output [CW_C:0] Addess //(O)Address Output -); - -//Define Parameter -/////////////////////////////////////////////////////////// -localparam TCo_C = 1; - - wire [CW_C-1:0] GrayAddrCnt; - wire CarryOut; - - GrayCnt #(.CounterWidth_C (CW_C)) - U1_AddrCnt - ( - //System Signal - .Reset ( Reset ), //System Reset - .SysClk ( SysClk ), //System Clock - //Counter Signal - .SyncClr ( 1'h0 ), //(I)Sync Clear - .ClkEn ( ClkEn ), //(I)Clock Enable - .CarryIn ( ~FifoFlag ), //(I)Carry input - .CarryOut ( CarryOut ), //(O)Carry output - .Count ( GrayAddrCnt ) //(O)Counter Value Output - ); - -/////////////////////////////////////////////////////////// - reg CntHighBit; - - always @( posedge SysClk ) - begin - if (Reset) CntHighBit <= # TCo_C 1'h0; - else if (ClkEn) CntHighBit <= # TCo_C CntHighBit + CarryOut; - end - -/////////////////////////////////////////////////////////// - reg [CW_C:0] AddrOut; //(O)Address Output - - always @(posedge SysClk) - begin - if (Reset) AddrOut <= # TCo_C {CW_C{1'h0}}; - else if (ClkEn) AddrOut <= # TCo_C FifoFlag ? AddrOut : AddrCnt; - end - -/////////////////////////////////////////////////////////// - assign AddrCnt = {CntHighBit , GrayAddrCnt} ; //(O)Address Counter - assign Addess = AddrOut ; //(O)Address Output - -//111111111111111111111111111111111111111111111111111111111 - -endmodule - -/////////////////// FifoAddrCnt ////////////////////////// - -module GrayCnt -# ( - parameter CounterWidth_C = 9 , - parameter CW_C = CounterWidth_C - ) -( - //System Signal - input Reset , //System Reset - input SysClk , //System Clock - //Counter Signal - input SyncClr , //(I)Sync Clear - input ClkEn , //(I)Clock Enable - input CarryIn , //(I)Carry input - output CarryOut , //(O)Carry output - output [CW_C-1:0] Count //(O)Counter Value Output -); - -//Define Parameter -/////////////////////////////////////////////////////////// -localparam TCo_C = 1; - - wire [CW_C:0 ] CryIn ; - wire [CW_C-1:0] CryOut ; - - reg [CW_C-1:0] GrayCnt; - - assign CryIn[0] = CarryIn; - - genvar i; - generate - for(i=0;i1) ? 1'h0: 1'h1 ; - else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ; - else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i]; - end - - ////////////// - if (i==0) - begin - assign CryOut[0] = GrayCnt[0] && CarryIn; - assign CryIn [1] = ~GrayCnt[0] && CarryIn; - end - else - begin - assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]); - assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ; - end - end - - endgenerate - - wire GrayCarry = CryOut[CW_C-2]; - -/////////////////////////////////////////////////////////// - reg CntHigh = 1'h0; - - always @( posedge SysClk) - begin - if (Reset) CntHigh <= # TCo_C 1'h0; - else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry); - end - -/////////////////////////////////////////////////////////// - assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output - assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output - -/////////////////////////////////////////////////////////// - -//111111111111111111111111111111111111111111111111111111111 - -endmodule - -////////////////////// GrayCnt //////////////////////////// - -module GrayDecode -# ( - parameter DataWidht_C = 8 - ) -( - input [DataWidht_C-1:0] GrayIn, - output [DataWidht_C-1:0] HexOut -); - - //Define Parameter - /////////////////////////////////////////////////////////////// - parameter TCo_C = 1; - - localparam DW_C = DataWidht_C; - - /////////////////////////////////////////////////////////////// - reg [DW_C-1:0] Hex; - - integer i; - - always @ (GrayIn) - begin - Hex[DW_C-1]=GrayIn[DW_C-1]; - for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i]; - end - - assign HexOut = Hex; - - /////////////////////////////////////////////////////////////// - -endmodule - - - diff --git a/fpga/ip/gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v b/fpga/ip/gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v deleted file mode 100644 index a167005..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v +++ /dev/null @@ -1,215 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module apb3_2_axi4_lite#( - parameter ADDR_WTH = 10 -) -( -//Globle Signals -input clk, -input rstn, -//APB3 Slave Interface -input [ADDR_WTH-1:0] s_apb3_paddr, -input s_apb3_psel, -input s_apb3_penable, -output reg s_apb3_pready, -input s_apb3_pwrite,//0:rd; 1:wr; -input [31:0] s_apb3_pwdata, -output reg [31:0] s_apb3_prdata, -output reg s_apb3_pslverror, -//AXI4-Lite Master Interface -output reg [ADDR_WTH-1:0] m_axi_awaddr,//Write Address. byte address. -output reg m_axi_awvalid,//Write address valid. -input m_axi_awready,//Write address ready. -output reg [31:0] m_axi_wdata,//Write data bus. -output reg m_axi_wvalid,//Write valid. -input m_axi_wready,//Write ready. -input [1:0] m_axi_bresp,//Write response. -input m_axi_bvalid,//Write response valid. -output wire m_axi_bready,//Response ready. -output reg [ADDR_WTH-1:0] m_axi_araddr,//Read address. byte address. -output reg m_axi_arvalid,//Read address valid. -input m_axi_arready,//Read address ready. -input [1:0] m_axi_rresp,//Read response. -input [31:0] m_axi_rdata,//Read data. -input m_axi_rvalid,//Read valid. -output wire m_axi_rready//Read ready. -); -// Parameter Define -parameter State_idle = 3'd0; -parameter State_wsetup = 3'd1; -parameter State_rsetup = 3'd2; -parameter State_ready = 3'd3; -parameter State_err = 3'd4; - -// Register Define -reg [2:0] cur_state; -reg [2:0] next_state; -reg [7:0] timeout_cnt; - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ - -/*----------------------- FSM Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - cur_state <= State_idle; - else - cur_state <= next_state; -end - -always @(*) -begin - case(cur_state) - State_idle : - if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - next_state = State_wsetup; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) - next_state = State_rsetup; - else - next_state = State_idle; - - State_wsetup : - if((m_axi_awvalid == 1'b0) && (m_axi_wvalid == 1'b0)) - next_state = State_ready; - else if(timeout_cnt[7] == 1'b1) - next_state = State_err; - else - next_state = State_wsetup; - - State_rsetup : - if(m_axi_rvalid == 1'b1) - next_state = State_ready; - else if(timeout_cnt[7] == 1'b1) - next_state = State_err; - else - next_state = State_rsetup; - - State_ready : - next_state = State_idle; - - State_err : - next_state = State_idle; - - default : - next_state = State_idle; - endcase -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - timeout_cnt <= 8'h0; - else if((cur_state == State_wsetup) || (cur_state == State_rsetup)) - timeout_cnt <= timeout_cnt + 1'b1; - else - timeout_cnt <= 8'h0; -end - -/*----------------------- APB3 Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - s_apb3_pready <= 1'b0; - else if((cur_state == State_ready) || (cur_state == State_err)) - s_apb3_pready <= 1'b1; - else - s_apb3_pready <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - s_apb3_pslverror <= 1'b0; - else if(cur_state == State_err) - s_apb3_pslverror <= 1'b1; - else - s_apb3_pslverror <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - s_apb3_prdata <= 32'h0; - else if(m_axi_rvalid == 1'b1) - s_apb3_prdata <= m_axi_rdata; -end - -/*----------------------- AXI4-Lite Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_awaddr <= {ADDR_WTH{1'b0}}; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_awaddr <= s_apb3_paddr; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_awvalid <= 1'b0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_awvalid <= 1'b1; - else if((m_axi_awready == 1'b1) || (cur_state == State_idle)) - m_axi_awvalid <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_wdata <= 32'h0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_wdata <= s_apb3_pwdata; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_wvalid <= 1'b0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - m_axi_wvalid <= 1'b1; - else if((m_axi_wready == 1'b1) || (cur_state == State_idle)) - m_axi_wvalid <= 1'b0; -end - -assign m_axi_bready = 1'b1; - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_araddr <= {ADDR_WTH{1'b0}}; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) - m_axi_araddr <= s_apb3_paddr; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - m_axi_arvalid <= 1'b0; - else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) - m_axi_arvalid <= 1'b1; - else if((m_axi_arready == 1'b1) || (cur_state == State_idle)) - m_axi_arvalid <= 1'b0; -end - -assign m_axi_rready = 1'b1; - -endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/axi4_st_mux.v b/fpga/ip/gTSE/Ti60F225_devkit/axi4_st_mux.v deleted file mode 100644 index fc32c17..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/axi4_st_mux.v +++ /dev/null @@ -1,61 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module axi4_st_mux -( -//Globle Signals -input mux_select, -//Mux In 0 Interface -input [7:0] tdata0, -input tvalid0, -input tlast0, -input tuser0, -output wire tready0, -//Mux In 1 Interface -input [7:0] tdata1, -input tvalid1, -input tlast1, -input tuser1, -output wire tready1, -//Mux Out Interface -output wire [7:0] tdata, -output wire tvalid, -output wire tlast, -output wire tuser, -input tready -); - -// Parameter Define - -// Register Define - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ - -assign tdata = (mux_select) ? tdata1 : tdata0; -assign tvalid = (mux_select) ? tvalid1 : tvalid0; -assign tlast = (mux_select) ? tlast1 : tlast0; -assign tuser = (mux_select) ? tuser1 : tuser0; - -assign tready0 = (mux_select) ? 1'b1 : tready; -assign tready1 = (mux_select) ? tready : 1'b1; - - -endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/gTSE.sv b/fpga/ip/gTSE/Ti60F225_devkit/gTSE.sv deleted file mode 100644 index 8095d65..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/gTSE.sv +++ /dev/null @@ -1,9844 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.288.2.10 -// IP Version: 7.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _4c19f37180ff465ca20760e199a0613f -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gTSE -( - input mac_reset, - input proto_reset, - output rx_mac_aclk, - input tx_mac_aclk, - output [2:0] eth_speed, - input rx_axis_clk, - output rx_axis_mac_tuser, - output rx_axis_mac_tlast, - output rx_axis_mac_tvalid, - input rx_axis_mac_tready, - input tx_axis_clk, - input tx_axis_mac_tvalid, - input tx_axis_mac_tlast, - input tx_axis_mac_tuser, - output tx_axis_mac_tready, - output [3:0] rgmii_txd_HI, - output [3:0] rgmii_txd_LO, - output rgmii_tx_ctl_HI, - output rgmii_tx_ctl_LO, - output rgmii_txc_HI, - output rgmii_txc_LO, - input [3:0] rgmii_rxd_HI, - input [3:0] rgmii_rxd_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input rgmii_rxc, - input s_axi_aclk, - output [7:0] rx_axis_mac_tdata, - input [7:0] tx_axis_mac_tdata, - input [0:0] tx_axis_mac_tstrb, - output [0:0] rx_axis_mac_tstrb, - output MdoEn, - output Mdo, - input Mdi, - output Mdc, - input [9:0] s_axi_araddr, - output s_axi_arready, - input s_axi_arvalid, - input [9:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_awvalid, - input s_axi_bready, - output [1:0] s_axi_bresp, - output s_axi_bvalid, - output [31:0] s_axi_rdata, - input s_axi_rready, - output [1:0] s_axi_rresp, - output s_axi_rvalid, - input [31:0] s_axi_wdata, - output s_axi_wready, - input s_axi_wvalid -); -`IP_MODULE_NAME(efx_mac1gbe) -#( - .VERSION (16), - .TXFIFO_EN (1'b1), - .RXFIFO_EN (1'b1), - .TXFIFO_DTH (4096), - .RXFIFO_DTH (4096), - .PHY_INTF_MODE (0), - .AXIS_DW (8), - .RGMII_RXC_EDGE (1'b1), - .RGMII_TXC_DLY (1'b1), - .INTER_PACKET_GAP (6'd12), - .MTU_FRAME_LENGTH (16'd1518), - .MAC_SOURCE_ADDRESS (48'd0), - .ENABLE_BROADCAST_FILTERING (1'b1), - .LOOPBACK_EN (1'b1), - .APBIF (1'b0), - .FAMILY ("TITANIUM") -) -u_efx_mac1gbe -( - .mac_reset ( mac_reset ), - .proto_reset ( proto_reset ), - .rx_mac_aclk ( rx_mac_aclk ), - .tx_mac_aclk ( tx_mac_aclk ), - .eth_speed ( eth_speed ), - .rx_axis_clk ( rx_axis_clk ), - .rx_axis_mac_tuser ( rx_axis_mac_tuser ), - .rx_axis_mac_tlast ( rx_axis_mac_tlast ), - .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), - .rx_axis_mac_tready ( rx_axis_mac_tready ), - .tx_axis_clk ( tx_axis_clk ), - .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), - .tx_axis_mac_tlast ( tx_axis_mac_tlast ), - .tx_axis_mac_tuser ( tx_axis_mac_tuser ), - .tx_axis_mac_tready ( tx_axis_mac_tready ), - .rgmii_txd_HI ( rgmii_txd_HI ), - .rgmii_txd_LO ( rgmii_txd_LO ), - .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), - .rgmii_txc_HI ( rgmii_txc_HI ), - .rgmii_txc_LO ( rgmii_txc_LO ), - .rgmii_rxd_HI ( rgmii_rxd_HI ), - .rgmii_rxd_LO ( rgmii_rxd_LO ), - .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), - .rgmii_rxc ( rgmii_rxc ), - .s_axi_aclk ( s_axi_aclk ), - .rx_axis_mac_tdata ( rx_axis_mac_tdata ), - .tx_axis_mac_tdata ( tx_axis_mac_tdata ), - .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), - .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), - .MdoEn ( MdoEn ), - .Mdo ( Mdo ), - .Mdi ( Mdi ), - .Mdc ( Mdc ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rready ( s_axi_rready ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ) -); -endmodule - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_top) # ( - parameter FAMILY = "TRION", // New Param - parameter SYNC_CLK = 0, - parameter BYPASS_RESET_SYNC = 0, // New Param - parameter SYNC_STAGE = 2, // New Param - parameter MODE = "STANDARD", - parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) - parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) - parameter PIPELINE_REG = 1, // Reverted (By default is ON) - parameter OPTIONAL_FLAGS = 1, // Reverted - parameter OUTPUT_REG = 0, - parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_FULL_ASSERT = 27, - parameter PROG_FULL_NEGATE = 23, - parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_EMPTY_ASSERT = 5, - parameter PROG_EMPTY_NEGATE = 7, - parameter ALMOST_FLAG = OPTIONAL_FLAGS, - parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, - parameter ASYM_WIDTH_RATIO = 4, - parameter WADDR_WIDTH = depth2width(DEPTH), - parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), - parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), - parameter RADDR_WIDTH = depth2width(RD_DEPTH), - parameter ENDIANESS = 0, - parameter OVERFLOW_PROTECT = 1, - parameter UNDERFLOW_PROTECT = 1, - parameter RAM_STYLE = "block_ram" - -)( - input wire a_rst_i, - input wire a_wr_rst_i, - input wire a_rd_rst_i, - input wire clk_i, - input wire wr_clk_i, - input wire rd_clk_i, - input wire wr_en_i, - input wire rd_en_i, - input wire [DATA_WIDTH-1:0] wdata, - output wire almost_full_o, - output wire prog_full_o, - output wire full_o, - output wire overflow_o, - output wire wr_ack_o, - output wire [WADDR_WIDTH :0] datacount_o, - output wire [WADDR_WIDTH :0] wr_datacount_o, - output wire empty_o, - output wire almost_empty_o, - output wire prog_empty_o, - output wire underflow_o, - output wire rd_valid_o, - output wire [RDATA_WIDTH-1:0] rdata, - output wire [RADDR_WIDTH :0] rd_datacount_o, - output wire rst_busy -); - -localparam WR_DEPTH = DEPTH; -localparam WDATA_WIDTH = DATA_WIDTH; -localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; - -wire wr_rst_int; -wire rd_rst_int; -wire wr_en_int; -wire rd_en_int; -wire [WADDR_WIDTH-1:0] waddr; -wire [RADDR_WIDTH-1:0] raddr; -wire wr_clk_int; -wire rd_clk_int; -wire [WADDR_WIDTH :0] wr_datacount_int; -wire [RADDR_WIDTH :0] rd_datacount_int; - -generate - if (ASYM_WIDTH_RATIO == 4) begin - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - assign datacount_o = wr_datacount_int; - assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - end - end - else begin - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - end - end - - if (!SYNC_CLK) begin - //(* async_reg = "true" *) reg [1:0] wr_rst; - //(* async_reg = "true" *) reg [1:0] rd_rst; - // - //always @ (posedge wr_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // wr_rst <= 2'b11; - // else - // wr_rst <= {wr_rst[0],1'b0}; - //end - // - //always @ (posedge rd_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // rd_rst <= 2'b11; - // else - // rd_rst <= {rd_rst[0],1'b0}; - //end - - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_wr_rst_i; - assign rd_rst_int = a_rd_rst_i; - assign rst_busy = 1'b0; - end - else begin - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_wr_rst ( - .clk (wr_clk_int), - .reset (a_rst_i), - .d_o (wr_rst_int) - ); - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_rd_rst ( - .clk (rd_clk_int), - .reset (a_rst_i), - .d_o (rd_rst_int) - ); - assign rst_busy = wr_rst_int | rd_rst_int; - end - - end - else begin - //(* async_reg = "true" *) reg [1:0] a_rst; - // - //always @ (posedge clk_i or posedge a_rst_i) begin - // if (a_rst_i) - // a_rst <= 2'b11; - // else - // a_rst <= {a_rst[0],1'b0}; - //end - wire a_rst; - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_a_rst ( - .clk (clk_i), - .reset (a_rst_i), - .d_o (a_rst) - ); - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_rst_i; - assign rd_rst_int = a_rst_i; - assign rst_busy = 1'b0; - end - else begin - assign wr_rst_int = a_rst; - assign rd_rst_int = a_rst; - assign rst_busy = wr_rst_int | rd_rst_int; - end - end -endgenerate - -`IP_MODULE_NAME(efx_fifo_ram) # ( - .FAMILY (FAMILY), - .WR_DEPTH (WR_DEPTH), - .RD_DEPTH (RD_DEPTH), - .WDATA_WIDTH (WDATA_WIDTH), - .RDATA_WIDTH (RDATA_WIDTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .OUTPUT_REG (OUTPUT_REG), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .ENDIANESS (ENDIANESS), - .RAM_STYLE (RAM_STYLE) -) xefx_fifo_ram ( - .wdata (wdata), - .waddr (waddr), - .raddr (raddr), - .we (wr_en_int), - .re (rd_en_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .rdata (rdata) -); - -`IP_MODULE_NAME(efx_fifo_ctl) # ( - .SYNC_CLK (SYNC_CLK), - .SYNC_STAGE (SYNC_STAGE), - .MODE (MODE), - .WR_DEPTH (WR_DEPTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .PIPELINE_REG (PIPELINE_REG), - .ALMOST_FLAG (ALMOST_FLAG), - .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), - .PROG_FULL_ASSERT (PROG_FULL_ASSERT), - .PROG_FULL_NEGATE (PROG_FULL_NEGATE), - .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), - .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), - .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), - .OUTPUT_REG (OUTPUT_REG), - .HANDSHAKE_FLAG (HANDSHAKE_FLAG), - .OVERFLOW_PROTECT (OVERFLOW_PROTECT), - .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) -) xefx_fifo_ctl ( - .wr_rst (wr_rst_int), - .rd_rst (rd_rst_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .we (wr_en_i), - .re (rd_en_i), - .wr_full (full_o), - .wr_ack (wr_ack_o), - .rd_empty (empty_o), - .wr_almost_full (almost_full_o), - .rd_almost_empty (almost_empty_o), - .wr_prog_full (prog_full_o), - .rd_prog_empty (prog_empty_o), - .wr_en_int (wr_en_int), - .rd_en_int (rd_en_int), - .waddr (waddr), - .raddr (raddr), - .wr_datacount (wr_datacount_int), - .rd_datacount (rd_datacount_int), - .rd_vld (rd_valid_o), - .wr_overflow (overflow_o), - .rd_underflow (underflow_o) -); - -function integer depth2width; -input [31:0] depth; -begin : fnDepth2Width - if (depth > 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p -yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU -De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF -GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh -0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r -mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q -z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx>> 2); - assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); - BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_5 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_5_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .io_asyncReset (io_asyncReset ) //i - ); - BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_6 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_6_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset) //i - ); - VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b system_cores_0_logic_cpu ( - .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o - .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i - .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o - .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o - .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o - .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o - .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o - .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o - .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o - .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i - .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i - .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i - .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i - .timerInterrupt (_zz_timerInterrupt ), //i - .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i - .softwareInterrupt (_zz_softwareInterrupt ), //i - .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i - .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o - .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i - .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i - .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i - .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o - .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o - .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o - .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i - .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o - .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o - .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i - .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i - .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_jtagBridge ( - .io_ctrl_tdi (jtagCtrl_tdi ), //i - .io_ctrl_enable (jtagCtrl_enable ), //i - .io_ctrl_capture (jtagCtrl_capture ), //i - .io_ctrl_shift (jtagCtrl_shift ), //i - .io_ctrl_update (jtagCtrl_update ), //i - .io_ctrl_reset (jtagCtrl_reset ), //i - .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i - .jtagCtrl_tck (jtagCtrl_tck ) //i - ); - SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_debugger ( - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o - .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i - .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o - .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o - .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i - .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_7 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_7_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .system_cores_0_debugReset (system_cores_0_debugReset) //i - ); - BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b bmbDecoder_4 ( - .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i - .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i - .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_exclusiveMonitor_logic ( - .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i - .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i - .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i - .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i - ); - BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_iBus_bmb_decoder ( - .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i - ); - BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_arbiter ( - .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i - .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o - .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i - .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i - .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o - .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i - .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o - .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o - .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o - .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o - .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o - .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i - .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i - .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o - .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o - .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o - .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o - .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i - .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_decoder ( - .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o - .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i - .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o - .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b system_ramA_logic ( - .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i - .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i - .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i - .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify_1 ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b system_bmbPeripheral_bmb_decoder ( - .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i - .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i - .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i - .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i - .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i - .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i - .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i - .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o - .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i - .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o - .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o - .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o - .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i - .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o - .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i - .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i - .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i - .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i - .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o - .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i - .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o - .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o - .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o - .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i - .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o - .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i - .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i - .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i - .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i - .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o - .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i - .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o - .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o - .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o - .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i - .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o - .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i - .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i - .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i - .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b system_clint_logic ( - .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o - .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o - .io_time (system_clint_logic_io_time[63:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_uart_0_io_logic ( - .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i - .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i - .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i - .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o - .io_uart_rxd (system_uart_0_io_rxd ), //i - .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_spi_0_io_logic ( - .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o - .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i - .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i - .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o - .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o - .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o - .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o - .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o - .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i - .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i - .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i - .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i - .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o - .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o - .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b io_apbSlave_0_logic ( - .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o - .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o - .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o - .io_output_PREADY (io_apbSlave_0_PREADY ), //i - .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o - .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o - .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i - .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - initial begin - debugCd_logic_holdingLogic_resetCounter = 12'h0; - debugCd_logic_outputReset = 1'b1; - end - - always @(*) begin - debugCd_logic_inputResetTrigger = 1'b0; - if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin - debugCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - debugCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); - assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; - always @(*) begin - systemCd_logic_inputResetTrigger = 1'b0; - if(bufferCC_6_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - if(bufferCC_7_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - systemCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); - assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; - assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; - assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; - assign system_cores_0_iBus_cmd_payload_last = 1'b1; - assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_iBus_rsp_ready = 1'b1; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; - always @(*) begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; - case(system_cores_0_logic_cpu_dBus_cmd_payload_size) - 3'b000 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; - end - 3'b001 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; - end - 3'b010 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; - end - 3'b011 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; - end - 3'b100 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; - end - 3'b101 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; - end - 3'b110 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; - end - default : begin - end - endcase - end - - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; - always @(*) begin - system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; - if(when_DataCache_l532) begin - system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; - end - end - - assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; - assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; - assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; - assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; - assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; - always @(*) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; - if(when_Stream_l368) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); - assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; - assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; - assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; - assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; - assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; - assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; - always @(*) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; - if(when_Stream_l368_1) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; - assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; - assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; - assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; - always @(*) begin - case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) - 2'b00 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; - end - 2'b01 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; - end - default : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; - end - endcase - end - - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; - assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; - assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; - assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; - assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; - assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; - assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; - assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); - always @(*) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_2) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; - always @(*) begin - _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_3) begin - _zz_io_input_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; - assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; - assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); - assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; - assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; - assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; - assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; - assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; - assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; - assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; - assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; - assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; - assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; - assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; - assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; - if(when_Stream_l368_4) begin - system_fabric_iBus_bmb_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); - assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; - assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; - assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; - assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; - assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; - assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; - assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; - assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; - assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; - assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; - assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; - assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; - assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; - assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; - assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; - assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); - always @(*) begin - system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_5) begin - system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; - assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; - assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; - assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; - assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; - always @(*) begin - _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_6) begin - _zz_io_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; - assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; - assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); - assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; - assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; - assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; - assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; - assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; - assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; - assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; - assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); - assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); - assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); - assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; - assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; - assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; - assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; - assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; - assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; - assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; - assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; - assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; - assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_plic_logic_bus_readHaltTrigger = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bus_readHaltTrigger = 1'b1; - end - end - - assign system_plic_logic_bus_writeHaltTrigger = 1'b0; - assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); - assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); - always @(*) begin - _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; - if(when_Stream_l368_7) begin - _zz_system_plic_logic_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); - assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; - assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; - assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; - assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; - assign system_plic_logic_bus_rsp_payload_last = 1'b1; - assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; - end - 22'h001000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; - end - 22'h000010 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; - end - 22'h200000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; - end - 22'h200004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; - end - 22'h002000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; - end - default : begin - end - endcase - end - - assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; - assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; - assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; - assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; - assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; - assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); - assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; - assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); - assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); - assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); - assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; - assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; - always @(*) begin - system_plic_logic_bridge_claim_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_valid = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_claim_payload = 3'bxxx; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_completion_valid = 1'b0; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_valid = 1'b1; - end - end - - always @(*) begin - system_plic_logic_bridge_completion_payload = 3'bxxx; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; - end - end - - always @(*) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(when_BmbSlaveFactory_l71) begin - if(system_plic_logic_bus_askWrite) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(system_plic_logic_bus_askRead) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - end - end - - assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; - assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); - assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); - always @(*) begin - system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); - if(system_plic_logic_bridge_coherencyStall_willClear) begin - system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; - end - end - - assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); - assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; - always @(*) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doWrite) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; - assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; - assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; - assign when_BmbSlaveFactory_l71 = 1'b1; - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); - end - if(debugCd_logic_inputResetTrigger) begin - debugCd_logic_holdingLogic_resetCounter <= 12'h0; - end - debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); - end - if(systemCd_logic_inputResetTrigger) begin - systemCd_logic_holdingLogic_resetCounter <= 6'h0; - end - systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - io_systemReset <= systemCd_logic_outputReset; - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; - _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; - _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; - system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; - system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; - system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; - end - if(system_bridge_bmb_cmd_ready) begin - system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; - system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; - system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; - system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; - system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; - system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; - system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; - system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; - end - if(_zz_io_input_rsp_ready_1) begin - _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - end - _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; - _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready_1) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; - _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; - _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; - _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; - end - system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); - system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); - system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); - system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; - end - - always @(posedge io_systemClk) begin - system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_fabric_iBus_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; - system_plic_logic_bridge_coherencyStall_value <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; - end else begin - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; - end - if(system_bridge_bmb_cmd_valid) begin - system_bridge_bmb_cmd_rValid <= 1'b1; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_rValid <= 1'b0; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; - end - if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; - end - if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_uart_0_io_logic_io_bus_rsp_valid) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; - end - if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - end - if(when_PlicGateway_l21) begin - system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; - end - if(when_PlicGateway_l21_1) begin - system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); - end - if(system_plic_logic_bridge_claim_valid) begin - case(system_plic_logic_bridge_claim_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - default : begin - end - endcase - end - if(system_plic_logic_bridge_completion_valid) begin - case(system_plic_logic_bridge_completion_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - default : begin - end - endcase - end - system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h000010 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h200000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h002000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; - end else begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; - end - end - - -endmodule - -module BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [15:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [3:0] io_input_rsp_payload_fragment_context, - output [15:0] io_output_PADDR, - output [0:0] io_output_PSEL, - output io_output_PENABLE, - input io_output_PREADY, - output io_output_PWRITE, - output [31:0] io_output_PWDATA, - input [31:0] io_output_PRDATA, - input io_output_PSLVERROR, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire bmbBuffer_cmd_valid; - reg bmbBuffer_cmd_ready; - wire bmbBuffer_cmd_payload_last; - wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; - wire [15:0] bmbBuffer_cmd_payload_fragment_address; - wire [1:0] bmbBuffer_cmd_payload_fragment_length; - wire [31:0] bmbBuffer_cmd_payload_fragment_data; - wire [3:0] bmbBuffer_cmd_payload_fragment_context; - reg bmbBuffer_rsp_valid; - reg bmbBuffer_rsp_ready; - wire bmbBuffer_rsp_payload_last; - reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_payload_fragment_context; - wire io_input_rsp_isStall; - wire _zz_io_input_cmd_ready; - wire bmbBuffer_rsp_m2sPipe_valid; - wire bmbBuffer_rsp_m2sPipe_ready; - wire bmbBuffer_rsp_m2sPipe_payload_last; - wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; - reg bmbBuffer_rsp_rValid; - reg bmbBuffer_rsp_rData_last; - reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; - reg [31:0] bmbBuffer_rsp_rData_fragment_data; - reg [3:0] bmbBuffer_rsp_rData_fragment_context; - wire when_Stream_l368; - reg state; - wire when_BmbToApb3Bridge_l46; - - assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); - assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); - assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; - assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - always @(*) begin - bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; - if(when_Stream_l368) begin - bmbBuffer_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); - assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; - assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; - assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; - assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; - assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; - always @(*) begin - bmbBuffer_cmd_ready = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_cmd_ready = 1'b1; - end - end - end - - assign io_output_PSEL[0] = bmbBuffer_cmd_valid; - assign io_output_PENABLE = state; - assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); - assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; - assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; - always @(*) begin - bmbBuffer_rsp_valid = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_rsp_valid = 1'b1; - end - end - end - - assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; - assign when_BmbToApb3Bridge_l46 = (! state); - assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign bmbBuffer_rsp_payload_last = 1'b1; - always @(*) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b0; - if(io_output_PSLVERROR) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b1; - end - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - bmbBuffer_rsp_rValid <= 1'b0; - state <= 1'b0; - end else begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; - end - if(when_BmbToApb3Bridge_l46) begin - state <= bmbBuffer_cmd_valid; - end else begin - if(io_output_PREADY) begin - state <= 1'b0; - end - end - end - end - - always @(posedge io_systemClk) begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; - bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; - bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; - bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; - end - end - - -endmodule - -module BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_ctrl_cmd_valid, - output io_ctrl_cmd_ready, - input io_ctrl_cmd_payload_last, - input [0:0] io_ctrl_cmd_payload_fragment_opcode, - input [11:0] io_ctrl_cmd_payload_fragment_address, - input [1:0] io_ctrl_cmd_payload_fragment_length, - input [31:0] io_ctrl_cmd_payload_fragment_data, - input [3:0] io_ctrl_cmd_payload_fragment_context, - output io_ctrl_rsp_valid, - input io_ctrl_rsp_ready, - output io_ctrl_rsp_payload_last, - output [0:0] io_ctrl_rsp_payload_fragment_opcode, - output [31:0] io_ctrl_rsp_payload_fragment_data, - output [3:0] io_ctrl_rsp_payload_fragment_context, - output [0:0] io_spi_sclk_write, - output io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output [0:0] io_spi_data_0_write, - output io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output [0:0] io_spi_data_1_write, - output io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output [0:0] io_spi_data_2_write, - output io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; - wire ctrl_io_cmd_ready; - wire ctrl_io_rsp_valid; - wire [7:0] ctrl_io_rsp_payload_data; - wire [0:0] ctrl_io_spi_sclk_write; - wire [0:0] ctrl_io_spi_ss; - wire [0:0] ctrl_io_spi_data_0_write; - wire ctrl_io_spi_data_0_writeEnable; - wire [0:0] ctrl_io_spi_data_1_write; - wire ctrl_io_spi_data_1_writeEnable; - wire [0:0] ctrl_io_spi_data_2_write; - wire ctrl_io_spi_data_2_writeEnable; - wire [0:0] ctrl_io_spi_data_3_write; - wire ctrl_io_spi_data_3_writeEnable; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; - wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_ctrl_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_ctrl_rsp_valid_1; - reg _zz_io_ctrl_rsp_valid_2; - reg _zz_io_ctrl_rsp_payload_last; - reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; - reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_ctrl_cmd_fire; - wire factory_doWrite; - wire io_ctrl_cmd_fire_1; - wire factory_doRead; - wire [31:0] mapping_cmdLogic_writeData; - reg mapping_cmdLogic_doRegular; - reg mapping_cmdLogic_doWriteLarge; - reg mapping_cmdLogic_doReadWriteLarge; - wire mapping_cmdLogic_streamUnbuffered_valid; - wire mapping_cmdLogic_streamUnbuffered_ready; - wire mapping_cmdLogic_streamUnbuffered_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_payload_read; - wire mapping_cmdLogic_streamUnbuffered_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - wire when_Stream_l368_1; - wire ctrl_io_rsp_toStream_valid; - wire ctrl_io_rsp_toStream_ready; - wire [7:0] ctrl_io_rsp_toStream_payload_data; - reg _zz_io_pop_ready; - reg _zz_io_pop_ready_1; - reg mapping_interruptCtrl_cmdIntEnable; - reg mapping_interruptCtrl_rspIntEnable; - wire mapping_interruptCtrl_cmdInt; - wire mapping_interruptCtrl_rspInt; - wire mapping_interruptCtrl_interrupt; - reg _zz_io_config_kind_cpol; - reg _zz_io_config_kind_cpha; - reg [1:0] _zz_io_config_mod; - reg [11:0] _zz_io_config_sclkToogle; - reg [11:0] _zz_io_config_ss_setup; - reg [11:0] _zz_io_config_ss_hold; - reg [11:0] _zz_io_config_ss_disable; - reg [0:0] _zz_io_config_ss_activeHigh; - wire [1:0] _zz_io_config_kind_cpol_1; - - TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ctrl ( - .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i - .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i - .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i - .io_config_mod (_zz_io_config_mod[1:0] ), //i - .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i - .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i - .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i - .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i - .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i - .io_cmd_ready (ctrl_io_cmd_ready ), //o - .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i - .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i - .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i - .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i - .io_rsp_valid (ctrl_io_rsp_valid ), //o - .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o - .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (io_spi_data_0_read ), //i - .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (io_spi_data_1_read ), //i - .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (io_spi_data_2_read ), //i - .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (io_spi_data_3_read ), //i - .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o - .io_spi_ss (ctrl_io_spi_ss ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( - .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i - .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o - .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i - .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i - .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i - .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i - .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o - .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i - .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o - .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o - .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o - .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o - .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ctrl_io_rsp_queueWithOccupancy ( - .io_push_valid (ctrl_io_rsp_toStream_valid ), //i - .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o - .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i - .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o - .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_ctrl_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); - assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - 12'h004 : begin - factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; - end - 12'h00c : begin - factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; - factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; - factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; - factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; - end - 12'h058 : begin - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - default : begin - end - endcase - end - - assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - always @(*) begin - mapping_cmdLogic_doRegular = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doRegular = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h050 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doReadWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h054 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doReadWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); - assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; - assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); - always @(*) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_1) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; - assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; - assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; - assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; - always @(*) begin - _zz_io_pop_ready = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doRead) begin - _zz_io_pop_ready = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - _zz_io_pop_ready_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h058 : begin - if(factory_doRead) begin - _zz_io_pop_ready_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); - assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); - assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); - assign io_spi_sclk_write = ctrl_io_spi_sclk_write; - assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; - assign io_spi_data_0_write = ctrl_io_spi_data_0_write; - assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; - assign io_spi_data_1_write = ctrl_io_spi_data_1_write; - assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; - assign io_spi_data_2_write = ctrl_io_spi_data_2_write; - assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; - assign io_spi_data_3_write = ctrl_io_spi_data_3_write; - assign io_spi_ss = ctrl_io_spi_ss; - assign io_interrupt = mapping_interruptCtrl_interrupt; - assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; - assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_ctrl_rsp_valid_2 <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; - mapping_interruptCtrl_cmdIntEnable <= 1'b0; - mapping_interruptCtrl_rspIntEnable <= 1'b0; - _zz_io_config_ss_activeHigh <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h00c : begin - if(factory_doWrite) begin - mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; - mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; - end - end - 12'h030 : begin - if(factory_doWrite) begin - _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h008 : begin - if(factory_doWrite) begin - _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; - _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; - _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; - end - end - 12'h020 : begin - if(factory_doWrite) begin - _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h024 : begin - if(factory_doWrite) begin - _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h028 : begin - if(factory_doWrite) begin - _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h02c : begin - if(factory_doWrite) begin - _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - default : begin - end - endcase - end - - -endmodule - -module BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [5:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output io_uart_txd, - input io_uart_rxd, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; - wire uartCtrl_1_io_write_ready; - wire uartCtrl_1_io_read_valid; - wire [7:0] uartCtrl_1_io_read_payload; - wire uartCtrl_1_io_uart_txd; - wire uartCtrl_1_io_readError; - wire uartCtrl_1_io_readBreak; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; - wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; - wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; - wire [0:0] _zz_bridge_misc_readError; - wire [0:0] _zz_bridge_misc_readOverflowError; - wire [0:0] _zz_bridge_misc_breakDetected; - wire [0:0] _zz_bridge_misc_doBreak; - wire [0:0] _zz_bridge_misc_doBreak_1; - wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - wire [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [3:0] busCtrl_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_busCtrl_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_bus_cmd_fire; - wire busCtrl_doWrite; - wire io_bus_cmd_fire_1; - wire busCtrl_doRead; - reg [2:0] bridge_uartConfigReg_frame_dataLength; - reg [0:0] bridge_uartConfigReg_frame_stop; - reg [1:0] bridge_uartConfigReg_frame_parity; - reg [19:0] bridge_uartConfigReg_clockDivider; - reg _zz_bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_ready; - wire [7:0] bridge_write_streamUnbuffered_payload; - reg bridge_read_streamBreaked_valid; - reg bridge_read_streamBreaked_ready; - wire [7:0] bridge_read_streamBreaked_payload; - reg bridge_interruptCtrl_writeIntEnable; - reg bridge_interruptCtrl_readIntEnable; - wire bridge_interruptCtrl_readInt; - wire bridge_interruptCtrl_writeInt; - wire bridge_interruptCtrl_interrupt; - reg bridge_misc_readError; - reg when_BusSlaveFactory_l335; - wire when_BusSlaveFactory_l341; - reg bridge_misc_readOverflowError; - reg when_BusSlaveFactory_l335_1; - wire when_BusSlaveFactory_l341_1; - wire uartCtrl_1_io_read_isStall; - reg bridge_misc_breakDetected; - reg uartCtrl_1_io_readBreak_regNext; - wire when_UartCtrl_l155; - reg when_BusSlaveFactory_l335_2; - wire when_BusSlaveFactory_l341_2; - reg bridge_misc_doBreak; - reg when_BusSlaveFactory_l371; - wire when_BusSlaveFactory_l373; - reg when_BusSlaveFactory_l335_3; - wire when_BusSlaveFactory_l341_3; - wire [1:0] _zz_bridge_uartConfigReg_frame_parity; - wire [0:0] _zz_bridge_uartConfigReg_frame_stop; - wire when_BmbSlaveFactory_l71; - `ifndef SYNTHESIS - reg [23:0] bridge_uartConfigReg_frame_stop_string; - reg [31:0] bridge_uartConfigReg_frame_parity_string; - reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; - reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; - `endif - - - assign _zz_bridge_misc_readError = 1'b0; - assign _zz_bridge_misc_readOverflowError = 1'b0; - assign _zz_bridge_misc_breakDetected = 1'b0; - assign _zz_bridge_misc_doBreak = 1'b1; - assign _zz_bridge_misc_doBreak_1 = 1'b0; - assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); - assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; - assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; - UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1 ( - .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i - .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i - .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i - .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i - .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i - .io_write_ready (uartCtrl_1_io_write_ready ), //o - .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i - .io_read_valid (uartCtrl_1_io_read_valid ), //o - .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i - .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o - .io_uart_txd (uartCtrl_1_io_uart_txd ), //o - .io_uart_rxd (io_uart_rxd ), //i - .io_readError (uartCtrl_1_io_readError ), //o - .io_writeBreak (bridge_misc_doBreak ), //i - .io_readBreak (uartCtrl_1_io_readBreak ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b bridge_write_streamUnbuffered_queueWithOccupancy ( - .io_push_valid (bridge_write_streamUnbuffered_valid ), //i - .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i - .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_write_ready ), //i - .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1_io_read_queueWithOccupancy ( - .io_push_valid (uartCtrl_1_io_read_valid ), //i - .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i - .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(bridge_uartConfigReg_frame_stop) - UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; - default : bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(bridge_uartConfigReg_frame_parity) - UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; - default : bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_parity) - UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; - default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_stop) - UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; - default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - `endif - - assign io_uart_txd = uartCtrl_1_io_uart_txd; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_busCtrl_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_busCtrl_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign busCtrl_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; - end - 6'h04 : begin - busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; - end - 6'h10 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; - busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - always @(*) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doWrite) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; - assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; - assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - always @(*) begin - bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - if(uartCtrl_1_io_readBreak) begin - bridge_read_streamBreaked_valid = 1'b0; - end - end - - always @(*) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; - if(uartCtrl_1_io_readBreak) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; - end - end - - assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - always @(*) begin - bridge_read_streamBreaked_ready = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doRead) begin - bridge_read_streamBreaked_ready = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); - assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); - assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); - always @(*) begin - when_BusSlaveFactory_l335 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; - always @(*) begin - when_BusSlaveFactory_l335_1 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; - assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); - assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); - always @(*) begin - when_BusSlaveFactory_l335_2 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l371 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l371 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l335_3 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; - assign io_interrupt = bridge_interruptCtrl_interrupt; - assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; - assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - bridge_uartConfigReg_clockDivider <= 20'h0; - bridge_uartConfigReg_clockDivider <= 20'h00035; - bridge_uartConfigReg_frame_dataLength <= 3'b111; - bridge_uartConfigReg_frame_parity <= UartParityType_NONE; - bridge_uartConfigReg_frame_stop <= UartStopType_ONE; - bridge_interruptCtrl_writeIntEnable <= 1'b0; - bridge_interruptCtrl_readIntEnable <= 1'b0; - bridge_misc_readError <= 1'b0; - bridge_misc_readOverflowError <= 1'b0; - bridge_misc_breakDetected <= 1'b0; - bridge_misc_doBreak <= 1'b0; - end else begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); - end - if(when_BusSlaveFactory_l335) begin - if(when_BusSlaveFactory_l341) begin - bridge_misc_readError <= _zz_bridge_misc_readError[0]; - end - end - if(uartCtrl_1_io_readError) begin - bridge_misc_readError <= 1'b1; - end - if(when_BusSlaveFactory_l335_1) begin - if(when_BusSlaveFactory_l341_1) begin - bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; - end - end - if(uartCtrl_1_io_read_isStall) begin - bridge_misc_readOverflowError <= 1'b1; - end - if(when_UartCtrl_l155) begin - bridge_misc_breakDetected <= 1'b1; - end - if(when_BusSlaveFactory_l335_2) begin - if(when_BusSlaveFactory_l341_2) begin - bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; - end - end - if(when_BusSlaveFactory_l371) begin - if(when_BusSlaveFactory_l373) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; - end - end - if(when_BusSlaveFactory_l335_3) begin - if(when_BusSlaveFactory_l341_3) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; - end - end - case(io_bus_cmd_payload_fragment_address) - 6'h0c : begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; - bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; - bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; - end - end - 6'h04 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; - end - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; - end - end - end - end - - always @(posedge io_systemClk) begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; - end - - -endmodule - -module BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [15:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output [0:0] io_timerInterrupt, - output [0:0] io_softwareInterrupt, - output [63:0] io_time, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [31:0] _zz_logic_harts_0_cmp; - wire [31:0] _zz_logic_harts_0_cmp_1; - wire [31:0] _zz_logic_harts_0_cmp_2; - wire [31:0] _zz_logic_harts_0_cmp_3; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_bus_cmd_fire; - wire factory_doWrite; - wire io_bus_cmd_fire_1; - wire factory_doRead; - reg [63:0] logic_time; - reg [63:0] logic_harts_0_cmp; - reg logic_harts_0_timerInterrupt; - reg logic_harts_0_softwareInterrupt; - wire [63:0] _zz_factory_rsp_payload_fragment_data; - wire when_BmbSlaveFactory_l71; - wire when_BmbSlaveFactory_l71_1; - wire when_BmbSlaveFactory_l71_2; - wire when_BmbSlaveFactory_l71_3; - - assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; - assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; - end - if(when_BmbSlaveFactory_l71_1) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; - end - end - - assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - assign _zz_factory_rsp_payload_fragment_data = logic_time; - assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; - assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; - assign io_time = logic_time; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); - assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); - assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); - assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - logic_time <= 64'h0; - logic_harts_0_softwareInterrupt <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); - end - logic_time <= (logic_time + 64'h0000000000000001); - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - if(factory_doWrite) begin - logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); - if(when_BmbSlaveFactory_l71_2) begin - if(factory_doWrite) begin - logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; - end - end - if(when_BmbSlaveFactory_l71_3) begin - if(factory_doWrite) begin - logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; - end - end - end - - -endmodule - -module BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [23:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [3:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [3:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [23:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [3:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [3:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [23:0] io_outputs_1_cmd_payload_fragment_address, - output [1:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [3:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [3:0] io_outputs_1_rsp_payload_fragment_context, - output reg io_outputs_2_cmd_valid, - input io_outputs_2_cmd_ready, - output io_outputs_2_cmd_payload_last, - output [0:0] io_outputs_2_cmd_payload_fragment_opcode, - output [23:0] io_outputs_2_cmd_payload_fragment_address, - output [1:0] io_outputs_2_cmd_payload_fragment_length, - output [31:0] io_outputs_2_cmd_payload_fragment_data, - output [3:0] io_outputs_2_cmd_payload_fragment_mask, - output [3:0] io_outputs_2_cmd_payload_fragment_context, - input io_outputs_2_rsp_valid, - output io_outputs_2_rsp_ready, - input io_outputs_2_rsp_payload_last, - input [0:0] io_outputs_2_rsp_payload_fragment_opcode, - input [31:0] io_outputs_2_rsp_payload_fragment_data, - input [3:0] io_outputs_2_rsp_payload_fragment_context, - output reg io_outputs_3_cmd_valid, - input io_outputs_3_cmd_ready, - output io_outputs_3_cmd_payload_last, - output [0:0] io_outputs_3_cmd_payload_fragment_opcode, - output [23:0] io_outputs_3_cmd_payload_fragment_address, - output [1:0] io_outputs_3_cmd_payload_fragment_length, - output [31:0] io_outputs_3_cmd_payload_fragment_data, - output [3:0] io_outputs_3_cmd_payload_fragment_mask, - output [3:0] io_outputs_3_cmd_payload_fragment_context, - input io_outputs_3_rsp_valid, - output io_outputs_3_rsp_ready, - input io_outputs_3_rsp_payload_last, - input [0:0] io_outputs_3_rsp_payload_fragment_opcode, - input [31:0] io_outputs_3_rsp_payload_fragment_data, - input [3:0] io_outputs_3_rsp_payload_fragment_context, - output reg io_outputs_4_cmd_valid, - input io_outputs_4_cmd_ready, - output io_outputs_4_cmd_payload_last, - output [0:0] io_outputs_4_cmd_payload_fragment_opcode, - output [23:0] io_outputs_4_cmd_payload_fragment_address, - output [1:0] io_outputs_4_cmd_payload_fragment_length, - output [31:0] io_outputs_4_cmd_payload_fragment_data, - output [3:0] io_outputs_4_cmd_payload_fragment_mask, - output [3:0] io_outputs_4_cmd_payload_fragment_context, - input io_outputs_4_rsp_valid, - output io_outputs_4_rsp_ready, - input io_outputs_4_rsp_payload_last, - input [0:0] io_outputs_4_rsp_payload_fragment_opcode, - input [31:0] io_outputs_4_rsp_payload_fragment_data, - input [3:0] io_outputs_4_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_logic_rspPendingCounter; - wire [3:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [3:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_3; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [3:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [3:0] logic_input_payload_fragment_context; - reg io_input_cmd_rValid; - wire logic_input_fire; - reg io_input_cmd_rData_last; - reg [0:0] io_input_cmd_rData_fragment_opcode; - reg [23:0] io_input_cmd_rData_fragment_address; - reg [1:0] io_input_cmd_rData_fragment_length; - reg [31:0] io_input_cmd_rData_fragment_data; - reg [3:0] io_input_cmd_rData_fragment_mask; - reg [3:0] io_input_cmd_rData_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_hitsS0_2; - wire logic_hitsS0_3; - wire logic_hitsS0_4; - wire logic_noHitS0; - wire io_input_cmd_fire; - reg logic_hitsS1_0; - reg logic_hitsS1_1; - reg logic_hitsS1_2; - reg logic_hitsS1_3; - reg logic_hitsS1_4; - wire io_input_cmd_fire_1; - reg logic_noHitS1; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - wire _zz_io_outputs_2_cmd_payload_last; - wire _zz_io_outputs_3_cmd_payload_last; - wire _zz_io_outputs_4_cmd_payload_last; - reg [3:0] logic_rspPendingCounter; - wire logic_input_fire_1; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - reg logic_rspHits_2; - reg logic_rspHits_3; - reg logic_rspHits_4; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_2; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_3; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_4; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_context; - wire logic_input_fire_6; - wire _zz_io_input_rsp_payload_last; - wire _zz_io_input_rsp_payload_last_1; - wire [2:0] _zz_io_input_rsp_payload_last_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last_2) - 3'b000 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - 3'b001 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - 3'b010 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; - end - 3'b011 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_cmd_ready = (! io_input_cmd_rValid); - assign logic_input_valid = io_input_cmd_rValid; - assign logic_input_payload_last = io_input_cmd_rData_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); - assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); - assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); - always @(*) begin - io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); - if(logic_cmdWait) begin - io_outputs_2_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; - assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; - assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); - always @(*) begin - io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); - if(logic_cmdWait) begin - io_outputs_3_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; - assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; - assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); - always @(*) begin - io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); - if(logic_cmdWait) begin - io_outputs_4_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; - assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; - assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); - assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign io_outputs_2_rsp_ready = io_input_rsp_ready; - assign io_outputs_3_rsp_ready = io_input_rsp_ready; - assign io_outputs_4_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_input_cmd_rValid <= 1'b0; - logic_rspPendingCounter <= 4'b0000; - logic_rspNoHit_doIt <= 1'b0; - end else begin - if(io_input_cmd_valid) begin - io_input_cmd_rValid <= 1'b1; - end - if(logic_input_fire) begin - io_input_cmd_rValid <= 1'b0; - end - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(io_input_cmd_ready) begin - io_input_cmd_rData_last <= io_input_cmd_payload_last; - io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; - io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; - io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; - io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; - io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; - io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; - end - if(io_input_cmd_fire) begin - logic_hitsS1_0 <= logic_hitsS0_0; - logic_hitsS1_1 <= logic_hitsS0_1; - logic_hitsS1_2 <= logic_hitsS0_2; - logic_hitsS1_3 <= logic_hitsS0_3; - logic_hitsS1_4 <= logic_hitsS0_4; - end - if(io_input_cmd_fire_1) begin - logic_noHitS1 <= logic_noHitS0; - end - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS1_0; - logic_rspHits_1 <= logic_hitsS1_1; - logic_rspHits_2 <= logic_hitsS1_2; - logic_rspHits_3 <= logic_hitsS1_3; - logic_rspHits_4 <= logic_hitsS1_4; - end - if(logic_input_fire_3) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_5) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - end - - -endmodule - -//BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b replaced by BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b - -module BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output reg io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_source, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output reg io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output reg [0:0] io_output_cmd_payload_fragment_opcode, - output reg [31:0] io_output_cmd_payload_fragment_address, - output reg [1:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [3:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output reg io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [3:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_buffer_last; - wire [0:0] _zz_buffer_last_1; - wire [11:0] _zz_buffer_addressIncr; - wire [11:0] _zz_buffer_addressIncr_1; - wire [11:0] _zz_buffer_addressIncr_2; - wire doResult; - reg buffer_valid; - reg [0:0] buffer_opcode; - reg [0:0] buffer_source; - reg [31:0] buffer_address; - reg [0:0] buffer_context; - reg [3:0] buffer_beat; - wire buffer_last; - wire [31:0] buffer_addressIncr; - wire buffer_isWrite; - wire io_output_cmd_fire; - wire [3:0] cmdTransferBeatCount; - wire requireBuffer; - reg cmdContext_drop; - reg cmdContext_last; - reg [0:0] cmdContext_source; - reg [0:0] cmdContext_context; - wire io_output_cmd_fire_1; - wire rspContext_drop; - wire rspContext_last; - wire [0:0] rspContext_source; - wire [0:0] rspContext_context; - wire [3:0] _zz_rspContext_drop; - wire when_Stream_l434; - reg io_output_rsp_thrown_valid; - wire io_output_rsp_thrown_ready; - wire io_output_rsp_thrown_payload_last; - wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; - wire [31:0] io_output_rsp_thrown_payload_fragment_data; - wire [3:0] io_output_rsp_thrown_payload_fragment_context; - - assign _zz_buffer_last_1 = 1'b1; - assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; - assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); - assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; - assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; - assign buffer_last = (buffer_beat == _zz_buffer_last); - assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; - assign buffer_isWrite = (buffer_opcode == 1'b1); - assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); - assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; - assign requireBuffer = (cmdTransferBeatCount != 4'b0000); - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_last = 1'b1; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_address = buffer_addressIncr; - end else begin - io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - if(requireBuffer) begin - io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; - end - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_opcode = buffer_opcode; - end else begin - io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - if(requireBuffer) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; - end - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_context = buffer_context; - end else begin - cmdContext_context = io_input_cmd_payload_fragment_context; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_source = buffer_source; - end else begin - cmdContext_source = io_input_cmd_payload_fragment_source; - end - end - - always @(*) begin - io_input_cmd_ready = 1'b0; - if(buffer_valid) begin - io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); - end else begin - io_input_cmd_ready = io_output_cmd_ready; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); - end else begin - io_output_cmd_valid = io_input_cmd_valid; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_last = buffer_last; - end else begin - cmdContext_last = (! requireBuffer); - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_drop = buffer_isWrite; - end else begin - cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); - end - end - - assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); - assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; - assign rspContext_drop = _zz_rspContext_drop[0]; - assign rspContext_last = _zz_rspContext_drop[1]; - assign rspContext_source = _zz_rspContext_drop[2 : 2]; - assign rspContext_context = _zz_rspContext_drop[3 : 3]; - assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); - always @(*) begin - io_output_rsp_thrown_valid = io_output_rsp_valid; - if(when_Stream_l434) begin - io_output_rsp_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_output_rsp_ready = io_output_rsp_thrown_ready; - if(when_Stream_l434) begin - io_output_rsp_ready = 1'b1; - end - end - - assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; - assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_input_rsp_valid = io_output_rsp_thrown_valid; - assign io_output_rsp_thrown_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = rspContext_last; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = rspContext_context; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffer_valid <= 1'b0; - end else begin - if(io_output_cmd_fire) begin - if(buffer_last) begin - buffer_valid <= 1'b0; - end - end - if(!buffer_valid) begin - buffer_valid <= (requireBuffer && io_output_cmd_fire_1); - end - end - end - - always @(posedge io_systemClk) begin - if(io_output_cmd_fire) begin - buffer_beat <= (buffer_beat - 4'b0001); - buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; - end - if(!buffer_valid) begin - buffer_opcode <= io_input_cmd_payload_fragment_opcode; - buffer_source <= io_input_cmd_payload_fragment_source; - buffer_address <= io_input_cmd_payload_fragment_address; - buffer_context <= io_input_cmd_payload_fragment_context; - buffer_beat <= cmdTransferBeatCount; - end - end - - -endmodule - -module BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [14:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_mask, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_ram_port0; - wire io_bus_rsp_isStall; - reg io_bus_cmd_valid_regNextWhen; - reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; - wire [12:0] _zz_io_bus_rsp_payload_fragment_data; - wire io_bus_cmd_fire; - wire _zz_io_bus_rsp_payload_fragment_data_1; - wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; - reg [7:0] ram_symbol0 [0:8191]; - reg [7:0] ram_symbol1 [0:8191]; - reg [7:0] ram_symbol2 [0:8191]; - reg [7:0] ram_symbol3 [0:8191]; - reg [7:0] _zz_ramsymbol_read; - reg [7:0] _zz_ramsymbol_read_1; - reg [7:0] _zz_ramsymbol_read_2; - reg [7:0] _zz_ramsymbol_read_3; - - initial begin - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); - end - always @(*) begin - _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; - end - always @(posedge io_systemClk) begin - if(io_bus_cmd_fire) begin - _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; - end - if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; - end - if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; - end - if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; - end - end - - assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); - assign io_bus_cmd_ready = (! io_bus_rsp_isStall); - assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; - assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; - assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); - assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; - assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; - assign io_bus_rsp_payload_fragment_opcode = 1'b0; - assign io_bus_rsp_payload_last = 1'b1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_bus_cmd_valid_regNextWhen <= 1'b0; - end else begin - if(io_bus_cmd_ready) begin - io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; - end - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_ready) begin - io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; - end - end - - -endmodule - -module BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_source, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [0:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_source, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [0:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_source, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [0:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_source, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [31:0] io_outputs_1_cmd_payload_fragment_address, - output [5:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [0:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_source, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [0:0] io_outputs_1_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_1; - reg [0:0] _zz_io_input_rsp_payload_fragment_source; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [0:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_source; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [5:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [0:0] logic_input_payload_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - reg [0:0] logic_rspNoHit_source; - wire logic_input_fire_4; - reg [0:0] logic_rspNoHit_context; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_counter; - wire [0:0] _zz_io_input_rsp_payload_last; - wire when_BmbDecoder_l81; - wire io_input_rsp_fire_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last) - 1'b0 : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = logic_rspHits_1; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b0; - if(when_BmbDecoder_l81) begin - io_input_rsp_payload_last = 1'b1; - end - if(logic_rspNoHit_singleBeatRsp) begin - io_input_rsp_payload_last = 1'b1; - end - end - end - - always @(*) begin - io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_source = logic_rspNoHit_source; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); - assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - logic_rspHits_1 <= logic_hitsS0_1; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_3) begin - logic_rspNoHit_source <= logic_input_payload_fragment_source; - end - if(logic_input_fire_4) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - if(logic_input_fire_5) begin - logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; - end - if(logic_rspNoHit_doIt) begin - if(io_input_rsp_fire_2) begin - logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); - end - end - end - - -endmodule - -module BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_inputs_0_cmd_valid, - output io_inputs_0_cmd_ready, - input io_inputs_0_cmd_payload_last, - input [0:0] io_inputs_0_cmd_payload_fragment_opcode, - input [31:0] io_inputs_0_cmd_payload_fragment_address, - input [5:0] io_inputs_0_cmd_payload_fragment_length, - input [31:0] io_inputs_0_cmd_payload_fragment_data, - input [3:0] io_inputs_0_cmd_payload_fragment_mask, - input [0:0] io_inputs_0_cmd_payload_fragment_context, - output io_inputs_0_rsp_valid, - input io_inputs_0_rsp_ready, - output io_inputs_0_rsp_payload_last, - output [0:0] io_inputs_0_rsp_payload_fragment_opcode, - output [31:0] io_inputs_0_rsp_payload_fragment_data, - output [0:0] io_inputs_0_rsp_payload_fragment_context, - input io_inputs_1_cmd_valid, - output io_inputs_1_cmd_ready, - input io_inputs_1_cmd_payload_last, - input [0:0] io_inputs_1_cmd_payload_fragment_opcode, - input [31:0] io_inputs_1_cmd_payload_fragment_address, - input [5:0] io_inputs_1_cmd_payload_fragment_length, - input [31:0] io_inputs_1_cmd_payload_fragment_data, - input [3:0] io_inputs_1_cmd_payload_fragment_mask, - output io_inputs_1_rsp_valid, - input io_inputs_1_rsp_ready, - output io_inputs_1_rsp_payload_last, - output [0:0] io_inputs_1_rsp_payload_fragment_opcode, - output [31:0] io_inputs_1_rsp_payload_fragment_data, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_source, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_source, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire memory_arbiter_io_inputs_0_ready; - wire memory_arbiter_io_inputs_1_ready; - wire memory_arbiter_io_output_valid; - wire memory_arbiter_io_output_payload_last; - wire [0:0] memory_arbiter_io_output_payload_fragment_source; - wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; - wire [31:0] memory_arbiter_io_output_payload_fragment_address; - wire [5:0] memory_arbiter_io_output_payload_fragment_length; - wire [31:0] memory_arbiter_io_output_payload_fragment_data; - wire [3:0] memory_arbiter_io_output_payload_fragment_mask; - wire [0:0] memory_arbiter_io_output_payload_fragment_context; - wire [0:0] memory_arbiter_io_chosen; - wire [1:0] memory_arbiter_io_chosenOH; - wire [1:0] _zz_io_output_cmd_payload_fragment_source; - reg _zz_io_output_rsp_ready; - wire [0:0] memory_rspSel; - - assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; - StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b memory_arbiter ( - .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i - .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o - .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i - .io_inputs_0_payload_fragment_source (1'b0 ), //i - .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i - .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i - .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o - .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i - .io_inputs_1_payload_fragment_source (1'b0 ), //i - .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i - .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_1_payload_fragment_context (1'b0 ), //i - .io_output_valid (memory_arbiter_io_output_valid ), //o - .io_output_ready (io_output_cmd_ready ), //i - .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o - .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o - .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o - .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o - .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o - .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o - .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o - .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o - .io_chosen (memory_arbiter_io_chosen ), //o - .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(memory_rspSel) - 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; - default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; - endcase - end - - assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; - assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; - assign io_output_cmd_valid = memory_arbiter_io_output_valid; - assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; - assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; - assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; - assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; - assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); - assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); - assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_ready = _zz_io_output_rsp_ready; - -endmodule - -module BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data -); - - - assign io_outputs_0_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_outputs_0_cmd_ready; - assign io_input_rsp_valid = io_outputs_0_rsp_valid; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - -endmodule - -module BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context -); - - - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - -endmodule - -module BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire logic_hitsS0_0; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - wire logic_input_fire_4; - wire logic_input_fire_5; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - always @(*) begin - logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - end - - -endmodule - -module BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input system_cores_0_debugReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin - if(system_cores_0_debugReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_remote_cmd_valid, - output io_remote_cmd_ready, - input io_remote_cmd_payload_last, - input [0:0] io_remote_cmd_payload_fragment, - output io_remote_rsp_valid, - input io_remote_rsp_ready, - output io_remote_rsp_payload_error, - output [31:0] io_remote_rsp_payload_data, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output io_mem_cmd_payload_wr, - output [1:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload, - input io_systemClk, - input debugCd_logic_outputReset -); - - reg [66:0] dispatcher_dataShifter; - reg dispatcher_dataLoaded; - reg [7:0] dispatcher_headerShifter; - wire [7:0] dispatcher_header; - reg dispatcher_headerLoaded; - reg [2:0] dispatcher_counter; - wire when_Fragment_l346; - wire when_Fragment_l349; - wire [66:0] _zz_io_mem_cmd_payload_address; - wire io_mem_cmd_isStall; - wire when_Fragment_l372; - - assign dispatcher_header = dispatcher_headerShifter[7 : 0]; - assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); - assign when_Fragment_l349 = (dispatcher_counter == 3'b111); - assign io_remote_cmd_ready = (! dispatcher_dataLoaded); - assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; - assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; - assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; - assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; - assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; - assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); - assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); - assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); - assign io_remote_rsp_valid = io_mem_rsp_valid; - assign io_remote_rsp_payload_error = 1'b0; - assign io_remote_rsp_payload_data = io_mem_rsp_payload; - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - dispatcher_dataLoaded <= 1'b0; - dispatcher_headerLoaded <= 1'b0; - dispatcher_counter <= 3'b000; - end else begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_counter <= (dispatcher_counter + 3'b001); - if(when_Fragment_l349) begin - dispatcher_headerLoaded <= 1'b1; - end - end - if(io_remote_cmd_payload_last) begin - dispatcher_headerLoaded <= 1'b1; - dispatcher_dataLoaded <= 1'b1; - dispatcher_counter <= 3'b000; - end - end - if(when_Fragment_l372) begin - dispatcher_headerLoaded <= 1'b0; - dispatcher_dataLoaded <= 1'b0; - end - end - end - - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); - end else begin - dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); - end - end - end - - -endmodule - -module JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_ctrl_tdi, - input io_ctrl_enable, - input io_ctrl_capture, - input io_ctrl_shift, - input io_ctrl_update, - input io_ctrl_reset, - output io_ctrl_tdo, - output io_remote_cmd_valid, - input io_remote_cmd_ready, - output io_remote_cmd_payload_last, - output [0:0] io_remote_cmd_payload_fragment, - input io_remote_rsp_valid, - output io_remote_rsp_ready, - input io_remote_rsp_payload_error, - input [31:0] io_remote_rsp_payload_data, - input io_systemClk, - input debugCd_logic_outputReset, - input jtagCtrl_tck -); - - wire flowCCByToggle_1_io_output_valid; - wire flowCCByToggle_1_io_output_payload_last; - wire [0:0] flowCCByToggle_1_io_output_payload_fragment; - wire system_cmd_valid; - wire system_cmd_payload_last; - wire [0:0] system_cmd_payload_fragment; - wire system_cmd_toStream_valid; - wire system_cmd_toStream_ready; - wire system_cmd_toStream_payload_last; - wire [0:0] system_cmd_toStream_payload_fragment; - (* async_reg = "true" *) reg system_rsp_valid; - (* async_reg = "true" *) reg system_rsp_payload_error; - (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; - wire io_remote_rsp_fire; - wire jtag_wrapper_ctrl_tdi; - wire jtag_wrapper_ctrl_enable; - wire jtag_wrapper_ctrl_capture; - wire jtag_wrapper_ctrl_shift; - wire jtag_wrapper_ctrl_update; - wire jtag_wrapper_ctrl_reset; - reg jtag_wrapper_ctrl_tdo; - reg [1:0] jtag_wrapper_header; - wire [1:0] jtag_wrapper_headerNext; - reg [0:0] jtag_wrapper_counter; - reg jtag_wrapper_done; - reg jtag_wrapper_sendCapture; - reg jtag_wrapper_sendShift; - reg jtag_wrapper_sendUpdate; - wire when_JtagTapInstructions_l183; - wire when_JtagTapInstructions_l186; - wire jtag_writeArea_ctrl_tdi; - wire jtag_writeArea_ctrl_enable; - wire jtag_writeArea_ctrl_capture; - wire jtag_writeArea_ctrl_shift; - wire jtag_writeArea_ctrl_update; - wire jtag_writeArea_ctrl_reset; - wire jtag_writeArea_ctrl_tdo; - wire jtag_writeArea_source_valid; - wire jtag_writeArea_source_payload_last; - wire [0:0] jtag_writeArea_source_payload_fragment; - reg jtag_writeArea_valid; - reg jtag_writeArea_data; - wire when_JtagTapInstructions_l209; - wire jtag_readArea_ctrl_tdi; - wire jtag_readArea_ctrl_enable; - wire jtag_readArea_ctrl_capture; - wire jtag_readArea_ctrl_shift; - wire jtag_readArea_ctrl_update; - wire jtag_readArea_ctrl_reset; - wire jtag_readArea_ctrl_tdo; - reg [33:0] jtag_readArea_full_shifter; - wire when_JtagTapInstructions_l209_1; - - FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b flowCCByToggle_1 ( - .io_input_valid (jtag_writeArea_source_valid ), //i - .io_input_payload_last (jtag_writeArea_source_payload_last ), //i - .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i - .io_output_valid (flowCCByToggle_1_io_output_valid ), //o - .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o - .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o - .jtagCtrl_tck (jtagCtrl_tck ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - assign system_cmd_toStream_valid = system_cmd_valid; - assign system_cmd_toStream_payload_last = system_cmd_payload_last; - assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; - assign io_remote_cmd_valid = system_cmd_toStream_valid; - assign system_cmd_toStream_ready = io_remote_cmd_ready; - assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; - assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; - assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); - assign io_remote_rsp_ready = 1'b1; - assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); - always @(*) begin - jtag_wrapper_sendCapture = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_sendCapture = 1'b1; - end - end - end - end - end - - always @(*) begin - jtag_wrapper_sendShift = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(!when_JtagTapInstructions_l183) begin - jtag_wrapper_sendShift = 1'b1; - end - end - end - end - - always @(*) begin - jtag_wrapper_sendUpdate = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_update) begin - jtag_wrapper_sendUpdate = 1'b1; - end - end - end - - assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); - assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); - always @(*) begin - jtag_wrapper_ctrl_tdo = 1'b0; - if(when_JtagTapInstructions_l209) begin - jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; - end - if(when_JtagTapInstructions_l209_1) begin - jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; - end - end - - assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; - assign jtag_wrapper_ctrl_enable = io_ctrl_enable; - assign jtag_wrapper_ctrl_capture = io_ctrl_capture; - assign jtag_wrapper_ctrl_shift = io_ctrl_shift; - assign jtag_wrapper_ctrl_update = io_ctrl_update; - assign jtag_wrapper_ctrl_reset = io_ctrl_reset; - assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; - assign jtag_writeArea_source_valid = jtag_writeArea_valid; - assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); - assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; - assign system_cmd_valid = flowCCByToggle_1_io_output_valid; - assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; - assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; - assign jtag_writeArea_ctrl_tdo = 1'b0; - assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); - assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_writeArea_ctrl_enable = 1'b1; - assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); - assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); - assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); - assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; - assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; - assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); - assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_readArea_ctrl_enable = 1'b1; - assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); - assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); - assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); - assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - system_rsp_valid <= 1'b0; - end - if(io_remote_rsp_fire) begin - system_rsp_valid <= 1'b1; - system_rsp_payload_error <= io_remote_rsp_payload_error; - system_rsp_payload_data <= io_remote_rsp_payload_data; - end - end - - always @(posedge jtagCtrl_tck) begin - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_capture) begin - jtag_wrapper_done <= 1'b0; - jtag_wrapper_counter <= 1'b0; - end - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); - jtag_wrapper_header <= jtag_wrapper_headerNext; - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_done <= 1'b1; - end - end - end - end - jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); - jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; - if(jtag_readArea_ctrl_enable) begin - if(jtag_readArea_ctrl_capture) begin - jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; - end - if(jtag_readArea_ctrl_shift) begin - jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); - end - end - end - - -endmodule - -module VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b ( - output dBus_cmd_valid, - input dBus_cmd_ready, - output dBus_cmd_payload_wr, - output dBus_cmd_payload_uncached, - output [31:0] dBus_cmd_payload_address, - output [31:0] dBus_cmd_payload_data, - output [3:0] dBus_cmd_payload_mask, - output [2:0] dBus_cmd_payload_size, - output dBus_cmd_payload_last, - input dBus_rsp_valid, - input dBus_rsp_payload_last, - input [31:0] dBus_rsp_payload_data, - input dBus_rsp_payload_error, - input timerInterrupt, - input externalInterrupt, - input softwareInterrupt, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBus_cmd_valid, - input iBus_cmd_ready, - output reg [31:0] iBus_cmd_payload_address, - output [2:0] iBus_cmd_payload_size, - input iBus_rsp_valid, - input [31:0] iBus_rsp_payload_data, - input iBus_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset, - input debugCd_logic_outputReset -); - localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; - localparam ShiftCtrlEnum_SLL_1 = 2'd1; - localparam ShiftCtrlEnum_SRL_1 = 2'd2; - localparam ShiftCtrlEnum_SRA_1 = 2'd3; - localparam BranchCtrlEnum_INC = 2'd0; - localparam BranchCtrlEnum_B = 2'd1; - localparam BranchCtrlEnum_JAL = 2'd2; - localparam BranchCtrlEnum_JALR = 2'd3; - localparam EnvCtrlEnum_NONE = 2'd0; - localparam EnvCtrlEnum_XRET = 2'd1; - localparam EnvCtrlEnum_ECALL = 2'd2; - localparam EnvCtrlEnum_EBREAK = 2'd3; - localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; - localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; - localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; - localparam AluCtrlEnum_ADD_SUB = 2'd0; - localparam AluCtrlEnum_SLT_SLTU = 2'd1; - localparam AluCtrlEnum_BITWISE = 2'd2; - localparam Src2CtrlEnum_RS = 2'd0; - localparam Src2CtrlEnum_IMI = 2'd1; - localparam Src2CtrlEnum_IMS = 2'd2; - localparam Src2CtrlEnum_PC = 2'd3; - localparam Src1CtrlEnum_RS = 2'd0; - localparam Src1CtrlEnum_IMU = 2'd1; - localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; - localparam Src1CtrlEnum_URS1 = 2'd3; - - wire IBusCachedPlugin_cache_io_flush; - wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; - wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; - wire IBusCachedPlugin_cache_io_cpu_decode_isValid; - wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; - wire IBusCachedPlugin_cache_io_cpu_decode_isUser; - reg IBusCachedPlugin_cache_io_cpu_fill_valid; - wire dataCache_1_io_cpu_execute_isValid; - wire [31:0] dataCache_1_io_cpu_execute_address; - wire dataCache_1_io_cpu_memory_isValid; - reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; - reg dataCache_1_io_cpu_writeBack_isValid; - wire dataCache_1_io_cpu_writeBack_isUser; - wire [31:0] dataCache_1_io_cpu_writeBack_storeData; - wire [31:0] dataCache_1_io_cpu_writeBack_address; - wire dataCache_1_io_cpu_writeBack_fence_SW; - wire dataCache_1_io_cpu_writeBack_fence_SR; - wire dataCache_1_io_cpu_writeBack_fence_SO; - wire dataCache_1_io_cpu_writeBack_fence_SI; - wire dataCache_1_io_cpu_writeBack_fence_PW; - wire dataCache_1_io_cpu_writeBack_fence_PR; - wire dataCache_1_io_cpu_writeBack_fence_PO; - wire dataCache_1_io_cpu_writeBack_fence_PI; - wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; - wire dataCache_1_io_cpu_flush_valid; - wire dataCache_1_io_cpu_flush_payload_singleLine; - wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; - wire dataCache_1_io_mem_cmd_ready; - reg [31:0] _zz_RegFilePlugin_regFile_port0; - reg [31:0] _zz_RegFilePlugin_regFile_port1; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1_io_cpu_execute_haltIt; - wire dataCache_1_io_cpu_execute_refilling; - wire dataCache_1_io_cpu_memory_isWrite; - wire dataCache_1_io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1_io_cpu_writeBack_data; - wire dataCache_1_io_cpu_writeBack_mmuException; - wire dataCache_1_io_cpu_writeBack_unalignedAccess; - wire dataCache_1_io_cpu_writeBack_accessError; - wire dataCache_1_io_cpu_writeBack_isWrite; - wire dataCache_1_io_cpu_writeBack_keepMemRspData; - wire dataCache_1_io_cpu_writeBack_exclusiveOk; - wire dataCache_1_io_cpu_flush_ready; - wire dataCache_1_io_cpu_redo; - wire dataCache_1_io_mem_cmd_valid; - wire dataCache_1_io_mem_cmd_payload_wr; - wire dataCache_1_io_mem_cmd_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_size; - wire dataCache_1_io_mem_cmd_payload_last; - wire [51:0] _zz_memory_MUL_LOW; - wire [51:0] _zz_memory_MUL_LOW_1; - wire [51:0] _zz_memory_MUL_LOW_2; - wire [51:0] _zz_memory_MUL_LOW_3; - wire [32:0] _zz_memory_MUL_LOW_4; - wire [51:0] _zz_memory_MUL_LOW_5; - wire [49:0] _zz_memory_MUL_LOW_6; - wire [51:0] _zz_memory_MUL_LOW_7; - wire [49:0] _zz_memory_MUL_LOW_8; - wire [31:0] _zz_execute_SHIFT_RIGHT; - wire [32:0] _zz_execute_SHIFT_RIGHT_1; - wire [32:0] _zz_execute_SHIFT_RIGHT_2; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; - wire _zz_decode_LEGAL_INSTRUCTION_3; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; - wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; - wire _zz_decode_LEGAL_INSTRUCTION_9; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; - wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; - wire _zz_decode_LEGAL_INSTRUCTION_15; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; - wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; - wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; - reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; - wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; - wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; - wire [25:0] _zz_io_cpu_flush_payload_lineId; - wire [25:0] _zz_io_cpu_flush_payload_lineId_1; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; - wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; - wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; - wire _zz__zz_decode_BRANCH_CTRL_2_5; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; - wire _zz__zz_decode_BRANCH_CTRL_2_9; - wire _zz__zz_decode_BRANCH_CTRL_2_10; - wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; - wire _zz__zz_decode_BRANCH_CTRL_2_13; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; - wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; - wire _zz__zz_decode_BRANCH_CTRL_2_26; - wire _zz__zz_decode_BRANCH_CTRL_2_27; - wire _zz__zz_decode_BRANCH_CTRL_2_28; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; - wire _zz__zz_decode_BRANCH_CTRL_2_32; - wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; - wire _zz__zz_decode_BRANCH_CTRL_2_36; - wire _zz__zz_decode_BRANCH_CTRL_2_37; - wire _zz__zz_decode_BRANCH_CTRL_2_38; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; - wire _zz__zz_decode_BRANCH_CTRL_2_40; - wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; - wire _zz__zz_decode_BRANCH_CTRL_2_47; - wire _zz__zz_decode_BRANCH_CTRL_2_48; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; - wire _zz__zz_decode_BRANCH_CTRL_2_54; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; - wire _zz__zz_decode_BRANCH_CTRL_2_57; - wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; - wire _zz__zz_decode_BRANCH_CTRL_2_66; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; - wire _zz__zz_decode_BRANCH_CTRL_2_68; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; - wire _zz__zz_decode_BRANCH_CTRL_2_70; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; - wire _zz__zz_decode_BRANCH_CTRL_2_75; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; - wire _zz__zz_decode_BRANCH_CTRL_2_86; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; - wire _zz__zz_decode_BRANCH_CTRL_2_92; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; - wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; - wire _zz__zz_decode_BRANCH_CTRL_2_99; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; - wire _zz__zz_decode_BRANCH_CTRL_2_101; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; - wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; - wire _zz__zz_decode_BRANCH_CTRL_2_111; - wire _zz__zz_decode_BRANCH_CTRL_2_112; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; - wire _zz__zz_decode_BRANCH_CTRL_2_125; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; - wire _zz__zz_decode_BRANCH_CTRL_2_140; - wire _zz__zz_decode_BRANCH_CTRL_2_141; - wire _zz__zz_decode_BRANCH_CTRL_2_142; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; - wire _zz_RegFilePlugin_regFile_port; - wire _zz_decode_RegFilePlugin_rs1Data; - wire _zz_RegFilePlugin_regFile_port_1; - wire _zz_decode_RegFilePlugin_rs2Data; - wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; - wire [2:0] _zz__zz_decode_SRC1_1; - wire [4:0] _zz__zz_decode_SRC1_1_1; - wire [11:0] _zz__zz_decode_SRC2_4; - wire [31:0] _zz_execute_SrcPlugin_addSub; - wire [31:0] _zz_execute_SrcPlugin_addSub_1; - wire [31:0] _zz_execute_SrcPlugin_addSub_2; - wire [31:0] _zz_execute_SrcPlugin_addSub_3; - wire [31:0] _zz_execute_SrcPlugin_addSub_4; - wire [31:0] _zz_execute_SrcPlugin_addSub_5; - wire [31:0] _zz_execute_SrcPlugin_addSub_6; - wire [65:0] _zz_writeBack_MulPlugin_result; - wire [65:0] _zz_writeBack_MulPlugin_result_1; - wire [31:0] _zz__zz_decode_RS2_2; - wire [31:0] _zz__zz_decode_RS2_2_1; - wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; - wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; - wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; - wire _zz_when; - wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; - wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; - wire [51:0] memory_MUL_LOW; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire [33:0] execute_MUL_HL; - wire [33:0] execute_MUL_LH; - wire [31:0] execute_MUL_LL; - wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; - wire [31:0] memory_MEMORY_STORE_DATA_RF; - wire [31:0] execute_MEMORY_STORE_DATA_RF; - wire decode_DO_EBREAK; - wire decode_CSR_READ_OPCODE; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] decode_SRC2; - wire [31:0] decode_SRC1; - wire decode_SRC2_FORCE_ZERO; - wire [1:0] decode_BRANCH_CTRL; - wire [1:0] _zz_decode_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; - wire [1:0] _zz_execute_to_memory_ENV_CTRL; - wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; - wire [1:0] decode_ENV_CTRL; - wire [1:0] _zz_decode_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; - wire decode_IS_CSR; - wire decode_IS_RS2_SIGNED; - wire decode_IS_RS1_SIGNED; - wire decode_IS_DIV; - wire memory_IS_MUL; - wire decode_IS_MUL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; - wire [1:0] decode_SHIFT_CTRL; - wire [1:0] _zz_decode_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; - wire [1:0] decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_MANAGMENT; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [1:0] decode_ALU_CTRL; - wire [1:0] _zz_decode_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; - wire decode_MEMORY_FORCE_CONSTISTENCY; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [31:0] memory_PC; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] execute_PC; - wire [1:0] execute_BRANCH_CTRL; - wire [1:0] _zz_execute_BRANCH_CTRL; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire [1:0] memory_ENV_CTRL; - wire [1:0] _zz_memory_ENV_CTRL; - wire [1:0] execute_ENV_CTRL; - wire [1:0] _zz_execute_ENV_CTRL; - wire [1:0] writeBack_ENV_CTRL; - wire [1:0] _zz_writeBack_ENV_CTRL; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire execute_IS_MUL; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_decode_RS2; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_decode_RS2_1; - wire [1:0] memory_SHIFT_CTRL; - wire [1:0] _zz_memory_SHIFT_CTRL; - wire [1:0] execute_SHIFT_CTRL; - wire [1:0] _zz_execute_SHIFT_CTRL; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_decode_SRC2; - wire [31:0] _zz_decode_SRC2_1; - wire [1:0] decode_SRC2_CTRL; - wire [1:0] _zz_decode_SRC2_CTRL; - wire [31:0] _zz_decode_SRC1; - wire [1:0] decode_SRC1_CTRL; - wire [1:0] _zz_decode_SRC1_CTRL; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire [1:0] execute_ALU_CTRL; - wire [1:0] _zz_execute_ALU_CTRL; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire [1:0] execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_execute_ALU_BITWISE_CTRL; - wire [31:0] _zz_lastStageRegFileWrite_payload_address; - wire _zz_lastStageRegFileWrite_valid; - reg _zz_1; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire [1:0] _zz_decode_BRANCH_CTRL_1; - wire [1:0] _zz_decode_ENV_CTRL_1; - wire [1:0] _zz_decode_SHIFT_CTRL_1; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; - wire [1:0] _zz_decode_SRC2_CTRL_1; - wire [1:0] _zz_decode_ALU_CTRL_1; - wire [1:0] _zz_decode_SRC1_CTRL_1; - reg [31:0] _zz_decode_RS2_2; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_MEMORY_STORE_DATA_RF; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire memory_MEMORY_ENABLE; - wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; - wire execute_MEMORY_FORCE_CONSTISTENCY; - (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_MANAGMENT; - (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected_4; - reg IBusCachedPlugin_rsp_issueDetected_3; - reg IBusCachedPlugin_rsp_issueDetected_2; - reg IBusCachedPlugin_rsp_issueDetected_1; - reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; - wire [31:0] decode_PC; - wire [31:0] decode_INSTRUCTION; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - wire IBusCachedPlugin_forceNoDecodeCond; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_0_isValid; - wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_isPaging; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_0_isValid; - wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_isPaging; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_when_DBusCachedPlugin_l393; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire [31:0] CsrPlugin_csrMapping_readDataSignal; - wire [31:0] CsrPlugin_csrMapping_readDataInit; - wire [31:0] CsrPlugin_csrMapping_writeDataSignal; - wire CsrPlugin_csrMapping_allowCsrSignal; - wire CsrPlugin_csrMapping_hazardFree; - wire CsrPlugin_inWfi /* verilator public */ ; - reg CsrPlugin_thirdPartyWake; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg CsrPlugin_allowEbreakException; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg BranchPlugin_inDebugNoFetchFlag; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_externalFlush; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_correction; - reg IBusCachedPlugin_fetchPc_correctionReg; - wire IBusCachedPlugin_fetchPc_output_fire; - wire IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - wire when_Fetcher_l134; - wire IBusCachedPlugin_fetchPc_output_fire_1; - wire when_Fetcher_l134_1; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_fetchPc_redo_valid; - wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; - reg IBusCachedPlugin_fetchPc_flushed; - wire when_Fetcher_l161; - reg IBusCachedPlugin_iBusRsp_redoFetch; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_output_valid; - wire IBusCachedPlugin_iBusRsp_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; - wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; - wire when_Fetcher_l243; - wire IBusCachedPlugin_injector_decodeInput_valid; - wire IBusCachedPlugin_injector_decodeInput_ready; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; - wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_IBusCachedPlugin_injector_decodeInput_valid; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - wire when_Fetcher_l323; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - wire when_Fetcher_l332; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - wire when_Fetcher_l332_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - wire when_Fetcher_l332_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - wire when_Fetcher_l332_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire when_Fetcher_l332_4; - reg IBusCachedPlugin_injector_nextPcCalc_valids_5; - wire when_Fetcher_l332_5; - reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - wire IBusCachedPlugin_rsp_issueDetected; - reg IBusCachedPlugin_rsp_redoFetch; - wire when_IBusCachedPlugin_l239; - wire when_IBusCachedPlugin_l244; - wire when_IBusCachedPlugin_l250; - wire when_IBusCachedPlugin_l256; - wire when_IBusCachedPlugin_l267; - wire dataCache_1_io_mem_cmd_s2mPipe_valid; - reg dataCache_1_io_mem_cmd_s2mPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_rValid; - reg dataCache_1_io_mem_cmd_rData_wr; - reg dataCache_1_io_mem_cmd_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_rData_size; - reg dataCache_1_io_mem_cmd_rData_last; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; - wire when_Stream_l368; - reg dBus_rsp_regNext_valid; - reg dBus_rsp_regNext_payload_last; - reg [31:0] dBus_rsp_regNext_payload_data; - reg dBus_rsp_regNext_payload_error; - reg [31:0] DBusCachedPlugin_rspCounter; - wire when_DBusCachedPlugin_l308; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; - wire dataCache_1_io_cpu_flush_isStall; - wire when_DBusCachedPlugin_l350; - wire when_DBusCachedPlugin_l366; - wire when_DBusCachedPlugin_l393; - wire when_DBusCachedPlugin_l446; - wire when_DBusCachedPlugin_l466; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire [31:0] writeBack_DBusCachedPlugin_rspRf; - wire [1:0] switch_Misc_l210; - wire _zz_writeBack_DBusCachedPlugin_rspFormated; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; - wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire when_DBusCachedPlugin_l492; - wire [32:0] _zz_decode_BRANCH_CTRL_2; - wire _zz_decode_BRANCH_CTRL_3; - wire _zz_decode_BRANCH_CTRL_4; - wire _zz_decode_BRANCH_CTRL_5; - wire _zz_decode_BRANCH_CTRL_6; - wire _zz_decode_BRANCH_CTRL_7; - wire _zz_decode_BRANCH_CTRL_8; - wire [1:0] _zz_decode_SRC1_CTRL_2; - wire [1:0] _zz_decode_ALU_CTRL_2; - wire [1:0] _zz_decode_SRC2_CTRL_2; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; - wire [1:0] _zz_decode_SHIFT_CTRL_2; - wire [1:0] _zz_decode_ENV_CTRL_2; - wire [1:0] _zz_decode_BRANCH_CTRL_9; - wire when_RegFilePlugin_l63; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_2; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_execute_REGFILE_WRITE_DATA; - reg [31:0] _zz_decode_SRC1_1; - wire _zz_decode_SRC2_2; - reg [19:0] _zz_decode_SRC2_3; - wire _zz_decode_SRC2_4; - reg [19:0] _zz_decode_SRC2_5; - reg [31:0] _zz_decode_SRC2_6; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_decode_RS2_3; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire when_HazardSimplePlugin_l47; - wire when_HazardSimplePlugin_l48; - wire when_HazardSimplePlugin_l51; - wire when_HazardSimplePlugin_l45; - wire when_HazardSimplePlugin_l57; - wire when_HazardSimplePlugin_l58; - wire when_HazardSimplePlugin_l48_1; - wire when_HazardSimplePlugin_l51_1; - wire when_HazardSimplePlugin_l45_1; - wire when_HazardSimplePlugin_l57_1; - wire when_HazardSimplePlugin_l58_1; - wire when_HazardSimplePlugin_l48_2; - wire when_HazardSimplePlugin_l51_2; - wire when_HazardSimplePlugin_l45_2; - wire when_HazardSimplePlugin_l57_2; - wire when_HazardSimplePlugin_l58_2; - wire when_HazardSimplePlugin_l105; - wire when_HazardSimplePlugin_l108; - wire when_HazardSimplePlugin_l113; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - reg [0:0] execute_MulPlugin_delayLogic_counter; - wire when_MulPlugin_l65; - wire when_MulPlugin_l70; - wire [1:0] switch_MulPlugin_l87; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; - wire [65:0] writeBack_MulPlugin_result; - wire when_MulPlugin_l147; - wire [1:0] switch_MulPlugin_l148; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - wire when_MulDivIterativePlugin_l126; - wire when_MulDivIterativePlugin_l126_1; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l128; - wire when_MulDivIterativePlugin_l129; - wire when_MulDivIterativePlugin_l132; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire when_MulDivIterativePlugin_l151; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l162; - wire _zz_memory_MulDivIterativePlugin_rs2; - wire _zz_memory_MulDivIterativePlugin_rs1; - reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle; - reg [63:0] CsrPlugin_minstret; - wire _zz_when_CsrPlugin_l965; - wire _zz_when_CsrPlugin_l965_1; - wire _zz_when_CsrPlugin_l965_2; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; - wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire when_CsrPlugin_l922; - wire when_CsrPlugin_l922_1; - wire when_CsrPlugin_l922_2; - wire when_CsrPlugin_l922_3; - wire when_CsrPlugin_l935; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire when_CsrPlugin_l959; - wire when_CsrPlugin_l965; - wire when_CsrPlugin_l965_1; - wire when_CsrPlugin_l965_2; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_pcValids_0; - reg CsrPlugin_pipelineLiberator_pcValids_1; - reg CsrPlugin_pipelineLiberator_pcValids_2; - wire CsrPlugin_pipelineLiberator_active; - wire when_CsrPlugin_l993; - wire when_CsrPlugin_l993_1; - wire when_CsrPlugin_l993_2; - wire when_CsrPlugin_l998; - reg CsrPlugin_pipelineLiberator_done; - wire when_CsrPlugin_l1004; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException /* verilator public */ ; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire when_CsrPlugin_l1032; - wire when_CsrPlugin_l1077; - wire [1:0] switch_CsrPlugin_l1081; - reg execute_CsrPlugin_wfiWake; - wire when_CsrPlugin_l1129; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - wire when_CsrPlugin_l1142; - wire when_CsrPlugin_l1149; - wire when_CsrPlugin_l1150; - wire when_CsrPlugin_l1157; - wire when_CsrPlugin_l1167; - reg execute_CsrPlugin_writeInstruction; - reg execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - wire switch_Misc_l210_1; - reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; - wire when_CsrPlugin_l1189; - wire when_CsrPlugin_l1193; - wire [11:0] execute_CsrPlugin_csrAddress; - wire execute_BranchPlugin_eq; - wire [2:0] switch_Misc_l210_2; - reg _zz_execute_BRANCH_DO; - reg _zz_execute_BRANCH_DO_1; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_execute_BranchPlugin_branch_src2; - reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; - wire _zz_execute_BranchPlugin_branch_src2_2; - reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; - wire _zz_execute_BranchPlugin_branch_src2_4; - reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; - reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - wire when_DebugPlugin_l225; - reg DebugPlugin_haltedByBreak; - reg DebugPlugin_debugUsed /* verilator public */ ; - reg DebugPlugin_disableEbreak; - wire DebugPlugin_allowEBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_when_DebugPlugin_l244; - wire when_DebugPlugin_l244; - wire [5:0] switch_DebugPlugin_l267; - wire when_DebugPlugin_l271; - wire when_DebugPlugin_l271_1; - wire when_DebugPlugin_l272; - wire when_DebugPlugin_l272_1; - wire when_DebugPlugin_l273; - wire when_DebugPlugin_l274; - wire when_DebugPlugin_l275; - wire when_DebugPlugin_l275_1; - wire when_DebugPlugin_l295; - wire when_DebugPlugin_l298; - wire when_DebugPlugin_l311; - reg DebugPlugin_resetIt_regNext; - wire when_DebugPlugin_l331; - wire when_Pipeline_l124; - reg [31:0] decode_to_execute_PC; - wire when_Pipeline_l124_1; - reg [31:0] execute_to_memory_PC; - wire when_Pipeline_l124_2; - reg [31:0] memory_to_writeBack_PC; - wire when_Pipeline_l124_3; - reg [31:0] decode_to_execute_INSTRUCTION; - wire when_Pipeline_l124_4; - reg [31:0] execute_to_memory_INSTRUCTION; - wire when_Pipeline_l124_5; - reg [31:0] memory_to_writeBack_INSTRUCTION; - wire when_Pipeline_l124_6; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - wire when_Pipeline_l124_7; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - wire when_Pipeline_l124_8; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - wire when_Pipeline_l124_9; - reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - wire when_Pipeline_l124_10; - reg decode_to_execute_SRC_USE_SUB_LESS; - wire when_Pipeline_l124_11; - reg decode_to_execute_MEMORY_ENABLE; - wire when_Pipeline_l124_12; - reg execute_to_memory_MEMORY_ENABLE; - wire when_Pipeline_l124_13; - reg memory_to_writeBack_MEMORY_ENABLE; - wire when_Pipeline_l124_14; - reg [1:0] decode_to_execute_ALU_CTRL; - wire when_Pipeline_l124_15; - reg decode_to_execute_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_16; - reg execute_to_memory_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_17; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_18; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - wire when_Pipeline_l124_19; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_20; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_21; - reg decode_to_execute_MEMORY_WR; - wire when_Pipeline_l124_22; - reg execute_to_memory_MEMORY_WR; - wire when_Pipeline_l124_23; - reg memory_to_writeBack_MEMORY_WR; - wire when_Pipeline_l124_24; - reg decode_to_execute_MEMORY_MANAGMENT; - wire when_Pipeline_l124_25; - reg decode_to_execute_SRC_LESS_UNSIGNED; - wire when_Pipeline_l124_26; - reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; - wire when_Pipeline_l124_27; - reg [1:0] decode_to_execute_SHIFT_CTRL; - wire when_Pipeline_l124_28; - reg [1:0] execute_to_memory_SHIFT_CTRL; - wire when_Pipeline_l124_29; - reg decode_to_execute_IS_MUL; - wire when_Pipeline_l124_30; - reg execute_to_memory_IS_MUL; - wire when_Pipeline_l124_31; - reg memory_to_writeBack_IS_MUL; - wire when_Pipeline_l124_32; - reg decode_to_execute_IS_DIV; - wire when_Pipeline_l124_33; - reg execute_to_memory_IS_DIV; - wire when_Pipeline_l124_34; - reg decode_to_execute_IS_RS1_SIGNED; - wire when_Pipeline_l124_35; - reg decode_to_execute_IS_RS2_SIGNED; - wire when_Pipeline_l124_36; - reg decode_to_execute_IS_CSR; - wire when_Pipeline_l124_37; - reg [1:0] decode_to_execute_ENV_CTRL; - wire when_Pipeline_l124_38; - reg [1:0] execute_to_memory_ENV_CTRL; - wire when_Pipeline_l124_39; - reg [1:0] memory_to_writeBack_ENV_CTRL; - wire when_Pipeline_l124_40; - reg [1:0] decode_to_execute_BRANCH_CTRL; - wire when_Pipeline_l124_41; - reg [31:0] decode_to_execute_RS1; - wire when_Pipeline_l124_42; - reg [31:0] decode_to_execute_RS2; - wire when_Pipeline_l124_43; - reg decode_to_execute_SRC2_FORCE_ZERO; - wire when_Pipeline_l124_44; - reg [31:0] decode_to_execute_SRC1; - wire when_Pipeline_l124_45; - reg [31:0] decode_to_execute_SRC2; - wire when_Pipeline_l124_46; - reg decode_to_execute_CSR_WRITE_OPCODE; - wire when_Pipeline_l124_47; - reg decode_to_execute_CSR_READ_OPCODE; - wire when_Pipeline_l124_48; - reg decode_to_execute_DO_EBREAK; - wire when_Pipeline_l124_49; - reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_50; - reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_51; - (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; - wire when_Pipeline_l124_52; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_53; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_54; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - wire when_Pipeline_l124_55; - reg [31:0] execute_to_memory_MUL_LL; - wire when_Pipeline_l124_56; - reg [33:0] execute_to_memory_MUL_LH; - wire when_Pipeline_l124_57; - reg [33:0] execute_to_memory_MUL_HL; - wire when_Pipeline_l124_58; - reg [33:0] execute_to_memory_MUL_HH; - wire when_Pipeline_l124_59; - reg [33:0] memory_to_writeBack_MUL_HH; - wire when_Pipeline_l124_60; - reg execute_to_memory_BRANCH_DO; - wire when_Pipeline_l124_61; - reg [31:0] execute_to_memory_BRANCH_CALC; - wire when_Pipeline_l124_62; - reg [51:0] memory_to_writeBack_MUL_LOW; - wire when_Pipeline_l151; - wire when_Pipeline_l154; - wire when_Pipeline_l151_1; - wire when_Pipeline_l154_1; - wire when_Pipeline_l151_2; - wire when_Pipeline_l154_2; - reg [2:0] switch_Fetcher_l365; - wire when_Fetcher_l381; - wire when_Fetcher_l401; - wire when_CsrPlugin_l1277; - reg execute_CsrPlugin_csr_3860; - wire when_CsrPlugin_l1277_1; - reg execute_CsrPlugin_csr_769; - wire when_CsrPlugin_l1277_2; - reg execute_CsrPlugin_csr_768; - wire when_CsrPlugin_l1277_3; - reg execute_CsrPlugin_csr_836; - wire when_CsrPlugin_l1277_4; - reg execute_CsrPlugin_csr_772; - wire when_CsrPlugin_l1277_5; - reg execute_CsrPlugin_csr_773; - wire when_CsrPlugin_l1277_6; - reg execute_CsrPlugin_csr_833; - wire when_CsrPlugin_l1277_7; - reg execute_CsrPlugin_csr_832; - wire when_CsrPlugin_l1277_8; - reg execute_CsrPlugin_csr_834; - wire when_CsrPlugin_l1277_9; - reg execute_CsrPlugin_csr_835; - wire [1:0] switch_CsrPlugin_l723; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; - wire when_CsrPlugin_l1310; - wire when_CsrPlugin_l1315; - `ifndef SYNTHESIS - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; - reg [47:0] decode_ENV_CTRL_string; - reg [47:0] _zz_decode_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_decode_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_execute_BRANCH_CTRL_string; - reg [47:0] memory_ENV_CTRL_string; - reg [47:0] _zz_memory_ENV_CTRL_string; - reg [47:0] execute_ENV_CTRL_string; - reg [47:0] _zz_execute_ENV_CTRL_string; - reg [47:0] writeBack_ENV_CTRL_string; - reg [47:0] _zz_writeBack_ENV_CTRL_string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_memory_SHIFT_CTRL_string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_execute_SHIFT_CTRL_string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_decode_SRC2_CTRL_string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_decode_SRC1_CTRL_string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_execute_ALU_CTRL_string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_1_string; - reg [47:0] _zz_decode_ENV_CTRL_1_string; - reg [71:0] _zz_decode_SHIFT_CTRL_1_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; - reg [23:0] _zz_decode_SRC2_CTRL_1_string; - reg [63:0] _zz_decode_ALU_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_2_string; - reg [63:0] _zz_decode_ALU_CTRL_2_string; - reg [23:0] _zz_decode_SRC2_CTRL_2_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; - reg [71:0] _zz_decode_SHIFT_CTRL_2_string; - reg [47:0] _zz_decode_ENV_CTRL_2_string; - reg [31:0] _zz_decode_BRANCH_CTRL_9_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [47:0] decode_to_execute_ENV_CTRL_string; - reg [47:0] execute_to_memory_ENV_CTRL_string; - reg [47:0] memory_to_writeBack_ENV_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - `endif - - reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - - assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); - assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); - assign _zz_memory_MUL_LOW_2 = 52'h0; - assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; - assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; - assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; - assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; - assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; - assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); - assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; - assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; - assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; - assign _zz__zz_decode_SRC1_1 = 3'b100; - assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; - assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); - assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); - assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; - assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); - assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; - assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; - assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; - assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; - assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; - assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); - assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; - assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; - assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; - assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; - assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); - assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; - assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; - assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; - assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; - assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; - assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; - assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; - assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; - assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); - assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); - assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); - assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; - assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; - assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); - assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); - assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; - assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); - assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; - assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); - assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); - assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; - assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); - assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); - assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; - assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; - assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); - assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; - assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; - assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); - assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); - assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; - assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); - assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; - assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); - assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); - assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); - assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); - assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); - assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; - assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); - assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); - assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; - assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); - assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; - assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); - assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; - assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; - assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; - assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; - assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); - assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); - assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; - assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; - assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); - assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; - assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); - assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); - assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); - assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); - assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; - assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; - assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); - assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); - assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); - assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); - assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; - assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; - assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; - assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; - assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); - assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; - assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); - assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; - assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); - assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; - assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); - assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; - assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); - assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); - assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; - assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; - assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; - assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); - assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; - assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; - assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; - assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); - assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); - assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; - assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); - assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; - assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); - assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; - assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; - assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); - assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); - assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; - assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); - assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); - assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs1Data) begin - _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs2Data) begin - _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b IBusCachedPlugin_cache ( - .io_flush (IBusCachedPlugin_cache_io_flush ), //i - .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i - .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i - .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i - .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i - .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - DataCache_b62b14ffe6bb44e5a817b8d08e286c6b dataCache_1 ( - .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i - .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i - .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i - .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i - .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i - .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i - .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i - .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i - .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i - .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i - .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i - .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i - .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i - .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) - 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; - 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; - default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) - 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; - 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; - 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; - default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) - 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; - default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - `ifndef SYNTHESIS - always @(*) begin - case(decode_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; - default : decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; - default : memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; - default : execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; - default : writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; - default : _zz_decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_1) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; - default : _zz_decode_SRC2_CTRL_1_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_1) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_1_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_2) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_2_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_2) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_2_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_2) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; - default : _zz_decode_SRC2_CTRL_2_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_2) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_2) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_2) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_2_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_9) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_9_string = "????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - `endif - - assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; - assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; - assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; - assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; - assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; - assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; - assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; - assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; - assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); - assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); - assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); - assign decode_SRC2 = _zz_decode_SRC2_6; - assign decode_SRC1 = _zz_decode_SRC1_1; - assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; - assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; - assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; - assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; - assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; - assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; - assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; - assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; - assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; - assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; - assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; - assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; - assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; - assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; - assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; - assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign memory_PC = execute_to_memory_PC; - assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; - assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; - assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; - assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; - assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; - assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; - assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; - assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; - assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; - assign memory_MUL_HL = execute_to_memory_MUL_HL; - assign memory_MUL_LH = execute_to_memory_MUL_LH; - assign memory_MUL_LL = execute_to_memory_MUL_LL; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; - assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; - always @(*) begin - _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; - if(when_CsrPlugin_l1189) begin - _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; - end - end - - assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @(*) begin - decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr1Match) begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l51) begin - decode_RS2 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l51_1) begin - decode_RS2 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l51_2) begin - decode_RS2 = _zz_decode_RS2; - end - end - end - end - - always @(*) begin - decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr0Match) begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l48) begin - decode_RS1 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l48_1) begin - decode_RS1 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l48_2) begin - decode_RS1 = _zz_decode_RS2; - end - end - end - end - - assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @(*) begin - _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_SLL_1 : begin - _zz_decode_RS2_1 = _zz_decode_RS2_3; - end - ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin - _zz_decode_RS2_1 = memory_SHIFT_RIGHT; - end - default : begin - end - endcase - end - if(when_MulDivIterativePlugin_l128) begin - _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; - end - end - - assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; - assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; - assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; - assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; - assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_decode_SRC2 = decode_PC; - assign _zz_decode_SRC2_1 = decode_RS2; - assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; - assign _zz_decode_SRC1 = decode_RS1; - assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; - assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; - assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; - assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; - assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; - assign execute_SRC2 = decode_to_execute_SRC2; - assign execute_SRC1 = decode_to_execute_SRC1; - assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; - assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; - assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; - always @(*) begin - _zz_1 = 1'b0; - if(lastStageRegFileWrite_valid) begin - _zz_1 = 1'b1; - end - end - - assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); - always @(*) begin - decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; - if(when_RegFilePlugin_l63) begin - decode_REGFILE_WRITE_VALID = 1'b0; - end - end - - assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); - always @(*) begin - _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; - if(when_DBusCachedPlugin_l492) begin - _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; - end - if(when_MulPlugin_l147) begin - case(switch_MulPlugin_l148) - 2'b00 : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; - end - default : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; - end - endcase - end - end - - assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; - assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; - assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - assign execute_RS1 = decode_to_execute_RS1; - assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; - assign execute_RS2 = decode_to_execute_RS2; - assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = execute_SrcPlugin_addSub; - assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; - assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; - end - end - - always @(*) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; - end - end - - assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; - assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @(*) begin - decode_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l308) begin - decode_arbitration_haltItself = 1'b1; - end - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_haltItself = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - decode_arbitration_haltByOther = 1'b0; - if(when_HazardSimplePlugin_l113) begin - decode_arbitration_haltByOther = 1'b1; - end - if(CsrPlugin_pipelineLiberator_active) begin - decode_arbitration_haltByOther = 1'b1; - end - if(when_CsrPlugin_l1129) begin - decode_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - decode_arbitration_removeIt = 1'b0; - if(_zz_when) begin - decode_arbitration_removeIt = 1'b1; - end - if(decode_arbitration_isFlushed) begin - decode_arbitration_removeIt = 1'b1; - end - end - - assign decode_arbitration_flushIt = 1'b0; - always @(*) begin - decode_arbitration_flushNext = 1'b0; - if(_zz_when) begin - decode_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - execute_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l350) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_MulPlugin_l65) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_CsrPlugin_l1193) begin - if(execute_CsrPlugin_blockedBySideEffects) begin - execute_arbitration_haltItself = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_haltByOther = 1'b0; - if(when_DBusCachedPlugin_l366) begin - execute_arbitration_haltByOther = 1'b1; - end - if(when_DebugPlugin_l295) begin - execute_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_removeIt = 1'b1; - end - if(execute_arbitration_isFlushed) begin - execute_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - execute_arbitration_flushIt = 1'b0; - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushIt = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_flushNext = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushNext = 1'b1; - end - end - end - - always @(*) begin - memory_arbitration_haltItself = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l129) begin - memory_arbitration_haltItself = 1'b1; - end - end - end - - assign memory_arbitration_haltByOther = 1'b0; - always @(*) begin - memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed) begin - memory_arbitration_removeIt = 1'b1; - end - end - - assign memory_arbitration_flushIt = 1'b0; - always @(*) begin - memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid) begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l466) begin - writeBack_arbitration_haltItself = 1'b1; - end - end - - assign writeBack_arbitration_haltByOther = 1'b0; - always @(*) begin - writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_removeIt = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - writeBack_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1032) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1077) begin - writeBack_arbitration_flushNext = 1'b1; - end - end - - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @(*) begin - IBusCachedPlugin_fetcherHalt = 1'b0; - if(when_CsrPlugin_l935) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1032) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1077) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - if(DebugPlugin_haltIt) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l311) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - - assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; - always @(*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if(when_Fetcher_l243) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - end - - always @(*) begin - _zz_when_DBusCachedPlugin_l393 = 1'b0; - if(DebugPlugin_godmode) begin - _zz_when_DBusCachedPlugin_l393 = 1'b1; - end - end - - assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; - assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; - assign CsrPlugin_inWfi = 1'b0; - always @(*) begin - CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt) begin - CsrPlugin_thirdPartyWake = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_valid = 1'b0; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - if(when_CsrPlugin_l1077) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; - end - default : begin - end - endcase - end - end - - always @(*) begin - CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode) begin - CsrPlugin_forceMachineWire = 1'b1; - end - end - - always @(*) begin - CsrPlugin_allowInterrupts = 1'b1; - if(when_DebugPlugin_l331) begin - CsrPlugin_allowInterrupts = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode) begin - CsrPlugin_allowException = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowEbreakException = 1'b1; - if(DebugPlugin_allowEBreak) begin - CsrPlugin_allowEbreakException = 1'b0; - end - end - - always @(*) begin - BranchPlugin_inDebugNoFetchFlag = 1'b0; - if(DebugPlugin_godmode) begin - BranchPlugin_inDebugNoFetchFlag = 1'b1; - end - end - - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - always @(*) begin - IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - end - - assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @(*) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; - end - end - - assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); - assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); - always @(*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; - end - IBusCachedPlugin_fetchPc_pc[0] = 1'b0; - IBusCachedPlugin_fetchPc_pc[1] = 1'b0; - end - - always @(*) begin - IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - end - - assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); - assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); - assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @(*) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; - end - end - - assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; - assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if(when_IBusCachedPlugin_l267) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; - assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - if(when_Fetcher_l323) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - end - - assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); - assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); - assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); - assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); - assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); - assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); - assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); - assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); - assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; - assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; - assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; - assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - always @(*) begin - decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_isValid = 1'b1; - end - 3'b011 : begin - decode_arbitration_isValid = 1'b1; - end - default : begin - end - endcase - if(IBusCachedPlugin_forceNoDecodeCond) begin - decode_arbitration_isValid = 1'b0; - end - end - - assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @(*) begin - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - end - - assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; - assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; - assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); - assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; - assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @(*) begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; - assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); - assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; - assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; - assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); - always @(*) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; - assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); - assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; - always @(*) begin - case(execute_DBusCachedPlugin_size) - 2'b00 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; - end - 2'b01 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; - end - default : begin - _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; - end - endcase - end - - assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); - assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; - assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); - assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); - assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); - assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; - assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; - assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @(*) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if(when_DBusCachedPlugin_l393) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; - end - end - - assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); - always @(*) begin - dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - if(writeBack_arbitration_haltByOther) begin - dataCache_1_io_cpu_writeBack_isValid = 1'b0; - end - end - - assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); - assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; - assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; - always @(*) begin - DBusCachedPlugin_redoBranch_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_redoBranch_valid = 1'b1; - end - end - end - - assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @(*) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - end - end - end - - assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @(*) begin - DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; - end - end - end - - assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); - assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; - assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; - assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; - assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; - always @(*) begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; - writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; - writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; - writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; - end - - assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; - assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; - end - - assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; - end - - always @(*) begin - case(switch_Misc_l210) - 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; - end - 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; - end - default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; - end - endcase - end - - assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); - assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); - assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; - assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; - assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; - assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; - assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; - assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; - assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; - assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; - assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; - assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; - assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; - assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; - assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; - assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; - assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; - assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = 4'b0010; - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; - assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); - assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; - assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; - assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; - always @(*) begin - lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - if(_zz_2) begin - lastStageRegFileWrite_valid = 1'b1; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - if(_zz_2) begin - lastStageRegFileWrite_payload_address = 5'h0; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; - if(_zz_2) begin - lastStageRegFileWrite_payload_data = 32'h0; - end - end - - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_AND_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); - end - AluBitwiseCtrlEnum_OR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); - end - default : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); - end - endcase - end - - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_BITWISE : begin - _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; - end - AluCtrlEnum_SLT_SLTU : begin - _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; - end - default : begin - _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; - end - endcase - end - - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : begin - _zz_decode_SRC1_1 = _zz_decode_SRC1; - end - Src1CtrlEnum_PC_INCREMENT : begin - _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; - end - Src1CtrlEnum_IMU : begin - _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; - end - default : begin - _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; - end - endcase - end - - assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; - always @(*) begin - _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; - end - - assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; - always @(*) begin - _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; - end - - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2_1; - end - Src2CtrlEnum_IMI : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; - end - Src2CtrlEnum_IMS : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; - end - default : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2; - end - endcase - end - - always @(*) begin - execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; - if(execute_SRC2_FORCE_ZERO) begin - execute_SrcPlugin_addSub = execute_SRC1; - end - end - - assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @(*) begin - _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; - _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; - _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; - _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; - _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; - _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; - _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; - _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; - _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; - _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; - _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; - _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; - _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; - _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; - _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; - _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; - _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; - _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; - _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; - _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; - _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; - _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; - _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; - _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; - _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; - _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; - _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; - _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; - _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; - _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; - _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; - _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); - always @(*) begin - _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; - _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; - _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; - _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; - _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; - _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; - _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; - _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; - _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; - _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; - _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; - _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; - _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; - _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; - _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; - _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; - _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; - _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; - _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; - _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; - _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; - _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; - _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; - _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; - _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; - _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; - _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; - _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; - _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; - _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; - _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; - _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; - end - - always @(*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l48) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l48_1) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l48_2) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l105) begin - HazardSimplePlugin_src0Hazard = 1'b0; - end - end - - always @(*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l51) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l51_1) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l51_2) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l108) begin - HazardSimplePlugin_src1Hazard = 1'b0; - end - end - - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l47 = 1'b1; - assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); - assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); - assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); - assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); - assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); - assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); - assign execute_MulPlugin_a = execute_RS1; - assign execute_MulPlugin_b = execute_RS2; - assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_aSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_aSigned = 1'b1; - end - default : begin - execute_MulPlugin_aSigned = 1'b0; - end - endcase - end - - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_bSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_bSigned = 1'b0; - end - default : begin - execute_MulPlugin_bSigned = 1'b0; - end - endcase - end - - assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; - assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; - assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; - assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; - assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; - assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); - assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); - assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; - end - end - end - - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; - end - end - - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); - assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); - always @(*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); - end - if(memory_MulDivIterativePlugin_div_counter_willClear) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end - end - - assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); - assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); - assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); - assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; - assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); - assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @(*) begin - _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; - end - - always @(*) begin - CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire) begin - CsrPlugin_privilege = 2'b11; - end - end - - assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; - end - if(decode_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; - end - if(execute_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; - end - end - - assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); - assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); - assign CsrPlugin_lastStageWasWfi = 1'b0; - assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); - always @(*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(when_CsrPlugin_l1004) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - if(CsrPlugin_hadException) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - end - - assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); - assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @(*) begin - CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException) begin - CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - end - end - - always @(*) begin - CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException) begin - CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; - end - end - - always @(*) begin - CsrPlugin_xtvec_mode = 2'bxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; - end - default : begin - end - endcase - end - - always @(*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; - end - default : begin - end - endcase - end - - assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); - assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; - assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); - assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); - always @(*) begin - execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3860) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_769) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_768) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_836) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_772) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_773) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_833) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_832) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_834) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_835) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(CsrPlugin_csrMapping_allowCsrSignal) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_illegalAccess = 1'b1; - end - if(when_CsrPlugin_l1315) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_illegalInstruction = 1'b0; - if(when_CsrPlugin_l1149) begin - if(when_CsrPlugin_l1150) begin - execute_CsrPlugin_illegalInstruction = 1'b1; - end - end - end - - always @(*) begin - CsrPlugin_selfException_valid = 1'b0; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1157) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_selfException_payload_code = 4'bxxxx; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_payload_code = 4'b0010; - end - if(when_CsrPlugin_l1157) begin - case(CsrPlugin_privilege) - 2'b00 : begin - CsrPlugin_selfException_payload_code = 4'b1000; - end - default : begin - CsrPlugin_selfException_payload_code = 4'b1011; - end - endcase - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_payload_code = 4'b0011; - end - end - - assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); - assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); - assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); - assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); - always @(*) begin - execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_writeInstruction = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_readInstruction = 1'b0; - end - end - - assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); - assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; - assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; - always @(*) begin - case(switch_Misc_l210_1) - 1'b0 : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; - end - default : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); - end - endcase - end - - assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; - assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); - assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); - assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; - always @(*) begin - casez(switch_Misc_l210_2) - 3'b000 : begin - _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; - end - 3'b001 : begin - _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); - end - 3'b1?1 : begin - _zz_execute_BRANCH_DO = (! execute_SRC_LESS); - end - default : begin - _zz_execute_BRANCH_DO = execute_SRC_LESS; - end - endcase - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : begin - _zz_execute_BRANCH_DO_1 = 1'b0; - end - BranchCtrlEnum_JAL : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - default : begin - _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; - end - endcase - end - - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); - assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; - end - - assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; - end - - assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_JAL : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; - end - default : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - end - endcase - end - - assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); - assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); - always @(*) begin - debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; - end - end - default : begin - end - endcase - end - end - - always @(*) begin - debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if(when_DebugPlugin_l244) begin - debug_bus_rsp_data[0] = DebugPlugin_resetIt; - debug_bus_rsp_data[1] = DebugPlugin_haltIt; - debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; - debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; - debug_bus_rsp_data[4] = DebugPlugin_stepIt; - end - end - - assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); - always @(*) begin - IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - IBusCachedPlugin_injectionPort_valid = 1'b1; - end - end - default : begin - end - endcase - end - end - - assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; - assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; - assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; - assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; - assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; - assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; - assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); - assign when_Pipeline_l124 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); - assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); - assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; - assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; - assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; - assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; - assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; - assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; - assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; - assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; - assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; - assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; - assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); - assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; - assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); - assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; - assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; - assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; - assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; - assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; - assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); - assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; - assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); - assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; - assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); - assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; - assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; - assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); - assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; - assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); - assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); - assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); - assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - always @(*) begin - IBusCachedPlugin_injectionPort_ready = 1'b0; - case(switch_Fetcher_l365) - 3'b100 : begin - IBusCachedPlugin_injectionPort_ready = 1'b1; - end - default : begin - end - endcase - end - - assign when_Fetcher_l381 = (! decode_arbitration_isStuck); - assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); - assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); - assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; - if(execute_CsrPlugin_csr_768) begin - _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; - if(execute_CsrPlugin_csr_836) begin - _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; - if(execute_CsrPlugin_csr_772) begin - _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; - if(execute_CsrPlugin_csr_773) begin - _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; - _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; - if(execute_CsrPlugin_csr_833) begin - _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; - if(execute_CsrPlugin_csr_832) begin - _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; - if(execute_CsrPlugin_csr_834) begin - _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; - if(execute_CsrPlugin_csr_835) begin - _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; - end - end - - assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); - assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - IBusCachedPlugin_fetchPc_booted <= 1'b0; - IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - IBusCachedPlugin_rspCounter <= 32'h0; - dataCache_1_io_mem_cmd_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dBus_rsp_regNext_valid <= 1'b0; - DBusCachedPlugin_rspCounter <= 32'h0; - _zz_2 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; - memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - CsrPlugin_misa_base <= 2'b01; - CsrPlugin_misa_extensions <= 26'h0041101; - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= 2'b11; - CsrPlugin_mie_MEIE <= 1'b0; - CsrPlugin_mie_MTIE <= 1'b0; - CsrPlugin_mie_MSIE <= 1'b0; - CsrPlugin_mcycle <= 64'h0; - CsrPlugin_minstret <= 64'h0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - CsrPlugin_interrupt_valid <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - CsrPlugin_hadException <= 1'b0; - execute_CsrPlugin_wfiWake <= 1'b0; - execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - switch_Fetcher_l365 <= 3'b000; - end else begin - if(IBusCachedPlugin_fetchPc_correction) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_output_fire) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - end - IBusCachedPlugin_fetchPc_booted <= 1'b1; - if(when_Fetcher_l134) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_output_fire_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b1; - end - if(when_Fetcher_l134_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(when_Fetcher_l161) begin - IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - end - if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); - end - if(decode_arbitration_removeIt) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - end - if(when_Fetcher_l332) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(when_Fetcher_l332_1) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(when_Fetcher_l332_2) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(when_Fetcher_l332_3) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(when_Fetcher_l332_4) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(when_Fetcher_l332_5) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(iBus_rsp_valid) begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); - end - if(dataCache_1_io_mem_cmd_valid) begin - dataCache_1_io_mem_cmd_rValid <= 1'b1; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_rValid <= 1'b0; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; - end - dBus_rsp_regNext_valid <= dBus_rsp_valid; - if(dBus_rsp_valid) begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); - end - _zz_2 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; - memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring) begin - CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); - end - if(when_CsrPlugin_l922) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - end - if(when_CsrPlugin_l922_1) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if(when_CsrPlugin_l922_2) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if(when_CsrPlugin_l922_3) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - end - CsrPlugin_interrupt_valid <= 1'b0; - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - end - if(CsrPlugin_pipelineLiberator_active) begin - if(when_CsrPlugin_l993) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; - end - if(when_CsrPlugin_l993_1) begin - CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; - end - if(when_CsrPlugin_l993_2) begin - CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; - end - end - if(when_CsrPlugin_l998) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - end - if(CsrPlugin_interruptJump) begin - CsrPlugin_interrupt_valid <= 1'b0; - end - CsrPlugin_hadException <= CsrPlugin_exception; - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; - CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; - end - default : begin - end - endcase - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b00; - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; - end - default : begin - end - endcase - end - execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(when_Pipeline_l151) begin - execute_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154) begin - execute_arbitration_isValid <= decode_arbitration_isValid; - end - if(when_Pipeline_l151_1) begin - memory_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_1) begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(when_Pipeline_l151_2) begin - writeBack_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_2) begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(switch_Fetcher_l365) - 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid) begin - switch_Fetcher_l365 <= 3'b001; - end - end - 3'b001 : begin - switch_Fetcher_l365 <= 3'b010; - end - 3'b010 : begin - switch_Fetcher_l365 <= 3'b011; - end - 3'b011 : begin - if(when_Fetcher_l381) begin - switch_Fetcher_l365 <= 3'b100; - end - end - 3'b100 : begin - switch_Fetcher_l365 <= 3'b000; - end - default : begin - end - endcase - if(execute_CsrPlugin_csr_769) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; - CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; - end - end - if(execute_CsrPlugin_csr_768) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - case(switch_CsrPlugin_l723) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b11; - end - default : begin - end - endcase - end - end - if(execute_CsrPlugin_csr_772) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; - CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - end - end - - always @(posedge io_systemClk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; - end - if(IBusCachedPlugin_injector_decodeInput_ready) begin - IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; - end - if(dataCache_1_io_mem_cmd_ready) begin - dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; - dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; - dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; - dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; - execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); - if(when_MulPlugin_l70) begin - execute_MulPlugin_delayLogic_counter <= 1'b0; - end - execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - if(when_MulDivIterativePlugin_l126) begin - memory_MulDivIterativePlugin_div_done <= 1'b1; - end - if(when_MulDivIterativePlugin_l126_1) begin - memory_MulDivIterativePlugin_div_done <= 1'b0; - end - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if(when_MulDivIterativePlugin_l151) begin - memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; - end - end - end - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); - memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; - end - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_code <= 4'b0111; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_code <= 4'b0011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_code <= 4'b1011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - end - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException) begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase - end - if(when_Pipeline_l124) begin - decode_to_execute_PC <= _zz_decode_SRC2; - end - if(when_Pipeline_l124_1) begin - execute_to_memory_PC <= execute_PC; - end - if(when_Pipeline_l124_2) begin - memory_to_writeBack_PC <= memory_PC; - end - if(when_Pipeline_l124_3) begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; - end - if(when_Pipeline_l124_4) begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; - end - if(when_Pipeline_l124_5) begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if(when_Pipeline_l124_6) begin - decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_7) begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_8) begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_9) begin - decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; - end - if(when_Pipeline_l124_10) begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; - end - if(when_Pipeline_l124_11) begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; - end - if(when_Pipeline_l124_12) begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; - end - if(when_Pipeline_l124_13) begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if(when_Pipeline_l124_14) begin - decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; - end - if(when_Pipeline_l124_15) begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_16) begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_17) begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_18) begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; - end - if(when_Pipeline_l124_19) begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_20) begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_21) begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; - end - if(when_Pipeline_l124_22) begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; - end - if(when_Pipeline_l124_23) begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; - end - if(when_Pipeline_l124_24) begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; - end - if(when_Pipeline_l124_25) begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; - end - if(when_Pipeline_l124_26) begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; - end - if(when_Pipeline_l124_27) begin - decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; - end - if(when_Pipeline_l124_28) begin - execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; - end - if(when_Pipeline_l124_29) begin - decode_to_execute_IS_MUL <= decode_IS_MUL; - end - if(when_Pipeline_l124_30) begin - execute_to_memory_IS_MUL <= execute_IS_MUL; - end - if(when_Pipeline_l124_31) begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; - end - if(when_Pipeline_l124_32) begin - decode_to_execute_IS_DIV <= decode_IS_DIV; - end - if(when_Pipeline_l124_33) begin - execute_to_memory_IS_DIV <= execute_IS_DIV; - end - if(when_Pipeline_l124_34) begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; - end - if(when_Pipeline_l124_35) begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; - end - if(when_Pipeline_l124_36) begin - decode_to_execute_IS_CSR <= decode_IS_CSR; - end - if(when_Pipeline_l124_37) begin - decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; - end - if(when_Pipeline_l124_38) begin - execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; - end - if(when_Pipeline_l124_39) begin - memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; - end - if(when_Pipeline_l124_40) begin - decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; - end - if(when_Pipeline_l124_41) begin - decode_to_execute_RS1 <= _zz_decode_SRC1; - end - if(when_Pipeline_l124_42) begin - decode_to_execute_RS2 <= _zz_decode_SRC2_1; - end - if(when_Pipeline_l124_43) begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; - end - if(when_Pipeline_l124_44) begin - decode_to_execute_SRC1 <= decode_SRC1; - end - if(when_Pipeline_l124_45) begin - decode_to_execute_SRC2 <= decode_SRC2; - end - if(when_Pipeline_l124_46) begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; - end - if(when_Pipeline_l124_47) begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; - end - if(when_Pipeline_l124_48) begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; - end - if(when_Pipeline_l124_49) begin - execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_50) begin - memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_51) begin - execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; - end - if(when_Pipeline_l124_52) begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; - end - if(when_Pipeline_l124_53) begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; - end - if(when_Pipeline_l124_54) begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; - end - if(when_Pipeline_l124_55) begin - execute_to_memory_MUL_LL <= execute_MUL_LL; - end - if(when_Pipeline_l124_56) begin - execute_to_memory_MUL_LH <= execute_MUL_LH; - end - if(when_Pipeline_l124_57) begin - execute_to_memory_MUL_HL <= execute_MUL_HL; - end - if(when_Pipeline_l124_58) begin - execute_to_memory_MUL_HH <= execute_MUL_HH; - end - if(when_Pipeline_l124_59) begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; - end - if(when_Pipeline_l124_60) begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if(when_Pipeline_l124_61) begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end - if(when_Pipeline_l124_62) begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; - end - if(when_Fetcher_l401) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; - end - if(when_CsrPlugin_l1277) begin - execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); - end - if(when_CsrPlugin_l1277_1) begin - execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); - end - if(when_CsrPlugin_l1277_2) begin - execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); - end - if(when_CsrPlugin_l1277_3) begin - execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); - end - if(when_CsrPlugin_l1277_4) begin - execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); - end - if(when_CsrPlugin_l1277_5) begin - execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); - end - if(when_CsrPlugin_l1277_6) begin - execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); - end - if(when_CsrPlugin_l1277_7) begin - execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); - end - if(when_CsrPlugin_l1277_8) begin - execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); - end - if(when_CsrPlugin_l1277_9) begin - execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); - end - if(execute_CsrPlugin_csr_836) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - if(execute_CsrPlugin_csr_773) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; - CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; - end - end - if(execute_CsrPlugin_csr_833) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_832) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - end - - always @(posedge io_systemClk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready) begin - DebugPlugin_firstCycle <= 1'b1; - end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid) begin - DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; - end - _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; - if(when_DebugPlugin_l295) begin - DebugPlugin_busReadDataReg <= execute_PC; - end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - DebugPlugin_debugUsed <= 1'b0; - DebugPlugin_disableEbreak <= 1'b0; - end else begin - if(when_DebugPlugin_l225) begin - DebugPlugin_godmode <= 1'b1; - end - if(debug_bus_cmd_valid) begin - DebugPlugin_debugUsed <= 1'b1; - end - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h0 : begin - if(debug_bus_cmd_payload_wr) begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(when_DebugPlugin_l271) begin - DebugPlugin_resetIt <= 1'b1; - end - if(when_DebugPlugin_l271_1) begin - DebugPlugin_resetIt <= 1'b0; - end - if(when_DebugPlugin_l272) begin - DebugPlugin_haltIt <= 1'b1; - end - if(when_DebugPlugin_l272_1) begin - DebugPlugin_haltIt <= 1'b0; - end - if(when_DebugPlugin_l273) begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(when_DebugPlugin_l274) begin - DebugPlugin_godmode <= 1'b0; - end - if(when_DebugPlugin_l275) begin - DebugPlugin_disableEbreak <= 1'b1; - end - if(when_DebugPlugin_l275_1) begin - DebugPlugin_disableEbreak <= 1'b0; - end - end - end - default : begin - end - endcase - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end - end - if(when_DebugPlugin_l311) begin - if(decode_arbitration_isValid) begin - DebugPlugin_haltIt <= 1'b1; - end - end - end - end - - -endmodule - -module BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin - if(debugCd_logic_outputReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input io_asyncReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge io_asyncReset) begin - if(io_asyncReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload_data; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [7:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload_data = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload_data) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload_data; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_push_valid, - output io_push_ready, - input io_push_payload_kind, - input io_push_payload_read, - input io_push_payload_write, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output io_pop_payload_kind, - output io_pop_payload_read, - output io_pop_payload_write, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [10:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz__zz_io_pop_payload_kind; - wire [10:0] _zz_logic_ram_port_1; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [10:0] _zz_io_pop_payload_kind; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [10:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_kind = 1'b1; - assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; - always @(posedge io_systemClk) begin - if(_zz__zz_io_pop_payload_kind) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; - assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; - assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; - assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; - assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_config_kind_cpol, - input io_config_kind_cpha, - input [11:0] io_config_sclkToogle, - input [1:0] io_config_mod, - input [0:0] io_config_ss_activeHigh, - input [11:0] io_config_ss_setup, - input [11:0] io_config_ss_hold, - input [11:0] io_config_ss_disable, - input io_cmd_valid, - output reg io_cmd_ready, - input io_cmd_payload_kind, - input io_cmd_payload_read, - input io_cmd_payload_write, - input [7:0] io_cmd_payload_data, - output io_rsp_valid, - output [7:0] io_rsp_payload_data, - output [0:0] io_spi_sclk_write, - output reg io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output reg [0:0] io_spi_data_0_write, - output reg io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output reg [0:0] io_spi_data_1_write, - output reg io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output reg [0:0] io_spi_data_2_write, - output reg io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output reg [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [0:0] _zz_outputPhy_dataWrite_3; - wire [2:0] _zz_outputPhy_dataWrite_4; - wire [2:0] _zz_outputPhy_dataWrite_5; - reg [1:0] _zz_outputPhy_dataWrite_6; - wire [1:0] _zz_outputPhy_dataWrite_7; - wire [2:0] _zz_outputPhy_dataWrite_8; - reg [3:0] _zz_outputPhy_dataWrite_9; - wire [0:0] _zz_outputPhy_dataWrite_10; - wire [2:0] _zz_outputPhy_dataWrite_11; - wire [3:0] _zz_inputPhy_dataRead; - wire [3:0] _zz_inputPhy_dataRead_1; - wire [3:0] _zz_inputPhy_dataRead_2; - wire [3:0] _zz_inputPhy_dataRead_3; - wire [3:0] _zz_inputPhy_dataRead_4; - wire [3:0] _zz_inputPhy_dataRead_5; - wire [3:0] _zz_inputPhy_dataRead_6; - wire [8:0] _zz_inputPhy_bufferNext; - wire [10:0] _zz_inputPhy_bufferNext_1; - reg [11:0] timer_counter; - reg timer_reset; - wire timer_ss_setupHit; - wire timer_ss_holdHit; - wire timer_ss_disableHit; - wire timer_sclkToogleHit; - reg fsm_state; - reg [2:0] fsm_counter; - reg [2:0] _zz_fsm_counterPlus; - wire [2:0] fsm_counterPlus; - reg fsm_fastRate; - reg fsm_isDdr; - reg [2:0] fsm_counterMax; - reg fsm_lateSampling; - reg fsm_readFill; - reg fsm_readDone; - reg [0:0] fsm_ss; - wire when_SpiXdrMasterCtrl_l739; - wire when_SpiXdrMasterCtrl_l742; - wire when_SpiXdrMasterCtrl_l749; - wire when_SpiXdrMasterCtrl_l751; - wire when_SpiXdrMasterCtrl_l758; - wire when_SpiXdrMasterCtrl_l764; - wire when_SpiXdrMasterCtrl_l781; - reg [0:0] outputPhy_sclkWrite; - wire [0:0] _zz_io_spi_sclk_write; - wire when_SpiXdrMasterCtrl_l796; - reg [3:0] outputPhy_dataWrite; - reg [2:0] outputPhy_widthSel; - reg [2:0] outputPhy_offset; - wire [7:0] _zz_outputPhy_dataWrite; - wire [7:0] _zz_outputPhy_dataWrite_1; - wire [7:0] _zz_outputPhy_dataWrite_2; - wire when_SpiXdrMasterCtrl_l839; - wire when_SpiXdrMasterCtrl_l839_1; - reg [1:0] io_config_mod_delay_1; - reg [1:0] inputPhy_mod; - reg fsm_readFill_delay_1; - reg inputPhy_readFill; - reg fsm_readDone_delay_1; - reg inputPhy_readDone; - reg [6:0] inputPhy_buffer; - reg [7:0] inputPhy_bufferNext; - reg [2:0] inputPhy_widthSel; - wire [3:0] inputPhy_dataWrite; - reg [3:0] inputPhy_dataRead; - reg fsm_state_delay_1; - reg fsm_state_delay_2; - wire when_SpiXdrMasterCtrl_l861; - reg [3:0] inputPhy_dataReadBuffer; - - assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); - assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); - assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); - assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); - assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; - assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; - always @(*) begin - case(_zz_outputPhy_dataWrite_4) - 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; - 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; - 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; - 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; - 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; - 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; - 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; - default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_7) - 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; - 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; - 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; - default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_10) - 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; - default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; - endcase - end - - always @(*) begin - timer_reset = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - timer_reset = timer_sclkToogleHit; - end else begin - if(!when_SpiXdrMasterCtrl_l758) begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - timer_reset = 1'b1; - end - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - timer_reset = 1'b1; - end - end - - assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); - assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); - assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); - assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); - always @(*) begin - _zz_fsm_counterPlus = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - _zz_fsm_counterPlus = 3'b001; - end - 2'b01 : begin - _zz_fsm_counterPlus = 3'b010; - end - 2'b10 : begin - _zz_fsm_counterPlus = 3'b100; - end - default : begin - end - endcase - end - - assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); - always @(*) begin - fsm_fastRate = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_fastRate = 1'b0; - end - 2'b01 : begin - fsm_fastRate = 1'b0; - end - 2'b10 : begin - fsm_fastRate = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_isDdr = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_isDdr = 1'b0; - end - 2'b01 : begin - fsm_isDdr = 1'b0; - end - 2'b10 : begin - fsm_isDdr = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_counterMax = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - fsm_counterMax = 3'b111; - end - 2'b01 : begin - fsm_counterMax = 3'b110; - end - 2'b10 : begin - fsm_counterMax = 3'b100; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_lateSampling = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_lateSampling = 1'b1; - end - 2'b01 : begin - fsm_lateSampling = 1'b1; - end - 2'b10 : begin - fsm_lateSampling = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_readFill = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readFill = 1'b1; - end - end - end - end - - always @(*) begin - fsm_readDone = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); - end - end - end - end - - assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); - always @(*) begin - io_cmd_ready = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l749) begin - if(when_SpiXdrMasterCtrl_l751) begin - io_cmd_ready = 1'b1; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - if(timer_ss_setupHit) begin - io_cmd_ready = 1'b1; - end - end else begin - if(!when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_disableHit) begin - io_cmd_ready = 1'b1; - end - end - end - end - end - end - - assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); - assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); - assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; - assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); - assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); - always @(*) begin - outputPhy_sclkWrite = 1'b0; - if(when_SpiXdrMasterCtrl_l796) begin - case(io_config_mod) - 2'b00 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b01 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b10 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - default : begin - end - endcase - end - end - - assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; - assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); - assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); - always @(*) begin - outputPhy_widthSel = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_widthSel = 3'b000; - end - 2'b01 : begin - outputPhy_widthSel = 3'b001; - end - 2'b10 : begin - outputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_offset = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_offset = 3'b111; - end - 2'b01 : begin - outputPhy_offset = 3'b111; - end - 2'b10 : begin - outputPhy_offset = 3'b111; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_dataWrite = 4'bxxxx; - case(outputPhy_widthSel) - 3'b000 : begin - outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; - end - 3'b001 : begin - outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; - end - 3'b010 : begin - outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; - end - default : begin - end - endcase - end - - assign _zz_outputPhy_dataWrite = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; - always @(*) begin - io_spi_data_0_writeEnable = 1'b0; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_writeEnable = 1'b1; - end - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_writeEnable = 1'b0; - case(io_config_mod) - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_2_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_3_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_0_write = 1'bx; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); - end - 2'b01 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - 2'b10 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_write = 1'bx; - case(io_config_mod) - 2'b01 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - 2'b10 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_2_write[0] = outputPhy_dataWrite[2]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_3_write[0] = outputPhy_dataWrite[3]; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); - assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); - always @(*) begin - inputPhy_bufferNext = 8'bxxxxxxxx; - case(inputPhy_widthSel) - 3'b000 : begin - inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; - end - 3'b001 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; - end - 3'b010 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; - end - default : begin - end - endcase - end - - always @(*) begin - inputPhy_widthSel = 3'bxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_widthSel = 3'b000; - end - 2'b01 : begin - inputPhy_widthSel = 3'b001; - end - 2'b10 : begin - inputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); - always @(*) begin - inputPhy_dataRead = 4'bxxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; - end - 2'b01 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; - end - 2'b10 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; - inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; - inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; - end - default : begin - end - endcase - end - - assign io_rsp_valid = inputPhy_readDone; - assign io_rsp_payload_data = inputPhy_bufferNext; - always @(posedge io_systemClk) begin - timer_counter <= (timer_counter + 12'h001); - if(timer_reset) begin - timer_counter <= 12'h0; - end - io_config_mod_delay_1 <= io_config_mod; - inputPhy_mod <= io_config_mod_delay_1; - fsm_state_delay_1 <= fsm_state; - fsm_state_delay_2 <= fsm_state_delay_1; - if(when_SpiXdrMasterCtrl_l861) begin - inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - end - case(inputPhy_widthSel) - 3'b000 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b001 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b010 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - default : begin - end - endcase - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - fsm_ss <= 1'b0; - fsm_readFill_delay_1 <= 1'b0; - inputPhy_readFill <= 1'b0; - fsm_readDone_delay_1 <= 1'b0; - inputPhy_readDone <= 1'b0; - end else begin - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(timer_sclkToogleHit) begin - fsm_state <= (! fsm_state); - end - if(when_SpiXdrMasterCtrl_l749) begin - fsm_counter <= fsm_counterPlus; - if(when_SpiXdrMasterCtrl_l751) begin - fsm_state <= 1'b0; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - fsm_ss[0] <= 1'b1; - end else begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - fsm_state <= 1'b1; - end - end else begin - fsm_ss[0] <= 1'b0; - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - end - fsm_readFill_delay_1 <= fsm_readFill; - inputPhy_readFill <= fsm_readFill_delay_1; - fsm_readDone_delay_1 <= fsm_readDone; - inputPhy_readDone <= fsm_readDone_delay_1; - end - end - - -endmodule - -//StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b replaced by StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b - -module StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload, - input io_flush, - output [7:0] io_occupancy, - output [7:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [6:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [6:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload; - wire [6:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [6:0] logic_pushPtr_valueNext; - reg [6:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [6:0] logic_popPtr_valueNext; - reg [6:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [6:0] logic_ptrDif; - reg [7:0] logic_ram [0:127]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 7'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 7'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload = _zz_logic_ram_port0; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 7'h0; - logic_popPtr_value <= 7'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( - input [2:0] io_config_frame_dataLength, - input [0:0] io_config_frame_stop, - input [1:0] io_config_frame_parity, - input [19:0] io_config_clockDivider, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - output io_uart_txd, - input io_uart_rxd, - output io_readError, - input io_writeBreak, - output io_readBreak, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - wire tx_io_write_ready; - wire tx_io_txd; - wire rx_io_read_valid; - wire [7:0] rx_io_read_payload; - wire rx_io_rts; - wire rx_io_error; - wire rx_io_break; - reg [19:0] clockDivider_counter; - wire clockDivider_tick; - reg clockDivider_tickReg; - reg io_write_thrown_valid; - wire io_write_thrown_ready; - wire [7:0] io_write_thrown_payload; - `ifndef SYNTHESIS - reg [23:0] io_config_frame_stop_string; - reg [31:0] io_config_frame_parity_string; - `endif - - - UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b tx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_write_valid (io_write_thrown_valid ), //i - .io_write_ready (tx_io_write_ready ), //o - .io_write_payload (io_write_thrown_payload[7:0] ), //i - .io_cts (1'b0 ), //i - .io_txd (tx_io_txd ), //o - .io_break (io_writeBreak ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b rx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_read_valid (rx_io_read_valid ), //o - .io_read_ready (io_read_ready ), //i - .io_read_payload (rx_io_read_payload[7:0] ), //o - .io_rxd (io_uart_rxd ), //i - .io_rts (rx_io_rts ), //o - .io_error (rx_io_error ), //o - .io_break (rx_io_break ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_config_frame_stop) - UartStopType_ONE : io_config_frame_stop_string = "ONE"; - UartStopType_TWO : io_config_frame_stop_string = "TWO"; - default : io_config_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_config_frame_parity) - UartParityType_NONE : io_config_frame_parity_string = "NONE"; - UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; - UartParityType_ODD : io_config_frame_parity_string = "ODD "; - default : io_config_frame_parity_string = "????"; - endcase - end - `endif - - assign clockDivider_tick = (clockDivider_counter == 20'h0); - always @(*) begin - io_write_thrown_valid = io_write_valid; - if(rx_io_break) begin - io_write_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_write_ready = io_write_thrown_ready; - if(rx_io_break) begin - io_write_ready = 1'b1; - end - end - - assign io_write_thrown_payload = io_write_payload; - assign io_write_thrown_ready = tx_io_write_ready; - assign io_read_valid = rx_io_read_valid; - assign io_read_payload = rx_io_read_payload; - assign io_uart_txd = tx_io_txd; - assign io_readError = rx_io_error; - assign io_readBreak = rx_io_break; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter <= 20'h0; - clockDivider_tickReg <= 1'b0; - end else begin - clockDivider_tickReg <= clockDivider_tick; - clockDivider_counter <= (clockDivider_counter - 20'h00001); - if(clockDivider_tick) begin - clockDivider_counter <= io_config_clockDivider; - end - end - end - - -endmodule - -module StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_inputs_0_valid, - output io_inputs_0_ready, - input io_inputs_0_payload_last, - input [0:0] io_inputs_0_payload_fragment_source, - input [0:0] io_inputs_0_payload_fragment_opcode, - input [31:0] io_inputs_0_payload_fragment_address, - input [5:0] io_inputs_0_payload_fragment_length, - input [31:0] io_inputs_0_payload_fragment_data, - input [3:0] io_inputs_0_payload_fragment_mask, - input [0:0] io_inputs_0_payload_fragment_context, - input io_inputs_1_valid, - output io_inputs_1_ready, - input io_inputs_1_payload_last, - input [0:0] io_inputs_1_payload_fragment_source, - input [0:0] io_inputs_1_payload_fragment_opcode, - input [31:0] io_inputs_1_payload_fragment_address, - input [5:0] io_inputs_1_payload_fragment_length, - input [31:0] io_inputs_1_payload_fragment_data, - input [3:0] io_inputs_1_payload_fragment_mask, - input [0:0] io_inputs_1_payload_fragment_context, - output io_output_valid, - input io_output_ready, - output io_output_payload_last, - output [0:0] io_output_payload_fragment_source, - output [0:0] io_output_payload_fragment_opcode, - output [31:0] io_output_payload_fragment_address, - output [5:0] io_output_payload_fragment_length, - output [31:0] io_output_payload_fragment_data, - output [3:0] io_output_payload_fragment_mask, - output [0:0] io_output_payload_fragment_context, - output [0:0] io_chosen, - output [1:0] io_chosenOH, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l621; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l621 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); - assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l621) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_input_valid, - input io_input_payload_last, - input [0:0] io_input_payload_fragment, - output io_output_valid, - output io_output_payload_last, - output [0:0] io_output_payload_fragment, - input jtagCtrl_tck, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg inputArea_data_last; - reg [0:0] inputArea_data_fragment; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire outputArea_flow_payload_last; - wire [0:0] outputArea_flow_payload_fragment; - reg outputArea_flow_m2sPipe_valid; - reg outputArea_flow_m2sPipe_payload_last; - reg [0:0] outputArea_flow_m2sPipe_payload_fragment; - - BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - initial begin - `ifndef SYNTHESIS - inputArea_target = $urandom; - outputArea_hit = $urandom; - `endif - end - - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_last = inputArea_data_last; - assign outputArea_flow_payload_fragment = inputArea_data_fragment; - assign io_output_valid = outputArea_flow_m2sPipe_valid; - assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; - assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; - always @(posedge jtagCtrl_tck) begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - inputArea_data_last <= io_input_payload_last; - inputArea_data_fragment <= io_input_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - outputArea_hit <= outputArea_target; - if(outputArea_flow_valid) begin - outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; - outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - outputArea_flow_m2sPipe_valid <= 1'b0; - end else begin - outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; - end - end - - -endmodule - -module DataCache_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - output reg io_cpu_execute_haltIt, - input io_cpu_execute_args_wr, - input [1:0] io_cpu_execute_args_size, - input io_cpu_execute_args_totalyConsistent, - output io_cpu_execute_refilling, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - input [31:0] io_cpu_memory_mmuRsp_physicalAddress, - input io_cpu_memory_mmuRsp_isIoAccess, - input io_cpu_memory_mmuRsp_isPaging, - input io_cpu_memory_mmuRsp_allowRead, - input io_cpu_memory_mmuRsp_allowWrite, - input io_cpu_memory_mmuRsp_allowExecute, - input io_cpu_memory_mmuRsp_exception, - input io_cpu_memory_mmuRsp_refilling, - input io_cpu_memory_mmuRsp_bypassTranslation, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isFiring, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - input [31:0] io_cpu_writeBack_storeData, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output io_cpu_writeBack_keepMemRspData, - input io_cpu_writeBack_fence_SW, - input io_cpu_writeBack_fence_SR, - input io_cpu_writeBack_fence_SO, - input io_cpu_writeBack_fence_SI, - input io_cpu_writeBack_fence_PW, - input io_cpu_writeBack_fence_PR, - input io_cpu_writeBack_fence_PO, - input io_cpu_writeBack_fence_PI, - input [3:0] io_cpu_writeBack_fence_FM, - output io_cpu_writeBack_exclusiveOk, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output io_cpu_flush_ready, - input io_cpu_flush_payload_singleLine, - input [5:0] io_cpu_flush_payload_lineId, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output io_mem_cmd_payload_uncached, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_size, - output io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input io_mem_rsp_payload_last, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [21:0] _zz_ways_0_tags_port0; - reg [31:0] _zz_ways_0_data_port0; - wire [21:0] _zz_ways_0_tags_port; - wire [9:0] _zz_stage0_dataColisions; - wire [9:0] _zz__zz_stageA_dataColisions; - wire [0:0] _zz_when; - wire [3:0] _zz_loader_counter_valueNext; - wire [0:0] _zz_loader_counter_valueNext_1; - wire [1:0] _zz_loader_waysAllocator; - reg _zz_1; - reg _zz_2; - wire haltCpu; - reg tagsReadCmd_valid; - reg [5:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [5:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [5:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; - wire _zz_ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRsp; - wire when_DataCache_l642; - wire when_DataCache_l645; - wire when_DataCache_l664; - wire rspSync; - wire rspLast; - reg memCmdSent; - wire io_mem_cmd_fire; - wire when_DataCache_l686; - reg [3:0] _zz_stage0_mask; - wire [3:0] stage0_mask; - wire [0:0] stage0_dataColisions; - wire [0:0] stage0_wayInvalidate; - wire stage0_isAmo; - wire when_DataCache_l771; - reg stageA_request_wr; - reg [1:0] stageA_request_size; - reg stageA_request_totalyConsistent; - wire when_DataCache_l771_1; - reg [3:0] stageA_mask; - wire stageA_isAmo; - wire stageA_isLrsc; - wire [0:0] stageA_wayHits; - wire when_DataCache_l771_2; - reg [0:0] stageA_wayInvalidate; - wire when_DataCache_l771_3; - reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_stageA_dataColisions; - wire [0:0] stageA_dataColisions; - wire when_DataCache_l822; - reg stageB_request_wr; - reg [1:0] stageB_request_size; - reg stageB_request_totalyConsistent; - reg stageB_mmuRspFreeze; - wire when_DataCache_l824; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_isPaging; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_mmuRsp_bypassTranslation; - wire when_DataCache_l821; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - wire when_DataCache_l821_1; - reg [31:0] stageB_dataReadRsp_0; - wire when_DataCache_l820; - reg [0:0] stageB_wayInvalidate; - wire stageB_consistancyHazard; - wire when_DataCache_l820_1; - reg [0:0] stageB_dataColisions; - wire when_DataCache_l820_2; - reg stageB_unaligned; - wire when_DataCache_l820_3; - reg [0:0] stageB_waysHitsBeforeInvalidate; - wire [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - wire when_DataCache_l820_4; - reg [3:0] stageB_mask; - reg stageB_loaderValid; - wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_waitDone; - wire stageB_flusher_hold; - reg [6:0] stageB_flusher_counter; - wire when_DataCache_l850; - wire when_DataCache_l856; - reg stageB_flusher_start; - wire stageB_isAmo; - wire stageB_isAmoCached; - wire stageB_isExternalLsrc; - wire stageB_isExternalAmo; - wire [31:0] stageB_requestDataBypass; - reg stageB_cpuWriteToCache; - wire when_DataCache_l926; - wire stageB_badPermissions; - wire stageB_loadStoreFault; - wire stageB_bypassCache; - wire when_DataCache_l995; - wire when_DataCache_l1004; - wire when_DataCache_l1009; - wire when_DataCache_l1020; - wire when_DataCache_l1032; - wire when_DataCache_l991; - wire when_DataCache_l1066; - wire when_DataCache_l1075; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [3:0] loader_counter_valueNext; - reg [3:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - wire loader_kill; - reg loader_killReg; - wire when_DataCache_l1090; - wire loader_done; - wire when_DataCache_l1118; - reg loader_valid_regNext; - wire when_DataCache_l1122; - wire when_DataCache_l1125; - reg [21:0] ways_0_tags [0:63]; - reg [7:0] ways_0_data_symbol0 [0:1023]; - reg [7:0] ways_0_data_symbol1 [0:1023]; - reg [7:0] ways_0_data_symbol2 [0:1023]; - reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_ways_0_datasymbol_read; - reg [7:0] _zz_ways_0_datasymbol_read_1; - reg [7:0] _zz_ways_0_datasymbol_read_2; - reg [7:0] _zz_ways_0_datasymbol_read_3; - - assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_when = 1'b1; - assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; - assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; - assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_ways_0_tagsReadRsp_valid) begin - _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(*) begin - _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; - end - always @(posedge io_systemClk) begin - if(_zz_ways_0_dataReadRspMem) begin - _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(when_DataCache_l645) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(when_DataCache_l642) begin - _zz_2 = 1'b1; - end - end - - assign haltCpu = 1'b0; - assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; - assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; - assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; - assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; - assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; - assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); - assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); - always @(*) begin - tagsReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - tagsReadCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsReadCmd_payload = 6'bxxxxxx; - if(when_DataCache_l664) begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; - end - end - - always @(*) begin - dataReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - dataReadCmd_valid = 1'b1; - end - end - - always @(*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; - if(when_DataCache_l664) begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end - end - - always @(*) begin - tagsWriteCmd_valid = 1'b0; - if(when_DataCache_l850) begin - tagsWriteCmd_valid = 1'b1; - end - if(when_DataCache_l1066) begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsWriteCmd_payload_way = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_way = 1'b1; - end - if(loader_done) begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - tagsWriteCmd_payload_address = 6'bxxxxxx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; - end - if(loader_done) begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; - end - end - - always @(*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done) begin - tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; - if(loader_done) begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end - end - - always @(*) begin - dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache) begin - if(when_DataCache_l926) begin - dataWriteCmd_valid = 1'b1; - end - end - if(when_DataCache_l1066) begin - dataWriteCmd_valid = 1'b0; - end - if(when_DataCache_l1090) begin - dataWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_way = stageB_waysHits; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; - end - end - - always @(*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end - end - - always @(*) begin - dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_mask = 4'b0000; - if(_zz_when[0]) begin - dataWriteCmd_payload_mask[3 : 0] = stageB_mask; - end - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_mask = 4'b1111; - end - end - - assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - always @(*) begin - io_cpu_execute_haltIt = 1'b0; - if(when_DataCache_l850) begin - io_cpu_execute_haltIt = 1'b1; - end - end - - assign rspSync = 1'b1; - assign rspLast = 1'b1; - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); - always @(*) begin - _zz_stage0_mask = 4'bxxxx; - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_stage0_mask = 4'b0001; - end - 2'b01 : begin - _zz_stage0_mask = 4'b0011; - end - 2'b10 : begin - _zz_stage0_mask = 4'b1111; - end - default : begin - end - endcase - end - - assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stage0_wayInvalidate = 1'b0; - assign stage0_isAmo = 1'b0; - assign when_DataCache_l771 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_isAmo = 1'b0; - assign stageA_isLrsc = 1'b0; - assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); - assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); - assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_mmuRspFreeze = 1'b0; - if(when_DataCache_l1125) begin - stageB_mmuRspFreeze = 1'b1; - end - end - - assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); - assign stageB_consistancyHazard = 1'b0; - assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); - assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (|stageB_waysHits); - assign stageB_dataMux = stageB_dataReadRsp_0; - assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - if(io_mem_cmd_ready) begin - stageB_loaderValid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - stageB_loaderValid = 1'b0; - end - end - - assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @(*) begin - io_cpu_writeBack_haltIt = 1'b1; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - if(when_DataCache_l995) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1009) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - - assign stageB_flusher_hold = 1'b0; - assign when_DataCache_l850 = (! stageB_flusher_counter[6]); - assign when_DataCache_l856 = (! stageB_flusher_hold); - assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); - assign stageB_isAmo = 1'b0; - assign stageB_isAmoCached = 1'b0; - assign stageB_isExternalLsrc = 1'b0; - assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = io_cpu_writeBack_storeData; - always @(*) begin - stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - stageB_cpuWriteToCache = 1'b1; - end - end - end - end - end - - assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); - assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); - assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @(*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1020) begin - io_cpu_redo = 1'b1; - end - end - end - end - end - if(when_DataCache_l1075) begin - io_cpu_redo = 1'b1; - end - if(when_DataCache_l1122) begin - io_cpu_redo = 1'b1; - end - end - - always @(*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache) begin - io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); - end - end - - assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @(*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - io_mem_cmd_valid = (! memCmdSent); - end else begin - if(when_DataCache_l1004) begin - if(stageB_request_wr) begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if(when_DataCache_l1032) begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_mem_cmd_valid = 1'b0; - end - end - - always @(*) begin - io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_address[5 : 0] = 6'h0; - end - end - end - end - end - - assign io_mem_cmd_payload_last = 1'b1; - always @(*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; - always @(*) begin - io_mem_cmd_payload_size = {1'd0, stageB_request_size}; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_size = 3'b110; - end - end - end - end - end - - assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); - assign io_cpu_writeBack_keepMemRspData = 1'b0; - assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); - assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); - assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); - assign when_DataCache_l1032 = (! memCmdSent); - assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - always @(*) begin - if(stageB_bypassCache) begin - io_cpu_writeBack_data = stageB_ioMemRspMuxed; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); - always @(*) begin - loader_counter_willIncrement = 1'b0; - if(when_DataCache_l1090) begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @(*) begin - loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); - if(loader_counter_willClear) begin - loader_counter_valueNext = 4'b0000; - end - end - - assign loader_kill = 1'b0; - assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign loader_done = loader_counter_willOverflow; - assign when_DataCache_l1118 = (! loader_valid); - assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); - assign io_cpu_execute_refilling = loader_valid; - assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); - always @(posedge io_systemClk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if(when_DataCache_l771) begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_size <= io_cpu_execute_args_size; - stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; - end - if(when_DataCache_l771_1) begin - stageA_mask <= stage0_mask; - end - if(when_DataCache_l771_2) begin - stageA_wayInvalidate <= stage0_wayInvalidate; - end - if(when_DataCache_l771_3) begin - stage0_dataColisions_regNextWhen <= stage0_dataColisions; - end - if(when_DataCache_l822) begin - stageB_request_wr <= stageA_request_wr; - stageB_request_size <= stageA_request_size; - stageB_request_totalyConsistent <= stageA_request_totalyConsistent; - end - if(when_DataCache_l824) begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; - stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; - stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; - end - if(when_DataCache_l821) begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if(when_DataCache_l821_1) begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if(when_DataCache_l820) begin - stageB_wayInvalidate <= stageA_wayInvalidate; - end - if(when_DataCache_l820_1) begin - stageB_dataColisions <= stageA_dataColisions; - end - if(when_DataCache_l820_2) begin - stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); - end - if(when_DataCache_l820_3) begin - stageB_waysHitsBeforeInvalidate <= stageA_wayHits; - end - if(when_DataCache_l820_4) begin - stageB_mask <= stageA_mask; - end - loader_valid_regNext <= loader_valid; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - memCmdSent <= 1'b0; - stageB_flusher_waitDone <= 1'b0; - stageB_flusher_counter <= 7'h0; - stageB_flusher_start <= 1'b1; - loader_valid <= 1'b0; - loader_counter_value <= 4'b0000; - loader_waysAllocator <= 1'b1; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end else begin - if(io_mem_cmd_fire) begin - memCmdSent <= 1'b1; - end - if(when_DataCache_l686) begin - memCmdSent <= 1'b0; - end - if(io_cpu_flush_ready) begin - stageB_flusher_waitDone <= 1'b0; - end - if(when_DataCache_l850) begin - if(when_DataCache_l856) begin - stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter[6] <= 1'b1; - end - end - end - stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start) begin - stageB_flusher_waitDone <= 1'b1; - stageB_flusher_counter <= 7'h0; - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; - end - end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 - `else - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 - end - `endif - `endif - if(stageB_loaderValid) begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(loader_kill) begin - loader_killReg <= 1'b1; - end - if(when_DataCache_l1090) begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_done) begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end - if(when_DataCache_l1118) begin - loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; - end - end - end - - -endmodule - -module InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, - input io_cpu_fetch_mmuRsp_isIoAccess, - input io_cpu_fetch_mmuRsp_isPaging, - input io_cpu_fetch_mmuRsp_allowRead, - input io_cpu_fetch_mmuRsp_allowWrite, - input io_cpu_fetch_mmuRsp_allowExecute, - input io_cpu_fetch_mmuRsp_exception, - input io_cpu_fetch_mmuRsp_refilling, - input io_cpu_fetch_mmuRsp_bypassTranslation, - output [31:0] io_cpu_fetch_physicalAddress, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_banks_0_port1; - reg [21:0] _zz_ways_0_tags_port1; - wire [21:0] _zz_ways_0_tags_port; - reg _zz_1; - reg _zz_2; - reg lineLoader_fire; - reg lineLoader_valid; - (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; - wire when_InstructionCache_l338; - reg _zz_when_InstructionCache_l342; - wire when_InstructionCache_l342; - wire when_InstructionCache_l351; - reg lineLoader_cmdSent; - wire io_mem_cmd_fire; - wire when_Utils_l513; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; - wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire when_InstructionCache_l401; - wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; - wire _zz_fetchStage_read_banksValue_0_dataMem_1; - wire [31:0] fetchStage_read_banksValue_0_dataMem; - wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; - wire _zz_fetchStage_read_waysValues_0_tag_valid_1; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - wire when_InstructionCache_l435; - reg [31:0] io_cpu_fetch_data_regNextWhen; - wire when_InstructionCache_l459; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_isPaging; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_mmuRsp_bypassTranslation; - wire when_InstructionCache_l459_1; - reg decodeStage_hit_valid; - wire when_InstructionCache_l459_2; - reg decodeStage_hit_error; - reg [31:0] banks_0 [0:1023]; - reg [21:0] ways_0_tags [0:63]; - - assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_1) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin - _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin - _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid) begin - _zz_2 = 1'b1; - end - end - - always @(*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid) begin - if(when_InstructionCache_l401) begin - lineLoader_fire = 1'b1; - end - end - end - - always @(*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(when_InstructionCache_l338) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(when_InstructionCache_l342) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush) begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); - assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); - assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; - assign io_mem_cmd_payload_size = 3'b110; - assign when_Utils_l513 = (! lineLoader_valid); - always @(*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if(when_Utils_l513) begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end - end - - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; - assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); - assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; - assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; - assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; - assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); - assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; - assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; - assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; - assign fetchStage_hit_word = fetchStage_hit_data; - assign io_cpu_fetch_data = fetchStage_hit_word; - assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; - assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= 4'b0000; - end else begin - if(lineLoader_fire) begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire) begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid) begin - lineLoader_valid <= 1'b1; - end - if(io_flush) begin - lineLoader_flushPending <= 1'b1; - end - if(when_InstructionCache_l351) begin - lineLoader_flushPending <= 1'b0; - end - if(io_mem_cmd_fire) begin - lineLoader_cmdSent <= 1'b1; - end - if(lineLoader_fire) begin - lineLoader_cmdSent <= 1'b0; - end - if(io_mem_rsp_valid) begin - lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); - if(io_mem_rsp_payload_error) begin - lineLoader_hadError <= 1'b1; - end - end - end - end - - always @(posedge io_systemClk) begin - if(io_cpu_fill_valid) begin - lineLoader_address <= io_cpu_fill_payload; - end - if(when_InstructionCache_l338) begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); - end - _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; - if(when_InstructionCache_l351) begin - lineLoader_flushCounter <= 7'h0; - end - if(when_InstructionCache_l435) begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if(when_InstructionCache_l459) begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; - decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; - decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; - end - if(when_InstructionCache_l459_1) begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if(when_InstructionCache_l459_2) begin - decodeStage_hit_error <= fetchStage_hit_error; - end - end - - -endmodule - -module UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - input io_rxd, - output io_rts, - output reg io_error, - output io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlRxState_IDLE = 3'd0; - localparam UartCtrlRxState_START = 3'd1; - localparam UartCtrlRxState_DATA = 3'd2; - localparam UartCtrlRxState_PARITY = 3'd3; - localparam UartCtrlRxState_STOP = 3'd4; - - wire io_rxd_buffercc_io_dataOut; - wire _zz_sampler_value; - wire _zz_sampler_value_1; - wire _zz_sampler_value_2; - wire _zz_sampler_value_3; - wire _zz_sampler_value_4; - wire _zz_sampler_value_5; - wire _zz_sampler_value_6; - wire [2:0] _zz_when_UartCtrlRx_l139; - wire [0:0] _zz_when_UartCtrlRx_l139_1; - reg _zz_io_rts; - wire sampler_synchroniser; - wire sampler_samples_0; - reg sampler_samples_1; - reg sampler_samples_2; - reg sampler_samples_3; - reg sampler_samples_4; - reg sampler_value; - reg sampler_tick; - reg [2:0] bitTimer_counter; - reg bitTimer_tick; - wire when_UartCtrlRx_l43; - reg [2:0] bitCounter_value; - reg [6:0] break_counter; - wire break_valid; - wire when_UartCtrlRx_l69; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg [7:0] stateMachine_shifter; - reg stateMachine_validReg; - wire when_UartCtrlRx_l93; - wire when_UartCtrlRx_l103; - wire when_UartCtrlRx_l111; - wire when_UartCtrlRx_l113; - wire when_UartCtrlRx_l125; - wire when_UartCtrlRx_l136; - wire when_UartCtrlRx_l139; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; - assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); - assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); - assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); - assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); - assign _zz_sampler_value_6 = 1'b1; - assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); - assign _zz_sampler_value_2 = 1'b1; - BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b io_rxd_buffercc ( - .io_dataIn (io_rxd ), //i - .io_dataOut (io_rxd_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlRxState_START : stateMachine_state_string = "START "; - UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - io_error = 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - end - UartCtrlRxState_START : begin - end - UartCtrlRxState_DATA : begin - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(!when_UartCtrlRx_l125) begin - io_error = 1'b1; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - io_error = 1'b1; - end - end - end - endcase - end - - assign io_rts = _zz_io_rts; - assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; - assign sampler_samples_0 = sampler_synchroniser; - always @(*) begin - bitTimer_tick = 1'b0; - if(sampler_tick) begin - if(when_UartCtrlRx_l43) begin - bitTimer_tick = 1'b1; - end - end - end - - assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); - assign break_valid = (break_counter == 7'h68); - assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); - assign io_break = break_valid; - assign io_read_valid = stateMachine_validReg; - assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); - assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); - assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); - assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); - assign when_UartCtrlRx_l136 = (! sampler_value); - assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); - assign io_read_payload = stateMachine_shifter; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_rts <= 1'b0; - sampler_samples_1 <= 1'b1; - sampler_samples_2 <= 1'b1; - sampler_samples_3 <= 1'b1; - sampler_samples_4 <= 1'b1; - sampler_value <= 1'b1; - sampler_tick <= 1'b0; - break_counter <= 7'h0; - stateMachine_state <= UartCtrlRxState_IDLE; - stateMachine_validReg <= 1'b0; - end else begin - _zz_io_rts <= (! io_read_ready); - if(io_samplingTick) begin - sampler_samples_1 <= sampler_samples_0; - end - if(io_samplingTick) begin - sampler_samples_2 <= sampler_samples_1; - end - if(io_samplingTick) begin - sampler_samples_3 <= sampler_samples_2; - end - if(io_samplingTick) begin - sampler_samples_4 <= sampler_samples_3; - end - sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); - sampler_tick <= io_samplingTick; - if(sampler_value) begin - break_counter <= 7'h0; - end else begin - if(when_UartCtrlRx_l69) begin - break_counter <= (break_counter + 7'h01); - end - end - stateMachine_validReg <= 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - stateMachine_state <= UartCtrlRxState_START; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - stateMachine_state <= UartCtrlRxState_DATA; - if(when_UartCtrlRx_l103) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l111) begin - if(when_UartCtrlRx_l113) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_PARITY; - end - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l125) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end else begin - if(when_UartCtrlRx_l139) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(sampler_tick) begin - bitTimer_counter <= (bitTimer_counter - 3'b001); - end - if(bitTimer_tick) begin - bitCounter_value <= (bitCounter_value + 3'b001); - end - if(bitTimer_tick) begin - stateMachine_parity <= (stateMachine_parity ^ sampler_value); - end - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - bitTimer_counter <= 3'b010; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - stateMachine_shifter[bitCounter_value] <= sampler_value; - if(when_UartCtrlRx_l111) begin - bitCounter_value <= 3'b000; - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - input io_cts, - output io_txd, - input io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlTxState_IDLE = 3'd0; - localparam UartCtrlTxState_START = 3'd1; - localparam UartCtrlTxState_DATA = 3'd2; - localparam UartCtrlTxState_PARITY = 3'd3; - localparam UartCtrlTxState_STOP = 3'd4; - - wire [2:0] _zz_clockDivider_counter_valueNext; - wire [0:0] _zz_clockDivider_counter_valueNext_1; - wire [2:0] _zz_when_UartCtrlTx_l93; - wire [0:0] _zz_when_UartCtrlTx_l93_1; - reg clockDivider_counter_willIncrement; - wire clockDivider_counter_willClear; - reg [2:0] clockDivider_counter_valueNext; - reg [2:0] clockDivider_counter_value; - wire clockDivider_counter_willOverflowIfInc; - wire clockDivider_counter_willOverflow; - reg [2:0] tickCounter_value; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg stateMachine_txd; - wire when_UartCtrlTx_l58; - wire when_UartCtrlTx_l73; - wire when_UartCtrlTx_l76; - wire when_UartCtrlTx_l93; - reg _zz_io_txd; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; - assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; - assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlTxState_START : stateMachine_state_string = "START "; - UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - clockDivider_counter_willIncrement = 1'b0; - if(io_samplingTick) begin - clockDivider_counter_willIncrement = 1'b1; - end - end - - assign clockDivider_counter_willClear = 1'b0; - assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); - assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); - always @(*) begin - clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); - if(clockDivider_counter_willClear) begin - clockDivider_counter_valueNext = 3'b000; - end - end - - always @(*) begin - stateMachine_txd = 1'b1; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - stateMachine_txd = 1'b0; - end - UartCtrlTxState_DATA : begin - stateMachine_txd = io_write_payload[tickCounter_value]; - end - UartCtrlTxState_PARITY : begin - stateMachine_txd = stateMachine_parity; - end - default : begin - end - endcase - end - - always @(*) begin - io_write_ready = io_break; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - io_write_ready = 1'b1; - end - end - end - UartCtrlTxState_PARITY : begin - end - default : begin - end - endcase - end - - assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); - assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); - assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); - assign io_txd = _zz_io_txd; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter_value <= 3'b000; - stateMachine_state <= UartCtrlTxState_IDLE; - _zz_io_txd <= 1'b1; - end else begin - clockDivider_counter_value <= clockDivider_counter_valueNext; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - if(when_UartCtrlTx_l58) begin - stateMachine_state <= UartCtrlTxState_START; - end - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_DATA; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - if(when_UartCtrlTx_l76) begin - stateMachine_state <= UartCtrlTxState_STOP; - end else begin - stateMachine_state <= UartCtrlTxState_PARITY; - end - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_STOP; - end - end - default : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l93) begin - stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); - end - end - end - endcase - _zz_io_txd <= (stateMachine_txd && (! io_break)); - end - end - - always @(posedge io_systemClk) begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= (tickCounter_value + 3'b001); - end - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); - end - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - tickCounter_value <= 3'b000; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - tickCounter_value <= 3'b000; - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - initial begin - `ifndef SYNTHESIS - buffers_0 = $urandom; - buffers_1 = $urandom; - `endif - end - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - - -endmodule - -module BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input systemCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_define.vh b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_define.vh deleted file mode 100644 index c60c9f4..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_define.vh +++ /dev/null @@ -1,45 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2022.1.196 -// IP Version: 2.2 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.v b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.v deleted file mode 100644 index 4b3fc22..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.v +++ /dev/null @@ -1,76 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -sapphire u_sapphire( -.io_systemClk ( io_systemClk ), -.jtagCtrl_enable ( jtagCtrl_enable ), -.jtagCtrl_tdi ( jtagCtrl_tdi ), -.jtagCtrl_capture ( jtagCtrl_capture ), -.jtagCtrl_shift ( jtagCtrl_shift ), -.jtagCtrl_update ( jtagCtrl_update ), -.jtagCtrl_reset ( jtagCtrl_reset ), -.jtagCtrl_tdo ( jtagCtrl_tdo ), -.jtagCtrl_tck ( jtagCtrl_tck ), -.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), -.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), -.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), -.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), -.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), -.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), -.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), -.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), -.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), -.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), -.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), -.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), -.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), -.system_spi_0_io_ss ( system_spi_0_io_ss ), -.io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), -.io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), -.io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), -.io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), -.io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), -.io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), -.io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), -.io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), -.io_asyncReset ( io_asyncReset ), -.io_systemReset ( io_systemReset ), -.system_uart_0_io_txd ( system_uart_0_io_txd ), -.system_uart_0_io_rxd ( system_uart_0_io_rxd ) -); diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.vhd b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.vhd deleted file mode 100644 index a8c601e..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.vhd +++ /dev/null @@ -1,118 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// -------------- Begin Cut here for COMPONENT Declaration ------ -COMPONENT sapphire is -PORT ( -io_systemClk : in std_logic; -jtagCtrl_enable : in std_logic; -jtagCtrl_tdi : in std_logic; -jtagCtrl_capture : in std_logic; -jtagCtrl_shift : in std_logic; -jtagCtrl_update : in std_logic; -jtagCtrl_reset : in std_logic; -jtagCtrl_tdo : out std_logic; -jtagCtrl_tck : in std_logic; -system_spi_0_io_data_0_read : in std_logic; -system_spi_0_io_data_0_write : out std_logic; -system_spi_0_io_data_0_writeEnable : out std_logic; -system_spi_0_io_data_1_read : in std_logic; -system_spi_0_io_data_1_write : out std_logic; -system_spi_0_io_data_1_writeEnable : out std_logic; -system_spi_0_io_data_2_read : in std_logic; -system_spi_0_io_data_2_write : out std_logic; -system_spi_0_io_data_2_writeEnable : out std_logic; -system_spi_0_io_data_3_read : in std_logic; -system_spi_0_io_data_3_write : out std_logic; -system_spi_0_io_data_3_writeEnable : out std_logic; -system_spi_0_io_sclk_write : out std_logic; -system_spi_0_io_ss : out std_logic_vector(0 to 0); -io_apbSlave_0_PADDR : out std_logic_vector(15 downto 0); -io_apbSlave_0_PENABLE : out std_logic; -io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0); -io_apbSlave_0_PREADY : in std_logic; -io_apbSlave_0_PSEL : out std_logic; -io_apbSlave_0_PSLVERROR : in std_logic; -io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0); -io_apbSlave_0_PWRITE : out std_logic; -io_asyncReset : in std_logic; -io_systemReset : out std_logic; -system_uart_0_io_txd : out std_logic; -system_uart_0_io_rxd : in std_logic); -END COMPONENT; ----------------------- End COMPONENT Declaration ------------ - -------------- Begin Cut here for INSTANTIATION Template ----- -u_sapphire : sapphire -PORT MAP ( -io_systemClk => io_systemClk, -jtagCtrl_enable => jtagCtrl_enable, -jtagCtrl_tdi => jtagCtrl_tdi, -jtagCtrl_capture => jtagCtrl_capture, -jtagCtrl_shift => jtagCtrl_shift, -jtagCtrl_update => jtagCtrl_update, -jtagCtrl_reset => jtagCtrl_reset, -jtagCtrl_tdo => jtagCtrl_tdo, -jtagCtrl_tck => jtagCtrl_tck, -system_spi_0_io_data_0_read => system_spi_0_io_data_0_read, -system_spi_0_io_data_0_write => system_spi_0_io_data_0_write, -system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable, -system_spi_0_io_data_1_read => system_spi_0_io_data_1_read, -system_spi_0_io_data_1_write => system_spi_0_io_data_1_write, -system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable, -system_spi_0_io_data_2_read => system_spi_0_io_data_2_read, -system_spi_0_io_data_2_write => system_spi_0_io_data_2_write, -system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable, -system_spi_0_io_data_3_read => system_spi_0_io_data_3_read, -system_spi_0_io_data_3_write => system_spi_0_io_data_3_write, -system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable, -system_spi_0_io_sclk_write => system_spi_0_io_sclk_write, -system_spi_0_io_ss => system_spi_0_io_ss, -io_apbSlave_0_PADDR => io_apbSlave_0_PADDR, -io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE, -io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA, -io_apbSlave_0_PREADY => io_apbSlave_0_PREADY, -io_apbSlave_0_PSEL => io_apbSlave_0_PSEL, -io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR, -io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA, -io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE, -io_asyncReset => io_asyncReset, -io_systemReset => io_systemReset, -system_uart_0_io_txd => system_uart_0_io_txd, -system_uart_0_io_rxd => system_uart_0_io_rxd); ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/settings.json b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/settings.json deleted file mode 100644 index 594e31f..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/settings.json +++ /dev/null @@ -1,156 +0,0 @@ -{ - "args": [ - "-o", - "sapphire", - "--base_path", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip", - "--vlnv", - { - "vendor": "efinixinc.com", - "library": "soc", - "name": "efx_soc", - "version": "2.2" - } - ], - "conf": { - "HexFile_PathEnable": "0", - "HexFile_Path": "", - "APBSlave0_Size": "65536", - "DEVKIT_CUSTOM": "sapphireBoard_rev0", - "LDSize": "124", - "LDStackSize": "4", - "DEVKIT": "2", - "DEBUG": "1", - "SOFT_TAP": "0", - "TAP_COUNT": "0", - "TAP_SEL": "8", - "Frequency": "50", - "PeriFrequencyEnable": "0", - "PeriFrequency": "50", - "UART2_INT_ID": "3", - "TEST": "0", - "Base_M_AXIS": "3774873600", - "APBSlave0": "1", - "APBSlave2": "0", - "Base_M_IO": "4160749568", - "APBSlave1": "0", - "APBSlave3": "0", - "USER_1_INTR_ID": "17", - "USER_1_INTR": "0", - "USER_0_INTR_ID": "16", - "USER_0_INTR": "0", - "USER_2_INTR": "0", - "USER_2_INTR_ID": "22", - "USER_3_INTR": "0", - "USER_3_INTR_ID": "23", - "USER_4_INTR": "0", - "USER_4_INTR_ID": "24", - "USER_5_INTR": "0", - "USER_5_INTR_ID": "25", - "USER_6_INTR": "0", - "USER_6_INTR_ID": "26", - "USER_7_INTR": "0", - "USER_7_INTR_ID": "27", - "APBSlave4": "0", - "CustomInstruction": "0", - "ATMEXT": "0", - "CMREXT": "0", - "FPEXT": "1", - "FPU": "0", - "LINUX": "0", - "ICACHEWAY": "1", - "DCACHEWAY": "1", - "CpuCount": "1", - "ICacheSize": "4096", - "DCacheSize": "4096", - "Cache": "1", - "DDR": "0", - "DDR_AXI4": "0", - "DDRWidth": "128", - "DDRSize": "3758096384", - "OCRSize": "32768", - "AXISlave": "0", - "AXISlaveSize": "16777216", - "GPIO1_INT_ID1": "15", - "GPIO1_INT_ID0": "14", - "GPIO0_INT_ID1": "13", - "GPIO0_INT_ID0": "12", - "GPIO0": "0", - "GPIO0Width": "4", - "GPIO1Width": "8", - "GPIO1": "0", - "UART0_INT_ID": "1", - "IOSize": "4096", - "UART0_M_Addr": "4096", - "UART1_M_Addr": "8192", - "UART2_M_Addr": "12288", - "SPI0_M_Addr": "24576", - "SPI1_M_Addr": "16384", - "SPI2_M_Addr": "20480", - "I2C0_M_Addr": "40960", - "I2C1_M_Addr": "45056", - "I2C2_M_Addr": "49152", - "GPIO0_M_Addr": "53248", - "GPIO1_M_Addr": "57344", - "APBSlave0_M_Addr": "1048576", - "APBSlave1_M_Addr": "2097152", - "APBSlave2_M_Addr": "3145728", - "APBSlave3_M_Addr": "4194304", - "APBSlave4_M_Addr": "5242880", - "UART0": "1", - "UART2": "0", - "UART1_INT_ID": "2", - "UART1": "0", - "SPI2": "0", - "SPI2DW": "8", - "SPI2SS": "1", - "SPI1_INT_ID": "5", - "SPI1": "0", - "SPI1DW": "8", - "SPI1SS": "1", - "SPI0_INT_ID": "4", - "SPI0": "1", - "SPI0DW": "8", - "SPI0SS": "1", - "I2C2_INT_ID": "10", - "ADDR_Scheme": "0", - "I2C2": "0", - "I2C1": "0", - "SPI2_INT_ID": "6", - "I2C1_INT_ID": "9", - "I2C0_INT_ID": "8", - "I2C0": "0", - "AXIMasterWidth_1": "32", - "AXIMaster_1": "0", - "AXIMasterWidth": "32", - "AXIMaster": "1", - "USER_TIMER0": "0", - "USER_TIMER0_CNT_WIDTH": "12", - "USER_TIMER0_PS_WIDTH": "8", - "USER_TIMER0_INT_ID": "19", - "USER_TIMER0_M_Addr": "61440", - "USER_TIMER1": "0", - "USER_TIMER1_CNT_WIDTH": "12", - "USER_TIMER1_PS_WIDTH": "8", - "USER_TIMER1_INT_ID": "20", - "USER_TIMER1_M_Addr": "65536", - "USER_TIMER2": "0", - "USER_TIMER2_CNT_WIDTH": "12", - "USER_TIMER2_PS_WIDTH": "8", - "USER_TIMER2_INT_ID": "21", - "USER_TIMER2_M_Addr": "69632" - }, - "output": { - "external_generator": [], - "external_source": [ - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.v", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire.v", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_define.vh", - "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd" - ], - "external_script": [], - "external_embedded_sw": [] - }, - "sw_version": "2022.1.196", - "generated_date": "2022-08-08T02:57:54.948573" -} \ No newline at end of file diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v deleted file mode 100644 index d8f0f2f..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v +++ /dev/null @@ -1,14093 +0,0 @@ -// Generator : SpinalHDL v1.7.1-SNAPSHOT git head : 2aaf6e4d1af9719ce8d12a973793990e489d8055 -// Component : EfxSapphireSoc - -`timescale 1ns/1ps - -module EfxSapphireSoc ( - input io_systemClk, - input io_asyncReset, - input jtagCtrl_tck, - output reg io_systemReset, - input jtagCtrl_tdi, - input jtagCtrl_enable, - input jtagCtrl_capture, - input jtagCtrl_shift, - input jtagCtrl_update, - input jtagCtrl_reset, - output jtagCtrl_tdo, - output system_uart_0_io_txd, - input system_uart_0_io_rxd, - output [15:0] io_apbSlave_0_PADDR, - output [0:0] io_apbSlave_0_PSEL, - output io_apbSlave_0_PENABLE, - input io_apbSlave_0_PREADY, - output io_apbSlave_0_PWRITE, - output [31:0] io_apbSlave_0_PWDATA, - input [31:0] io_apbSlave_0_PRDATA, - input io_apbSlave_0_PSLVERROR, - output [0:0] system_spi_0_io_sclk_write, - output system_spi_0_io_data_0_writeEnable, - input [0:0] system_spi_0_io_data_0_read, - output [0:0] system_spi_0_io_data_0_write, - output system_spi_0_io_data_1_writeEnable, - input [0:0] system_spi_0_io_data_1_read, - output [0:0] system_spi_0_io_data_1_write, - output system_spi_0_io_data_2_writeEnable, - input [0:0] system_spi_0_io_data_2_read, - output [0:0] system_spi_0_io_data_2_write, - output system_spi_0_io_data_3_writeEnable, - input [0:0] system_spi_0_io_data_3_read, - output [0:0] system_spi_0_io_data_3_write, - output [0:0] system_spi_0_io_ss -); - - reg system_cores_0_logic_cpu_dBus_rsp_valid; - wire system_cores_0_logic_cpu_dBus_rsp_payload_error; - wire system_cores_0_logic_cpu_debug_bus_cmd_payload_wr; - wire system_cores_0_logic_cpu_iBus_rsp_payload_error; - wire bufferCC_5_io_dataOut; - wire bufferCC_6_io_dataOut; - wire system_cores_0_logic_cpu_dBus_cmd_valid; - wire system_cores_0_logic_cpu_dBus_cmd_payload_wr; - wire system_cores_0_logic_cpu_dBus_cmd_payload_uncached; - wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_address; - wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_data; - wire [3:0] system_cores_0_logic_cpu_dBus_cmd_payload_mask; - wire [2:0] system_cores_0_logic_cpu_dBus_cmd_payload_size; - wire system_cores_0_logic_cpu_dBus_cmd_payload_last; - wire system_cores_0_logic_cpu_debug_bus_cmd_ready; - wire [31:0] system_cores_0_logic_cpu_debug_bus_rsp_data; - wire system_cores_0_logic_cpu_debug_resetOut; - wire system_cores_0_logic_cpu_iBus_cmd_valid; - wire [31:0] system_cores_0_logic_cpu_iBus_cmd_payload_address; - wire [2:0] system_cores_0_logic_cpu_iBus_cmd_payload_size; - wire system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; - wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid; - wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last; - wire [0:0] system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment; - wire system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready; - wire system_hardJtag_debug_logic_debugger_io_remote_cmd_ready; - wire system_hardJtag_debug_logic_debugger_io_remote_rsp_valid; - wire system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error; - wire [31:0] system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data; - wire system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; - wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address; - wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; - wire system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr; - wire [1:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size; - wire bufferCC_7_io_dataOut; - wire bmbDecoder_4_io_input_cmd_ready; - wire bmbDecoder_4_io_input_rsp_valid; - wire bmbDecoder_4_io_input_rsp_payload_last; - wire [0:0] bmbDecoder_4_io_input_rsp_payload_fragment_opcode; - wire [31:0] bmbDecoder_4_io_input_rsp_payload_fragment_data; - wire bmbDecoder_4_io_outputs_0_cmd_valid; - wire bmbDecoder_4_io_outputs_0_cmd_payload_last; - wire [0:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; - wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address; - wire [1:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; - wire bmbDecoder_4_io_outputs_0_rsp_ready; - wire system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; - wire system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; - wire system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; - wire system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; - wire system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; - wire system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; - wire system_fabric_iBus_bmb_decoder_io_input_cmd_ready; - wire system_fabric_iBus_bmb_decoder_io_input_rsp_valid; - wire system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; - wire [0:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; - wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid; - wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - wire system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready; - wire system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; - wire system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; - wire system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; - wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; - wire system_bridge_bmb_arbiter_io_inputs_1_cmd_ready; - wire system_bridge_bmb_arbiter_io_inputs_1_rsp_valid; - wire system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last; - wire [0:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data; - wire system_bridge_bmb_arbiter_io_output_cmd_valid; - wire system_bridge_bmb_arbiter_io_output_cmd_payload_last; - wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; - wire system_bridge_bmb_arbiter_io_output_rsp_ready; - wire system_bridge_bmb_decoder_io_input_cmd_ready; - wire system_bridge_bmb_decoder_io_input_rsp_valid; - wire system_bridge_bmb_decoder_io_input_rsp_payload_last; - wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; - wire system_bridge_bmb_decoder_io_outputs_0_cmd_valid; - wire system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - wire system_bridge_bmb_decoder_io_outputs_0_rsp_ready; - wire system_bridge_bmb_decoder_io_outputs_1_cmd_valid; - wire system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last; - wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - wire system_bridge_bmb_decoder_io_outputs_1_rsp_ready; - wire system_ramA_logic_io_bus_cmd_ready; - wire system_ramA_logic_io_bus_rsp_valid; - wire system_ramA_logic_io_bus_rsp_payload_last; - wire [0:0] system_ramA_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_ramA_logic_io_bus_rsp_payload_fragment_data; - wire [3:0] system_ramA_logic_io_bus_rsp_payload_fragment_context; - wire system_bridge_bmb_unburstify_io_input_cmd_ready; - wire system_bridge_bmb_unburstify_io_input_rsp_valid; - wire system_bridge_bmb_unburstify_io_input_rsp_payload_last; - wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context; - wire system_bridge_bmb_unburstify_io_output_cmd_valid; - wire system_bridge_bmb_unburstify_io_output_cmd_payload_last; - wire [0:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address; - wire [1:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; - wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; - wire system_bridge_bmb_unburstify_io_output_rsp_ready; - wire system_bridge_bmb_unburstify_1_io_input_cmd_ready; - wire system_bridge_bmb_unburstify_1_io_input_rsp_valid; - wire system_bridge_bmb_unburstify_1_io_input_rsp_payload_last; - wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context; - wire system_bridge_bmb_unburstify_1_io_output_cmd_valid; - wire system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; - wire [0:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address; - wire [1:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; - wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; - wire system_bridge_bmb_unburstify_1_io_output_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; - wire system_bmbPeripheral_bmb_decoder_io_input_rsp_valid; - wire system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - wire system_clint_logic_io_bus_cmd_ready; - wire system_clint_logic_io_bus_rsp_valid; - wire system_clint_logic_io_bus_rsp_payload_last; - wire [0:0] system_clint_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_clint_logic_io_bus_rsp_payload_fragment_data; - wire [3:0] system_clint_logic_io_bus_rsp_payload_fragment_context; - wire [0:0] system_clint_logic_io_timerInterrupt; - wire [0:0] system_clint_logic_io_softwareInterrupt; - wire [63:0] system_clint_logic_io_time; - wire system_uart_0_io_logic_io_bus_cmd_ready; - wire system_uart_0_io_logic_io_bus_rsp_valid; - wire system_uart_0_io_logic_io_bus_rsp_payload_last; - wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - wire [3:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - wire system_uart_0_io_logic_io_uart_txd; - wire system_uart_0_io_logic_io_interrupt; - wire system_spi_0_io_logic_io_ctrl_cmd_ready; - wire system_spi_0_io_logic_io_ctrl_rsp_valid; - wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; - wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - wire [3:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; - wire [0:0] system_spi_0_io_logic_io_spi_ss; - wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; - wire system_spi_0_io_logic_io_spi_data_0_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; - wire system_spi_0_io_logic_io_spi_data_1_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; - wire system_spi_0_io_logic_io_spi_data_2_writeEnable; - wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; - wire system_spi_0_io_logic_io_spi_data_3_writeEnable; - wire system_spi_0_io_logic_io_interrupt; - wire io_apbSlave_0_logic_io_input_cmd_ready; - wire io_apbSlave_0_logic_io_input_rsp_valid; - wire io_apbSlave_0_logic_io_input_rsp_payload_last; - wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - wire [3:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - wire [15:0] io_apbSlave_0_logic_io_output_PADDR; - wire [0:0] io_apbSlave_0_logic_io_output_PSEL; - wire io_apbSlave_0_logic_io_output_PENABLE; - wire io_apbSlave_0_logic_io_output_PWRITE; - wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; - wire [29:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - wire [6:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1; - reg debugCd_logic_inputResetTrigger; - reg debugCd_logic_outputResetUnbuffered; - reg [11:0] debugCd_logic_holdingLogic_resetCounter; - wire when_ClockDomainGenerator_l77; - reg debugCd_logic_outputReset; - wire debugCd_logic_inputResetAdapter_stuff_syncTrigger; - reg systemCd_logic_inputResetTrigger; - reg systemCd_logic_outputResetUnbuffered; - reg [5:0] systemCd_logic_holdingLogic_resetCounter; - wire when_ClockDomainGenerator_l77_1; - reg systemCd_logic_outputReset; - wire system_cores_0_iBus_cmd_valid; - wire system_cores_0_iBus_cmd_ready; - wire system_cores_0_iBus_cmd_payload_last; - wire [0:0] system_cores_0_iBus_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_cmd_payload_fragment_address; - wire [5:0] system_cores_0_iBus_cmd_payload_fragment_length; - wire system_cores_0_iBus_rsp_valid; - wire system_cores_0_iBus_rsp_ready; - wire system_cores_0_iBus_rsp_payload_last; - wire [0:0] system_cores_0_iBus_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_rsp_payload_fragment_data; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; - reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; - wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; - wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context; - wire system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; - reg [5:0] _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - wire when_DataCache_l532; - reg system_cores_0_debugReset; - wire system_cores_0_iBus_connector_decoder_cmd_valid; - wire system_cores_0_iBus_connector_decoder_cmd_ready; - wire system_cores_0_iBus_connector_decoder_cmd_payload_last; - wire [0:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; - wire system_cores_0_iBus_connector_decoder_rsp_valid; - wire system_cores_0_iBus_connector_decoder_rsp_ready; - wire system_cores_0_iBus_connector_decoder_rsp_payload_last; - wire [0:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; - reg _zz_system_cores_0_iBus_connector_decoder_rsp_ready; - wire system_cores_0_iBus_cmd_combStage_valid; - wire system_cores_0_iBus_cmd_combStage_ready; - wire system_cores_0_iBus_cmd_combStage_payload_last; - wire [0:0] system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; - wire [31:0] system_cores_0_iBus_cmd_combStage_payload_fragment_address; - wire [5:0] system_cores_0_iBus_cmd_combStage_payload_fragment_length; - wire _zz_system_cores_0_iBus_rsp_valid; - reg _zz_system_cores_0_iBus_rsp_valid_1; - reg _zz_system_cores_0_iBus_rsp_payload_last; - reg [0:0] _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_cores_0_iBus_rsp_payload_fragment_data; - wire when_Stream_l368; - wire system_cores_0_dBus_connector_decoder_cmd_valid; - wire system_cores_0_dBus_connector_decoder_cmd_ready; - wire system_cores_0_dBus_connector_decoder_cmd_payload_last; - wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; - wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; - wire system_cores_0_dBus_connector_decoder_rsp_valid; - wire system_cores_0_dBus_connector_decoder_rsp_ready; - wire system_cores_0_dBus_connector_decoder_rsp_payload_last; - wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; - wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; - wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; - wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; - wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; - wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; - wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; - reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; - reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; - reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; - reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; - reg [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; - reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; - reg [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; - reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; - wire when_Stream_l368_1; - wire system_hardJtag_debug_logic_mmMaster_cmd_valid; - wire system_hardJtag_debug_logic_mmMaster_cmd_ready; - wire system_hardJtag_debug_logic_mmMaster_cmd_payload_last; - wire [0:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - wire [1:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; - wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; - wire [3:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - wire system_hardJtag_debug_logic_mmMaster_rsp_valid; - wire system_hardJtag_debug_logic_mmMaster_rsp_ready; - wire system_hardJtag_debug_logic_mmMaster_rsp_payload_last; - wire [0:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data; - reg [3:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - wire system_hardJtag_debug_bmb_connector_decoder_cmd_valid; - wire system_hardJtag_debug_bmb_connector_decoder_cmd_ready; - wire system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last; - wire [0:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address; - wire [1:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask; - wire system_hardJtag_debug_bmb_connector_decoder_rsp_valid; - wire system_hardJtag_debug_bmb_connector_decoder_rsp_ready; - wire system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; - wire [0:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; - wire system_fabric_iBus_bmb_cmd_valid; - reg system_fabric_iBus_bmb_cmd_ready; - wire system_fabric_iBus_bmb_cmd_payload_last; - wire [0:0] system_fabric_iBus_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_cmd_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_cmd_payload_fragment_length; - wire system_fabric_iBus_bmb_rsp_valid; - wire system_fabric_iBus_bmb_rsp_ready; - wire system_fabric_iBus_bmb_rsp_payload_last; - wire [0:0] system_fabric_iBus_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_rsp_payload_fragment_data; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire system_cores_0_debugBmb_cmd_valid; - wire system_cores_0_debugBmb_cmd_ready; - wire system_cores_0_debugBmb_cmd_payload_last; - wire [0:0] system_cores_0_debugBmb_cmd_payload_fragment_opcode; - wire [7:0] system_cores_0_debugBmb_cmd_payload_fragment_address; - wire [1:0] system_cores_0_debugBmb_cmd_payload_fragment_length; - wire [31:0] system_cores_0_debugBmb_cmd_payload_fragment_data; - wire [3:0] system_cores_0_debugBmb_cmd_payload_fragment_mask; - wire system_cores_0_debugBmb_rsp_valid; - wire system_cores_0_debugBmb_rsp_ready; - wire system_cores_0_debugBmb_rsp_payload_last; - wire [0:0] system_cores_0_debugBmb_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_debugBmb_rsp_payload_fragment_data; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - reg _zz_io_input_rsp_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; - wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; - reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; - reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; - reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; - reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; - reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; - wire when_Stream_l368_2; - wire _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire when_Stream_l368_3; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [7:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire system_cores_0_logic_cpu_debug_bus_cmd_fire; - reg system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; - wire system_fabric_dBusCoherent_bmb_cmd_valid; - wire system_fabric_dBusCoherent_bmb_cmd_ready; - wire system_fabric_dBusCoherent_bmb_cmd_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_rsp_valid; - wire system_fabric_dBusCoherent_bmb_rsp_ready; - wire system_fabric_dBusCoherent_bmb_rsp_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; - wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; - wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; - wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; - wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; - wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; - wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; - wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready; - wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; - wire [5:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; - wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; - wire [3:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; - wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid; - wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; - wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data; - wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context; - wire system_fabric_dBus_bmb_cmd_valid; - wire system_fabric_dBus_bmb_cmd_ready; - wire system_fabric_dBus_bmb_cmd_payload_last; - wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBus_bmb_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBus_bmb_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_context; - wire system_fabric_dBus_bmb_rsp_valid; - wire system_fabric_dBus_bmb_rsp_ready; - wire system_fabric_dBus_bmb_rsp_payload_last; - wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_context; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [5:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_fabric_iBus_bmb_cmd_m2sPipe_valid; - wire system_fabric_iBus_bmb_cmd_m2sPipe_ready; - wire system_fabric_iBus_bmb_cmd_m2sPipe_payload_last; - wire [0:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode; - wire [31:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address; - wire [5:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length; - reg system_fabric_iBus_bmb_cmd_rValid; - reg system_fabric_iBus_bmb_cmd_rData_last; - reg [0:0] system_fabric_iBus_bmb_cmd_rData_fragment_opcode; - reg [31:0] system_fabric_iBus_bmb_cmd_rData_fragment_address; - reg [5:0] system_fabric_iBus_bmb_cmd_rData_fragment_length; - wire when_Stream_l368_4; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; - wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - wire system_bridge_bmb_cmd_valid; - wire system_bridge_bmb_cmd_ready; - wire system_bridge_bmb_cmd_payload_last; - wire [0:0] system_bridge_bmb_cmd_payload_fragment_source; - wire [0:0] system_bridge_bmb_cmd_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_cmd_payload_fragment_address; - wire [5:0] system_bridge_bmb_cmd_payload_fragment_length; - wire [31:0] system_bridge_bmb_cmd_payload_fragment_data; - wire [3:0] system_bridge_bmb_cmd_payload_fragment_mask; - wire [0:0] system_bridge_bmb_cmd_payload_fragment_context; - wire system_bridge_bmb_rsp_valid; - wire system_bridge_bmb_rsp_ready; - wire system_bridge_bmb_rsp_payload_last; - wire [0:0] system_bridge_bmb_rsp_payload_fragment_source; - wire [0:0] system_bridge_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_rsp_payload_fragment_data; - wire [0:0] system_bridge_bmb_rsp_payload_fragment_context; - wire system_bridge_bmb_cmd_s2mPipe_valid; - reg system_bridge_bmb_cmd_s2mPipe_ready; - wire system_bridge_bmb_cmd_s2mPipe_payload_last; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; - wire [5:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; - wire [3:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; - reg system_bridge_bmb_cmd_rValid; - reg system_bridge_bmb_cmd_rData_last; - reg [0:0] system_bridge_bmb_cmd_rData_fragment_source; - reg [0:0] system_bridge_bmb_cmd_rData_fragment_opcode; - reg [31:0] system_bridge_bmb_cmd_rData_fragment_address; - reg [5:0] system_bridge_bmb_cmd_rData_fragment_length; - reg [31:0] system_bridge_bmb_cmd_rData_fragment_data; - reg [3:0] system_bridge_bmb_cmd_rData_fragment_mask; - reg [0:0] system_bridge_bmb_cmd_rData_fragment_context; - wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid; - wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; - wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address; - wire [5:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length; - wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data; - wire [3:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask; - wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context; - reg system_bridge_bmb_cmd_s2mPipe_rValid; - reg system_bridge_bmb_cmd_s2mPipe_rData_last; - reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; - reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; - reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; - reg [5:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; - reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; - reg [3:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; - reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; - wire when_Stream_l368_5; - wire system_bmbPeripheral_bmb_cmd_valid; - wire system_bmbPeripheral_bmb_cmd_ready; - wire system_bmbPeripheral_bmb_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_rsp_valid; - wire system_bmbPeripheral_bmb_rsp_ready; - wire system_bmbPeripheral_bmb_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - reg _zz_io_bus_rsp_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; - wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last; - wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode; - wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address; - wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length; - wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask; - wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context; - wire _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - reg [0:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - reg [3:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire when_Stream_l368_6; - wire _zz_io_input_rsp_ready_1; - wire system_bmbPeripheral_bmb_cmd_combStage_valid; - wire system_bmbPeripheral_bmb_cmd_combStage_ready; - wire system_bmbPeripheral_bmb_cmd_combStage_payload_last; - wire [0:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask; - wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context; - wire _zz_system_bmbPeripheral_bmb_rsp_valid; - reg _zz_system_bmbPeripheral_bmb_rsp_valid_1; - reg _zz_system_bmbPeripheral_bmb_rsp_payload_last; - reg [0:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; - reg [3:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [15:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - reg _zz_timerInterrupt; - reg _zz_softwareInterrupt; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_ready_1; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; - wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; - wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; - wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; - wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; - wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; - reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; - reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - reg [3:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire [1:0] system_uart_0_io_interrupt_plic_gateway_priority; - reg system_uart_0_io_interrupt_plic_gateway_ip; - reg system_uart_0_io_interrupt_plic_gateway_waitCompletion; - wire when_PlicGateway_l21; - wire [1:0] system_spi_0_io_interrupt_plic_gateway_priority; - reg system_spi_0_io_interrupt_plic_gateway_ip; - reg system_spi_0_io_interrupt_plic_gateway_waitCompletion; - wire when_PlicGateway_l21_1; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; - wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; - wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; - wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; - wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; - wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; - reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; - reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - reg [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_1; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_1; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; - wire system_plic_logic_bmb_cmd_valid; - wire system_plic_logic_bmb_cmd_ready; - wire system_plic_logic_bmb_cmd_payload_last; - wire [0:0] system_plic_logic_bmb_cmd_payload_fragment_opcode; - wire [21:0] system_plic_logic_bmb_cmd_payload_fragment_address; - wire [1:0] system_plic_logic_bmb_cmd_payload_fragment_length; - wire [31:0] system_plic_logic_bmb_cmd_payload_fragment_data; - wire [3:0] system_plic_logic_bmb_cmd_payload_fragment_context; - wire system_plic_logic_bmb_rsp_valid; - wire system_plic_logic_bmb_rsp_ready; - wire system_plic_logic_bmb_rsp_payload_last; - wire [0:0] system_plic_logic_bmb_rsp_payload_fragment_opcode; - wire [31:0] system_plic_logic_bmb_rsp_payload_fragment_data; - wire [3:0] system_plic_logic_bmb_rsp_payload_fragment_context; - reg system_plic_logic_bus_readHaltTrigger; - wire system_plic_logic_bus_writeHaltTrigger; - wire system_plic_logic_bus_rsp_valid; - wire system_plic_logic_bus_rsp_ready; - wire system_plic_logic_bus_rsp_payload_last; - wire [0:0] system_plic_logic_bus_rsp_payload_fragment_opcode; - reg [31:0] system_plic_logic_bus_rsp_payload_fragment_data; - wire [3:0] system_plic_logic_bus_rsp_payload_fragment_context; - wire _zz_system_plic_logic_bmb_rsp_valid; - reg _zz_system_plic_logic_bus_rsp_ready; - wire _zz_system_plic_logic_bmb_rsp_valid_1; - reg _zz_system_plic_logic_bmb_rsp_valid_2; - reg _zz_system_plic_logic_bmb_rsp_payload_last; - reg [0:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; - reg [31:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_data; - reg [3:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_context; - wire when_Stream_l368_7; - wire system_plic_logic_bus_askWrite; - wire system_plic_logic_bus_askRead; - wire system_plic_logic_bmb_cmd_fire; - wire system_plic_logic_bus_doWrite; - wire system_plic_logic_bmb_cmd_fire_1; - wire system_plic_logic_bus_doRead; - wire system_cores_0_externalInterrupt_plic_target_ie_0; - wire system_cores_0_externalInterrupt_plic_target_ie_1; - wire [1:0] system_cores_0_externalInterrupt_plic_target_threshold; - wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_0_priority; - wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_0_id; - wire system_cores_0_externalInterrupt_plic_target_requests_0_valid; - wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_1_priority; - wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_1_id; - wire system_cores_0_externalInterrupt_plic_target_requests_1_valid; - wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_2_priority; - wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_2_id; - wire system_cores_0_externalInterrupt_plic_target_requests_2_valid; - wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority; - wire [1:0] _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1; - wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2; - wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3; - reg [1:0] system_cores_0_externalInterrupt_plic_target_bestRequest_priority; - reg [2:0] system_cores_0_externalInterrupt_plic_target_bestRequest_id; - reg system_cores_0_externalInterrupt_plic_target_bestRequest_valid; - wire system_cores_0_externalInterrupt_plic_target_iep; - wire [2:0] system_cores_0_externalInterrupt_plic_target_claim; - reg [1:0] _zz_system_uart_0_io_interrupt_plic_gateway_priority; - reg [1:0] _zz_system_spi_0_io_interrupt_plic_gateway_priority; - reg system_plic_logic_bridge_claim_valid; - reg [2:0] system_plic_logic_bridge_claim_payload; - reg system_plic_logic_bridge_completion_valid; - reg [2:0] system_plic_logic_bridge_completion_payload; - reg system_plic_logic_bridge_coherencyStall_willIncrement; - wire system_plic_logic_bridge_coherencyStall_willClear; - reg [0:0] system_plic_logic_bridge_coherencyStall_valueNext; - reg [0:0] system_plic_logic_bridge_coherencyStall_value; - wire system_plic_logic_bridge_coherencyStall_willOverflowIfInc; - wire system_plic_logic_bridge_coherencyStall_willOverflow; - wire when_PlicMapper_l122; - reg [1:0] _zz_system_cores_0_externalInterrupt_plic_target_threshold; - reg system_plic_logic_bridge_targetMapping_0_targetCompletion_valid; - wire [2:0] system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; - reg _zz_system_cores_0_externalInterrupt_plic_target_ie_0; - reg _zz_system_cores_0_externalInterrupt_plic_target_ie_1; - reg system_cores_0_externalInterrupt_plic_target_iep_regNext; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_2; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_2; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_3; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_3; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - wire [21:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - wire [1:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; - wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_4; - wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; - wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_4; - wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; - wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; - wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; - wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; - wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; - wire when_BmbSlaveFactory_l71; - - assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address >>> 2); - assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); - BufferCC_2 bufferCC_5 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_5_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .io_asyncReset (io_asyncReset ) //i - ); - BufferCC_3 bufferCC_6 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_6_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset) //i - ); - VexRiscv system_cores_0_logic_cpu ( - .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o - .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i - .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o - .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o - .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o - .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o - .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o - .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o - .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o - .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i - .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i - .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i - .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i - .timerInterrupt (_zz_timerInterrupt ), //i - .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i - .softwareInterrupt (_zz_softwareInterrupt ), //i - .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i - .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o - .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i - .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i - .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i - .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o - .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o - .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o - .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i - .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o - .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o - .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i - .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i - .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - JtagBridgeNoTap system_hardJtag_debug_logic_jtagBridge ( - .io_ctrl_tdi (jtagCtrl_tdi ), //i - .io_ctrl_enable (jtagCtrl_enable ), //i - .io_ctrl_capture (jtagCtrl_capture ), //i - .io_ctrl_shift (jtagCtrl_shift ), //i - .io_ctrl_update (jtagCtrl_update ), //i - .io_ctrl_reset (jtagCtrl_reset ), //i - .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i - .jtagCtrl_tck (jtagCtrl_tck ) //i - ); - SystemDebugger system_hardJtag_debug_logic_debugger ( - .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i - .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o - .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i - .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i - .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o - .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i - .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o - .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o - .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i - .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o - .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o - .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i - .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BufferCC_4 bufferCC_7 ( - .io_dataIn (1'b0 ), //i - .io_dataOut (bufferCC_7_io_dataOut ), //o - .io_systemClk (io_systemClk ), //i - .system_cores_0_debugReset (system_cores_0_debugReset) //i - ); - BmbDecoder bmbDecoder_4 ( - .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i - .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i - .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - BmbExclusiveMonitor system_fabric_exclusiveMonitor_logic ( - .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i - .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i - .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i - .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i - ); - BmbDecoder_1 system_fabric_iBus_bmb_decoder ( - .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i - .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i - ); - BmbArbiter system_bridge_bmb_arbiter ( - .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i - .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o - .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i - .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i - .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i - .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i - .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o - .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i - .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o - .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o - .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o - .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o - .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o - .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i - .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i - .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o - .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o - .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o - .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o - .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o - .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i - .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_2 system_bridge_bmb_decoder ( - .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o - .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i - .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o - .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i - .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i - .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i - .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o - .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbOnChipRam system_ramA_logic ( - .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i - .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i - .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i - .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify system_bridge_bmb_unburstify ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUnburstify system_bridge_bmb_unburstify_1 ( - .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i - .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i - .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i - .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o - .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i - .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o - .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o - .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o - .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i - .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o - .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o - .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o - .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o - .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o - .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o - .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o - .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i - .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o - .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i - .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i - .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i - .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbDecoder_3 system_bmbPeripheral_bmb_decoder ( - .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i - .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i - .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i - .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o - .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i - .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o - .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i - .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o - .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o - .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o - .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i - .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o - .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i - .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i - .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i - .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i - .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o - .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i - .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o - .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o - .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o - .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i - .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o - .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i - .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i - .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i - .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i - .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o - .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i - .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o - .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o - .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o - .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i - .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o - .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i - .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i - .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i - .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i - .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o - .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i - .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o - .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o - .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o - .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i - .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o - .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i - .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i - .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i - .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i - .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o - .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i - .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o - .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o - .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o - .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o - .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o - .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o - .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o - .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i - .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o - .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i - .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i - .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i - .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbClint system_clint_logic ( - .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o - .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o - .io_time (system_clint_logic_io_time[63:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbUartCtrl system_uart_0_io_logic ( - .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o - .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i - .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i - .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o - .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i - .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o - .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o - .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o - .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o - .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o - .io_uart_rxd (system_uart_0_io_rxd ), //i - .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbSpiXdrMasterCtrl system_spi_0_io_logic ( - .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i - .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o - .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i - .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i - .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i - .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i - .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i - .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i - .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o - .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o - .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o - .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o - .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o - .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i - .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i - .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i - .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i - .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o - .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o - .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - BmbToApb3Bridge io_apbSlave_0_logic ( - .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i - .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o - .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i - .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i - .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i - .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i - .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i - .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i - .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o - .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i - .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o - .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o - .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o - .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o - .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o - .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o - .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o - .io_output_PREADY (io_apbSlave_0_PREADY ), //i - .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o - .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o - .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i - .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - initial begin - debugCd_logic_holdingLogic_resetCounter = 12'h0; - debugCd_logic_outputReset = 1'b1; - end - - always @(*) begin - debugCd_logic_inputResetTrigger = 1'b0; - if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin - debugCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - debugCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); - assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; - always @(*) begin - systemCd_logic_inputResetTrigger = 1'b0; - if(bufferCC_6_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - if(bufferCC_7_io_dataOut) begin - systemCd_logic_inputResetTrigger = 1'b1; - end - end - - always @(*) begin - systemCd_logic_outputResetUnbuffered = 1'b0; - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_outputResetUnbuffered = 1'b1; - end - end - - assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); - assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; - assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; - assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; - assign system_cores_0_iBus_cmd_payload_last = 1'b1; - assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_iBus_rsp_ready = 1'b1; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; - always @(*) begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; - case(system_cores_0_logic_cpu_dBus_cmd_payload_size) - 3'b000 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; - end - 3'b001 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; - end - 3'b010 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; - end - 3'b011 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; - end - 3'b100 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; - end - 3'b101 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; - end - 3'b110 : begin - _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; - end - default : begin - end - endcase - end - - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; - always @(*) begin - system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; - if(when_DataCache_l532) begin - system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; - end - end - - assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; - assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; - assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; - assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; - assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; - assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; - assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; - always @(*) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; - if(when_Stream_l368) begin - _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); - assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; - assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; - assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; - assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; - assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; - assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; - assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; - always @(*) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; - if(when_Stream_l368_1) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; - assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; - assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; - assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; - assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; - always @(*) begin - case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) - 2'b00 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; - end - 2'b01 : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; - end - default : begin - _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; - end - endcase - end - - assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; - assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; - assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; - assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; - assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; - assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; - assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; - assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; - assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; - assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); - always @(*) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_2) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; - always @(*) begin - _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_3) begin - _zz_io_input_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; - assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; - assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; - assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); - assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); - assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; - assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; - assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; - assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; - assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; - assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; - assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; - assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; - assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; - assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; - assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; - assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; - assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; - assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; - assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; - assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; - if(when_Stream_l368_4) begin - system_fabric_iBus_bmb_cmd_ready = 1'b1; - end - end - - assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); - assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; - assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; - assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; - assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; - assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; - assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; - assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; - assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; - assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; - assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; - assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; - assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; - assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; - assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; - assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; - assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; - assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; - assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; - assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; - assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; - assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; - assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; - assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); - assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); - assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); - always @(*) begin - system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_5) begin - system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; - assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; - assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; - assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; - assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; - assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; - assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; - assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; - always @(*) begin - _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - if(when_Stream_l368_6) begin - _zz_io_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); - assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; - assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; - assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; - assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; - assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); - assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; - assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; - assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; - assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; - assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; - assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; - assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; - assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; - assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; - assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); - assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); - assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); - assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; - assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; - assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; - assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; - assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; - assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; - assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; - assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; - assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; - assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; - assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; - assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - always @(*) begin - system_plic_logic_bus_readHaltTrigger = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bus_readHaltTrigger = 1'b1; - end - end - - assign system_plic_logic_bus_writeHaltTrigger = 1'b0; - assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); - assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); - always @(*) begin - _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; - if(when_Stream_l368_7) begin - _zz_system_plic_logic_bus_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); - assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; - assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; - assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); - assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); - assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); - assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; - assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; - assign system_plic_logic_bus_rsp_payload_last = 1'b1; - assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; - end - 22'h001000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; - end - 22'h000010 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; - end - 22'h200000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; - end - 22'h200004 : begin - system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; - end - 22'h002000 : begin - system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; - system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; - end - default : begin - end - endcase - end - - assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; - assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; - assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; - assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; - assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; - assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); - assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; - assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; - assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); - assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); - assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); - assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); - assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; - assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; - always @(*) begin - system_plic_logic_bridge_claim_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_valid = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_claim_payload = 3'bxxx; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doRead) begin - system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; - end - end - default : begin - end - endcase - end - - always @(*) begin - system_plic_logic_bridge_completion_valid = 1'b0; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_valid = 1'b1; - end - end - - always @(*) begin - system_plic_logic_bridge_completion_payload = 3'bxxx; - if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin - system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; - end - end - - always @(*) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; - if(when_PlicMapper_l122) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(when_BmbSlaveFactory_l71) begin - if(system_plic_logic_bus_askWrite) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - if(system_plic_logic_bus_askRead) begin - system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; - end - end - end - - assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; - assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); - assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); - always @(*) begin - system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); - if(system_plic_logic_bridge_coherencyStall_willClear) begin - system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; - end - end - - assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); - assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; - always @(*) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h200004 : begin - if(system_plic_logic_bus_doWrite) begin - system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; - assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; - assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; - assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; - assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; - assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; - assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; - assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; - assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; - assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; - assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; - assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; - assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; - assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; - assign when_BmbSlaveFactory_l71 = 1'b1; - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77) begin - debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); - end - if(debugCd_logic_inputResetTrigger) begin - debugCd_logic_holdingLogic_resetCounter <= 12'h0; - end - debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - if(when_ClockDomainGenerator_l77_1) begin - systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); - end - if(systemCd_logic_inputResetTrigger) begin - systemCd_logic_holdingLogic_resetCounter <= 6'h0; - end - systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; - end - - always @(posedge io_systemClk) begin - io_systemReset <= systemCd_logic_outputReset; - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; - _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; - _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; - system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; - system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; - system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; - end - if(system_bridge_bmb_cmd_ready) begin - system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; - system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; - system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; - system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; - system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; - system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; - system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; - system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; - system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; - end - if(_zz_io_input_rsp_ready_1) begin - _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; - _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; - end - _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; - _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_io_bus_rsp_ready_1) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; - _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; - _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; - _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; - end - system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); - system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); - system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); - system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; - end - - always @(posedge io_systemClk) begin - system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_fabric_iBus_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_rValid <= 1'b0; - system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; - system_plic_logic_bridge_coherencyStall_value <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; - end else begin - if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin - _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; - end - if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin - system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin - system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; - end - if(_zz_io_input_rsp_ready) begin - _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; - end - if(system_fabric_iBus_bmb_cmd_ready) begin - system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; - end - if(system_bridge_bmb_cmd_valid) begin - system_bridge_bmb_cmd_rValid <= 1'b1; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_rValid <= 1'b0; - end - if(system_bridge_bmb_cmd_s2mPipe_ready) begin - system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; - end - if(_zz_io_bus_rsp_ready) begin - _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; - end - if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; - end - if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin - _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(system_uart_0_io_logic_io_bus_rsp_valid) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; - end - if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin - _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; - end - if(when_PlicGateway_l21) begin - system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; - end - if(when_PlicGateway_l21_1) begin - system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; - end - if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin - system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; - end - if(_zz_system_plic_logic_bus_rsp_ready) begin - _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); - end - if(system_plic_logic_bridge_claim_valid) begin - case(system_plic_logic_bridge_claim_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; - end - default : begin - end - endcase - end - if(system_plic_logic_bridge_completion_valid) begin - case(system_plic_logic_bridge_completion_payload) - 3'b001 : begin - system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - 3'b100 : begin - system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; - end - default : begin - end - endcase - end - system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; - case(system_plic_logic_bmb_cmd_payload_fragment_address) - 22'h000004 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h000010 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h200000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; - end - end - 22'h002000 : begin - if(system_plic_logic_bus_doWrite) begin - _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; - _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; - end else begin - system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; - end - end - - -endmodule - -module BmbToApb3Bridge ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [15:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [3:0] io_input_rsp_payload_fragment_context, - output [15:0] io_output_PADDR, - output [0:0] io_output_PSEL, - output io_output_PENABLE, - input io_output_PREADY, - output io_output_PWRITE, - output [31:0] io_output_PWDATA, - input [31:0] io_output_PRDATA, - input io_output_PSLVERROR, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire bmbBuffer_cmd_valid; - reg bmbBuffer_cmd_ready; - wire bmbBuffer_cmd_payload_last; - wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; - wire [15:0] bmbBuffer_cmd_payload_fragment_address; - wire [1:0] bmbBuffer_cmd_payload_fragment_length; - wire [31:0] bmbBuffer_cmd_payload_fragment_data; - wire [3:0] bmbBuffer_cmd_payload_fragment_context; - reg bmbBuffer_rsp_valid; - reg bmbBuffer_rsp_ready; - wire bmbBuffer_rsp_payload_last; - reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_payload_fragment_context; - wire io_input_rsp_isStall; - wire _zz_io_input_cmd_ready; - wire bmbBuffer_rsp_m2sPipe_valid; - wire bmbBuffer_rsp_m2sPipe_ready; - wire bmbBuffer_rsp_m2sPipe_payload_last; - wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; - wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; - reg bmbBuffer_rsp_rValid; - reg bmbBuffer_rsp_rData_last; - reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; - reg [31:0] bmbBuffer_rsp_rData_fragment_data; - reg [3:0] bmbBuffer_rsp_rData_fragment_context; - wire when_Stream_l368; - reg state; - wire when_BmbToApb3Bridge_l46; - - assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); - assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); - assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); - assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; - assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - always @(*) begin - bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; - if(when_Stream_l368) begin - bmbBuffer_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); - assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; - assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; - assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; - assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; - assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; - assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; - always @(*) begin - bmbBuffer_cmd_ready = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_cmd_ready = 1'b1; - end - end - end - - assign io_output_PSEL[0] = bmbBuffer_cmd_valid; - assign io_output_PENABLE = state; - assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); - assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; - assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; - always @(*) begin - bmbBuffer_rsp_valid = 1'b0; - if(!when_BmbToApb3Bridge_l46) begin - if(io_output_PREADY) begin - bmbBuffer_rsp_valid = 1'b1; - end - end - end - - assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; - assign when_BmbToApb3Bridge_l46 = (! state); - assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign bmbBuffer_rsp_payload_last = 1'b1; - always @(*) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b0; - if(io_output_PSLVERROR) begin - bmbBuffer_rsp_payload_fragment_opcode = 1'b1; - end - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - bmbBuffer_rsp_rValid <= 1'b0; - state <= 1'b0; - end else begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; - end - if(when_BmbToApb3Bridge_l46) begin - state <= bmbBuffer_cmd_valid; - end else begin - if(io_output_PREADY) begin - state <= 1'b0; - end - end - end - end - - always @(posedge io_systemClk) begin - if(bmbBuffer_rsp_ready) begin - bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; - bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; - bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; - bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; - end - end - - -endmodule - -module BmbSpiXdrMasterCtrl ( - input io_ctrl_cmd_valid, - output io_ctrl_cmd_ready, - input io_ctrl_cmd_payload_last, - input [0:0] io_ctrl_cmd_payload_fragment_opcode, - input [11:0] io_ctrl_cmd_payload_fragment_address, - input [1:0] io_ctrl_cmd_payload_fragment_length, - input [31:0] io_ctrl_cmd_payload_fragment_data, - input [3:0] io_ctrl_cmd_payload_fragment_context, - output io_ctrl_rsp_valid, - input io_ctrl_rsp_ready, - output io_ctrl_rsp_payload_last, - output [0:0] io_ctrl_rsp_payload_fragment_opcode, - output [31:0] io_ctrl_rsp_payload_fragment_data, - output [3:0] io_ctrl_rsp_payload_fragment_context, - output [0:0] io_spi_sclk_write, - output io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output [0:0] io_spi_data_0_write, - output io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output [0:0] io_spi_data_1_write, - output io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output [0:0] io_spi_data_2_write, - output io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; - wire ctrl_io_cmd_ready; - wire ctrl_io_rsp_valid; - wire [7:0] ctrl_io_rsp_payload_data; - wire [0:0] ctrl_io_spi_sclk_write; - wire [0:0] ctrl_io_spi_ss; - wire [0:0] ctrl_io_spi_data_0_write; - wire ctrl_io_spi_data_0_writeEnable; - wire [0:0] ctrl_io_spi_data_1_write; - wire ctrl_io_spi_data_1_writeEnable; - wire [0:0] ctrl_io_spi_data_2_write; - wire ctrl_io_spi_data_2_writeEnable; - wire [0:0] ctrl_io_spi_data_3_write; - wire ctrl_io_spi_data_3_writeEnable; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; - wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; - wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; - wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; - wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_ctrl_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_ctrl_rsp_valid_1; - reg _zz_io_ctrl_rsp_valid_2; - reg _zz_io_ctrl_rsp_payload_last; - reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; - reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_ctrl_cmd_fire; - wire factory_doWrite; - wire io_ctrl_cmd_fire_1; - wire factory_doRead; - wire [31:0] mapping_cmdLogic_writeData; - reg mapping_cmdLogic_doRegular; - reg mapping_cmdLogic_doWriteLarge; - reg mapping_cmdLogic_doReadWriteLarge; - wire mapping_cmdLogic_streamUnbuffered_valid; - wire mapping_cmdLogic_streamUnbuffered_ready; - wire mapping_cmdLogic_streamUnbuffered_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_payload_read; - wire mapping_cmdLogic_streamUnbuffered_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; - wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; - wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - wire when_Stream_l368_1; - wire ctrl_io_rsp_toStream_valid; - wire ctrl_io_rsp_toStream_ready; - wire [7:0] ctrl_io_rsp_toStream_payload_data; - reg _zz_io_pop_ready; - reg _zz_io_pop_ready_1; - reg mapping_interruptCtrl_cmdIntEnable; - reg mapping_interruptCtrl_rspIntEnable; - wire mapping_interruptCtrl_cmdInt; - wire mapping_interruptCtrl_rspInt; - wire mapping_interruptCtrl_interrupt; - reg _zz_io_config_kind_cpol; - reg _zz_io_config_kind_cpha; - reg [1:0] _zz_io_config_mod; - reg [11:0] _zz_io_config_sclkToogle; - reg [11:0] _zz_io_config_ss_setup; - reg [11:0] _zz_io_config_ss_hold; - reg [11:0] _zz_io_config_ss_disable; - reg [0:0] _zz_io_config_ss_activeHigh; - wire [1:0] _zz_io_config_kind_cpol_1; - - TopLevel ctrl ( - .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i - .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i - .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i - .io_config_mod (_zz_io_config_mod[1:0] ), //i - .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i - .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i - .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i - .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i - .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i - .io_cmd_ready (ctrl_io_cmd_ready ), //o - .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i - .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i - .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i - .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i - .io_rsp_valid (ctrl_io_rsp_valid ), //o - .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o - .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o - .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o - .io_spi_data_0_read (io_spi_data_0_read ), //i - .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o - .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o - .io_spi_data_1_read (io_spi_data_1_read ), //i - .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o - .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o - .io_spi_data_2_read (io_spi_data_2_read ), //i - .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o - .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o - .io_spi_data_3_read (io_spi_data_3_read ), //i - .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o - .io_spi_ss (ctrl_io_spi_ss ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_2 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( - .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i - .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o - .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i - .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i - .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i - .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i - .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o - .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i - .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o - .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o - .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o - .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o - .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo_3 ctrl_io_rsp_queueWithOccupancy ( - .io_push_valid (ctrl_io_rsp_toStream_valid ), //i - .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o - .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i - .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o - .io_flush (1'b0 ), //i - .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o - .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_ctrl_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); - assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; - assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; - assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; - assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; - assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; - assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; - assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); - assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); - assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_ctrl_cmd_valid; - assign io_ctrl_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - 12'h004 : begin - factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; - factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; - end - 12'h00c : begin - factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; - factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; - factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; - factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; - factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; - end - 12'h058 : begin - factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; - end - default : begin - end - endcase - end - - assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; - always @(*) begin - mapping_cmdLogic_doRegular = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doRegular = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h050 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - mapping_cmdLogic_doReadWriteLarge = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h054 : begin - if(factory_doWrite) begin - mapping_cmdLogic_doReadWriteLarge = 1'b1; - end - end - default : begin - end - endcase - end - - assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); - assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); - assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; - assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); - always @(*) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; - if(when_Stream_l368_1) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; - assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; - assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; - assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; - assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; - always @(*) begin - _zz_io_pop_ready = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h0 : begin - if(factory_doRead) begin - _zz_io_pop_ready = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - _zz_io_pop_ready_1 = 1'b0; - case(io_ctrl_cmd_payload_fragment_address) - 12'h058 : begin - if(factory_doRead) begin - _zz_io_pop_ready_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); - assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); - assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); - assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); - assign io_spi_sclk_write = ctrl_io_spi_sclk_write; - assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; - assign io_spi_data_0_write = ctrl_io_spi_data_0_write; - assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; - assign io_spi_data_1_write = ctrl_io_spi_data_1_write; - assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; - assign io_spi_data_2_write = ctrl_io_spi_data_2_write; - assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; - assign io_spi_data_3_write = ctrl_io_spi_data_3_write; - assign io_spi_ss = ctrl_io_spi_ss; - assign io_interrupt = mapping_interruptCtrl_interrupt; - assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; - assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_ctrl_rsp_valid_2 <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; - mapping_interruptCtrl_cmdIntEnable <= 1'b0; - mapping_interruptCtrl_rspIntEnable <= 1'b0; - _zz_io_config_ss_activeHigh <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h00c : begin - if(factory_doWrite) begin - mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; - mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; - end - end - 12'h030 : begin - if(factory_doWrite) begin - _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; - end - if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; - mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; - end - case(io_ctrl_cmd_payload_fragment_address) - 12'h008 : begin - if(factory_doWrite) begin - _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; - _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; - _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; - end - end - 12'h020 : begin - if(factory_doWrite) begin - _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h024 : begin - if(factory_doWrite) begin - _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h028 : begin - if(factory_doWrite) begin - _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - 12'h02c : begin - if(factory_doWrite) begin - _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; - end - end - default : begin - end - endcase - end - - -endmodule - -module BmbUartCtrl ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [5:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output io_uart_txd, - input io_uart_rxd, - output io_interrupt, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; - wire uartCtrl_1_io_write_ready; - wire uartCtrl_1_io_read_valid; - wire [7:0] uartCtrl_1_io_read_payload; - wire uartCtrl_1_io_uart_txd; - wire uartCtrl_1_io_readError; - wire uartCtrl_1_io_readBreak; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; - wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; - wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; - wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; - wire [0:0] _zz_bridge_misc_readError; - wire [0:0] _zz_bridge_misc_readOverflowError; - wire [0:0] _zz_bridge_misc_breakDetected; - wire [0:0] _zz_bridge_misc_doBreak; - wire [0:0] _zz_bridge_misc_doBreak_1; - wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider; - wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; - wire busCtrl_readHaltTrigger; - wire busCtrl_writeHaltTrigger; - wire busCtrl_rsp_valid; - wire busCtrl_rsp_ready; - wire busCtrl_rsp_payload_last; - wire [0:0] busCtrl_rsp_payload_fragment_opcode; - reg [31:0] busCtrl_rsp_payload_fragment_data; - wire [3:0] busCtrl_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_busCtrl_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire busCtrl_askWrite; - wire busCtrl_askRead; - wire io_bus_cmd_fire; - wire busCtrl_doWrite; - wire io_bus_cmd_fire_1; - wire busCtrl_doRead; - reg [2:0] bridge_uartConfigReg_frame_dataLength; - reg [0:0] bridge_uartConfigReg_frame_stop; - reg [1:0] bridge_uartConfigReg_frame_parity; - reg [19:0] bridge_uartConfigReg_clockDivider; - reg _zz_bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_valid; - wire bridge_write_streamUnbuffered_ready; - wire [7:0] bridge_write_streamUnbuffered_payload; - reg bridge_read_streamBreaked_valid; - reg bridge_read_streamBreaked_ready; - wire [7:0] bridge_read_streamBreaked_payload; - reg bridge_interruptCtrl_writeIntEnable; - reg bridge_interruptCtrl_readIntEnable; - wire bridge_interruptCtrl_readInt; - wire bridge_interruptCtrl_writeInt; - wire bridge_interruptCtrl_interrupt; - reg bridge_misc_readError; - reg when_BusSlaveFactory_l335; - wire when_BusSlaveFactory_l341; - reg bridge_misc_readOverflowError; - reg when_BusSlaveFactory_l335_1; - wire when_BusSlaveFactory_l341_1; - wire uartCtrl_1_io_read_isStall; - reg bridge_misc_breakDetected; - reg uartCtrl_1_io_readBreak_regNext; - wire when_UartCtrl_l155; - reg when_BusSlaveFactory_l335_2; - wire when_BusSlaveFactory_l341_2; - reg bridge_misc_doBreak; - reg when_BusSlaveFactory_l371; - wire when_BusSlaveFactory_l373; - reg when_BusSlaveFactory_l335_3; - wire when_BusSlaveFactory_l341_3; - wire [1:0] _zz_bridge_uartConfigReg_frame_parity; - wire [0:0] _zz_bridge_uartConfigReg_frame_stop; - wire when_BmbSlaveFactory_l71; - `ifndef SYNTHESIS - reg [23:0] bridge_uartConfigReg_frame_stop_string; - reg [31:0] bridge_uartConfigReg_frame_parity_string; - reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; - reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; - `endif - - - assign _zz_bridge_misc_readError = 1'b0; - assign _zz_bridge_misc_readOverflowError = 1'b0; - assign _zz_bridge_misc_breakDetected = 1'b0; - assign _zz_bridge_misc_doBreak = 1'b1; - assign _zz_bridge_misc_doBreak_1 = 1'b0; - assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); - assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; - assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; - UartCtrl uartCtrl_1 ( - .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i - .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i - .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i - .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i - .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i - .io_write_ready (uartCtrl_1_io_write_ready ), //o - .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i - .io_read_valid (uartCtrl_1_io_read_valid ), //o - .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i - .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o - .io_uart_txd (uartCtrl_1_io_uart_txd ), //o - .io_uart_rxd (io_uart_rxd ), //i - .io_readError (uartCtrl_1_io_readError ), //o - .io_writeBreak (bridge_misc_doBreak ), //i - .io_readBreak (uartCtrl_1_io_readBreak ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( - .io_push_valid (bridge_write_streamUnbuffered_valid ), //i - .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i - .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_write_ready ), //i - .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - StreamFifo uartCtrl_1_io_read_queueWithOccupancy ( - .io_push_valid (uartCtrl_1_io_read_valid ), //i - .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o - .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i - .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o - .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i - .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o - .io_flush (1'b0 ), //i - .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o - .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(bridge_uartConfigReg_frame_stop) - UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; - default : bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(bridge_uartConfigReg_frame_parity) - UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; - default : bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_parity) - UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; - UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; - UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; - default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; - endcase - end - always @(*) begin - case(_zz_bridge_uartConfigReg_frame_stop) - UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; - UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; - default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; - endcase - end - `endif - - assign io_uart_txd = uartCtrl_1_io_uart_txd; - assign busCtrl_readHaltTrigger = 1'b0; - assign busCtrl_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); - assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_busCtrl_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_busCtrl_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign busCtrl_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = busCtrl_rsp_ready; - assign busCtrl_rsp_payload_last = 1'b1; - assign busCtrl_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - busCtrl_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); - busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; - end - 6'h04 : begin - busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; - busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; - busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; - busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; - end - 6'h10 : begin - busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; - busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; - busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; - busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; - end - default : begin - end - endcase - end - - assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - always @(*) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doWrite) begin - _zz_bridge_write_streamUnbuffered_valid = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; - assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; - assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; - always @(*) begin - bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; - if(uartCtrl_1_io_readBreak) begin - bridge_read_streamBreaked_valid = 1'b0; - end - end - - always @(*) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; - if(uartCtrl_1_io_readBreak) begin - uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; - end - end - - assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; - always @(*) begin - bridge_read_streamBreaked_ready = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h0 : begin - if(busCtrl_doRead) begin - bridge_read_streamBreaked_ready = 1'b1; - end - end - default : begin - end - endcase - end - - assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); - assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); - assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); - always @(*) begin - when_BusSlaveFactory_l335 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; - always @(*) begin - when_BusSlaveFactory_l335_1 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_1 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; - assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); - assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); - always @(*) begin - when_BusSlaveFactory_l335_2 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_2 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; - always @(*) begin - when_BusSlaveFactory_l371 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l371 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; - always @(*) begin - when_BusSlaveFactory_l335_3 = 1'b0; - case(io_bus_cmd_payload_fragment_address) - 6'h10 : begin - if(busCtrl_doWrite) begin - when_BusSlaveFactory_l335_3 = 1'b1; - end - end - default : begin - end - endcase - end - - assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; - assign io_interrupt = bridge_interruptCtrl_interrupt; - assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; - assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - bridge_uartConfigReg_clockDivider <= 20'h0; - bridge_uartConfigReg_clockDivider <= 20'h00035; - bridge_uartConfigReg_frame_dataLength <= 3'b111; - bridge_uartConfigReg_frame_parity <= UartParityType_NONE; - bridge_uartConfigReg_frame_stop <= UartStopType_ONE; - bridge_interruptCtrl_writeIntEnable <= 1'b0; - bridge_interruptCtrl_readIntEnable <= 1'b0; - bridge_misc_readError <= 1'b0; - bridge_misc_readOverflowError <= 1'b0; - bridge_misc_breakDetected <= 1'b0; - bridge_misc_doBreak <= 1'b0; - end else begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); - end - if(when_BusSlaveFactory_l335) begin - if(when_BusSlaveFactory_l341) begin - bridge_misc_readError <= _zz_bridge_misc_readError[0]; - end - end - if(uartCtrl_1_io_readError) begin - bridge_misc_readError <= 1'b1; - end - if(when_BusSlaveFactory_l335_1) begin - if(when_BusSlaveFactory_l341_1) begin - bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; - end - end - if(uartCtrl_1_io_read_isStall) begin - bridge_misc_readOverflowError <= 1'b1; - end - if(when_UartCtrl_l155) begin - bridge_misc_breakDetected <= 1'b1; - end - if(when_BusSlaveFactory_l335_2) begin - if(when_BusSlaveFactory_l341_2) begin - bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; - end - end - if(when_BusSlaveFactory_l371) begin - if(when_BusSlaveFactory_l373) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; - end - end - if(when_BusSlaveFactory_l335_3) begin - if(when_BusSlaveFactory_l341_3) begin - bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; - end - end - case(io_bus_cmd_payload_fragment_address) - 6'h0c : begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; - bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; - bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; - end - end - 6'h04 : begin - if(busCtrl_doWrite) begin - bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; - bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; - end - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - if(busCtrl_doWrite) begin - bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; - end - end - end - end - - always @(posedge io_systemClk) begin - if(_zz_busCtrl_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; - end - uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; - end - - -endmodule - -module BmbClint ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [15:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - output [0:0] io_timerInterrupt, - output [0:0] io_softwareInterrupt, - output [63:0] io_time, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [31:0] _zz_logic_harts_0_cmp; - wire [31:0] _zz_logic_harts_0_cmp_1; - wire [31:0] _zz_logic_harts_0_cmp_2; - wire [31:0] _zz_logic_harts_0_cmp_3; - wire factory_readHaltTrigger; - wire factory_writeHaltTrigger; - wire factory_rsp_valid; - wire factory_rsp_ready; - wire factory_rsp_payload_last; - wire [0:0] factory_rsp_payload_fragment_opcode; - reg [31:0] factory_rsp_payload_fragment_data; - wire [3:0] factory_rsp_payload_fragment_context; - wire _zz_io_bus_rsp_valid; - reg _zz_factory_rsp_ready; - wire _zz_io_bus_rsp_valid_1; - reg _zz_io_bus_rsp_valid_2; - reg _zz_io_bus_rsp_payload_last; - reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_bus_rsp_payload_fragment_data; - reg [3:0] _zz_io_bus_rsp_payload_fragment_context; - wire when_Stream_l368; - wire factory_askWrite; - wire factory_askRead; - wire io_bus_cmd_fire; - wire factory_doWrite; - wire io_bus_cmd_fire_1; - wire factory_doRead; - reg [63:0] logic_time; - reg [63:0] logic_harts_0_cmp; - reg logic_harts_0_timerInterrupt; - reg logic_harts_0_softwareInterrupt; - wire [63:0] _zz_factory_rsp_payload_fragment_data; - wire when_BmbSlaveFactory_l71; - wire when_BmbSlaveFactory_l71_1; - wire when_BmbSlaveFactory_l71_2; - wire when_BmbSlaveFactory_l71_3; - - assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; - assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; - assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; - assign factory_readHaltTrigger = 1'b0; - assign factory_writeHaltTrigger = 1'b0; - assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); - assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); - always @(*) begin - _zz_factory_rsp_ready = io_bus_rsp_ready; - if(when_Stream_l368) begin - _zz_factory_rsp_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); - assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; - assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; - assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; - assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; - assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; - assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; - assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); - assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); - assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); - assign factory_rsp_valid = io_bus_cmd_valid; - assign io_bus_cmd_ready = factory_rsp_ready; - assign factory_rsp_payload_last = 1'b1; - assign factory_rsp_payload_fragment_opcode = 1'b0; - always @(*) begin - factory_rsp_payload_fragment_data = 32'h0; - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; - end - default : begin - end - endcase - if(when_BmbSlaveFactory_l71) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; - end - if(when_BmbSlaveFactory_l71_1) begin - factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; - end - end - - assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; - assign _zz_factory_rsp_payload_fragment_data = logic_time; - assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; - assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; - assign io_time = logic_time; - assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); - assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); - assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); - assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_bus_rsp_valid_2 <= 1'b0; - logic_time <= 64'h0; - logic_harts_0_softwareInterrupt <= 1'b0; - end else begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); - end - logic_time <= (logic_time + 64'h0000000000000001); - case(io_bus_cmd_payload_fragment_address) - 16'h0 : begin - if(factory_doWrite) begin - logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; - end - end - default : begin - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(_zz_factory_rsp_ready) begin - _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; - _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; - _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; - _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; - end - logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); - if(when_BmbSlaveFactory_l71_2) begin - if(factory_doWrite) begin - logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; - end - end - if(when_BmbSlaveFactory_l71_3) begin - if(factory_doWrite) begin - logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; - end - end - end - - -endmodule - -module BmbDecoder_3 ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [23:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [3:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [3:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [23:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [3:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [3:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [23:0] io_outputs_1_cmd_payload_fragment_address, - output [1:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [3:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [3:0] io_outputs_1_rsp_payload_fragment_context, - output reg io_outputs_2_cmd_valid, - input io_outputs_2_cmd_ready, - output io_outputs_2_cmd_payload_last, - output [0:0] io_outputs_2_cmd_payload_fragment_opcode, - output [23:0] io_outputs_2_cmd_payload_fragment_address, - output [1:0] io_outputs_2_cmd_payload_fragment_length, - output [31:0] io_outputs_2_cmd_payload_fragment_data, - output [3:0] io_outputs_2_cmd_payload_fragment_mask, - output [3:0] io_outputs_2_cmd_payload_fragment_context, - input io_outputs_2_rsp_valid, - output io_outputs_2_rsp_ready, - input io_outputs_2_rsp_payload_last, - input [0:0] io_outputs_2_rsp_payload_fragment_opcode, - input [31:0] io_outputs_2_rsp_payload_fragment_data, - input [3:0] io_outputs_2_rsp_payload_fragment_context, - output reg io_outputs_3_cmd_valid, - input io_outputs_3_cmd_ready, - output io_outputs_3_cmd_payload_last, - output [0:0] io_outputs_3_cmd_payload_fragment_opcode, - output [23:0] io_outputs_3_cmd_payload_fragment_address, - output [1:0] io_outputs_3_cmd_payload_fragment_length, - output [31:0] io_outputs_3_cmd_payload_fragment_data, - output [3:0] io_outputs_3_cmd_payload_fragment_mask, - output [3:0] io_outputs_3_cmd_payload_fragment_context, - input io_outputs_3_rsp_valid, - output io_outputs_3_rsp_ready, - input io_outputs_3_rsp_payload_last, - input [0:0] io_outputs_3_rsp_payload_fragment_opcode, - input [31:0] io_outputs_3_rsp_payload_fragment_data, - input [3:0] io_outputs_3_rsp_payload_fragment_context, - output reg io_outputs_4_cmd_valid, - input io_outputs_4_cmd_ready, - output io_outputs_4_cmd_payload_last, - output [0:0] io_outputs_4_cmd_payload_fragment_opcode, - output [23:0] io_outputs_4_cmd_payload_fragment_address, - output [1:0] io_outputs_4_cmd_payload_fragment_length, - output [31:0] io_outputs_4_cmd_payload_fragment_data, - output [3:0] io_outputs_4_cmd_payload_fragment_mask, - output [3:0] io_outputs_4_cmd_payload_fragment_context, - input io_outputs_4_rsp_valid, - output io_outputs_4_rsp_ready, - input io_outputs_4_rsp_payload_last, - input [0:0] io_outputs_4_rsp_payload_fragment_opcode, - input [31:0] io_outputs_4_rsp_payload_fragment_data, - input [3:0] io_outputs_4_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_logic_rspPendingCounter; - wire [3:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [3:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_3; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [3:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [23:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [3:0] logic_input_payload_fragment_context; - reg io_input_cmd_rValid; - wire logic_input_fire; - reg io_input_cmd_rData_last; - reg [0:0] io_input_cmd_rData_fragment_opcode; - reg [23:0] io_input_cmd_rData_fragment_address; - reg [1:0] io_input_cmd_rData_fragment_length; - reg [31:0] io_input_cmd_rData_fragment_data; - reg [3:0] io_input_cmd_rData_fragment_mask; - reg [3:0] io_input_cmd_rData_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_hitsS0_2; - wire logic_hitsS0_3; - wire logic_hitsS0_4; - wire logic_noHitS0; - wire io_input_cmd_fire; - reg logic_hitsS1_0; - reg logic_hitsS1_1; - reg logic_hitsS1_2; - reg logic_hitsS1_3; - reg logic_hitsS1_4; - wire io_input_cmd_fire_1; - reg logic_noHitS1; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - wire _zz_io_outputs_2_cmd_payload_last; - wire _zz_io_outputs_3_cmd_payload_last; - wire _zz_io_outputs_4_cmd_payload_last; - reg [3:0] logic_rspPendingCounter; - wire logic_input_fire_1; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - reg logic_rspHits_2; - reg logic_rspHits_3; - reg logic_rspHits_4; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_2; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_3; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_4; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_context; - wire logic_input_fire_6; - wire _zz_io_input_rsp_payload_last; - wire _zz_io_input_rsp_payload_last_1; - wire [2:0] _zz_io_input_rsp_payload_last_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last_2) - 3'b000 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - 3'b001 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - 3'b010 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; - end - 3'b011 : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_cmd_ready = (! io_input_cmd_rValid); - assign logic_input_valid = io_input_cmd_rValid; - assign logic_input_payload_last = io_input_cmd_rData_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); - assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); - assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); - always @(*) begin - io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); - if(logic_cmdWait) begin - io_outputs_2_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; - assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; - assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); - always @(*) begin - io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); - if(logic_cmdWait) begin - io_outputs_3_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; - assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; - assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); - always @(*) begin - io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); - if(logic_cmdWait) begin - io_outputs_4_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; - assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; - assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); - assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); - assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign io_outputs_2_rsp_ready = io_input_rsp_ready; - assign io_outputs_3_rsp_ready = io_input_rsp_ready; - assign io_outputs_4_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_input_cmd_rValid <= 1'b0; - logic_rspPendingCounter <= 4'b0000; - logic_rspNoHit_doIt <= 1'b0; - end else begin - if(io_input_cmd_valid) begin - io_input_cmd_rValid <= 1'b1; - end - if(logic_input_fire) begin - io_input_cmd_rValid <= 1'b0; - end - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(io_input_cmd_ready) begin - io_input_cmd_rData_last <= io_input_cmd_payload_last; - io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; - io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; - io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; - io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; - io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; - io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; - end - if(io_input_cmd_fire) begin - logic_hitsS1_0 <= logic_hitsS0_0; - logic_hitsS1_1 <= logic_hitsS0_1; - logic_hitsS1_2 <= logic_hitsS0_2; - logic_hitsS1_3 <= logic_hitsS0_3; - logic_hitsS1_4 <= logic_hitsS0_4; - end - if(io_input_cmd_fire_1) begin - logic_noHitS1 <= logic_noHitS0; - end - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS1_0; - logic_rspHits_1 <= logic_hitsS1_1; - logic_rspHits_2 <= logic_hitsS1_2; - logic_rspHits_3 <= logic_hitsS1_3; - logic_rspHits_4 <= logic_hitsS1_4; - end - if(logic_input_fire_3) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_5) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - end - - -endmodule - -//BmbUnburstify replaced by BmbUnburstify - -module BmbUnburstify ( - input io_input_cmd_valid, - output reg io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_source, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output reg io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output reg [0:0] io_output_cmd_payload_fragment_opcode, - output reg [31:0] io_output_cmd_payload_fragment_address, - output reg [1:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [3:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output reg io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [3:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz_buffer_last; - wire [0:0] _zz_buffer_last_1; - wire [11:0] _zz_buffer_addressIncr; - wire [11:0] _zz_buffer_addressIncr_1; - wire [11:0] _zz_buffer_addressIncr_2; - wire doResult; - reg buffer_valid; - reg [0:0] buffer_opcode; - reg [0:0] buffer_source; - reg [31:0] buffer_address; - reg [0:0] buffer_context; - reg [3:0] buffer_beat; - wire buffer_last; - wire [31:0] buffer_addressIncr; - wire buffer_isWrite; - wire io_output_cmd_fire; - wire [3:0] cmdTransferBeatCount; - wire requireBuffer; - reg cmdContext_drop; - reg cmdContext_last; - reg [0:0] cmdContext_source; - reg [0:0] cmdContext_context; - wire io_output_cmd_fire_1; - wire rspContext_drop; - wire rspContext_last; - wire [0:0] rspContext_source; - wire [0:0] rspContext_context; - wire [3:0] _zz_rspContext_drop; - wire when_Stream_l434; - reg io_output_rsp_thrown_valid; - wire io_output_rsp_thrown_ready; - wire io_output_rsp_thrown_payload_last; - wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; - wire [31:0] io_output_rsp_thrown_payload_fragment_data; - wire [3:0] io_output_rsp_thrown_payload_fragment_context; - - assign _zz_buffer_last_1 = 1'b1; - assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; - assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); - assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; - assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; - assign buffer_last = (buffer_beat == _zz_buffer_last); - assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; - assign buffer_isWrite = (buffer_opcode == 1'b1); - assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); - assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; - assign requireBuffer = (cmdTransferBeatCount != 4'b0000); - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_last = 1'b1; - assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_address = buffer_addressIncr; - end else begin - io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - if(requireBuffer) begin - io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; - end - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_opcode = buffer_opcode; - end else begin - io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - if(requireBuffer) begin - io_output_cmd_payload_fragment_length = 2'b11; - end else begin - io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; - end - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_context = buffer_context; - end else begin - cmdContext_context = io_input_cmd_payload_fragment_context; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_source = buffer_source; - end else begin - cmdContext_source = io_input_cmd_payload_fragment_source; - end - end - - always @(*) begin - io_input_cmd_ready = 1'b0; - if(buffer_valid) begin - io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); - end else begin - io_input_cmd_ready = io_output_cmd_ready; - end - end - - always @(*) begin - if(buffer_valid) begin - io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); - end else begin - io_output_cmd_valid = io_input_cmd_valid; - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_last = buffer_last; - end else begin - cmdContext_last = (! requireBuffer); - end - end - - always @(*) begin - if(buffer_valid) begin - cmdContext_drop = buffer_isWrite; - end else begin - cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); - end - end - - assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); - assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; - assign rspContext_drop = _zz_rspContext_drop[0]; - assign rspContext_last = _zz_rspContext_drop[1]; - assign rspContext_source = _zz_rspContext_drop[2 : 2]; - assign rspContext_context = _zz_rspContext_drop[3 : 3]; - assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); - always @(*) begin - io_output_rsp_thrown_valid = io_output_rsp_valid; - if(when_Stream_l434) begin - io_output_rsp_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_output_rsp_ready = io_output_rsp_thrown_ready; - if(when_Stream_l434) begin - io_output_rsp_ready = 1'b1; - end - end - - assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; - assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_input_rsp_valid = io_output_rsp_thrown_valid; - assign io_output_rsp_thrown_ready = io_input_rsp_ready; - assign io_input_rsp_payload_last = rspContext_last; - assign io_input_rsp_payload_fragment_source = rspContext_source; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = rspContext_context; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffer_valid <= 1'b0; - end else begin - if(io_output_cmd_fire) begin - if(buffer_last) begin - buffer_valid <= 1'b0; - end - end - if(!buffer_valid) begin - buffer_valid <= (requireBuffer && io_output_cmd_fire_1); - end - end - end - - always @(posedge io_systemClk) begin - if(io_output_cmd_fire) begin - buffer_beat <= (buffer_beat - 4'b0001); - buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; - end - if(!buffer_valid) begin - buffer_opcode <= io_input_cmd_payload_fragment_opcode; - buffer_source <= io_input_cmd_payload_fragment_source; - buffer_address <= io_input_cmd_payload_fragment_address; - buffer_context <= io_input_cmd_payload_fragment_context; - buffer_beat <= cmdTransferBeatCount; - end - end - - -endmodule - -module BmbOnChipRam ( - input io_bus_cmd_valid, - output io_bus_cmd_ready, - input io_bus_cmd_payload_last, - input [0:0] io_bus_cmd_payload_fragment_opcode, - input [14:0] io_bus_cmd_payload_fragment_address, - input [1:0] io_bus_cmd_payload_fragment_length, - input [31:0] io_bus_cmd_payload_fragment_data, - input [3:0] io_bus_cmd_payload_fragment_mask, - input [3:0] io_bus_cmd_payload_fragment_context, - output io_bus_rsp_valid, - input io_bus_rsp_ready, - output io_bus_rsp_payload_last, - output [0:0] io_bus_rsp_payload_fragment_opcode, - output [31:0] io_bus_rsp_payload_fragment_data, - output [3:0] io_bus_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_ram_port0; - wire io_bus_rsp_isStall; - reg io_bus_cmd_valid_regNextWhen; - reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; - wire [12:0] _zz_io_bus_rsp_payload_fragment_data; - wire io_bus_cmd_fire; - wire _zz_io_bus_rsp_payload_fragment_data_1; - wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; - reg [7:0] ram_symbol0 [0:8191]; - reg [7:0] ram_symbol1 [0:8191]; - reg [7:0] ram_symbol2 [0:8191]; - reg [7:0] ram_symbol3 [0:8191]; - reg [7:0] _zz_ramsymbol_read; - reg [7:0] _zz_ramsymbol_read_1; - reg [7:0] _zz_ramsymbol_read_2; - reg [7:0] _zz_ramsymbol_read_3; - - initial begin - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); - $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); - end - always @(*) begin - _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; - end - always @(posedge io_systemClk) begin - if(io_bus_cmd_fire) begin - _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; - _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; - end - if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; - end - if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; - end - if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin - ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; - end - end - - assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); - assign io_bus_cmd_ready = (! io_bus_rsp_isStall); - assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; - assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; - assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); - assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); - assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); - assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; - assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; - assign io_bus_rsp_payload_fragment_opcode = 1'b0; - assign io_bus_rsp_payload_last = 1'b1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - io_bus_cmd_valid_regNextWhen <= 1'b0; - end else begin - if(io_bus_cmd_ready) begin - io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; - end - end - end - - always @(posedge io_systemClk) begin - if(io_bus_cmd_ready) begin - io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; - end - end - - -endmodule - -module BmbDecoder_2 ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_source, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_source, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg [0:0] io_input_rsp_payload_fragment_context, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_source, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - output [0:0] io_outputs_0_cmd_payload_fragment_context, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_source, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input [0:0] io_outputs_0_rsp_payload_fragment_context, - output reg io_outputs_1_cmd_valid, - input io_outputs_1_cmd_ready, - output io_outputs_1_cmd_payload_last, - output [0:0] io_outputs_1_cmd_payload_fragment_source, - output [0:0] io_outputs_1_cmd_payload_fragment_opcode, - output [31:0] io_outputs_1_cmd_payload_fragment_address, - output [5:0] io_outputs_1_cmd_payload_fragment_length, - output [31:0] io_outputs_1_cmd_payload_fragment_data, - output [3:0] io_outputs_1_cmd_payload_fragment_mask, - output [0:0] io_outputs_1_cmd_payload_fragment_context, - input io_outputs_1_rsp_valid, - output io_outputs_1_rsp_ready, - input io_outputs_1_rsp_payload_last, - input [0:0] io_outputs_1_rsp_payload_fragment_source, - input [0:0] io_outputs_1_rsp_payload_fragment_opcode, - input [31:0] io_outputs_1_rsp_payload_fragment_data, - input [0:0] io_outputs_1_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - reg _zz_io_input_rsp_payload_last_1; - reg [0:0] _zz_io_input_rsp_payload_fragment_source; - reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; - reg [31:0] _zz_io_input_rsp_payload_fragment_data; - reg [0:0] _zz_io_input_rsp_payload_fragment_context; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_source; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [5:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire [0:0] logic_input_payload_fragment_context; - wire logic_hitsS0_0; - wire logic_hitsS0_1; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - wire _zz_io_outputs_1_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - reg logic_rspHits_1; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - reg [0:0] logic_rspNoHit_source; - wire logic_input_fire_4; - reg [0:0] logic_rspNoHit_context; - wire logic_input_fire_5; - reg [3:0] logic_rspNoHit_counter; - wire [0:0] _zz_io_input_rsp_payload_last; - wire when_BmbDecoder_l81; - wire io_input_rsp_fire_2; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - always @(*) begin - case(_zz_io_input_rsp_payload_last) - 1'b0 : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; - end - default : begin - _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; - _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; - _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; - _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; - _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; - end - endcase - end - - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; - assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); - always @(*) begin - io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); - if(logic_cmdWait) begin - io_outputs_1_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; - assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; - assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; - assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; - always @(*) begin - logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - assign _zz_io_input_rsp_payload_last = logic_rspHits_1; - always @(*) begin - io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b0; - if(when_BmbDecoder_l81) begin - io_input_rsp_payload_last = 1'b1; - end - if(logic_rspNoHit_singleBeatRsp) begin - io_input_rsp_payload_last = 1'b1; - end - end - end - - always @(*) begin - io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_source = logic_rspNoHit_source; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; - always @(*) begin - io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_context = logic_rspNoHit_context; - end - end - - assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); - assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_1_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - logic_rspHits_1 <= logic_hitsS0_1; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - if(logic_input_fire_3) begin - logic_rspNoHit_source <= logic_input_payload_fragment_source; - end - if(logic_input_fire_4) begin - logic_rspNoHit_context <= logic_input_payload_fragment_context; - end - if(logic_input_fire_5) begin - logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; - end - if(logic_rspNoHit_doIt) begin - if(io_input_rsp_fire_2) begin - logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); - end - end - end - - -endmodule - -module BmbArbiter ( - input io_inputs_0_cmd_valid, - output io_inputs_0_cmd_ready, - input io_inputs_0_cmd_payload_last, - input [0:0] io_inputs_0_cmd_payload_fragment_opcode, - input [31:0] io_inputs_0_cmd_payload_fragment_address, - input [5:0] io_inputs_0_cmd_payload_fragment_length, - input [31:0] io_inputs_0_cmd_payload_fragment_data, - input [3:0] io_inputs_0_cmd_payload_fragment_mask, - input [0:0] io_inputs_0_cmd_payload_fragment_context, - output io_inputs_0_rsp_valid, - input io_inputs_0_rsp_ready, - output io_inputs_0_rsp_payload_last, - output [0:0] io_inputs_0_rsp_payload_fragment_opcode, - output [31:0] io_inputs_0_rsp_payload_fragment_data, - output [0:0] io_inputs_0_rsp_payload_fragment_context, - input io_inputs_1_cmd_valid, - output io_inputs_1_cmd_ready, - input io_inputs_1_cmd_payload_last, - input [0:0] io_inputs_1_cmd_payload_fragment_opcode, - input [31:0] io_inputs_1_cmd_payload_fragment_address, - input [5:0] io_inputs_1_cmd_payload_fragment_length, - input [31:0] io_inputs_1_cmd_payload_fragment_data, - input [3:0] io_inputs_1_cmd_payload_fragment_mask, - output io_inputs_1_rsp_valid, - input io_inputs_1_rsp_ready, - output io_inputs_1_rsp_payload_last, - output [0:0] io_inputs_1_rsp_payload_fragment_opcode, - output [31:0] io_inputs_1_rsp_payload_fragment_data, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_source, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_source, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire memory_arbiter_io_inputs_0_ready; - wire memory_arbiter_io_inputs_1_ready; - wire memory_arbiter_io_output_valid; - wire memory_arbiter_io_output_payload_last; - wire [0:0] memory_arbiter_io_output_payload_fragment_source; - wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; - wire [31:0] memory_arbiter_io_output_payload_fragment_address; - wire [5:0] memory_arbiter_io_output_payload_fragment_length; - wire [31:0] memory_arbiter_io_output_payload_fragment_data; - wire [3:0] memory_arbiter_io_output_payload_fragment_mask; - wire [0:0] memory_arbiter_io_output_payload_fragment_context; - wire [0:0] memory_arbiter_io_chosen; - wire [1:0] memory_arbiter_io_chosenOH; - wire [1:0] _zz_io_output_cmd_payload_fragment_source; - reg _zz_io_output_rsp_ready; - wire [0:0] memory_rspSel; - - assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; - StreamArbiter memory_arbiter ( - .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i - .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o - .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i - .io_inputs_0_payload_fragment_source (1'b0 ), //i - .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i - .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i - .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i - .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o - .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i - .io_inputs_1_payload_fragment_source (1'b0 ), //i - .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i - .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i - .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i - .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i - .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i - .io_inputs_1_payload_fragment_context (1'b0 ), //i - .io_output_valid (memory_arbiter_io_output_valid ), //o - .io_output_ready (io_output_cmd_ready ), //i - .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o - .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o - .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o - .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o - .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o - .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o - .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o - .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o - .io_chosen (memory_arbiter_io_chosen ), //o - .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(memory_rspSel) - 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; - default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; - endcase - end - - assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; - assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; - assign io_output_cmd_valid = memory_arbiter_io_output_valid; - assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; - assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; - assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; - assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; - assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); - assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); - assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; - assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_output_rsp_ready = _zz_io_output_rsp_ready; - -endmodule - -module BmbDecoder_1 ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [5:0] io_outputs_0_cmd_payload_fragment_length, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data -); - - - assign io_outputs_0_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_outputs_0_cmd_ready; - assign io_input_rsp_valid = io_outputs_0_rsp_valid; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - -endmodule - -module BmbExclusiveMonitor ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [5:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - input [0:0] io_input_cmd_payload_fragment_context, - output io_input_rsp_valid, - input io_input_rsp_ready, - output io_input_rsp_payload_last, - output [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output [0:0] io_input_rsp_payload_fragment_context, - output io_output_cmd_valid, - input io_output_cmd_ready, - output io_output_cmd_payload_last, - output [0:0] io_output_cmd_payload_fragment_opcode, - output [31:0] io_output_cmd_payload_fragment_address, - output [5:0] io_output_cmd_payload_fragment_length, - output [31:0] io_output_cmd_payload_fragment_data, - output [3:0] io_output_cmd_payload_fragment_mask, - output [0:0] io_output_cmd_payload_fragment_context, - input io_output_rsp_valid, - output io_output_rsp_ready, - input io_output_rsp_payload_last, - input [0:0] io_output_rsp_payload_fragment_opcode, - input [31:0] io_output_rsp_payload_fragment_data, - input [0:0] io_output_rsp_payload_fragment_context -); - - - assign io_output_cmd_valid = io_input_cmd_valid; - assign io_input_cmd_ready = io_output_cmd_ready; - assign io_input_rsp_valid = io_output_rsp_valid; - assign io_output_rsp_ready = io_input_rsp_ready; - assign io_output_cmd_payload_last = io_input_cmd_payload_last; - assign io_input_rsp_payload_last = io_output_rsp_payload_last; - assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; - assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; - assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; - assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; - -endmodule - -module BmbDecoder ( - input io_input_cmd_valid, - output io_input_cmd_ready, - input io_input_cmd_payload_last, - input [0:0] io_input_cmd_payload_fragment_opcode, - input [31:0] io_input_cmd_payload_fragment_address, - input [1:0] io_input_cmd_payload_fragment_length, - input [31:0] io_input_cmd_payload_fragment_data, - input [3:0] io_input_cmd_payload_fragment_mask, - output reg io_input_rsp_valid, - input io_input_rsp_ready, - output reg io_input_rsp_payload_last, - output reg [0:0] io_input_rsp_payload_fragment_opcode, - output [31:0] io_input_rsp_payload_fragment_data, - output reg io_outputs_0_cmd_valid, - input io_outputs_0_cmd_ready, - output io_outputs_0_cmd_payload_last, - output [0:0] io_outputs_0_cmd_payload_fragment_opcode, - output [31:0] io_outputs_0_cmd_payload_fragment_address, - output [1:0] io_outputs_0_cmd_payload_fragment_length, - output [31:0] io_outputs_0_cmd_payload_fragment_data, - output [3:0] io_outputs_0_cmd_payload_fragment_mask, - input io_outputs_0_rsp_valid, - output io_outputs_0_rsp_ready, - input io_outputs_0_rsp_payload_last, - input [0:0] io_outputs_0_rsp_payload_fragment_opcode, - input [31:0] io_outputs_0_rsp_payload_fragment_data, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire [6:0] _zz_logic_rspPendingCounter; - wire [6:0] _zz_logic_rspPendingCounter_1; - wire [0:0] _zz_logic_rspPendingCounter_2; - wire [6:0] _zz_logic_rspPendingCounter_3; - wire [0:0] _zz_logic_rspPendingCounter_4; - wire logic_input_valid; - reg logic_input_ready; - wire logic_input_payload_last; - wire [0:0] logic_input_payload_fragment_opcode; - wire [31:0] logic_input_payload_fragment_address; - wire [1:0] logic_input_payload_fragment_length; - wire [31:0] logic_input_payload_fragment_data; - wire [3:0] logic_input_payload_fragment_mask; - wire logic_hitsS0_0; - wire logic_noHitS0; - wire _zz_io_outputs_0_cmd_payload_last; - reg [6:0] logic_rspPendingCounter; - wire logic_input_fire; - wire io_input_rsp_fire; - wire logic_cmdWait; - wire when_BmbDecoder_l56; - reg logic_rspHits_0; - wire logic_rspPending; - wire logic_rspNoHitValid; - reg logic_rspNoHit_doIt; - wire io_input_rsp_fire_1; - wire when_BmbDecoder_l60; - wire logic_input_fire_1; - wire when_BmbDecoder_l60_1; - wire logic_input_fire_2; - reg logic_rspNoHit_singleBeatRsp; - wire logic_input_fire_3; - wire logic_input_fire_4; - wire logic_input_fire_5; - - assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); - assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); - assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; - assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); - assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; - assign logic_input_valid = io_input_cmd_valid; - assign io_input_cmd_ready = logic_input_ready; - assign logic_input_payload_last = io_input_cmd_payload_last; - assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; - assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; - assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; - assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; - assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; - assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); - assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); - always @(*) begin - io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); - if(logic_cmdWait) begin - io_outputs_0_cmd_valid = 1'b0; - end - end - - assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; - assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; - assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; - assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; - assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; - assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; - assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; - always @(*) begin - logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); - if(logic_cmdWait) begin - logic_input_ready = 1'b0; - end - end - - assign logic_input_fire = (logic_input_valid && logic_input_ready); - assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); - assign logic_rspPending = (logic_rspPendingCounter != 7'h0); - assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); - assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); - assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); - assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); - assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); - assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); - assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); - always @(*) begin - io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); - if(logic_rspNoHit_doIt) begin - io_input_rsp_valid = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_last = 1'b1; - end - end - - always @(*) begin - io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; - if(logic_rspNoHit_doIt) begin - io_input_rsp_payload_fragment_opcode = 1'b1; - end - end - - assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; - assign io_outputs_0_rsp_ready = io_input_rsp_ready; - assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - logic_rspPendingCounter <= 7'h0; - logic_rspNoHit_doIt <= 1'b0; - end else begin - logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); - if(when_BmbDecoder_l60) begin - logic_rspNoHit_doIt <= 1'b0; - end - if(when_BmbDecoder_l60_1) begin - logic_rspNoHit_doIt <= 1'b1; - end - end - end - - always @(posedge io_systemClk) begin - if(when_BmbDecoder_l56) begin - logic_rspHits_0 <= logic_hitsS0_0; - end - if(logic_input_fire_2) begin - logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); - end - end - - -endmodule - -module BufferCC_4 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input system_cores_0_debugReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin - if(system_cores_0_debugReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module SystemDebugger ( - input io_remote_cmd_valid, - output io_remote_cmd_ready, - input io_remote_cmd_payload_last, - input [0:0] io_remote_cmd_payload_fragment, - output io_remote_rsp_valid, - input io_remote_rsp_ready, - output io_remote_rsp_payload_error, - output [31:0] io_remote_rsp_payload_data, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output io_mem_cmd_payload_wr, - output [1:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload, - input io_systemClk, - input debugCd_logic_outputReset -); - - reg [66:0] dispatcher_dataShifter; - reg dispatcher_dataLoaded; - reg [7:0] dispatcher_headerShifter; - wire [7:0] dispatcher_header; - reg dispatcher_headerLoaded; - reg [2:0] dispatcher_counter; - wire when_Fragment_l346; - wire when_Fragment_l349; - wire [66:0] _zz_io_mem_cmd_payload_address; - wire io_mem_cmd_isStall; - wire when_Fragment_l372; - - assign dispatcher_header = dispatcher_headerShifter[7 : 0]; - assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); - assign when_Fragment_l349 = (dispatcher_counter == 3'b111); - assign io_remote_cmd_ready = (! dispatcher_dataLoaded); - assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; - assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; - assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; - assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; - assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; - assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); - assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); - assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); - assign io_remote_rsp_valid = io_mem_rsp_valid; - assign io_remote_rsp_payload_error = 1'b0; - assign io_remote_rsp_payload_data = io_mem_rsp_payload; - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - dispatcher_dataLoaded <= 1'b0; - dispatcher_headerLoaded <= 1'b0; - dispatcher_counter <= 3'b000; - end else begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_counter <= (dispatcher_counter + 3'b001); - if(when_Fragment_l349) begin - dispatcher_headerLoaded <= 1'b1; - end - end - if(io_remote_cmd_payload_last) begin - dispatcher_headerLoaded <= 1'b1; - dispatcher_dataLoaded <= 1'b1; - dispatcher_counter <= 3'b000; - end - end - if(when_Fragment_l372) begin - dispatcher_headerLoaded <= 1'b0; - dispatcher_dataLoaded <= 1'b0; - end - end - end - - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - if(when_Fragment_l346) begin - dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); - end else begin - dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); - end - end - end - - -endmodule - -module JtagBridgeNoTap ( - input io_ctrl_tdi, - input io_ctrl_enable, - input io_ctrl_capture, - input io_ctrl_shift, - input io_ctrl_update, - input io_ctrl_reset, - output io_ctrl_tdo, - output io_remote_cmd_valid, - input io_remote_cmd_ready, - output io_remote_cmd_payload_last, - output [0:0] io_remote_cmd_payload_fragment, - input io_remote_rsp_valid, - output io_remote_rsp_ready, - input io_remote_rsp_payload_error, - input [31:0] io_remote_rsp_payload_data, - input io_systemClk, - input debugCd_logic_outputReset, - input jtagCtrl_tck -); - - wire flowCCByToggle_1_io_output_valid; - wire flowCCByToggle_1_io_output_payload_last; - wire [0:0] flowCCByToggle_1_io_output_payload_fragment; - wire system_cmd_valid; - wire system_cmd_payload_last; - wire [0:0] system_cmd_payload_fragment; - wire system_cmd_toStream_valid; - wire system_cmd_toStream_ready; - wire system_cmd_toStream_payload_last; - wire [0:0] system_cmd_toStream_payload_fragment; - (* async_reg = "true" *) reg system_rsp_valid; - (* async_reg = "true" *) reg system_rsp_payload_error; - (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; - wire io_remote_rsp_fire; - wire jtag_wrapper_ctrl_tdi; - wire jtag_wrapper_ctrl_enable; - wire jtag_wrapper_ctrl_capture; - wire jtag_wrapper_ctrl_shift; - wire jtag_wrapper_ctrl_update; - wire jtag_wrapper_ctrl_reset; - reg jtag_wrapper_ctrl_tdo; - reg [1:0] jtag_wrapper_header; - wire [1:0] jtag_wrapper_headerNext; - reg [0:0] jtag_wrapper_counter; - reg jtag_wrapper_done; - reg jtag_wrapper_sendCapture; - reg jtag_wrapper_sendShift; - reg jtag_wrapper_sendUpdate; - wire when_JtagTapInstructions_l183; - wire when_JtagTapInstructions_l186; - wire jtag_writeArea_ctrl_tdi; - wire jtag_writeArea_ctrl_enable; - wire jtag_writeArea_ctrl_capture; - wire jtag_writeArea_ctrl_shift; - wire jtag_writeArea_ctrl_update; - wire jtag_writeArea_ctrl_reset; - wire jtag_writeArea_ctrl_tdo; - wire jtag_writeArea_source_valid; - wire jtag_writeArea_source_payload_last; - wire [0:0] jtag_writeArea_source_payload_fragment; - reg jtag_writeArea_valid; - reg jtag_writeArea_data; - wire when_JtagTapInstructions_l209; - wire jtag_readArea_ctrl_tdi; - wire jtag_readArea_ctrl_enable; - wire jtag_readArea_ctrl_capture; - wire jtag_readArea_ctrl_shift; - wire jtag_readArea_ctrl_update; - wire jtag_readArea_ctrl_reset; - wire jtag_readArea_ctrl_tdo; - reg [33:0] jtag_readArea_full_shifter; - wire when_JtagTapInstructions_l209_1; - - FlowCCByToggle flowCCByToggle_1 ( - .io_input_valid (jtag_writeArea_source_valid ), //i - .io_input_payload_last (jtag_writeArea_source_payload_last ), //i - .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i - .io_output_valid (flowCCByToggle_1_io_output_valid ), //o - .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o - .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o - .jtagCtrl_tck (jtagCtrl_tck ), //i - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - assign system_cmd_toStream_valid = system_cmd_valid; - assign system_cmd_toStream_payload_last = system_cmd_payload_last; - assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; - assign io_remote_cmd_valid = system_cmd_toStream_valid; - assign system_cmd_toStream_ready = io_remote_cmd_ready; - assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; - assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; - assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); - assign io_remote_rsp_ready = 1'b1; - assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); - always @(*) begin - jtag_wrapper_sendCapture = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_sendCapture = 1'b1; - end - end - end - end - end - - always @(*) begin - jtag_wrapper_sendShift = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_shift) begin - if(!when_JtagTapInstructions_l183) begin - jtag_wrapper_sendShift = 1'b1; - end - end - end - end - - always @(*) begin - jtag_wrapper_sendUpdate = 1'b0; - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_update) begin - jtag_wrapper_sendUpdate = 1'b1; - end - end - end - - assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); - assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); - always @(*) begin - jtag_wrapper_ctrl_tdo = 1'b0; - if(when_JtagTapInstructions_l209) begin - jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; - end - if(when_JtagTapInstructions_l209_1) begin - jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; - end - end - - assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; - assign jtag_wrapper_ctrl_enable = io_ctrl_enable; - assign jtag_wrapper_ctrl_capture = io_ctrl_capture; - assign jtag_wrapper_ctrl_shift = io_ctrl_shift; - assign jtag_wrapper_ctrl_update = io_ctrl_update; - assign jtag_wrapper_ctrl_reset = io_ctrl_reset; - assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; - assign jtag_writeArea_source_valid = jtag_writeArea_valid; - assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); - assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; - assign system_cmd_valid = flowCCByToggle_1_io_output_valid; - assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; - assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; - assign jtag_writeArea_ctrl_tdo = 1'b0; - assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); - assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_writeArea_ctrl_enable = 1'b1; - assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); - assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); - assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); - assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; - assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; - assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); - assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; - assign jtag_readArea_ctrl_enable = 1'b1; - assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); - assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); - assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); - assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; - always @(posedge io_systemClk) begin - if(io_remote_cmd_valid) begin - system_rsp_valid <= 1'b0; - end - if(io_remote_rsp_fire) begin - system_rsp_valid <= 1'b1; - system_rsp_payload_error <= io_remote_rsp_payload_error; - system_rsp_payload_data <= io_remote_rsp_payload_data; - end - end - - always @(posedge jtagCtrl_tck) begin - if(jtag_wrapper_ctrl_enable) begin - if(jtag_wrapper_ctrl_capture) begin - jtag_wrapper_done <= 1'b0; - jtag_wrapper_counter <= 1'b0; - end - if(jtag_wrapper_ctrl_shift) begin - if(when_JtagTapInstructions_l183) begin - jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); - jtag_wrapper_header <= jtag_wrapper_headerNext; - if(when_JtagTapInstructions_l186) begin - jtag_wrapper_done <= 1'b1; - end - end - end - end - jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); - jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; - if(jtag_readArea_ctrl_enable) begin - if(jtag_readArea_ctrl_capture) begin - jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; - end - if(jtag_readArea_ctrl_shift) begin - jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); - end - end - end - - -endmodule - -module VexRiscv ( - output dBus_cmd_valid, - input dBus_cmd_ready, - output dBus_cmd_payload_wr, - output dBus_cmd_payload_uncached, - output [31:0] dBus_cmd_payload_address, - output [31:0] dBus_cmd_payload_data, - output [3:0] dBus_cmd_payload_mask, - output [2:0] dBus_cmd_payload_size, - output dBus_cmd_payload_last, - input dBus_rsp_valid, - input dBus_rsp_payload_last, - input [31:0] dBus_rsp_payload_data, - input dBus_rsp_payload_error, - input timerInterrupt, - input externalInterrupt, - input softwareInterrupt, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBus_cmd_valid, - input iBus_cmd_ready, - output reg [31:0] iBus_cmd_payload_address, - output [2:0] iBus_cmd_payload_size, - input iBus_rsp_valid, - input [31:0] iBus_rsp_payload_data, - input iBus_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset, - input debugCd_logic_outputReset -); - localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; - localparam ShiftCtrlEnum_SLL_1 = 2'd1; - localparam ShiftCtrlEnum_SRL_1 = 2'd2; - localparam ShiftCtrlEnum_SRA_1 = 2'd3; - localparam BranchCtrlEnum_INC = 2'd0; - localparam BranchCtrlEnum_B = 2'd1; - localparam BranchCtrlEnum_JAL = 2'd2; - localparam BranchCtrlEnum_JALR = 2'd3; - localparam EnvCtrlEnum_NONE = 2'd0; - localparam EnvCtrlEnum_XRET = 2'd1; - localparam EnvCtrlEnum_ECALL = 2'd2; - localparam EnvCtrlEnum_EBREAK = 2'd3; - localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; - localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; - localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; - localparam AluCtrlEnum_ADD_SUB = 2'd0; - localparam AluCtrlEnum_SLT_SLTU = 2'd1; - localparam AluCtrlEnum_BITWISE = 2'd2; - localparam Src2CtrlEnum_RS = 2'd0; - localparam Src2CtrlEnum_IMI = 2'd1; - localparam Src2CtrlEnum_IMS = 2'd2; - localparam Src2CtrlEnum_PC = 2'd3; - localparam Src1CtrlEnum_RS = 2'd0; - localparam Src1CtrlEnum_IMU = 2'd1; - localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; - localparam Src1CtrlEnum_URS1 = 2'd3; - - wire IBusCachedPlugin_cache_io_flush; - wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; - wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; - wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; - wire IBusCachedPlugin_cache_io_cpu_decode_isValid; - wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; - wire IBusCachedPlugin_cache_io_cpu_decode_isUser; - reg IBusCachedPlugin_cache_io_cpu_fill_valid; - wire dataCache_1_io_cpu_execute_isValid; - wire [31:0] dataCache_1_io_cpu_execute_address; - wire dataCache_1_io_cpu_memory_isValid; - reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; - reg dataCache_1_io_cpu_writeBack_isValid; - wire dataCache_1_io_cpu_writeBack_isUser; - wire [31:0] dataCache_1_io_cpu_writeBack_storeData; - wire [31:0] dataCache_1_io_cpu_writeBack_address; - wire dataCache_1_io_cpu_writeBack_fence_SW; - wire dataCache_1_io_cpu_writeBack_fence_SR; - wire dataCache_1_io_cpu_writeBack_fence_SO; - wire dataCache_1_io_cpu_writeBack_fence_SI; - wire dataCache_1_io_cpu_writeBack_fence_PW; - wire dataCache_1_io_cpu_writeBack_fence_PR; - wire dataCache_1_io_cpu_writeBack_fence_PO; - wire dataCache_1_io_cpu_writeBack_fence_PI; - wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; - wire dataCache_1_io_cpu_flush_valid; - wire dataCache_1_io_cpu_flush_payload_singleLine; - wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; - wire dataCache_1_io_mem_cmd_ready; - reg [31:0] _zz_RegFilePlugin_regFile_port0; - reg [31:0] _zz_RegFilePlugin_regFile_port1; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1_io_cpu_execute_haltIt; - wire dataCache_1_io_cpu_execute_refilling; - wire dataCache_1_io_cpu_memory_isWrite; - wire dataCache_1_io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1_io_cpu_writeBack_data; - wire dataCache_1_io_cpu_writeBack_mmuException; - wire dataCache_1_io_cpu_writeBack_unalignedAccess; - wire dataCache_1_io_cpu_writeBack_accessError; - wire dataCache_1_io_cpu_writeBack_isWrite; - wire dataCache_1_io_cpu_writeBack_keepMemRspData; - wire dataCache_1_io_cpu_writeBack_exclusiveOk; - wire dataCache_1_io_cpu_flush_ready; - wire dataCache_1_io_cpu_redo; - wire dataCache_1_io_mem_cmd_valid; - wire dataCache_1_io_mem_cmd_payload_wr; - wire dataCache_1_io_mem_cmd_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_size; - wire dataCache_1_io_mem_cmd_payload_last; - wire [51:0] _zz_memory_MUL_LOW; - wire [51:0] _zz_memory_MUL_LOW_1; - wire [51:0] _zz_memory_MUL_LOW_2; - wire [51:0] _zz_memory_MUL_LOW_3; - wire [32:0] _zz_memory_MUL_LOW_4; - wire [51:0] _zz_memory_MUL_LOW_5; - wire [49:0] _zz_memory_MUL_LOW_6; - wire [51:0] _zz_memory_MUL_LOW_7; - wire [49:0] _zz_memory_MUL_LOW_8; - wire [31:0] _zz_execute_SHIFT_RIGHT; - wire [32:0] _zz_execute_SHIFT_RIGHT_1; - wire [32:0] _zz_execute_SHIFT_RIGHT_2; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; - wire _zz_decode_LEGAL_INSTRUCTION_3; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; - wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; - wire _zz_decode_LEGAL_INSTRUCTION_9; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; - wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; - wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; - wire _zz_decode_LEGAL_INSTRUCTION_15; - wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; - wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; - wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; - reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; - wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; - wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; - wire [25:0] _zz_io_cpu_flush_payload_lineId; - wire [25:0] _zz_io_cpu_flush_payload_lineId_1; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; - wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; - wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; - reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; - wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; - wire _zz__zz_decode_BRANCH_CTRL_2_5; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; - wire _zz__zz_decode_BRANCH_CTRL_2_9; - wire _zz__zz_decode_BRANCH_CTRL_2_10; - wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; - wire _zz__zz_decode_BRANCH_CTRL_2_13; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; - wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; - wire _zz__zz_decode_BRANCH_CTRL_2_26; - wire _zz__zz_decode_BRANCH_CTRL_2_27; - wire _zz__zz_decode_BRANCH_CTRL_2_28; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; - wire _zz__zz_decode_BRANCH_CTRL_2_32; - wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; - wire _zz__zz_decode_BRANCH_CTRL_2_36; - wire _zz__zz_decode_BRANCH_CTRL_2_37; - wire _zz__zz_decode_BRANCH_CTRL_2_38; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; - wire _zz__zz_decode_BRANCH_CTRL_2_40; - wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; - wire _zz__zz_decode_BRANCH_CTRL_2_47; - wire _zz__zz_decode_BRANCH_CTRL_2_48; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; - wire _zz__zz_decode_BRANCH_CTRL_2_54; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; - wire _zz__zz_decode_BRANCH_CTRL_2_57; - wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; - wire _zz__zz_decode_BRANCH_CTRL_2_66; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; - wire _zz__zz_decode_BRANCH_CTRL_2_68; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; - wire _zz__zz_decode_BRANCH_CTRL_2_70; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; - wire _zz__zz_decode_BRANCH_CTRL_2_75; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; - wire _zz__zz_decode_BRANCH_CTRL_2_86; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; - wire _zz__zz_decode_BRANCH_CTRL_2_92; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; - wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; - wire _zz__zz_decode_BRANCH_CTRL_2_99; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; - wire _zz__zz_decode_BRANCH_CTRL_2_101; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; - wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; - wire _zz__zz_decode_BRANCH_CTRL_2_111; - wire _zz__zz_decode_BRANCH_CTRL_2_112; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; - wire _zz__zz_decode_BRANCH_CTRL_2_125; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; - wire _zz__zz_decode_BRANCH_CTRL_2_140; - wire _zz__zz_decode_BRANCH_CTRL_2_141; - wire _zz__zz_decode_BRANCH_CTRL_2_142; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; - wire _zz_RegFilePlugin_regFile_port; - wire _zz_decode_RegFilePlugin_rs1Data; - wire _zz_RegFilePlugin_regFile_port_1; - wire _zz_decode_RegFilePlugin_rs2Data; - wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; - wire [2:0] _zz__zz_decode_SRC1_1; - wire [4:0] _zz__zz_decode_SRC1_1_1; - wire [11:0] _zz__zz_decode_SRC2_4; - wire [31:0] _zz_execute_SrcPlugin_addSub; - wire [31:0] _zz_execute_SrcPlugin_addSub_1; - wire [31:0] _zz_execute_SrcPlugin_addSub_2; - wire [31:0] _zz_execute_SrcPlugin_addSub_3; - wire [31:0] _zz_execute_SrcPlugin_addSub_4; - wire [31:0] _zz_execute_SrcPlugin_addSub_5; - wire [31:0] _zz_execute_SrcPlugin_addSub_6; - wire [65:0] _zz_writeBack_MulPlugin_result; - wire [65:0] _zz_writeBack_MulPlugin_result_1; - wire [31:0] _zz__zz_decode_RS2_2; - wire [31:0] _zz__zz_decode_RS2_2_1; - wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; - wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; - wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; - wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; - wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; - wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; - wire _zz_when; - wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; - wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; - wire [51:0] memory_MUL_LOW; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire [33:0] execute_MUL_HL; - wire [33:0] execute_MUL_LH; - wire [31:0] execute_MUL_LL; - wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; - wire [31:0] memory_MEMORY_STORE_DATA_RF; - wire [31:0] execute_MEMORY_STORE_DATA_RF; - wire decode_DO_EBREAK; - wire decode_CSR_READ_OPCODE; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] decode_SRC2; - wire [31:0] decode_SRC1; - wire decode_SRC2_FORCE_ZERO; - wire [1:0] decode_BRANCH_CTRL; - wire [1:0] _zz_decode_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; - wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; - wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; - wire [1:0] _zz_execute_to_memory_ENV_CTRL; - wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; - wire [1:0] decode_ENV_CTRL; - wire [1:0] _zz_decode_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL; - wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; - wire decode_IS_CSR; - wire decode_IS_RS2_SIGNED; - wire decode_IS_RS1_SIGNED; - wire decode_IS_DIV; - wire memory_IS_MUL; - wire decode_IS_MUL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; - wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; - wire [1:0] decode_SHIFT_CTRL; - wire [1:0] _zz_decode_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; - wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; - wire [1:0] decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_MANAGMENT; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [1:0] decode_ALU_CTRL; - wire [1:0] _zz_decode_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL; - wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; - wire decode_MEMORY_FORCE_CONSTISTENCY; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [31:0] memory_PC; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] execute_PC; - wire [1:0] execute_BRANCH_CTRL; - wire [1:0] _zz_execute_BRANCH_CTRL; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire [1:0] memory_ENV_CTRL; - wire [1:0] _zz_memory_ENV_CTRL; - wire [1:0] execute_ENV_CTRL; - wire [1:0] _zz_execute_ENV_CTRL; - wire [1:0] writeBack_ENV_CTRL; - wire [1:0] _zz_writeBack_ENV_CTRL; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire execute_IS_MUL; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_decode_RS2; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_decode_RS2_1; - wire [1:0] memory_SHIFT_CTRL; - wire [1:0] _zz_memory_SHIFT_CTRL; - wire [1:0] execute_SHIFT_CTRL; - wire [1:0] _zz_execute_SHIFT_CTRL; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_decode_SRC2; - wire [31:0] _zz_decode_SRC2_1; - wire [1:0] decode_SRC2_CTRL; - wire [1:0] _zz_decode_SRC2_CTRL; - wire [31:0] _zz_decode_SRC1; - wire [1:0] decode_SRC1_CTRL; - wire [1:0] _zz_decode_SRC1_CTRL; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire [1:0] execute_ALU_CTRL; - wire [1:0] _zz_execute_ALU_CTRL; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire [1:0] execute_ALU_BITWISE_CTRL; - wire [1:0] _zz_execute_ALU_BITWISE_CTRL; - wire [31:0] _zz_lastStageRegFileWrite_payload_address; - wire _zz_lastStageRegFileWrite_valid; - reg _zz_1; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire [1:0] _zz_decode_BRANCH_CTRL_1; - wire [1:0] _zz_decode_ENV_CTRL_1; - wire [1:0] _zz_decode_SHIFT_CTRL_1; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; - wire [1:0] _zz_decode_SRC2_CTRL_1; - wire [1:0] _zz_decode_ALU_CTRL_1; - wire [1:0] _zz_decode_SRC1_CTRL_1; - reg [31:0] _zz_decode_RS2_2; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_MEMORY_STORE_DATA_RF; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire memory_MEMORY_ENABLE; - wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; - wire execute_MEMORY_FORCE_CONSTISTENCY; - (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_MANAGMENT; - (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected_4; - reg IBusCachedPlugin_rsp_issueDetected_3; - reg IBusCachedPlugin_rsp_issueDetected_2; - reg IBusCachedPlugin_rsp_issueDetected_1; - reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; - wire [31:0] decode_PC; - wire [31:0] decode_INSTRUCTION; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - wire IBusCachedPlugin_forceNoDecodeCond; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_0_isValid; - wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_isPaging; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_0_isValid; - wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_isPaging; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_when_DBusCachedPlugin_l393; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire [31:0] CsrPlugin_csrMapping_readDataSignal; - wire [31:0] CsrPlugin_csrMapping_readDataInit; - wire [31:0] CsrPlugin_csrMapping_writeDataSignal; - wire CsrPlugin_csrMapping_allowCsrSignal; - wire CsrPlugin_csrMapping_hazardFree; - wire CsrPlugin_inWfi /* verilator public */ ; - reg CsrPlugin_thirdPartyWake; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg CsrPlugin_allowEbreakException; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg BranchPlugin_inDebugNoFetchFlag; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_externalFlush; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; - wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_correction; - reg IBusCachedPlugin_fetchPc_correctionReg; - wire IBusCachedPlugin_fetchPc_output_fire; - wire IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - wire when_Fetcher_l134; - wire IBusCachedPlugin_fetchPc_output_fire_1; - wire when_Fetcher_l134_1; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_fetchPc_redo_valid; - wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; - reg IBusCachedPlugin_fetchPc_flushed; - wire when_Fetcher_l161; - reg IBusCachedPlugin_iBusRsp_redoFetch; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_output_valid; - wire IBusCachedPlugin_iBusRsp_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; - wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; - wire when_Fetcher_l243; - wire IBusCachedPlugin_injector_decodeInput_valid; - wire IBusCachedPlugin_injector_decodeInput_ready; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; - wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_IBusCachedPlugin_injector_decodeInput_valid; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - wire when_Fetcher_l323; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - wire when_Fetcher_l332; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - wire when_Fetcher_l332_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - wire when_Fetcher_l332_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - wire when_Fetcher_l332_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire when_Fetcher_l332_4; - reg IBusCachedPlugin_injector_nextPcCalc_valids_5; - wire when_Fetcher_l332_5; - reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - wire IBusCachedPlugin_rsp_issueDetected; - reg IBusCachedPlugin_rsp_redoFetch; - wire when_IBusCachedPlugin_l239; - wire when_IBusCachedPlugin_l244; - wire when_IBusCachedPlugin_l250; - wire when_IBusCachedPlugin_l256; - wire when_IBusCachedPlugin_l267; - wire dataCache_1_io_mem_cmd_s2mPipe_valid; - reg dataCache_1_io_mem_cmd_s2mPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_rValid; - reg dataCache_1_io_mem_cmd_rData_wr; - reg dataCache_1_io_mem_cmd_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_rData_size; - reg dataCache_1_io_mem_cmd_rData_last; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; - wire when_Stream_l368; - reg dBus_rsp_regNext_valid; - reg dBus_rsp_regNext_payload_last; - reg [31:0] dBus_rsp_regNext_payload_data; - reg dBus_rsp_regNext_payload_error; - reg [31:0] DBusCachedPlugin_rspCounter; - wire when_DBusCachedPlugin_l308; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; - wire dataCache_1_io_cpu_flush_isStall; - wire when_DBusCachedPlugin_l350; - wire when_DBusCachedPlugin_l366; - wire when_DBusCachedPlugin_l393; - wire when_DBusCachedPlugin_l446; - wire when_DBusCachedPlugin_l466; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; - wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire [31:0] writeBack_DBusCachedPlugin_rspRf; - wire [1:0] switch_Misc_l210; - wire _zz_writeBack_DBusCachedPlugin_rspFormated; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; - wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; - reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire when_DBusCachedPlugin_l492; - wire [32:0] _zz_decode_BRANCH_CTRL_2; - wire _zz_decode_BRANCH_CTRL_3; - wire _zz_decode_BRANCH_CTRL_4; - wire _zz_decode_BRANCH_CTRL_5; - wire _zz_decode_BRANCH_CTRL_6; - wire _zz_decode_BRANCH_CTRL_7; - wire _zz_decode_BRANCH_CTRL_8; - wire [1:0] _zz_decode_SRC1_CTRL_2; - wire [1:0] _zz_decode_ALU_CTRL_2; - wire [1:0] _zz_decode_SRC2_CTRL_2; - wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; - wire [1:0] _zz_decode_SHIFT_CTRL_2; - wire [1:0] _zz_decode_ENV_CTRL_2; - wire [1:0] _zz_decode_BRANCH_CTRL_9; - wire when_RegFilePlugin_l63; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_2; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_execute_REGFILE_WRITE_DATA; - reg [31:0] _zz_decode_SRC1_1; - wire _zz_decode_SRC2_2; - reg [19:0] _zz_decode_SRC2_3; - wire _zz_decode_SRC2_4; - reg [19:0] _zz_decode_SRC2_5; - reg [31:0] _zz_decode_SRC2_6; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_decode_RS2_3; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire when_HazardSimplePlugin_l47; - wire when_HazardSimplePlugin_l48; - wire when_HazardSimplePlugin_l51; - wire when_HazardSimplePlugin_l45; - wire when_HazardSimplePlugin_l57; - wire when_HazardSimplePlugin_l58; - wire when_HazardSimplePlugin_l48_1; - wire when_HazardSimplePlugin_l51_1; - wire when_HazardSimplePlugin_l45_1; - wire when_HazardSimplePlugin_l57_1; - wire when_HazardSimplePlugin_l58_1; - wire when_HazardSimplePlugin_l48_2; - wire when_HazardSimplePlugin_l51_2; - wire when_HazardSimplePlugin_l45_2; - wire when_HazardSimplePlugin_l57_2; - wire when_HazardSimplePlugin_l58_2; - wire when_HazardSimplePlugin_l105; - wire when_HazardSimplePlugin_l108; - wire when_HazardSimplePlugin_l113; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - reg [0:0] execute_MulPlugin_delayLogic_counter; - wire when_MulPlugin_l65; - wire when_MulPlugin_l70; - wire [1:0] switch_MulPlugin_l87; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; - reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; - wire [65:0] writeBack_MulPlugin_result; - wire when_MulPlugin_l147; - wire [1:0] switch_MulPlugin_l148; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - wire when_MulDivIterativePlugin_l126; - wire when_MulDivIterativePlugin_l126_1; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l128; - wire when_MulDivIterativePlugin_l129; - wire when_MulDivIterativePlugin_l132; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire when_MulDivIterativePlugin_l151; - wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; - wire when_MulDivIterativePlugin_l162; - wire _zz_memory_MulDivIterativePlugin_rs2; - wire _zz_memory_MulDivIterativePlugin_rs1; - reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle; - reg [63:0] CsrPlugin_minstret; - wire _zz_when_CsrPlugin_l965; - wire _zz_when_CsrPlugin_l965_1; - wire _zz_when_CsrPlugin_l965_2; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; - wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; - wire when_CsrPlugin_l922; - wire when_CsrPlugin_l922_1; - wire when_CsrPlugin_l922_2; - wire when_CsrPlugin_l922_3; - wire when_CsrPlugin_l935; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire when_CsrPlugin_l959; - wire when_CsrPlugin_l965; - wire when_CsrPlugin_l965_1; - wire when_CsrPlugin_l965_2; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_pcValids_0; - reg CsrPlugin_pipelineLiberator_pcValids_1; - reg CsrPlugin_pipelineLiberator_pcValids_2; - wire CsrPlugin_pipelineLiberator_active; - wire when_CsrPlugin_l993; - wire when_CsrPlugin_l993_1; - wire when_CsrPlugin_l993_2; - wire when_CsrPlugin_l998; - reg CsrPlugin_pipelineLiberator_done; - wire when_CsrPlugin_l1004; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException /* verilator public */ ; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire when_CsrPlugin_l1032; - wire when_CsrPlugin_l1077; - wire [1:0] switch_CsrPlugin_l1081; - reg execute_CsrPlugin_wfiWake; - wire when_CsrPlugin_l1129; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - wire when_CsrPlugin_l1142; - wire when_CsrPlugin_l1149; - wire when_CsrPlugin_l1150; - wire when_CsrPlugin_l1157; - wire when_CsrPlugin_l1167; - reg execute_CsrPlugin_writeInstruction; - reg execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - wire switch_Misc_l210_1; - reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; - wire when_CsrPlugin_l1189; - wire when_CsrPlugin_l1193; - wire [11:0] execute_CsrPlugin_csrAddress; - wire execute_BranchPlugin_eq; - wire [2:0] switch_Misc_l210_2; - reg _zz_execute_BRANCH_DO; - reg _zz_execute_BRANCH_DO_1; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_execute_BranchPlugin_branch_src2; - reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; - wire _zz_execute_BranchPlugin_branch_src2_2; - reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; - wire _zz_execute_BranchPlugin_branch_src2_4; - reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; - reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - wire when_DebugPlugin_l225; - reg DebugPlugin_haltedByBreak; - reg DebugPlugin_debugUsed /* verilator public */ ; - reg DebugPlugin_disableEbreak; - wire DebugPlugin_allowEBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_when_DebugPlugin_l244; - wire when_DebugPlugin_l244; - wire [5:0] switch_DebugPlugin_l267; - wire when_DebugPlugin_l271; - wire when_DebugPlugin_l271_1; - wire when_DebugPlugin_l272; - wire when_DebugPlugin_l272_1; - wire when_DebugPlugin_l273; - wire when_DebugPlugin_l274; - wire when_DebugPlugin_l275; - wire when_DebugPlugin_l275_1; - wire when_DebugPlugin_l295; - wire when_DebugPlugin_l298; - wire when_DebugPlugin_l311; - reg DebugPlugin_resetIt_regNext; - wire when_DebugPlugin_l331; - wire when_Pipeline_l124; - reg [31:0] decode_to_execute_PC; - wire when_Pipeline_l124_1; - reg [31:0] execute_to_memory_PC; - wire when_Pipeline_l124_2; - reg [31:0] memory_to_writeBack_PC; - wire when_Pipeline_l124_3; - reg [31:0] decode_to_execute_INSTRUCTION; - wire when_Pipeline_l124_4; - reg [31:0] execute_to_memory_INSTRUCTION; - wire when_Pipeline_l124_5; - reg [31:0] memory_to_writeBack_INSTRUCTION; - wire when_Pipeline_l124_6; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - wire when_Pipeline_l124_7; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - wire when_Pipeline_l124_8; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - wire when_Pipeline_l124_9; - reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - wire when_Pipeline_l124_10; - reg decode_to_execute_SRC_USE_SUB_LESS; - wire when_Pipeline_l124_11; - reg decode_to_execute_MEMORY_ENABLE; - wire when_Pipeline_l124_12; - reg execute_to_memory_MEMORY_ENABLE; - wire when_Pipeline_l124_13; - reg memory_to_writeBack_MEMORY_ENABLE; - wire when_Pipeline_l124_14; - reg [1:0] decode_to_execute_ALU_CTRL; - wire when_Pipeline_l124_15; - reg decode_to_execute_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_16; - reg execute_to_memory_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_17; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - wire when_Pipeline_l124_18; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - wire when_Pipeline_l124_19; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_20; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - wire when_Pipeline_l124_21; - reg decode_to_execute_MEMORY_WR; - wire when_Pipeline_l124_22; - reg execute_to_memory_MEMORY_WR; - wire when_Pipeline_l124_23; - reg memory_to_writeBack_MEMORY_WR; - wire when_Pipeline_l124_24; - reg decode_to_execute_MEMORY_MANAGMENT; - wire when_Pipeline_l124_25; - reg decode_to_execute_SRC_LESS_UNSIGNED; - wire when_Pipeline_l124_26; - reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; - wire when_Pipeline_l124_27; - reg [1:0] decode_to_execute_SHIFT_CTRL; - wire when_Pipeline_l124_28; - reg [1:0] execute_to_memory_SHIFT_CTRL; - wire when_Pipeline_l124_29; - reg decode_to_execute_IS_MUL; - wire when_Pipeline_l124_30; - reg execute_to_memory_IS_MUL; - wire when_Pipeline_l124_31; - reg memory_to_writeBack_IS_MUL; - wire when_Pipeline_l124_32; - reg decode_to_execute_IS_DIV; - wire when_Pipeline_l124_33; - reg execute_to_memory_IS_DIV; - wire when_Pipeline_l124_34; - reg decode_to_execute_IS_RS1_SIGNED; - wire when_Pipeline_l124_35; - reg decode_to_execute_IS_RS2_SIGNED; - wire when_Pipeline_l124_36; - reg decode_to_execute_IS_CSR; - wire when_Pipeline_l124_37; - reg [1:0] decode_to_execute_ENV_CTRL; - wire when_Pipeline_l124_38; - reg [1:0] execute_to_memory_ENV_CTRL; - wire when_Pipeline_l124_39; - reg [1:0] memory_to_writeBack_ENV_CTRL; - wire when_Pipeline_l124_40; - reg [1:0] decode_to_execute_BRANCH_CTRL; - wire when_Pipeline_l124_41; - reg [31:0] decode_to_execute_RS1; - wire when_Pipeline_l124_42; - reg [31:0] decode_to_execute_RS2; - wire when_Pipeline_l124_43; - reg decode_to_execute_SRC2_FORCE_ZERO; - wire when_Pipeline_l124_44; - reg [31:0] decode_to_execute_SRC1; - wire when_Pipeline_l124_45; - reg [31:0] decode_to_execute_SRC2; - wire when_Pipeline_l124_46; - reg decode_to_execute_CSR_WRITE_OPCODE; - wire when_Pipeline_l124_47; - reg decode_to_execute_CSR_READ_OPCODE; - wire when_Pipeline_l124_48; - reg decode_to_execute_DO_EBREAK; - wire when_Pipeline_l124_49; - reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_50; - reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; - wire when_Pipeline_l124_51; - (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; - wire when_Pipeline_l124_52; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_53; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - wire when_Pipeline_l124_54; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - wire when_Pipeline_l124_55; - reg [31:0] execute_to_memory_MUL_LL; - wire when_Pipeline_l124_56; - reg [33:0] execute_to_memory_MUL_LH; - wire when_Pipeline_l124_57; - reg [33:0] execute_to_memory_MUL_HL; - wire when_Pipeline_l124_58; - reg [33:0] execute_to_memory_MUL_HH; - wire when_Pipeline_l124_59; - reg [33:0] memory_to_writeBack_MUL_HH; - wire when_Pipeline_l124_60; - reg execute_to_memory_BRANCH_DO; - wire when_Pipeline_l124_61; - reg [31:0] execute_to_memory_BRANCH_CALC; - wire when_Pipeline_l124_62; - reg [51:0] memory_to_writeBack_MUL_LOW; - wire when_Pipeline_l151; - wire when_Pipeline_l154; - wire when_Pipeline_l151_1; - wire when_Pipeline_l154_1; - wire when_Pipeline_l151_2; - wire when_Pipeline_l154_2; - reg [2:0] switch_Fetcher_l365; - wire when_Fetcher_l381; - wire when_Fetcher_l401; - wire when_CsrPlugin_l1277; - reg execute_CsrPlugin_csr_3860; - wire when_CsrPlugin_l1277_1; - reg execute_CsrPlugin_csr_769; - wire when_CsrPlugin_l1277_2; - reg execute_CsrPlugin_csr_768; - wire when_CsrPlugin_l1277_3; - reg execute_CsrPlugin_csr_836; - wire when_CsrPlugin_l1277_4; - reg execute_CsrPlugin_csr_772; - wire when_CsrPlugin_l1277_5; - reg execute_CsrPlugin_csr_773; - wire when_CsrPlugin_l1277_6; - reg execute_CsrPlugin_csr_833; - wire when_CsrPlugin_l1277_7; - reg execute_CsrPlugin_csr_832; - wire when_CsrPlugin_l1277_8; - reg execute_CsrPlugin_csr_834; - wire when_CsrPlugin_l1277_9; - reg execute_CsrPlugin_csr_835; - wire [1:0] switch_CsrPlugin_l723; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; - wire when_CsrPlugin_l1310; - wire when_CsrPlugin_l1315; - `ifndef SYNTHESIS - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; - reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; - reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; - reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; - reg [47:0] decode_ENV_CTRL_string; - reg [47:0] _zz_decode_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; - reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; - reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; - reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_decode_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; - reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_execute_BRANCH_CTRL_string; - reg [47:0] memory_ENV_CTRL_string; - reg [47:0] _zz_memory_ENV_CTRL_string; - reg [47:0] execute_ENV_CTRL_string; - reg [47:0] _zz_execute_ENV_CTRL_string; - reg [47:0] writeBack_ENV_CTRL_string; - reg [47:0] _zz_writeBack_ENV_CTRL_string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_memory_SHIFT_CTRL_string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_execute_SHIFT_CTRL_string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_decode_SRC2_CTRL_string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_decode_SRC1_CTRL_string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_execute_ALU_CTRL_string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; - reg [31:0] _zz_decode_BRANCH_CTRL_1_string; - reg [47:0] _zz_decode_ENV_CTRL_1_string; - reg [71:0] _zz_decode_SHIFT_CTRL_1_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; - reg [23:0] _zz_decode_SRC2_CTRL_1_string; - reg [63:0] _zz_decode_ALU_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_1_string; - reg [95:0] _zz_decode_SRC1_CTRL_2_string; - reg [63:0] _zz_decode_ALU_CTRL_2_string; - reg [23:0] _zz_decode_SRC2_CTRL_2_string; - reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; - reg [71:0] _zz_decode_SHIFT_CTRL_2_string; - reg [47:0] _zz_decode_ENV_CTRL_2_string; - reg [31:0] _zz_decode_BRANCH_CTRL_9_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [47:0] decode_to_execute_ENV_CTRL_string; - reg [47:0] execute_to_memory_ENV_CTRL_string; - reg [47:0] memory_to_writeBack_ENV_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - `endif - - reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - - assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); - assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); - assign _zz_memory_MUL_LOW_2 = 52'h0; - assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; - assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; - assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; - assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; - assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; - assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); - assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; - assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; - assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; - assign _zz__zz_decode_SRC1_1 = 3'b100; - assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; - assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); - assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); - assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; - assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); - assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; - assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; - assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; - assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; - assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; - assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); - assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; - assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; - assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; - assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; - assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); - assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); - assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; - assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; - assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; - assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; - assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; - assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; - assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; - assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; - assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; - assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; - assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); - assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); - assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); - assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; - assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; - assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); - assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); - assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; - assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); - assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; - assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); - assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); - assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; - assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); - assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); - assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; - assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; - assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); - assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; - assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; - assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); - assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); - assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; - assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); - assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; - assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); - assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); - assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); - assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); - assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); - assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; - assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); - assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); - assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; - assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); - assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); - assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; - assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); - assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; - assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; - assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; - assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; - assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); - assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); - assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; - assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; - assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); - assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; - assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); - assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); - assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); - assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); - assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); - assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; - assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; - assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); - assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); - assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); - assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); - assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; - assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; - assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; - assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; - assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); - assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; - assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); - assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; - assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); - assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; - assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); - assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; - assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); - assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); - assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; - assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; - assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; - assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); - assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; - assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); - assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; - assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); - assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; - assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; - assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); - assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); - assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; - assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); - assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; - assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); - assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; - assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; - assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); - assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); - assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; - assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); - assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; - assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); - assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs1Data) begin - _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_decode_RegFilePlugin_rs2Data) begin - _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush (IBusCachedPlugin_cache_io_flush ), //i - .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i - .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i - .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i - .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i - .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - DataCache dataCache_1 ( - .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i - .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i - .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i - .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i - .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i - .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i - .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i - .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i - .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i - .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i - .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i - .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i - .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i - .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - always @(*) begin - case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) - 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; - 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; - default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) - 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; - 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; - 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; - default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - always @(*) begin - case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) - 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; - default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; - endcase - end - - `ifndef SYNTHESIS - always @(*) begin - case(decode_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_to_writeBack_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; - default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; - default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; - default : decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_to_memory_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_to_execute_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; - default : _zz_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; - default : memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_memory_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; - default : _zz_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; - default : execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_execute_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; - default : _zz_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; - default : writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(_zz_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; - default : _zz_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; - default : _zz_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; - default : _zz_decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; - default : _zz_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_1) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_1_string = "????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_1) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_1_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_1) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_1) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_1) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; - default : _zz_decode_SRC2_CTRL_1_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_1) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_1_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_1) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_1_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC1_CTRL_2) - Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; - Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; - Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; - Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; - default : _zz_decode_SRC1_CTRL_2_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_CTRL_2) - AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; - default : _zz_decode_ALU_CTRL_2_string = "????????"; - endcase - end - always @(*) begin - case(_zz_decode_SRC2_CTRL_2) - Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; - Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; - Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; - Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; - default : _zz_decode_SRC2_CTRL_2_string = "???"; - endcase - end - always @(*) begin - case(_zz_decode_ALU_BITWISE_CTRL_2) - AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; - default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; - endcase - end - always @(*) begin - case(_zz_decode_SHIFT_CTRL_2) - ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; - default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_decode_ENV_CTRL_2) - EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; - EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; - EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; - EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; - default : _zz_decode_ENV_CTRL_2_string = "??????"; - endcase - end - always @(*) begin - case(_zz_decode_BRANCH_CTRL_9) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_9_string = "????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_to_memory_SHIFT_CTRL) - ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ENV_CTRL) - EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; - default : decode_to_execute_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; - default : execute_to_memory_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; - EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; - default : memory_to_writeBack_ENV_CTRL_string = "??????"; - endcase - end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; - BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - `endif - - assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; - assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; - assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; - assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; - assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; - assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; - assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; - assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; - assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); - assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); - assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); - assign decode_SRC2 = _zz_decode_SRC2_6; - assign decode_SRC1 = _zz_decode_SRC1_1; - assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; - assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; - assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; - assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; - assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; - assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; - assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; - assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; - assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; - assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; - assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; - assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; - assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; - assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; - assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; - assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign memory_PC = execute_to_memory_PC; - assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; - assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; - assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; - assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; - assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; - assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; - assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; - assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; - assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; - assign memory_MUL_HL = execute_to_memory_MUL_HL; - assign memory_MUL_LH = execute_to_memory_MUL_LH; - assign memory_MUL_LL = execute_to_memory_MUL_LL; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; - assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; - always @(*) begin - _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; - if(when_CsrPlugin_l1189) begin - _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; - end - end - - assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @(*) begin - decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr1Match) begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l51) begin - decode_RS2 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l51_1) begin - decode_RS2 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l51_2) begin - decode_RS2 = _zz_decode_RS2; - end - end - end - end - - always @(*) begin - decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid) begin - if(HazardSimplePlugin_addr0Match) begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; - end - end - if(when_HazardSimplePlugin_l45) begin - if(when_HazardSimplePlugin_l47) begin - if(when_HazardSimplePlugin_l48) begin - decode_RS1 = _zz_decode_RS2_2; - end - end - end - if(when_HazardSimplePlugin_l45_1) begin - if(memory_BYPASSABLE_MEMORY_STAGE) begin - if(when_HazardSimplePlugin_l48_1) begin - decode_RS1 = _zz_decode_RS2_1; - end - end - end - if(when_HazardSimplePlugin_l45_2) begin - if(execute_BYPASSABLE_EXECUTE_STAGE) begin - if(when_HazardSimplePlugin_l48_2) begin - decode_RS1 = _zz_decode_RS2; - end - end - end - end - - assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @(*) begin - _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid) begin - case(memory_SHIFT_CTRL) - ShiftCtrlEnum_SLL_1 : begin - _zz_decode_RS2_1 = _zz_decode_RS2_3; - end - ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin - _zz_decode_RS2_1 = memory_SHIFT_RIGHT; - end - default : begin - end - endcase - end - if(when_MulDivIterativePlugin_l128) begin - _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; - end - end - - assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; - assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; - assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; - assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; - assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_decode_SRC2 = decode_PC; - assign _zz_decode_SRC2_1 = decode_RS2; - assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; - assign _zz_decode_SRC1 = decode_RS1; - assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; - assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; - assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; - assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; - assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; - assign execute_SRC2 = decode_to_execute_SRC2; - assign execute_SRC1 = decode_to_execute_SRC1; - assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; - assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; - assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; - always @(*) begin - _zz_1 = 1'b0; - if(lastStageRegFileWrite_valid) begin - _zz_1 = 1'b1; - end - end - - assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); - always @(*) begin - decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; - if(when_RegFilePlugin_l63) begin - decode_REGFILE_WRITE_VALID = 1'b0; - end - end - - assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); - always @(*) begin - _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; - if(when_DBusCachedPlugin_l492) begin - _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; - end - if(when_MulPlugin_l147) begin - case(switch_MulPlugin_l148) - 2'b00 : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; - end - default : begin - _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; - end - endcase - end - end - - assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; - assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; - assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - assign execute_RS1 = decode_to_execute_RS1; - assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; - assign execute_RS2 = decode_to_execute_RS2; - assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = execute_SrcPlugin_addSub; - assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; - assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; - end - end - - always @(*) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid) begin - _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; - end - end - - assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; - assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @(*) begin - decode_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l308) begin - decode_arbitration_haltItself = 1'b1; - end - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_haltItself = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - decode_arbitration_haltByOther = 1'b0; - if(when_HazardSimplePlugin_l113) begin - decode_arbitration_haltByOther = 1'b1; - end - if(CsrPlugin_pipelineLiberator_active) begin - decode_arbitration_haltByOther = 1'b1; - end - if(when_CsrPlugin_l1129) begin - decode_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - decode_arbitration_removeIt = 1'b0; - if(_zz_when) begin - decode_arbitration_removeIt = 1'b1; - end - if(decode_arbitration_isFlushed) begin - decode_arbitration_removeIt = 1'b1; - end - end - - assign decode_arbitration_flushIt = 1'b0; - always @(*) begin - decode_arbitration_flushNext = 1'b0; - if(_zz_when) begin - decode_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - execute_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l350) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_MulPlugin_l65) begin - execute_arbitration_haltItself = 1'b1; - end - if(when_CsrPlugin_l1193) begin - if(execute_CsrPlugin_blockedBySideEffects) begin - execute_arbitration_haltItself = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_haltByOther = 1'b0; - if(when_DBusCachedPlugin_l366) begin - execute_arbitration_haltByOther = 1'b1; - end - if(when_DebugPlugin_l295) begin - execute_arbitration_haltByOther = 1'b1; - end - end - - always @(*) begin - execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_removeIt = 1'b1; - end - if(execute_arbitration_isFlushed) begin - execute_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - execute_arbitration_flushIt = 1'b0; - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushIt = 1'b1; - end - end - end - - always @(*) begin - execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid) begin - execute_arbitration_flushNext = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - execute_arbitration_flushNext = 1'b1; - end - end - end - - always @(*) begin - memory_arbitration_haltItself = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l129) begin - memory_arbitration_haltItself = 1'b1; - end - end - end - - assign memory_arbitration_haltByOther = 1'b0; - always @(*) begin - memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed) begin - memory_arbitration_removeIt = 1'b1; - end - end - - assign memory_arbitration_flushIt = 1'b0; - always @(*) begin - memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_branchExceptionPort_valid) begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid) begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_haltItself = 1'b0; - if(when_DBusCachedPlugin_l466) begin - writeBack_arbitration_haltItself = 1'b1; - end - end - - assign writeBack_arbitration_haltByOther = 1'b0; - always @(*) begin - writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_removeIt = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - writeBack_arbitration_removeIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushIt = 1'b1; - end - end - - always @(*) begin - writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1032) begin - writeBack_arbitration_flushNext = 1'b1; - end - if(when_CsrPlugin_l1077) begin - writeBack_arbitration_flushNext = 1'b1; - end - end - - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @(*) begin - IBusCachedPlugin_fetcherHalt = 1'b0; - if(when_CsrPlugin_l935) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1032) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_CsrPlugin_l1077) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - if(DebugPlugin_haltIt) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - if(when_DebugPlugin_l311) begin - IBusCachedPlugin_fetcherHalt = 1'b1; - end - end - - assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; - always @(*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if(when_Fetcher_l243) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - end - - always @(*) begin - _zz_when_DBusCachedPlugin_l393 = 1'b0; - if(DebugPlugin_godmode) begin - _zz_when_DBusCachedPlugin_l393 = 1'b1; - end - end - - assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; - assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; - assign CsrPlugin_inWfi = 1'b0; - always @(*) begin - CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt) begin - CsrPlugin_thirdPartyWake = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_valid = 1'b0; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - if(when_CsrPlugin_l1077) begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(when_CsrPlugin_l1032) begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; - end - default : begin - end - endcase - end - end - - always @(*) begin - CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode) begin - CsrPlugin_forceMachineWire = 1'b1; - end - end - - always @(*) begin - CsrPlugin_allowInterrupts = 1'b1; - if(when_DebugPlugin_l331) begin - CsrPlugin_allowInterrupts = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode) begin - CsrPlugin_allowException = 1'b0; - end - end - - always @(*) begin - CsrPlugin_allowEbreakException = 1'b1; - if(DebugPlugin_allowEBreak) begin - CsrPlugin_allowEbreakException = 1'b0; - end - end - - always @(*) begin - BranchPlugin_inDebugNoFetchFlag = 1'b0; - if(DebugPlugin_godmode) begin - BranchPlugin_inDebugNoFetchFlag = 1'b1; - end - end - - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; - assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); - assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; - assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; - always @(*) begin - IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_correction = 1'b1; - end - end - - assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @(*) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; - end - end - - assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); - assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); - assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); - always @(*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; - end - IBusCachedPlugin_fetchPc_pc[0] = 1'b0; - IBusCachedPlugin_fetchPc_pc[1] = 1'b0; - end - - always @(*) begin - IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - if(IBusCachedPlugin_jump_pcLoad_valid) begin - IBusCachedPlugin_fetchPc_flushed = 1'b1; - end - end - - assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); - assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); - assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @(*) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch) begin - IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; - end - end - - assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; - assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if(when_IBusCachedPlugin_l267) begin - IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; - end - end - - assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; - assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; - assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; - always @(*) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if(IBusCachedPlugin_injector_decodeInput_valid) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - if(when_Fetcher_l323) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; - end - end - - assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); - assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; - assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); - assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); - assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); - assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); - assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); - assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); - assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); - assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; - assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; - assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; - assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - always @(*) begin - decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - case(switch_Fetcher_l365) - 3'b010 : begin - decode_arbitration_isValid = 1'b1; - end - 3'b011 : begin - decode_arbitration_isValid = 1'b1; - end - default : begin - end - endcase - if(IBusCachedPlugin_forceNoDecodeCond) begin - decode_arbitration_isValid = 1'b0; - end - end - - assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @(*) begin - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - end - - assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; - assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; - assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); - assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; - assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @(*) begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(when_IBusCachedPlugin_l239) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(when_IBusCachedPlugin_l250) begin - IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - end - - always @(*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(when_IBusCachedPlugin_l244) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; - end - if(when_IBusCachedPlugin_l256) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; - assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); - assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; - assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; - assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); - always @(*) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; - if(when_Stream_l368) begin - dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; - end - end - - assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; - assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; - assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; - assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); - assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; - always @(*) begin - case(execute_DBusCachedPlugin_size) - 2'b00 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; - end - 2'b01 : begin - _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; - end - default : begin - _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; - end - endcase - end - - assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); - assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; - assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); - assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); - assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); - assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; - assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; - assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @(*) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if(when_DBusCachedPlugin_l393) begin - dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; - end - end - - assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); - always @(*) begin - dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - if(writeBack_arbitration_haltByOther) begin - dataCache_1_io_cpu_writeBack_isValid = 1'b0; - end - end - - assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); - assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; - assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; - always @(*) begin - DBusCachedPlugin_redoBranch_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_redoBranch_valid = 1'b1; - end - end - end - - assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @(*) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; - end - if(dataCache_1_io_cpu_redo) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - end - end - end - - assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @(*) begin - DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(when_DBusCachedPlugin_l446) begin - if(dataCache_1_io_cpu_writeBack_accessError) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; - end - if(dataCache_1_io_cpu_writeBack_mmuException) begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; - end - end - end - - assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); - assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; - assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; - assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; - assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; - always @(*) begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; - writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; - writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; - writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; - end - - assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; - assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; - _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; - end - - assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); - always @(*) begin - _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; - _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; - end - - always @(*) begin - case(switch_Misc_l210) - 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; - end - 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; - end - default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; - end - endcase - end - - assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); - assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); - assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; - assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; - assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; - assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; - assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; - assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; - assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; - assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; - assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; - assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; - assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; - assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; - assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; - assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; - assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; - assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = 4'b0010; - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; - assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); - assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; - assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; - assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; - always @(*) begin - lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - if(_zz_2) begin - lastStageRegFileWrite_valid = 1'b1; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - if(_zz_2) begin - lastStageRegFileWrite_payload_address = 5'h0; - end - end - - always @(*) begin - lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; - if(_zz_2) begin - lastStageRegFileWrite_payload_data = 32'h0; - end - end - - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - AluBitwiseCtrlEnum_AND_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); - end - AluBitwiseCtrlEnum_OR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); - end - default : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); - end - endcase - end - - always @(*) begin - case(execute_ALU_CTRL) - AluCtrlEnum_BITWISE : begin - _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; - end - AluCtrlEnum_SLT_SLTU : begin - _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; - end - default : begin - _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; - end - endcase - end - - always @(*) begin - case(decode_SRC1_CTRL) - Src1CtrlEnum_RS : begin - _zz_decode_SRC1_1 = _zz_decode_SRC1; - end - Src1CtrlEnum_PC_INCREMENT : begin - _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; - end - Src1CtrlEnum_IMU : begin - _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; - end - default : begin - _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; - end - endcase - end - - assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; - always @(*) begin - _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; - _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; - end - - assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; - always @(*) begin - _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; - _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; - end - - always @(*) begin - case(decode_SRC2_CTRL) - Src2CtrlEnum_RS : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2_1; - end - Src2CtrlEnum_IMI : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; - end - Src2CtrlEnum_IMS : begin - _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; - end - default : begin - _zz_decode_SRC2_6 = _zz_decode_SRC2; - end - endcase - end - - always @(*) begin - execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; - if(execute_SRC2_FORCE_ZERO) begin - execute_SrcPlugin_addSub = execute_SRC1; - end - end - - assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @(*) begin - _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; - _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; - _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; - _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; - _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; - _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; - _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; - _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; - _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; - _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; - _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; - _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; - _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; - _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; - _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; - _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; - _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; - _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; - _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; - _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; - _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; - _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; - _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; - _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; - _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; - _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; - _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; - _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; - _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; - _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; - _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; - _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); - always @(*) begin - _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; - _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; - _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; - _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; - _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; - _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; - _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; - _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; - _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; - _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; - _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; - _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; - _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; - _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; - _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; - _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; - _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; - _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; - _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; - _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; - _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; - _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; - _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; - _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; - _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; - _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; - _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; - _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; - _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; - _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; - _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; - _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; - end - - always @(*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l48) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l48_1) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l48_2) begin - HazardSimplePlugin_src0Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l105) begin - HazardSimplePlugin_src0Hazard = 1'b0; - end - end - - always @(*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(when_HazardSimplePlugin_l57) begin - if(when_HazardSimplePlugin_l58) begin - if(when_HazardSimplePlugin_l51) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_1) begin - if(when_HazardSimplePlugin_l58_1) begin - if(when_HazardSimplePlugin_l51_1) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l57_2) begin - if(when_HazardSimplePlugin_l58_2) begin - if(when_HazardSimplePlugin_l51_2) begin - HazardSimplePlugin_src1Hazard = 1'b1; - end - end - end - if(when_HazardSimplePlugin_l108) begin - HazardSimplePlugin_src1Hazard = 1'b0; - end - end - - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l47 = 1'b1; - assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); - assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); - assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); - assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); - assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); - assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); - assign execute_MulPlugin_a = execute_RS1; - assign execute_MulPlugin_b = execute_RS2; - assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_aSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_aSigned = 1'b1; - end - default : begin - execute_MulPlugin_aSigned = 1'b0; - end - endcase - end - - always @(*) begin - case(switch_MulPlugin_l87) - 2'b01 : begin - execute_MulPlugin_bSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_bSigned = 1'b0; - end - default : begin - execute_MulPlugin_bSigned = 1'b0; - end - endcase - end - - assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; - assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; - assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; - assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; - assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; - assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); - assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); - assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; - end - end - end - - always @(*) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; - end - end - - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); - assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); - always @(*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); - end - if(memory_MulDivIterativePlugin_div_counter_willClear) begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end - end - - assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); - assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); - assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); - assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; - assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); - assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); - assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @(*) begin - _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; - end - - always @(*) begin - CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire) begin - CsrPlugin_privilege = 2'b11; - end - end - - assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; - end - if(decode_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; - end - if(execute_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; - end - end - - always @(*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; - end - if(writeBack_arbitration_isFlushed) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; - end - end - - assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); - assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); - assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); - assign CsrPlugin_lastStageWasWfi = 1'b0; - assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); - assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); - assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); - always @(*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(when_CsrPlugin_l1004) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - if(CsrPlugin_hadException) begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - end - - assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); - assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @(*) begin - CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException) begin - CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - end - end - - always @(*) begin - CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException) begin - CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; - end - end - - always @(*) begin - CsrPlugin_xtvec_mode = 2'bxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; - end - default : begin - end - endcase - end - - always @(*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; - end - default : begin - end - endcase - end - - assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); - assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; - assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); - assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); - always @(*) begin - execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3860) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_769) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_768) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_836) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_772) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_773) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_833) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_832) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_834) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_835) begin - if(execute_CSR_READ_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(CsrPlugin_csrMapping_allowCsrSignal) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_illegalAccess = 1'b1; - end - if(when_CsrPlugin_l1315) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_illegalInstruction = 1'b0; - if(when_CsrPlugin_l1149) begin - if(when_CsrPlugin_l1150) begin - execute_CsrPlugin_illegalInstruction = 1'b1; - end - end - end - - always @(*) begin - CsrPlugin_selfException_valid = 1'b0; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1157) begin - CsrPlugin_selfException_valid = 1'b1; - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_valid = 1'b1; - end - end - - always @(*) begin - CsrPlugin_selfException_payload_code = 4'bxxxx; - if(when_CsrPlugin_l1142) begin - CsrPlugin_selfException_payload_code = 4'b0010; - end - if(when_CsrPlugin_l1157) begin - case(CsrPlugin_privilege) - 2'b00 : begin - CsrPlugin_selfException_payload_code = 4'b1000; - end - default : begin - CsrPlugin_selfException_payload_code = 4'b1011; - end - endcase - end - if(when_CsrPlugin_l1167) begin - CsrPlugin_selfException_payload_code = 4'b0011; - end - end - - assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); - assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); - assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); - assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); - always @(*) begin - execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_writeInstruction = 1'b0; - end - end - - always @(*) begin - execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(when_CsrPlugin_l1310) begin - execute_CsrPlugin_readInstruction = 1'b0; - end - end - - assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); - assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; - assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; - always @(*) begin - case(switch_Misc_l210_1) - 1'b0 : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; - end - default : begin - _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); - end - endcase - end - - assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; - assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); - assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); - assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; - always @(*) begin - casez(switch_Misc_l210_2) - 3'b000 : begin - _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; - end - 3'b001 : begin - _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); - end - 3'b1?1 : begin - _zz_execute_BRANCH_DO = (! execute_SRC_LESS); - end - default : begin - _zz_execute_BRANCH_DO = execute_SRC_LESS; - end - endcase - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_INC : begin - _zz_execute_BRANCH_DO_1 = 1'b0; - end - BranchCtrlEnum_JAL : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BRANCH_DO_1 = 1'b1; - end - default : begin - _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; - end - endcase - end - - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); - assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; - _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; - end - - assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; - _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; - end - - assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; - always @(*) begin - _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; - _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; - end - - always @(*) begin - case(execute_BRANCH_CTRL) - BranchCtrlEnum_JAL : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - end - BranchCtrlEnum_JALR : begin - _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; - end - default : begin - _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - end - endcase - end - - assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); - assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); - always @(*) begin - debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; - end - end - default : begin - end - endcase - end - end - - always @(*) begin - debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if(when_DebugPlugin_l244) begin - debug_bus_rsp_data[0] = DebugPlugin_resetIt; - debug_bus_rsp_data[1] = DebugPlugin_haltIt; - debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; - debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; - debug_bus_rsp_data[4] = DebugPlugin_stepIt; - end - end - - assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); - always @(*) begin - IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h01 : begin - if(debug_bus_cmd_payload_wr) begin - IBusCachedPlugin_injectionPort_valid = 1'b1; - end - end - default : begin - end - endcase - end - end - - assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; - assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; - assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; - assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; - assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; - assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; - assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; - assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); - assign when_Pipeline_l124 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); - assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); - assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; - assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; - assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; - assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; - assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; - assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; - assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; - assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); - assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; - assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; - assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; - assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); - assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; - assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); - assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; - assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); - assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; - assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; - assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; - assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; - assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); - assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; - assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); - assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; - assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); - assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; - assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; - assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; - assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); - assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; - assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); - assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); - assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); - assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); - assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - always @(*) begin - IBusCachedPlugin_injectionPort_ready = 1'b0; - case(switch_Fetcher_l365) - 3'b100 : begin - IBusCachedPlugin_injectionPort_ready = 1'b1; - end - default : begin - end - endcase - end - - assign when_Fetcher_l381 = (! decode_arbitration_isStuck); - assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); - assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); - assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; - if(execute_CsrPlugin_csr_768) begin - _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; - if(execute_CsrPlugin_csr_836) begin - _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; - _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; - if(execute_CsrPlugin_csr_772) begin - _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; - _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; - if(execute_CsrPlugin_csr_773) begin - _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; - _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; - if(execute_CsrPlugin_csr_833) begin - _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; - if(execute_CsrPlugin_csr_832) begin - _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; - if(execute_CsrPlugin_csr_834) begin - _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; - if(execute_CsrPlugin_csr_835) begin - _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; - end - end - - assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); - assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - IBusCachedPlugin_fetchPc_booted <= 1'b0; - IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - IBusCachedPlugin_rspCounter <= 32'h0; - dataCache_1_io_mem_cmd_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dBus_rsp_regNext_valid <= 1'b0; - DBusCachedPlugin_rspCounter <= 32'h0; - _zz_2 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; - memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - CsrPlugin_misa_base <= 2'b01; - CsrPlugin_misa_extensions <= 26'h0041101; - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= 2'b11; - CsrPlugin_mie_MEIE <= 1'b0; - CsrPlugin_mie_MTIE <= 1'b0; - CsrPlugin_mie_MSIE <= 1'b0; - CsrPlugin_mcycle <= 64'h0; - CsrPlugin_minstret <= 64'h0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - CsrPlugin_interrupt_valid <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - CsrPlugin_hadException <= 1'b0; - execute_CsrPlugin_wfiWake <= 1'b0; - execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - switch_Fetcher_l365 <= 3'b000; - end else begin - if(IBusCachedPlugin_fetchPc_correction) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_output_fire) begin - IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; - end - IBusCachedPlugin_fetchPc_booted <= 1'b1; - if(when_Fetcher_l134) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_output_fire_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b1; - end - if(when_Fetcher_l134_1) begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if(when_Fetcher_l161) begin - IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; - end - if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); - end - if(IBusCachedPlugin_iBusRsp_flush) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); - end - if(decode_arbitration_removeIt) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - end - if(when_Fetcher_l332) begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(when_Fetcher_l332_1) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(when_Fetcher_l332_2) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(when_Fetcher_l332_3) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(when_Fetcher_l332_4) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(when_Fetcher_l332_5) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; - end - if(IBusCachedPlugin_fetchPc_flushed) begin - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - end - if(iBus_rsp_valid) begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); - end - if(dataCache_1_io_mem_cmd_valid) begin - dataCache_1_io_mem_cmd_rValid <= 1'b1; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_rValid <= 1'b0; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; - end - dBus_rsp_regNext_valid <= dBus_rsp_valid; - if(dBus_rsp_valid) begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); - end - _zz_2 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; - memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring) begin - CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); - end - if(when_CsrPlugin_l922) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - end - if(when_CsrPlugin_l922_1) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if(when_CsrPlugin_l922_2) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if(when_CsrPlugin_l922_3) begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - end - CsrPlugin_interrupt_valid <= 1'b0; - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_valid <= 1'b1; - end - end - if(CsrPlugin_pipelineLiberator_active) begin - if(when_CsrPlugin_l993) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; - end - if(when_CsrPlugin_l993_1) begin - CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; - end - if(when_CsrPlugin_l993_2) begin - CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; - end - end - if(when_CsrPlugin_l998) begin - CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; - end - if(CsrPlugin_interruptJump) begin - CsrPlugin_interrupt_valid <= 1'b0; - end - CsrPlugin_hadException <= CsrPlugin_exception; - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; - CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; - end - default : begin - end - endcase - end - if(when_CsrPlugin_l1077) begin - case(switch_CsrPlugin_l1081) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b00; - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; - end - default : begin - end - endcase - end - execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(when_Pipeline_l151) begin - execute_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154) begin - execute_arbitration_isValid <= decode_arbitration_isValid; - end - if(when_Pipeline_l151_1) begin - memory_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_1) begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(when_Pipeline_l151_2) begin - writeBack_arbitration_isValid <= 1'b0; - end - if(when_Pipeline_l154_2) begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(switch_Fetcher_l365) - 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid) begin - switch_Fetcher_l365 <= 3'b001; - end - end - 3'b001 : begin - switch_Fetcher_l365 <= 3'b010; - end - 3'b010 : begin - switch_Fetcher_l365 <= 3'b011; - end - 3'b011 : begin - if(when_Fetcher_l381) begin - switch_Fetcher_l365 <= 3'b100; - end - end - 3'b100 : begin - switch_Fetcher_l365 <= 3'b000; - end - default : begin - end - endcase - if(execute_CsrPlugin_csr_769) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; - CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; - end - end - if(execute_CsrPlugin_csr_768) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - case(switch_CsrPlugin_l723) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= 2'b11; - end - default : begin - end - endcase - end - end - if(execute_CsrPlugin_csr_772) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; - CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; - CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - end - end - - always @(posedge io_systemClk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin - _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_output_ready) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; - end - if(IBusCachedPlugin_injector_decodeInput_ready) begin - IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; - end - if(dataCache_1_io_mem_cmd_ready) begin - dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; - dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; - dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; - dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; - execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); - if(when_MulPlugin_l70) begin - execute_MulPlugin_delayLogic_counter <= 1'b0; - end - execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - if(when_MulDivIterativePlugin_l126) begin - memory_MulDivIterativePlugin_div_done <= 1'b1; - end - if(when_MulDivIterativePlugin_l126_1) begin - memory_MulDivIterativePlugin_div_done <= 1'b0; - end - if(when_MulDivIterativePlugin_l128) begin - if(when_MulDivIterativePlugin_l132) begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if(when_MulDivIterativePlugin_l151) begin - memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; - end - end - end - if(when_MulDivIterativePlugin_l162) begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); - memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - if(_zz_when) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(BranchPlugin_branchExceptionPort_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid) begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; - end - if(when_CsrPlugin_l959) begin - if(when_CsrPlugin_l965) begin - CsrPlugin_interrupt_code <= 4'b0111; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_1) begin - CsrPlugin_interrupt_code <= 4'b0011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - if(when_CsrPlugin_l965_2) begin - CsrPlugin_interrupt_code <= 4'b1011; - CsrPlugin_interrupt_targetPrivilege <= 2'b11; - end - end - if(when_CsrPlugin_l1032) begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException) begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase - end - if(when_Pipeline_l124) begin - decode_to_execute_PC <= _zz_decode_SRC2; - end - if(when_Pipeline_l124_1) begin - execute_to_memory_PC <= execute_PC; - end - if(when_Pipeline_l124_2) begin - memory_to_writeBack_PC <= memory_PC; - end - if(when_Pipeline_l124_3) begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; - end - if(when_Pipeline_l124_4) begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; - end - if(when_Pipeline_l124_5) begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if(when_Pipeline_l124_6) begin - decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_7) begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_8) begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; - end - if(when_Pipeline_l124_9) begin - decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; - end - if(when_Pipeline_l124_10) begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; - end - if(when_Pipeline_l124_11) begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; - end - if(when_Pipeline_l124_12) begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; - end - if(when_Pipeline_l124_13) begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if(when_Pipeline_l124_14) begin - decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; - end - if(when_Pipeline_l124_15) begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_16) begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_17) begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; - end - if(when_Pipeline_l124_18) begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; - end - if(when_Pipeline_l124_19) begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_20) begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end - if(when_Pipeline_l124_21) begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; - end - if(when_Pipeline_l124_22) begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; - end - if(when_Pipeline_l124_23) begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; - end - if(when_Pipeline_l124_24) begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; - end - if(when_Pipeline_l124_25) begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; - end - if(when_Pipeline_l124_26) begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; - end - if(when_Pipeline_l124_27) begin - decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; - end - if(when_Pipeline_l124_28) begin - execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; - end - if(when_Pipeline_l124_29) begin - decode_to_execute_IS_MUL <= decode_IS_MUL; - end - if(when_Pipeline_l124_30) begin - execute_to_memory_IS_MUL <= execute_IS_MUL; - end - if(when_Pipeline_l124_31) begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; - end - if(when_Pipeline_l124_32) begin - decode_to_execute_IS_DIV <= decode_IS_DIV; - end - if(when_Pipeline_l124_33) begin - execute_to_memory_IS_DIV <= execute_IS_DIV; - end - if(when_Pipeline_l124_34) begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; - end - if(when_Pipeline_l124_35) begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; - end - if(when_Pipeline_l124_36) begin - decode_to_execute_IS_CSR <= decode_IS_CSR; - end - if(when_Pipeline_l124_37) begin - decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; - end - if(when_Pipeline_l124_38) begin - execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; - end - if(when_Pipeline_l124_39) begin - memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; - end - if(when_Pipeline_l124_40) begin - decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; - end - if(when_Pipeline_l124_41) begin - decode_to_execute_RS1 <= _zz_decode_SRC1; - end - if(when_Pipeline_l124_42) begin - decode_to_execute_RS2 <= _zz_decode_SRC2_1; - end - if(when_Pipeline_l124_43) begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; - end - if(when_Pipeline_l124_44) begin - decode_to_execute_SRC1 <= decode_SRC1; - end - if(when_Pipeline_l124_45) begin - decode_to_execute_SRC2 <= decode_SRC2; - end - if(when_Pipeline_l124_46) begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; - end - if(when_Pipeline_l124_47) begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; - end - if(when_Pipeline_l124_48) begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; - end - if(when_Pipeline_l124_49) begin - execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_50) begin - memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; - end - if(when_Pipeline_l124_51) begin - execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; - end - if(when_Pipeline_l124_52) begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; - end - if(when_Pipeline_l124_53) begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; - end - if(when_Pipeline_l124_54) begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; - end - if(when_Pipeline_l124_55) begin - execute_to_memory_MUL_LL <= execute_MUL_LL; - end - if(when_Pipeline_l124_56) begin - execute_to_memory_MUL_LH <= execute_MUL_LH; - end - if(when_Pipeline_l124_57) begin - execute_to_memory_MUL_HL <= execute_MUL_HL; - end - if(when_Pipeline_l124_58) begin - execute_to_memory_MUL_HH <= execute_MUL_HH; - end - if(when_Pipeline_l124_59) begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; - end - if(when_Pipeline_l124_60) begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if(when_Pipeline_l124_61) begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end - if(when_Pipeline_l124_62) begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; - end - if(when_Fetcher_l401) begin - _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; - end - if(when_CsrPlugin_l1277) begin - execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); - end - if(when_CsrPlugin_l1277_1) begin - execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); - end - if(when_CsrPlugin_l1277_2) begin - execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); - end - if(when_CsrPlugin_l1277_3) begin - execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); - end - if(when_CsrPlugin_l1277_4) begin - execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); - end - if(when_CsrPlugin_l1277_5) begin - execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); - end - if(when_CsrPlugin_l1277_6) begin - execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); - end - if(when_CsrPlugin_l1277_7) begin - execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); - end - if(when_CsrPlugin_l1277_8) begin - execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); - end - if(when_CsrPlugin_l1277_9) begin - execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); - end - if(execute_CsrPlugin_csr_836) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; - end - end - if(execute_CsrPlugin_csr_773) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; - CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; - end - end - if(execute_CsrPlugin_csr_833) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_832) begin - if(execute_CsrPlugin_writeEnable) begin - CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - end - - always @(posedge io_systemClk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready) begin - DebugPlugin_firstCycle <= 1'b1; - end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid) begin - DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; - end - _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; - if(when_DebugPlugin_l295) begin - DebugPlugin_busReadDataReg <= execute_PC; - end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - DebugPlugin_debugUsed <= 1'b0; - DebugPlugin_disableEbreak <= 1'b0; - end else begin - if(when_DebugPlugin_l225) begin - DebugPlugin_godmode <= 1'b1; - end - if(debug_bus_cmd_valid) begin - DebugPlugin_debugUsed <= 1'b1; - end - if(debug_bus_cmd_valid) begin - case(switch_DebugPlugin_l267) - 6'h0 : begin - if(debug_bus_cmd_payload_wr) begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(when_DebugPlugin_l271) begin - DebugPlugin_resetIt <= 1'b1; - end - if(when_DebugPlugin_l271_1) begin - DebugPlugin_resetIt <= 1'b0; - end - if(when_DebugPlugin_l272) begin - DebugPlugin_haltIt <= 1'b1; - end - if(when_DebugPlugin_l272_1) begin - DebugPlugin_haltIt <= 1'b0; - end - if(when_DebugPlugin_l273) begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(when_DebugPlugin_l274) begin - DebugPlugin_godmode <= 1'b0; - end - if(when_DebugPlugin_l275) begin - DebugPlugin_disableEbreak <= 1'b1; - end - if(when_DebugPlugin_l275_1) begin - DebugPlugin_disableEbreak <= 1'b0; - end - end - end - default : begin - end - endcase - end - if(when_DebugPlugin_l295) begin - if(when_DebugPlugin_l298) begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end - end - if(when_DebugPlugin_l311) begin - if(decode_arbitration_isValid) begin - DebugPlugin_haltIt <= 1'b1; - end - end - end - end - - -endmodule - -module BufferCC_3 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin - if(debugCd_logic_outputReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module BufferCC_2 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input io_asyncReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk or posedge io_asyncReset) begin - if(io_asyncReset) begin - buffers_0 <= 1'b1; - buffers_1 <= 1'b1; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule - -module StreamFifo_3 ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload_data; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [7:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload_data = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload_data) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload_data; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module StreamFifo_2 ( - input io_push_valid, - output io_push_ready, - input io_push_payload_kind, - input io_push_payload_read, - input io_push_payload_write, - input [7:0] io_push_payload_data, - output io_pop_valid, - input io_pop_ready, - output io_pop_payload_kind, - output io_pop_payload_read, - output io_pop_payload_write, - output [7:0] io_pop_payload_data, - input io_flush, - output [8:0] io_occupancy, - output [8:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [10:0] _zz_logic_ram_port0; - wire [7:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [7:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz__zz_io_pop_payload_kind; - wire [10:0] _zz_logic_ram_port_1; - wire [7:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [7:0] logic_pushPtr_valueNext; - reg [7:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [7:0] logic_popPtr_valueNext; - reg [7:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire [10:0] _zz_io_pop_payload_kind; - wire when_Stream_l1037; - wire [7:0] logic_ptrDif; - reg [10:0] logic_ram [0:255]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz__zz_io_pop_payload_kind = 1'b1; - assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; - always @(posedge io_systemClk) begin - if(_zz__zz_io_pop_payload_kind) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 8'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 8'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; - assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; - assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; - assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; - assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 8'h0; - logic_popPtr_value <= 8'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module TopLevel ( - input io_config_kind_cpol, - input io_config_kind_cpha, - input [11:0] io_config_sclkToogle, - input [1:0] io_config_mod, - input [0:0] io_config_ss_activeHigh, - input [11:0] io_config_ss_setup, - input [11:0] io_config_ss_hold, - input [11:0] io_config_ss_disable, - input io_cmd_valid, - output reg io_cmd_ready, - input io_cmd_payload_kind, - input io_cmd_payload_read, - input io_cmd_payload_write, - input [7:0] io_cmd_payload_data, - output io_rsp_valid, - output [7:0] io_rsp_payload_data, - output [0:0] io_spi_sclk_write, - output reg io_spi_data_0_writeEnable, - input [0:0] io_spi_data_0_read, - output reg [0:0] io_spi_data_0_write, - output reg io_spi_data_1_writeEnable, - input [0:0] io_spi_data_1_read, - output reg [0:0] io_spi_data_1_write, - output reg io_spi_data_2_writeEnable, - input [0:0] io_spi_data_2_read, - output reg [0:0] io_spi_data_2_write, - output reg io_spi_data_3_writeEnable, - input [0:0] io_spi_data_3_read, - output reg [0:0] io_spi_data_3_write, - output [0:0] io_spi_ss, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [0:0] _zz_outputPhy_dataWrite_3; - wire [2:0] _zz_outputPhy_dataWrite_4; - wire [2:0] _zz_outputPhy_dataWrite_5; - reg [1:0] _zz_outputPhy_dataWrite_6; - wire [1:0] _zz_outputPhy_dataWrite_7; - wire [2:0] _zz_outputPhy_dataWrite_8; - reg [3:0] _zz_outputPhy_dataWrite_9; - wire [0:0] _zz_outputPhy_dataWrite_10; - wire [2:0] _zz_outputPhy_dataWrite_11; - wire [3:0] _zz_inputPhy_dataRead; - wire [3:0] _zz_inputPhy_dataRead_1; - wire [3:0] _zz_inputPhy_dataRead_2; - wire [3:0] _zz_inputPhy_dataRead_3; - wire [3:0] _zz_inputPhy_dataRead_4; - wire [3:0] _zz_inputPhy_dataRead_5; - wire [3:0] _zz_inputPhy_dataRead_6; - wire [8:0] _zz_inputPhy_bufferNext; - wire [10:0] _zz_inputPhy_bufferNext_1; - reg [11:0] timer_counter; - reg timer_reset; - wire timer_ss_setupHit; - wire timer_ss_holdHit; - wire timer_ss_disableHit; - wire timer_sclkToogleHit; - reg fsm_state; - reg [2:0] fsm_counter; - reg [2:0] _zz_fsm_counterPlus; - wire [2:0] fsm_counterPlus; - reg fsm_fastRate; - reg fsm_isDdr; - reg [2:0] fsm_counterMax; - reg fsm_lateSampling; - reg fsm_readFill; - reg fsm_readDone; - reg [0:0] fsm_ss; - wire when_SpiXdrMasterCtrl_l739; - wire when_SpiXdrMasterCtrl_l742; - wire when_SpiXdrMasterCtrl_l749; - wire when_SpiXdrMasterCtrl_l751; - wire when_SpiXdrMasterCtrl_l758; - wire when_SpiXdrMasterCtrl_l764; - wire when_SpiXdrMasterCtrl_l781; - reg [0:0] outputPhy_sclkWrite; - wire [0:0] _zz_io_spi_sclk_write; - wire when_SpiXdrMasterCtrl_l796; - reg [3:0] outputPhy_dataWrite; - reg [2:0] outputPhy_widthSel; - reg [2:0] outputPhy_offset; - wire [7:0] _zz_outputPhy_dataWrite; - wire [7:0] _zz_outputPhy_dataWrite_1; - wire [7:0] _zz_outputPhy_dataWrite_2; - wire when_SpiXdrMasterCtrl_l839; - wire when_SpiXdrMasterCtrl_l839_1; - reg [1:0] io_config_mod_delay_1; - reg [1:0] inputPhy_mod; - reg fsm_readFill_delay_1; - reg inputPhy_readFill; - reg fsm_readDone_delay_1; - reg inputPhy_readDone; - reg [6:0] inputPhy_buffer; - reg [7:0] inputPhy_bufferNext; - reg [2:0] inputPhy_widthSel; - wire [3:0] inputPhy_dataWrite; - reg [3:0] inputPhy_dataRead; - reg fsm_state_delay_1; - reg fsm_state_delay_2; - wire when_SpiXdrMasterCtrl_l861; - reg [3:0] inputPhy_dataReadBuffer; - - assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); - assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); - assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); - assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); - assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); - assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; - assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; - always @(*) begin - case(_zz_outputPhy_dataWrite_4) - 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; - 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; - 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; - 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; - 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; - 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; - 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; - default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_7) - 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; - 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; - 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; - default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; - endcase - end - - always @(*) begin - case(_zz_outputPhy_dataWrite_10) - 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; - default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; - endcase - end - - always @(*) begin - timer_reset = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - timer_reset = timer_sclkToogleHit; - end else begin - if(!when_SpiXdrMasterCtrl_l758) begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - timer_reset = 1'b1; - end - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - timer_reset = 1'b1; - end - end - - assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); - assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); - assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); - assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); - always @(*) begin - _zz_fsm_counterPlus = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - _zz_fsm_counterPlus = 3'b001; - end - 2'b01 : begin - _zz_fsm_counterPlus = 3'b010; - end - 2'b10 : begin - _zz_fsm_counterPlus = 3'b100; - end - default : begin - end - endcase - end - - assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); - always @(*) begin - fsm_fastRate = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_fastRate = 1'b0; - end - 2'b01 : begin - fsm_fastRate = 1'b0; - end - 2'b10 : begin - fsm_fastRate = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_isDdr = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_isDdr = 1'b0; - end - 2'b01 : begin - fsm_isDdr = 1'b0; - end - 2'b10 : begin - fsm_isDdr = 1'b0; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_counterMax = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - fsm_counterMax = 3'b111; - end - 2'b01 : begin - fsm_counterMax = 3'b110; - end - 2'b10 : begin - fsm_counterMax = 3'b100; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_lateSampling = 1'bx; - case(io_config_mod) - 2'b00 : begin - fsm_lateSampling = 1'b1; - end - 2'b01 : begin - fsm_lateSampling = 1'b1; - end - 2'b10 : begin - fsm_lateSampling = 1'b1; - end - default : begin - end - endcase - end - - always @(*) begin - fsm_readFill = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readFill = 1'b1; - end - end - end - end - - always @(*) begin - fsm_readDone = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l742) begin - fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); - end - end - end - end - - assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); - always @(*) begin - io_cmd_ready = 1'b0; - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(when_SpiXdrMasterCtrl_l749) begin - if(when_SpiXdrMasterCtrl_l751) begin - io_cmd_ready = 1'b1; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - if(timer_ss_setupHit) begin - io_cmd_ready = 1'b1; - end - end else begin - if(!when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_disableHit) begin - io_cmd_ready = 1'b1; - end - end - end - end - end - end - - assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); - assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); - assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); - assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; - assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); - assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); - always @(*) begin - outputPhy_sclkWrite = 1'b0; - if(when_SpiXdrMasterCtrl_l796) begin - case(io_config_mod) - 2'b00 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b01 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - 2'b10 : begin - outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); - end - default : begin - end - endcase - end - end - - assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; - assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); - assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); - always @(*) begin - outputPhy_widthSel = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_widthSel = 3'b000; - end - 2'b01 : begin - outputPhy_widthSel = 3'b001; - end - 2'b10 : begin - outputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_offset = 3'bxxx; - case(io_config_mod) - 2'b00 : begin - outputPhy_offset = 3'b111; - end - 2'b01 : begin - outputPhy_offset = 3'b111; - end - 2'b10 : begin - outputPhy_offset = 3'b111; - end - default : begin - end - endcase - end - - always @(*) begin - outputPhy_dataWrite = 4'bxxxx; - case(outputPhy_widthSel) - 3'b000 : begin - outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; - end - 3'b001 : begin - outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; - end - 3'b010 : begin - outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; - end - default : begin - end - endcase - end - - assign _zz_outputPhy_dataWrite = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; - assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; - always @(*) begin - io_spi_data_0_writeEnable = 1'b0; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_writeEnable = 1'b1; - end - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_0_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_writeEnable = 1'b0; - case(io_config_mod) - 2'b01 : begin - if(when_SpiXdrMasterCtrl_l839) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_1_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_2_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_writeEnable = 1'b0; - case(io_config_mod) - 2'b10 : begin - if(when_SpiXdrMasterCtrl_l839_1) begin - io_spi_data_3_writeEnable = 1'b1; - end - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_0_write = 1'bx; - case(io_config_mod) - 2'b00 : begin - io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); - end - 2'b01 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - 2'b10 : begin - io_spi_data_0_write[0] = outputPhy_dataWrite[0]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_1_write = 1'bx; - case(io_config_mod) - 2'b01 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - 2'b10 : begin - io_spi_data_1_write[0] = outputPhy_dataWrite[1]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_2_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_2_write[0] = outputPhy_dataWrite[2]; - end - default : begin - end - endcase - end - - always @(*) begin - io_spi_data_3_write = 1'bx; - case(io_config_mod) - 2'b10 : begin - io_spi_data_3_write[0] = outputPhy_dataWrite[3]; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); - assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); - always @(*) begin - inputPhy_bufferNext = 8'bxxxxxxxx; - case(inputPhy_widthSel) - 3'b000 : begin - inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; - end - 3'b001 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; - end - 3'b010 : begin - inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; - end - default : begin - end - endcase - end - - always @(*) begin - inputPhy_widthSel = 3'bxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_widthSel = 3'b000; - end - 2'b01 : begin - inputPhy_widthSel = 3'b001; - end - 2'b10 : begin - inputPhy_widthSel = 3'b010; - end - default : begin - end - endcase - end - - assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); - always @(*) begin - inputPhy_dataRead = 4'bxxxx; - case(inputPhy_mod) - 2'b00 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; - end - 2'b01 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; - end - 2'b10 : begin - inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; - inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; - inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; - inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; - end - default : begin - end - endcase - end - - assign io_rsp_valid = inputPhy_readDone; - assign io_rsp_payload_data = inputPhy_bufferNext; - always @(posedge io_systemClk) begin - timer_counter <= (timer_counter + 12'h001); - if(timer_reset) begin - timer_counter <= 12'h0; - end - io_config_mod_delay_1 <= io_config_mod; - inputPhy_mod <= io_config_mod_delay_1; - fsm_state_delay_1 <= fsm_state; - fsm_state_delay_2 <= fsm_state_delay_1; - if(when_SpiXdrMasterCtrl_l861) begin - inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; - end - case(inputPhy_widthSel) - 3'b000 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b001 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - 3'b010 : begin - if(inputPhy_readFill) begin - inputPhy_buffer <= inputPhy_bufferNext[6:0]; - end - end - default : begin - end - endcase - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - fsm_ss <= 1'b0; - fsm_readFill_delay_1 <= 1'b0; - inputPhy_readFill <= 1'b0; - fsm_readDone_delay_1 <= 1'b0; - inputPhy_readDone <= 1'b0; - end else begin - if(io_cmd_valid) begin - if(when_SpiXdrMasterCtrl_l739) begin - if(timer_sclkToogleHit) begin - fsm_state <= (! fsm_state); - end - if(when_SpiXdrMasterCtrl_l749) begin - fsm_counter <= fsm_counterPlus; - if(when_SpiXdrMasterCtrl_l751) begin - fsm_state <= 1'b0; - end - end - end else begin - if(when_SpiXdrMasterCtrl_l758) begin - fsm_ss[0] <= 1'b1; - end else begin - if(when_SpiXdrMasterCtrl_l764) begin - if(timer_ss_holdHit) begin - fsm_state <= 1'b1; - end - end else begin - fsm_ss[0] <= 1'b0; - end - end - end - end - if(when_SpiXdrMasterCtrl_l781) begin - fsm_state <= 1'b0; - fsm_counter <= 3'b000; - end - fsm_readFill_delay_1 <= fsm_readFill; - inputPhy_readFill <= fsm_readFill_delay_1; - fsm_readDone_delay_1 <= fsm_readDone; - inputPhy_readDone <= fsm_readDone_delay_1; - end - end - - -endmodule - -//StreamFifo replaced by StreamFifo - -module StreamFifo ( - input io_push_valid, - output io_push_ready, - input [7:0] io_push_payload, - output io_pop_valid, - input io_pop_ready, - output [7:0] io_pop_payload, - input io_flush, - output [7:0] io_occupancy, - output [7:0] io_availability, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [7:0] _zz_logic_ram_port0; - wire [6:0] _zz_logic_pushPtr_valueNext; - wire [0:0] _zz_logic_pushPtr_valueNext_1; - wire [6:0] _zz_logic_popPtr_valueNext; - wire [0:0] _zz_logic_popPtr_valueNext_1; - wire _zz_logic_ram_port; - wire _zz_io_pop_payload; - wire [6:0] _zz_io_availability; - reg _zz_1; - reg logic_pushPtr_willIncrement; - reg logic_pushPtr_willClear; - reg [6:0] logic_pushPtr_valueNext; - reg [6:0] logic_pushPtr_value; - wire logic_pushPtr_willOverflowIfInc; - wire logic_pushPtr_willOverflow; - reg logic_popPtr_willIncrement; - reg logic_popPtr_willClear; - reg [6:0] logic_popPtr_valueNext; - reg [6:0] logic_popPtr_value; - wire logic_popPtr_willOverflowIfInc; - wire logic_popPtr_willOverflow; - wire logic_ptrMatch; - reg logic_risingOccupancy; - wire logic_pushing; - wire logic_popping; - wire logic_empty; - wire logic_full; - reg _zz_io_pop_valid; - wire when_Stream_l1037; - wire [6:0] logic_ptrDif; - reg [7:0] logic_ram [0:127]; - - assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; - assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; - assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; - assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; - assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); - assign _zz_io_pop_payload = 1'b1; - always @(posedge io_systemClk) begin - if(_zz_io_pop_payload) begin - _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_1) begin - logic_ram[logic_pushPtr_value] <= io_push_payload; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(logic_pushing) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willIncrement = 1'b0; - if(logic_pushing) begin - logic_pushPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_pushPtr_willClear = 1'b0; - if(io_flush) begin - logic_pushPtr_willClear = 1'b1; - end - end - - assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); - assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); - always @(*) begin - logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); - if(logic_pushPtr_willClear) begin - logic_pushPtr_valueNext = 7'h0; - end - end - - always @(*) begin - logic_popPtr_willIncrement = 1'b0; - if(logic_popping) begin - logic_popPtr_willIncrement = 1'b1; - end - end - - always @(*) begin - logic_popPtr_willClear = 1'b0; - if(io_flush) begin - logic_popPtr_willClear = 1'b1; - end - end - - assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); - assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); - always @(*) begin - logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); - if(logic_popPtr_willClear) begin - logic_popPtr_valueNext = 7'h0; - end - end - - assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); - assign logic_pushing = (io_push_valid && io_push_ready); - assign logic_popping = (io_pop_valid && io_pop_ready); - assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); - assign logic_full = (logic_ptrMatch && logic_risingOccupancy); - assign io_push_ready = (! logic_full); - assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); - assign io_pop_payload = _zz_logic_ram_port0; - assign when_Stream_l1037 = (logic_pushing != logic_popping); - assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); - assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; - assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - logic_pushPtr_value <= 7'h0; - logic_popPtr_value <= 7'h0; - logic_risingOccupancy <= 1'b0; - _zz_io_pop_valid <= 1'b0; - end else begin - logic_pushPtr_value <= logic_pushPtr_valueNext; - logic_popPtr_value <= logic_popPtr_valueNext; - _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); - if(when_Stream_l1037) begin - logic_risingOccupancy <= logic_pushing; - end - if(io_flush) begin - logic_risingOccupancy <= 1'b0; - end - end - end - - -endmodule - -module UartCtrl ( - input [2:0] io_config_frame_dataLength, - input [0:0] io_config_frame_stop, - input [1:0] io_config_frame_parity, - input [19:0] io_config_clockDivider, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - output io_uart_txd, - input io_uart_rxd, - output io_readError, - input io_writeBreak, - output io_readBreak, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - - wire tx_io_write_ready; - wire tx_io_txd; - wire rx_io_read_valid; - wire [7:0] rx_io_read_payload; - wire rx_io_rts; - wire rx_io_error; - wire rx_io_break; - reg [19:0] clockDivider_counter; - wire clockDivider_tick; - reg clockDivider_tickReg; - reg io_write_thrown_valid; - wire io_write_thrown_ready; - wire [7:0] io_write_thrown_payload; - `ifndef SYNTHESIS - reg [23:0] io_config_frame_stop_string; - reg [31:0] io_config_frame_parity_string; - `endif - - - UartCtrlTx tx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_write_valid (io_write_thrown_valid ), //i - .io_write_ready (tx_io_write_ready ), //o - .io_write_payload (io_write_thrown_payload[7:0] ), //i - .io_cts (1'b0 ), //i - .io_txd (tx_io_txd ), //o - .io_break (io_writeBreak ), //i - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - UartCtrlRx rx ( - .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i - .io_configFrame_stop (io_config_frame_stop ), //i - .io_configFrame_parity (io_config_frame_parity[1:0] ), //i - .io_samplingTick (clockDivider_tickReg ), //i - .io_read_valid (rx_io_read_valid ), //o - .io_read_ready (io_read_ready ), //i - .io_read_payload (rx_io_read_payload[7:0] ), //o - .io_rxd (io_uart_rxd ), //i - .io_rts (rx_io_rts ), //o - .io_error (rx_io_error ), //o - .io_break (rx_io_break ), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_config_frame_stop) - UartStopType_ONE : io_config_frame_stop_string = "ONE"; - UartStopType_TWO : io_config_frame_stop_string = "TWO"; - default : io_config_frame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_config_frame_parity) - UartParityType_NONE : io_config_frame_parity_string = "NONE"; - UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; - UartParityType_ODD : io_config_frame_parity_string = "ODD "; - default : io_config_frame_parity_string = "????"; - endcase - end - `endif - - assign clockDivider_tick = (clockDivider_counter == 20'h0); - always @(*) begin - io_write_thrown_valid = io_write_valid; - if(rx_io_break) begin - io_write_thrown_valid = 1'b0; - end - end - - always @(*) begin - io_write_ready = io_write_thrown_ready; - if(rx_io_break) begin - io_write_ready = 1'b1; - end - end - - assign io_write_thrown_payload = io_write_payload; - assign io_write_thrown_ready = tx_io_write_ready; - assign io_read_valid = rx_io_read_valid; - assign io_read_payload = rx_io_read_payload; - assign io_uart_txd = tx_io_txd; - assign io_readError = rx_io_error; - assign io_readBreak = rx_io_break; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter <= 20'h0; - clockDivider_tickReg <= 1'b0; - end else begin - clockDivider_tickReg <= clockDivider_tick; - clockDivider_counter <= (clockDivider_counter - 20'h00001); - if(clockDivider_tick) begin - clockDivider_counter <= io_config_clockDivider; - end - end - end - - -endmodule - -module StreamArbiter ( - input io_inputs_0_valid, - output io_inputs_0_ready, - input io_inputs_0_payload_last, - input [0:0] io_inputs_0_payload_fragment_source, - input [0:0] io_inputs_0_payload_fragment_opcode, - input [31:0] io_inputs_0_payload_fragment_address, - input [5:0] io_inputs_0_payload_fragment_length, - input [31:0] io_inputs_0_payload_fragment_data, - input [3:0] io_inputs_0_payload_fragment_mask, - input [0:0] io_inputs_0_payload_fragment_context, - input io_inputs_1_valid, - output io_inputs_1_ready, - input io_inputs_1_payload_last, - input [0:0] io_inputs_1_payload_fragment_source, - input [0:0] io_inputs_1_payload_fragment_opcode, - input [31:0] io_inputs_1_payload_fragment_address, - input [5:0] io_inputs_1_payload_fragment_length, - input [31:0] io_inputs_1_payload_fragment_data, - input [3:0] io_inputs_1_payload_fragment_mask, - input [0:0] io_inputs_1_payload_fragment_context, - output io_output_valid, - input io_output_ready, - output io_output_payload_last, - output [0:0] io_output_payload_fragment_source, - output [0:0] io_output_payload_fragment_opcode, - output [31:0] io_output_payload_fragment_address, - output [5:0] io_output_payload_fragment_length, - output [31:0] io_output_payload_fragment_data, - output [3:0] io_output_payload_fragment_mask, - output [0:0] io_output_payload_fragment_context, - output [0:0] io_chosen, - output [1:0] io_chosenOH, - input io_systemClk, - input systemCd_logic_outputReset -); - - wire [3:0] _zz__zz_maskProposal_0_2; - wire [3:0] _zz__zz_maskProposal_0_2_1; - wire [1:0] _zz__zz_maskProposal_0_2_2; - reg locked; - wire maskProposal_0; - wire maskProposal_1; - reg maskLocked_0; - reg maskLocked_1; - wire maskRouted_0; - wire maskRouted_1; - wire [1:0] _zz_maskProposal_0; - wire [3:0] _zz_maskProposal_0_1; - wire [3:0] _zz_maskProposal_0_2; - wire [1:0] _zz_maskProposal_0_3; - wire io_output_fire; - wire when_Stream_l621; - wire _zz_io_chosen; - - assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); - assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; - assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; - assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); - assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); - assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; - assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; - assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); - assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); - assign maskProposal_0 = _zz_maskProposal_0_3[0]; - assign maskProposal_1 = _zz_maskProposal_0_3[1]; - assign io_output_fire = (io_output_valid && io_output_ready); - assign when_Stream_l621 = (io_output_fire && io_output_payload_last); - assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); - assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); - assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); - assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); - assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); - assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); - assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); - assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); - assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); - assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); - assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); - assign io_chosenOH = {maskRouted_1,maskRouted_0}; - assign _zz_io_chosen = io_chosenOH[1]; - assign io_chosen = _zz_io_chosen; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - locked <= 1'b0; - maskLocked_0 <= 1'b0; - maskLocked_1 <= 1'b1; - end else begin - if(io_output_valid) begin - maskLocked_0 <= maskRouted_0; - maskLocked_1 <= maskRouted_1; - end - if(io_output_valid) begin - locked <= 1'b1; - end - if(when_Stream_l621) begin - locked <= 1'b0; - end - end - end - - -endmodule - -module FlowCCByToggle ( - input io_input_valid, - input io_input_payload_last, - input [0:0] io_input_payload_fragment, - output io_output_valid, - output io_output_payload_last, - output [0:0] io_output_payload_fragment, - input jtagCtrl_tck, - input io_systemClk, - input debugCd_logic_outputReset -); - - wire inputArea_target_buffercc_io_dataOut; - reg inputArea_target; - reg inputArea_data_last; - reg [0:0] inputArea_data_fragment; - wire outputArea_target; - reg outputArea_hit; - wire outputArea_flow_valid; - wire outputArea_flow_payload_last; - wire [0:0] outputArea_flow_payload_fragment; - reg outputArea_flow_m2sPipe_valid; - reg outputArea_flow_m2sPipe_payload_last; - reg [0:0] outputArea_flow_m2sPipe_payload_fragment; - - BufferCC_1 inputArea_target_buffercc ( - .io_dataIn (inputArea_target ), //i - .io_dataOut (inputArea_target_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i - ); - initial begin - `ifndef SYNTHESIS - inputArea_target = $urandom; - outputArea_hit = $urandom; - `endif - end - - assign outputArea_target = inputArea_target_buffercc_io_dataOut; - assign outputArea_flow_valid = (outputArea_target != outputArea_hit); - assign outputArea_flow_payload_last = inputArea_data_last; - assign outputArea_flow_payload_fragment = inputArea_data_fragment; - assign io_output_valid = outputArea_flow_m2sPipe_valid; - assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; - assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; - always @(posedge jtagCtrl_tck) begin - if(io_input_valid) begin - inputArea_target <= (! inputArea_target); - inputArea_data_last <= io_input_payload_last; - inputArea_data_fragment <= io_input_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - outputArea_hit <= outputArea_target; - if(outputArea_flow_valid) begin - outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; - outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; - end - end - - always @(posedge io_systemClk) begin - if(debugCd_logic_outputReset) begin - outputArea_flow_m2sPipe_valid <= 1'b0; - end else begin - outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; - end - end - - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - output reg io_cpu_execute_haltIt, - input io_cpu_execute_args_wr, - input [1:0] io_cpu_execute_args_size, - input io_cpu_execute_args_totalyConsistent, - output io_cpu_execute_refilling, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - input [31:0] io_cpu_memory_mmuRsp_physicalAddress, - input io_cpu_memory_mmuRsp_isIoAccess, - input io_cpu_memory_mmuRsp_isPaging, - input io_cpu_memory_mmuRsp_allowRead, - input io_cpu_memory_mmuRsp_allowWrite, - input io_cpu_memory_mmuRsp_allowExecute, - input io_cpu_memory_mmuRsp_exception, - input io_cpu_memory_mmuRsp_refilling, - input io_cpu_memory_mmuRsp_bypassTranslation, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isFiring, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - input [31:0] io_cpu_writeBack_storeData, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output io_cpu_writeBack_keepMemRspData, - input io_cpu_writeBack_fence_SW, - input io_cpu_writeBack_fence_SR, - input io_cpu_writeBack_fence_SO, - input io_cpu_writeBack_fence_SI, - input io_cpu_writeBack_fence_PW, - input io_cpu_writeBack_fence_PR, - input io_cpu_writeBack_fence_PO, - input io_cpu_writeBack_fence_PI, - input [3:0] io_cpu_writeBack_fence_FM, - output io_cpu_writeBack_exclusiveOk, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output io_cpu_flush_ready, - input io_cpu_flush_payload_singleLine, - input [5:0] io_cpu_flush_payload_lineId, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output io_mem_cmd_payload_uncached, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_size, - output io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input io_mem_rsp_payload_last, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [21:0] _zz_ways_0_tags_port0; - reg [31:0] _zz_ways_0_data_port0; - wire [21:0] _zz_ways_0_tags_port; - wire [9:0] _zz_stage0_dataColisions; - wire [9:0] _zz__zz_stageA_dataColisions; - wire [0:0] _zz_when; - wire [3:0] _zz_loader_counter_valueNext; - wire [0:0] _zz_loader_counter_valueNext_1; - wire [1:0] _zz_loader_waysAllocator; - reg _zz_1; - reg _zz_2; - wire haltCpu; - reg tagsReadCmd_valid; - reg [5:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [5:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [5:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; - wire _zz_ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRspMem; - wire [31:0] ways_0_dataReadRsp; - wire when_DataCache_l642; - wire when_DataCache_l645; - wire when_DataCache_l664; - wire rspSync; - wire rspLast; - reg memCmdSent; - wire io_mem_cmd_fire; - wire when_DataCache_l686; - reg [3:0] _zz_stage0_mask; - wire [3:0] stage0_mask; - wire [0:0] stage0_dataColisions; - wire [0:0] stage0_wayInvalidate; - wire stage0_isAmo; - wire when_DataCache_l771; - reg stageA_request_wr; - reg [1:0] stageA_request_size; - reg stageA_request_totalyConsistent; - wire when_DataCache_l771_1; - reg [3:0] stageA_mask; - wire stageA_isAmo; - wire stageA_isLrsc; - wire [0:0] stageA_wayHits; - wire when_DataCache_l771_2; - reg [0:0] stageA_wayInvalidate; - wire when_DataCache_l771_3; - reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_stageA_dataColisions; - wire [0:0] stageA_dataColisions; - wire when_DataCache_l822; - reg stageB_request_wr; - reg [1:0] stageB_request_size; - reg stageB_request_totalyConsistent; - reg stageB_mmuRspFreeze; - wire when_DataCache_l824; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_isPaging; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_mmuRsp_bypassTranslation; - wire when_DataCache_l821; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - wire when_DataCache_l821_1; - reg [31:0] stageB_dataReadRsp_0; - wire when_DataCache_l820; - reg [0:0] stageB_wayInvalidate; - wire stageB_consistancyHazard; - wire when_DataCache_l820_1; - reg [0:0] stageB_dataColisions; - wire when_DataCache_l820_2; - reg stageB_unaligned; - wire when_DataCache_l820_3; - reg [0:0] stageB_waysHitsBeforeInvalidate; - wire [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - wire when_DataCache_l820_4; - reg [3:0] stageB_mask; - reg stageB_loaderValid; - wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_waitDone; - wire stageB_flusher_hold; - reg [6:0] stageB_flusher_counter; - wire when_DataCache_l850; - wire when_DataCache_l856; - reg stageB_flusher_start; - wire stageB_isAmo; - wire stageB_isAmoCached; - wire stageB_isExternalLsrc; - wire stageB_isExternalAmo; - wire [31:0] stageB_requestDataBypass; - reg stageB_cpuWriteToCache; - wire when_DataCache_l926; - wire stageB_badPermissions; - wire stageB_loadStoreFault; - wire stageB_bypassCache; - wire when_DataCache_l995; - wire when_DataCache_l1004; - wire when_DataCache_l1009; - wire when_DataCache_l1020; - wire when_DataCache_l1032; - wire when_DataCache_l991; - wire when_DataCache_l1066; - wire when_DataCache_l1075; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [3:0] loader_counter_valueNext; - reg [3:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - wire loader_kill; - reg loader_killReg; - wire when_DataCache_l1090; - wire loader_done; - wire when_DataCache_l1118; - reg loader_valid_regNext; - wire when_DataCache_l1122; - wire when_DataCache_l1125; - reg [21:0] ways_0_tags [0:63]; - reg [7:0] ways_0_data_symbol0 [0:1023]; - reg [7:0] ways_0_data_symbol1 [0:1023]; - reg [7:0] ways_0_data_symbol2 [0:1023]; - reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_ways_0_datasymbol_read; - reg [7:0] _zz_ways_0_datasymbol_read_1; - reg [7:0] _zz_ways_0_datasymbol_read_2; - reg [7:0] _zz_ways_0_datasymbol_read_3; - - assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_when = 1'b1; - assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; - assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; - assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_ways_0_tagsReadRsp_valid) begin - _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(*) begin - _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; - end - always @(posedge io_systemClk) begin - if(_zz_ways_0_dataReadRspMem) begin - _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @(posedge io_systemClk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(when_DataCache_l645) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(when_DataCache_l642) begin - _zz_2 = 1'b1; - end - end - - assign haltCpu = 1'b0; - assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; - assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; - assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; - assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; - assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; - assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); - assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); - always @(*) begin - tagsReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - tagsReadCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsReadCmd_payload = 6'bxxxxxx; - if(when_DataCache_l664) begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; - end - end - - always @(*) begin - dataReadCmd_valid = 1'b0; - if(when_DataCache_l664) begin - dataReadCmd_valid = 1'b1; - end - end - - always @(*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; - if(when_DataCache_l664) begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end - end - - always @(*) begin - tagsWriteCmd_valid = 1'b0; - if(when_DataCache_l850) begin - tagsWriteCmd_valid = 1'b1; - end - if(when_DataCache_l1066) begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - tagsWriteCmd_payload_way = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_way = 1'b1; - end - if(loader_done) begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - tagsWriteCmd_payload_address = 6'bxxxxxx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; - end - if(loader_done) begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; - end - end - - always @(*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(when_DataCache_l850) begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_done) begin - tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done) begin - tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); - end - end - - always @(*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; - if(loader_done) begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end - end - - always @(*) begin - dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache) begin - if(when_DataCache_l926) begin - dataWriteCmd_valid = 1'b1; - end - end - if(when_DataCache_l1066) begin - dataWriteCmd_valid = 1'b0; - end - if(when_DataCache_l1090) begin - dataWriteCmd_valid = 1'b1; - end - end - - always @(*) begin - dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_way = stageB_waysHits; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_way = loader_waysAllocator; - end - end - - always @(*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; - end - end - - always @(*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end - end - - always @(*) begin - dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache) begin - dataWriteCmd_payload_mask = 4'b0000; - if(_zz_when[0]) begin - dataWriteCmd_payload_mask[3 : 0] = stageB_mask; - end - end - if(when_DataCache_l1090) begin - dataWriteCmd_payload_mask = 4'b1111; - end - end - - assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - always @(*) begin - io_cpu_execute_haltIt = 1'b0; - if(when_DataCache_l850) begin - io_cpu_execute_haltIt = 1'b1; - end - end - - assign rspSync = 1'b1; - assign rspLast = 1'b1; - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); - always @(*) begin - _zz_stage0_mask = 4'bxxxx; - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_stage0_mask = 4'b0001; - end - 2'b01 : begin - _zz_stage0_mask = 4'b0011; - end - 2'b10 : begin - _zz_stage0_mask = 4'b1111; - end - default : begin - end - endcase - end - - assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stage0_wayInvalidate = 1'b0; - assign stage0_isAmo = 1'b0; - assign when_DataCache_l771 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_isAmo = 1'b0; - assign stageA_isLrsc = 1'b0; - assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); - assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); - assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); - assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_mmuRspFreeze = 1'b0; - if(when_DataCache_l1125) begin - stageB_mmuRspFreeze = 1'b1; - end - end - - assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); - assign stageB_consistancyHazard = 1'b0; - assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); - assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); - assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (|stageB_waysHits); - assign stageB_dataMux = stageB_dataReadRsp_0; - assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); - always @(*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - if(io_mem_cmd_ready) begin - stageB_loaderValid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - stageB_loaderValid = 1'b0; - end - end - - assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @(*) begin - io_cpu_writeBack_haltIt = 1'b1; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - if(when_DataCache_l995) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1009) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - - assign stageB_flusher_hold = 1'b0; - assign when_DataCache_l850 = (! stageB_flusher_counter[6]); - assign when_DataCache_l856 = (! stageB_flusher_hold); - assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); - assign stageB_isAmo = 1'b0; - assign stageB_isAmoCached = 1'b0; - assign stageB_isExternalLsrc = 1'b0; - assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = io_cpu_writeBack_storeData; - always @(*) begin - stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - stageB_cpuWriteToCache = 1'b1; - end - end - end - end - end - - assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); - assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); - assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @(*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(when_DataCache_l1004) begin - if(when_DataCache_l1020) begin - io_cpu_redo = 1'b1; - end - end - end - end - end - if(when_DataCache_l1075) begin - io_cpu_redo = 1'b1; - end - if(when_DataCache_l1122) begin - io_cpu_redo = 1'b1; - end - end - - always @(*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache) begin - io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); - end - end - - assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @(*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(when_DataCache_l991) begin - io_mem_cmd_valid = (! memCmdSent); - end else begin - if(when_DataCache_l1004) begin - if(stageB_request_wr) begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if(when_DataCache_l1032) begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - end - if(when_DataCache_l1066) begin - io_mem_cmd_valid = 1'b0; - end - end - - always @(*) begin - io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_address[5 : 0] = 6'h0; - end - end - end - end - end - - assign io_mem_cmd_payload_last = 1'b1; - always @(*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; - always @(*) begin - io_mem_cmd_payload_size = {1'd0, stageB_request_size}; - if(io_cpu_writeBack_isValid) begin - if(!stageB_isExternalAmo) begin - if(!when_DataCache_l991) begin - if(!when_DataCache_l1004) begin - io_mem_cmd_payload_size = 3'b110; - end - end - end - end - end - - assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); - assign io_cpu_writeBack_keepMemRspData = 1'b0; - assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); - assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); - assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); - assign when_DataCache_l1032 = (! memCmdSent); - assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - always @(*) begin - if(stageB_bypassCache) begin - io_cpu_writeBack_data = stageB_ioMemRspMuxed; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); - always @(*) begin - loader_counter_willIncrement = 1'b0; - if(when_DataCache_l1090) begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @(*) begin - loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); - if(loader_counter_willClear) begin - loader_counter_valueNext = 4'b0000; - end - end - - assign loader_kill = 1'b0; - assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign loader_done = loader_counter_willOverflow; - assign when_DataCache_l1118 = (! loader_valid); - assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); - assign io_cpu_execute_refilling = loader_valid; - assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); - always @(posedge io_systemClk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if(when_DataCache_l771) begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_size <= io_cpu_execute_args_size; - stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; - end - if(when_DataCache_l771_1) begin - stageA_mask <= stage0_mask; - end - if(when_DataCache_l771_2) begin - stageA_wayInvalidate <= stage0_wayInvalidate; - end - if(when_DataCache_l771_3) begin - stage0_dataColisions_regNextWhen <= stage0_dataColisions; - end - if(when_DataCache_l822) begin - stageB_request_wr <= stageA_request_wr; - stageB_request_size <= stageA_request_size; - stageB_request_totalyConsistent <= stageA_request_totalyConsistent; - end - if(when_DataCache_l824) begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; - stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; - stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; - end - if(when_DataCache_l821) begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if(when_DataCache_l821_1) begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if(when_DataCache_l820) begin - stageB_wayInvalidate <= stageA_wayInvalidate; - end - if(when_DataCache_l820_1) begin - stageB_dataColisions <= stageA_dataColisions; - end - if(when_DataCache_l820_2) begin - stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); - end - if(when_DataCache_l820_3) begin - stageB_waysHitsBeforeInvalidate <= stageA_wayHits; - end - if(when_DataCache_l820_4) begin - stageB_mask <= stageA_mask; - end - loader_valid_regNext <= loader_valid; - end - - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - memCmdSent <= 1'b0; - stageB_flusher_waitDone <= 1'b0; - stageB_flusher_counter <= 7'h0; - stageB_flusher_start <= 1'b1; - loader_valid <= 1'b0; - loader_counter_value <= 4'b0000; - loader_waysAllocator <= 1'b1; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end else begin - if(io_mem_cmd_fire) begin - memCmdSent <= 1'b1; - end - if(when_DataCache_l686) begin - memCmdSent <= 1'b0; - end - if(io_cpu_flush_ready) begin - stageB_flusher_waitDone <= 1'b0; - end - if(when_DataCache_l850) begin - if(when_DataCache_l856) begin - stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter[6] <= 1'b1; - end - end - end - stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start) begin - stageB_flusher_waitDone <= 1'b1; - stageB_flusher_counter <= 7'h0; - if(io_cpu_flush_payload_singleLine) begin - stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; - end - end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache.scala:L1077 - `else - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache.scala:L1077 - end - `endif - `endif - if(stageB_loaderValid) begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(loader_kill) begin - loader_killReg <= 1'b1; - end - if(when_DataCache_l1090) begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_done) begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - loader_killReg <= 1'b0; - end - if(when_DataCache_l1118) begin - loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; - end - end - end - - -endmodule - -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, - input io_cpu_fetch_mmuRsp_isIoAccess, - input io_cpu_fetch_mmuRsp_isPaging, - input io_cpu_fetch_mmuRsp_allowRead, - input io_cpu_fetch_mmuRsp_allowWrite, - input io_cpu_fetch_mmuRsp_allowExecute, - input io_cpu_fetch_mmuRsp_exception, - input io_cpu_fetch_mmuRsp_refilling, - input io_cpu_fetch_mmuRsp_bypassTranslation, - output [31:0] io_cpu_fetch_physicalAddress, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input io_systemClk, - input systemCd_logic_outputReset -); - - reg [31:0] _zz_banks_0_port1; - reg [21:0] _zz_ways_0_tags_port1; - wire [21:0] _zz_ways_0_tags_port; - reg _zz_1; - reg _zz_2; - reg lineLoader_fire; - reg lineLoader_valid; - (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; - wire when_InstructionCache_l338; - reg _zz_when_InstructionCache_l342; - wire when_InstructionCache_l342; - wire when_InstructionCache_l351; - reg lineLoader_cmdSent; - wire io_mem_cmd_fire; - wire when_Utils_l513; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; - wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire when_InstructionCache_l401; - wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; - wire _zz_fetchStage_read_banksValue_0_dataMem_1; - wire [31:0] fetchStage_read_banksValue_0_dataMem; - wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; - wire _zz_fetchStage_read_waysValues_0_tag_valid_1; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - wire when_InstructionCache_l435; - reg [31:0] io_cpu_fetch_data_regNextWhen; - wire when_InstructionCache_l459; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_isPaging; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_mmuRsp_bypassTranslation; - wire when_InstructionCache_l459_1; - reg decodeStage_hit_valid; - wire when_InstructionCache_l459_2; - reg decodeStage_hit_error; - reg [31:0] banks_0 [0:1023]; - reg [21:0] ways_0_tags [0:63]; - - assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @(posedge io_systemClk) begin - if(_zz_1) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin - _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; - end - end - - always @(posedge io_systemClk) begin - if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; - end - end - - always @(posedge io_systemClk) begin - if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin - _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; - end - end - - always @(*) begin - _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid) begin - _zz_1 = 1'b1; - end - end - - always @(*) begin - _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid) begin - _zz_2 = 1'b1; - end - end - - always @(*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid) begin - if(when_InstructionCache_l401) begin - lineLoader_fire = 1'b1; - end - end - end - - always @(*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(when_InstructionCache_l338) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(when_InstructionCache_l342) begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush) begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); - assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); - assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; - assign io_mem_cmd_payload_size = 3'b110; - assign when_Utils_l513 = (! lineLoader_valid); - always @(*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if(when_Utils_l513) begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end - end - - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; - assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); - assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; - assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; - assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; - assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); - assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; - assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; - assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; - assign fetchStage_hit_word = fetchStage_hit_data; - assign io_cpu_fetch_data = fetchStage_hit_word; - assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; - assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); - assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= 4'b0000; - end else begin - if(lineLoader_fire) begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire) begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid) begin - lineLoader_valid <= 1'b1; - end - if(io_flush) begin - lineLoader_flushPending <= 1'b1; - end - if(when_InstructionCache_l351) begin - lineLoader_flushPending <= 1'b0; - end - if(io_mem_cmd_fire) begin - lineLoader_cmdSent <= 1'b1; - end - if(lineLoader_fire) begin - lineLoader_cmdSent <= 1'b0; - end - if(io_mem_rsp_valid) begin - lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); - if(io_mem_rsp_payload_error) begin - lineLoader_hadError <= 1'b1; - end - end - end - end - - always @(posedge io_systemClk) begin - if(io_cpu_fill_valid) begin - lineLoader_address <= io_cpu_fill_payload; - end - if(when_InstructionCache_l338) begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); - end - _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; - if(when_InstructionCache_l351) begin - lineLoader_flushCounter <= 7'h0; - end - if(when_InstructionCache_l435) begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if(when_InstructionCache_l459) begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; - decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; - decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; - end - if(when_InstructionCache_l459_1) begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if(when_InstructionCache_l459_2) begin - decodeStage_hit_error <= fetchStage_hit_error; - end - end - - -endmodule - -module UartCtrlRx ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - output io_read_valid, - input io_read_ready, - output [7:0] io_read_payload, - input io_rxd, - output io_rts, - output reg io_error, - output io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlRxState_IDLE = 3'd0; - localparam UartCtrlRxState_START = 3'd1; - localparam UartCtrlRxState_DATA = 3'd2; - localparam UartCtrlRxState_PARITY = 3'd3; - localparam UartCtrlRxState_STOP = 3'd4; - - wire io_rxd_buffercc_io_dataOut; - wire _zz_sampler_value; - wire _zz_sampler_value_1; - wire _zz_sampler_value_2; - wire _zz_sampler_value_3; - wire _zz_sampler_value_4; - wire _zz_sampler_value_5; - wire _zz_sampler_value_6; - wire [2:0] _zz_when_UartCtrlRx_l139; - wire [0:0] _zz_when_UartCtrlRx_l139_1; - reg _zz_io_rts; - wire sampler_synchroniser; - wire sampler_samples_0; - reg sampler_samples_1; - reg sampler_samples_2; - reg sampler_samples_3; - reg sampler_samples_4; - reg sampler_value; - reg sampler_tick; - reg [2:0] bitTimer_counter; - reg bitTimer_tick; - wire when_UartCtrlRx_l43; - reg [2:0] bitCounter_value; - reg [6:0] break_counter; - wire break_valid; - wire when_UartCtrlRx_l69; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg [7:0] stateMachine_shifter; - reg stateMachine_validReg; - wire when_UartCtrlRx_l93; - wire when_UartCtrlRx_l103; - wire when_UartCtrlRx_l111; - wire when_UartCtrlRx_l113; - wire when_UartCtrlRx_l125; - wire when_UartCtrlRx_l136; - wire when_UartCtrlRx_l139; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; - assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); - assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); - assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); - assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); - assign _zz_sampler_value_6 = 1'b1; - assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); - assign _zz_sampler_value_2 = 1'b1; - BufferCC io_rxd_buffercc ( - .io_dataIn (io_rxd ), //i - .io_dataOut (io_rxd_buffercc_io_dataOut), //o - .io_systemClk (io_systemClk ), //i - .systemCd_logic_outputReset (systemCd_logic_outputReset) //i - ); - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlRxState_START : stateMachine_state_string = "START "; - UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - io_error = 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - end - UartCtrlRxState_START : begin - end - UartCtrlRxState_DATA : begin - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(!when_UartCtrlRx_l125) begin - io_error = 1'b1; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - io_error = 1'b1; - end - end - end - endcase - end - - assign io_rts = _zz_io_rts; - assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; - assign sampler_samples_0 = sampler_synchroniser; - always @(*) begin - bitTimer_tick = 1'b0; - if(sampler_tick) begin - if(when_UartCtrlRx_l43) begin - bitTimer_tick = 1'b1; - end - end - end - - assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); - assign break_valid = (break_counter == 7'h68); - assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); - assign io_break = break_valid; - assign io_read_valid = stateMachine_validReg; - assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); - assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); - assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); - assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); - assign when_UartCtrlRx_l136 = (! sampler_value); - assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); - assign io_read_payload = stateMachine_shifter; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - _zz_io_rts <= 1'b0; - sampler_samples_1 <= 1'b1; - sampler_samples_2 <= 1'b1; - sampler_samples_3 <= 1'b1; - sampler_samples_4 <= 1'b1; - sampler_value <= 1'b1; - sampler_tick <= 1'b0; - break_counter <= 7'h0; - stateMachine_state <= UartCtrlRxState_IDLE; - stateMachine_validReg <= 1'b0; - end else begin - _zz_io_rts <= (! io_read_ready); - if(io_samplingTick) begin - sampler_samples_1 <= sampler_samples_0; - end - if(io_samplingTick) begin - sampler_samples_2 <= sampler_samples_1; - end - if(io_samplingTick) begin - sampler_samples_3 <= sampler_samples_2; - end - if(io_samplingTick) begin - sampler_samples_4 <= sampler_samples_3; - end - sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); - sampler_tick <= io_samplingTick; - if(sampler_value) begin - break_counter <= 7'h0; - end else begin - if(when_UartCtrlRx_l69) begin - break_counter <= (break_counter + 7'h01); - end - end - stateMachine_validReg <= 1'b0; - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - stateMachine_state <= UartCtrlRxState_START; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - stateMachine_state <= UartCtrlRxState_DATA; - if(when_UartCtrlRx_l103) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l111) begin - if(when_UartCtrlRx_l113) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_PARITY; - end - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l125) begin - stateMachine_state <= UartCtrlRxState_STOP; - stateMachine_validReg <= 1'b1; - end else begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - default : begin - if(bitTimer_tick) begin - if(when_UartCtrlRx_l136) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end else begin - if(when_UartCtrlRx_l139) begin - stateMachine_state <= UartCtrlRxState_IDLE; - end - end - end - end - endcase - end - end - - always @(posedge io_systemClk) begin - if(sampler_tick) begin - bitTimer_counter <= (bitTimer_counter - 3'b001); - end - if(bitTimer_tick) begin - bitCounter_value <= (bitCounter_value + 3'b001); - end - if(bitTimer_tick) begin - stateMachine_parity <= (stateMachine_parity ^ sampler_value); - end - case(stateMachine_state) - UartCtrlRxState_IDLE : begin - if(when_UartCtrlRx_l93) begin - bitTimer_counter <= 3'b010; - end - end - UartCtrlRxState_START : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - end - end - UartCtrlRxState_DATA : begin - if(bitTimer_tick) begin - stateMachine_shifter[bitCounter_value] <= sampler_value; - if(when_UartCtrlRx_l111) begin - bitCounter_value <= 3'b000; - end - end - end - UartCtrlRxState_PARITY : begin - if(bitTimer_tick) begin - bitCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module UartCtrlTx ( - input [2:0] io_configFrame_dataLength, - input [0:0] io_configFrame_stop, - input [1:0] io_configFrame_parity, - input io_samplingTick, - input io_write_valid, - output reg io_write_ready, - input [7:0] io_write_payload, - input io_cts, - output io_txd, - input io_break, - input io_systemClk, - input systemCd_logic_outputReset -); - localparam UartStopType_ONE = 1'd0; - localparam UartStopType_TWO = 1'd1; - localparam UartParityType_NONE = 2'd0; - localparam UartParityType_EVEN = 2'd1; - localparam UartParityType_ODD = 2'd2; - localparam UartCtrlTxState_IDLE = 3'd0; - localparam UartCtrlTxState_START = 3'd1; - localparam UartCtrlTxState_DATA = 3'd2; - localparam UartCtrlTxState_PARITY = 3'd3; - localparam UartCtrlTxState_STOP = 3'd4; - - wire [2:0] _zz_clockDivider_counter_valueNext; - wire [0:0] _zz_clockDivider_counter_valueNext_1; - wire [2:0] _zz_when_UartCtrlTx_l93; - wire [0:0] _zz_when_UartCtrlTx_l93_1; - reg clockDivider_counter_willIncrement; - wire clockDivider_counter_willClear; - reg [2:0] clockDivider_counter_valueNext; - reg [2:0] clockDivider_counter_value; - wire clockDivider_counter_willOverflowIfInc; - wire clockDivider_counter_willOverflow; - reg [2:0] tickCounter_value; - reg [2:0] stateMachine_state; - reg stateMachine_parity; - reg stateMachine_txd; - wire when_UartCtrlTx_l58; - wire when_UartCtrlTx_l73; - wire when_UartCtrlTx_l76; - wire when_UartCtrlTx_l93; - reg _zz_io_txd; - `ifndef SYNTHESIS - reg [23:0] io_configFrame_stop_string; - reg [31:0] io_configFrame_parity_string; - reg [47:0] stateMachine_state_string; - `endif - - - assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; - assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; - assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); - assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; - `ifndef SYNTHESIS - always @(*) begin - case(io_configFrame_stop) - UartStopType_ONE : io_configFrame_stop_string = "ONE"; - UartStopType_TWO : io_configFrame_stop_string = "TWO"; - default : io_configFrame_stop_string = "???"; - endcase - end - always @(*) begin - case(io_configFrame_parity) - UartParityType_NONE : io_configFrame_parity_string = "NONE"; - UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; - UartParityType_ODD : io_configFrame_parity_string = "ODD "; - default : io_configFrame_parity_string = "????"; - endcase - end - always @(*) begin - case(stateMachine_state) - UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; - UartCtrlTxState_START : stateMachine_state_string = "START "; - UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; - UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; - UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; - default : stateMachine_state_string = "??????"; - endcase - end - `endif - - always @(*) begin - clockDivider_counter_willIncrement = 1'b0; - if(io_samplingTick) begin - clockDivider_counter_willIncrement = 1'b1; - end - end - - assign clockDivider_counter_willClear = 1'b0; - assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); - assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); - always @(*) begin - clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); - if(clockDivider_counter_willClear) begin - clockDivider_counter_valueNext = 3'b000; - end - end - - always @(*) begin - stateMachine_txd = 1'b1; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - stateMachine_txd = 1'b0; - end - UartCtrlTxState_DATA : begin - stateMachine_txd = io_write_payload[tickCounter_value]; - end - UartCtrlTxState_PARITY : begin - stateMachine_txd = stateMachine_parity; - end - default : begin - end - endcase - end - - always @(*) begin - io_write_ready = io_break; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - io_write_ready = 1'b1; - end - end - end - UartCtrlTxState_PARITY : begin - end - default : begin - end - endcase - end - - assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); - assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); - assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); - assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); - assign io_txd = _zz_io_txd; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - clockDivider_counter_value <= 3'b000; - stateMachine_state <= UartCtrlTxState_IDLE; - _zz_io_txd <= 1'b1; - end else begin - clockDivider_counter_value <= clockDivider_counter_valueNext; - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - if(when_UartCtrlTx_l58) begin - stateMachine_state <= UartCtrlTxState_START; - end - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_DATA; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - if(when_UartCtrlTx_l76) begin - stateMachine_state <= UartCtrlTxState_STOP; - end else begin - stateMachine_state <= UartCtrlTxState_PARITY; - end - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_state <= UartCtrlTxState_STOP; - end - end - default : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l93) begin - stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); - end - end - end - endcase - _zz_io_txd <= (stateMachine_txd && (! io_break)); - end - end - - always @(posedge io_systemClk) begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= (tickCounter_value + 3'b001); - end - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); - end - case(stateMachine_state) - UartCtrlTxState_IDLE : begin - end - UartCtrlTxState_START : begin - if(clockDivider_counter_willOverflow) begin - stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); - tickCounter_value <= 3'b000; - end - end - UartCtrlTxState_DATA : begin - if(clockDivider_counter_willOverflow) begin - if(when_UartCtrlTx_l73) begin - tickCounter_value <= 3'b000; - end - end - end - UartCtrlTxState_PARITY : begin - if(clockDivider_counter_willOverflow) begin - tickCounter_value <= 3'b000; - end - end - default : begin - end - endcase - end - - -endmodule - -module BufferCC_1 ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input debugCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - initial begin - `ifndef SYNTHESIS - buffers_0 = $urandom; - buffers_1 = $urandom; - `endif - end - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - - -endmodule - -module BufferCC ( - input io_dataIn, - output io_dataOut, - input io_systemClk, - input systemCd_logic_outputReset -); - - (* async_reg = "true" *) reg buffers_0; - (* async_reg = "true" *) reg buffers_1; - - assign io_dataOut = buffers_1; - always @(posedge io_systemClk) begin - if(systemCd_logic_outputReset) begin - buffers_0 <= 1'b0; - buffers_1 <= 1'b0; - end else begin - buffers_0 <= io_dataIn; - buffers_1 <= buffers_0; - end - end - - -endmodule diff --git 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"/projects/SSE/kmlau/install/efinity/2022.1/ipm/ip/efx_soc/efx_soc/generator/bootloader/bootloader_32K.hex" ---cpuCount 1 ---spi name=system_spi_0_io,address=0x014000,interruptId=4,width=8,ssCount=1 ---Fpu false ---uart name=system_uart_0_io,address=0x010000,interruptId=1 ---L1I true ---dCacheSize 4096 ---axiAEnable false ---onChipRamSize 0x8000 ---iCacheWays 1 ---apbSlave name=io_apbSlave_0,address=0x100000,size=65536 ---ddrAEnable false ---iCacheSize 4096 ---onChipRamAddress 0xf9000000 ---Atomic false ---PeripheralClock false ---softTap false ---customInstruction false ---apbBridgeAddress 0xf8000000 ---L1D true ---Linux false ---dCacheWays 1 ---systemFrequency 50000000 diff --git a/fpga/ip/gTSE/Ti60F225_devkit/mac_pat_gen.v b/fpga/ip/gTSE/Ti60F225_devkit/mac_pat_gen.v deleted file mode 100644 index 64c5fed..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/mac_pat_gen.v +++ /dev/null @@ -1,241 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module mac_pat_gen -( -//Globle Signals -input clk, -input rstn, -//Control Interface -input pat_gen_en, -input [15:0] pat_gen_num,//When value is 0, it's infinite mode -input [15:0] pat_gen_ipg, -//MAC Protocol Signals -input [47:0] dst_mac, -input [47:0] src_mac, -input [15:0] mac_dlen, -//AXI4-Stream Interface -input rclk, -input rrstn, -input [7:0] rdata, -input rvalid, -input rlast, - -output reg [7:0] tdata, -output reg tvalid, -output reg tlast, -input tready -); - -// Parameter Define -localparam IDLE = 2'h0; -localparam PAT_IPG = 2'h1; -localparam PAT_GEN = 2'h2; - -// Register Define -reg pat_gen_en_dl1; -reg pat_gen_en_dl2; -reg [1:0] cur_state; -reg [1:0] next_state; -reg pat_en; -reg infinite_en; -reg [15:0] num_cnt; -reg [15:0] ipg_cnt; -reg [15:0] pat_cnt; - -reg [15:0] pat_gen_num_r; -reg [15:0] pat_gen_ipg_r; -reg [47:0] dst_mac_r; -reg [47:0] src_mac_r; -reg [15:0] mac_dlen_r; - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) begin - pat_gen_num_r <= 16'h0; - pat_gen_ipg_r <= 16'h0; - dst_mac_r <= 48'h0; - src_mac_r <= 48'h0; - mac_dlen_r <= 16'h0; - end - else begin - pat_gen_num_r <= pat_gen_num; - pat_gen_ipg_r <= pat_gen_ipg; - dst_mac_r <= dst_mac; - src_mac_r <= src_mac; - mac_dlen_r <= mac_dlen; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - pat_gen_en_dl1 <= 1'h0; - pat_gen_en_dl2 <= 1'h0; - end - else - begin - pat_gen_en_dl1 <= pat_gen_en; - pat_gen_en_dl2 <= pat_gen_en_dl1; - end -end - -/*----------------------- FSM Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - cur_state <= IDLE; - else - cur_state <= next_state; -end - -always @(*) - begin - case(cur_state) - IDLE : - if(pat_en == 1'b1) - next_state = PAT_GEN; - else - next_state = IDLE; - - PAT_IPG : - if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) - next_state = IDLE; - else if(ipg_cnt == pat_gen_ipg_r) - next_state = PAT_GEN; - else - next_state = PAT_IPG; - - PAT_GEN : - if((tlast == 1'b1) && (tready == 1'b1)) - next_state = PAT_IPG; - else - next_state = PAT_GEN; - - default : - next_state = IDLE; - endcase - end - -/*----------------------- Generator Control Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - pat_en <= 1'h1; - else if((cur_state == IDLE) && (pat_en == 1'b1)) - pat_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - infinite_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) - infinite_en <= 1'h1; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - infinite_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - num_cnt <= 16'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - num_cnt <= pat_gen_num_r; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) - num_cnt <= num_cnt - 1'b1; -end - -/*----------------------- Pattern Counter Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ipg_cnt <= 16'h0; - else if(cur_state == PAT_IPG) - ipg_cnt <= ipg_cnt + 1'b1; - else - ipg_cnt <= 8'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_cnt <= 16'h0; - else if(cur_state != PAT_GEN) - pat_cnt <= 16'h0; - else if(tready == 1'b1) - pat_cnt <= pat_cnt + 1'b1; -end - -/*----------------------- Pattern Generator Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tvalid <= 1'b0; - else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) - tvalid <= 1'b1; - else if((tready == 1'b1) && (tlast == 1'b1)) - tvalid <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tdata <= 8'h0; - else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd14)) - case(pat_cnt[3:0]) - 4'd0 : tdata <= dst_mac_r[5*8 +: 8]; - 4'd1 : tdata <= dst_mac_r[4*8 +: 8]; - 4'd2 : tdata <= dst_mac_r[3*8 +: 8]; - 4'd3 : tdata <= dst_mac_r[2*8 +: 8]; - 4'd4 : tdata <= dst_mac_r[1*8 +: 8]; - 4'd5 : tdata <= dst_mac_r[0*8 +: 8]; - 4'd6 : tdata <= src_mac_r[5*8 +: 8]; - 4'd7 : tdata <= src_mac_r[4*8 +: 8]; - 4'd8 : tdata <= src_mac_r[3*8 +: 8]; - 4'd9 : tdata <= src_mac_r[2*8 +: 8]; - 4'd10 : tdata <= src_mac_r[1*8 +: 8]; - 4'd11 : tdata <= src_mac_r[0*8 +: 8]; - 4'd12 : tdata <= mac_dlen_r[15:8]; - 4'd13 : tdata <= mac_dlen_r[7:0]; - 4'd14 : tdata <= 8'h0;//MAC First Data - default : tdata <= tdata + 1'b1; - endcase - else if((cur_state == PAT_GEN) && (tready == 1'b1)) - tdata <= tdata + 1'b1; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tlast <= 1'b0; - else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == mac_dlen_r+16'd13)) - tlast <= 1'b1; - else if(tready == 1'b1) - tlast <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/mac_rx2tx.v b/fpga/ip/gTSE/Ti60F225_devkit/mac_rx2tx.v deleted file mode 100644 index 14508a7..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/mac_rx2tx.v +++ /dev/null @@ -1,139 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module mac_rx2tx -( -//Globle Signals -// -//Receive AXI4-Stream Interface -input rx_axis_clk, -input rx_axis_rstn, -input [7:0] rx_axis_mac_tdata, -input rx_axis_mac_tvalid, -input rx_axis_mac_tlast, -input rx_axis_mac_tuser, -output reg rx_axis_mac_tready, -//Transmit AXI4-Stream Interface -input tx_axis_clk, -input tx_axis_rstn, -output reg [7:0] tx_axis_mac_tdata, -output reg tx_axis_mac_tvalid, -output reg tx_axis_mac_tlast, -output reg tx_axis_mac_tuser, -input tx_axis_mac_tready -); -// Parameter Define - -// Register Define - -// Wire Define -wire [9:0] u1_data; -wire u1_wrreq; -wire u1_rdreq; -wire [9:0] u1_q; -wire u1_empty; -wire u1_almfull; -wire [10:0] u1_wrcnt; - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ - -/*----------------------- Rx Clock Region ----------------------------*/ -assign u1_almfull = (u1_wrcnt >= 2045); - -always @(posedge rx_axis_clk or negedge rx_axis_rstn) -begin - if(rx_axis_rstn == 1'b0) - rx_axis_mac_tready <= 1'b0; - else if(u1_almfull == 1'b1) - rx_axis_mac_tready <= 1'b0; - else - rx_axis_mac_tready <= 1'b1; -end - -/*----------------------- Fifo 1 Region ----------------------------*/ -DC_FIFO #( - .FIFO_MODE ("ShowAhead" ), - .DATA_WIDTH (10 ), - .FIFO_DEPTH (2048 ) -) -u1 -( - //System Signal - .Reset (!rx_axis_rstn ), - //Write Signal - .WrClk (rx_axis_clk ), - .WrEn (u1_wrreq ), - .WrDNum (u1_wrcnt ), - .WrFull ( ), - .WrData (u1_data ), - //Read Signal - .RdClk (tx_axis_clk ), - .RdEn (u1_rdreq ), - .RdDNum ( ), - .RdEmpty (u1_empty ), - .RdData (u1_q ) -); - -assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata}; -assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1); -assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1)); - -/*----------------------- Tx Clock Region ----------------------------*/ - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tvalid <= 1'b0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tvalid <= 1'b1; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tvalid <= 1'b0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tdata <= 8'h0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tdata <= u1_q[7:0]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tdata <= 8'h0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tlast <= 1'b0; - else if(u1_rdreq == 1'b1) - tx_axis_mac_tlast <= u1_q[8]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tlast <= 1'b0; -end - -always @(posedge tx_axis_clk or negedge tx_axis_rstn) -begin - if(tx_axis_rstn == 1'b0) - tx_axis_mac_tuser <= 1'b0; - else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1)) - tx_axis_mac_tuser <= u1_q[9]; - else if(tx_axis_mac_tready == 1'b1) - tx_axis_mac_tuser <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/reg_apb3.v b/fpga/ip/gTSE/Ti60F225_devkit/reg_apb3.v deleted file mode 100644 index 3447897..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/reg_apb3.v +++ /dev/null @@ -1,333 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module reg_apb3#( - parameter ADDR_WTH = 10 -) -( -//Globle Signals -// -//APB3 Slave Interface -input s_apb3_clk, -input s_apb3_rstn, -input [ADDR_WTH-1:0] s_apb3_paddr, -input s_apb3_psel, -input s_apb3_penable, -output reg s_apb3_pready, -input s_apb3_pwrite,//0:rd; 1:wr; -input [31:0] s_apb3_pwdata, -output reg [31:0] s_apb3_prdata, -output wire s_apb3_pslverror, -//Cfg Space Registers -//--Example Registers Field -output reg mac_sw_rst, -output reg axi4_st_mux_select, -output reg pat_mux_select, -output reg udp_pat_gen_en, -output reg mac_pat_gen_en, -output reg [15:0] pat_gen_num, -output reg [15:0] pat_gen_ipg, -output reg [47:0] pat_dst_mac, -output reg [47:0] pat_src_mac, -output reg [15:0] pat_mac_dlen, -output reg [31:0] pat_src_ip, -output reg [31:0] pat_dst_ip, -output reg [15:0] pat_src_port, -output reg [15:0] pat_dst_port, -output reg [15:0] pat_udp_dlen, -output reg [1:0] clkmux_sel -); -// Parameter Define - -// Register Define -reg [ADDR_WTH-3:0] loc_addr; -reg loc_wr_vld; -reg loc_rd_vld; - -// Wire Define - -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -//apb3 interface -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - loc_addr <= {ADDR_WTH-2{1'b0}}; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) - loc_addr <= s_apb3_paddr[2+:ADDR_WTH-2]; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - loc_wr_vld <= 1'b0; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) - loc_wr_vld <= 1'b1; - else - loc_wr_vld <= 1'b0; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - loc_rd_vld <= 1'b0; - else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) - loc_rd_vld <= 1'b1; - else - loc_rd_vld <= 1'b0; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - s_apb3_pready <= 1'b0; - else if((loc_wr_vld == 1'b1) || (loc_rd_vld == 1'b1)) - s_apb3_pready <= 1'b1; - else - s_apb3_pready <= 1'b0; -end - -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - s_apb3_prdata <= 32'h0; - else if(loc_rd_vld == 1'b1) - begin - case(loc_addr) - //Example Registers Field - 'h080 : s_apb3_prdata <= {31'h0,mac_sw_rst}; - 'h081 : s_apb3_prdata <= {30'h0,pat_mux_select,axi4_st_mux_select}; - 'h082 : s_apb3_prdata <= {30'h0,mac_pat_gen_en,udp_pat_gen_en}; - 'h083 : s_apb3_prdata <= {pat_gen_ipg,pat_gen_num}; - 'h084 : s_apb3_prdata <= pat_dst_mac[31:0]; - 'h085 : s_apb3_prdata <= {16'h0,pat_dst_mac[47:32]}; - 'h086 : s_apb3_prdata <= pat_src_mac[31:0]; - 'h087 : s_apb3_prdata <= {16'h0,pat_src_mac[47:32]}; - 'h088 : s_apb3_prdata <= {16'h0,pat_mac_dlen}; - 'h089 : s_apb3_prdata <= pat_src_ip; - 'h08a : s_apb3_prdata <= pat_dst_ip; - 'h08b : s_apb3_prdata <= {pat_dst_port,pat_src_port}; - 'h08c : s_apb3_prdata <= {16'h0,pat_udp_dlen}; - 'h08d : s_apb3_prdata <= {30'h0,clkmux_sel}; - endcase - end -end - -assign s_apb3_pslverror = 1'b0; - -/*----------------------------------------------------------------------------------*\ - Register Space -- Example Registers Field -\*----------------------------------------------------------------------------------*/ -//loc_addr = 0x080; axi_addr = 0x200; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - mac_sw_rst <= 1'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h080)) - begin - mac_sw_rst <= s_apb3_pwdata[0]; - end -end - -//loc_addr = 0x081; axi_addr = 0x204; RW; -//[axi4_st_mux_select] 0:pat tx mode; 1:rx2tx loopback mode; -//[pat_mux_select] 0:udp pat; 1:mac pat; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - axi4_st_mux_select <= 1'h0; - pat_mux_select <= 1'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h081)) - begin - axi4_st_mux_select <= s_apb3_pwdata[0]; - pat_mux_select <= s_apb3_pwdata[1]; - end -end - -//loc_addr = 0x082; axi_addr = 0x208; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - udp_pat_gen_en <= 1'h0; - mac_pat_gen_en <= 1'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h082)) - begin - udp_pat_gen_en <= s_apb3_pwdata[0]; - mac_pat_gen_en <= s_apb3_pwdata[1]; - end -end - -//loc_addr = 0x083; axi_addr = 0x20c; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_gen_num <= 16'h0; - pat_gen_ipg <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h083)) - begin - pat_gen_num <= s_apb3_pwdata[15:0]; - pat_gen_ipg <= s_apb3_pwdata[31:16]; - end -end - -//loc_addr = 0x084; axi_addr = 0x210; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_dst_mac[31:0] <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h084)) - begin - pat_dst_mac[31:0] <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x085; axi_addr = 0x214; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_dst_mac[47:32] <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h085)) - begin - pat_dst_mac[47:32] <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x086; axi_addr = 0x218; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_mac[31:0] <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h086)) - begin - pat_src_mac[31:0] <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x087; axi_addr = 0x21c; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_mac[47:32] <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h087)) - begin - pat_src_mac[47:32] <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x088; axi_addr = 0x220; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_mac_dlen <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h088)) - begin - pat_mac_dlen <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x089; axi_addr = 0x224; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_ip <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h089)) - begin - pat_src_ip <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x08a; axi_addr = 0x228; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_dst_ip <= 32'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08a)) - begin - pat_dst_ip <= s_apb3_pwdata[31:0]; - end -end - -//loc_addr = 0x08b; axi_addr = 0x22c; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_src_port <= 16'h0; - pat_dst_port <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08b)) - begin - pat_src_port <= s_apb3_pwdata[15:0]; - pat_dst_port <= s_apb3_pwdata[31:16]; - end -end - -//loc_addr = 0x08c; axi_addr = 0x230; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - pat_udp_dlen <= 16'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08c)) - begin - pat_udp_dlen <= s_apb3_pwdata[15:0]; - end -end - -//loc_addr = 0x08d; axi_addr = 0x234; RW; -always @(posedge s_apb3_clk or negedge s_apb3_rstn) -begin - if(s_apb3_rstn == 1'b0) - begin - clkmux_sel <= 2'h0; - end - else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08d)) - begin - clkmux_sel <= s_apb3_pwdata[1:0]; - end -end - - -/*----------------------------------------------------------------------------------*\ - Register Space -- The End -\*----------------------------------------------------------------------------------*/ - -endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/rgmii_2_rmii.v b/fpga/ip/gTSE/Ti60F225_devkit/rgmii_2_rmii.v deleted file mode 100644 index e7a1f19..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/rgmii_2_rmii.v +++ /dev/null @@ -1,206 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`timescale 1 ns / 1 ns -module rgmii_2_rmii ( - input clk_50m, //50Mhz refclock - input rst_n, - //conduit - input [2:0] eth_speed, - //rgmii interface - input [3:0] rgmii_txd, - input rgmii_tx_ctl, - output wire [3:0] rgmii_rxd, - output wire rgmii_rx_ctl, - output reg rgmii_rxc, - //rmii interface - output wire rmii_clk, - output reg [1:0] rmii_txd, - output reg rmii_txen, - input [1:0] rmii_rxd, - input rmii_crsdv -); - -wire [3:0] rxd_c; -wire rx_ctl_c; -reg [3:0] rxd_r; -reg rx_ctl_r; -reg rmii_crsdv_r, shift_en; -reg [4:0] txd_cnt, rxd_cnt; -reg [3:0] rxd_shiftreg; -reg [1:0] shift2; -reg [19:0] shift20; -reg [1:0] rx_ctl_p2; -reg [19:0] rx_ctl_p20; - -assign rmii_clk = ~clk_50m; //create 180deg phaseshift - -/*--------------- TX path ---------------------*/ -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - txd_cnt <= 5'd0; - end - else if (rgmii_tx_ctl) begin - if (((eth_speed == 3'h2) && txd_cnt == 5'd1) || - ((eth_speed == 3'h1) && txd_cnt == 5'd19)) begin - txd_cnt <= 5'd0; - end - else begin - txd_cnt <= txd_cnt + 5'd1; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rmii_txen <= 1'b0; - end - else begin - rmii_txen <= rgmii_tx_ctl; - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rmii_txd <= 2'b00; - end - else begin - if ((eth_speed == 3'h2) && txd_cnt == 5'd0) begin - rmii_txd <= rgmii_txd[1:0]; - end - else if ((eth_speed == 3'h2) && txd_cnt == 5'd1) begin - rmii_txd <= rgmii_txd[3:2]; - end - - if ((eth_speed == 3'h1) && txd_cnt == 5'd0) begin - rmii_txd <= rgmii_txd[1:0]; - end - else if ((eth_speed == 3'h1) && txd_cnt == 5'd10) begin - rmii_txd <= rgmii_txd[3:2]; - end - end -end -/*------------------ end of TX path ------------------------*/ - -/*------------ RX path ------------------*/ -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rxd_cnt <= 5'd0; - end - else if (rmii_crsdv) begin - if (((eth_speed == 3'h2) && rxd_cnt == 5'd1) || ((eth_speed == 3'h1) && rxd_cnt == 5'd19)) begin - rxd_cnt <= 5'd0; - end - else begin - rxd_cnt <= rxd_cnt + 5'd1; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rxd_shiftreg <= 4'd0; - end - else if (rmii_crsdv) begin - if (eth_speed == 3'h2 || ((eth_speed == 3'h1) && (rxd_cnt == 5'd0 || rxd_cnt == 5'd10))) begin - rxd_shiftreg <= {rmii_rxd, rxd_shiftreg[3:2]}; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - shift2 <= 2'b1; - shift20 <= 20'b1; - end - else begin - shift2 <= {shift2[0],shift2[1]}; - shift20 <= {shift20[18:0],shift20[19]}; - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rgmii_rxc <= 1'b0; - end - else begin - if ((eth_speed == 3'h2 && shift2[1]) || (eth_speed == 3'h1 && (shift20[10]))) begin - rgmii_rxc <= 1'b1; - end - else if ((eth_speed == 3'h2 && shift2[0]) || (eth_speed == 3'h1 && (shift20[0]))) begin - rgmii_rxc <= 1'b0; - end - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rx_ctl_p2 <= 2'd0; - rx_ctl_p20 <= 20'd0; - end - else begin - rx_ctl_p2 <= {rmii_crsdv , rx_ctl_p2[1]}; - rx_ctl_p20 <= {rmii_crsdv, rx_ctl_p20[19:1]}; - end -end - -/*---- shift rxd & rx_ctl so that they are not edge align with rgmii_rxc ----*/ -assign rxd_c = (rxd_cnt == 5'd0) ? rxd_shiftreg : rxd_r; -assign rx_ctl_c = (eth_speed == 3'h2) ? rx_ctl_p2[0] : rx_ctl_p20[0]; - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - rxd_r <= 4'd0; - rx_ctl_r <= 1'd0; - rmii_crsdv_r <= 1'd0; - end - else begin - rxd_r <= rxd_c; - rx_ctl_r <= rx_ctl_c; - rmii_crsdv_r <= rmii_crsdv; - end -end - -always @(posedge clk_50m or negedge rst_n) -begin - if (!rst_n) begin - shift_en <= 1'd0; - end // to detect if rmii_crsdv assert at the posedge of rgmii_rxc, delay rgmii_rxd & rgmii_rx_ctl if they are aligned with rgmii_rxc - else if (rmii_crsdv && ~rmii_crsdv_r) begin - if (((eth_speed == 3'h2) && shift2[0]) || ((eth_speed == 3'h1) && shift20[11])) begin - shift_en <= 1'd1; - end - else begin - shift_en <= 1'd0; - end - end -end - -assign rgmii_rxd = shift_en ? rxd_r : rxd_c; -assign rgmii_rx_ctl = shift_en ? rx_ctl_r : rx_ctl_c; -/*--------------------------------------------------------*/ -/*------------------ end of RX path ------------------------*/ -endmodule \ No newline at end of file diff --git a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.peri.xml b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.peri.xml deleted file mode 100644 index bb6a41a..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.peri.xml +++ /dev/null @@ -1,231 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.v b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.v deleted file mode 100644 index 15d4a24..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.v +++ /dev/null @@ -1,563 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -//`include "header.v" // use JTAG hard block -module temac_ex -( -//Globle Signals -//----pll_0 -input clk, -input clk_125m, -input pll_0_locked, -input sw6, -output wire pll_rstn, - -//TEMAC PHY RGMII Interface -output wire [3:0] rgmii_txd_HI, -output wire [3:0] rgmii_txd_LO, -output wire rgmii_txc_HI, -output wire rgmii_txc_LO, -input [3:0] rgmii_rxd_HI, -input [3:0] rgmii_rxd_LO, -`ifdef TITANIUM - output wire rgmii_tx_ctl_HI, - output wire rgmii_tx_ctl_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input mux_clk, - output [1:0] mux_clk_sw, -`else - input rgmii_rxc, - output wire rgmii_tx_ctl, - input rgmii_rx_ctl, -`endif -//TEMAC PHY Ctr Interface -output wire phy_rstn, -//hardware Jtag Interface -`ifndef SIM_MODE -`ifndef SOFT_TAP -input jtag_inst1_TCK, -input jtag_inst1_TDI, -output wire jtag_inst1_TDO, -input jtag_inst1_SEL, -input jtag_inst1_CAPTURE, -input jtag_inst1_SHIFT, -input jtag_inst1_UPDATE, -input jtag_inst1_RESET, -`else -//software Jtag Interface -input io_jtag_tms, -input io_jtag_tdi, -output wire io_jtag_tdo, -input io_jtag_tck, -`endif - -//Debug Signals -//output wire [1:0] debug_led -output wire system_uart_0_io_txd, -input system_uart_0_io_rxd, -`endif - -output system_spi_0_io_sclk_write, -output system_spi_0_io_data_0_writeEnable, -input system_spi_0_io_data_0_read, -output system_spi_0_io_data_0_write, -output system_spi_0_io_data_1_writeEnable, -input system_spi_0_io_data_1_read, -output system_spi_0_io_data_1_write, -output system_spi_0_io_ss, - -//TEMAC PHY MDIO Interface -input phy_mdi, -output wire phy_mdo, -output wire phy_mdo_en, -output wire phy_mdc -); -// Parameter Define -`include "gTSE_define.svh" - -// Register Define - -// Wire Define -wire clk_50m; -wire clk_50m_rstn; -wire mac_reset; -wire proto_reset; -wire mac_rstn; -//AXI4-Stream Interface -wire rx_axis_clk; -wire [7:0] rx_axis_mac_tdata; -wire rx_axis_mac_tvalid; -wire rx_axis_mac_tlast; -wire rx_axis_mac_tuser; -wire rx_axis_mac_tready; -wire tx_axis_clk; -wire [7:0] tx_axis_mac_tdata; -wire tx_axis_mac_tvalid; -wire tx_axis_mac_tlast; -wire tx_axis_mac_tuser; -wire tx_axis_mac_tready; -wire [7:0] udp_tx_axis_mac_tdata; -wire udp_tx_axis_mac_tvalid; -wire udp_tx_axis_mac_tlast; -wire udp_tx_axis_mac_tready; -wire [7:0] mac_tx_axis_mac_tdata; -wire mac_tx_axis_mac_tvalid; -wire mac_tx_axis_mac_tlast; -wire mac_tx_axis_mac_tready; -wire [7:0] pat_tx_axis_mac_tdata; -wire pat_tx_axis_mac_tvalid; -wire pat_tx_axis_mac_tlast; -wire pat_tx_axis_mac_tuser; -wire pat_tx_axis_mac_tready; -wire [7:0] loop_tx_axis_mac_tdata; -wire loop_tx_axis_mac_tvalid; -wire loop_tx_axis_mac_tlast; -wire loop_tx_axis_mac_tuser; -wire loop_tx_axis_mac_tready; -//RiscV APB3 Interface -wire [15:0] apb3_paddr; -wire apb3_psel; -wire apb3_penable; -wire apb3_pready; -wire apb3_pwrite; -wire [31:0] apb3_pwdata; -wire [31:0] apb3_prdata; -wire apb3_pslverror; -//Mac APB3 Interface -wire [9:0] mac_apb3_paddr; -wire mac_apb3_psel; -wire mac_apb3_penable; -wire mac_apb3_pready; -wire mac_apb3_pwrite; -wire [31:0] mac_apb3_pwdata; -wire [31:0] mac_apb3_prdata; -wire mac_apb3_pslverror; -//Ex APB3 Interface -wire [9:0] ex_apb3_paddr; -wire ex_apb3_psel; -wire ex_apb3_penable; -wire ex_apb3_pready; -wire ex_apb3_pwrite; -wire [31:0] ex_apb3_pwdata; -wire [31:0] ex_apb3_prdata; -wire ex_apb3_pslverror; -//AXI4-Lite Interface -wire [9:0] axi_awaddr; -wire axi_awvalid; -wire axi_awready; -wire [31:0] axi_wdata; -wire axi_wvalid; -wire axi_wready; -wire [1:0] axi_bresp; -wire axi_bvalid; -wire axi_bready; -wire [9:0] axi_araddr; -wire axi_arvalid; -wire axi_arready; -wire [1:0] axi_rresp; -wire [31:0] axi_rdata; -wire axi_rvalid; -wire axi_rready; -//Cfg Space Registers -wire mac_sw_rst; -wire axi4_st_mux_select; -wire pat_mux_select; -wire udp_pat_gen_en; -wire mac_pat_gen_en; -wire [15:0] pat_gen_num; -wire [15:0] pat_gen_ipg; -wire [47:0] pat_dst_mac; -wire [47:0] pat_src_mac; -wire [15:0] pat_mac_dlen; -wire [31:0] pat_src_ip; -wire [31:0] pat_dst_ip; -wire [15:0] pat_src_port; -wire [15:0] pat_dst_port; -wire [15:0] pat_udp_dlen; - -//TSE DDIO -`ifdef TITANIUM - wire rgmii_rxc; - - assign rgmii_rxc = mux_clk; -`else - wire rgmii_rx_ctl_LO; - wire rgmii_rx_ctl_HI; - wire rgmii_tx_ctl_LO; - wire rgmii_tx_ctl_HI; - - assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ; - assign rgmii_rx_ctl_HI = rgmii_rx_ctl ; - assign rgmii_rx_ctl_LO = rgmii_rx_ctl ; -`endif -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -assign pll_rstn = 1; -/*----------------------- Clock Region -----------------------*/ -//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above. -//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has -//high combi logic and couldn't meet timing at 125Mhz. -assign rx_axis_clk = clk;//clk_125m; -assign tx_axis_clk = clk;//clk_125m; - - -/*----------------------- Reset Region -----------------------*/ -//assign pll_0_reset = 1'b0; -assign clk_50m = clk; -assign phy_rstn = sw6; -assign clk_50m_rstn = pll_0_locked; -assign mac_reset = ~pll_0_locked; -assign proto_reset = mac_sw_rst; -assign mac_rstn = ~(mac_reset || proto_reset); - -/*----------------------- MCU Module ----------------------------*/ -`ifndef SIM_MODE -sapphire u_mcu -( -//user custom ports - //SOC - .io_systemClk (clk_50m ), - .io_asyncReset (1'b0 ), - .system_uart_0_io_txd (system_uart_0_io_txd ), - .system_uart_0_io_rxd (system_uart_0_io_rxd ), - .system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ), - .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ), - .system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ), - .system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ), - .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ), - .system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ), - .system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ), - .system_spi_0_io_ss (system_spi_0_io_ss ), - .jtagCtrl_tck (jtag_inst1_TCK ), - .jtagCtrl_tdi (jtag_inst1_TDI ), - .jtagCtrl_tdo (jtag_inst1_TDO ), - .jtagCtrl_enable (jtag_inst1_SEL ), - .jtagCtrl_capture (jtag_inst1_CAPTURE ), - .jtagCtrl_shift (jtag_inst1_SHIFT ), - .jtagCtrl_update (jtag_inst1_UPDATE ), - .jtagCtrl_reset (jtag_inst1_RESET ), -//APB3 Master Interface - .io_apbSlave_0_PADDR (apb3_paddr ), - .io_apbSlave_0_PSEL (apb3_psel ), - .io_apbSlave_0_PENABLE (apb3_penable ), - .io_apbSlave_0_PREADY (apb3_pready ), - .io_apbSlave_0_PWRITE (apb3_pwrite ), - .io_apbSlave_0_PWDATA (apb3_pwdata ), - .io_apbSlave_0_PRDATA (apb3_prdata ), - .io_apbSlave_0_PSLVERROR (apb3_pslverror ) -); -`endif - -assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready; -assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata; -assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror; - -assign mac_apb3_paddr = apb3_paddr[9:0]; -assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0; -assign mac_apb3_penable = apb3_penable; -assign mac_apb3_pwrite = apb3_pwrite; -assign mac_apb3_pwdata = apb3_pwdata; - -assign ex_apb3_paddr = apb3_paddr[9:0]; -assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0; -assign ex_apb3_penable = apb3_penable; -assign ex_apb3_pwrite = apb3_pwrite; -assign ex_apb3_pwdata = apb3_pwdata; - -apb3_2_axi4_lite#( - .ADDR_WTH (10 ) -) -u_apb3_2_axi4_lite -( -//Globle Signals - .clk (clk_50m ), - .rstn (clk_50m_rstn ), -//APB3 Slave Interface - .s_apb3_paddr (mac_apb3_paddr ), - .s_apb3_psel (mac_apb3_psel ), - .s_apb3_penable (mac_apb3_penable ), - .s_apb3_pready (mac_apb3_pready ), - .s_apb3_pwrite (mac_apb3_pwrite ), - .s_apb3_pwdata (mac_apb3_pwdata ), - .s_apb3_prdata (mac_apb3_prdata ), - .s_apb3_pslverror (mac_apb3_pslverror ), -//AXI4-Lite Master Interface - .m_axi_awaddr (axi_awaddr ), - .m_axi_awvalid (axi_awvalid ), - .m_axi_awready (axi_awready ), - .m_axi_wdata (axi_wdata ), - .m_axi_wvalid (axi_wvalid ), - .m_axi_wready (axi_wready ), - .m_axi_bresp (axi_bresp ), - .m_axi_bvalid (axi_bvalid ), - .m_axi_bready (axi_bready ), - .m_axi_araddr (axi_araddr ), - .m_axi_arvalid (axi_arvalid ), - .m_axi_arready (axi_arready ), - .m_axi_rresp (axi_rresp ), - .m_axi_rdata (axi_rdata ), - .m_axi_rvalid (axi_rvalid ), - .m_axi_rready (axi_rready ) -); - -reg_apb3#( - .ADDR_WTH (10 ) -) -u_reg_apb3 -( -//Globle Signals -// -//APB3 Slave Interface - .s_apb3_clk (clk_50m ), - .s_apb3_rstn (clk_50m_rstn ), - .s_apb3_paddr (ex_apb3_paddr ), - .s_apb3_psel (ex_apb3_psel ), - .s_apb3_penable (ex_apb3_penable ), - .s_apb3_pready (ex_apb3_pready ), - .s_apb3_pwrite (ex_apb3_pwrite ), - .s_apb3_pwdata (ex_apb3_pwdata ), - .s_apb3_prdata (ex_apb3_prdata ), - .s_apb3_pslverror (ex_apb3_pslverror ), -//Cfg Space Registers -//--Example Registers Field - .mac_sw_rst (mac_sw_rst ), - .axi4_st_mux_select (axi4_st_mux_select ), - .pat_mux_select (pat_mux_select ), - .udp_pat_gen_en (udp_pat_gen_en ), - .mac_pat_gen_en (mac_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), - .pat_dst_mac (pat_dst_mac ), - .pat_src_mac (pat_src_mac ), - .pat_mac_dlen (pat_mac_dlen ), - .pat_src_ip (pat_src_ip ), - .pat_dst_ip (pat_dst_ip ), - .pat_src_port (pat_src_port ), - .pat_dst_port (pat_dst_port ), - .pat_udp_dlen (pat_udp_dlen ), - .clkmux_sel (mux_clk_sw ) -); - -//generate if (PATTERN_TYPE == 0) begin //UDP -// -//assign mac_tx_axis_mac_tdata = 8'h0; -//assign mac_tx_axis_mac_tvalid = 1'b0; -//assign mac_tx_axis_mac_tlast = 1'b0; - -/*----------------------- The Ethernet Pattern Module -----------------------*/ -udp_pat_gen u_udp_pat_gen -( -//Globle Signals - .clk (tx_axis_clk ), - .rstn (mac_rstn ), -//Control Interface - .pat_gen_en (udp_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), -//MAC Protocol Signals - .dst_mac (pat_dst_mac ), - .src_mac (pat_src_mac ), -//IP Protocol Signals - .src_ip (pat_src_ip ), - .dst_ip (pat_dst_ip ), -//UDP Protocol Signals - .src_port (pat_src_port ), - .dst_port (pat_dst_port ), - .udp_dlen (pat_udp_dlen ), -//AXI4-Stream Interface - .rclk (rx_axis_clk ), - .rrstn (mac_rstn ), - .rdata (rx_axis_mac_tdata ), - .rvalid (rx_axis_mac_tvalid ), - .rlast (rx_axis_mac_tlast ), - .tdata (udp_tx_axis_mac_tdata ), - .tvalid (udp_tx_axis_mac_tvalid ), - .tlast (udp_tx_axis_mac_tlast ), - .tready (udp_tx_axis_mac_tready ) -); -//end -//else begin //MAC -// -//assign udp_tx_axis_mac_tdata = 8'h0; -//assign udp_tx_axis_mac_tvalid = 1'b0; -//assign udp_tx_axis_mac_tlast = 1'b0; - -mac_pat_gen u_mac_pat_gen -( -//Globle Signals - .clk (tx_axis_clk ), - .rstn (mac_rstn ), -//Control Interface - .pat_gen_en (mac_pat_gen_en ), - .pat_gen_num (pat_gen_num ), - .pat_gen_ipg (pat_gen_ipg ), -//MAC Protocol Signals - .dst_mac (pat_dst_mac ), - .src_mac (pat_src_mac ), - .mac_dlen (pat_mac_dlen ), -//AXI4-Stream Interface - .rclk (rx_axis_clk ), - .rrstn (mac_rstn ), - .rdata (rx_axis_mac_tdata ), - .rvalid (rx_axis_mac_tvalid ), - .rlast (rx_axis_mac_tlast ), - .tdata (mac_tx_axis_mac_tdata ), - .tvalid (mac_tx_axis_mac_tvalid ), - .tlast (mac_tx_axis_mac_tlast ), - .tready (mac_tx_axis_mac_tready ) -); -//end -//endgenerate - -axi4_st_mux u_pat_mux -( -//Globle Signals - .mux_select (pat_mux_select ),//0:udp pat; 1:mac pat; -//Mux In 0 Interface - .tdata0 (udp_tx_axis_mac_tdata ), - .tvalid0 (udp_tx_axis_mac_tvalid ), - .tlast0 (udp_tx_axis_mac_tlast ), - .tuser0 (1'b0 ), - .tready0 (udp_tx_axis_mac_tready ), -//Mux In 1 Interface - .tdata1 (mac_tx_axis_mac_tdata ), - .tvalid1 (mac_tx_axis_mac_tvalid ), - .tlast1 (mac_tx_axis_mac_tlast ), - .tuser1 (1'b0 ), - .tready1 (mac_tx_axis_mac_tready ), -//Mux Out Interface - .tdata (pat_tx_axis_mac_tdata ), - .tvalid (pat_tx_axis_mac_tvalid ), - .tlast (pat_tx_axis_mac_tlast ), - .tuser (pat_tx_axis_mac_tuser ), - .tready (pat_tx_axis_mac_tready ) -); - -/*----------------------- The Tx AXI4 St Mux Module -----------------------*/ -axi4_st_mux u_tx_axi4st_mux -( -//Globle Signals - .mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback; -//Mux In 0 Interface - .tdata0 (pat_tx_axis_mac_tdata ), - .tvalid0 (pat_tx_axis_mac_tvalid ), - .tlast0 (pat_tx_axis_mac_tlast ), - .tuser0 (pat_tx_axis_mac_tuser ), - .tready0 (pat_tx_axis_mac_tready ), -//Mux In 1 Interface - .tdata1 (loop_tx_axis_mac_tdata ), - .tvalid1 (loop_tx_axis_mac_tvalid ), - .tlast1 (loop_tx_axis_mac_tlast ), - .tuser1 (loop_tx_axis_mac_tuser ), - .tready1 (loop_tx_axis_mac_tready ), -//Mux Out Interface - .tdata (tx_axis_mac_tdata ), - .tvalid (tx_axis_mac_tvalid ), - .tlast (tx_axis_mac_tlast ), - .tuser (tx_axis_mac_tuser ), - .tready (tx_axis_mac_tready ) -); - -/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/ -gTSE u_tsemac -( -//Globle Signals - .mac_reset (mac_reset ), - .proto_reset (proto_reset ), - .tx_mac_aclk (clk_125m ), - .rx_mac_aclk ( ), - .eth_speed ( ), -//Receive AXI4-Stream Interface - .rx_axis_clk (rx_axis_clk ), - .rx_axis_mac_tdata (rx_axis_mac_tdata ), - .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), - .rx_axis_mac_tlast (rx_axis_mac_tlast ), - .rx_axis_mac_tstrb (), - .rx_axis_mac_tuser (rx_axis_mac_tuser ), - .rx_axis_mac_tready (rx_axis_mac_tready ), -//Transmit AXI4-Stream Interface - .tx_axis_clk (tx_axis_clk ), - .tx_axis_mac_tdata (tx_axis_mac_tdata ), - .tx_axis_mac_tvalid (tx_axis_mac_tvalid ), - .tx_axis_mac_tlast (tx_axis_mac_tlast ), - .tx_axis_mac_tstrb (1'b1 ), - .tx_axis_mac_tuser (tx_axis_mac_tuser ), - .tx_axis_mac_tready (tx_axis_mac_tready ), - //--RGMII Interface - .rgmii_txd_HI (rgmii_txd_HI ), - .rgmii_txd_LO (rgmii_txd_LO ), - .rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ), - .rgmii_txc_HI (rgmii_txc_HI ), - .rgmii_txc_LO (rgmii_txc_LO ), - .rgmii_rxd_HI (rgmii_rxd_HI ), - .rgmii_rxd_LO (rgmii_rxd_LO ), - .rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ), - .rgmii_rxc (rgmii_rxc ), - //AXI4-Lite Interface - .s_axi_aclk (clk_50m ), - .s_axi_awaddr (axi_awaddr ), - .s_axi_awvalid (axi_awvalid ), - .s_axi_awready (axi_awready ), - .s_axi_wdata (axi_wdata ), - .s_axi_wvalid (axi_wvalid ), - .s_axi_wready (axi_wready ), - .s_axi_bresp (axi_bresp ), - .s_axi_bvalid (axi_bvalid ), - .s_axi_bready (axi_bready ), - .s_axi_araddr (axi_araddr ), - .s_axi_arvalid (axi_arvalid ), - .s_axi_arready (axi_arready ), - .s_axi_rresp (axi_rresp ), - .s_axi_rdata (axi_rdata ), - .s_axi_rvalid (axi_rvalid ), - .s_axi_rready (axi_rready ), - //MDIO Interface - .Mdo (phy_mdo ), - .MdoEn (phy_mdo_en ), - .Mdi (phy_mdi ), - .Mdc (phy_mdc ) -); - -/*----------------------- User Interface Loopback Module ----------------------------*/ -mac_rx2tx u_mac_rx2tx -( -//Globle Signals -// -//Receive AXI4-Stream Interface - .rx_axis_clk (rx_axis_clk ), - .rx_axis_rstn (mac_rstn ), - .rx_axis_mac_tdata (rx_axis_mac_tdata ), - .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), - .rx_axis_mac_tlast (rx_axis_mac_tlast ), - .rx_axis_mac_tuser (rx_axis_mac_tuser ), - .rx_axis_mac_tready (rx_axis_mac_tready ), -//Transmit AXI4-Stream Interface - .tx_axis_clk (tx_axis_clk ), - .tx_axis_rstn (mac_rstn ), - .tx_axis_mac_tdata (loop_tx_axis_mac_tdata ), - .tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ), - .tx_axis_mac_tlast (loop_tx_axis_mac_tlast ), - .tx_axis_mac_tuser (loop_tx_axis_mac_tuser ), - .tx_axis_mac_tready (loop_tx_axis_mac_tready ) -); - -endmodule - diff --git a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.xml b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.xml deleted file mode 100644 index d7a0967..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.xml +++ /dev/null @@ -1,124 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/ip/gTSE/Ti60F225_devkit/timing_Ti60.sdc b/fpga/ip/gTSE/Ti60F225_devkit/timing_Ti60.sdc deleted file mode 100644 index 6476988..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/timing_Ti60.sdc +++ /dev/null @@ -1,77 +0,0 @@ -################################## Clock Constraints ########################## -create_clock -period 20.00 clk -create_clock -period 8.00 clk_125m -create_clock -waveform {2.00 6.00} -period 8.00 clk_125m_90deg -create_clock -period 100.00 [get_ports {jtag_inst1_TCK}] - -# Dynamic Clock Mux Outputs -##################################### -create_clock -period 8.000 -name mux_clk [get_ports {mux_clk}] - - -#################################################################################################################################### -# Timing Mode Constrains -#################################################################################################################################### -set_clock_groups -exclusive -group {clk} -group {clk_125m} -group {clk_125m_90deg} -group {mux_clk} -group {jtag_inst1_TCK} - -# JTAG Constraints -#################### -# create_clock -period [get_ports {jtag_inst1_TCK}] -# create_clock -period [get_ports {jtag_inst1_DRCK}] -set_output_delay -clock jtag_inst1_TCK -max 0.117 [get_ports {jtag_inst1_TDO}] -set_output_delay -clock jtag_inst1_TCK -min -0.075 [get_ports {jtag_inst1_TDO}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.280 [get_ports {jtag_inst1_CAPTURE}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.187 [get_ports {jtag_inst1_CAPTURE}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.243 [get_ports {jtag_inst1_SEL}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.162 [get_ports {jtag_inst1_SEL}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.337 [get_ports {jtag_inst1_SHIFT}] -set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.225 [get_ports {jtag_inst1_SHIFT}] - -# HSIO GPIO Constraints -######################### -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~278}] -max 0.414 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~278}] -min 0.276 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~268}] -max 0.414 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~268}] -min 0.276 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~267}] -max 0.414 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~267}] -min 0.276 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~255}] -max 0.414 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~255}] -min 0.276 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~254}] -max 0.414 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] -set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~254}] -min 0.276 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] -# set_input_delay -clock [-reference_pin ] -max [get_ports {sw6}] -# set_input_delay -clock [-reference_pin ] -min [get_ports {sw6}] -# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdc}] -# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdc}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~210}] -max 0.263 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~210}] -min -0.140 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] -set_output_delay -clock clk_125m_90deg -reference_pin [get_ports {clk_125m_90deg~CLKOUT~218~225}] -max 0.263 [get_ports {rgmii_txc_LO rgmii_txc_HI}] -set_output_delay -clock clk_125m_90deg -reference_pin [get_ports {clk_125m_90deg~CLKOUT~218~225}] -min -0.140 [get_ports {rgmii_txc_LO rgmii_txc_HI}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~171}] -max 0.263 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~171}] -min -0.140 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~170}] -max 0.263 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~170}] -min -0.140 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~196}] -max 0.263 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~196}] -min -0.140 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~195}] -max 0.263 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] -set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~195}] -min -0.140 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] -# set_input_delay -clock [-reference_pin ] -max [get_ports {phy_mdi}] -# set_input_delay -clock [-reference_pin ] -min [get_ports {phy_mdi}] -# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdo}] -# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdo}] -# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdo_en}] -# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdo_en}] - -# Clockout Interface -###################### -# rgmii_rx_ctl -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~278}] -# rgmii_rxd[0] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~268}] -# rgmii_rxd[1] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~267}] -# rgmii_rxd[2] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~255}] -# rgmii_rxd[3] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~254}] -# rgmii_tx_ctl -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~210}] -# rgmii_txc -clock clk_125m_90deg -reference_pin [get_ports {clk_125m_90deg~CLKOUT~218~225}] -# rgmii_txd[0] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~171}] -# rgmii_txd[1] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~170}] -# rgmii_txd[2] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~196}] -# rgmii_txd[3] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~195}] diff --git a/fpga/ip/gTSE/Ti60F225_devkit/udp_pat_gen.v b/fpga/ip/gTSE/Ti60F225_devkit/udp_pat_gen.v deleted file mode 100644 index e5626c3..0000000 --- a/fpga/ip/gTSE/Ti60F225_devkit/udp_pat_gen.v +++ /dev/null @@ -1,497 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / -// / / .' / -// __/ /.' / -// __ \ / -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* -`timescale 1 ns / 1 ns -module udp_pat_gen -( -//Globle Signals -input clk, -input rstn, -//Control Interface -input pat_gen_en, -input [15:0] pat_gen_num,//When value is 0, it's infinite mode -input [15:0] pat_gen_ipg, -//MAC Protocol Signals -input [47:0] dst_mac, -input [47:0] src_mac, -//IP Protocol Signals -input [31:0] src_ip, -input [31:0] dst_ip, -//UDP Protocol Signals -input [15:0] udp_dlen, -input [15:0] src_port, -input [15:0] dst_port, -//AXI4-Stream Interface -input rclk, -input rrstn, -input [7:0] rdata, -input rvalid, -input rlast, - -output reg [7:0] tdata, -output reg tvalid, -output reg tlast, -input tready -); - -// Parameter Define -localparam VER = 4'h4;//IPv4 -localparam IHL = 4'h5;//Internet Header Length -localparam TOS = 8'h0;//Type Of Service -localparam FLG = 3'h0;//Flags -localparam TTL = 8'h40;//Time To Live -localparam PTC = 8'h11;//UDP Protocol - -localparam IDLE = 3'h0; -localparam UDP_CHKSUM = 3'h1; -localparam IP_CHKSUM = 3'h2; -localparam PAT_IPG = 3'h3; -localparam PAT_GEN = 3'h4; - -// Register Define -reg [2:0] cur_state; -reg [2:0] next_state; -reg pat_gen_en_dl1; -reg pat_gen_en_dl2; -reg [31:0] src_ip_r; -reg [31:0] dst_ip_r; -reg [15:0] src_port_r; -reg [15:0] dst_port_r; -reg pat_en; -reg infinite_en; -reg [15:0] num_cnt; -reg [15:0] udp_chksum_cnt; -reg [3:0] ip_chksum_cnt; -reg [15:0] ipg_cnt; -reg [15:0] pat_cnt; -reg [15:0] udp_len; -reg [15:0] udp_chksum_num; -reg [7:0] udp_data_h; -reg [7:0] udp_data_l; -reg [16:0] udp_chksum_r; -reg [15:0] udp_chksum; -reg [15:0] ip_len; -reg [15:0] ip_id; -reg [12:0] ip_ofs; -reg [16:0] ip_chksum_r; -reg [15:0] ip_chksum; - -reg [15:0] pat_gen_num_r; -reg [15:0] pat_gen_ipg_r; -reg [47:0] dst_mac_r; -reg [47:0] src_mac_r; -reg [15:0] udp_dlen_r; - -// Wire Define -/*----------------------------------------------------------------------------------*\ - The main code -\*----------------------------------------------------------------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) begin - pat_gen_num_r <= 16'h0; - pat_gen_ipg_r <= 16'h0; - dst_mac_r <= 48'h0; - src_mac_r <= 48'h0; - udp_dlen_r <= 16'h0; - end - else begin - pat_gen_num_r <= pat_gen_num; - pat_gen_ipg_r <= pat_gen_ipg; - dst_mac_r <= dst_mac; - src_mac_r <= src_mac; - udp_dlen_r <= udp_dlen; - end -end - -/*----------------------- FSM Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - cur_state <= IDLE; - else - cur_state <= next_state; -end - -always @(*) - begin - case(cur_state) - IDLE : - if(pat_en == 1'b1) - next_state = UDP_CHKSUM; - else - next_state = IDLE; - - UDP_CHKSUM : - if(udp_chksum_cnt == udp_chksum_num) - next_state = IP_CHKSUM; - else - next_state = UDP_CHKSUM; - - IP_CHKSUM : - if(ip_chksum_cnt == 4'd9) - next_state = PAT_GEN; - else - next_state = IP_CHKSUM; - - PAT_IPG : - if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) - next_state = IDLE; - else if(ipg_cnt == pat_gen_ipg_r) - next_state = IP_CHKSUM; - else - next_state = PAT_IPG; - - PAT_GEN : - if((tlast == 1'b1) && (tready == 1'b1)) - next_state = PAT_IPG; - else - next_state = PAT_GEN; - - default : - next_state = IDLE; - endcase - end - -/*----------------------- Generator Control Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - pat_gen_en_dl1 <= 1'h0; - pat_gen_en_dl2 <= 1'h0; - end - else - begin - pat_gen_en_dl1 <= pat_gen_en; - pat_gen_en_dl2 <= pat_gen_en_dl1; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - src_ip_r <= 32'h0; - dst_ip_r <= 32'h0; - src_port_r <= 16'h0; - dst_port_r <= 16'h0; - end - else - begin - src_ip_r <= src_ip; - dst_ip_r <= dst_ip; - src_port_r <= src_port; - dst_port_r <= dst_port; - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - pat_en <= 1'h1; - else if((cur_state == IDLE) && (pat_en == 1'b1)) - pat_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - infinite_en <= 1'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) - infinite_en <= 1'h1; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - infinite_en <= 1'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - num_cnt <= 16'h0; - else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) - num_cnt <= pat_gen_num_r; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) - num_cnt <= num_cnt - 1'b1; -end - -/*----------------------- UDP Protocol Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_len <= 16'h0; - else - udp_len <= udp_dlen_r + 16'd8; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_num <= 16'h0; - else if(udp_dlen_r[0] == 1'b1) - udp_chksum_num <= udp_dlen_r[15:1] + 16'd10; - else - udp_chksum_num <= udp_dlen_r[15:1] + 16'd9; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - begin - udp_data_h <= 8'h0; - udp_data_l <= 8'h0; - end - else if(cur_state == IDLE) - begin - udp_data_h <= 8'h0; - udp_data_l <= 8'h1; - end - else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9)) - begin - udp_data_h <= udp_data_h + 8'h2; - udp_data_l <= udp_data_l + 8'h2; - end -end - -//udp checksum calculate -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_r <= 17'h0; - else if(cur_state == IDLE) - udp_chksum_r <= 17'h0; - else if(cur_state == UDP_CHKSUM) begin - if (udp_chksum_cnt <= 16'd8) begin - case(udp_chksum_cnt[3:0]) - 4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16]; - 4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16]; - 4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16]; - 4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16]; - 4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16]; - 4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; - 4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16]; - 4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16]; - 4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; - default : udp_chksum_r <= 17'h0; - endcase - end - else begin - if(udp_chksum_cnt == udp_chksum_num) - udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16]; - else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1)) - udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16]; - else - udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16]; - end - end -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum <= 16'h0; - else - udp_chksum <= ~udp_chksum_r[15:0]; -end - -/*----------------------- IP Protocol Region ----------------------------*/ -//IP Frame Total Length -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_len <= 16'h0; - else - ip_len <= udp_len + 16'd20; -end - -//IP Frame Identification -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_id <= 16'h0; - else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1)) - ip_id <= ip_id + 1'b1; -end - -//IP Frame Fragment Offset -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum <= 16'h0; - else - ip_chksum <= ~ip_chksum_r[15:0]; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_ofs <= 13'h0; -end - -//ip checksum calculate -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum_r <= 16'h0; - else if(cur_state == IDLE) - ip_chksum_r <= 16'h0; - else if(cur_state == IP_CHKSUM) begin - case(ip_chksum_cnt) - 4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16]; - 4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16]; - 4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16]; - 4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16]; - 4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16]; - 4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16]; - 4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16]; - 4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16]; - 4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16]; - 4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16]; - endcase - end - else if(cur_state == PAT_IPG) - ip_chksum_r <= 16'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum <= 16'h0; - else - ip_chksum <= ~ip_chksum_r[15:0]; -end - -/*----------------------- Pattern Counter Region ----------------------------*/ -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - udp_chksum_cnt <= 16'h0; - else if(cur_state == UDP_CHKSUM) - udp_chksum_cnt <= udp_chksum_cnt + 1'b1; - else - udp_chksum_cnt <= 16'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ip_chksum_cnt <= 4'h0; - else if(cur_state == IP_CHKSUM) - ip_chksum_cnt <= ip_chksum_cnt + 1'b1; - else - ip_chksum_cnt <= 4'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - ipg_cnt <= 16'h0; - else if(cur_state == PAT_IPG) - ipg_cnt <= ipg_cnt + 1'b1; - else - ipg_cnt <= 8'h0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - pat_cnt <= 16'h0; - else if(cur_state != PAT_GEN) - pat_cnt <= 16'h0; - else if(tready == 1'b1) - pat_cnt <= pat_cnt + 1'b1; -end - -/*----------------------- Pattern Generator Region ----------------------------*/ - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tvalid <= 1'b0; - else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) - tvalid <= 1'b1; - else if((tready == 1'b1) && (tlast == 1'b1)) - tvalid <= 1'b0; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tdata <= 8'h0; - else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42)) - case(pat_cnt[5:0]) - 6'd0 : tdata <= dst_mac_r[5*8 +: 8]; - 6'd1 : tdata <= dst_mac_r[4*8 +: 8]; - 6'd2 : tdata <= dst_mac_r[3*8 +: 8]; - 6'd3 : tdata <= dst_mac_r[2*8 +: 8]; - 6'd4 : tdata <= dst_mac_r[1*8 +: 8]; - 6'd5 : tdata <= dst_mac_r[0*8 +: 8]; - 6'd6 : tdata <= src_mac_r[5*8 +: 8]; - 6'd7 : tdata <= src_mac_r[4*8 +: 8]; - 6'd8 : tdata <= src_mac_r[3*8 +: 8]; - 6'd9 : tdata <= src_mac_r[2*8 +: 8]; - 6'd10 : tdata <= src_mac_r[1*8 +: 8]; - 6'd11 : tdata <= src_mac_r[0*8 +: 8]; - 6'd12 : tdata <= 8'h08; - 6'd13 : tdata <= 8'h00; - 6'd14 : tdata <= {VER,IHL}; - 6'd15 : tdata <= TOS; - 6'd16 : tdata <= ip_len[15:8]; - 6'd17 : tdata <= ip_len[7:0]; - 6'd18 : tdata <= ip_id[15:8]; - 6'd19 : tdata <= ip_id[7:0]; - 6'd20 : tdata <= {FLG,ip_ofs[12:8]}; - 6'd21 : tdata <= ip_ofs[7:0]; - 6'd22 : tdata <= TTL; - 6'd23 : tdata <= PTC; - 6'd24 : tdata <= ip_chksum[15:8]; - 6'd25 : tdata <= ip_chksum[7:0]; - 6'd26 : tdata <= src_ip_r[3*8 +: 8]; - 6'd27 : tdata <= src_ip_r[2*8 +: 8]; - 6'd28 : tdata <= src_ip_r[1*8 +: 8]; - 6'd29 : tdata <= src_ip_r[0*8 +: 8]; - 6'd30 : tdata <= dst_ip_r[3*8 +: 8]; - 6'd31 : tdata <= dst_ip_r[2*8 +: 8]; - 6'd32 : tdata <= dst_ip_r[1*8 +: 8]; - 6'd33 : tdata <= dst_ip_r[0*8 +: 8]; - 6'd34 : tdata <= src_port_r[15:8]; - 6'd35 : tdata <= src_port_r[7:0]; - 6'd36 : tdata <= dst_port_r[15:8]; - 6'd37 : tdata <= dst_port_r[7:0]; - 6'd38 : tdata <= udp_len[15:8]; - 6'd39 : tdata <= udp_len[7:0]; - 6'd40 : tdata <= udp_chksum[15:8]; - 6'd41 : tdata <= udp_chksum[7:0]; - 6'd42 : tdata <= 8'h0;//UDP First Data - default : tdata <= tdata + 1'b1; - endcase - else if((cur_state == PAT_GEN) && (tready == 1'b1)) - tdata <= tdata + 1'b1; -end - -always @(posedge clk or negedge rstn) -begin - if(rstn == 1'b0) - tlast <= 1'b0; - else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13)) - tlast <= 1'b1; - else if(tready == 1'b1) - tlast <= 1'b0; -end - -endmodule diff --git a/fpga/ip/gTSE/gTSE.sv b/fpga/ip/gTSE/gTSE.sv deleted file mode 100644 index 8095d65..0000000 --- a/fpga/ip/gTSE/gTSE.sv +++ /dev/null @@ -1,9844 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.288.2.10 -// IP Version: 7.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _4c19f37180ff465ca20760e199a0613f -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gTSE -( - input mac_reset, - input proto_reset, - output rx_mac_aclk, - input tx_mac_aclk, - output [2:0] eth_speed, - input rx_axis_clk, - output rx_axis_mac_tuser, - output rx_axis_mac_tlast, - output rx_axis_mac_tvalid, - input rx_axis_mac_tready, - input tx_axis_clk, - input tx_axis_mac_tvalid, - input tx_axis_mac_tlast, - input tx_axis_mac_tuser, - output tx_axis_mac_tready, - output [3:0] rgmii_txd_HI, - output [3:0] rgmii_txd_LO, - output rgmii_tx_ctl_HI, - output rgmii_tx_ctl_LO, - output rgmii_txc_HI, - output rgmii_txc_LO, - input [3:0] rgmii_rxd_HI, - input [3:0] rgmii_rxd_LO, - input rgmii_rx_ctl_HI, - input rgmii_rx_ctl_LO, - input rgmii_rxc, - input s_axi_aclk, - output [7:0] rx_axis_mac_tdata, - input [7:0] tx_axis_mac_tdata, - input [0:0] tx_axis_mac_tstrb, - output [0:0] rx_axis_mac_tstrb, - output MdoEn, - output Mdo, - input Mdi, - output Mdc, - input [9:0] s_axi_araddr, - output s_axi_arready, - input s_axi_arvalid, - input [9:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_awvalid, - input s_axi_bready, - output [1:0] s_axi_bresp, - output s_axi_bvalid, - output [31:0] s_axi_rdata, - input s_axi_rready, - output [1:0] s_axi_rresp, - output s_axi_rvalid, - input [31:0] s_axi_wdata, - output s_axi_wready, - input s_axi_wvalid -); -`IP_MODULE_NAME(efx_mac1gbe) -#( - .VERSION (16), - .TXFIFO_EN (1'b1), - .RXFIFO_EN (1'b1), - .TXFIFO_DTH (4096), - .RXFIFO_DTH (4096), - .PHY_INTF_MODE (0), - .AXIS_DW (8), - .RGMII_RXC_EDGE (1'b1), - .RGMII_TXC_DLY (1'b1), - .INTER_PACKET_GAP (6'd12), - .MTU_FRAME_LENGTH (16'd1518), - .MAC_SOURCE_ADDRESS (48'd0), - .ENABLE_BROADCAST_FILTERING (1'b1), - .LOOPBACK_EN (1'b1), - .APBIF (1'b0), - .FAMILY ("TITANIUM") -) -u_efx_mac1gbe -( - .mac_reset ( mac_reset ), - .proto_reset ( proto_reset ), - .rx_mac_aclk ( rx_mac_aclk ), - .tx_mac_aclk ( tx_mac_aclk ), - .eth_speed ( eth_speed ), - .rx_axis_clk ( rx_axis_clk ), - .rx_axis_mac_tuser ( rx_axis_mac_tuser ), - .rx_axis_mac_tlast ( rx_axis_mac_tlast ), - .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), - .rx_axis_mac_tready ( rx_axis_mac_tready ), - .tx_axis_clk ( tx_axis_clk ), - .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), - .tx_axis_mac_tlast ( tx_axis_mac_tlast ), - .tx_axis_mac_tuser ( tx_axis_mac_tuser ), - .tx_axis_mac_tready ( tx_axis_mac_tready ), - .rgmii_txd_HI ( rgmii_txd_HI ), - .rgmii_txd_LO ( rgmii_txd_LO ), - .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), - .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), - .rgmii_txc_HI ( rgmii_txc_HI ), - .rgmii_txc_LO ( rgmii_txc_LO ), - .rgmii_rxd_HI ( rgmii_rxd_HI ), - .rgmii_rxd_LO ( rgmii_rxd_LO ), - .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), - .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), - .rgmii_rxc ( rgmii_rxc ), - .s_axi_aclk ( s_axi_aclk ), - .rx_axis_mac_tdata ( rx_axis_mac_tdata ), - .tx_axis_mac_tdata ( tx_axis_mac_tdata ), - .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), - .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), - .MdoEn ( MdoEn ), - .Mdo ( Mdo ), - .Mdi ( Mdi ), - .Mdc ( Mdc ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arready ( s_axi_arready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awready ( s_axi_awready ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rready ( s_axi_rready ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_wready ( s_axi_wready ), - .s_axi_wvalid ( s_axi_wvalid ) -); -endmodule - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_top) # ( - parameter FAMILY = "TRION", // New Param - parameter SYNC_CLK = 0, - parameter BYPASS_RESET_SYNC = 0, // New Param - parameter SYNC_STAGE = 2, // New Param - parameter MODE = "STANDARD", - parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) - parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) - parameter PIPELINE_REG = 1, // Reverted (By default is ON) - parameter OPTIONAL_FLAGS = 1, // Reverted - parameter OUTPUT_REG = 0, - parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_FULL_ASSERT = 27, - parameter PROG_FULL_NEGATE = 23, - parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature - parameter PROG_EMPTY_ASSERT = 5, - parameter PROG_EMPTY_NEGATE = 7, - parameter ALMOST_FLAG = OPTIONAL_FLAGS, - parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, - parameter ASYM_WIDTH_RATIO = 4, - parameter WADDR_WIDTH = depth2width(DEPTH), - parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), - parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), - parameter RADDR_WIDTH = depth2width(RD_DEPTH), - parameter ENDIANESS = 0, - parameter OVERFLOW_PROTECT = 1, - parameter UNDERFLOW_PROTECT = 1, - parameter RAM_STYLE = "block_ram" - -)( - input wire a_rst_i, - input wire a_wr_rst_i, - input wire a_rd_rst_i, - input wire clk_i, - input wire wr_clk_i, - input wire rd_clk_i, - input wire wr_en_i, - input wire rd_en_i, - input wire [DATA_WIDTH-1:0] wdata, - output wire almost_full_o, - output wire prog_full_o, - output wire full_o, - output wire overflow_o, - output wire wr_ack_o, - output wire [WADDR_WIDTH :0] datacount_o, - output wire [WADDR_WIDTH :0] wr_datacount_o, - output wire empty_o, - output wire almost_empty_o, - output wire prog_empty_o, - output wire underflow_o, - output wire rd_valid_o, - output wire [RDATA_WIDTH-1:0] rdata, - output wire [RADDR_WIDTH :0] rd_datacount_o, - output wire rst_busy -); - -localparam WR_DEPTH = DEPTH; -localparam WDATA_WIDTH = DATA_WIDTH; -localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : - (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : - (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; - -wire wr_rst_int; -wire rd_rst_int; -wire wr_en_int; -wire rd_en_int; -wire [WADDR_WIDTH-1:0] waddr; -wire [RADDR_WIDTH-1:0] raddr; -wire wr_clk_int; -wire rd_clk_int; -wire [WADDR_WIDTH :0] wr_datacount_int; -wire [RADDR_WIDTH :0] rd_datacount_int; - -generate - if (ASYM_WIDTH_RATIO == 4) begin - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - assign datacount_o = wr_datacount_int; - assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - end - end - else begin - assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; - assign wr_datacount_o = wr_datacount_int; - assign rd_datacount_o = rd_datacount_int; - if (SYNC_CLK) begin - assign wr_clk_int = clk_i; - assign rd_clk_int = clk_i; - end - else begin - assign wr_clk_int = wr_clk_i; - assign rd_clk_int = rd_clk_i; - end - end - - if (!SYNC_CLK) begin - //(* async_reg = "true" *) reg [1:0] wr_rst; - //(* async_reg = "true" *) reg [1:0] rd_rst; - // - //always @ (posedge wr_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // wr_rst <= 2'b11; - // else - // wr_rst <= {wr_rst[0],1'b0}; - //end - // - //always @ (posedge rd_clk_int or posedge a_rst_i) begin - // if (a_rst_i) - // rd_rst <= 2'b11; - // else - // rd_rst <= {rd_rst[0],1'b0}; - //end - - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_wr_rst_i; - assign rd_rst_int = a_rd_rst_i; - assign rst_busy = 1'b0; - end - else begin - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_wr_rst ( - .clk (wr_clk_int), - .reset (a_rst_i), - .d_o (wr_rst_int) - ); - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_rd_rst ( - .clk (rd_clk_int), - .reset (a_rst_i), - .d_o (rd_rst_int) - ); - assign rst_busy = wr_rst_int | rd_rst_int; - end - - end - else begin - //(* async_reg = "true" *) reg [1:0] a_rst; - // - //always @ (posedge clk_i or posedge a_rst_i) begin - // if (a_rst_i) - // a_rst <= 2'b11; - // else - // a_rst <= {a_rst[0],1'b0}; - //end - wire a_rst; - - `IP_MODULE_NAME(efx_resetsync) #( - .ACTIVE_LOW (0) - ) efx_resetsync_a_rst ( - .clk (clk_i), - .reset (a_rst_i), - .d_o (a_rst) - ); - - if (BYPASS_RESET_SYNC) begin - assign wr_rst_int = a_rst_i; - assign rd_rst_int = a_rst_i; - assign rst_busy = 1'b0; - end - else begin - assign wr_rst_int = a_rst; - assign rd_rst_int = a_rst; - assign rst_busy = wr_rst_int | rd_rst_int; - end - end -endgenerate - -`IP_MODULE_NAME(efx_fifo_ram) # ( - .FAMILY (FAMILY), - .WR_DEPTH (WR_DEPTH), - .RD_DEPTH (RD_DEPTH), - .WDATA_WIDTH (WDATA_WIDTH), - .RDATA_WIDTH (RDATA_WIDTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .OUTPUT_REG (OUTPUT_REG), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .ENDIANESS (ENDIANESS), - .RAM_STYLE (RAM_STYLE) -) xefx_fifo_ram ( - .wdata (wdata), - .waddr (waddr), - .raddr (raddr), - .we (wr_en_int), - .re (rd_en_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .rdata (rdata) -); - -`IP_MODULE_NAME(efx_fifo_ctl) # ( - .SYNC_CLK (SYNC_CLK), - .SYNC_STAGE (SYNC_STAGE), - .MODE (MODE), - .WR_DEPTH (WR_DEPTH), - .WADDR_WIDTH (WADDR_WIDTH), - .RADDR_WIDTH (RADDR_WIDTH), - .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), - .RAM_MUX_RATIO (RAM_MUX_RATIO), - .PIPELINE_REG (PIPELINE_REG), - .ALMOST_FLAG (ALMOST_FLAG), - .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), - .PROG_FULL_ASSERT (PROG_FULL_ASSERT), - .PROG_FULL_NEGATE (PROG_FULL_NEGATE), - .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), - .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), - .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), - .OUTPUT_REG (OUTPUT_REG), - .HANDSHAKE_FLAG (HANDSHAKE_FLAG), - .OVERFLOW_PROTECT (OVERFLOW_PROTECT), - .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) -) xefx_fifo_ctl ( - .wr_rst (wr_rst_int), - .rd_rst (rd_rst_int), - .wclk (wr_clk_int), - .rclk (rd_clk_int), - .we (wr_en_i), - .re (rd_en_i), - .wr_full (full_o), - .wr_ack (wr_ack_o), - .rd_empty (empty_o), - .wr_almost_full (almost_full_o), - .rd_almost_empty (almost_empty_o), - .wr_prog_full (prog_full_o), - .rd_prog_empty (prog_empty_o), - .wr_en_int (wr_en_int), - .rd_en_int (rd_en_int), - .waddr (waddr), - .raddr (raddr), - .wr_datacount (wr_datacount_int), - .rd_datacount (rd_datacount_int), - .rd_vld (rd_valid_o), - .wr_overflow (overflow_o), - .rd_underflow (underflow_o) -); - -function integer depth2width; -input [31:0] depth; -begin : fnDepth2Width - if (depth > 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / pipe_reg.v -// / / .' / -// __/ /.' / Description: -// __ \ / Parallel Pipelining Shift Register -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_datasync) #( - parameter STAGE = 32, - parameter WIDTH = 4 -) ( - input wire clk_i, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - -(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; -integer i; - -always @(posedge clk_i) begin - for (i=STAGE-1; i>0; i = i - 1) begin - pipe_reg[i] <= pipe_reg[i-1]; - end - pipe_reg[0] <= d_i; -end -assign d_o = pipe_reg[STAGE-1]; - - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP 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All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ctl) # ( - parameter SYNC_CLK = 1, - parameter SYNC_STAGE = 2, - parameter MODE = "STANDARD", - parameter WR_DEPTH = 512, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter ASYM_WIDTH_RATIO = 4, - parameter RAM_MUX_RATIO = 1, - parameter PIPELINE_REG = 1, - parameter ALMOST_FLAG = 1, - parameter PROGRAMMABLE_FULL = "NONE", - parameter PROG_FULL_ASSERT = 0, - parameter PROG_FULL_NEGATE = 0, - parameter PROGRAMMABLE_EMPTY = "NONE", - parameter PROG_EMPTY_ASSERT = 0, - parameter PROG_EMPTY_NEGATE = 0, - parameter OUTPUT_REG = 0, - parameter HANDSHAKE_FLAG = 1, - parameter OVERFLOW_PROTECT = 0, - parameter UNDERFLOW_PROTECT = 0 -)( - input wire wr_rst, - input wire rd_rst, - input wire wclk, - input wire rclk, - input wire we, - input wire re, - output wire wr_full, - output reg wr_ack, - output wire wr_almost_full, - output wire rd_empty, - output wire rd_almost_empty, - output wire wr_prog_full, - output wire rd_prog_empty, - output wire wr_en_int, - output wire rd_en_int, - output wire [WADDR_WIDTH-1:0] waddr, - output wire [RADDR_WIDTH-1:0] raddr, - output wire [WADDR_WIDTH:0] wr_datacount, - output wire [RADDR_WIDTH:0] rd_datacount, - output wire rd_vld, - output reg wr_overflow, - output reg rd_underflow -); - -reg [WADDR_WIDTH:0] waddr_cntr; -reg [WADDR_WIDTH:0] waddr_cntr_r; -reg [RADDR_WIDTH:0] raddr_cntr; -reg rd_valid; - -wire [WADDR_WIDTH:0] waddr_int; -wire [RADDR_WIDTH:0] raddr_int; -wire rd_empty_int; -wire [WADDR_WIDTH:0] wr_datacount_int; -wire [RADDR_WIDTH:0] rd_datacount_int; - -assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; -// NIC -wire [RADDR_WIDTH:0] ram_raddr; -assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; -//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; -//assign wr_en_int = we & ~wr_full; -assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; - -assign wr_datacount = wr_datacount_int; -assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; - - -generate - if (MODE == "FWFT") begin - // NIC - //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); - //assign rd_empty = rd_empty_fwft; - - assign rd_en_int = 1'b1; - //assign rd_empty = rd_empty_int; - - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // init_set <= 1'b1; - // end - // else if (~init_set & rd_empty) begin - // init_set <= 1'b1; - // end - // else if (~rd_empty_int) begin - // init_set <= 1'b0; - // end - // else if (rd_empty) begin - // init_set <= 1'b1; - // end - //end - // NIC - //always @ (posedge rclk or posedge rd_rst) begin - // if (rd_rst) begin - // rd_empty_fwft <= 1'b1; - // end - // else if (rd_en_int) begin - // rd_empty_fwft <= 1'b0; - // end - // else if (re) begin - // rd_empty_fwft <= 1'b1; - // end - //end - - //if (FAMILY == "TRION") begin - if (OUTPUT_REG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 1'b0; - end - else begin - rd_valid <= ~rd_empty; - end - end - assign rd_vld = rd_valid; - end - else begin - assign rd_vld = ~rd_empty; - end - - assign rd_empty = rd_empty_int; - end - else begin - assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; - assign rd_empty = rd_empty_int; - - if (OUTPUT_REG) begin - reg rd_valid_r; - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid_r <= 'h0; - rd_valid <= 'h0; - end - else begin - {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; - end - end - assign rd_vld = rd_valid; - end - else begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_valid <= 'h0; - end - else begin - rd_valid <= rd_en_int; - end - end - assign rd_vld = rd_valid; - end - end - - if (ALMOST_FLAG) begin - assign wr_almost_full = wr_datacount >= WR_DEPTH-1; - assign rd_almost_empty = rd_datacount <= 'd1; - end - else begin - assign wr_almost_full = 1'b0; - assign rd_almost_empty = 1'b0; - end - - if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx mac_reset, - proto_reset => proto_reset, - rx_mac_aclk => rx_mac_aclk, - tx_mac_aclk => tx_mac_aclk, - eth_speed => eth_speed, - rx_axis_clk => rx_axis_clk, - rx_axis_mac_tuser => rx_axis_mac_tuser, - rx_axis_mac_tlast => rx_axis_mac_tlast, - rx_axis_mac_tvalid => rx_axis_mac_tvalid, - rx_axis_mac_tready => rx_axis_mac_tready, - tx_axis_clk => tx_axis_clk, - tx_axis_mac_tvalid => tx_axis_mac_tvalid, - tx_axis_mac_tlast => tx_axis_mac_tlast, - tx_axis_mac_tuser => tx_axis_mac_tuser, - tx_axis_mac_tready => tx_axis_mac_tready, - rgmii_txd_HI => rgmii_txd_HI, - rgmii_txd_LO => rgmii_txd_LO, - rgmii_tx_ctl_HI => rgmii_tx_ctl_HI, - rgmii_tx_ctl_LO => rgmii_tx_ctl_LO, - rgmii_txc_HI => rgmii_txc_HI, - rgmii_txc_LO => rgmii_txc_LO, - rgmii_rxd_HI => rgmii_rxd_HI, - rgmii_rxd_LO => rgmii_rxd_LO, - rgmii_rx_ctl_HI => rgmii_rx_ctl_HI, - rgmii_rx_ctl_LO => rgmii_rx_ctl_LO, - rgmii_rxc => rgmii_rxc, - s_axi_aclk => s_axi_aclk, - rx_axis_mac_tdata => rx_axis_mac_tdata, - tx_axis_mac_tdata => tx_axis_mac_tdata, - tx_axis_mac_tstrb => tx_axis_mac_tstrb, - rx_axis_mac_tstrb => rx_axis_mac_tstrb, - MdoEn => MdoEn, - Mdo => Mdo, - Mdi => Mdi, - Mdc => Mdc, - s_axi_araddr => s_axi_araddr, - s_axi_arready => s_axi_arready, - s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr => s_axi_awaddr, - s_axi_awready => s_axi_awready, - s_axi_awvalid => s_axi_awvalid, - s_axi_bready => s_axi_bready, - s_axi_bresp => s_axi_bresp, - s_axi_bvalid => s_axi_bvalid, - s_axi_rdata => s_axi_rdata, - s_axi_rready => s_axi_rready, - s_axi_rresp => s_axi_rresp, - s_axi_rvalid => s_axi_rvalid, - s_axi_wdata => s_axi_wdata, - s_axi_wready => s_axi_wready, - s_axi_wvalid => s_axi_wvalid -); - ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE/ipm/component.pickle b/fpga/ip/gTSE/ipm/component.pickle deleted file mode 100644 index 9dd92407df04da73e7c2a2f3d595ab1fdf898084..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 85117 zcmeHw378yLedkD;(Hy!ZTb7M%7qPJAV9j**j7BrU!k(jN)X`k@v}`E})K+&_cU7q` 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zg9nPc_U&vhw(sA&cmL36ad+Fup7zn*ql3GLMtAMnzi;2Z(Ve5k(c;LSo$S~4{i8eg zkG2mDA80$!*1o5GZ`%m_XL0|ow$YK{o$dRE_YRK??c6s!v~Os5bpP%H?Ys6KII#b~ Yfwtnlk^Osj5A7e?x%a@H!O_A02l}}BwEzGB diff --git a/fpga/ip/gTSE_1to2_switch/.gitignore b/fpga/ip/gTSE_1to2_switch/.gitignore new file mode 100644 index 0000000..4e31dc3 --- /dev/null +++ b/fpga/ip/gTSE_1to2_switch/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!settings.json \ No newline at end of file diff --git a/fpga/ip/gTSE_1to2_switch/axi_interconnect.vh b/fpga/ip/gTSE_1to2_switch/axi_interconnect.vh deleted file mode 100644 index 4163a66..0000000 --- a/fpga/ip/gTSE_1to2_switch/axi_interconnect.vh +++ /dev/null @@ -1,2 +0,0 @@ -localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h200,32'h0}; -localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd8,32'd9}; \ No newline at end of file diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch.v b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch.v deleted file mode 100644 index 2046f49..0000000 --- a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch.v +++ /dev/null @@ -1,1269 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -`define IP_UUID _c22db128920343a0ae5b4fc5c7fb0e16 -`define IP_NAME_CONCAT(a,b) a``b -`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) -module gTSE_1to2_switch -( - input rst_n, - input clk, - input [0:0] s_axi_awvalid, - input [31:0] s_axi_awaddr, - input [1:0] s_axi_awlock, - output [0:0] s_axi_awready, - input [0:0] s_axi_arvalid, - input [31:0] s_axi_araddr, - input [1:0] s_axi_arlock, - output [0:0] s_axi_arready, - input [0:0] s_axi_wvalid, - input [0:0] s_axi_wlast, - input [7:0] s_axi_wid, - input [0:0] s_axi_bready, - output [1:0] s_axi_bresp, - input [0:0] s_axi_rready, - output [7:0] s_axi_bid, - output [7:0] s_axi_rid, - input [31:0] s_axi_wdata, - output [31:0] s_axi_rdata, - output [1:0] s_axi_rresp, - output [0:0] s_axi_bvalid, - output [0:0] s_axi_rvalid, - output [0:0] s_axi_rlast, - input [3:0] s_axi_wstrb, - output [1:0] m_axi_awvalid, - output [63:0] m_axi_awaddr, - output [3:0] m_axi_awlock, - input [1:0] m_axi_awready, - output [1:0] m_axi_arvalid, - output [63:0] m_axi_araddr, - output [3:0] m_axi_arlock, - input [1:0] m_axi_arready, - output [1:0] m_axi_wvalid, - output [1:0] m_axi_wlast, - output [1:0] m_axi_bready, - input [3:0] m_axi_bresp, - output [1:0] m_axi_rready, - input [15:0] m_axi_bid, - input [15:0] m_axi_rid, - output [63:0] m_axi_wdata, - input [63:0] m_axi_rdata, - input [3:0] m_axi_rresp, - input [1:0] m_axi_bvalid, - input [1:0] m_axi_rvalid, - input [1:0] m_axi_rlast, - output [7:0] m_axi_wstrb, - input [1:0] m_axi_wready, - output [0:0] s_axi_wready -); -`IP_MODULE_NAME(efx_axi_interconnect) -#( - .ARB_MODE ("ROUND_ROBIN_1"), - .S_PORTS (1), - .DATA_WIDTH (32), - .ADDR_WIDTH (32), - .M_PORTS (2), - .ID_WIDTH (8), - .USER_WIDTH (3), - .PROTOCOL ("AXI4_LITE") -) -u_efx_axi_interconnect -( - .rst_n ( rst_n ), - .clk ( clk ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awlock ( s_axi_awlock ), - .s_axi_awready ( s_axi_awready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arlock ( s_axi_arlock ), - .s_axi_arready ( s_axi_arready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_wlast ( s_axi_wlast ), - .s_axi_wid ( s_axi_wid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_rready ( s_axi_rready ), - .s_axi_bid ( s_axi_bid ), - .s_axi_rid ( s_axi_rid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rlast ( s_axi_rlast ), - .s_axi_wstrb ( s_axi_wstrb ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awready ( m_axi_awready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arready ( m_axi_arready ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_bready ( m_axi_bready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_rready ( m_axi_rready ), - .m_axi_bid ( m_axi_bid ), - .m_axi_rid ( m_axi_rid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wready ( m_axi_wready ), - .s_axi_wready ( s_axi_wready ) -); -endmodule - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -k0MNGAL+siJuDYrFA58rRJscMTUE6hiuNEylu7uA+mdVk/vCPJpUprjqZIgJ75i6 -csRX146zVh4AUQABC09rbvto0kqPbqsZwZGmdOm1W8NmGZIXLCsG4MZs984TiToI -QMOSc+XFr9GVx1rFODfIQCsRVOla6WZCpHrBZzFjmFwY4t9fXFQCs5fSkNbGyG6v -8YDvdegFPMYp5Qu9ccfxeosyrpdCBompAmWscbYmzMrmyFiInvb8Y5dyqCuve1NW -jirl6fz1954ypdomnZDn+X9k8zTCJAxovyf9Qxk6Q+/Pf6e6yRqEYBxT7dtZhWRG -tEQdKP3bt5KBf+EuwdVLuQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) -`pragma protect data_block -CosGYIkH0xBRxN95EJWx839RlT4VAi4LCJZ1mt3NitRA5g2pDgJLsvVh2D1y5BVA -pdFnLxJlKeO8VGxcbjdy9+FeBPs3Bo0hcGMo8L+LaJ0bVkv+6b77n30HN7W4KS8h -FD1Ep9sROiwLtXRFHJO89i05/tAaQLM8i1caOwWOyxnOkkN9uNWnXu8Q0YVHwDSo -6edwH6pDm7sUFDB7MkilS2mpOjdUBdlO7TGkRl9TuEENWQoMfIDEVtwj5ArywPyR -ABP441amQzUHEwhfDKcPN2iMoBL+T+S1wuWnJHqvzHEb6nVPARgwM2LxvxR9dJld -dNlxyS3zC6MHchUMEAThn6/mNnJEIrcrJfsvf1vvLfpUlQ5d+C8Gj2KcQl4cX+1i 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parameter ARB_MODE = "PRIORITY", - parameter S_PORTS = 1, - parameter M_PORTS = 8, - parameter ID_WIDTH = 8, - parameter DATA_WIDTH = 32, - parameter USER_WIDTH = 3, - parameter ADDR_WIDTH = 32, - parameter M_REGIONS = 1, - parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, - parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, - parameter STRB_WIDTH = DATA_WIDTH/8 -) ( - input wire clk, - input wire rst_n, - input wire [S_PORTS-1:0] s_axi_awvalid, - input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [S_PORTS*3-1:0] s_axi_awprot, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, - input wire [S_PORTS*2-1:0] s_axi_awburst, - input wire [S_PORTS*8-1:0] s_axi_awlen, - input wire [S_PORTS*3-1:0] s_axi_awsize, - input wire [S_PORTS*4-1:0] s_axi_awcache, - input wire [S_PORTS*4-1:0] s_axi_awqos, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, - input wire [S_PORTS*2-1:0] s_axi_awlock, - output reg [S_PORTS-1:0] s_axi_awready, - input wire [S_PORTS-1:0] s_axi_wvalid, - input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, - input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, - input wire [S_PORTS-1:0] s_axi_wlast, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, - output wire [S_PORTS-1:0] s_axi_wready, - input wire [S_PORTS-1:0] s_axi_bready, - output wire [S_PORTS*2-1:0] s_axi_bresp, - output reg [S_PORTS-1:0] s_axi_bvalid, - output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, - output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, - input wire [S_PORTS-1:0] s_axi_arvalid, - input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, - input wire [S_PORTS*3-1:0] s_axi_arprot, - input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, - input wire [S_PORTS*2-1:0] s_axi_arburst, - input wire [S_PORTS*8-1:0] s_axi_arlen, - input wire [S_PORTS*3-1:0] s_axi_arsize, - input wire [S_PORTS*4-1:0] s_axi_arcache, - input wire [S_PORTS*4-1:0] s_axi_arqos, - input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, - input wire [S_PORTS*2-1:0] s_axi_arlock, - output reg [S_PORTS-1:0] s_axi_arready, - input wire [S_PORTS-1:0] s_axi_rready, - output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, - output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, - output wire [S_PORTS*2-1:0] s_axi_rresp, - output wire [S_PORTS-1:0] s_axi_rvalid, - output wire [S_PORTS-1:0] s_axi_rlast, - output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, - output reg [M_PORTS-1:0] m_axi_awvalid, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, - output wire [M_PORTS*2-1:0] m_axi_awburst, - output wire [M_PORTS*8-1:0] m_axi_awlen, - output wire [M_PORTS*3-1:0] m_axi_awsize, - output wire [M_PORTS*4-1:0] m_axi_awcache, - output wire [M_PORTS*4-1:0] m_axi_awqos, - output wire [M_PORTS*4-1:0] m_axi_awregion, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, - output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [M_PORTS*3-1:0] m_axi_awprot, - output wire [M_PORTS*2-1:0] m_axi_awlock, - input wire [M_PORTS-1:0] m_axi_awready, - output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, - output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, - output wire [M_PORTS-1:0] m_axi_wvalid, - output wire [M_PORTS-1:0] m_axi_wlast, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, - input wire [M_PORTS-1:0] m_axi_wready, - input wire [M_PORTS*2-1:0] m_axi_bresp, - input wire [M_PORTS-1:0] m_axi_bvalid, - input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, - input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, - output reg [M_PORTS-1:0] m_axi_bready, - output reg [M_PORTS-1:0] m_axi_arvalid, - output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, - output wire [M_PORTS*2-1:0] m_axi_arburst, - output wire [M_PORTS*8-1:0] m_axi_arlen, - output wire [M_PORTS*3-1:0] m_axi_arsize, - output wire [M_PORTS*4-1:0] m_axi_arcache, - output wire [M_PORTS*4-1:0] m_axi_arqos, - output wire [M_PORTS*4-1:0] m_axi_arregion, - output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, - output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, - output wire [M_PORTS*3-1:0] m_axi_arprot, - output wire [M_PORTS*2-1:0] m_axi_arlock, - input wire [M_PORTS-1:0] m_axi_arready, - input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, - input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, - input wire [M_PORTS*2-1:0] m_axi_rresp, - input wire [M_PORTS-1:0] m_axi_rvalid, - input wire [M_PORTS-1:0] m_axi_rlast, - input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, - output wire [M_PORTS-1:0] m_axi_rready -); -`include "axi_interconnect.vh" -parameter S_PORTS_WIDTH = clog2(S_PORTS); -parameter M_PORTS_WIDTH = clog2(M_PORTS); -parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); -parameter IDLE = 0, - PORT_GRANT = 1, - ADDR_DECODE = 2, - WR_FORWARD = 3, - WR_RESPONSE = 4, - RD_REQUEST = 5, - RD_RETURN = 6, - DRP_REQUEST = 7, - DRP_WAIT = 8, - END_WAIT = 9; -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -f0DVmU/kdU862C3ryhjQlDsM4c/0bG91GM/Tt0YfOziNIhVBbdZsoYW2RTSSEC81 -yNXUBt7tFmZq4YDopiOye7MWsFmf8WWRQEL3slo6DkYqzPlqCgnjys82AVws5Cco -WGW89TXAcQAYHJy7oG8Ae9oSMdLa3PIQNp7mSA6rz4RhAKHQyvxQU3wr0zXDmYKl -CeyI1ZIu155HAUZL2bXguauGtJWtwaTXIrQO4i5/hXied5l3pm8lCdXsKbM1Enxx -V3E/sk/RBAVETx2fmYxracwCdN363LHRvYHyP4b2qkmUndhj47mK2s4d6wc/G0IJ -HQRhooSUf5bQscVy4yyOxw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 24464 ) -`pragma protect data_block -VTq/qeL5rbYMXcLz0pVnq2QU7OySLW7WR1ySFBochA6uqctGyUZMjS/Pnq7DeDQA -s5ClOKMV4s33FMhzgVOQol94f7qpRytPtHwO4wJfN4F2g5QpANsEk5OSaLDZaL+T -9JNTHQOahODVVMjsEwLu3Hf3nxQqnUpY1Jq2hY3IPT9HQw+jYUbU1mwaaPtk3z/B -wfByi6gTuDXLRhTsDy9zF2v2hyVz2yDuu+x9TSJkxCf5Ivowir1LIvj5/3PTq70h -N6f3RfvSBCkVywuTW3T7/OhSi8wnLfdctcCOumE1svbUYFgxg4J2eKZs7MjC0kx9 -BSZcpQPmbuAEPr0X4s1LPhIA3vVVwZzzfsgimy/Xg5Jay4omrboBZMNf9zoz/upT -CWeKBGZMPg7uyDy+H3GpdRNVVeOleOFSVrU/4KbsSuM7/fgKqbwL1vbL3FoZihPh -ldxqCnYv2m//sJpbeK3FtM5xLVdzq8u7WgS2RNd0wbzqdcIbA5ahg4/wV5r22Zo3 -pDP2uVlZvB4LOCQM7VnNmxqVSUNOdZrdkfxscccugLwsZ/LRvxbuw3GVqzFEQGGl -FBnm83T00BwwWMh3yKaRmz9mYY8xXcUOaZ9cgJpRVvfKPq/yHCtnHgXpEEkbHFoC -p3eSX44fIQ/EIHBkJ6jvFyA61OKdjC0gsAj02XudRxsxq76JhRuRBETksNXiKo1k -txGlub+1WwXw3GYTDyjs23iROrf853eo1PTW2BocqDzdb6AFB8CkhQIM8lKkRJFe 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-9U/fwZ1Aw573Y8yV23mCoVz+46CizX1R0tt8RsiUUuJRedZuXpdgmloXHSwHqVir -4TeoeKbJ5TabI9wAUk5DudmB5BBA5WQUXbk863Vmp6ZrYuTLfrMjZIX9wugW7G99 -XjupmycimgGdDcwkPXsuhcn+y+kypAeSBT8BmORPoMB3GBQcBFCpksISgnzfj9Df -f88VaFEwPw6WYPsr5zD3qmYV2Wcsa1+AXMyVWEud3OibijB/ydovxfhoylxzubgq -c5dWawXZrm5RAj6OLUtonq8ExeCxZUVesAT41fPbsmxPMODfaNW5FbLVC3kqoKSR -/vBOG3e/0w29HIfCe3INg/hQVqRtqNawZuPB3U4eg6mkDZO0y9woSZUx+4YHiEnU -NTXJ5dCxVSwAc1bY/Ip6OLqp0SL7pbJLVLOZcdpgE5tqhkRt2TK3t44YBFUW+niA -+7vUO6hk9FiP9bQI/e7mVqrPotPqBtZ/BYUCVLnHL1JkdNsfhSH93PbRBOL30thr -a/CDhbsHwqYjqkrPHUZbNL6xs3s1Ebn/iXs+MoUC0UijkUhThusSGW3zplPE0G54 -0jWIUjvdB/4anXrEkP0+JFchB+2p29bDA6M6GqPIVL5rQWDi/hZj7Jo0GIXXkCmh -pvHuQ5Figaz8huMCbW3V2iIeCWQtEZCIlkqcyGu/srkMp8Qy6LofUqNL4sudqhPx -f4uyi9jp8NVnv5ItQ16FzQScH1btWx693lWnmb0+Z2LTNY3edWuP30Cn2zr10hQO -93mjE8j8xiqRmhLimsfa03ja3y1M5RFuYdaN/LBTd4fTOYAzlN0jlO+qU0fuEZpk -uQWrVWtrciib0QKfC1g20lTslFmwF9dosu8yjarIqZXr+RJVRJ+dXzaC9RXCMNZb -65UcvJNvzjdQOIPUdQcFIuSQwWUnMe5P8kikQsxEZuT+BErj9Pt17T+HPstvcsd4 -mLxzNtdOSZuENCu1k9eImFqEVVl2odtXcLBE6f8fS1rDtjNUupb+m5h+WR63QHid -eDln4z8ShnayiKhW6xp0jj2dUvWnOyhQwZWRP8m/EmfeFO7gYiIw1SxDD/ZqH364 -PzVEZruTbQ4jUKjpfHxf9WBgIVrEYTPTBjPjxaZbhfA= -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -gQ+VauIuH+g40FNOpVzoPSXPaSSXzZWh6rE+e4zt/Higof5lTVqndEO2y+vyS/HT -Uz3/xsHmLa5/hfJOzrQ2WAbWJcFOc0pzmbDqYnUgEw1W4IUS1qcjifpXTLdxvwfy -rSWd00QRecQN7v+pyLFb6xf5TELzzsB2PAr6/xlRVs03sGcC8jpFMP1gppLRrh+C -xnDjMIBVdGmu01tJ1gcEY/913addbws7HLgMcMDLft0U/4zTbjE/rrDoC7+eO+3k -z9ZPUNkRvEPxurfsVZfIuglJuZJSqyaB+Khmc5Q1nMDb9IswcttQUM3RtjEksR13 -Y4OcKLh/ejWsVorB6JLJeA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) -`pragma protect data_block -fo0JdXfIQsWgrENhFGo0RRW9s/IV4eGBK5upzSxFjRkxTj+wCit1QKkd15jJgDu4 -P06Rnw+P2/Cu/tkXRjH7RGfSCa1EZ08cwLiSykEmyb+qQo8wTkOBh8KIag5m0P1t -XTuNeK4lZP50EUwL/4wSSMPuRtdpIAF+0PAXjdoge2gwhduxtVQZpgPO12dwk0Wo -Qyfuxrm/7iyjiETt18QCBk/PXC9JLX6a9hmtr8ujb+7IKQJFj1S7F9WxCZ1yamDs -e1D+l34aYZ5r3sBbAysWrg65oN3fAAd6bhptfeU2+BDBA8oKIcTClBK2f3pBUPul -8YV5xUU0+FGat/Rjkm2ZmKKpm9JD+w7ufesbJ2fqRCCex08yynx+EuV6lNupQQk3 -UbxIK2+04eVmLtY7V87103cxyVnLFXqAQY3XaG0AWBpO2Ew1NwH6CU4yFpyUAC84 -Bjztc1mHKONeueopzONq61tRDqarI0ex6IhDy04D9/zAOhMyBrEHzeR0UozXtK6Y -TB/qqFBgJmagIMQWcL03s2FYWQgGUU3PRQ4JiB57ubJG6H64M9UJUMXI7VXW245F -S0oLuBSWchTwY4/6zvioNieoCZgdkxOTUqHNuV4Zf7Epcgh3IQIZRzjBSpah3skn -kQwLdkHYbh3EzBAN0L4lF8u4LE/8SqwLPpsl91D8Qck2jzgNTYnbsG+t2tsum6n8 -wYvw9H2G6SCXAimDrg2Qy66lpdDA8XQf+1Pu8sYKlEd3GH9lQyGX+l4gx3OLuOtR -fAlYbOhHnFRDXMNE9ZG/I8VKDFToJD1/SjoKUnrz4TdMcQZn3Asrj6LyXsw5CHgd -zhf60BREHK5nXIJRGkqTlV0OyCbaEe0yTgmpWapYbnUcpX4UNu07ijUdSbUBReil -f2PULQwchd1Nh+nj49FyRm0SU4twHeYIMoSC2sMtPiJkuqAZPugzpBpKZUPnKzDd -VmHxPV5Fl4haVbGLfQj4rfl6Mqpqk2DLOiPmwiXnf7CTAjpnwNQ07KsBw6SKxLAe -YS+1RZFe1JQTA73Dv+hAjOEby2uC1tz9V61abAakI4omdhXK1WBGS7AW7VIkOhsa -U2d43C1vqygKdJzTQVB3SVqswMzruIiClRGEypfl8F1L7BIegRA7y6KJYY2lQ69u -7eDX8XmDYmXDiWgXqtWRALbhHrDi8EwOCp5Tts6KK1q+HZNB6UjiGUrGZ2/EhU4H -rNhfbS8YD9wTQtEs/QCi40wIeLIYjIf429BBIRU8k3na6ZwzGLdfxJnqsRLJ6E7X -aCiJk8iag4Wfv0HsAb9J8vDUKzzLHS5OYlHmEss6CTswBAYs7u8/UF9rlfvXy8Mb -z5tfh7xCXqOQpY1gF85w0agvdFKLhhUzfB2Y/XiH+P9zw8608Q4B2irkUuj0fbhU -/VGCOg52ghhNNkaio6JDtzCj/4nMf3QJwdYnJNTiSWLmN/D4rgU8FE7RObm2foEA -5qemSiCt9nYnRGtaRQ0jFh1zieourorN3TI49Lfh/b++M/Hq8OUZh7Uxs5ni4scB -RqEGxATE+29gCCCJ1S3HVi7fcit9xh2mupZnT+m3qHM+Jt01sv59AUJ/UFx/cNYz -qo1oB/NkzOstxVDMlcp8bOO+elF1X4n4wKeC0g/eMM8C+ffQiVT7Rqh2mYLgXQA7 -BhBS+E0RB6UhkxYPnRFEgtk0VLL54VPEVDTINYlLs+L3ZsWwYJs39Gen6vvvepYy -bujDTnnouQqtvD9ok3pkbA== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TpRHXtmr81JyoWaAtQOsoLu44jF5UvFDPdO5/CllOd3kdY7PwU2fkKx7bS6RlGe6 -282Wvc58pPBGh6uImNRfZkaAKTaspN+giuR1GHAo4nfIKi92dgY2DTW5JbEU67ml -1IGNiK4su606fm7n90PZ69MZadoZPNpUxZxzYbSs+I39eZWsgU+rtoUE2d35qjdW -UyorSD+O2F5Wv51CWlcWJyscNK886BFGFi72CtEY8IdYcolZ7hcONOhQT5jbhGWK -UFFTqjnMO6iVrEodujVvUgcUtFQSTl5/oHSkmacP7CSADA82+06uIHf+rByqHGTp -JNgtSAVN844IRP39n4T5EA== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) -`pragma protect data_block -dW2N/rFxim9wkWiMqoV2KfFOb7ryaosiEjsKQ5d9XAY99bfh9dHXfxBwbIc/m/4e -C1jjMt+51lGF8ncrYuentPA6MwNEfk27Jwvqv9/Trdq+kOdiWuYmhbZxfJC2L3WJ -BzjhoC/o2ZNSFpgmDKLxln0/pf6iM8sUIldzujq1RDEv/fZvcQ9IXZ0c0cgbXEWf -SfOaD5E2qBGsljqkzqzIKjaiTPnGPsKJ6cZ41jLGbcm+AcbSk6th9Vdeim0hCA9t -HjX+E+Tq77j/ivdd5OuzAehdPAg3IiMJTQxdTNsI3km5GzvomnmxK+pG8L9aCaAh -o+hCsSXZD2QyVCRFZjVT4s0ltvRto5PgSDzzqm1N69eUDE/spFnroMx1TQCLbjBT -zS0w4mCeLkzFlxc0DJduqQlnRMlA8AnBFujD/Q2OAdVMSHQC7YscXbPzF31GPlqx -Eg2t/VyotaMLOGG0wG7ax43UokgdGbSuphzh14sCh3ZSbPueJQLw2MQwK5M2gcvg -/OCrpP6ZQDt10hFz8i/uLrgNIWA93ZzqujdUnYXBBCwUzRJEyHSLnlXX6Ko3rzE5 -ct8FuQPGV8vF+t6COL2nQ0qaq+23R5E5PuFtEMyRrDT+p8iXZasw8RECO0NyVnEE -YuX0T1i6imJS88oOkLq+ywGLgMFC+4O26DIlpPh4+UJ/fnt/pVOADhugk3UeF+QA -ZDR1sgxihCZe9rP7QzVpjm2tDiaPt+fklsKWPprWH2eAiuNaia9mSSHNYGF2x2lD -9h3FKeV/2LSUG5mOvvl3sgKhV2fY0MuldurIH+utuZSPbknY3sebf3BKCntClVOm -6zvNgcnFtvD2+A79A8sltui4gm5GYPS2b0YDfju51vT0iTsCH30p3LWNEG/zEtf2 -48bHsr15Z/CgHdw169NsY8B3V8RHxaJP+T6zbPLBjVmRFbuTftozxf/dv+m7Rgl2 -3kmwmDxauFLyklSGjQ352H678ASYS37eMG1wvn3akQjYEAsrQTdi1sxmk6SACmSb -Ko7v8gOZpn886AO3O4V3iIggxtfGIfRMtOXcoEIX6dRl5GdFkcASHigHwoV56yRO -tlfJEHrrKLKbmqhjLMjDz5jTptQZfwCjZGzki/PYImxPv0ay8+PTa/qXEaJEMsWZ -vWEGZGSO9zphfmPXEJI+qF22X0dYlKGn/U8rzBEsdcxIXyGWQwBJvbo+GhnPURiQ -i1MJHwfOEDztC3XemmsQeaMuSDWZFrnOKXuYkOBj7tD8ir7vJOor8isvwQUz9LGK -g5Vx+0HdaBgE32QEZ/NjYA1V6bM0iUHz9e9qzEVqN/kRww8HFXA6SnpD5lz6hyxy -jFVRtphwYQWmSzwLvFWa2AYQuI4xjU7tJKOCZRqxjD4hiIkjDK6/K/01Gk5QL/3K -12xoSmqSIZRHwxFGBoHiuBmy+wBhSdqqIOdJ/OsoBT+1OwzQ24l0CRjfAk+zBdVi -7A89GoA5JGSeX8OCJopZvuJ/kEWBUL+l+AU3S9Z4l0uVYybFXE7WXuTNCWRjCQFQ -DmofPA/+XPmyr1MT/3DpFQgnMN00C/jJ1eRmmSntrjCcYaPS0vX117igGa1YWfcD -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TBCX5/gAT5S6xdVBuY05hYDsXmHLnm/0Yl4d4ayUlKrDe3IUWB3JcRtZJEwtIwhQ -wqO6qIYs21XvVt74eCxdt1SZXHRXXJiT196fD9q5vFrJxAQqeTDvH51bmshhKW+i -DwXpMTwZlLgBsT2BEP5C0RiiICy9chJTycHB7vHEh6lTXT6S/2H7bweTMlFCh6s6 -n5aHgBbfjk9BYIUSTuEvOxw9Yki0T44zjqGmjZ3qxkhk5Rae8iPLqCnjRTjNfqOE -zQtaoVQW+8NbATVUmZC4WlgxF/J03hq0TLeqLYfcuWR0uH9vLAWsUzHqlGMZvUSV -23zwmB8p0BqUeaj1cllyzw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) -`pragma protect data_block -2OvJlNYOCu/okutbEvWbuQI4X9C4wmVA84hW5XRuqc+R7lDXEYZ89g58fT3Wyd8M -ecpTY/f/5J++NaepFO9rZ71cRzxgXD7ZQypxrBwT8eXz6kwhomKLL8xgQuGMrD2h -002LEC5h770bZFbr2QDl94Kd8oWweGDIcwbbPgGtsgfsrwnZq107rvdgRLsvDJ6H -A9T68XpAsV83OJOA8hk5S1ytXOtMoD1vxUA9NgZ2d9BBiwxnfNC6r2DYa/TpgT+F -8Dlnu2u3Ch2T50E1FvIsU2NsOkKdsN8k6Nmhr7J+mWrK8q1RSElNbQt02yIshAzD -fz1m7maxuzNvKiofs7xTJYH5Zl3jsRgP4i3jUPcFIYQTdju0XGFuzz4tT0y3o98B -wJPQRdZzLdAIRwwOeqCGe94DNj6v4B0lCOW+L2I2xO/Zd85RIWk0KQ11TMBxIioX -lElgvMwoYdOobLmpseg4vchu9jvsSwd1ET14HpSefqoM8cHFSvGA3j0KpwHUHD6N -cAg2z8pkpvWyZBxPOnKrjjHml3gwE3q+X2mtD1ayi41L4xn6E8czI/znMUiRwwcz -u/UG8I65XcONtBswjX1cTAad9X9cP37rq7ly/mnCVaQ1fwdx50rBY6tOiF0jiVR5 -JjSBl4FkBYJu7kHqA7DcluE9ATZ1+D+BIfESxs4o+MIGiPbk2VMeafwTD7GkJFOt -pp85p5WDA/qQLIA+aQsaHfBRLInMjsajsBU1Nnr1Z2FuT4dNgRDU1JiEJoiGBh4S -RZzlhgVKqLQdDiC5KHU60BMuW3u1CxkP6BLofYO1/DTsIOzKRlb9s3+Bx2RBLO+X -LpI1kmPdmyjjLOe9xPxUuWAlk4Ona2bF7SOrCRKslzRwj5WK3kdfynnrqi6fyg/g -6RtRb5T19kv8xkX8Q0Nu2f6aIj9NFg8R8LJhXh6X45cptFvZzqgrDrKouB2qeqzv -r/ARvwCCrLhqU1Rwol3o14E8rmlZcjNTDxMVbtGHIC6f+FQD8Ge6dA7TLtOmbzhg -ADyiBfAGChDV8d6/1Hzt1ZCbp6C5hSA43mtpTQYEjZcGds4olsLWRMFlvn6SaE8U -/yc4f8I5aqNLijlkaO5yVtVndDXvrhyJK63yxQ2hv4wjwsq4K2PDQ4XYvUcmKPD/ -XlPlsS9Ze38WOmF18BNsWhFg/X1ZEsnJQZqQFknQ9z/lHiYTcq+HtWHD6JfZzOaM -E3UA8T88Db5hkBxdi+VdfTfF/tcJB9TVv94cA8SuyNnP6Q6AMPtj4AcaMmUbLwpN -6fOz+eRjs375gUjeGtSoPhbJZ6VvJjLK6xs1mDGS9ROACnxpeDCou3/Z35w98hvB -+vycfefBU/3Oz/FibzGZfGGRZxR88DoezSovO8xS1UTztbTV/E3Hf50BgcR927BL -NJGAapWYDd8JtV0BHG5wpaes7/XmU1ypZarztFE+5fUtgzp4AKZ9d8fLPqu7uHyy -VFSlknUG3lKAvV+aTv5kwTm6T24a0lpxxYWzaadSBxuqeJtU7FNijzCia9l+KD/j -MuWIX01bTZapbrnUlFm4fAAgbW5f3nA4jSdhRz4mKzYdZ4aMWDM8hBS+zHKdAxt+ -r3IOTmKOM53qQd6/AzPhoA0A+KC7CNCPEgYxWjHD9LvdybgmZ3XenDSbtLwQbD6Q -UwWAn1xKUS+VTfDL9VkVXP1CneqLQxZtc1Sc/vBPwSJ6+7jAYG5QfCsFKpYk6KVg -WWBjX/iaBk51jQZ/ISopM3fO5XEr5/3lYtazRsrg0f+S3e4Zzo8nxEOq9P5xVhSQ -O7JVUzPKxB+mq8b8+Trp0jpdlwATuoCmknWv7M7xGQxIxgYlBegfgpZNrb4ocJt1 -C2A5oMK874OASkTuFy/CZtTCSKDyyC2WSUJy/ybgFlZWnTyWBNaSIgYpaI2Gq/5N -W2sAGdn2IzwgLXJcE2TeXPkUP8I6D0EvyGS8UJ8WVt4jXlr/F3VEInfxr2Y6siXk -AHHFHgrTgDIGLtO8E808PqkxvLBmGkuPh75G6ryBOPonCZ0aT1e/GX3dbFPpEaEW -llXDZSgbk2fjRwniN+3OtnrHeVbQUlTC3iaVcpJd1hL8XMqXbPIDInH7Hno0Rp0/ -Voc9LaQvrTj/kEwf26rJMPkHP3A/gue3fawMlgP2mdiTeVrBYqtURRsKaMlxgKT3 -3O7Gyd/yxwB05GETZ6zA/3Z0q4ztIi5TZ5m+C2wW+NIXwkcYJdqHOodrO1fkRlTs -npvFlNq1Br3v3gImbnvFaouFkT+542lb5sOY50i4uwrifKPntqOl0n9+dE1pyipU -QURHoCbkL2QR65H1hYcDoLRvhJAfS/oEFf4DSf8HgiZITq5pSvnYcJn76jC0mNiX -9LRJqxBuOkHcdFIbmkvDuwIN0asrQmGQCAsYOOxVA6EpX0XWcJ8dVmRyWbGVZXNq -45wAMvGDj0F6Jm7b2sQ3quJFDXDWvD7hPWp8nLqRDN+P/s9tHqK5LMXPHFdcqMn4 -hKSmCVgEtnsVfWUGyjVJ0Yvh+jxdg3vECIO38UuFBuTGroD0egvsyd7iuwT3aOmn -5YaYW0vHuHERbtLy6AkO1sVVmg18jSH32tE036uQS+LCrj+G0cg6Mf5sU2CHJZA0 -9Jse9KsUSQdI7bnqvPdYIQ== -`pragma protect end_protected - -//pragma protect end - - -//pragma protect -//pragma protect begin - -/* Encryption Envelope */ - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -eiP/26NloMbfJbEe1aU/cN+AkTVidxKZaNv824TVZXkpjf5L1zEVLf4buBzXwSr1 -MiO1FaB1qgL+ZgKHLwNzc4IiIP0d7qYOaGR46jDr8/k9N2BVxXC3V0wJJ6yhDom9 -O7B9d2Lcm+b0UifdEaFcX3luTwZzXAQW83Bggnm4eVP275Vqog3REHo5wgsstEU3 -AG6o+oVDnNjZTPDPyJ4uHq9bjFFyvY3ga+lOo2iVymecnhCiRtjy3AFtvWBJW0ek -uhj8QvNYf04TXkRXdhdRfq/HDLr3M6Qa7/Xn6vGE+drFyRTL1nmH9wkjBBbD3swn -58tiwvvx3ajgMOCJeXfrXQ== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) -`pragma protect data_block -z83CFN/6+XAqqlsaR10y0/0TRdqihm7Mln1SErDagYzHq/tf3472iVn71ufDnRwX -XjpfuAMiYkGYL+YySToA+S247ZqaWHze8oceixrYgRvhox5tY82fxq9Fl8kghDLv -SjC2MS3eD6cYQeQLFqzD1Mn0WKOQZFVCku3VAWFB2lduR5mhayfY/Fa3R/W72ABn -Z0d6Zn4ZBsgSyb/M70GpfeksPL4x3rnLEOyMOaWSU6+bpfwlHv6gwzh9HPzLZxVy -08g2U6/uxm0PBfE3o/LncY5k29GaWHkcOHv6VhXh/m8K01MJZqFeBphDIArYoxxq -PWDxAO8AUxxtI14Tgpa2V285dFMvK+4KnQioTwi0kMw0x+o+AprykzkXPkE/VVzK -KXd3WO23uskN1uRWHMVa+YBeVjuyFSDLn3GxfHH9tkFDow1kssYW0TqHWs0aqHah -qnNS7hoeJjqPZiowmyQrmDxNCJSTzH8quhzu6sXOHqjuy3hV/M2EY8gngXNAKKsb -WbOvs5QeFheEcLGYrod/Zfv9aZk0e3y0m11vKOyZVQVGFJQzc1uQ0fLjWrpSt7yG -qya4/JgJ8aoha2vBdN7gKSQ0jQBRSMhhOkv1iunq1iT+1ZETzOdrs32w7jLu65tq -rkZk2Z9PlyyFm4XlIu3ljYIH3Z1F+BdPGXiUKHiLhEHanApDED/zljh7BDGApCKl -t1zRJJjZMckJfWQclrLgdXSejbEhZFqHfgYNQe4ywo4o/SbWaqGvPgahhDBBVxZV -rvCFFNip8ka1YAIM4x0DqYw1pSFzn0sUmEm44Jl+Eo4D5chLPEJnYyAjsKm0nIFa -We3J6DKurh1q/PmPYqN51Vno2A5tlFLR8v6SH4m4qu3V3skZsRF0vR6BGx84VdVj -bN8BlLOwDEGmTO8UZpg5knVPN5bAfvf/kXvbSbr8KPR5NBZRqz3SXFeMxZYBPfbj -GI8S5ZZZeq5AvybyDwwt8BHWypNkKlsr+UxyAt+phMEA8F/U9gAt5r50llYjO4qu -5tLeotWmT7oFHBktGytHHC+gKwtWEMsJLm7+744JbDfnMvdHRr+AQgpYts9jdNY6 -guxuay2WoNBpjmE51Kq8M1xXeO6beJN3h1JAlESUfz7eFKkE8Vkr5Jg6ccn0KUsS -ZZmNyAaAta//k2mRELcX5bJmUCCHy7lAgQBjtv7XZBfyULC/eXy3RUO/ar8/VQKj -wwOLkv6PJN1DfDlpZ+oswIslScrN1ijU4t2buGKO8zI+cQCpYuC9FBN8V8chHOZw -//0ODvW7AEl6D/OUt8ZC6gUirNCSFRQjXz5x+MOrJPH54wUb0gmtQRPSsbnbcm8g -r+J90t6Fz+FSggPmyNbgv8Z+eWprb5Z3QuqJaQlTYxXGJYLXXwcTjZP3Sf58Vd4Q -9PV9zVG1BxTwV5hFTLJrTkIFGs6wyF+96e+3TnhJKuzZ4Qgf0XJPp9crAdiNtxfx -`pragma protect end_protected - -//pragma protect end - -`undef IP_UUID -`undef IP_NAME_CONCAT -`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh deleted file mode 100644 index b794024..0000000 --- a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh +++ /dev/null @@ -1,53 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -localparam ARB_MODE = "ROUND_ROBIN_1"; -localparam S_PORTS = 1; -localparam DATA_WIDTH = 32; -localparam ADDR_WIDTH = 32; -localparam M_PORTS = 2; -localparam ID_WIDTH = 8; -localparam USER_WIDTH = 3; -localparam PROTOCOL = "AXI4_LITE"; diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v deleted file mode 100644 index 1711a12..0000000 --- a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v +++ /dev/null @@ -1,97 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.1.95 -// IP Version: 5.4 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -gTSE_1to2_switch u_gTSE_1to2_switch -( - .rst_n ( rst_n ), - .clk ( clk ), - .s_axi_awvalid ( s_axi_awvalid ), - .s_axi_awaddr ( s_axi_awaddr ), - .s_axi_awlock ( s_axi_awlock ), - .s_axi_awready ( s_axi_awready ), - .s_axi_arvalid ( s_axi_arvalid ), - .s_axi_araddr ( s_axi_araddr ), - .s_axi_arlock ( s_axi_arlock ), - .s_axi_arready ( s_axi_arready ), - .s_axi_wvalid ( s_axi_wvalid ), - .s_axi_wlast ( s_axi_wlast ), - .s_axi_wid ( s_axi_wid ), - .s_axi_bready ( s_axi_bready ), - .s_axi_bresp ( s_axi_bresp ), - .s_axi_rready ( s_axi_rready ), - .s_axi_bid ( s_axi_bid ), - .s_axi_rid ( s_axi_rid ), - .s_axi_wdata ( s_axi_wdata ), - .s_axi_rdata ( s_axi_rdata ), - .s_axi_rresp ( s_axi_rresp ), - .s_axi_bvalid ( s_axi_bvalid ), - .s_axi_rvalid ( s_axi_rvalid ), - .s_axi_rlast ( s_axi_rlast ), - .s_axi_wstrb ( s_axi_wstrb ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awready ( m_axi_awready ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arready ( m_axi_arready ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_bready ( m_axi_bready ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_rready ( m_axi_rready ), - .m_axi_bid ( m_axi_bid ), - .m_axi_rid ( m_axi_rid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wready ( m_axi_wready ), - .s_axi_wready ( s_axi_wready ) -); diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd deleted file mode 100644 index 2c4910b..0000000 --- a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd +++ /dev/null @@ -1,149 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component gTSE_1to2_switch is -port ( - rst_n : in std_logic; - clk : in std_logic; - s_axi_awvalid : in std_logic_vector(0 to 0); - s_axi_awaddr : in std_logic_vector(31 downto 0); - s_axi_awlock : in std_logic_vector(1 downto 0); - s_axi_awready : out std_logic_vector(0 to 0); - s_axi_arvalid : in std_logic_vector(0 to 0); - s_axi_araddr : in std_logic_vector(31 downto 0); - s_axi_arlock : in std_logic_vector(1 downto 0); - s_axi_arready : out std_logic_vector(0 to 0); - s_axi_wvalid : in std_logic_vector(0 to 0); - s_axi_wlast : in std_logic_vector(0 to 0); - s_axi_wid : in std_logic_vector(7 downto 0); - s_axi_bready : in std_logic_vector(0 to 0); - s_axi_bresp : out std_logic_vector(1 downto 0); - s_axi_rready : in std_logic_vector(0 to 0); - s_axi_bid : out std_logic_vector(7 downto 0); - s_axi_rid : out std_logic_vector(7 downto 0); - s_axi_wdata : in std_logic_vector(31 downto 0); - s_axi_rdata : out std_logic_vector(31 downto 0); - s_axi_rresp : out std_logic_vector(1 downto 0); - s_axi_bvalid : out std_logic_vector(0 to 0); - s_axi_rvalid : out std_logic_vector(0 to 0); - s_axi_rlast : out std_logic_vector(0 to 0); - s_axi_wstrb : in std_logic_vector(3 downto 0); - m_axi_awvalid : out std_logic_vector(1 downto 0); - m_axi_awaddr : out std_logic_vector(63 downto 0); - m_axi_awlock : out std_logic_vector(3 downto 0); - m_axi_awready : in std_logic_vector(1 downto 0); - m_axi_arvalid : out std_logic_vector(1 downto 0); - m_axi_araddr : out std_logic_vector(63 downto 0); - m_axi_arlock : out std_logic_vector(3 downto 0); - m_axi_arready : in std_logic_vector(1 downto 0); - m_axi_wvalid : out std_logic_vector(1 downto 0); - m_axi_wlast : out std_logic_vector(1 downto 0); - m_axi_bready : out std_logic_vector(1 downto 0); - m_axi_bresp : in std_logic_vector(3 downto 0); - m_axi_rready : out std_logic_vector(1 downto 0); - m_axi_bid : in std_logic_vector(15 downto 0); - m_axi_rid : in std_logic_vector(15 downto 0); - m_axi_wdata : out std_logic_vector(63 downto 0); - m_axi_rdata : in std_logic_vector(63 downto 0); - m_axi_rresp : in std_logic_vector(3 downto 0); - m_axi_bvalid : in std_logic_vector(1 downto 0); - m_axi_rvalid : in std_logic_vector(1 downto 0); - m_axi_rlast : in std_logic_vector(1 downto 0); - m_axi_wstrb : out std_logic_vector(7 downto 0); - m_axi_wready : in std_logic_vector(1 downto 0); - s_axi_wready : out std_logic_vector(0 to 0) -); -end component gTSE_1to2_switch; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_gTSE_1to2_switch : gTSE_1to2_switch -port map ( - rst_n => rst_n, - clk => clk, - s_axi_awvalid => s_axi_awvalid, - s_axi_awaddr => s_axi_awaddr, - s_axi_awlock => s_axi_awlock, - s_axi_awready => s_axi_awready, - s_axi_arvalid => s_axi_arvalid, - s_axi_araddr => s_axi_araddr, - s_axi_arlock => s_axi_arlock, - s_axi_arready => s_axi_arready, - s_axi_wvalid => s_axi_wvalid, - s_axi_wlast => s_axi_wlast, - s_axi_wid => s_axi_wid, - s_axi_bready => s_axi_bready, - s_axi_bresp => s_axi_bresp, - s_axi_rready => s_axi_rready, - s_axi_bid => s_axi_bid, - s_axi_rid => s_axi_rid, - s_axi_wdata => s_axi_wdata, - s_axi_rdata => s_axi_rdata, - s_axi_rresp => s_axi_rresp, - s_axi_bvalid => s_axi_bvalid, - s_axi_rvalid => s_axi_rvalid, - s_axi_rlast => s_axi_rlast, - s_axi_wstrb => s_axi_wstrb, - m_axi_awvalid => m_axi_awvalid, - m_axi_awaddr => m_axi_awaddr, - m_axi_awlock => m_axi_awlock, - m_axi_awready => m_axi_awready, - m_axi_arvalid => m_axi_arvalid, - m_axi_araddr => m_axi_araddr, - m_axi_arlock => m_axi_arlock, - m_axi_arready => m_axi_arready, - m_axi_wvalid => m_axi_wvalid, - m_axi_wlast => m_axi_wlast, - m_axi_bready => m_axi_bready, - m_axi_bresp => m_axi_bresp, - m_axi_rready => m_axi_rready, - m_axi_bid => m_axi_bid, - m_axi_rid => m_axi_rid, - m_axi_wdata => m_axi_wdata, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_rvalid => m_axi_rvalid, - m_axi_rlast => m_axi_rlast, - m_axi_wstrb => m_axi_wstrb, - m_axi_wready => m_axi_wready, - s_axi_wready => s_axi_wready -); - ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE_1to2_switch/ipm/component.pickle b/fpga/ip/gTSE_1to2_switch/ipm/component.pickle deleted file mode 100644 index e262fd75b3669a20dbbfaffb03f816ce77d2e4ed..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 55706 zcmeHQYit|Yb(SA`+OjOa*1KL~6U+ajG}gM^Ew=pzkMq(!<#(4uHjq{yOJpa@bFMccIK{%BKlk^RvE37Q0b z|L8e)UUy!6+#!dG-2_-`IQN`;=DXiL_sqTb%zgdnTSM=4k^jl#d}cQx6t^~{iK0|U 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-//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf 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key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p 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============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 8.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -localparam SYNC_CLK = 0; -localparam SYNC_STAGE = 2; -localparam DATA_WIDTH = 16; -localparam MODE = "FWFT"; -localparam OUTPUT_REG = 0; -localparam PROG_FULL_ASSERT = 128; -localparam PROGRAMMABLE_FULL = "NONE"; -localparam PROG_FULL_NEGATE = 128; -localparam PROGRAMMABLE_EMPTY = "NONE"; -localparam PROG_EMPTY_ASSERT = 2; -localparam PROG_EMPTY_NEGATE = 3; -localparam OPTIONAL_FLAGS = 0; -localparam PIPELINE_REG = 1; -localparam DEPTH = 512; -localparam FAMILY = "TITANIUM"; -localparam ASYM_WIDTH_RATIO = 4; -localparam BYPASS_RESET_SYNC = 0; -localparam ENDIANESS = 0; -localparam RAM_STYLE = "block_ram"; -localparam OVERFLOW_PROTECT = 0; -localparam UNDERFLOW_PROTECT = 0; diff --git a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv deleted file mode 100644 index a0f357f..0000000 --- a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv +++ /dev/null @@ -1,60 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 8.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -gTSE_core_fifo_ctrl u_gTSE_core_fifo_ctrl -( - .full_o ( full_o ), - .empty_o ( empty_o ), - .wr_clk_i ( wr_clk_i ), - .rd_clk_i ( rd_clk_i ), - .wr_en_i ( wr_en_i ), - .rd_en_i ( rd_en_i ), - .wdata ( wdata ), - .rst_busy ( rst_busy ), - .rdata ( rdata ), - .a_rst_i ( a_rst_i ), - .wr_datacount_o ( wr_datacount_o ), - .rd_datacount_o ( rd_datacount_o ) -); diff --git a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd deleted file mode 100644 index 470be78..0000000 --- a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd +++ /dev/null @@ -1,75 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component gTSE_core_fifo_ctrl is -port ( - full_o : out std_logic; - empty_o : out std_logic; - wr_clk_i : in std_logic; - rd_clk_i : in std_logic; - wr_en_i : in std_logic; - rd_en_i : in std_logic; - wdata : in std_logic_vector(15 downto 0); - rst_busy : out std_logic; - rdata : out std_logic_vector(15 downto 0); - a_rst_i : in std_logic; - wr_datacount_o : out std_logic_vector(9 downto 0); - rd_datacount_o : out std_logic_vector(9 downto 0) -); -end component gTSE_core_fifo_ctrl; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_gTSE_core_fifo_ctrl : gTSE_core_fifo_ctrl -port map ( - full_o => full_o, - empty_o => empty_o, - wr_clk_i => wr_clk_i, - rd_clk_i => rd_clk_i, - wr_en_i => wr_en_i, - rd_en_i => rd_en_i, - wdata => wdata, - rst_busy => rst_busy, - rdata => rdata, - a_rst_i => a_rst_i, - wr_datacount_o => wr_datacount_o, - rd_datacount_o => rd_datacount_o -); - ------------------------- End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE_core_fifo_ctrl/ipm/component.pickle b/fpga/ip/gTSE_core_fifo_ctrl/ipm/component.pickle deleted file mode 100644 index 61a1d4c40760523bc67dc460dfed1eb9d1309b62..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 47078 zcmeG_3v3(7b@u5`$+9Io=S%K-xBi@ecb51O^~*U9Em1nw`hleEbAy28XDRNQYl{|bkThtD1})GAMS}j23y`Ep(@)X{Z3-mq zo0;9^&g=}ilqG+4@Yy7HX77w$kGze#k4LreyMTxJ&mo#8Kb+L zF3AmJ2o0H6@>)vQDh*>WC)cu7r9%3DIa!dUh1kNXl+~)Tq|~Ielvk=X{k&2(KWKGb zD#<0Sx+%R}m+P{W*Q!#wyeXwCm7d-n<)Uwy5cw|`u z;F48%_{Gv&cx=ar2V%mfp~m|8>BGE_-tufsHR^N3K4w*>vc@Ogjed~ho1 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zxK;UbWoT%|`CImP_Lqstg7?0*(Cj2HamdRM@{)kO>#|uZV;bkznG4C6vgF5y%vgIUtbxA(J{FnL}o4{QoQs=RYe;1Cg#!?QT*z zHJP@q!6~L1vrK4_ zvp~M#PHOyG-Z=G|I;qv`d8_})cg;@neQuK6H*mS(($`%N!y=P5;Bv!x11|y>!qu)$ zIm=25$)`~T*_iwvRoFO|z)q*?j#mpIs?aD%eIxGiSTKtXk8Hz24)FF2UH}!r8+TGpgluGjnvD z?|Ne%xF@r2lAWJqZLuv;()j}jMutPAuWC-Lu$Th?7xOg!s4xvNxeO@bN@PD}y>J96S( z3O)XFF5|7p90`$mYgzomUYDaHhRnHju8Aw9;>wx0QYx;zIIfh6D{o_xN6ICWWt|Vi zl~U2?6LFq2sKbY~!5tewAZoChm!`TF!p2I3hoV)YoV7zW&!FtYG8S&yhih z#j8h`a~ zl@Li@#!0A&DB6O9%ep4sA~jP5ksFb)e|w|nnqv2FZ{;2-EW;vV3v?$RW@_3*L}PE} zjXeb^6$yHIQ=(qp#`W^wC^3WG*XxZ|z_%GYt^2*cVal@5^#yEM7Q4QLEz3^4zJe{w zP9ndCEz3?LAHbGnCzAhwEz3?Nzlkl&PA0$2%2u4PG#Nzp3p-)cqv(A-DVO&iA2-ij zzURpjUy6;~54aTJxilh4L_L=-7Hmz-*pi&M!^)({T*0N1I0J0cB2!sn&MH6T37WWL z?1?L-c8s^gl~Oy#7si!RJI1##FCHnE+A+RAu9Vs_ek`t(+A-c2S4!;|AB-!dc8m_+ zF;dfnk|xXu(_Gnk3Uhs8PapQOoK&T99ipUE|%&%b!yE4C1GUccwgD=fpuT?2Qniqw9wx}|# zyo{CX7FD#37lll?s4`hzCS{tOJYNjnNPn0&n=*?|%IZsmc5dVYlbm9Q%V>98-W;Uk zA*;NCSFuv}kTqY)YeJeIvdZ7`DppD$vgQo03F(8#DzD*HtW-lex`CHBIO};~D-%(g zROst)oWr~VBrC?3Ji<#_`HazWoXZPa>5lQO_wWjk5gA|d8eY;$nw0m_eSyb(ooQa$ zN~(-+zMogv%|fGo??AZfj`EULYNnUK%x~?&gX02LLoQ!~VO&JeudzZE2XZ_U+N;8} z_W*CtN)}CMcCpv2xKRzPY2@mVw+cz83C%4C(P&iL9Hm|~2ORm+;HDh!`w0y$UhWC~l} zQ<=)Lzne9x8THA@fr;Wwae=$Udqv=IX=n=SR|egsrLp{Q;pAkYAlg{bIo8hqZZ+cc zvi6G$oITs-&EpBZ&R*|NHQxWVv7aExcX9rf0{=8jcZGc>WY0jM(9+ac-_+1J*s`x_ zsHUd5cCeIQ1+3pE4vLqo%Z ztoq= 1) begin - wire [1:0] bin_1; - assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; - if (WIDTH == 2) begin - assign bin_o = bin_1; - end - else begin - assign bin_o[WIDTH-1] = bin_1[1]; - `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); - end - end - else /* if (WIDTH == 1) */ - assign bin_o = gray_i; -endgenerate - -endmodule - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. -// / / \ -// / / .. / bin2gray.v -// / / .' / -// __/ /.' / Description: -// __ \ / Binary to Gray Encoding Convertor -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// 1.0 Initial rev -// -// ******************************* - -`resetall -`timescale 1ns/1ps - -module `IP_MODULE_NAME(efx_fifo_bin2gray) -#(parameter WIDTH=5) -(// outputs - output wire [WIDTH-1:0] gray_o, - // input - input [WIDTH-1:0] bin_i - ); - -//--------------------------------------------------------------------- -// Function : bit_xor -// Description: reduction xor -function bit_xor ( - input [31:0] nex_bit, - input [31:0] curr_bit, - input [WIDTH-1:0] xor_in); - begin : fn_bit_xor - bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; - end -endfunction - -// Convert Binary to Gray, bit by bit -generate -begin - genvar bit_idx; - for(bit_idx=0; bit_idx 1) begin - depth = depth - 1; - for (depth2width=0; depth>0; depth2width = depth2width + 1) - depth = depth>>1; - end - else - depth2width = 0; -end -endfunction - -function integer width2depth; -input [31:0] width; -begin : fnWidth2Depth - width2depth = width**2; -end -endfunction - -function integer rdwidthcompute; -input [31:0] asym_option; -input [31:0] wr_width; -begin : RdWidthCompute - rdwidthcompute = (asym_option==0)? wr_width/16 : - (asym_option==1)? wr_width/8 : - (asym_option==2)? wr_width/4 : - (asym_option==3)? wr_width/2 : - (asym_option==4)? wr_width/1 : - (asym_option==5)? wr_width*2 : - (asym_option==6)? wr_width*4 : - (asym_option==7)? wr_width*8 : - (asym_option==8)? wr_width*16 : wr_width/1; -end -endfunction - -function integer rddepthcompute; -input [31:0] wr_depth; -input [31:0] wr_width; -input [31:0] rd_width; -begin : RdDepthCompute - rddepthcompute = (wr_depth * wr_width) / rd_width; -end -endfunction - -endmodule - - -///////////////////////////////////////////////////////////////////////////// -// _____ -// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. -// / / \ -// / / .. / simple_dual_port_ram_fifo.v -// / / .' / -// __/ /.' / Description: -// __ \ / EFX FIFO -// /_/ /\ \_____/ / -// ____/ \_______/ -// -// ******************************* -// Revisions: -// -// ******************************* - -module `IP_MODULE_NAME(efx_fifo_ram) #( - parameter FAMILY = "TRION", - parameter WR_DEPTH = 512, - parameter RD_DEPTH = 512, - parameter WDATA_WIDTH = 8, - parameter RDATA_WIDTH = 8, - parameter WADDR_WIDTH = 9, - parameter RADDR_WIDTH = 9, - parameter OUTPUT_REG = 1, - parameter RAM_MUX_RATIO = 4, - parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian - parameter RAM_STYLE = "block_ram" -) ( - input wire wclk, - input wire rclk, - input wire we, - input wire re, - input wire [(WDATA_WIDTH-1):0] wdata, - input wire [(WADDR_WIDTH-1):0] waddr, - input wire [(RADDR_WIDTH-1):0] raddr, - output wire [(RDATA_WIDTH-1):0] rdata -); - -localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; -localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; -localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); -localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : - (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : - (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : - (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : - (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : - (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : - (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : - (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; - -(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; -reg [RDATA_WIDTH-1:0] r_rdata_1P; -reg [RDATA_WIDTH-1:0] r_rdata_2P; - -wire re_int; - -generate - if (FAMILY == "TRION") begin - if (RDATA_WDATA_RATIO == "ONE") begin - always @ (posedge wclk) begin - if (we) - ram[waddr] <= wdata; - end - - always @ (posedge rclk) begin - if (re_int) begin - r_rdata_1P <= ram[raddr]; - end - r_rdata_2P <= r_rdata_1P; - end - end - - else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin - if (ENDIANESS == 0) begin - integer i; - always @ (posedge wclk) begin - for (i=0; i= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin - reg wr_prog_full_int; - assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_prog_full_int <= 1'b0; - end - else begin - wr_prog_full_int <= wr_prog_full; - end - end - end - else begin - assign wr_prog_full = 1'b0; - end - - if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin - reg rd_prog_empty_int; - assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_prog_empty_int <= 1'b1; - end - else begin - rd_prog_empty_int <= rd_prog_empty; - end - end - end - else begin - assign rd_prog_empty = 1'b0; - end - - if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_ack <= 1'b0; - end - else begin - // NIC - //wr_ack <= wr_en_int & ~wr_overflow; - wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; - end - end - end - - if (OVERFLOW_PROTECT) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else if (we && wr_full) begin - wr_overflow <= 1'b1; - end - else begin - wr_overflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - wr_overflow <= 1'b0; - end - else begin - wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; - end - end - end - - if (UNDERFLOW_PROTECT) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else if (re && rd_empty) begin - rd_underflow <= 1'b1; - end - else begin - rd_underflow <= 1'b0; - end - end - end - else if (HANDSHAKE_FLAG) begin - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - rd_underflow <= 1'b0; - end - else begin - rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; - end - end - end - - localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; - - if (ASYM_WIDTH_RATIO < 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; - assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; - end - // NIC - else if (ASYM_WIDTH_RATIO == 4) begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); - assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - raddr_int; - assign rd_datacount_int = waddr_int - raddr_cntr; - end - else begin - assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); - // NIC - //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; - assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; - assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); - assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; - end -endgenerate - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr <= 'h0; - end - else if (wr_en_int) begin - waddr_cntr <= waddr_cntr + 1'b1; - end -end - -always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_r <= 'h0; - end - else begin - waddr_cntr_r <= waddr_cntr; - end -end - -always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr <= 'h0; - end - // NIC - //else if (rd_en_int) begin - else begin - //raddr_cntr <= raddr_cntr + 1'b1; - //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); - raddr_cntr <= ram_raddr; - end -end -// NIC -assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); - - -generate - if (SYNC_CLK) begin : sync_clk - if (MODE == "FWFT") begin - assign waddr_int = waddr_cntr_r; - assign raddr_int = raddr_cntr; - end - else begin - assign waddr_int = waddr_cntr; - assign raddr_int = raddr_cntr; - end - end - else begin : async_clk - reg [RADDR_WIDTH:0] raddr_cntr_gry_r; - reg [WADDR_WIDTH:0] waddr_cntr_gry_r; - - wire [RADDR_WIDTH:0] raddr_cntr_gry; - wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; - wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; - wire [WADDR_WIDTH:0] waddr_cntr_gry; - wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; - wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; - - if (PIPELINE_REG) begin - reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; - reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; - - assign waddr_int = waddr_cntr_sync_g2b_r; - assign raddr_int = raddr_cntr_sync_g2b_r; - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - raddr_cntr_sync_g2b_r <= 'h0; - end - else begin - raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; - end - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - waddr_cntr_sync_g2b_r <= 'h0; - end - else begin - waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; - end - end - end - else begin - assign waddr_int = waddr_cntr_sync_g2b; - assign raddr_int = raddr_cntr_sync_g2b; - end - - always @ (posedge rclk or posedge rd_rst) begin - if (rd_rst) begin - raddr_cntr_gry_r <= 'h0; - end - else begin - raddr_cntr_gry_r <= raddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); - - always @ (posedge wclk or posedge wr_rst) begin - if (wr_rst) begin - waddr_cntr_gry_r <= 'h0; - end - else begin - waddr_cntr_gry_r <= waddr_cntr_gry; - end - end - `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); - `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); - `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); - - end -endgenerate -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_resetsync) #( - parameter ASYNC_STAGE = 2, - parameter ACTIVE_LOW = 1 -) ( - input wire clk, - input wire reset, - output wire d_o -); - - -generate - if (ACTIVE_LOW == 1) begin: active_low - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (1), - .RST_VALUE (0) - ) efx_resetsync_active_low ( - .clk (clk), - .reset_n (reset), - .d_i (1'b1), - .d_o (d_o) - ); - end - else begin: active_high - `IP_MODULE_NAME(efx_asyncreg) #( - .WIDTH (1), - .ACTIVE_LOW (0), - .RST_VALUE (1) - ) efx_resetsync_active_high ( - .clk (clk), - .reset_n (reset), - .d_i (1'b0), - .d_o (d_o) - ); - end -endgenerate - -endmodule - - - -// synopsys translate_off -`timescale 1 ns / 1 ps -// synopsys translate_on - -module `IP_MODULE_NAME(efx_asyncreg) #( - parameter ASYNC_STAGE = 2, - parameter WIDTH = 4, - parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset - parameter RST_VALUE = 0, - parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance -) ( - input wire clk, - input wire reset_n, - input wire [WIDTH-1:0] d_i, - output wire [WIDTH-1:0] d_o -); - - - - - - - - - - -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect author = "author-a" , author_info = "author-a-details" -`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" -`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V -o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE -El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY -kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc -/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 -uYJaS5tuGEuFInBHa7oO8g== -`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 -fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa -rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq -PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL -DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w -K3OoKmk3zFeArSsql8B4/Q== -`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) -`pragma protect key_block -RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M -GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l -6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= -`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf -RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk -1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw -Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz -eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 -2HflB1HYKxojQCcZU7qUgQ== -`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx -Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB -rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr -XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD -e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod -B2Zpo2FQ//YDRSAaEa9ksQ== -`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" -`pragma protect key_method = "rsa" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) -`pragma protect key_block -TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze -vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 -ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 -06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP -fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN -ZoPzFCMjGk5ZmMyIlytNCw== -`pragma protect data_method = "aes256-cbc" -`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) -`pragma protect data_block -0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 -Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr -MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI -01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k -egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p 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============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 8.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -localparam SYNC_CLK = 0; -localparam SYNC_STAGE = 2; -localparam DATA_WIDTH = 13; -localparam MODE = "STANDARD"; -localparam OUTPUT_REG = 0; -localparam PROG_FULL_ASSERT = 128; -localparam PROGRAMMABLE_FULL = "NONE"; -localparam PROG_FULL_NEGATE = 128; -localparam PROGRAMMABLE_EMPTY = "NONE"; -localparam PROG_EMPTY_ASSERT = 2; -localparam PROG_EMPTY_NEGATE = 3; -localparam OPTIONAL_FLAGS = 0; -localparam PIPELINE_REG = 1; -localparam DEPTH = 4096; -localparam FAMILY = "TITANIUM"; -localparam ASYM_WIDTH_RATIO = 4; -localparam BYPASS_RESET_SYNC = 0; -localparam ENDIANESS = 0; -localparam RAM_STYLE = "block_ram"; -localparam OVERFLOW_PROTECT = 0; -localparam UNDERFLOW_PROTECT = 0; diff --git a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv deleted file mode 100644 index 1305620..0000000 --- a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv +++ /dev/null @@ -1,60 +0,0 @@ -// ============================================================================= -// Generated by efx_ipmgr -// Version: 2025.2.272 -// IP Version: 8.1 -// ============================================================================= - -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// - -gTSE_core_fifo_data u_gTSE_core_fifo_data -( - .full_o ( full_o ), - .empty_o ( empty_o ), - .wr_clk_i ( wr_clk_i ), - .rd_clk_i ( rd_clk_i ), - .wr_en_i ( wr_en_i ), - .rd_en_i ( rd_en_i ), - .wdata ( wdata ), - .rst_busy ( rst_busy ), - .rdata ( rdata ), - .a_rst_i ( a_rst_i ), - .wr_datacount_o ( wr_datacount_o ), - .rd_datacount_o ( rd_datacount_o ) -); diff --git a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd deleted file mode 100644 index 513297d..0000000 --- a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd +++ /dev/null @@ -1,75 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. --- --- This document contains proprietary information which is --- protected by copyright. All rights are reserved. This notice --- refers to original work by Efinix, Inc. which may be derivitive --- of other work distributed under license of the authors. In the --- case of derivative work, nothing in this notice overrides the --- original author's license agreement. Where applicable, the --- original license agreement is included in it's original --- unmodified form immediately below this header. --- --- WARRANTY DISCLAIMER. --- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND --- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH --- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, --- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF --- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR --- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED --- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. --- --- LIMITATION OF LIABILITY. --- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY --- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT --- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY --- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, --- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY --- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF --- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR --- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN --- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER --- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE --- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO --- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR --- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT --- APPLY TO LICENSEE. --- --------------------------------------------------------------------------------- -------------- Begin Cut here for COMPONENT Declaration ------ -component gTSE_core_fifo_data is -port ( - full_o : out std_logic; - empty_o : out std_logic; - wr_clk_i : in std_logic; - rd_clk_i : in std_logic; - wr_en_i : in std_logic; - rd_en_i : in std_logic; - wdata : in std_logic_vector(12 downto 0); - rst_busy : out std_logic; - rdata : out std_logic_vector(12 downto 0); - a_rst_i : in std_logic; - wr_datacount_o : out std_logic_vector(12 downto 0); - rd_datacount_o : out std_logic_vector(12 downto 0) -); -end component gTSE_core_fifo_data; - ----------------------- End COMPONENT Declaration ------------ -------------- Begin Cut here for INSTANTIATION Template ----- -u_gTSE_core_fifo_data : gTSE_core_fifo_data -port map ( - full_o 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